WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_uncore.c

 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
+#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
+static void
+assert_device_not_suspended(struct drm_i915_private *dev_priv)
+{
+	WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
-#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
+	     "Device suspended\n");
+}
 	/* WaRsForcewakeWaitTC0:snb */
 	__gen6_gt_wait_for_thread_c0(dev_priv);
 }
-static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
+static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
+{
 	__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
 	/* something from same cacheline, but !FORCEWAKE_MT */
 	__raw_posting_read(dev_priv, ECOBUS);
+}
-static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
+static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
 							int fw_engine)
 	/* something from same cacheline, but !FORCEWAKE */
 	__raw_posting_read(dev_priv, ECOBUS);
 	gen6_gt_check_fifodbg(dev_priv);
+}
-static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
+static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
 							int fw_engine)
+{
 	__raw_i915_write32(dev_priv, FORCEWAKE_MT,
 			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 	/* something from same cacheline, but !FORCEWAKE_MT */
+	__raw_posting_read(dev_priv, ECOBUS);
-	__raw_posting_read(dev_priv, ECOBUS);
+	if (IS_GEN7(dev_priv->dev))
 	gen6_gt_check_fifodbg(dev_priv);
+}
 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
+{
 	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
+			   _MASKED_BIT_DISABLE(0xffff));
+	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 			   _MASKED_BIT_DISABLE(0xffff));
 	/* something from same cacheline, but !FORCEWAKE_VLV */
 	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
+}
 			    FORCEWAKE_ACK_TIMEOUT_MS))
 			DRM_ERROR("Timed out: waiting for media to ack.\n");
+	}
+	/* WaRsForcewakeWaitTC0:vlv */
-	/* WaRsForcewakeWaitTC0:vlv */
+	if (!IS_CHERRYVIEW(dev_priv->dev))
-	__gen6_gt_wait_for_thread_c0(dev_priv);
 	__gen6_gt_wait_for_thread_c0(dev_priv);
+}
 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 	/* Check for Media Engine */
 	if (FORCEWAKE_MEDIA & fw_engine)
 	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
+	/* something from same cacheline, but !FORCEWAKE_VLV */
+	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
-	/* The below doubles as a POSTING_READ */
+	if (!IS_CHERRYVIEW(dev_priv->dev))
-	gen6_gt_check_fifodbg(dev_priv);
 	gen6_gt_check_fifodbg(dev_priv);
 }
 void vlv_force_wake_get(struct drm_i915_private *dev_priv,
-						int fw_engine)
+static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
+{
+	unsigned long irqflags;
-	unsigned long irqflags;
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	if (FORCEWAKE_RENDER & fw_engine) {
-		if (dev_priv->uncore.fw_rendercount++ == 0)
-			dev_priv->uncore.funcs.force_wake_get(dev_priv,
+	if (fw_engine & FORCEWAKE_RENDER &&
-							FORCEWAKE_RENDER);
+	    dev_priv->uncore.fw_rendercount++ != 0)
-	}
-	if (FORCEWAKE_MEDIA & fw_engine) {
+		fw_engine &= ~FORCEWAKE_RENDER;
-		if (dev_priv->uncore.fw_mediacount++ == 0)
+	if (fw_engine & FORCEWAKE_MEDIA &&
+	    dev_priv->uncore.fw_mediacount++ != 0)
+		fw_engine &= ~FORCEWAKE_MEDIA;
 			dev_priv->uncore.funcs.force_wake_get(dev_priv,
-							FORCEWAKE_MEDIA);
+	if (fw_engine)
-	}
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
-void vlv_force_wake_put(struct drm_i915_private *dev_priv,
-						int fw_engine)
+static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 {
-	unsigned long irqflags;
+	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	if (FORCEWAKE_RENDER & fw_engine) {
-		WARN_ON(dev_priv->uncore.fw_rendercount == 0);
+	if (fw_engine & FORCEWAKE_RENDER) {
-		if (--dev_priv->uncore.fw_rendercount == 0)
-			dev_priv->uncore.funcs.force_wake_put(dev_priv,
+		WARN_ON(!dev_priv->uncore.fw_rendercount);
-							FORCEWAKE_RENDER);
+		if (--dev_priv->uncore.fw_rendercount != 0)
+			fw_engine &= ~FORCEWAKE_RENDER;
+	}
 	if (fw_engine & FORCEWAKE_MEDIA) {
 		WARN_ON(!dev_priv->uncore.fw_mediacount);
-	if (FORCEWAKE_MEDIA & fw_engine) {
+		if (--dev_priv->uncore.fw_mediacount != 0)
-		WARN_ON(dev_priv->uncore.fw_mediacount == 0);
+			fw_engine &= ~FORCEWAKE_MEDIA;
-		if (--dev_priv->uncore.fw_mediacount == 0)
+	}
-			dev_priv->uncore.funcs.force_wake_put(dev_priv,
 							FORCEWAKE_MEDIA);
+	if (fw_engine)
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+static void gen6_force_wake_timer(unsigned long arg)
+{
+	struct drm_i915_private *dev_priv = (void *)arg;
+	unsigned long irqflags;
-static void gen6_force_wake_work(struct work_struct *work)
+	assert_device_not_suspended(dev_priv);
-	struct drm_i915_private *dev_priv =
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	WARN_ON(!dev_priv->uncore.forcewake_count);
+	if (--dev_priv->uncore.forcewake_count == 0)
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	intel_runtime_pm_put(dev_priv);
+}
-		container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
+void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 	unsigned long irqflags;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	unsigned long irqflags;
-	if (--dev_priv->uncore.forcewake_count == 0)
+	if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
+		gen6_force_wake_timer((unsigned long)dev_priv);
+	/* Hold uncore.lock across reset to prevent any register access
+	 * with forcewake not set correctly
+	 */
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	if (IS_VALLEYVIEW(dev))
+		vlv_force_wake_reset(dev_priv);
+	else if (IS_GEN6(dev) || IS_GEN7(dev))
+		__gen6_gt_force_wake_reset(dev_priv);
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
+		__gen7_gt_force_wake_mt_reset(dev_priv);
+	if (restore) { /* If reset with a user forcewake, try to restore */
+		unsigned fw = 0;
+		if (IS_VALLEYVIEW(dev)) {
+			if (dev_priv->uncore.fw_rendercount)
+				fw |= FORCEWAKE_RENDER;
+			if (dev_priv->uncore.fw_mediacount)
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+				fw |= FORCEWAKE_MEDIA;
+		} else {
+			if (dev_priv->uncore.forcewake_count)
 				fw = FORCEWAKE_ALL;
+	}
 static void intel_uncore_forcewake_reset(struct drm_device *dev)
 		if (fw)
-	struct drm_i915_private *dev_priv = dev->dev_private;
+			dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
-	if (IS_VALLEYVIEW(dev)) {
+		if (IS_GEN6(dev) || IS_GEN7(dev))
-		vlv_force_wake_reset(dev_priv);
+			dev_priv->uncore.fifo_count =
-	} else if (INTEL_INFO(dev)->gen >= 6) {
+				__raw_i915_read32(dev_priv, GTFIFOCTL) &
-		__gen6_gt_force_wake_reset(dev_priv);
+				GT_FIFO_FREE_ENTRIES_MASK;
 		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 			__gen6_gt_force_wake_mt_reset(dev_priv);
 	/* clear out old GT FIFO errors */
 	if (IS_GEN6(dev) || IS_GEN7(dev))
 		__raw_i915_write32(dev_priv, GTFIFODBG,
 				   __raw_i915_read32(dev_priv, GTFIFODBG));
-	intel_uncore_forcewake_reset(dev);
+	intel_uncore_forcewake_reset(dev, restore_forcewake);
+}
-void intel_uncore_sanitize(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg_val;
+void intel_uncore_sanitize(struct drm_device *dev)
+{
-	/* BIOS often leaves RC6 enabled, but disable it for hw init */
-	intel_disable_gt_powersave(dev);
-	/* Turn off power gate, require especially for the BIOS less system */
-	if (IS_VALLEYVIEW(dev)) {
-		mutex_lock(&dev_priv->rps.hw_lock);
-		reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
-		if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
-			vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
-		mutex_unlock(&dev_priv->rps.hw_lock);
 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
 	intel_disable_gt_powersave(dev);
+}
  * see gen6_gt_force_wake_get()
  */
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
+{
 	unsigned long irqflags;
+	bool delayed = false;
 	if (!dev_priv->uncore.funcs.force_wake_put)
 		return;
 	/* Redirect to VLV specific routine */
+	if (IS_VALLEYVIEW(dev_priv->dev)) {
+		vlv_force_wake_put(dev_priv, fw_engine);
-	if (IS_VALLEYVIEW(dev_priv->dev))
+		goto out;
+	}
 		return vlv_force_wake_put(dev_priv, fw_engine);
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	WARN_ON(!dev_priv->uncore.forcewake_count);
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 	if (--dev_priv->uncore.forcewake_count == 0) {
 		dev_priv->uncore.forcewake_count++;
-		mod_delayed_work(dev_priv->wq,
+		delayed = true;
+//       mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
+//                GetTimerTicks() + 1);
 				 &dev_priv->uncore.force_wake_work,
-);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+out:
+	if (!delayed)
+	intel_runtime_pm_put(dev_priv);
+}
+void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
+{
 	if (!dev_priv->uncore.funcs.force_wake_get)
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+		return;
+	WARN_ON(dev_priv->uncore.forcewake_count > 0);
+}
+/* We give fast paths for the really cool registers */
+#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
+#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
+#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x2000, 0x4000) || \
+	 REG_RANGE((reg), 0x5000, 0x8000) || \
+	 REG_RANGE((reg), 0xB000, 0x12000) || \
+	 REG_RANGE((reg), 0x2E000, 0x30000))
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x12000, 0x14000) || \
+	 REG_RANGE((reg), 0x22000, 0x24000) || \
+	 REG_RANGE((reg), 0x30000, 0x40000))
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x2000, 0x4000) || \
+	 REG_RANGE((reg), 0x5000, 0x8000) || \
+	 REG_RANGE((reg), 0x8300, 0x8500) || \
+	 REG_RANGE((reg), 0xB000, 0xC000) || \
+	 REG_RANGE((reg), 0xE000, 0xE800))
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x8800, 0x8900) || \
+	 REG_RANGE((reg), 0xD000, 0xD800) || \
+	 REG_RANGE((reg), 0x12000, 0x14000) || \
+	 REG_RANGE((reg), 0x1A000, 0x1C000) || \
+	 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+	 REG_RANGE((reg), 0x30000, 0x40000))
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x4000, 0x5000) || \
+	 REG_RANGE((reg), 0x8000, 0x8300) || \
-	intel_runtime_pm_put(dev_priv);
+	 REG_RANGE((reg), 0x8500, 0x8600) || \
 	 REG_RANGE((reg), 0x9000, 0xB000) || \
 	 REG_RANGE((reg), 0xC000, 0xC800) || \
-/* We give fast paths for the really cool registers */
+	 REG_RANGE((reg), 0xF000, 0x10000) || \
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+	 REG_RANGE((reg), 0x14000, 0x14400) || \
-	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
+	 REG_RANGE((reg), 0x22000, 0x24000))
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)
 {
+	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
-	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
+	 * the chip from rc6 before touching it for real. MI_MODE is masked,
+	 * hence harmless to write 0 into. */
+	__raw_i915_write32(dev_priv, MI_MODE, 0);
+}
+static void
+hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
-	 * the chip from rc6 before touching it for real. MI_MODE is masked,
+			bool before)
-	 * hence harmless to write 0 into. */
+{
-	__raw_i915_write32(dev_priv, MI_MODE, 0);
+	const char *op = read ? "reading" : "writing to";
 	const char *when = before ? "before" : "after";
-static void
+	if (!i915.mmio_debug)
-hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
+		return;
-{
 	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
+		WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
+		     when, op, reg);
+		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 		DRM_ERROR("Unknown unclaimed register before writing to %x\n",
-			  reg);
+}
 		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 static void
 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
-static void
-hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
-{
-	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
-		DRM_ERROR("Unclaimed write to %x\n", reg);
-		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+{
 	if (i915.mmio_debug)
 		return;
-static void
+	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
-assert_device_not_suspended(struct drm_i915_private *dev_priv)
+		DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 	WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
 #define __gen6_read(x) \
 static u##x \
 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	REG_READ_HEADER(x); \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
+	if (dev_priv->uncore.forcewake_count == 0 && \
-		if (dev_priv->uncore.forcewake_count == 0) \
+	    NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 			dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 							FORCEWAKE_ALL); \
-		val = __raw_i915_read##x(dev_priv, reg); \
-		if (dev_priv->uncore.forcewake_count == 0) \
+		val = __raw_i915_read##x(dev_priv, reg); \
 			dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 							FORCEWAKE_ALL); \
 	} else { \
 		val = __raw_i915_read##x(dev_priv, reg); \
+	} \
-	} \
+	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 	REG_READ_FOOTER; \
+}
 #define __vlv_read(x) \
 static u##x \
-vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	unsigned fwengine = 0; \
+vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	unsigned *fwcount; \
+	unsigned fwengine = 0; \
+	REG_READ_HEADER(x); \
-	REG_READ_HEADER(x); \
+	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) {   \
-	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) {   \
-		fwengine = FORCEWAKE_RENDER;            \
-		fwcount = &dev_priv->uncore.fw_rendercount;    \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+		fwengine = FORCEWAKE_RENDER;            \
-	}                                               \
+	} else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
-	else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) {       \
-		fwengine = FORCEWAKE_MEDIA;             \
+		if (dev_priv->uncore.fw_mediacount == 0) \
-		fwcount = &dev_priv->uncore.fw_mediacount;     \
+		fwengine = FORCEWAKE_MEDIA;             \
-	}  \
-	if (fwengine != 0) {		\
+	}                                               \
-		if ((*fwcount)++ == 0) \
-			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
-								fwengine); \
-		val = __raw_i915_read##x(dev_priv, reg); \
-		if (--(*fwcount) == 0) \
-			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
-							fwengine); \
+	if (fwengine) \
-	} else { \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+		val = __raw_i915_read##x(dev_priv, reg); \
-		val = __raw_i915_read##x(dev_priv, reg); \
+	if (fwengine) \
-	} \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	REG_READ_FOOTER; \
+}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+	unsigned fwengine = 0; \
+	REG_READ_HEADER(x); \
+	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine = FORCEWAKE_RENDER; \
+	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+		fwengine = FORCEWAKE_MEDIA;             \
+	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine |= FORCEWAKE_RENDER; \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+			fwengine |= FORCEWAKE_MEDIA; \
+	}  \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+		val = __raw_i915_read##x(dev_priv, reg); \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	REG_READ_FOOTER; \
+}
-	REG_READ_FOOTER; \
+__chv_read(8)
 __chv_read(16)
 __chv_read(32)
 __chv_read(64)
 __vlv_read(8)
 __gen4_read(8)
 __gen4_read(16)
 __gen4_read(32)
 __gen4_read(64)
 #undef __chv_read
 #undef __vlv_read
 #undef __gen6_read
 #undef __gen5_read
 #undef __gen4_read
 #undef REG_READ_FOOTER
 #undef REG_READ_HEADER
 #define REG_WRITE_HEADER \
+	unsigned long irqflags; \
-	unsigned long irqflags; \
+	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
-	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
+	assert_device_not_suspended(dev_priv); \
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 	u32 __fifo_ret = 0; \
 	REG_WRITE_HEADER; \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
-	assert_device_not_suspended(dev_priv); \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
 	REG_WRITE_FOOTER; \
 	u32 __fifo_ret = 0; \
 	REG_WRITE_HEADER; \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
-	assert_device_not_suspended(dev_priv); \
-	hsw_unclaimed_reg_clear(dev_priv, reg); \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
-	hsw_unclaimed_reg_check(dev_priv, reg); \
+	hsw_unclaimed_reg_detect(dev_priv); \
 	REG_WRITE_FOOTER; \
+}
 static const u32 gen8_shadowed_regs[] = {
+}
 #define __gen8_write(x) \
 static void \
-gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
-	bool __needs_put = reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg); \
+gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	REG_WRITE_HEADER; \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-	REG_WRITE_HEADER; \
+	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
-	if (__needs_put) { \
+		if (dev_priv->uncore.forcewake_count == 0) \
 		dev_priv->uncore.funcs.force_wake_get(dev_priv, \
-							FORCEWAKE_ALL); \
-	} \
+							FORCEWAKE_ALL); \
 	__raw_i915_write##x(dev_priv, reg, val); \
-	if (__needs_put) { \
+		if (dev_priv->uncore.forcewake_count == 0) \
 		dev_priv->uncore.funcs.force_wake_put(dev_priv, \
+							FORCEWAKE_ALL); \
+	} else { \
-							FORCEWAKE_ALL); \
+		__raw_i915_write##x(dev_priv, reg, val); \
+	} \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
-	} \
+	hsw_unclaimed_reg_detect(dev_priv); \
 	REG_WRITE_FOOTER; \
+}
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	unsigned fwengine = 0; \
+	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
+	REG_WRITE_HEADER; \
+	if (!shadowed) { \
+		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine = FORCEWAKE_RENDER; \
+		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine = FORCEWAKE_MEDIA; \
+		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine |= FORCEWAKE_RENDER; \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine |= FORCEWAKE_MEDIA; \
+		} \
+	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	REG_WRITE_FOOTER; \
+}
+__chv_write(8)
+__chv_write(16)
 __chv_write(32)
 __chv_write(64)
 __gen8_write(8)
 __gen8_write(16)
 __gen8_write(32)
 __gen4_write(8)
 __gen4_write(16)
 __gen4_write(32)
 __gen4_write(64)
 #undef __chv_write
 #undef __gen8_write
 #undef __hsw_write
 #undef __gen6_write
 #undef __gen5_write
 void intel_uncore_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	setup_timer(&dev_priv->uncore.force_wake_timer,
+		    gen6_force_wake_timer, (unsigned long)dev_priv);
 	INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
-			  gen6_force_wake_work);
+	intel_uncore_early_sanitize(dev, false);
 	if (IS_VALLEYVIEW(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
 		dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
 	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
-		dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
+		dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
-		dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
+		dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
 		 * ECOBUS read will return zero. Which will be
 		 * (correctly) interpreted by the test below as MT
 		 * forcewake being disabled.
 		 */
 		mutex_lock(&dev->struct_mutex);
-		__gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
+		__gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
 		ecobus = __raw_i915_read32(dev_priv, ECOBUS);
-		__gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
+		__gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
 		mutex_unlock(&dev->struct_mutex);
 		if (ecobus & FORCEWAKE_MT_ENABLE) {
 			dev_priv->uncore.funcs.force_wake_get =
-				__gen6_gt_force_wake_mt_get;
+				__gen7_gt_force_wake_mt_get;
 			dev_priv->uncore.funcs.force_wake_put =
-				__gen6_gt_force_wake_mt_put;
+				__gen7_gt_force_wake_mt_put;
 		} else {
 			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
 			DRM_INFO("when using vblank-synced partial screen updates.\n");
 			dev_priv->uncore.funcs.force_wake_get =
 			__gen6_gt_force_wake_put;
+	}
 	switch (INTEL_INFO(dev)->gen) {
+	default:
+		if (IS_CHERRYVIEW(dev)) {
+			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
+			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
+			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
+			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
+			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
+			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
+			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
+			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
-	default:
+		} else {
 		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
 		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
 		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
 		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
 		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
 		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
 		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
+		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
 		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
 		break;
 	case 7:
 	case 6:
 		if (IS_HASWELL(dev)) {
+	}
+}
 void intel_uncore_fini(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-//   flush_delayed_work(&dev_priv->uncore.force_wake_work);
+{
 	/* Paranoia: make sure we have disabled everything before we exit. */
+	intel_uncore_sanitize(dev);
-	intel_uncore_sanitize(dev);
+	intel_uncore_forcewake_reset(dev, false);
+}
 #define GEN_RANGE(l, h) GENMASK(h, l)
 static const struct register_whitelist {
 	uint64_t offset;
+	uint32_t size;
-	uint32_t size;
+	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
-	uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
+	uint32_t gen_bitmask;
 } whitelist[] = {
-	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
+	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
 };
 int i915_reg_read_ioctl(struct drm_device *dev,
 			void *data, struct drm_file *file)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_reg_read *reg = data;
 	struct register_whitelist const *entry = whitelist;
-	int i;
+	int i, ret = 0;
 	case 1:
 		reg->val = I915_READ8(reg->offset);
 		break;
 	default:
 		WARN_ON(1);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out;
+	}
+out:
-	return 0;
+	return ret;
+}
 int i915_get_reset_stats_ioctl(struct drm_device *dev,
 			       void *data, struct drm_file *file)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_reset_stats *args = data;
-	struct drm_i915_reset_stats *args = data;
+	struct i915_ctx_hang_stats *hs;
-	struct i915_ctx_hang_stats *hs;
+	struct intel_context *ctx;
 	int ret;
-	if (args->flags || args->pad)
-		return -EINVAL;
-	if (args->ctx_id == DEFAULT_CONTEXT_ID)
+	if (args->flags || args->pad)
-		return -EPERM;
+		return -EINVAL;
 	ret = mutex_lock_interruptible(&dev->struct_mutex);
 	if (ret)
 		return ret;
+	ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
-	hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id);
+	if (IS_ERR(ctx)) {
-	if (IS_ERR(hs)) {
+		mutex_unlock(&dev->struct_mutex);
-		mutex_unlock(&dev->struct_mutex);
+		return PTR_ERR(ctx);
 static int i965_do_reset(struct drm_device *dev)
+{
+	int ret;
+	/* FIXME: i965g/gm need a display save/restore for gpu reset. */
-	int ret;
+	return -ENODEV;
 	/*
 	 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 	 * well as the reset bit (GR/bit 0).  Setting the GR bit
 			      GRDOM_RENDER | GRDOM_RESET_ENABLE);
 	ret =  wait_for(i965_reset_complete(dev), 500);
 	if (ret)
 		return ret;
 	/* We can't reset render&media without also resetting display ... */
 	pci_write_config_byte(dev->pdev, I965_GDRST,
 			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 	pci_write_config_byte(dev->pdev, I965_GDRST, 0);
 	return 0;
+}
+static int g4x_do_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret;
+	pci_write_config_byte(dev->pdev, I965_GDRST,
+			      GRDOM_RENDER | GRDOM_RESET_ENABLE);
+	ret =  wait_for(i965_reset_complete(dev), 500);
+	if (ret)
+		return ret;
+	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
+	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+	POSTING_READ(VDECCLK_GATE_D);
+	pci_write_config_byte(dev->pdev, I965_GDRST,
+			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
+	ret =  wait_for(i965_reset_complete(dev), 500);
+	if (ret)
+		return ret;
+	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
+	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+	POSTING_READ(VDECCLK_GATE_D);
+	pci_write_config_byte(dev->pdev, I965_GDRST, 0);
+	return 0;
+}
 static int ironlake_do_reset(struct drm_device *dev)
-{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 gdrst;
-	int ret;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
+	int ret;
-	gdrst &= ~GRDOM_MASK;
+	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+		   ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
-		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
+	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
-	ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
-	if (ret)
-		return ret;
 			ILK_GRDOM_RESET_ENABLE) == 0, 500);
-	/* We can't reset render&media without also resetting display ... */
+	if (ret)
-	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
+		return ret;
+	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+		   ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+			ILK_GRDOM_RESET_ENABLE) == 0, 500);
+	if (ret)
+		return ret;
 	gdrst &= ~GRDOM_MASK;
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
 		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
-	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
+	return 0;
+}
-static int gen6_do_reset(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int	ret;
-	unsigned long irqflags;
-	/* Hold uncore.lock across reset to prevent any register access
+static int gen6_do_reset(struct drm_device *dev)
 	 * with forcewake not set correctly
 	__raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
 	/* Spin waiting for the device to ack the reset request */
 	ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
-	intel_uncore_forcewake_reset(dev);
-	/* If reset with a user forcewake, try to restore, otherwise turn it off */
-	if (dev_priv->uncore.forcewake_count)
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
-	else
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
-	/* Restore fifo count */
 	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 	intel_uncore_forcewake_reset(dev, true);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 	return ret;
 }
 int intel_gpu_reset(struct drm_device *dev)
 {
+	if (INTEL_INFO(dev)->gen >= 6)
-	switch (INTEL_INFO(dev)->gen) {
+		return gen6_do_reset(dev);
+	else if (IS_GEN5(dev))
-	case 8:
+		return ironlake_do_reset(dev);
+	else if (IS_G4X(dev))
-	case 7:
+			return g4x_do_reset(dev);
-	case 6: return gen6_do_reset(dev);
-	case 5: return ironlake_do_reset(dev);
+	else if (IS_GEN4(dev))
-	case 4: return i965_do_reset(dev);
+		return i965_do_reset(dev);
-	default: return -ENODEV;
+		else
 		return -ENODEV;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_uncore.c – Rev 4560 → 5060