WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_sprite.c

  */
 #include
 #include
 #include
 #include
+#include
+#include
 #include "intel_drv.h"
 #include
 #include "i915_drv.h"
 	default:
 		return false;
+	}
+}
+static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
-static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
+			      int usecs)
+{
 	/* paranoia */
-	if (!mode->crtc_htotal)
+	if (!adjusted_mode->crtc_htotal)
 		return 1;
 	return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
-	return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
+* adjusted_mode->crtc_htotal);
+}
+ *
  * After a successful call to this function, interrupts will be disabled
  * until a subsequent call to intel_pipe_update_end(). That is done to
  * avoid random delays. The value written to @start_vbl_count should be
  * supplied to intel_pipe_update_end() for error checking.
- *
- * Return: true if the call was successful
  */
-bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
+void intel_pipe_update_start(struct intel_crtc *crtc)
+{
+ENTER();
 	struct drm_device *dev = crtc->base.dev;
-	const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 	enum pipe pipe = crtc->pipe;
 	long timeout = msecs_to_jiffies_timeout(1);
 	int scanline, min, max, vblank_start;
+#if 0
-	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
+//   wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
-	DEFINE_WAIT(wait);
+//   DEFINE_WAIT(wait);
-	vblank_start = mode->crtc_vblank_start;
+	vblank_start = adjusted_mode->crtc_vblank_start;
-	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
 	/* FIXME needs to be calibrated sensibly */
-	min = vblank_start - usecs_to_scanlines(mode, 100);
+	min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
 	max = vblank_start - 1;
 	if (min <= 0 || max <= 0)
-		return false;
+		return;
 //   if (WARN_ON(drm_vblank_get(dev, pipe)))
 //       return false;
-//   local_irq_disable();
+	crtc->debug.min_vbl = min;
 	crtc->debug.max_vbl = max;
         timeout = 0;
 //       local_irq_disable();
+	}
+	finish_wait(wq, &wait);
+#endif
-	finish_wait(wq, &wait);
-//   drm_vblank_put(dev, pipe);
+	crtc->debug.scanline_start = scanline;
-	*start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
+	crtc->debug.start_vbl_time = ktime_get();
+	crtc->debug.start_vbl_count =
-//   trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
+		dev->driver->get_vblank_counter(dev, pipe);
-	return true;
+	trace_i915_pipe_update_vblank_evaded(crtc);
+}
+ *
  * Mark the end of an update started with intel_pipe_update_start(). This
  * re-enables interrupts and verifies the update was actually completed
  * before a vblank using the value of @start_vbl_count.
  */
-void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
+void intel_pipe_update_end(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	enum pipe pipe = crtc->pipe;
+	int scanline_end = intel_get_crtc_scanline(crtc);
 	u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
+	ktime_t end_vbl_time = ktime_get();
-//   trace_i915_pipe_update_end(crtc, end_vbl_count);
+	trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
+//   local_irq_enable();
-//   local_irq_enable();
+	if (crtc->debug.start_vbl_count &&
+	    crtc->debug.start_vbl_count != end_vbl_count) {
+		DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
+			  pipe_name(pipe), crtc->debug.start_vbl_count,
+			  end_vbl_count,
-	if (start_vbl_count != end_vbl_count)
+			  ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
-		DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
-			  pipe_name(pipe), start_vbl_count, end_vbl_count);
-}
-static void intel_update_primary_plane(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
-	int reg = DSPCNTR(crtc->plane);
-	if (crtc->primary_enabled)
-		I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+			  crtc->debug.min_vbl, crtc->debug.max_vbl,
-	else
+			  crtc->debug.scanline_start, scanline_end);
 		I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
+}
 static void
 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		 struct drm_framebuffer *fb,
-		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+		 int crtc_x, int crtc_y,
 		 unsigned int crtc_w, unsigned int crtc_h,
 		 uint32_t x, uint32_t y,
 		 uint32_t src_w, uint32_t src_h)
+{
 	struct drm_device *dev = drm_plane->dev;
-	struct drm_device *dev = drm_plane->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
-	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+	const int pipe = intel_plane->pipe;
+	const int plane = intel_plane->plane + 1;
+	u32 plane_ctl, stride_div, stride;
+	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	const struct drm_intel_sprite_colorkey *key =
+		&to_intel_plane_state(drm_plane->state)->ckey;
+	unsigned long surf_addr;
+	u32 tile_height, plane_offset, plane_size;
+	unsigned int rotation;
+	int x_offset, y_offset;
+	struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
+	int scaler_id;
-	const int pipe = intel_plane->pipe;
-	const int plane = intel_plane->plane + 1;
-	u32 plane_ctl, stride;
-	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
-	/* Mask out pixel format bits in case we change it */
-	plane_ctl &= ~PLANE_CTL_FORMAT_MASK;
-	plane_ctl &= ~PLANE_CTL_ORDER_RGBX;
-	plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK;
-	plane_ctl &= ~PLANE_CTL_TILED_MASK;
+	plane_ctl = PLANE_CTL_ENABLE |
-	plane_ctl &= ~PLANE_CTL_ALPHA_MASK;
-	plane_ctl &= ~PLANE_CTL_ROTATE_MASK;
-	/* Trickle feed has to be enabled */
-	plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE;
-	switch (fb->pixel_format) {
-	case DRM_FORMAT_RGB565:
-		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
-		break;
-	case DRM_FORMAT_XBGR8888:
-		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
-		break;
-	case DRM_FORMAT_XRGB8888:
-		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
-		break;
-	/*
-	 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-	 * to be already pre-multiplied. We need to add a knob (or a different
-	 * DRM_FORMAT) for user-space to configure that.
-	 */
-	case DRM_FORMAT_ABGR8888:
-		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
-			     PLANE_CTL_ORDER_RGBX |
-			     PLANE_CTL_ALPHA_SW_PREMULTIPLY;
-		break;
-	case DRM_FORMAT_ARGB8888:
-		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
-			     PLANE_CTL_ALPHA_SW_PREMULTIPLY;
-		break;
-	case DRM_FORMAT_YUYV:
-		plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
-		break;
-	case DRM_FORMAT_YVYU:
-		plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
-		break;
-	case DRM_FORMAT_UYVY:
-		plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
-		break;
-	case DRM_FORMAT_VYUY:
-		plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
-		break;
-	default:
-		BUG();
-	}
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
-		stride = fb->pitches[0] >> 6;
-		break;
-	case I915_TILING_X:
-		plane_ctl |= PLANE_CTL_TILED_X;
-		stride = fb->pitches[0] >> 9;
-		break;
-	default:
+		PLANE_CTL_PIPE_GAMMA_ENABLE |
-		BUG();
+		PLANE_CTL_PIPE_CSC_ENABLE;
-	if (intel_plane->rotation == BIT(DRM_ROTATE_180))
+	plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
-		plane_ctl |= PLANE_CTL_ROTATE_180;
+	plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
+	rotation = drm_plane->state->rotation;
+	plane_ctl |= skl_plane_ctl_rotation(rotation);
+	intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 				       pixel_size, true,
-	plane_ctl |= PLANE_CTL_ENABLE;
+				       src_w != crtc_w || src_h != crtc_h);
 	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
-	intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
+					       fb->pixel_format);
-				       pixel_size, true,
-				       src_w != crtc_w || src_h != crtc_h);
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-	crtc_w--;
-	crtc_h--;
-	I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
-	I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
-	I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
-	I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
-	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
-	I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));
-	POSTING_READ(PLANE_SURF(pipe, plane));
-}
-static void
-skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
-{
-	struct drm_device *dev = drm_plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
-	const int pipe = intel_plane->pipe;
-	const int plane = intel_plane->plane + 1;
-	I915_WRITE(PLANE_CTL(pipe, plane),
-		   I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
-	/* Activate double buffered register update */
-	I915_WRITE(PLANE_CTL(pipe, plane), 0);
-	POSTING_READ(PLANE_CTL(pipe, plane));
-	intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false);
-}
-static int
-skl_update_colorkey(struct drm_plane *drm_plane,
-		    struct drm_intel_sprite_colorkey *key)
+	scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
-	struct drm_device *dev = drm_plane->dev;
+	/* Sizes are 0 based */
+	src_w--;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
-	const int pipe = intel_plane->pipe;
+	src_h--;
-	const int plane = intel_plane->plane;
+	crtc_w--;
-	u32 plane_ctl;
+	crtc_h--;
-	I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
-	I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
+	if (key->flags) {
+		I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
+		I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
+		I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
+	}
+	if (key->flags & I915_SET_COLORKEY_DESTINATION)
+		plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
+	else if (key->flags & I915_SET_COLORKEY_SOURCE)
-	I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
+		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
+	surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
+	if (intel_rotation_90_or_270(rotation)) {
+		/* stride: Surface height in tiles */
+		tile_height = intel_tile_height(dev, fb->pixel_format,
+						fb->modifier[0], 0);
+		stride = DIV_ROUND_UP(fb->height, tile_height);
+		plane_size = (src_w << 16) | src_h;
+		x_offset = stride * tile_height - y - (src_h + 1);
+		y_offset = x;
+	} else {
+		stride = fb->pitches[0] / stride_div;
+		plane_size = (src_h << 16) | src_w;
+		x_offset = x;
+		y_offset = y;
+	}
+	plane_offset = y_offset << 16 | x_offset;
+	I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
+	I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
+	I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+	/* program plane scaler */
+	if (scaler_id >= 0) {
+		uint32_t ps_ctrl = 0;
+		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
+			PS_PLANE_SEL(plane));
+		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
+			crtc_state->scaler_state.scalers[scaler_id].mode;
+		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
+		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
-	plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
+		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
-	plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK;
+			((crtc_w + 1) << 16)|(crtc_h + 1));
-	if (key->flags & I915_SET_COLORKEY_DESTINATION)
 		plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
-	else if (key->flags & I915_SET_COLORKEY_SOURCE)
+		I915_WRITE(PLANE_POS(pipe, plane), 0);
-		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
+	} else {
-	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
+		I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
+	}
-	POSTING_READ(PLANE_CTL(pipe, plane));
-	return 0;
+	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
-}
+	I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
-static void
+	POSTING_READ(PLANE_SURF(pipe, plane));
-skl_get_colorkey(struct drm_plane *drm_plane,
+}
-		 struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = drm_plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(drm_plane);
-	const int pipe = intel_plane->pipe;
-	const int plane = intel_plane->plane;
-	u32 plane_ctl;
 	key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane));
-	key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane));
+static void
-	key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane));
+skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
+{
+}
 static void
 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 		 struct drm_framebuffer *fb,
-		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+		 int crtc_x, int crtc_y,
 		 unsigned int crtc_w, unsigned int crtc_h,
 		 uint32_t x, uint32_t y,
 		 uint32_t src_w, uint32_t src_h)
+{
 	struct drm_device *dev = dplane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int pipe = intel_plane->pipe;
 	int plane = intel_plane->plane;
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	u32 start_vbl_count;
+	const struct drm_intel_sprite_colorkey *key =
-	bool atomic_update;
-	sprctl = I915_READ(SPCNTR(pipe, plane));
-	/* Mask out pixel format bits in case we change it */
-	sprctl &= ~SP_PIXFORMAT_MASK;
+		&to_intel_plane_state(dplane->state)->ckey;
-	sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
 	sprctl &= ~SP_TILED;
-	sprctl &= ~SP_ROTATE_180;
+	sprctl = SP_ENABLE;
 	switch (fb->pixel_format) {
 	sprctl |= SP_GAMMA_ENABLE;
 	if (obj->tiling_mode != I915_TILING_NONE)
-		sprctl |= SP_TILED;
-	sprctl |= SP_ENABLE;
-	intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
-				       pixel_size, true,
-				       src_w != crtc_w || src_h != crtc_h);
+		sprctl |= SP_TILED;
 	/* Sizes are 0 based */
 	src_w--;
 	src_h--;
 	crtc_w--;
 	crtc_h--;
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
-	linear_offset = y * fb->pitches[0] + x * pixel_size;
+	sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
-	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
+							&x, &y,
 							obj->tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
-	if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+	if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 		sprctl |= SP_ROTATE_180;
+		x += src_w;
+		y += src_h;
+		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+	}
-		x += src_w;
+	if (key->flags) {
-		y += src_h;
+		I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
-		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+		I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 		I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 	I915_WRITE(SPCNTR(pipe, plane), sprctl);
 	I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
-			     sprsurf_offset);
+		   sprsurf_offset);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
+	POSTING_READ(SPSURF(pipe, plane));
+}
 static void
 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
+{
 	struct drm_device *dev = dplane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(dplane);
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
-	u32 start_vbl_count;
-	bool atomic_update;
+	int pipe = intel_plane->pipe;
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
-	intel_update_primary_plane(intel_crtc);
 	int plane = intel_plane->plane;
-	I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
-		   ~SP_ENABLE);
-	/* Activate double buffered register update */
-	I915_WRITE(SPSURF(pipe, plane), 0);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
-	intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
-}
-static int
-vlv_update_colorkey(struct drm_plane *dplane,
-		    struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = dplane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
-	u32 sprctl;
-	if (key->flags & I915_SET_COLORKEY_DESTINATION)
-		return -EINVAL;
-	I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
-	I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
-	I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
-	sprctl = I915_READ(SPCNTR(pipe, plane));
-	sprctl &= ~SP_SOURCE_KEY;
-	if (key->flags & I915_SET_COLORKEY_SOURCE)
-		sprctl |= SP_SOURCE_KEY;
-	I915_WRITE(SPCNTR(pipe, plane), sprctl);
-	POSTING_READ(SPKEYMSK(pipe, plane));
-	return 0;
-}
-static void
-vlv_get_colorkey(struct drm_plane *dplane,
-		 struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = dplane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(dplane);
-	int pipe = intel_plane->pipe;
-	int plane = intel_plane->plane;
-	u32 sprctl;
-	key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
-	key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
-	key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
-	sprctl = I915_READ(SPCNTR(pipe, plane));
-	if (sprctl & SP_SOURCE_KEY)
+	I915_WRITE(SPCNTR(pipe, plane), 0);
 		key->flags = I915_SET_COLORKEY_SOURCE;
-	else
+	I915_WRITE(SPSURF(pipe, plane), 0);
-		key->flags = I915_SET_COLORKEY_NONE;
+	POSTING_READ(SPSURF(pipe, plane));
 }
 static void
 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 		 struct drm_framebuffer *fb,
-		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+		 int crtc_x, int crtc_y,
 		 unsigned int crtc_w, unsigned int crtc_h,
 		 uint32_t x, uint32_t y,
 		 uint32_t src_w, uint32_t src_h)
 {
 	struct drm_device *dev = plane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-	int pipe = intel_plane->pipe;
+	enum pipe pipe = intel_plane->pipe;
-	u32 sprctl, sprscale = 0;
-	unsigned long sprsurf_offset, linear_offset;
-	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	u32 start_vbl_count;
-	bool atomic_update;
-	sprctl = I915_READ(SPRCTL(pipe));
+	u32 sprctl, sprscale = 0;
-	/* Mask out pixel format bits in case we change it */
+	unsigned long sprsurf_offset, linear_offset;
-	sprctl &= ~SPRITE_PIXFORMAT_MASK;
+	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
+	const struct drm_intel_sprite_colorkey *key =
-	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
+		&to_intel_plane_state(plane->state)->ckey;
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 	else
-	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
+		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
-	sprctl |= SPRITE_ENABLE;
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		sprctl |= SPRITE_PIPE_CSC_ENABLE;
 	if (crtc_w != src_w || crtc_h != src_h)
 		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
+		intel_gen4_compute_page_offset(dev_priv,
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+					       &x, &y, obj->tiling_mode,
-						 pixel_size, fb->pitches[0]);
+					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
-	if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+	if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 		sprctl |= SPRITE_ROTATE_180;
 			linear_offset += src_h * fb->pitches[0] +
 				src_w * pixel_size;
+		}
+	}
+	if (key->flags) {
+		I915_WRITE(SPRKEYVAL(pipe), key->min_value);
+		I915_WRITE(SPRKEYMAX(pipe), key->max_value);
+		I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
+	}
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
+	if (key->flags & I915_SET_COLORKEY_DESTINATION)
+		sprctl |= SPRITE_DEST_KEY;
 	else if (key->flags & I915_SET_COLORKEY_SOURCE)
-	intel_update_primary_plane(intel_crtc);
+		sprctl |= SPRITE_SOURCE_KEY;
 	if (intel_plane->can_scale)
-	I915_WRITE(SPRSCALE(pipe), sprscale);
+		I915_WRITE(SPRSCALE(pipe), sprscale);
 	I915_WRITE(SPRCTL(pipe), sprctl);
 	I915_WRITE(SPRSURF(pipe),
-			     i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
+		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
+	POSTING_READ(SPRSURF(pipe));
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
+}
 static void
 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
+{
 	struct drm_device *dev = plane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_plane *intel_plane = to_intel_plane(plane);
-	int pipe = intel_plane->pipe;
-	u32 start_vbl_count;
-	bool atomic_update;
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
-	intel_update_primary_plane(intel_crtc);
+	int pipe = intel_plane->pipe;
-	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
+	I915_WRITE(SPRCTL(pipe), 0);
 	/* Can't leave the scaler enabled... */
-	if (intel_plane->can_scale)
-	I915_WRITE(SPRSCALE(pipe), 0);
-	/* Activate double buffered register update */
-	I915_WRITE(SPRSURF(pipe), 0);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
-	/*
-	 * Avoid underruns when disabling the sprite.
-	 * FIXME remove once watermark updates are done properly.
-	 */
-	intel_wait_for_vblank(dev, pipe);
-	intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
-}
-static int
-ivb_update_colorkey(struct drm_plane *plane,
-		    struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane;
-	u32 sprctl;
-	int ret = 0;
-	intel_plane = to_intel_plane(plane);
-	I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
-	I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
-	I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
-	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
-	sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
-	if (key->flags & I915_SET_COLORKEY_DESTINATION)
-		sprctl |= SPRITE_DEST_KEY;
-	else if (key->flags & I915_SET_COLORKEY_SOURCE)
-		sprctl |= SPRITE_SOURCE_KEY;
+	if (intel_plane->can_scale)
-	I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
-	POSTING_READ(SPRKEYMSK(intel_plane->pipe));
-	return ret;
-}
-static void
-ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane;
-	u32 sprctl;
-	intel_plane = to_intel_plane(plane);
-	key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
-	key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
-	key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
+		I915_WRITE(SPRSCALE(pipe), 0);
-	key->flags = 0;
-	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
-	if (sprctl & SPRITE_DEST_KEY)
-		key->flags = I915_SET_COLORKEY_DESTINATION;
-	else if (sprctl & SPRITE_SOURCE_KEY)
 		key->flags = I915_SET_COLORKEY_SOURCE;
-	else
+	I915_WRITE(SPRSURF(pipe), 0);
-		key->flags = I915_SET_COLORKEY_NONE;
+	POSTING_READ(SPRSURF(pipe));
+}
 static void
 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 		 struct drm_framebuffer *fb,
-		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+		 int crtc_x, int crtc_y,
 		 unsigned int crtc_w, unsigned int crtc_h,
 		 uint32_t x, uint32_t y,
 		 uint32_t src_w, uint32_t src_h)
 {
 	struct drm_device *dev = plane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int pipe = intel_plane->pipe;
 	unsigned long dvssurf_offset, linear_offset;
-	u32 dvscntr, dvsscale;
-	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	u32 start_vbl_count;
-	bool atomic_update;
-	dvscntr = I915_READ(DVSCNTR(pipe));
+	u32 dvscntr, dvsscale;
-	/* Mask out pixel format bits in case we change it */
-	dvscntr &= ~DVS_PIXFORMAT_MASK;
+	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
-	dvscntr &= ~DVS_RGB_ORDER_XBGR;
+	const struct drm_intel_sprite_colorkey *key =
-	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
+		&to_intel_plane_state(plane->state)->ckey;
 	dvscntr &= ~DVS_TILED;
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dvscntr |= DVS_TILED;
 	if (IS_GEN6(dev))
-		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
-	dvscntr |= DVS_ENABLE;
+		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 	intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 	if (crtc_w != src_w || crtc_h != src_h)
 		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
+		intel_gen4_compute_page_offset(dev_priv,
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+					       &x, &y, obj->tiling_mode,
-						 pixel_size, fb->pitches[0]);
+					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
-	if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+	if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 		dvscntr |= DVS_ROTATE_180;
 		x += src_w;
+		y += src_h;
+		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+	}
-		y += src_h;
+	if (key->flags) {
+		I915_WRITE(DVSKEYVAL(pipe), key->min_value);
+		I915_WRITE(DVSKEYMAX(pipe), key->max_value);
-		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+		I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
+	}
 	if (key->flags & I915_SET_COLORKEY_DESTINATION)
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
+		dvscntr |= DVS_DEST_KEY;
 	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 	I915_WRITE(DVSSCALE(pipe), dvsscale);
 	I915_WRITE(DVSCNTR(pipe), dvscntr);
 	I915_WRITE(DVSSURF(pipe),
-			     i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
+		   i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
+	POSTING_READ(DVSSURF(pipe));
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
+}
 static void
 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
+{
 	struct drm_device *dev = plane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_plane *intel_plane = to_intel_plane(plane);
-	int pipe = intel_plane->pipe;
-	u32 start_vbl_count;
-	bool atomic_update;
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
-	intel_update_primary_plane(intel_crtc);
+	int pipe = intel_plane->pipe;
-	I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
+	I915_WRITE(DVSCNTR(pipe), 0);
-	/* Disable the scaler */
-	I915_WRITE(DVSSCALE(pipe), 0);
-	/* Flush double buffered register updates */
-	I915_WRITE(DVSSURF(pipe), 0);
-	intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	if (atomic_update)
-		intel_pipe_update_end(intel_crtc, start_vbl_count);
-	/*
-	 * Avoid underruns when disabling the sprite.
-	 * FIXME remove once watermark updates are done properly.
-	 */
-	intel_wait_for_vblank(dev, pipe);
-	intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
-}
-static void
-intel_post_enable_primary(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	/*
-	 * BDW signals flip done immediately if the plane
-	 * is disabled, even if the plane enable is already
-	 * armed to occur at the next vblank :(
-	 */
-	if (IS_BROADWELL(dev))
-		intel_wait_for_vblank(dev, intel_crtc->pipe);
-	/*
-	 * FIXME IPS should be fine as long as one plane is
-	 * enabled, but in practice it seems to have problems
-	 * when going from primary only to sprite only and vice
-	 * versa.
-	 */
-		hsw_enable_ips(intel_crtc);
-	mutex_lock(&dev->struct_mutex);
-	intel_update_fbc(dev);
-	mutex_unlock(&dev->struct_mutex);
-}
-static void
-intel_pre_disable_primary(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	mutex_lock(&dev->struct_mutex);
-	if (dev_priv->fbc.plane == intel_crtc->plane)
-		intel_disable_fbc(dev);
-	mutex_unlock(&dev->struct_mutex);
-	/*
-	 * FIXME IPS should be fine as long as one plane is
-	 * enabled, but in practice it seems to have problems
-	 * when going from primary only to sprite only and vice
-	 * versa.
-	 */
-	hsw_disable_ips(intel_crtc);
-}
-static int
-ilk_update_colorkey(struct drm_plane *plane,
-		    struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane;
-	u32 dvscntr;
-	int ret = 0;
-	intel_plane = to_intel_plane(plane);
-	I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
-	I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
-	I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
-	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
-	dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
-	if (key->flags & I915_SET_COLORKEY_DESTINATION)
-		dvscntr |= DVS_DEST_KEY;
-	else if (key->flags & I915_SET_COLORKEY_SOURCE)
-		dvscntr |= DVS_SOURCE_KEY;
-	I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
-	POSTING_READ(DVSKEYMSK(intel_plane->pipe));
-	return ret;
-}
-static void
-ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_plane *intel_plane;
-	u32 dvscntr;
-	intel_plane = to_intel_plane(plane);
-	key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
-	key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
-	key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
+	/* Disable the scaler */
-	key->flags = 0;
+	I915_WRITE(DVSSCALE(pipe), 0);
-	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
-	if (dvscntr & DVS_DEST_KEY)
-		key->flags = I915_SET_COLORKEY_DESTINATION;
-	else if (dvscntr & DVS_SOURCE_KEY)
-		key->flags = I915_SET_COLORKEY_SOURCE;
-	else
-		key->flags = I915_SET_COLORKEY_NONE;
-}
-static bool colorkey_enabled(struct intel_plane *intel_plane)
-{
-	struct drm_intel_sprite_colorkey key;
 	intel_plane->get_colorkey(&intel_plane->base, &key);
 	I915_WRITE(DVSSURF(pipe), 0);
-	return key.flags != I915_SET_COLORKEY_NONE;
+	POSTING_READ(DVSSURF(pipe));
+}
 static int
+intel_check_sprite_plane(struct drm_plane *plane,
+			 struct intel_crtc_state *crtc_state,
-static int
+			 struct intel_plane_state *state)
 intel_check_sprite_plane(struct drm_plane *plane,
-			 struct intel_plane_state *state)
+	struct drm_device *dev = plane->dev;
-{
-	struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
+	struct drm_crtc *crtc = state->base.crtc;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_framebuffer *fb = state->fb;
+	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+	struct drm_framebuffer *fb = state->base.fb;
 	int crtc_x, crtc_y;
-	unsigned int crtc_w, crtc_h;
-	uint32_t src_x, src_y, src_w, src_h;
+	unsigned int crtc_w, crtc_h;
-	struct drm_rect *src = &state->src;
+	uint32_t src_x, src_y, src_w, src_h;
-	struct drm_rect *dst = &state->dst;
+	struct drm_rect *src = &state->src;
+	struct drm_rect *dst = &state->dst;
+	const struct drm_rect *clip = &state->clip;
+	int hscale, vscale;
+	int max_scale, min_scale;
-	struct drm_rect *orig_src = &state->orig_src;
+	bool can_scale;
+	int pixel_size;
-	const struct drm_rect *clip = &state->clip;
+	if (!fb) {
-	int hscale, vscale;
+		state->visible = false;
-	int max_scale, min_scale;
+		return 0;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 	if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 		DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 		return -EINVAL;
+	}
-	/* Sprite planes can be linear or x-tiled surfaces */
+	/* setup can_scale, min_scale, max_scale */
+	if (INTEL_INFO(dev)->gen >= 9) {
-	switch (obj->tiling_mode) {
+		/* use scaler when colorkey is not required */
-		case I915_TILING_NONE:
+		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
-		case I915_TILING_X:
+			can_scale = 1;
+			min_scale = 1;
-			break;
+			max_scale = skl_max_scale(intel_crtc, crtc_state);
+		} else {
+			can_scale = 0;
-		default:
+			min_scale = DRM_PLANE_HELPER_NO_SCALING;
+			max_scale = DRM_PLANE_HELPER_NO_SCALING;
-			DRM_DEBUG_KMS("Unsupported tiling mode\n");
+		}
+	} else {
+		can_scale = intel_plane->can_scale;
+		max_scale = intel_plane->max_downscale << 16;
-			return -EINVAL;
+		min_scale = intel_plane->can_scale ? 1 : (1 << 16);
+	}
 	/*
 	 * FIXME the following code does a bunch of fuzzy adjustments to the
 	 * coordinates and sizes. We probably need some way to decide whether
-	 * more strict checking should be done instead.
-	 */
-	max_scale = intel_plane->max_downscale << 16;
-	min_scale = intel_plane->can_scale ? 1 : (1 << 16);
+	 * more strict checking should be done instead.
+	 */
 	drm_rect_rotate(src, fb->width << 16, fb->height << 16,
-			intel_plane->rotation);
+			state->base.rotation);
 		drm_rect_adjust_size(src,
 				     drm_rect_width(dst) * hscale - drm_rect_width(src),
 				     drm_rect_height(dst) * vscale - drm_rect_height(src));
 		drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
-				    intel_plane->rotation);
+				    state->base.rotation);
 		/* sanity check to make sure the src viewport wasn't enlarged */
-		WARN_ON(src->x1 < (int) orig_src->x1 ||
+		WARN_ON(src->x1 < (int) state->base.src_x ||
-			src->y1 < (int) orig_src->y1 ||
+			src->y1 < (int) state->base.src_y ||
-			src->x2 > (int) orig_src->x2 ||
+			src->x2 > (int) state->base.src_x + state->base.src_w ||
-			src->y2 > (int) orig_src->y2);
+			src->y2 > (int) state->base.src_y + state->base.src_h);
-	/*
+		/*
-	/*
+			/*
 			 * Must keep src and dst the
 			 * same if we can't scale.
-	 */
+			 */
-			if (!intel_plane->can_scale)
+			if (!can_scale)
 				crtc_w &= ~1;
 			if (crtc_w == 0)
 	/* Check size restrictions when scaling */
 	if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 		unsigned int width_bytes;
-		WARN_ON(!intel_plane->can_scale);
+		WARN_ON(!can_scale);
 		/* FIXME interlacing min height is 6 */
+		if (crtc_w < 3 || crtc_h < 3)
-		if (crtc_w < 3 || crtc_h < 3)
+			state->visible = false;
 			state->visible = false;
+		if (src_w < 3 || src_h < 3)
-		if (src_w < 3 || src_h < 3)
+			state->visible = false;
 			state->visible = false;
 		pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 		width_bytes = ((src_x * pixel_size) & 63) +
 					src_w * pixel_size;
-		if (src_w > 2048 || src_h > 2048 ||
+		if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
-		    width_bytes > 4096 || fb->pitches[0] > 4096) {
+		    width_bytes > 4096 || fb->pitches[0] > 4096)) {
 			DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
-		return -EINVAL;
+			return -EINVAL;
+		}
+	}
 	if (state->visible) {
-		src->x1 = src_x;
+		src->x1 = src_x << 16;
-		src->x2 = src_x + src_w;
+		src->x2 = (src_x + src_w) << 16;
-		src->y1 = src_y;
+		src->y1 = src_y << 16;
-		src->y2 = src_y + src_h;
-	}
-	dst->x1 = crtc_x;
-	dst->x2 = crtc_x + crtc_w;
-	dst->y1 = crtc_y;
-	dst->y2 = crtc_y + crtc_h;
-	return 0;
-}
-static int
-intel_prepare_sprite_plane(struct drm_plane *plane,
-			   struct intel_plane_state *state)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_crtc *crtc = state->crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	enum pipe pipe = intel_crtc->pipe;
-	struct drm_framebuffer *fb = state->fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-	struct drm_i915_gem_object *old_obj = intel_plane->obj;
-	int ret;
-	if (old_obj != obj) {
-	mutex_lock(&dev->struct_mutex);
-	/* Note that this will apply the VT-d workaround for scanouts,
-	 * which is more restrictive than required for sprites. (The
-	 * primary plane requires 256KiB alignment with 64 PTE padding,
-		 * the sprite planes only require 128KiB alignment and 32 PTE
-		 * padding.
-	 */
-		ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
-		if (ret == 0)
+		src->y2 = (src_y + src_h) << 16;
 	i915_gem_track_fb(old_obj, obj,
 			  INTEL_FRONTBUFFER_SPRITE(pipe));
-	mutex_unlock(&dev->struct_mutex);
+	dst->x1 = crtc_x;
-	if (ret)
-		return ret;
+	dst->x2 = crtc_x + crtc_w;
-	}
 	dst->y1 = crtc_y;
-	return 0;
-}
+	dst->y2 = crtc_y + crtc_h;
-static void
-intel_commit_sprite_plane(struct drm_plane *plane,
-			  struct intel_plane_state *state)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_crtc *crtc = state->crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	enum pipe pipe = intel_crtc->pipe;
-	struct drm_framebuffer *fb = state->fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-	struct drm_i915_gem_object *old_obj = intel_plane->obj;
-	int crtc_x, crtc_y;
-	unsigned int crtc_w, crtc_h;
-	uint32_t src_x, src_y, src_w, src_h;
-	struct drm_rect *dst = &state->dst;
-	const struct drm_rect *clip = &state->clip;
-	bool primary_enabled;
-	/*
-	 * If the sprite is completely covering the primary plane,
-	 * we can disable the primary and save power.
-	 */
-	primary_enabled = !drm_rect_equals(dst, clip) || colorkey_enabled(intel_plane);
-	WARN_ON(!primary_enabled && !state->visible && intel_crtc->active);
-	intel_plane->crtc_x = state->orig_dst.x1;
-	intel_plane->crtc_y = state->orig_dst.y1;
-	intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
-	intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
-	intel_plane->src_x = state->orig_src.x1;
-	intel_plane->src_y = state->orig_src.y1;
+	return 0;
-	intel_plane->src_w = drm_rect_width(&state->orig_src);
+}
 	intel_plane->src_h = drm_rect_height(&state->orig_src);
-	intel_plane->obj = obj;
+static void
+intel_commit_sprite_plane(struct drm_plane *plane,
-	if (intel_crtc->active) {
+			  struct intel_plane_state *state)
-		bool primary_was_enabled = intel_crtc->primary_enabled;
+{
+	struct drm_crtc *crtc = state->base.crtc;
-		intel_crtc->primary_enabled = primary_enabled;
+	struct intel_plane *intel_plane = to_intel_plane(plane);
+	struct drm_framebuffer *fb = state->base.fb;
-//       if (primary_was_enabled != primary_enabled)
-//           intel_crtc_wait_for_pending_flips(crtc);
-		if (primary_was_enabled && !primary_enabled)
-			intel_pre_disable_primary(crtc);
+	crtc = crtc ? crtc : plane->crtc;
-		if (state->visible) {
+	if (!crtc->state->active)
-			crtc_x = state->dst.x1;
-			crtc_y = state->dst.y1;
-			crtc_w = drm_rect_width(&state->dst);
-			crtc_h = drm_rect_height(&state->dst);
-			src_x = state->src.x1;
-			src_y = state->src.y1;
-			src_w = drm_rect_width(&state->src);
-			src_h = drm_rect_height(&state->src);
-		intel_plane->update_plane(plane, crtc, fb, obj,
-					  crtc_x, crtc_y, crtc_w, crtc_h,
-					  src_x, src_y, src_w, src_h);
-		} else {
-		intel_plane->disable_plane(plane, crtc);
-		}
-		intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe));
-		if (!primary_was_enabled && primary_enabled)
-			intel_post_enable_primary(crtc);
-	}
-	/* Unpin old obj after new one is active to avoid ugliness */
-	if (old_obj && old_obj != obj) {
-		/*
-		 * It's fairly common to simply update the position of
-		 * an existing object.  In that case, we don't need to
-		 * wait for vblank to avoid ugliness, we only need to
-		 * do the pin & ref bookkeeping.
-		 */
-		if (intel_crtc->active)
-			intel_wait_for_vblank(dev, intel_crtc->pipe);
-			mutex_lock(&dev->struct_mutex);
-		intel_unpin_fb_obj(old_obj);
-		mutex_unlock(&dev->struct_mutex);
-	}
-}
-static int
-intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
-		   struct drm_framebuffer *fb, int crtc_x, int crtc_y,
-		   unsigned int crtc_w, unsigned int crtc_h,
-		   uint32_t src_x, uint32_t src_y,
-		   uint32_t src_w, uint32_t src_h)
-{
-	struct intel_plane_state state;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int ret;
-	state.crtc = crtc;
-	state.fb = fb;
-	/* sample coordinates in 16.16 fixed point */
-	state.src.x1 = src_x;
-	state.src.x2 = src_x + src_w;
-	state.src.y1 = src_y;
-	state.src.y2 = src_y + src_h;
-	/* integer pixels */
-	state.dst.x1 = crtc_x;
-	state.dst.x2 = crtc_x + crtc_w;
-	state.dst.y1 = crtc_y;
-	state.dst.y2 = crtc_y + crtc_h;
-	state.clip.x1 = 0;
-	state.clip.y1 = 0;
-	state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
-	state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
-	state.orig_src = state.src;
-	state.orig_dst = state.dst;
-	ret = intel_check_sprite_plane(plane, &state);
-	if (ret)
-		return ret;
-	ret = intel_prepare_sprite_plane(plane, &state);
-	if (ret)
-		return ret;
-	intel_commit_sprite_plane(plane, &state);
-	return 0;
-}
-static int
-intel_disable_plane(struct drm_plane *plane)
-{
-	struct drm_device *dev = plane->dev;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct intel_crtc *intel_crtc;
-	enum pipe pipe;
-	if (!plane->fb)
-		return 0;
-	if (WARN_ON(!plane->crtc))
-		return -EINVAL;
-	intel_crtc = to_intel_crtc(plane->crtc);
-	pipe = intel_crtc->pipe;
-	if (intel_crtc->active) {
-		bool primary_was_enabled = intel_crtc->primary_enabled;
-		intel_crtc->primary_enabled = true;
-	intel_plane->disable_plane(plane, plane->crtc);
-		if (!primary_was_enabled && intel_crtc->primary_enabled)
-			intel_post_enable_primary(plane->crtc);
-	}
-	if (intel_plane->obj) {
-		if (intel_crtc->active)
-	intel_wait_for_vblank(dev, intel_plane->pipe);
-	mutex_lock(&dev->struct_mutex);
-	intel_unpin_fb_obj(intel_plane->obj);
-		i915_gem_track_fb(intel_plane->obj, NULL,
-				  INTEL_FRONTBUFFER_SPRITE(pipe));
-		mutex_unlock(&dev->struct_mutex);
+		return;
-	intel_plane->obj = NULL;
+	if (state->visible) {
 		intel_plane->update_plane(plane, crtc, fb,
 					  state->dst.x1, state->dst.y1,
-	return 0;
+					  drm_rect_width(&state->dst),
-}
+					  drm_rect_height(&state->dst),
+					  state->src.x1 >> 16,
+					  state->src.y1 >> 16,
 					  drm_rect_width(&state->src) >> 16,
-static void intel_destroy_plane(struct drm_plane *plane)
-{
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	intel_disable_plane(plane);
+					  drm_rect_height(&state->src) >> 16);
-	drm_plane_cleanup(plane);
+	} else {
-	kfree(intel_plane);
+		intel_plane->disable_plane(plane, crtc);
-}
+	}
+}
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
-int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv)
-			      struct drm_file *file_priv)
+{
-{
-	struct drm_intel_sprite_colorkey *set = data;
-	struct drm_plane *plane;
+	struct drm_intel_sprite_colorkey *set = data;
-	struct intel_plane *intel_plane;
+	struct drm_plane *plane;
-	int ret = 0;
+	struct drm_plane_state *plane_state;
+	struct drm_atomic_state *state;
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+	struct drm_modeset_acquire_ctx ctx;
-		return -ENODEV;
+	int ret = 0;
 	/* Make sure we don't try to enable both src & dest simultaneously */
-	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
-		return -EINVAL;
+	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
-	drm_modeset_lock_all(dev);
+		return -EINVAL;
-	plane = drm_plane_find(dev, set->plane_id);
-	if (!plane) {
+	if (IS_VALLEYVIEW(dev) &&
-		ret = -ENOENT;
-		goto out_unlock;
-	}
-	intel_plane = to_intel_plane(plane);
+	    set->flags & I915_SET_COLORKEY_DESTINATION)
-	ret = intel_plane->update_colorkey(plane, set);
-out_unlock:
-	drm_modeset_unlock_all(dev);
+		return -EINVAL;
-	return ret;
-}
+	plane = drm_plane_find(dev, set->plane_id);
+	if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
-int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
+		return -ENOENT;
-			      struct drm_file *file_priv)
-	struct drm_intel_sprite_colorkey *get = data;
-	struct drm_plane *plane;
-	struct intel_plane *intel_plane;
-	int ret = 0;
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		return -ENODEV;
-	drm_modeset_lock_all(dev);
-	plane = drm_plane_find(dev, get->plane_id);
-	if (!plane) {
-		ret = -ENOENT;
-		goto out_unlock;
-	}
-	intel_plane = to_intel_plane(plane);
-	intel_plane->get_colorkey(plane, get);
-out_unlock:
-	drm_modeset_unlock_all(dev);
+	drm_modeset_acquire_init(&ctx, 0);
-	return ret;
-}
+	state = drm_atomic_state_alloc(plane->dev);
+	if (!state) {
+		ret = -ENOMEM;
 		goto out;
 int intel_plane_set_property(struct drm_plane *plane,
-			     struct drm_property *prop,
-			     uint64_t val)
-{
-	struct drm_device *dev = plane->dev;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	uint64_t old_val;
-	int ret = -ENOENT;
-	if (prop == dev->mode_config.rotation_property) {
-		/* exactly one rotation angle please */
-		if (hweight32(val & 0xf) != 1)
-			return -EINVAL;
-		if (intel_plane->rotation == val)
-			return 0;
-		old_val = intel_plane->rotation;
-		intel_plane->rotation = val;
-		ret = intel_plane_restore(plane);
-		if (ret)
-			intel_plane->rotation = old_val;
-	}
-	return ret;
-}
-int intel_plane_restore(struct drm_plane *plane)
-{
-	struct intel_plane *intel_plane = to_intel_plane(plane);
+	state->acquire_ctx = &ctx;
 	if (!plane->crtc || !plane->fb)
-		return 0;
+	while (1) {
 		plane_state = drm_atomic_get_plane_state(state, plane);
-	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
+		ret = PTR_ERR_OR_ZERO(plane_state);
-			   intel_plane->crtc_x, intel_plane->crtc_y,
+		if (!ret) {
-			   intel_plane->crtc_w, intel_plane->crtc_h,
+			to_intel_plane_state(plane_state)->ckey = *set;
-			   intel_plane->src_x, intel_plane->src_y,
+			ret = drm_atomic_commit(state);
 			   intel_plane->src_w, intel_plane->src_h);
 		if (ret != -EDEADLK)
-void intel_plane_disable(struct drm_plane *plane)
+			break;
-	if (!plane->crtc || !plane->fb)
+		drm_atomic_state_clear(state);
-		return;
+		drm_modeset_backoff(&ctx);
+	}
 	intel_disable_plane(plane);
 	if (ret)
 		drm_atomic_state_free(state);
 static const struct drm_plane_funcs intel_plane_funcs = {
-	.update_plane = intel_update_plane,
+out:
 int
 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
+{
+	struct intel_plane *intel_plane;
-	struct intel_plane *intel_plane;
+	struct intel_plane_state *state;
 	unsigned long possible_crtcs;
 	const uint32_t *plane_formats;
 	int num_plane_formats;
 	intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
 	if (!intel_plane)
+		return -ENOMEM;
+	state = intel_create_plane_state(&intel_plane->base);
+	if (!state) {
+		kfree(intel_plane);
+		return -ENOMEM;
+	}
-		return -ENOMEM;
+	intel_plane->base.state = &state->base;
 	switch (INTEL_INFO(dev)->gen) {
 	case 5:
 	case 6:
 		intel_plane->can_scale = true;
 		intel_plane->max_downscale = 16;
-		intel_plane->update_plane = ilk_update_plane;
-		intel_plane->disable_plane = ilk_disable_plane;
-		intel_plane->update_colorkey = ilk_update_colorkey;
+		intel_plane->update_plane = ilk_update_plane;
-		intel_plane->get_colorkey = ilk_get_colorkey;
+		intel_plane->disable_plane = ilk_disable_plane;
-	if (IS_GEN6(dev)) {
+		if (IS_GEN6(dev)) {
+		}
 		if (IS_VALLEYVIEW(dev)) {
 			intel_plane->update_plane = vlv_update_plane;
-			intel_plane->disable_plane = vlv_disable_plane;
-			intel_plane->update_colorkey = vlv_update_colorkey;
-			intel_plane->get_colorkey = vlv_get_colorkey;
+			intel_plane->disable_plane = vlv_disable_plane;
 			plane_formats = vlv_plane_formats;
 			num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
 		} else {
-		intel_plane->update_plane = ivb_update_plane;
-		intel_plane->disable_plane = ivb_disable_plane;
-		intel_plane->update_colorkey = ivb_update_colorkey;
+			intel_plane->update_plane = ivb_update_plane;
-		intel_plane->get_colorkey = ivb_get_colorkey;
+			intel_plane->disable_plane = ivb_disable_plane;
-		plane_formats = snb_plane_formats;
+			plane_formats = snb_plane_formats;
-		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+			num_plane_formats = ARRAY_SIZE(snb_plane_formats);
-		}
-		break;
-	case 9:
-		/*
-		 * FIXME: Skylake planes can be scaled (with some restrictions),
+		}
-		 * but this is for another time.
-		 */
+		break;
-		intel_plane->can_scale = false;
+	case 9:
-		intel_plane->max_downscale = 1;
-		intel_plane->update_plane = skl_update_plane;
+		intel_plane->can_scale = true;
-		intel_plane->disable_plane = skl_disable_plane;
+		intel_plane->update_plane = skl_update_plane;
-		intel_plane->update_colorkey = skl_update_colorkey;
+		intel_plane->disable_plane = skl_disable_plane;
-		intel_plane->get_colorkey = skl_get_colorkey;
+		state->scaler_id = -1;
 		return -ENODEV;
+	}
 	intel_plane->pipe = pipe;
+	intel_plane->plane = plane;
+	intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
-	intel_plane->plane = plane;
+	intel_plane->check_plane = intel_check_sprite_plane;
-	intel_plane->rotation = BIT(DRM_ROTATE_0);
+	intel_plane->commit_plane = intel_commit_sprite_plane;
 	possible_crtcs = (1 << pipe);
 	ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
-			     &intel_plane_funcs,
+				       &intel_plane_funcs,
-			     plane_formats, num_plane_formats,
+				       plane_formats, num_plane_formats,
 				       DRM_PLANE_TYPE_OVERLAY);
 	if (ret) {
 		kfree(intel_plane);
 		goto out;
-	}
-	if (!dev->mode_config.rotation_property)
+	}
-		dev->mode_config.rotation_property =
-			drm_mode_create_rotation_property(dev,
-							  BIT(DRM_ROTATE_0) |
-							  BIT(DRM_ROTATE_180));
+	intel_create_rotation_property(dev, intel_plane);
-	if (dev->mode_config.rotation_property)
-		drm_object_attach_property(&intel_plane->base.base,
 					   dev->mode_config.rotation_property,
-					   intel_plane->rotation);
+	drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_sprite.c – Rev 5354 → 6084