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Rev 3243 | Rev 3480 | ||
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Line 48... | Line 48... | ||
48 | struct intel_plane *intel_plane = to_intel_plane(plane); |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); |
49 | int pipe = intel_plane->pipe; |
49 | int pipe = intel_plane->pipe; |
50 | u32 sprctl, sprscale = 0; |
50 | u32 sprctl, sprscale = 0; |
51 | unsigned long sprsurf_offset, linear_offset; |
51 | unsigned long sprsurf_offset, linear_offset; |
52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
- | 53 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
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Line 53... | Line 54... | ||
53 | 54 | ||
Line 54... | Line 55... | ||
54 | sprctl = I915_READ(SPRCTL(pipe)); |
55 | sprctl = I915_READ(SPRCTL(pipe)); |
55 | 56 | ||
Line 87... | Line 88... | ||
87 | 88 | ||
88 | /* must disable */ |
89 | /* must disable */ |
89 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
90 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
Line -... | Line 91... | ||
- | 91 | sprctl |= SPRITE_ENABLE; |
|
- | 92 | ||
- | 93 | if (IS_HASWELL(dev)) |
|
90 | sprctl |= SPRITE_ENABLE; |
94 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
91 | 95 | ||
92 | /* Sizes are 0 based */ |
96 | /* Sizes are 0 based */ |
93 | src_w--; |
97 | src_w--; |
94 | src_h--; |
98 | src_h--; |
Line 101... | Line 105... | ||
101 | * IVB workaround: must disable low power watermarks for at least |
105 | * IVB workaround: must disable low power watermarks for at least |
102 | * one frame before enabling scaling. LP watermarks can be re-enabled |
106 | * one frame before enabling scaling. LP watermarks can be re-enabled |
103 | * when scaling is disabled. |
107 | * when scaling is disabled. |
104 | */ |
108 | */ |
105 | if (crtc_w != src_w || crtc_h != src_h) { |
109 | if (crtc_w != src_w || crtc_h != src_h) { |
106 | if (!dev_priv->sprite_scaling_enabled) { |
110 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
- | 111 | ||
107 | dev_priv->sprite_scaling_enabled = true; |
112 | if (!scaling_was_enabled) { |
108 | intel_update_watermarks(dev); |
113 | intel_update_watermarks(dev); |
109 | intel_wait_for_vblank(dev, pipe); |
114 | intel_wait_for_vblank(dev, pipe); |
110 | } |
115 | } |
111 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
116 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
112 | } else { |
117 | } else |
113 | if (dev_priv->sprite_scaling_enabled) { |
- | |
114 | dev_priv->sprite_scaling_enabled = false; |
118 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
115 | /* potentially re-enable LP watermarks */ |
- | |
116 | intel_update_watermarks(dev); |
- | |
117 | } |
- | |
118 | } |
- | |
Line 119... | Line 119... | ||
119 | 119 | ||
120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
Line 121... | Line 121... | ||
121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
122 | 122 | ||
123 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
123 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
124 | sprsurf_offset = |
124 | sprsurf_offset = |
125 | intel_gen4_compute_offset_xtiled(&x, &y, |
125 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
Line 126... | Line 126... | ||
126 | pixel_size, fb->pitches[0]); |
126 | pixel_size, fb->pitches[0]); |
127 | linear_offset -= sprsurf_offset; |
127 | linear_offset -= sprsurf_offset; |
Line 139... | Line 139... | ||
139 | if (intel_plane->can_scale) |
139 | if (intel_plane->can_scale) |
140 | I915_WRITE(SPRSCALE(pipe), sprscale); |
140 | I915_WRITE(SPRSCALE(pipe), sprscale); |
141 | I915_WRITE(SPRCTL(pipe), sprctl); |
141 | I915_WRITE(SPRCTL(pipe), sprctl); |
142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
143 | POSTING_READ(SPRSURF(pipe)); |
143 | POSTING_READ(SPRSURF(pipe)); |
- | 144 | ||
- | 145 | /* potentially re-enable LP watermarks */ |
|
- | 146 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
|
- | 147 | intel_update_watermarks(dev); |
|
144 | } |
148 | } |
Line 145... | Line 149... | ||
145 | 149 | ||
146 | static void |
150 | static void |
147 | ivb_disable_plane(struct drm_plane *plane) |
151 | ivb_disable_plane(struct drm_plane *plane) |
148 | { |
152 | { |
149 | struct drm_device *dev = plane->dev; |
153 | struct drm_device *dev = plane->dev; |
150 | struct drm_i915_private *dev_priv = dev->dev_private; |
154 | struct drm_i915_private *dev_priv = dev->dev_private; |
151 | struct intel_plane *intel_plane = to_intel_plane(plane); |
155 | struct intel_plane *intel_plane = to_intel_plane(plane); |
- | 156 | int pipe = intel_plane->pipe; |
|
Line 152... | Line 157... | ||
152 | int pipe = intel_plane->pipe; |
157 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
153 | 158 | ||
154 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
159 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
155 | /* Can't leave the scaler enabled... */ |
160 | /* Can't leave the scaler enabled... */ |
156 | if (intel_plane->can_scale) |
161 | if (intel_plane->can_scale) |
157 | I915_WRITE(SPRSCALE(pipe), 0); |
162 | I915_WRITE(SPRSCALE(pipe), 0); |
158 | /* Activate double buffered register update */ |
163 | /* Activate double buffered register update */ |
Line 159... | Line 164... | ||
159 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
164 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
- | 165 | POSTING_READ(SPRSURF(pipe)); |
|
- | 166 | ||
- | 167 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
|
160 | POSTING_READ(SPRSURF(pipe)); |
168 | |
161 | 169 | /* potentially re-enable LP watermarks */ |
|
Line 162... | Line 170... | ||
162 | dev_priv->sprite_scaling_enabled = false; |
170 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
163 | intel_update_watermarks(dev); |
171 | intel_update_watermarks(dev); |
Line 285... | Line 293... | ||
285 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
293 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
286 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
294 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
Line 287... | Line 295... | ||
287 | 295 | ||
288 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
296 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
289 | dvssurf_offset = |
297 | dvssurf_offset = |
290 | intel_gen4_compute_offset_xtiled(&x, &y, |
298 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
291 | pixel_size, fb->pitches[0]); |
299 | pixel_size, fb->pitches[0]); |
Line 292... | Line 300... | ||
292 | linear_offset -= dvssurf_offset; |
300 | linear_offset -= dvssurf_offset; |
293 | 301 | ||
Line 589... | Line 597... | ||
589 | 597 | ||
590 | /* Make sure we don't try to enable both src & dest simultaneously */ |
598 | /* Make sure we don't try to enable both src & dest simultaneously */ |
591 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
599 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
Line 592... | Line 600... | ||
592 | return -EINVAL; |
600 | return -EINVAL; |
Line 593... | Line 601... | ||
593 | 601 | ||
594 | mutex_lock(&dev->mode_config.mutex); |
602 | drm_modeset_lock_all(dev); |
595 | 603 | ||
596 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
604 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
Line 602... | Line 610... | ||
602 | plane = obj_to_plane(obj); |
610 | plane = obj_to_plane(obj); |
603 | intel_plane = to_intel_plane(plane); |
611 | intel_plane = to_intel_plane(plane); |
604 | ret = intel_plane->update_colorkey(plane, set); |
612 | ret = intel_plane->update_colorkey(plane, set); |
Line 605... | Line 613... | ||
605 | 613 | ||
606 | out_unlock: |
614 | out_unlock: |
607 | mutex_unlock(&dev->mode_config.mutex); |
615 | drm_modeset_unlock_all(dev); |
608 | return ret; |
616 | return ret; |
Line 609... | Line 617... | ||
609 | } |
617 | } |
610 | 618 | ||
Line 616... | Line 624... | ||
616 | struct drm_plane *plane; |
624 | struct drm_plane *plane; |
617 | struct intel_plane *intel_plane; |
625 | struct intel_plane *intel_plane; |
618 | int ret = 0; |
626 | int ret = 0; |
Line 619... | Line 627... | ||
619 | 627 | ||
Line 620... | Line 628... | ||
620 | 628 | ||
621 | mutex_lock(&dev->mode_config.mutex); |
629 | drm_modeset_lock_all(dev); |
622 | 630 | ||
623 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
631 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
Line 629... | Line 637... | ||
629 | plane = obj_to_plane(obj); |
637 | plane = obj_to_plane(obj); |
630 | intel_plane = to_intel_plane(plane); |
638 | intel_plane = to_intel_plane(plane); |
631 | intel_plane->get_colorkey(plane, get); |
639 | intel_plane->get_colorkey(plane, get); |
Line 632... | Line 640... | ||
632 | 640 | ||
633 | out_unlock: |
641 | out_unlock: |
634 | mutex_unlock(&dev->mode_config.mutex); |
642 | drm_modeset_unlock_all(dev); |
635 | return ret; |
643 | return ret; |
Line 636... | Line 644... | ||
636 | } |
644 | } |
637 | 645 |