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Line 27... | Line 27... | ||
27 | 27 | ||
28 | /* |
28 | /* |
29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
30 | * VLV_VLV2_PUNIT_HAS_0.8.docx |
30 | * VLV_VLV2_PUNIT_HAS_0.8.docx |
- | 31 | */ |
|
- | 32 | ||
- | 33 | /* Standard MMIO read, non-posted */ |
|
- | 34 | #define SB_MRD_NP 0x00 |
|
- | 35 | /* Standard MMIO write, non-posted */ |
|
- | 36 | #define SB_MWR_NP 0x01 |
|
- | 37 | /* Private register read, double-word addressing, non-posted */ |
|
- | 38 | #define SB_CRRDDA_NP 0x06 |
|
- | 39 | /* Private register write, double-word addressing, non-posted */ |
|
- | 40 | #define SB_CRWRDA_NP 0x07 |
|
31 | */ |
41 | |
32 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
42 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
33 | u32 port, u32 opcode, u32 addr, u32 *val) |
43 | u32 port, u32 opcode, u32 addr, u32 *val) |
34 | { |
44 | { |
35 | u32 cmd, be = 0xf, bar = 0; |
45 | u32 cmd, be = 0xf, bar = 0; |
36 | bool is_read = (opcode == PUNIT_OPCODE_REG_READ || |
- | |
Line 37... | Line 46... | ||
37 | opcode == DPIO_OPCODE_REG_READ); |
46 | bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP); |
38 | 47 | ||
39 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
48 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
Line 72... | Line 81... | ||
72 | 81 | ||
Line 73... | Line 82... | ||
73 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
82 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
74 | 83 | ||
75 | mutex_lock(&dev_priv->dpio_lock); |
84 | mutex_lock(&dev_priv->dpio_lock); |
76 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
85 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
Line 77... | Line 86... | ||
77 | PUNIT_OPCODE_REG_READ, addr, &val); |
86 | SB_CRRDDA_NP, addr, &val); |
78 | mutex_unlock(&dev_priv->dpio_lock); |
87 | mutex_unlock(&dev_priv->dpio_lock); |
Line 84... | Line 93... | ||
84 | { |
93 | { |
85 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
94 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Line 86... | Line 95... | ||
86 | 95 | ||
87 | mutex_lock(&dev_priv->dpio_lock); |
96 | mutex_lock(&dev_priv->dpio_lock); |
88 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
89 | PUNIT_OPCODE_REG_WRITE, addr, &val); |
98 | SB_CRWRDA_NP, addr, &val); |
90 | mutex_unlock(&dev_priv->dpio_lock); |
99 | mutex_unlock(&dev_priv->dpio_lock); |
Line 91... | Line 100... | ||
91 | } |
100 | } |
92 | 101 | ||
93 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
102 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
Line 94... | Line 103... | ||
94 | { |
103 | { |
95 | u32 val = 0; |
104 | u32 val = 0; |
Line 96... | Line 105... | ||
96 | 105 | ||
97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
106 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
Line 98... | Line 107... | ||
98 | PUNIT_OPCODE_REG_READ, reg, &val); |
107 | SB_CRRDDA_NP, reg, &val); |
99 | 108 | ||
100 | return val; |
109 | return val; |
101 | } |
110 | } |
102 | 111 | ||
Line 103... | Line 112... | ||
103 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
112 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
104 | { |
113 | { |
105 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
114 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
Line 106... | Line 115... | ||
106 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
115 | SB_CRWRDA_NP, reg, &val); |
Line 107... | Line 116... | ||
107 | } |
116 | } |
108 | 117 | ||
109 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
118 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
110 | { |
119 | { |
Line 111... | Line 120... | ||
111 | u32 val = 0; |
120 | u32 val = 0; |
112 | 121 | ||
Line 113... | Line 122... | ||
113 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
122 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
114 | 123 | ||
115 | mutex_lock(&dev_priv->dpio_lock); |
124 | mutex_lock(&dev_priv->dpio_lock); |
116 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
125 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
117 | PUNIT_OPCODE_REG_READ, addr, &val); |
126 | SB_CRRDDA_NP, addr, &val); |
118 | mutex_unlock(&dev_priv->dpio_lock); |
127 | mutex_unlock(&dev_priv->dpio_lock); |
119 | 128 | ||
Line 120... | Line 129... | ||
120 | return val; |
129 | return val; |
121 | } |
130 | } |
122 | 131 | ||
123 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
132 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
124 | { |
133 | { |
Line 125... | Line 134... | ||
125 | u32 val = 0; |
134 | u32 val = 0; |
126 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
135 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
127 | PUNIT_OPCODE_REG_READ, reg, &val); |
136 | SB_CRRDDA_NP, reg, &val); |
128 | return val; |
137 | return val; |
129 | } |
138 | } |
130 | 139 | ||
131 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
140 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
Line 132... | Line 141... | ||
132 | { |
141 | { |
133 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
142 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
134 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
143 | SB_CRWRDA_NP, reg, &val); |
135 | } |
144 | } |
136 | 145 | ||
Line 137... | Line 146... | ||
137 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
146 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
138 | { |
147 | { |
139 | u32 val = 0; |
148 | u32 val = 0; |
140 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
149 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
141 | PUNIT_OPCODE_REG_READ, reg, &val); |
150 | SB_CRRDDA_NP, reg, &val); |
142 | return val; |
151 | return val; |
143 | } |
152 | } |
Line 144... | Line 153... | ||
144 | 153 | ||
145 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
154 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
146 | { |
155 | { |
147 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
156 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
148 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
157 | SB_CRWRDA_NP, reg, &val); |
Line 149... | Line 158... | ||
149 | } |
158 | } |
150 | 159 | ||
151 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
160 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
152 | { |
161 | { |
153 | u32 val = 0; |
162 | u32 val = 0; |
154 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
163 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
155 | PUNIT_OPCODE_REG_READ, reg, &val); |
164 | SB_CRRDDA_NP, reg, &val); |
Line 156... | Line 165... | ||
156 | return val; |
165 | return val; |
157 | } |
166 | } |
158 | 167 | ||
159 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
168 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
160 | { |
169 | { |
Line 161... | Line 170... | ||
161 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
170 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
162 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
171 | SB_CRWRDA_NP, reg, &val); |
163 | } |
172 | } |
Line 164... | Line 173... | ||
164 | 173 | ||
165 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
174 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
- | 175 | { |
|
- | 176 | u32 val = 0; |
|
- | 177 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
|
- | 178 | SB_CRRDDA_NP, reg, &val); |
|
- | 179 | return val; |
|
- | 180 | } |
|
- | 181 | ||
- | 182 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
166 | { |
183 | { |
167 | u32 val = 0; |
184 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
Line 168... | Line 185... | ||
168 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
185 | SB_CRWRDA_NP, reg, &val); |
169 | PUNIT_OPCODE_REG_READ, reg, &val); |
186 | } |
170 | return val; |
187 | |
171 | } |
188 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
172 | 189 | { |
|
Line 173... | Line 190... | ||
173 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
190 | u32 val = 0; |
174 | { |
191 | |
175 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
192 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
Line 251... | Line 268... | ||
251 | } |
268 | } |
Line 252... | Line 269... | ||
252 | 269 | ||
253 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
270 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
254 | { |
271 | { |
255 | u32 val = 0; |
272 | u32 val = 0; |
256 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
273 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, |
257 | DPIO_OPCODE_REG_READ, reg, &val); |
274 | reg, &val); |
258 | return val; |
275 | return val; |
Line 259... | Line 276... | ||
259 | } |
276 | } |
260 | 277 | ||
261 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
278 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
262 | { |
279 | { |
263 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
280 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, |