Rev 4104 | Rev 6084 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4104 | Rev 4560 | ||
---|---|---|---|
Line 23... | Line 23... | ||
23 | */ |
23 | */ |
Line 24... | Line 24... | ||
24 | 24 | ||
25 | #include "i915_drv.h" |
25 | #include "i915_drv.h" |
Line -... | Line 26... | ||
- | 26 | #include "intel_drv.h" |
|
26 | #include "intel_drv.h" |
27 | |
- | 28 | /* |
|
- | 29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
|
27 | 30 | * VLV_VLV2_PUNIT_HAS_0.8.docx |
|
28 | /* IOSF sideband */ |
31 | */ |
29 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
32 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
30 | u32 port, u32 opcode, u32 addr, u32 *val) |
33 | u32 port, u32 opcode, u32 addr, u32 *val) |
31 | { |
34 | { |
Line 85... | Line 88... | ||
85 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
88 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
86 | PUNIT_OPCODE_REG_WRITE, addr, &val); |
89 | PUNIT_OPCODE_REG_WRITE, addr, &val); |
87 | mutex_unlock(&dev_priv->dpio_lock); |
90 | mutex_unlock(&dev_priv->dpio_lock); |
88 | } |
91 | } |
Line -... | Line 92... | ||
- | 92 | ||
- | 93 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
|
- | 94 | { |
|
- | 95 | u32 val = 0; |
|
- | 96 | ||
- | 97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
|
- | 98 | PUNIT_OPCODE_REG_READ, reg, &val); |
|
- | 99 | ||
- | 100 | return val; |
|
- | 101 | } |
|
- | 102 | ||
- | 103 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 104 | { |
|
- | 105 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
|
- | 106 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
|
- | 107 | } |
|
89 | 108 | ||
90 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
109 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
91 | { |
110 | { |
Line 92... | Line 111... | ||
92 | u32 val = 0; |
111 | u32 val = 0; |
Line 99... | Line 118... | ||
99 | mutex_unlock(&dev_priv->dpio_lock); |
118 | mutex_unlock(&dev_priv->dpio_lock); |
Line 100... | Line 119... | ||
100 | 119 | ||
101 | return val; |
120 | return val; |
Line 102... | Line 121... | ||
102 | } |
121 | } |
103 | 122 | ||
104 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg) |
123 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
- | 124 | { |
|
- | 125 | u32 val = 0; |
|
- | 126 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
|
- | 127 | PUNIT_OPCODE_REG_READ, reg, &val); |
|
Line -... | Line 128... | ||
- | 128 | return val; |
|
- | 129 | } |
|
105 | { |
130 | |
- | 131 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 132 | { |
|
- | 133 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
|
- | 134 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
|
- | 135 | } |
|
- | 136 | ||
- | 137 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
|
- | 138 | { |
|
- | 139 | u32 val = 0; |
|
- | 140 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
|
- | 141 | PUNIT_OPCODE_REG_READ, reg, &val); |
|
- | 142 | return val; |
|
- | 143 | } |
|
- | 144 | ||
- | 145 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 146 | { |
|
- | 147 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
|
- | 148 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
|
- | 149 | } |
|
- | 150 | ||
- | 151 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
|
106 | u32 val = 0; |
152 | { |
- | 153 | u32 val = 0; |
|
- | 154 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
|
Line -... | Line 155... | ||
- | 155 | PUNIT_OPCODE_REG_READ, reg, &val); |
|
- | 156 | return val; |
|
- | 157 | } |
|
- | 158 | ||
- | 159 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 160 | { |
|
- | 161 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
|
- | 162 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
|
- | 163 | } |
|
- | 164 | ||
- | 165 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
|
107 | 166 | { |
|
108 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO, |
167 | u32 val = 0; |
Line 109... | Line 168... | ||
109 | DPIO_OPCODE_REG_READ, reg, &val); |
168 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
110 | 169 | PUNIT_OPCODE_REG_READ, reg, &val); |
|
111 | return val; |
170 | return val; |
- | 171 | } |
|
- | 172 | ||
- | 173 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 174 | { |
|
- | 175 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
|
- | 176 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
|
- | 177 | } |
|
- | 178 | ||
- | 179 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
|
- | 180 | { |
|
- | 181 | u32 val = 0; |
|
- | 182 | ||
- | 183 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
|
- | 184 | DPIO_OPCODE_REG_READ, reg, &val); |
|
- | 185 | return val; |
|
112 | } |
186 | } |
113 | 187 | ||
Line 114... | Line 188... | ||
114 | void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) |
188 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
115 | { |
189 | { |
Line 173... | Line 247... | ||
173 | 100)) { |
247 | 100)) { |
174 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
248 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
175 | return; |
249 | return; |
176 | } |
250 | } |
177 | }><>><>><>><>><>><>><> |
251 | } |
- | 252 | ||
- | 253 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
|
- | 254 | { |
|
- | 255 | u32 val = 0; |
|
- | 256 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
|
- | 257 | DPIO_OPCODE_REG_READ, reg, &val); |
|
- | 258 | return val; |
|
- | 259 | } |
|
- | 260 | ||
- | 261 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
|
- | 262 | { |
|
- | 263 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
|
- | 264 | DPIO_OPCODE_REG_WRITE, reg, &val); |
|
- | 265 | }><>><>><>><>><>><>><> |