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Rev 5354 | Rev 6084 | ||
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Line 24... | Line 24... | ||
24 | * Eugeni Dodonov |
24 | * Eugeni Dodonov |
25 | * Daniel Vetter |
25 | * Daniel Vetter |
26 | * |
26 | * |
27 | */ |
27 | */ |
Line 28... | Line 28... | ||
28 | 28 | ||
- | 29 | #include |
|
Line 29... | Line 30... | ||
29 | //#include |
30 | #include |
30 | 31 | ||
31 | #include "i915_drv.h" |
- | |
32 | #include "intel_drv.h" |
- | |
Line 33... | Line 32... | ||
33 | #include |
32 | #include "i915_drv.h" |
34 | #include |
33 | #include "intel_drv.h" |
35 | 34 | ||
36 | /** |
35 | /** |
Line 48... | Line 47... | ||
48 | * generic functions to the driver for grabbing and releasing references for |
47 | * generic functions to the driver for grabbing and releasing references for |
49 | * abstract power domains. It then maps those to the actual power wells |
48 | * abstract power domains. It then maps those to the actual power wells |
50 | * present for a given platform. |
49 | * present for a given platform. |
51 | */ |
50 | */ |
Line -... | Line 51... | ||
- | 51 | ||
52 | 52 | #define GEN9_ENABLE_DC5(dev) 0 |
|
Line 53... | Line 53... | ||
53 | static struct i915_power_domains *hsw_pwr; |
53 | #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) |
54 | 54 | ||
55 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
55 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
56 | for (i = 0; \ |
56 | for (i = 0; \ |
Line 63... | Line 63... | ||
63 | for (i = (power_domains)->power_well_count - 1; \ |
63 | for (i = (power_domains)->power_well_count - 1; \ |
64 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
64 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
65 | i--) \ |
65 | i--) \ |
66 | if ((power_well)->domains & (domain_mask)) |
66 | if ((power_well)->domains & (domain_mask)) |
Line -... | Line 67... | ||
- | 67 | ||
- | 68 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
|
- | 69 | int power_well_id); |
|
- | 70 | ||
- | 71 | static void intel_power_well_enable(struct drm_i915_private *dev_priv, |
|
- | 72 | struct i915_power_well *power_well) |
|
- | 73 | { |
|
- | 74 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
|
- | 75 | power_well->ops->enable(dev_priv, power_well); |
|
- | 76 | power_well->hw_enabled = true; |
|
- | 77 | } |
|
- | 78 | ||
- | 79 | static void intel_power_well_disable(struct drm_i915_private *dev_priv, |
|
- | 80 | struct i915_power_well *power_well) |
|
- | 81 | { |
|
- | 82 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
|
- | 83 | power_well->hw_enabled = false; |
|
- | 84 | power_well->ops->disable(dev_priv, power_well); |
|
- | 85 | } |
|
67 | 86 | ||
68 | /* |
87 | /* |
69 | * We should only use the power well if we explicitly asked the hardware to |
88 | * We should only use the power well if we explicitly asked the hardware to |
70 | * enable it, so check if it's enabled and also check if we've requested it to |
89 | * enable it, so check if it's enabled and also check if we've requested it to |
71 | * be enabled. |
90 | * be enabled. |
Line 116... | Line 135... | ||
116 | 135 | ||
117 | return is_enabled; |
136 | return is_enabled; |
Line 118... | Line 137... | ||
118 | } |
137 | } |
119 | 138 | ||
120 | /** |
139 | /** |
121 | * intel_display_power_is_enabled - unlocked check for a power domain |
140 | * intel_display_power_is_enabled - check for a power domain |
122 | * @dev_priv: i915 device instance |
141 | * @dev_priv: i915 device instance |
123 | * @domain: power domain to check |
142 | * @domain: power domain to check |
124 | * |
143 | * |
Line 195... | Line 214... | ||
195 | */ |
214 | */ |
196 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
215 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
197 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
216 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
198 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
217 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
Line 199... | Line 218... | ||
199 | 218 | ||
200 | if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) |
219 | if (IS_BROADWELL(dev)) |
- | 220 | gen8_irq_power_well_post_enable(dev_priv, |
|
- | 221 | 1 << PIPE_C | 1 << PIPE_B); |
|
- | 222 | } |
|
- | 223 | ||
- | 224 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
|
- | 225 | struct i915_power_well *power_well) |
|
- | 226 | { |
|
- | 227 | struct drm_device *dev = dev_priv->dev; |
|
- | 228 | ||
- | 229 | /* |
|
- | 230 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
|
- | 231 | * we'll get unclaimed register interrupts. This stops after we write |
|
- | 232 | * anything to the VGA MSR register. The vgacon module uses this |
|
- | 233 | * register all the time, so if we unbind our driver and, as a |
|
- | 234 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
|
- | 235 | * console_unlock(). So make here we touch the VGA MSR register, making |
|
- | 236 | * sure vgacon can keep working normally without triggering interrupts |
|
- | 237 | * and error messages. |
|
- | 238 | */ |
|
- | 239 | if (power_well->data == SKL_DISP_PW_2) { |
|
- | 240 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
|
- | 241 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
|
- | 242 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
|
- | 243 | ||
- | 244 | gen8_irq_power_well_post_enable(dev_priv, |
|
- | 245 | 1 << PIPE_C | 1 << PIPE_B); |
|
- | 246 | } |
|
- | 247 | ||
- | 248 | if (power_well->data == SKL_DISP_PW_1) { |
|
- | 249 | if (!dev_priv->power_domains.initializing) |
|
- | 250 | intel_prepare_ddi(dev); |
|
- | 251 | gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); |
|
201 | gen8_irq_power_well_post_enable(dev_priv); |
252 | } |
Line 202... | Line 253... | ||
202 | } |
253 | } |
203 | 254 | ||
204 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
255 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
Line 231... | Line 282... | ||
231 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
282 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
232 | } |
283 | } |
233 | } |
284 | } |
234 | } |
285 | } |
Line -... | Line 286... | ||
- | 286 | ||
- | 287 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
|
- | 288 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
|
- | 289 | BIT(POWER_DOMAIN_PIPE_B) | \ |
|
- | 290 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
|
- | 291 | BIT(POWER_DOMAIN_PIPE_C) | \ |
|
- | 292 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
|
- | 293 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
|
- | 294 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
|
- | 295 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
|
- | 296 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
|
- | 297 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
|
- | 298 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
|
- | 299 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
|
- | 300 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
|
- | 301 | BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ |
|
- | 302 | BIT(POWER_DOMAIN_AUX_B) | \ |
|
- | 303 | BIT(POWER_DOMAIN_AUX_C) | \ |
|
- | 304 | BIT(POWER_DOMAIN_AUX_D) | \ |
|
- | 305 | BIT(POWER_DOMAIN_AUDIO) | \ |
|
- | 306 | BIT(POWER_DOMAIN_VGA) | \ |
|
- | 307 | BIT(POWER_DOMAIN_INIT)) |
|
- | 308 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ |
|
- | 309 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
|
- | 310 | BIT(POWER_DOMAIN_PLLS) | \ |
|
- | 311 | BIT(POWER_DOMAIN_PIPE_A) | \ |
|
- | 312 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
|
- | 313 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ |
|
- | 314 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
|
- | 315 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
|
- | 316 | BIT(POWER_DOMAIN_AUX_A) | \ |
|
- | 317 | BIT(POWER_DOMAIN_INIT)) |
|
- | 318 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ |
|
- | 319 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
|
- | 320 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
|
- | 321 | BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ |
|
- | 322 | BIT(POWER_DOMAIN_INIT)) |
|
- | 323 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ |
|
- | 324 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
|
- | 325 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
|
- | 326 | BIT(POWER_DOMAIN_INIT)) |
|
- | 327 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ |
|
- | 328 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
|
- | 329 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
|
- | 330 | BIT(POWER_DOMAIN_INIT)) |
|
- | 331 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ |
|
- | 332 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
|
- | 333 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
|
- | 334 | BIT(POWER_DOMAIN_INIT)) |
|
- | 335 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ |
|
- | 336 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
|
- | 337 | BIT(POWER_DOMAIN_PLLS) | \ |
|
- | 338 | BIT(POWER_DOMAIN_INIT)) |
|
- | 339 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
|
- | 340 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
|
- | 341 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
|
- | 342 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ |
|
- | 343 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ |
|
- | 344 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ |
|
- | 345 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ |
|
- | 346 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ |
|
- | 347 | BIT(POWER_DOMAIN_INIT)) |
|
- | 348 | ||
- | 349 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
|
- | 350 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
|
- | 351 | BIT(POWER_DOMAIN_PIPE_B) | \ |
|
- | 352 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
|
- | 353 | BIT(POWER_DOMAIN_PIPE_C) | \ |
|
- | 354 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
|
- | 355 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
|
- | 356 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
|
- | 357 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
|
- | 358 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
|
- | 359 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
|
- | 360 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
|
- | 361 | BIT(POWER_DOMAIN_AUX_B) | \ |
|
- | 362 | BIT(POWER_DOMAIN_AUX_C) | \ |
|
- | 363 | BIT(POWER_DOMAIN_AUDIO) | \ |
|
- | 364 | BIT(POWER_DOMAIN_VGA) | \ |
|
- | 365 | BIT(POWER_DOMAIN_GMBUS) | \ |
|
- | 366 | BIT(POWER_DOMAIN_INIT)) |
|
- | 367 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ |
|
- | 368 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
|
- | 369 | BIT(POWER_DOMAIN_PIPE_A) | \ |
|
- | 370 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
|
- | 371 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ |
|
- | 372 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
|
- | 373 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
|
- | 374 | BIT(POWER_DOMAIN_AUX_A) | \ |
|
- | 375 | BIT(POWER_DOMAIN_PLLS) | \ |
|
- | 376 | BIT(POWER_DOMAIN_INIT)) |
|
- | 377 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
|
- | 378 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
|
- | 379 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ |
|
- | 380 | BIT(POWER_DOMAIN_INIT)) |
|
- | 381 | ||
- | 382 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
|
- | 383 | { |
|
- | 384 | struct drm_device *dev = dev_priv->dev; |
|
- | 385 | ||
- | 386 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); |
|
- | 387 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
|
- | 388 | "DC9 already programmed to be enabled.\n"); |
|
- | 389 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
|
- | 390 | "DC5 still not disabled to enable DC9.\n"); |
|
- | 391 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); |
|
- | 392 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); |
|
- | 393 | ||
- | 394 | /* |
|
- | 395 | * TODO: check for the following to verify the conditions to enter DC9 |
|
- | 396 | * state are satisfied: |
|
- | 397 | * 1] Check relevant display engine registers to verify if mode set |
|
- | 398 | * disable sequence was followed. |
|
- | 399 | * 2] Check if display uninitialize sequence is initialized. |
|
- | 400 | */ |
|
- | 401 | } |
|
- | 402 | ||
- | 403 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) |
|
- | 404 | { |
|
- | 405 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); |
|
- | 406 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
|
- | 407 | "DC9 already programmed to be disabled.\n"); |
|
- | 408 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
|
- | 409 | "DC5 still not disabled.\n"); |
|
- | 410 | ||
- | 411 | /* |
|
- | 412 | * TODO: check for the following to verify DC9 state was indeed |
|
- | 413 | * entered before programming to disable it: |
|
- | 414 | * 1] Check relevant display engine registers to verify if mode |
|
- | 415 | * set disable sequence was followed. |
|
- | 416 | * 2] Check if display uninitialize sequence is initialized. |
|
- | 417 | */ |
|
- | 418 | } |
|
- | 419 | ||
- | 420 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) |
|
- | 421 | { |
|
- | 422 | uint32_t val; |
|
- | 423 | ||
- | 424 | assert_can_enable_dc9(dev_priv); |
|
- | 425 | ||
- | 426 | DRM_DEBUG_KMS("Enabling DC9\n"); |
|
- | 427 | ||
- | 428 | val = I915_READ(DC_STATE_EN); |
|
- | 429 | val |= DC_STATE_EN_DC9; |
|
- | 430 | I915_WRITE(DC_STATE_EN, val); |
|
- | 431 | POSTING_READ(DC_STATE_EN); |
|
- | 432 | } |
|
- | 433 | ||
- | 434 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) |
|
- | 435 | { |
|
- | 436 | uint32_t val; |
|
- | 437 | ||
- | 438 | assert_can_disable_dc9(dev_priv); |
|
- | 439 | ||
- | 440 | DRM_DEBUG_KMS("Disabling DC9\n"); |
|
- | 441 | ||
- | 442 | val = I915_READ(DC_STATE_EN); |
|
- | 443 | val &= ~DC_STATE_EN_DC9; |
|
- | 444 | I915_WRITE(DC_STATE_EN, val); |
|
- | 445 | POSTING_READ(DC_STATE_EN); |
|
- | 446 | } |
|
- | 447 | ||
- | 448 | static void gen9_set_dc_state_debugmask_memory_up( |
|
- | 449 | struct drm_i915_private *dev_priv) |
|
- | 450 | { |
|
- | 451 | uint32_t val; |
|
- | 452 | ||
- | 453 | /* The below bit doesn't need to be cleared ever afterwards */ |
|
- | 454 | val = I915_READ(DC_STATE_DEBUG); |
|
- | 455 | if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { |
|
- | 456 | val |= DC_STATE_DEBUG_MASK_MEMORY_UP; |
|
- | 457 | I915_WRITE(DC_STATE_DEBUG, val); |
|
- | 458 | POSTING_READ(DC_STATE_DEBUG); |
|
- | 459 | } |
|
- | 460 | } |
|
- | 461 | ||
- | 462 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
|
- | 463 | { |
|
- | 464 | struct drm_device *dev = dev_priv->dev; |
|
- | 465 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
|
- | 466 | SKL_DISP_PW_2); |
|
- | 467 | ||
- | 468 | WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); |
|
- | 469 | WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
|
- | 470 | WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); |
|
- | 471 | ||
- | 472 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), |
|
- | 473 | "DC5 already programmed to be enabled.\n"); |
|
- | 474 | WARN_ONCE(dev_priv->pm.suspended, |
|
- | 475 | "DC5 cannot be enabled, if platform is runtime-suspended.\n"); |
|
- | 476 | ||
- | 477 | assert_csr_loaded(dev_priv); |
|
- | 478 | } |
|
- | 479 | ||
- | 480 | static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) |
|
- | 481 | { |
|
- | 482 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
|
- | 483 | SKL_DISP_PW_2); |
|
- | 484 | /* |
|
- | 485 | * During initialization, the firmware may not be loaded yet. |
|
- | 486 | * We still want to make sure that the DC enabling flag is cleared. |
|
- | 487 | */ |
|
- | 488 | if (dev_priv->power_domains.initializing) |
|
- | 489 | return; |
|
- | 490 | ||
- | 491 | WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); |
|
- | 492 | WARN_ONCE(dev_priv->pm.suspended, |
|
- | 493 | "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); |
|
- | 494 | } |
|
- | 495 | ||
- | 496 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) |
|
- | 497 | { |
|
- | 498 | uint32_t val; |
|
- | 499 | ||
- | 500 | assert_can_enable_dc5(dev_priv); |
|
- | 501 | ||
- | 502 | DRM_DEBUG_KMS("Enabling DC5\n"); |
|
- | 503 | ||
- | 504 | gen9_set_dc_state_debugmask_memory_up(dev_priv); |
|
- | 505 | ||
- | 506 | val = I915_READ(DC_STATE_EN); |
|
- | 507 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; |
|
- | 508 | val |= DC_STATE_EN_UPTO_DC5; |
|
- | 509 | I915_WRITE(DC_STATE_EN, val); |
|
- | 510 | POSTING_READ(DC_STATE_EN); |
|
- | 511 | } |
|
- | 512 | ||
- | 513 | static void gen9_disable_dc5(struct drm_i915_private *dev_priv) |
|
- | 514 | { |
|
- | 515 | uint32_t val; |
|
- | 516 | ||
- | 517 | assert_can_disable_dc5(dev_priv); |
|
- | 518 | ||
- | 519 | DRM_DEBUG_KMS("Disabling DC5\n"); |
|
- | 520 | ||
- | 521 | val = I915_READ(DC_STATE_EN); |
|
- | 522 | val &= ~DC_STATE_EN_UPTO_DC5; |
|
- | 523 | I915_WRITE(DC_STATE_EN, val); |
|
- | 524 | POSTING_READ(DC_STATE_EN); |
|
- | 525 | } |
|
- | 526 | ||
- | 527 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
|
- | 528 | { |
|
- | 529 | struct drm_device *dev = dev_priv->dev; |
|
- | 530 | ||
- | 531 | WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); |
|
- | 532 | WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
|
- | 533 | WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
|
- | 534 | "Backlight is not disabled.\n"); |
|
- | 535 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
|
- | 536 | "DC6 already programmed to be enabled.\n"); |
|
- | 537 | ||
- | 538 | assert_csr_loaded(dev_priv); |
|
- | 539 | } |
|
- | 540 | ||
- | 541 | static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) |
|
- | 542 | { |
|
- | 543 | /* |
|
- | 544 | * During initialization, the firmware may not be loaded yet. |
|
- | 545 | * We still want to make sure that the DC enabling flag is cleared. |
|
- | 546 | */ |
|
- | 547 | if (dev_priv->power_domains.initializing) |
|
- | 548 | return; |
|
- | 549 | ||
- | 550 | assert_csr_loaded(dev_priv); |
|
- | 551 | WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
|
- | 552 | "DC6 already programmed to be disabled.\n"); |
|
- | 553 | } |
|
- | 554 | ||
- | 555 | static void skl_enable_dc6(struct drm_i915_private *dev_priv) |
|
- | 556 | { |
|
- | 557 | uint32_t val; |
|
- | 558 | ||
- | 559 | assert_can_enable_dc6(dev_priv); |
|
- | 560 | ||
- | 561 | DRM_DEBUG_KMS("Enabling DC6\n"); |
|
- | 562 | ||
- | 563 | gen9_set_dc_state_debugmask_memory_up(dev_priv); |
|
- | 564 | ||
- | 565 | val = I915_READ(DC_STATE_EN); |
|
- | 566 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; |
|
- | 567 | val |= DC_STATE_EN_UPTO_DC6; |
|
- | 568 | I915_WRITE(DC_STATE_EN, val); |
|
- | 569 | POSTING_READ(DC_STATE_EN); |
|
- | 570 | } |
|
- | 571 | ||
- | 572 | static void skl_disable_dc6(struct drm_i915_private *dev_priv) |
|
- | 573 | { |
|
- | 574 | uint32_t val; |
|
- | 575 | ||
- | 576 | assert_can_disable_dc6(dev_priv); |
|
- | 577 | ||
- | 578 | DRM_DEBUG_KMS("Disabling DC6\n"); |
|
- | 579 | ||
- | 580 | val = I915_READ(DC_STATE_EN); |
|
- | 581 | val &= ~DC_STATE_EN_UPTO_DC6; |
|
- | 582 | I915_WRITE(DC_STATE_EN, val); |
|
- | 583 | POSTING_READ(DC_STATE_EN); |
|
- | 584 | } |
|
- | 585 | ||
- | 586 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
|
- | 587 | struct i915_power_well *power_well, bool enable) |
|
- | 588 | { |
|
- | 589 | struct drm_device *dev = dev_priv->dev; |
|
- | 590 | uint32_t tmp, fuse_status; |
|
- | 591 | uint32_t req_mask, state_mask; |
|
- | 592 | bool is_enabled, enable_requested, check_fuse_status = false; |
|
- | 593 | ||
- | 594 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
|
- | 595 | fuse_status = I915_READ(SKL_FUSE_STATUS); |
|
- | 596 | ||
- | 597 | switch (power_well->data) { |
|
- | 598 | case SKL_DISP_PW_1: |
|
- | 599 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
|
- | 600 | SKL_FUSE_PG0_DIST_STATUS), 1)) { |
|
- | 601 | DRM_ERROR("PG0 not enabled\n"); |
|
- | 602 | return; |
|
- | 603 | } |
|
- | 604 | break; |
|
- | 605 | case SKL_DISP_PW_2: |
|
- | 606 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { |
|
- | 607 | DRM_ERROR("PG1 in disabled state\n"); |
|
- | 608 | return; |
|
- | 609 | } |
|
- | 610 | break; |
|
- | 611 | case SKL_DISP_PW_DDI_A_E: |
|
- | 612 | case SKL_DISP_PW_DDI_B: |
|
- | 613 | case SKL_DISP_PW_DDI_C: |
|
- | 614 | case SKL_DISP_PW_DDI_D: |
|
- | 615 | case SKL_DISP_PW_MISC_IO: |
|
- | 616 | break; |
|
- | 617 | default: |
|
- | 618 | WARN(1, "Unknown power well %lu\n", power_well->data); |
|
- | 619 | return; |
|
- | 620 | } |
|
- | 621 | ||
- | 622 | req_mask = SKL_POWER_WELL_REQ(power_well->data); |
|
- | 623 | enable_requested = tmp & req_mask; |
|
- | 624 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
|
- | 625 | is_enabled = tmp & state_mask; |
|
- | 626 | ||
- | 627 | if (enable) { |
|
- | 628 | if (!enable_requested) { |
|
- | 629 | WARN((tmp & state_mask) && |
|
- | 630 | !I915_READ(HSW_PWR_WELL_BIOS), |
|
- | 631 | "Invalid for power well status to be enabled, unless done by the BIOS, \ |
|
- | 632 | when request is to disable!\n"); |
|
- | 633 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
|
- | 634 | power_well->data == SKL_DISP_PW_2) { |
|
- | 635 | if (SKL_ENABLE_DC6(dev)) { |
|
- | 636 | skl_disable_dc6(dev_priv); |
|
- | 637 | /* |
|
- | 638 | * DDI buffer programming unnecessary during driver-load/resume |
|
- | 639 | * as it's already done during modeset initialization then. |
|
- | 640 | * It's also invalid here as encoder list is still uninitialized. |
|
- | 641 | */ |
|
- | 642 | if (!dev_priv->power_domains.initializing) |
|
- | 643 | intel_prepare_ddi(dev); |
|
- | 644 | } else { |
|
- | 645 | gen9_disable_dc5(dev_priv); |
|
- | 646 | } |
|
- | 647 | } |
|
- | 648 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
|
- | 649 | } |
|
- | 650 | ||
- | 651 | if (!is_enabled) { |
|
- | 652 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
|
- | 653 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
|
- | 654 | state_mask), 1)) |
|
- | 655 | DRM_ERROR("%s enable timeout\n", |
|
- | 656 | power_well->name); |
|
- | 657 | check_fuse_status = true; |
|
- | 658 | } |
|
- | 659 | } else { |
|
- | 660 | if (enable_requested) { |
|
- | 661 | if (IS_SKYLAKE(dev) && |
|
- | 662 | (power_well->data == SKL_DISP_PW_1) && |
|
- | 663 | (intel_csr_load_status_get(dev_priv) == FW_LOADED)) |
|
- | 664 | DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); |
|
- | 665 | else { |
|
- | 666 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
|
- | 667 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
|
- | 668 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); |
|
- | 669 | } |
|
- | 670 | ||
- | 671 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
|
- | 672 | power_well->data == SKL_DISP_PW_2) { |
|
- | 673 | enum csr_state state; |
|
- | 674 | /* TODO: wait for a completion event or |
|
- | 675 | * similar here instead of busy |
|
- | 676 | * waiting using wait_for function. |
|
- | 677 | */ |
|
- | 678 | wait_for((state = intel_csr_load_status_get(dev_priv)) != |
|
- | 679 | FW_UNINITIALIZED, 1000); |
|
- | 680 | if (state != FW_LOADED) |
|
- | 681 | DRM_DEBUG("CSR firmware not ready (%d)\n", |
|
- | 682 | state); |
|
- | 683 | else |
|
- | 684 | if (SKL_ENABLE_DC6(dev)) |
|
- | 685 | skl_enable_dc6(dev_priv); |
|
- | 686 | else |
|
- | 687 | gen9_enable_dc5(dev_priv); |
|
- | 688 | } |
|
- | 689 | } |
|
- | 690 | } |
|
- | 691 | ||
- | 692 | if (check_fuse_status) { |
|
- | 693 | if (power_well->data == SKL_DISP_PW_1) { |
|
- | 694 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
|
- | 695 | SKL_FUSE_PG1_DIST_STATUS), 1)) |
|
- | 696 | DRM_ERROR("PG1 distributing status timeout\n"); |
|
- | 697 | } else if (power_well->data == SKL_DISP_PW_2) { |
|
- | 698 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
|
- | 699 | SKL_FUSE_PG2_DIST_STATUS), 1)) |
|
- | 700 | DRM_ERROR("PG2 distributing status timeout\n"); |
|
- | 701 | } |
|
- | 702 | } |
|
- | 703 | ||
- | 704 | if (enable && !is_enabled) |
|
- | 705 | skl_power_well_post_enable(dev_priv, power_well); |
|
- | 706 | } |
|
235 | 707 | ||
236 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
708 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
237 | struct i915_power_well *power_well) |
709 | struct i915_power_well *power_well) |
238 | { |
710 | { |
Line 256... | Line 728... | ||
256 | struct i915_power_well *power_well) |
728 | struct i915_power_well *power_well) |
257 | { |
729 | { |
258 | hsw_set_power_well(dev_priv, power_well, false); |
730 | hsw_set_power_well(dev_priv, power_well, false); |
259 | } |
731 | } |
Line -... | Line 732... | ||
- | 732 | ||
- | 733 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
|
- | 734 | struct i915_power_well *power_well) |
|
- | 735 | { |
|
- | 736 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | |
|
- | 737 | SKL_POWER_WELL_STATE(power_well->data); |
|
- | 738 | ||
- | 739 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; |
|
- | 740 | } |
|
- | 741 | ||
- | 742 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, |
|
- | 743 | struct i915_power_well *power_well) |
|
- | 744 | { |
|
- | 745 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); |
|
- | 746 | ||
- | 747 | /* Clear any request made by BIOS as driver is taking over */ |
|
- | 748 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
|
- | 749 | } |
|
- | 750 | ||
- | 751 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, |
|
- | 752 | struct i915_power_well *power_well) |
|
- | 753 | { |
|
- | 754 | skl_set_power_well(dev_priv, power_well, true); |
|
- | 755 | } |
|
- | 756 | ||
- | 757 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, |
|
- | 758 | struct i915_power_well *power_well) |
|
- | 759 | { |
|
- | 760 | skl_set_power_well(dev_priv, power_well, false); |
|
- | 761 | } |
|
260 | 762 | ||
261 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
763 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
262 | struct i915_power_well *power_well) |
764 | struct i915_power_well *power_well) |
263 | { |
765 | { |
Line 293... | Line 795... | ||
293 | ctrl &= ~mask; |
795 | ctrl &= ~mask; |
294 | ctrl |= state; |
796 | ctrl |= state; |
295 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
797 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
Line 296... | Line 798... | ||
296 | 798 | ||
297 | if (wait_for(COND, 100)) |
799 | if (wait_for(COND, 100)) |
298 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
800 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
299 | state, |
801 | state, |
Line 300... | Line 802... | ||
300 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
802 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
Line 357... | Line 859... | ||
357 | mutex_unlock(&dev_priv->rps.hw_lock); |
859 | mutex_unlock(&dev_priv->rps.hw_lock); |
Line 358... | Line 860... | ||
358 | 860 | ||
359 | return enabled; |
861 | return enabled; |
Line 360... | Line 862... | ||
360 | } |
862 | } |
361 | - | ||
362 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
863 | |
363 | struct i915_power_well *power_well) |
864 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
Line -... | Line 865... | ||
- | 865 | { |
|
- | 866 | enum pipe pipe; |
|
- | 867 | ||
- | 868 | /* |
|
- | 869 | * Enable the CRI clock source so we can get at the |
|
- | 870 | * display and the reference clock for VGA |
|
- | 871 | * hotplug / manual detection. Supposedly DSI also |
|
- | 872 | * needs the ref clock up and running. |
|
364 | { |
873 | * |
- | 874 | * CHV DPLL B/C have some issues if VGA mode is enabled. |
|
- | 875 | */ |
|
- | 876 | for_each_pipe(dev_priv->dev, pipe) { |
|
- | 877 | u32 val = I915_READ(DPLL(pipe)); |
|
- | 878 | ||
- | 879 | val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
|
- | 880 | if (pipe != PIPE_A) |
|
- | 881 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
Line 365... | Line 882... | ||
365 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
882 | |
366 | 883 | I915_WRITE(DPLL(pipe), val); |
|
367 | vlv_set_power_well(dev_priv, power_well, true); |
884 | } |
Line 375... | Line 892... | ||
375 | * part of the HW/SW state that will be inited anyway explicitly. |
892 | * part of the HW/SW state that will be inited anyway explicitly. |
376 | */ |
893 | */ |
377 | if (dev_priv->power_domains.initializing) |
894 | if (dev_priv->power_domains.initializing) |
378 | return; |
895 | return; |
Line 379... | Line 896... | ||
379 | 896 | ||
Line 380... | Line 897... | ||
380 | intel_hpd_init(dev_priv); |
897 | // intel_hpd_init(dev_priv); |
381 | 898 | ||
Line -... | Line 899... | ||
- | 899 | i915_redisable_vga_power_on(dev_priv->dev); |
|
- | 900 | } |
|
- | 901 | ||
- | 902 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
|
- | 903 | { |
|
- | 904 | spin_lock_irq(&dev_priv->irq_lock); |
|
- | 905 | valleyview_disable_display_irqs(dev_priv); |
|
- | 906 | spin_unlock_irq(&dev_priv->irq_lock); |
|
- | 907 | ||
- | 908 | vlv_power_sequencer_reset(dev_priv); |
|
- | 909 | } |
|
- | 910 | ||
- | 911 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
|
- | 912 | struct i915_power_well *power_well) |
|
- | 913 | { |
|
- | 914 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
|
- | 915 | ||
- | 916 | vlv_set_power_well(dev_priv, power_well, true); |
|
- | 917 | ||
382 | i915_redisable_vga_power_on(dev_priv->dev); |
918 | vlv_display_power_well_init(dev_priv); |
383 | } |
919 | } |
384 | 920 | ||
385 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
921 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
Line 386... | Line -... | ||
386 | struct i915_power_well *power_well) |
- | |
387 | { |
922 | struct i915_power_well *power_well) |
388 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
- | |
Line 389... | Line 923... | ||
389 | 923 | { |
|
390 | spin_lock_irq(&dev_priv->irq_lock); |
- | |
391 | valleyview_disable_display_irqs(dev_priv); |
- | |
392 | spin_unlock_irq(&dev_priv->irq_lock); |
924 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
Line 393... | Line 925... | ||
393 | 925 | ||
394 | vlv_set_power_well(dev_priv, power_well, false); |
926 | vlv_display_power_well_deinit(dev_priv); |
395 | 927 | ||
396 | vlv_power_sequencer_reset(dev_priv); |
928 | vlv_set_power_well(dev_priv, power_well, false); |
Line 397... | Line -... | ||
397 | } |
- | |
398 | 929 | } |
|
399 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
- | |
400 | struct i915_power_well *power_well) |
- | |
401 | { |
- | |
402 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
- | |
403 | - | ||
404 | /* |
930 | |
Line 405... | Line 931... | ||
405 | * Enable the CRI clock source so we can get at the |
931 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
Line 406... | Line 932... | ||
406 | * display and the reference clock for VGA |
932 | struct i915_power_well *power_well) |
Line 440... | Line 966... | ||
440 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
966 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
Line 441... | Line 967... | ||
441 | 967 | ||
442 | vlv_set_power_well(dev_priv, power_well, false); |
968 | vlv_set_power_well(dev_priv, power_well, false); |
Line -... | Line 969... | ||
- | 969 | } |
|
- | 970 | ||
- | 971 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
|
- | 972 | ||
- | 973 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
|
- | 974 | int power_well_id) |
|
- | 975 | { |
|
- | 976 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
|
- | 977 | struct i915_power_well *power_well; |
|
- | 978 | int i; |
|
- | 979 | ||
- | 980 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
|
- | 981 | if (power_well->data == power_well_id) |
|
- | 982 | return power_well; |
|
- | 983 | } |
|
- | 984 | ||
- | 985 | return NULL; |
|
- | 986 | } |
|
- | 987 | ||
- | 988 | #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) |
|
- | 989 | ||
- | 990 | static void assert_chv_phy_status(struct drm_i915_private *dev_priv) |
|
- | 991 | { |
|
- | 992 | struct i915_power_well *cmn_bc = |
|
- | 993 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
|
- | 994 | struct i915_power_well *cmn_d = |
|
- | 995 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); |
|
- | 996 | u32 phy_control = dev_priv->chv_phy_control; |
|
- | 997 | u32 phy_status = 0; |
|
- | 998 | u32 phy_status_mask = 0xffffffff; |
|
- | 999 | u32 tmp; |
|
- | 1000 | ||
- | 1001 | /* |
|
- | 1002 | * The BIOS can leave the PHY is some weird state |
|
- | 1003 | * where it doesn't fully power down some parts. |
|
- | 1004 | * Disable the asserts until the PHY has been fully |
|
- | 1005 | * reset (ie. the power well has been disabled at |
|
- | 1006 | * least once). |
|
- | 1007 | */ |
|
- | 1008 | if (!dev_priv->chv_phy_assert[DPIO_PHY0]) |
|
- | 1009 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | |
|
- | 1010 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | |
|
- | 1011 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | |
|
- | 1012 | PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | |
|
- | 1013 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | |
|
- | 1014 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); |
|
- | 1015 | ||
- | 1016 | if (!dev_priv->chv_phy_assert[DPIO_PHY1]) |
|
- | 1017 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | |
|
- | 1018 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | |
|
- | 1019 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); |
|
- | 1020 | ||
- | 1021 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
|
- | 1022 | phy_status |= PHY_POWERGOOD(DPIO_PHY0); |
|
- | 1023 | ||
- | 1024 | /* this assumes override is only used to enable lanes */ |
|
- | 1025 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) |
|
- | 1026 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); |
|
- | 1027 | ||
- | 1028 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) |
|
- | 1029 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); |
|
- | 1030 | ||
- | 1031 | /* CL1 is on whenever anything is on in either channel */ |
|
- | 1032 | if (BITS_SET(phy_control, |
|
- | 1033 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | |
|
- | 1034 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) |
|
- | 1035 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); |
|
- | 1036 | ||
- | 1037 | /* |
|
- | 1038 | * The DPLLB check accounts for the pipe B + port A usage |
|
- | 1039 | * with CL2 powered up but all the lanes in the second channel |
|
- | 1040 | * powered down. |
|
- | 1041 | */ |
|
- | 1042 | if (BITS_SET(phy_control, |
|
- | 1043 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && |
|
- | 1044 | (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) |
|
- | 1045 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); |
|
- | 1046 | ||
- | 1047 | if (BITS_SET(phy_control, |
|
- | 1048 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) |
|
- | 1049 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); |
|
- | 1050 | if (BITS_SET(phy_control, |
|
- | 1051 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) |
|
- | 1052 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); |
|
- | 1053 | ||
- | 1054 | if (BITS_SET(phy_control, |
|
- | 1055 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) |
|
- | 1056 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); |
|
- | 1057 | if (BITS_SET(phy_control, |
|
- | 1058 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) |
|
- | 1059 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); |
|
- | 1060 | } |
|
- | 1061 | ||
- | 1062 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { |
|
- | 1063 | phy_status |= PHY_POWERGOOD(DPIO_PHY1); |
|
- | 1064 | ||
- | 1065 | /* this assumes override is only used to enable lanes */ |
|
- | 1066 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) |
|
- | 1067 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); |
|
- | 1068 | ||
- | 1069 | if (BITS_SET(phy_control, |
|
- | 1070 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) |
|
- | 1071 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); |
|
- | 1072 | ||
- | 1073 | if (BITS_SET(phy_control, |
|
- | 1074 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) |
|
- | 1075 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); |
|
- | 1076 | if (BITS_SET(phy_control, |
|
- | 1077 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) |
|
- | 1078 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); |
|
- | 1079 | } |
|
- | 1080 | ||
- | 1081 | phy_status &= phy_status_mask; |
|
- | 1082 | ||
- | 1083 | /* |
|
- | 1084 | * The PHY may be busy with some initial calibration and whatnot, |
|
- | 1085 | * so the power state can take a while to actually change. |
|
- | 1086 | */ |
|
- | 1087 | if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) |
|
- | 1088 | WARN(phy_status != tmp, |
|
- | 1089 | "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", |
|
- | 1090 | tmp, phy_status, dev_priv->chv_phy_control); |
|
- | 1091 | } |
|
- | 1092 | ||
443 | } |
1093 | #undef BITS_SET |
444 | 1094 | ||
445 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
1095 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
446 | struct i915_power_well *power_well) |
1096 | struct i915_power_well *power_well) |
- | 1097 | { |
|
- | 1098 | enum dpio_phy phy; |
|
Line 447... | Line 1099... | ||
447 | { |
1099 | enum pipe pipe; |
448 | enum dpio_phy phy; |
1100 | uint32_t tmp; |
Line 449... | Line -... | ||
449 | - | ||
450 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
- | |
451 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
- | |
452 | - | ||
453 | /* |
- | |
454 | * Enable the CRI clock source so we can get at the |
1101 | |
- | 1102 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
|
455 | * display and the reference clock for VGA |
1103 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
456 | * hotplug / manual detection. |
- | |
457 | */ |
- | |
458 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
- | |
459 | phy = DPIO_PHY0; |
- | |
460 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
1104 | |
- | 1105 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
|
461 | DPLL_REFA_CLK_ENABLE_VLV); |
1106 | pipe = PIPE_A; |
462 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
- | |
463 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
- | |
464 | } else { |
1107 | phy = DPIO_PHY0; |
- | 1108 | } else { |
|
- | 1109 | pipe = PIPE_C; |
|
465 | phy = DPIO_PHY1; |
1110 | phy = DPIO_PHY1; |
466 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | |
1111 | } |
Line 467... | Line 1112... | ||
467 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
1112 | |
468 | } |
1113 | /* since ref/cri clock was enabled */ |
469 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
1114 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
Line -... | Line 1115... | ||
- | 1115 | vlv_set_power_well(dev_priv, power_well, true); |
|
- | 1116 | ||
- | 1117 | /* Poll for phypwrgood signal */ |
|
- | 1118 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
|
- | 1119 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
|
- | 1120 | ||
- | 1121 | mutex_lock(&dev_priv->sb_lock); |
|
- | 1122 | ||
- | 1123 | /* Enable dynamic power down */ |
|
- | 1124 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); |
|
- | 1125 | tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | |
|
- | 1126 | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; |
|
- | 1127 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); |
|
- | 1128 | ||
- | 1129 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
|
- | 1130 | tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); |
|
- | 1131 | tmp |= DPIO_DYNPWRDOWNEN_CH1; |
|
- | 1132 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); |
|
- | 1133 | } else { |
|
- | 1134 | /* |
|
- | 1135 | * Force the non-existing CL2 off. BXT does this |
|
- | 1136 | * too, so maybe it saves some power even though |
|
- | 1137 | * CL2 doesn't exist? |
|
- | 1138 | */ |
|
- | 1139 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
|
- | 1140 | tmp |= DPIO_CL2_LDOFUSE_PWRENB; |
|
470 | vlv_set_power_well(dev_priv, power_well, true); |
1141 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); |
- | 1142 | } |
|
- | 1143 | ||
471 | 1144 | mutex_unlock(&dev_priv->sb_lock); |
|
- | 1145 | ||
- | 1146 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
|
472 | /* Poll for phypwrgood signal */ |
1147 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
Line 473... | Line 1148... | ||
473 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
1148 | |
474 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
1149 | DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", |
475 | 1150 | phy, dev_priv->chv_phy_control); |
|
Line 492... | Line 1167... | ||
492 | } else { |
1167 | } else { |
493 | phy = DPIO_PHY1; |
1168 | phy = DPIO_PHY1; |
494 | assert_pll_disabled(dev_priv, PIPE_C); |
1169 | assert_pll_disabled(dev_priv, PIPE_C); |
495 | } |
1170 | } |
Line 496... | Line 1171... | ||
496 | 1171 | ||
497 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & |
1172 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
Line 498... | Line 1173... | ||
498 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); |
1173 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
- | 1174 | ||
- | 1175 | vlv_set_power_well(dev_priv, power_well, false); |
|
- | 1176 | ||
- | 1177 | DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", |
|
- | 1178 | phy, dev_priv->chv_phy_control); |
|
- | 1179 | ||
- | 1180 | /* PHY is fully reset now, so we can enable the PHY state asserts */ |
|
- | 1181 | dev_priv->chv_phy_assert[phy] = true; |
|
- | 1182 | ||
- | 1183 | assert_chv_phy_status(dev_priv); |
|
- | 1184 | } |
|
- | 1185 | ||
- | 1186 | static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
|
- | 1187 | enum dpio_channel ch, bool override, unsigned int mask) |
|
- | 1188 | { |
|
- | 1189 | enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; |
|
- | 1190 | u32 reg, val, expected, actual; |
|
- | 1191 | ||
- | 1192 | /* |
|
- | 1193 | * The BIOS can leave the PHY is some weird state |
|
- | 1194 | * where it doesn't fully power down some parts. |
|
- | 1195 | * Disable the asserts until the PHY has been fully |
|
- | 1196 | * reset (ie. the power well has been disabled at |
|
- | 1197 | * least once). |
|
- | 1198 | */ |
|
- | 1199 | if (!dev_priv->chv_phy_assert[phy]) |
|
- | 1200 | return; |
|
- | 1201 | ||
- | 1202 | if (ch == DPIO_CH0) |
|
- | 1203 | reg = _CHV_CMN_DW0_CH0; |
|
- | 1204 | else |
|
- | 1205 | reg = _CHV_CMN_DW6_CH1; |
|
- | 1206 | ||
- | 1207 | mutex_lock(&dev_priv->sb_lock); |
|
- | 1208 | val = vlv_dpio_read(dev_priv, pipe, reg); |
|
- | 1209 | mutex_unlock(&dev_priv->sb_lock); |
|
- | 1210 | ||
- | 1211 | /* |
|
- | 1212 | * This assumes !override is only used when the port is disabled. |
|
- | 1213 | * All lanes should power down even without the override when |
|
- | 1214 | * the port is disabled. |
|
- | 1215 | */ |
|
- | 1216 | if (!override || mask == 0xf) { |
|
- | 1217 | expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; |
|
- | 1218 | /* |
|
- | 1219 | * If CH1 common lane is not active anymore |
|
- | 1220 | * (eg. for pipe B DPLL) the entire channel will |
|
- | 1221 | * shut down, which causes the common lane registers |
|
- | 1222 | * to read as 0. That means we can't actually check |
|
- | 1223 | * the lane power down status bits, but as the entire |
|
- | 1224 | * register reads as 0 it's a good indication that the |
|
- | 1225 | * channel is indeed entirely powered down. |
|
- | 1226 | */ |
|
- | 1227 | if (ch == DPIO_CH1 && val == 0) |
|
- | 1228 | expected = 0; |
|
- | 1229 | } else if (mask != 0x0) { |
|
- | 1230 | expected = DPIO_ANYDL_POWERDOWN; |
|
- | 1231 | } else { |
|
- | 1232 | expected = 0; |
|
- | 1233 | } |
|
- | 1234 | ||
- | 1235 | if (ch == DPIO_CH0) |
|
- | 1236 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; |
|
- | 1237 | else |
|
- | 1238 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; |
|
- | 1239 | actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; |
|
- | 1240 | ||
- | 1241 | WARN(actual != expected, |
|
- | 1242 | "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", |
|
- | 1243 | !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), |
|
- | 1244 | !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), |
|
- | 1245 | reg, val); |
|
- | 1246 | } |
|
- | 1247 | ||
- | 1248 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
|
- | 1249 | enum dpio_channel ch, bool override) |
|
- | 1250 | { |
|
- | 1251 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
|
- | 1252 | bool was_override; |
|
- | 1253 | ||
- | 1254 | mutex_lock(&power_domains->lock); |
|
- | 1255 | ||
- | 1256 | was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
|
- | 1257 | ||
- | 1258 | if (override == was_override) |
|
- | 1259 | goto out; |
|
- | 1260 | ||
- | 1261 | if (override) |
|
- | 1262 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
|
- | 1263 | else |
|
- | 1264 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
|
- | 1265 | ||
- | 1266 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
|
- | 1267 | ||
- | 1268 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", |
|
- | 1269 | phy, ch, dev_priv->chv_phy_control); |
|
- | 1270 | ||
- | 1271 | assert_chv_phy_status(dev_priv); |
|
- | 1272 | ||
- | 1273 | out: |
|
- | 1274 | mutex_unlock(&power_domains->lock); |
|
- | 1275 | ||
- | 1276 | return was_override; |
|
- | 1277 | } |
|
- | 1278 | ||
- | 1279 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
|
- | 1280 | bool override, unsigned int mask) |
|
- | 1281 | { |
|
- | 1282 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
|
- | 1283 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
|
- | 1284 | enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); |
|
- | 1285 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
|
- | 1286 | ||
- | 1287 | mutex_lock(&power_domains->lock); |
|
- | 1288 | ||
- | 1289 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); |
|
- | 1290 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); |
|
- | 1291 | ||
- | 1292 | if (override) |
|
- | 1293 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
|
- | 1294 | else |
|
- | 1295 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
|
- | 1296 | ||
- | 1297 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
|
- | 1298 | ||
- | 1299 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", |
|
- | 1300 | phy, ch, mask, dev_priv->chv_phy_control); |
|
- | 1301 | ||
- | 1302 | assert_chv_phy_status(dev_priv); |
|
- | 1303 | ||
- | 1304 | assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); |
|
499 | 1305 | ||
Line 500... | Line 1306... | ||
500 | vlv_set_power_well(dev_priv, power_well, false); |
1306 | mutex_unlock(&power_domains->lock); |
501 | } |
1307 | } |
502 | 1308 | ||
Line 551... | Line 1357... | ||
551 | ctrl &= ~DP_SSC_MASK(pipe); |
1357 | ctrl &= ~DP_SSC_MASK(pipe); |
552 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
1358 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
553 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
1359 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
Line 554... | Line 1360... | ||
554 | 1360 | ||
555 | if (wait_for(COND, 100)) |
1361 | if (wait_for(COND, 100)) |
556 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
1362 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
557 | state, |
1363 | state, |
Line 558... | Line 1364... | ||
558 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
1364 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
Line 564... | Line 1370... | ||
564 | } |
1370 | } |
Line 565... | Line 1371... | ||
565 | 1371 | ||
566 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
1372 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
567 | struct i915_power_well *power_well) |
1373 | struct i915_power_well *power_well) |
- | 1374 | { |
|
- | 1375 | WARN_ON_ONCE(power_well->data != PIPE_A); |
|
568 | { |
1376 | |
569 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
1377 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
Line 570... | Line 1378... | ||
570 | } |
1378 | } |
571 | 1379 | ||
572 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
1380 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
573 | struct i915_power_well *power_well) |
1381 | struct i915_power_well *power_well) |
574 | { |
- | |
575 | WARN_ON_ONCE(power_well->data != PIPE_A && |
- | |
Line 576... | Line 1382... | ||
576 | power_well->data != PIPE_B && |
1382 | { |
Line 577... | Line -... | ||
577 | power_well->data != PIPE_C); |
- | |
578 | - | ||
579 | chv_set_pipe_power_well(dev_priv, power_well, true); |
- | |
580 | - | ||
581 | if (power_well->data == PIPE_A) { |
- | |
582 | spin_lock_irq(&dev_priv->irq_lock); |
- | |
583 | valleyview_enable_display_irqs(dev_priv); |
- | |
584 | spin_unlock_irq(&dev_priv->irq_lock); |
- | |
585 | - | ||
586 | /* |
- | |
587 | * During driver initialization/resume we can avoid restoring the |
- | |
588 | * part of the HW/SW state that will be inited anyway explicitly. |
- | |
589 | */ |
1383 | WARN_ON_ONCE(power_well->data != PIPE_A); |
590 | if (dev_priv->power_domains.initializing) |
- | |
591 | return; |
- | |
592 | - | ||
593 | intel_hpd_init(dev_priv); |
1384 | |
Line 594... | Line 1385... | ||
594 | 1385 | chv_set_pipe_power_well(dev_priv, power_well, true); |
|
595 | i915_redisable_vga_power_on(dev_priv->dev); |
1386 | |
596 | } |
1387 | vlv_display_power_well_init(dev_priv); |
597 | } |
1388 | } |
598 | - | ||
599 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
- | |
Line 600... | Line -... | ||
600 | struct i915_power_well *power_well) |
- | |
601 | { |
- | |
602 | WARN_ON_ONCE(power_well->data != PIPE_A && |
1389 | |
603 | power_well->data != PIPE_B && |
- | |
604 | power_well->data != PIPE_C); |
- | |
Line 605... | Line 1390... | ||
605 | 1390 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
|
606 | if (power_well->data == PIPE_A) { |
- | |
607 | spin_lock_irq(&dev_priv->irq_lock); |
- | |
608 | valleyview_disable_display_irqs(dev_priv); |
- | |
609 | spin_unlock_irq(&dev_priv->irq_lock); |
- | |
610 | } |
- | |
611 | - | ||
612 | chv_set_pipe_power_well(dev_priv, power_well, false); |
- | |
613 | - | ||
614 | if (power_well->data == PIPE_A) |
- | |
615 | vlv_power_sequencer_reset(dev_priv); |
- | |
616 | } |
- | |
617 | - | ||
618 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
- | |
619 | struct i915_power_well *power_well) |
- | |
620 | { |
- | |
621 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); |
- | |
622 | - | ||
623 | if (power_well->always_on || !i915.disable_power_well) { |
- | |
624 | if (!enabled) |
- | |
625 | goto mismatch; |
- | |
626 | - | ||
627 | return; |
- | |
628 | } |
- | |
629 | - | ||
630 | if (enabled != (power_well->count > 0)) |
- | |
631 | goto mismatch; |
- | |
632 | 1391 | struct i915_power_well *power_well) |
|
Line 633... | Line 1392... | ||
633 | return; |
1392 | { |
634 | 1393 | WARN_ON_ONCE(power_well->data != PIPE_A); |
|
635 | mismatch: |
1394 | |
Line 662... | Line 1421... | ||
662 | power_domains = &dev_priv->power_domains; |
1421 | power_domains = &dev_priv->power_domains; |
Line 663... | Line 1422... | ||
663 | 1422 | ||
Line 664... | Line 1423... | ||
664 | mutex_lock(&power_domains->lock); |
1423 | mutex_lock(&power_domains->lock); |
665 | 1424 | ||
666 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
- | |
667 | if (!power_well->count++) { |
- | |
668 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
- | |
669 | power_well->ops->enable(dev_priv, power_well); |
- | |
670 | power_well->hw_enabled = true; |
- | |
671 | } |
1425 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
672 | 1426 | if (!power_well->count++) |
|
Line 673... | Line 1427... | ||
673 | check_power_well_state(dev_priv, power_well); |
1427 | intel_power_well_enable(dev_priv, power_well); |
Line 674... | Line 1428... | ||
674 | } |
1428 | } |
Line 702... | Line 1456... | ||
702 | power_domains->domain_use_count[domain]--; |
1456 | power_domains->domain_use_count[domain]--; |
Line 703... | Line 1457... | ||
703 | 1457 | ||
704 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
1458 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
Line 705... | Line 1459... | ||
705 | WARN_ON(!power_well->count); |
1459 | WARN_ON(!power_well->count); |
706 | - | ||
707 | if (!--power_well->count && i915.disable_power_well) { |
- | |
708 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
- | |
709 | power_well->hw_enabled = false; |
- | |
710 | power_well->ops->disable(dev_priv, power_well); |
- | |
711 | } |
1460 | |
712 | 1461 | if (!--power_well->count && i915.disable_power_well) |
|
Line 713... | Line 1462... | ||
713 | check_power_well_state(dev_priv, power_well); |
1462 | intel_power_well_disable(dev_priv, power_well); |
Line 714... | Line 1463... | ||
714 | } |
1463 | } |
715 | 1464 | ||
Line 716... | Line -... | ||
716 | mutex_unlock(&power_domains->lock); |
- | |
717 | - | ||
718 | intel_runtime_pm_put(dev_priv); |
1465 | mutex_unlock(&power_domains->lock); |
719 | } |
1466 | |
720 | 1467 | intel_runtime_pm_put(dev_priv); |
|
721 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
1468 | } |
722 | 1469 | ||
Line 731... | Line 1478... | ||
731 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
1478 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
732 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
1479 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
733 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
1480 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
734 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
1481 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
735 | BIT(POWER_DOMAIN_PLLS) | \ |
1482 | BIT(POWER_DOMAIN_PLLS) | \ |
- | 1483 | BIT(POWER_DOMAIN_AUX_A) | \ |
|
- | 1484 | BIT(POWER_DOMAIN_AUX_B) | \ |
|
- | 1485 | BIT(POWER_DOMAIN_AUX_C) | \ |
|
- | 1486 | BIT(POWER_DOMAIN_AUX_D) | \ |
|
- | 1487 | BIT(POWER_DOMAIN_GMBUS) | \ |
|
736 | BIT(POWER_DOMAIN_INIT)) |
1488 | BIT(POWER_DOMAIN_INIT)) |
737 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
1489 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
738 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
1490 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
739 | BIT(POWER_DOMAIN_INIT)) |
1491 | BIT(POWER_DOMAIN_INIT)) |
Line 752... | Line 1504... | ||
752 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
1504 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
753 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
1505 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
754 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
1506 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
755 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
1507 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
756 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
1508 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
- | 1509 | BIT(POWER_DOMAIN_AUX_B) | \ |
|
- | 1510 | BIT(POWER_DOMAIN_AUX_C) | \ |
|
757 | BIT(POWER_DOMAIN_INIT)) |
1511 | BIT(POWER_DOMAIN_INIT)) |
Line 758... | Line 1512... | ||
758 | 1512 | ||
759 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
1513 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
760 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
1514 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
- | 1515 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
|
761 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
1516 | BIT(POWER_DOMAIN_AUX_B) | \ |
Line 762... | Line 1517... | ||
762 | BIT(POWER_DOMAIN_INIT)) |
1517 | BIT(POWER_DOMAIN_INIT)) |
763 | 1518 | ||
- | 1519 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
|
764 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
1520 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Line 765... | Line 1521... | ||
765 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
1521 | BIT(POWER_DOMAIN_AUX_B) | \ |
766 | BIT(POWER_DOMAIN_INIT)) |
1522 | BIT(POWER_DOMAIN_INIT)) |
767 | 1523 | ||
- | 1524 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
|
768 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
1525 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
Line 769... | Line 1526... | ||
769 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
1526 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
770 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
1527 | BIT(POWER_DOMAIN_AUX_C) | \ |
771 | BIT(POWER_DOMAIN_INIT)) |
- | |
772 | - | ||
773 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
- | |
774 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
- | |
775 | BIT(POWER_DOMAIN_INIT)) |
- | |
776 | - | ||
777 | #define CHV_PIPE_A_POWER_DOMAINS ( \ |
- | |
778 | BIT(POWER_DOMAIN_PIPE_A) | \ |
- | |
779 | BIT(POWER_DOMAIN_INIT)) |
- | |
780 | - | ||
781 | #define CHV_PIPE_B_POWER_DOMAINS ( \ |
- | |
782 | BIT(POWER_DOMAIN_PIPE_B) | \ |
1528 | BIT(POWER_DOMAIN_INIT)) |
783 | BIT(POWER_DOMAIN_INIT)) |
1529 | |
Line 784... | Line 1530... | ||
784 | 1530 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
|
785 | #define CHV_PIPE_C_POWER_DOMAINS ( \ |
1531 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
786 | BIT(POWER_DOMAIN_PIPE_C) | \ |
1532 | BIT(POWER_DOMAIN_AUX_C) | \ |
787 | BIT(POWER_DOMAIN_INIT)) |
1533 | BIT(POWER_DOMAIN_INIT)) |
788 | 1534 | ||
- | 1535 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
|
- | 1536 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
|
789 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
1537 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Line 790... | Line 1538... | ||
790 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
1538 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
791 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
1539 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
792 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
1540 | BIT(POWER_DOMAIN_AUX_B) | \ |
793 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
1541 | BIT(POWER_DOMAIN_AUX_C) | \ |
794 | BIT(POWER_DOMAIN_INIT)) |
- | |
795 | - | ||
796 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
- | |
797 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
- | |
798 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
- | |
799 | BIT(POWER_DOMAIN_INIT)) |
- | |
800 | - | ||
801 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ |
- | |
802 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
1542 | BIT(POWER_DOMAIN_INIT)) |
Line 803... | Line 1543... | ||
803 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
1543 | |
804 | BIT(POWER_DOMAIN_INIT)) |
1544 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
805 | 1545 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
|
Line 842... | Line 1582... | ||
842 | .enable = hsw_power_well_enable, |
1582 | .enable = hsw_power_well_enable, |
843 | .disable = hsw_power_well_disable, |
1583 | .disable = hsw_power_well_disable, |
844 | .is_enabled = hsw_power_well_enabled, |
1584 | .is_enabled = hsw_power_well_enabled, |
845 | }; |
1585 | }; |
Line -... | Line 1586... | ||
- | 1586 | ||
- | 1587 | static const struct i915_power_well_ops skl_power_well_ops = { |
|
- | 1588 | .sync_hw = skl_power_well_sync_hw, |
|
- | 1589 | .enable = skl_power_well_enable, |
|
- | 1590 | .disable = skl_power_well_disable, |
|
- | 1591 | .is_enabled = skl_power_well_enabled, |
|
- | 1592 | }; |
|
846 | 1593 | ||
847 | static struct i915_power_well hsw_power_wells[] = { |
1594 | static struct i915_power_well hsw_power_wells[] = { |
848 | { |
1595 | { |
849 | .name = "always-on", |
1596 | .name = "always-on", |
850 | .always_on = 1, |
1597 | .always_on = 1, |
Line 955... | Line 1702... | ||
955 | .name = "always-on", |
1702 | .name = "always-on", |
956 | .always_on = 1, |
1703 | .always_on = 1, |
957 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
1704 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
958 | .ops = &i9xx_always_on_power_well_ops, |
1705 | .ops = &i9xx_always_on_power_well_ops, |
959 | }, |
1706 | }, |
960 | #if 0 |
- | |
961 | { |
1707 | { |
962 | .name = "display", |
1708 | .name = "display", |
963 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
- | |
964 | .data = PUNIT_POWER_WELL_DISP2D, |
- | |
965 | .ops = &vlv_display_power_well_ops, |
- | |
966 | }, |
- | |
967 | #endif |
- | |
968 | { |
- | |
969 | .name = "pipe-a", |
- | |
970 | /* |
1709 | /* |
971 | * FIXME: pipe A power well seems to be the new disp2d well. |
1710 | * Pipe A power well is the new disp2d well. Pipe B and C |
972 | * At least all registers seem to be housed there. Figure |
- | |
973 | * out if this a a temporary situation in pre-production |
1711 | * power wells don't actually exist. Pipe A power well is |
974 | * hardware or a permanent state of affairs. |
1712 | * required for any pipe to work. |
975 | */ |
1713 | */ |
976 | .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, |
1714 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
977 | .data = PIPE_A, |
1715 | .data = PIPE_A, |
978 | .ops = &chv_pipe_power_well_ops, |
1716 | .ops = &chv_pipe_power_well_ops, |
979 | }, |
1717 | }, |
980 | #if 0 |
- | |
981 | { |
- | |
982 | .name = "pipe-b", |
- | |
983 | .domains = CHV_PIPE_B_POWER_DOMAINS, |
- | |
984 | .data = PIPE_B, |
- | |
985 | .ops = &chv_pipe_power_well_ops, |
- | |
986 | }, |
- | |
987 | { |
- | |
988 | .name = "pipe-c", |
- | |
989 | .domains = CHV_PIPE_C_POWER_DOMAINS, |
- | |
990 | .data = PIPE_C, |
- | |
991 | .ops = &chv_pipe_power_well_ops, |
- | |
992 | }, |
- | |
993 | #endif |
- | |
994 | { |
1718 | { |
995 | .name = "dpio-common-bc", |
1719 | .name = "dpio-common-bc", |
996 | /* |
- | |
997 | * XXX: cmnreset for one PHY seems to disturb the other. |
- | |
998 | * As a workaround keep both powered on at the same |
- | |
999 | * time for now. |
- | |
1000 | */ |
- | |
1001 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
1720 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
1002 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1721 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1003 | .ops = &chv_dpio_cmn_power_well_ops, |
1722 | .ops = &chv_dpio_cmn_power_well_ops, |
1004 | }, |
1723 | }, |
1005 | { |
1724 | { |
1006 | .name = "dpio-common-d", |
1725 | .name = "dpio-common-d", |
1007 | /* |
- | |
1008 | * XXX: cmnreset for one PHY seems to disturb the other. |
- | |
1009 | * As a workaround keep both powered on at the same |
- | |
1010 | * time for now. |
- | |
1011 | */ |
- | |
1012 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
1726 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
1013 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1727 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1014 | .ops = &chv_dpio_cmn_power_well_ops, |
1728 | .ops = &chv_dpio_cmn_power_well_ops, |
1015 | }, |
1729 | }, |
1016 | #if 0 |
1730 | }; |
- | 1731 | ||
- | 1732 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
|
- | 1733 | int power_well_id) |
|
1017 | { |
1734 | { |
- | 1735 | struct i915_power_well *power_well; |
|
- | 1736 | bool ret; |
|
- | 1737 | ||
- | 1738 | power_well = lookup_power_well(dev_priv, power_well_id); |
|
- | 1739 | ret = power_well->ops->is_enabled(dev_priv, power_well); |
|
- | 1740 | ||
- | 1741 | return ret; |
|
- | 1742 | } |
|
- | 1743 | ||
- | 1744 | static struct i915_power_well skl_power_wells[] = { |
|
- | 1745 | { |
|
1018 | .name = "dpio-tx-b-01", |
1746 | .name = "always-on", |
1019 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
1747 | .always_on = 1, |
1020 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
1748 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
1021 | .ops = &vlv_dpio_power_well_ops, |
1749 | .ops = &i9xx_always_on_power_well_ops, |
1022 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
- | |
1023 | }, |
1750 | }, |
1024 | { |
1751 | { |
1025 | .name = "dpio-tx-b-23", |
1752 | .name = "power well 1", |
1026 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
1753 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, |
1027 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
- | |
1028 | .ops = &vlv_dpio_power_well_ops, |
1754 | .ops = &skl_power_well_ops, |
1029 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
1755 | .data = SKL_DISP_PW_1, |
1030 | }, |
1756 | }, |
1031 | { |
1757 | { |
1032 | .name = "dpio-tx-c-01", |
1758 | .name = "MISC IO power well", |
1033 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
1759 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, |
1034 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
- | |
1035 | .ops = &vlv_dpio_power_well_ops, |
1760 | .ops = &skl_power_well_ops, |
1036 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
1761 | .data = SKL_DISP_PW_MISC_IO, |
1037 | }, |
1762 | }, |
1038 | { |
1763 | { |
1039 | .name = "dpio-tx-c-23", |
1764 | .name = "power well 2", |
1040 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
1765 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
1041 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
- | |
1042 | .ops = &vlv_dpio_power_well_ops, |
1766 | .ops = &skl_power_well_ops, |
1043 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
1767 | .data = SKL_DISP_PW_2, |
1044 | }, |
1768 | }, |
1045 | { |
1769 | { |
1046 | .name = "dpio-tx-d-01", |
1770 | .name = "DDI A/E power well", |
1047 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
1771 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, |
1048 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
- | |
1049 | .ops = &vlv_dpio_power_well_ops, |
1772 | .ops = &skl_power_well_ops, |
1050 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, |
1773 | .data = SKL_DISP_PW_DDI_A_E, |
1051 | }, |
1774 | }, |
1052 | { |
1775 | { |
1053 | .name = "dpio-tx-d-23", |
1776 | .name = "DDI B power well", |
1054 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
1777 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, |
- | 1778 | .ops = &skl_power_well_ops, |
|
- | 1779 | .data = SKL_DISP_PW_DDI_B, |
|
- | 1780 | }, |
|
- | 1781 | { |
|
- | 1782 | .name = "DDI C power well", |
|
1055 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
1783 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, |
1056 | .ops = &vlv_dpio_power_well_ops, |
1784 | .ops = &skl_power_well_ops, |
- | 1785 | .data = SKL_DISP_PW_DDI_C, |
|
- | 1786 | }, |
|
- | 1787 | { |
|
- | 1788 | .name = "DDI D power well", |
|
1057 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, |
1789 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, |
- | 1790 | .ops = &skl_power_well_ops, |
|
- | 1791 | .data = SKL_DISP_PW_DDI_D, |
|
1058 | }, |
1792 | }, |
1059 | #endif |
- | |
1060 | }; |
1793 | }; |
Line 1061... | Line -... | ||
1061 | - | ||
1062 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
1794 | |
1063 | enum punit_power_well power_well_id) |
1795 | static struct i915_power_well bxt_power_wells[] = { |
- | 1796 | { |
|
- | 1797 | .name = "always-on", |
|
1064 | { |
1798 | .always_on = 1, |
1065 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
1799 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
- | 1800 | .ops = &i9xx_always_on_power_well_ops, |
|
- | 1801 | }, |
|
- | 1802 | { |
|
- | 1803 | .name = "power well 1", |
|
- | 1804 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, |
|
- | 1805 | .ops = &skl_power_well_ops, |
|
1066 | struct i915_power_well *power_well; |
1806 | .data = SKL_DISP_PW_1, |
- | 1807 | }, |
|
- | 1808 | { |
|
- | 1809 | .name = "power well 2", |
|
- | 1810 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
|
- | 1811 | .ops = &skl_power_well_ops, |
|
- | 1812 | .data = SKL_DISP_PW_2, |
|
- | 1813 | } |
|
Line -... | Line 1814... | ||
- | 1814 | }; |
|
1067 | int i; |
1815 | |
1068 | 1816 | static int |
|
- | 1817 | sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, |
|
- | 1818 | int disable_power_well) |
|
1069 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
1819 | { |
- | 1820 | if (disable_power_well >= 0) |
|
- | 1821 | return !!disable_power_well; |
|
- | 1822 | ||
- | 1823 | if (IS_SKYLAKE(dev_priv)) { |
|
1070 | if (power_well->data == power_well_id) |
1824 | DRM_DEBUG_KMS("Disabling display power well support\n"); |
Line 1071... | Line 1825... | ||
1071 | return power_well; |
1825 | return 0; |
1072 | } |
1826 | } |
Line 1073... | Line 1827... | ||
1073 | 1827 | ||
1074 | return NULL; |
1828 | return 1; |
1075 | } |
1829 | } |
Line 1088... | Line 1842... | ||
1088 | */ |
1842 | */ |
1089 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1843 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1090 | { |
1844 | { |
1091 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
1845 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Line -... | Line 1846... | ||
- | 1846 | ||
- | 1847 | i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, |
|
- | 1848 | i915.disable_power_well); |
|
- | 1849 | ||
- | 1850 | BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); |
|
1092 | 1851 | ||
Line 1093... | Line 1852... | ||
1093 | mutex_init(&power_domains->lock); |
1852 | mutex_init(&power_domains->lock); |
1094 | 1853 | ||
1095 | /* |
1854 | /* |
1096 | * The enabling order will be from lower to higher indexed wells, |
1855 | * The enabling order will be from lower to higher indexed wells, |
1097 | * the disabling order is reversed. |
1856 | * the disabling order is reversed. |
1098 | */ |
1857 | */ |
1099 | if (IS_HASWELL(dev_priv->dev)) { |
- | |
1100 | set_power_wells(power_domains, hsw_power_wells); |
1858 | if (IS_HASWELL(dev_priv->dev)) { |
1101 | hsw_pwr = power_domains; |
1859 | set_power_wells(power_domains, hsw_power_wells); |
- | 1860 | } else if (IS_BROADWELL(dev_priv->dev)) { |
|
- | 1861 | set_power_wells(power_domains, bdw_power_wells); |
|
- | 1862 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
|
1102 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1863 | set_power_wells(power_domains, skl_power_wells); |
1103 | set_power_wells(power_domains, bdw_power_wells); |
1864 | } else if (IS_BROXTON(dev_priv->dev)) { |
1104 | hsw_pwr = power_domains; |
1865 | set_power_wells(power_domains, bxt_power_wells); |
1105 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1866 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1106 | set_power_wells(power_domains, chv_power_wells); |
1867 | set_power_wells(power_domains, chv_power_wells); |
1107 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
1868 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
Line 1124... | Line 1885... | ||
1124 | if (!intel_enable_rc6(dev)) |
1885 | if (!intel_enable_rc6(dev)) |
1125 | return; |
1886 | return; |
Line 1126... | Line 1887... | ||
1126 | 1887 | ||
1127 | /* Make sure we're not suspended first. */ |
1888 | /* Make sure we're not suspended first. */ |
1128 | pm_runtime_get_sync(device); |
- | |
1129 | pm_runtime_disable(device); |
1889 | pm_runtime_get_sync(device); |
Line 1130... | Line 1890... | ||
1130 | } |
1890 | } |
1131 | 1891 | ||
1132 | /** |
1892 | /** |
Line 1143... | Line 1903... | ||
1143 | 1903 | ||
1144 | /* The i915.ko module is still not prepared to be loaded when |
1904 | /* The i915.ko module is still not prepared to be loaded when |
1145 | * the power well is not enabled, so just enable it in case |
1905 | * the power well is not enabled, so just enable it in case |
1146 | * we're going to unload/reload. */ |
1906 | * we're going to unload/reload. */ |
1147 | intel_display_set_init_power(dev_priv, true); |
- | |
1148 | - | ||
1149 | hsw_pwr = NULL; |
1907 | intel_display_set_init_power(dev_priv, true); |
Line 1150... | Line 1908... | ||
1150 | } |
1908 | } |
1151 | 1909 | ||
1152 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
1910 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
Line 1162... | Line 1920... | ||
1162 | power_well); |
1920 | power_well); |
1163 | } |
1921 | } |
1164 | mutex_unlock(&power_domains->lock); |
1922 | mutex_unlock(&power_domains->lock); |
1165 | } |
1923 | } |
Line -... | Line 1924... | ||
- | 1924 | ||
- | 1925 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
|
- | 1926 | { |
|
- | 1927 | struct i915_power_well *cmn_bc = |
|
- | 1928 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
|
- | 1929 | struct i915_power_well *cmn_d = |
|
- | 1930 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); |
|
- | 1931 | ||
- | 1932 | /* |
|
- | 1933 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a |
|
- | 1934 | * workaround never ever read DISPLAY_PHY_CONTROL, and |
|
- | 1935 | * instead maintain a shadow copy ourselves. Use the actual |
|
- | 1936 | * power well state and lane status to reconstruct the |
|
- | 1937 | * expected initial value. |
|
- | 1938 | */ |
|
- | 1939 | dev_priv->chv_phy_control = |
|
- | 1940 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
|
- | 1941 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | |
|
- | 1942 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | |
|
- | 1943 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | |
|
- | 1944 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); |
|
- | 1945 | ||
- | 1946 | /* |
|
- | 1947 | * If all lanes are disabled we leave the override disabled |
|
- | 1948 | * with all power down bits cleared to match the state we |
|
- | 1949 | * would use after disabling the port. Otherwise enable the |
|
- | 1950 | * override and set the lane powerdown bits accding to the |
|
- | 1951 | * current lane status. |
|
- | 1952 | */ |
|
- | 1953 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
|
- | 1954 | uint32_t status = I915_READ(DPLL(PIPE_A)); |
|
- | 1955 | unsigned int mask; |
|
- | 1956 | ||
- | 1957 | mask = status & DPLL_PORTB_READY_MASK; |
|
- | 1958 | if (mask == 0xf) |
|
- | 1959 | mask = 0x0; |
|
- | 1960 | else |
|
- | 1961 | dev_priv->chv_phy_control |= |
|
- | 1962 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); |
|
- | 1963 | ||
- | 1964 | dev_priv->chv_phy_control |= |
|
- | 1965 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); |
|
- | 1966 | ||
- | 1967 | mask = (status & DPLL_PORTC_READY_MASK) >> 4; |
|
- | 1968 | if (mask == 0xf) |
|
- | 1969 | mask = 0x0; |
|
- | 1970 | else |
|
- | 1971 | dev_priv->chv_phy_control |= |
|
- | 1972 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); |
|
- | 1973 | ||
- | 1974 | dev_priv->chv_phy_control |= |
|
- | 1975 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); |
|
- | 1976 | ||
- | 1977 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
|
- | 1978 | ||
- | 1979 | dev_priv->chv_phy_assert[DPIO_PHY0] = false; |
|
- | 1980 | } else { |
|
- | 1981 | dev_priv->chv_phy_assert[DPIO_PHY0] = true; |
|
- | 1982 | } |
|
- | 1983 | ||
- | 1984 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { |
|
- | 1985 | uint32_t status = I915_READ(DPIO_PHY_STATUS); |
|
- | 1986 | unsigned int mask; |
|
- | 1987 | ||
- | 1988 | mask = status & DPLL_PORTD_READY_MASK; |
|
- | 1989 | ||
- | 1990 | if (mask == 0xf) |
|
- | 1991 | mask = 0x0; |
|
- | 1992 | else |
|
- | 1993 | dev_priv->chv_phy_control |= |
|
- | 1994 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); |
|
- | 1995 | ||
- | 1996 | dev_priv->chv_phy_control |= |
|
- | 1997 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); |
|
- | 1998 | ||
- | 1999 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
|
- | 2000 | ||
- | 2001 | dev_priv->chv_phy_assert[DPIO_PHY1] = false; |
|
- | 2002 | } else { |
|
- | 2003 | dev_priv->chv_phy_assert[DPIO_PHY1] = true; |
|
- | 2004 | } |
|
- | 2005 | ||
- | 2006 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
|
- | 2007 | ||
- | 2008 | DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", |
|
- | 2009 | dev_priv->chv_phy_control); |
|
- | 2010 | } |
|
1166 | 2011 | ||
1167 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
2012 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
1168 | { |
2013 | { |
1169 | struct i915_power_well *cmn = |
2014 | struct i915_power_well *cmn = |
1170 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
2015 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
Line 1204... | Line 2049... | ||
1204 | struct drm_device *dev = dev_priv->dev; |
2049 | struct drm_device *dev = dev_priv->dev; |
1205 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2050 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Line 1206... | Line 2051... | ||
1206 | 2051 | ||
Line 1207... | Line 2052... | ||
1207 | power_domains->initializing = true; |
2052 | power_domains->initializing = true; |
- | 2053 | ||
- | 2054 | if (IS_CHERRYVIEW(dev)) { |
|
- | 2055 | mutex_lock(&power_domains->lock); |
|
- | 2056 | chv_phy_control_init(dev_priv); |
|
1208 | 2057 | mutex_unlock(&power_domains->lock); |
|
1209 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
2058 | } else if (IS_VALLEYVIEW(dev)) { |
1210 | mutex_lock(&power_domains->lock); |
2059 | mutex_lock(&power_domains->lock); |
1211 | vlv_cmnlane_wa(dev_priv); |
2060 | vlv_cmnlane_wa(dev_priv); |
Line 1217... | Line 2066... | ||
1217 | intel_power_domains_resume(dev_priv); |
2066 | intel_power_domains_resume(dev_priv); |
1218 | power_domains->initializing = false; |
2067 | power_domains->initializing = false; |
1219 | } |
2068 | } |
Line 1220... | Line 2069... | ||
1220 | 2069 | ||
1221 | /** |
- | |
1222 | * intel_aux_display_runtime_get - grab an auxilliary power domain reference |
- | |
1223 | * @dev_priv: i915 device instance |
- | |
1224 | * |
- | |
1225 | * This function grabs a power domain reference for the auxiliary power domain |
- | |
1226 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its |
- | |
1227 | * parents are powered up. Therefore users should only grab a reference to the |
- | |
1228 | * innermost power domain they need. |
- | |
1229 | * |
- | |
1230 | * Any power domain reference obtained by this function must have a symmetric |
- | |
1231 | * call to intel_aux_display_runtime_put() to release the reference again. |
- | |
1232 | */ |
- | |
1233 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
- | |
1234 | { |
- | |
1235 | intel_runtime_pm_get(dev_priv); |
- | |
1236 | } |
- | |
1237 | - | ||
1238 | /** |
- | |
1239 | * intel_aux_display_runtime_put - release an auxilliary power domain reference |
- | |
1240 | * @dev_priv: i915 device instance |
- | |
1241 | * |
- | |
1242 | * This function drops the auxilliary power domain reference obtained by |
- | |
1243 | * intel_aux_display_runtime_get() and might power down the corresponding |
- | |
1244 | * hardware block right away if this is the last reference. |
- | |
1245 | */ |
- | |
1246 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
- | |
1247 | { |
- | |
1248 | intel_runtime_pm_put(dev_priv); |
- | |
1249 | } |
- | |
1250 | - | ||
1251 | /** |
2070 | /** |
1252 | * intel_runtime_pm_get - grab a runtime pm reference |
2071 | * intel_runtime_pm_get - grab a runtime pm reference |
1253 | * @dev_priv: i915 device instance |
2072 | * @dev_priv: i915 device instance |
1254 | * |
2073 | * |
1255 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
2074 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
Line 1294... | Line 2113... | ||
1294 | 2113 | ||
1295 | if (!HAS_RUNTIME_PM(dev)) |
2114 | if (!HAS_RUNTIME_PM(dev)) |
Line 1296... | Line 2115... | ||
1296 | return; |
2115 | return; |
1297 | 2116 | ||
1298 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
2117 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
Line 1299... | Line 2118... | ||
1299 | // pm_runtime_get_noresume(device); |
2118 | pm_runtime_get_noresume(device); |
1300 | } |
2119 | } |
1301 | 2120 | ||
Line 1313... | Line 2132... | ||
1313 | struct device *device = &dev->pdev->dev; |
2132 | struct device *device = &dev->pdev->dev; |
Line 1314... | Line 2133... | ||
1314 | 2133 | ||
1315 | if (!HAS_RUNTIME_PM(dev)) |
2134 | if (!HAS_RUNTIME_PM(dev)) |
Line 1316... | Line 2135... | ||
1316 | return; |
2135 | return; |
1317 | 2136 | ||
1318 | // pm_runtime_mark_last_busy(device); |
2137 | pm_runtime_mark_last_busy(device); |
Line 1319... | Line 2138... | ||
1319 | // pm_runtime_put_autosuspend(device); |
2138 | pm_runtime_put_autosuspend(device); |
1320 | } |
2139 | } |
1321 | 2140 | ||
Line 1335... | Line 2154... | ||
1335 | struct device *device = &dev->pdev->dev; |
2154 | struct device *device = &dev->pdev->dev; |
Line 1336... | Line 2155... | ||
1336 | 2155 | ||
1337 | if (!HAS_RUNTIME_PM(dev)) |
2156 | if (!HAS_RUNTIME_PM(dev)) |
Line 1338... | Line -... | ||
1338 | return; |
- | |
1339 | - | ||
1340 | pm_runtime_set_active(device); |
2157 | return; |
1341 | 2158 | ||
1342 | /* |
2159 | /* |
1343 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
2160 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
1344 | * requirement. |
2161 | * requirement. |
1345 | */ |
2162 | */ |
1346 | if (!intel_enable_rc6(dev)) { |
2163 | if (!intel_enable_rc6(dev)) { |
1347 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
2164 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
Line 1348... | Line 2165... | ||
1348 | return; |
2165 | return; |
1349 | } |
2166 | } |
1350 | 2167 | ||
1351 | // pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
- | |
1352 | // pm_runtime_mark_last_busy(device); |
- | |
1353 | // pm_runtime_use_autosuspend(device); |
- | |
1354 | - | ||
1355 | // pm_runtime_put_autosuspend(device); |
- | |
1356 | } |
- | |
1357 | - | ||
1358 | /* Display audio driver power well request */ |
- | |
1359 | int i915_request_power_well(void) |
- | |
1360 | { |
- | |
1361 | struct drm_i915_private *dev_priv; |
- | |
1362 | - | ||
1363 | if (!hsw_pwr) |
- | |
1364 | return -ENODEV; |
- | |
1365 | - | ||
1366 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
- | |
1367 | power_domains); |
- | |
1368 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
- | |
1369 | return 0; |
- | |
1370 | } |
- | |
1371 | EXPORT_SYMBOL_GPL(i915_request_power_well); |
- | |
1372 | - | ||
1373 | /* Display audio driver power well release */ |
- | |
1374 | int i915_release_power_well(void) |
- | |
1375 | { |
- | |
1376 | struct drm_i915_private *dev_priv; |
- | |
Line 1377... | Line 2168... | ||
1377 | 2168 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
|
1378 | if (!hsw_pwr) |
- | |
1379 | return -ENODEV; |
- | |
1380 | - | ||
1381 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
2169 | pm_runtime_mark_last_busy(device); |
1382 | power_domains); |
- | |
Line 1383... | Line -... | ||
1383 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
- | |
1384 | return 0; |
- | |
1385 | } |
- | |
1386 | EXPORT_SYMBOL_GPL(i915_release_power_well); |
- | |
1387 | - | ||
1388 | /* |
- | |
1389 | * Private interface for the audio driver to get CDCLK in kHz. |
- | |
1390 | * |
- | |
1391 | * Caller must request power well using i915_request_power_well() prior to |
- | |
1392 | * making the call. |
- | |
1393 | */ |
- | |
1394 | int i915_get_cdclk_freq(void) |
- | |
1395 | { |
- | |
1396 | struct drm_i915_private *dev_priv; |
- | |
1397 | - | ||
1398 | if (!hsw_pwr) |
- | |
1399 | return -ENODEV; |
- | |
1400 | - | ||
1401 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
- |