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1 | #ifndef _INTEL_RINGBUFFER_H_ |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
- | 3 | ||
- | 4 | #include |
|
- | 5 | ||
- | 6 | #define I915_CMD_HASH_ORDER 9 |
|
3 | 7 | ||
4 | /* |
8 | /* |
5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
9 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
10 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
11 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
8 | * |
12 | * |
9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
13 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
10 | * cacheline, the Head Pointer must not be greater than the Tail |
14 | * cacheline, the Head Pointer must not be greater than the Tail |
11 | * Pointer." |
15 | * Pointer." |
12 | */ |
16 | */ |
13 | #define I915_RING_FREE_SPACE 64 |
17 | #define I915_RING_FREE_SPACE 64 |
14 | 18 | ||
15 | struct intel_hw_status_page { |
19 | struct intel_hw_status_page { |
16 | u32 *page_addr; |
20 | u32 *page_addr; |
17 | unsigned int gfx_addr; |
21 | unsigned int gfx_addr; |
18 | struct drm_i915_gem_object *obj; |
22 | struct drm_i915_gem_object *obj; |
19 | }; |
23 | }; |
20 | 24 | ||
21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
25 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
26 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
23 | 27 | ||
24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
28 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
29 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
26 | 30 | ||
27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
31 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
32 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
29 | 33 | ||
30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
34 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
35 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
32 | 36 | ||
33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
37 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
38 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
- | 39 | ||
- | 40 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
|
- | 41 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
|
- | 42 | ||
- | 43 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
|
- | 44 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
|
- | 45 | */ |
|
- | 46 | #define i915_semaphore_seqno_size sizeof(uint64_t) |
|
- | 47 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
|
- | 48 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
|
- | 49 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
|
- | 50 | (i915_semaphore_seqno_size * (to))) |
|
- | 51 | ||
- | 52 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
|
- | 53 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
|
- | 54 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
|
- | 55 | (i915_semaphore_seqno_size * (__ring)->id)) |
|
- | 56 | ||
- | 57 | #define GEN8_RING_SEMAPHORE_INIT do { \ |
|
- | 58 | if (!dev_priv->semaphore_obj) { \ |
|
- | 59 | break; \ |
|
- | 60 | } \ |
|
- | 61 | ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \ |
|
- | 62 | ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \ |
|
- | 63 | ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \ |
|
- | 64 | ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \ |
|
- | 65 | ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \ |
|
- | 66 | ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \ |
|
- | 67 | } while(0) |
|
35 | 68 | ||
36 | enum intel_ring_hangcheck_action { |
69 | enum intel_ring_hangcheck_action { |
37 | HANGCHECK_IDLE = 0, |
70 | HANGCHECK_IDLE = 0, |
38 | HANGCHECK_WAIT, |
71 | HANGCHECK_WAIT, |
39 | HANGCHECK_ACTIVE, |
72 | HANGCHECK_ACTIVE, |
- | 73 | HANGCHECK_ACTIVE_LOOP, |
|
40 | HANGCHECK_KICK, |
74 | HANGCHECK_KICK, |
41 | HANGCHECK_HUNG, |
75 | HANGCHECK_HUNG, |
42 | }; |
76 | }; |
- | 77 | ||
- | 78 | #define HANGCHECK_SCORE_RING_HUNG 31 |
|
43 | 79 | ||
- | 80 | struct intel_ring_hangcheck { |
|
44 | struct intel_ring_hangcheck { |
81 | u64 acthd; |
45 | bool deadlock; |
82 | u64 max_acthd; |
46 | u32 seqno; |
- | |
47 | u32 acthd; |
83 | u32 seqno; |
48 | int score; |
84 | int score; |
- | 85 | enum intel_ring_hangcheck_action action; |
|
49 | enum intel_ring_hangcheck_action action; |
86 | int deadlock; |
50 | }; |
87 | }; |
51 | - | ||
52 | struct intel_ring_buffer { |
- | |
53 | const char *name; |
- | |
54 | enum intel_ring_id { |
- | |
55 | RCS = 0x0, |
- | |
56 | VCS, |
- | |
57 | BCS, |
- | |
58 | VECS, |
- | |
59 | } id; |
- | |
60 | #define I915_NUM_RINGS 4 |
- | |
61 | u32 mmio_base; |
- | |
62 | void __iomem *virtual_start; |
88 | |
- | 89 | struct intel_ringbuffer { |
|
63 | struct drm_device *dev; |
90 | struct drm_i915_gem_object *obj; |
64 | struct drm_i915_gem_object *obj; |
91 | void __iomem *virtual_start; |
65 | 92 | ||
66 | u32 head; |
93 | u32 head; |
67 | u32 tail; |
94 | u32 tail; |
68 | int space; |
95 | int space; |
69 | int size; |
96 | int size; |
70 | int effective_size; |
97 | int effective_size; |
71 | struct intel_hw_status_page status_page; |
- | |
72 | 98 | ||
73 | /** We track the position of the requests in the ring buffer, and |
99 | /** We track the position of the requests in the ring buffer, and |
74 | * when each is retired we increment last_retired_head as the GPU |
100 | * when each is retired we increment last_retired_head as the GPU |
75 | * must have finished processing the request and so we know we |
101 | * must have finished processing the request and so we know we |
76 | * can advance the ringbuffer up to that position. |
102 | * can advance the ringbuffer up to that position. |
77 | * |
103 | * |
78 | * last_retired_head is set to -1 after the value is consumed so |
104 | * last_retired_head is set to -1 after the value is consumed so |
79 | * we can detect new retirements. |
105 | * we can detect new retirements. |
80 | */ |
106 | */ |
81 | u32 last_retired_head; |
107 | u32 last_retired_head; |
- | 108 | }; |
|
- | 109 | ||
- | 110 | struct intel_engine_cs { |
|
- | 111 | const char *name; |
|
- | 112 | enum intel_ring_id { |
|
- | 113 | RCS = 0x0, |
|
- | 114 | VCS, |
|
- | 115 | BCS, |
|
- | 116 | VECS, |
|
- | 117 | VCS2 |
|
- | 118 | } id; |
|
- | 119 | #define I915_NUM_RINGS 5 |
|
- | 120 | #define LAST_USER_RING (VECS + 1) |
|
- | 121 | u32 mmio_base; |
|
- | 122 | struct drm_device *dev; |
|
- | 123 | struct intel_ringbuffer *buffer; |
|
- | 124 | ||
- | 125 | struct intel_hw_status_page status_page; |
|
82 | 126 | ||
83 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
127 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
84 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
128 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
85 | u32 trace_irq_seqno; |
129 | u32 trace_irq_seqno; |
86 | u32 sync_seqno[I915_NUM_RINGS-1]; |
- | |
87 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
130 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
88 | void (*irq_put)(struct intel_ring_buffer *ring); |
131 | void (*irq_put)(struct intel_engine_cs *ring); |
89 | 132 | ||
90 | int (*init)(struct intel_ring_buffer *ring); |
133 | int (*init)(struct intel_engine_cs *ring); |
91 | 134 | ||
92 | void (*write_tail)(struct intel_ring_buffer *ring, |
135 | void (*write_tail)(struct intel_engine_cs *ring, |
93 | u32 value); |
136 | u32 value); |
94 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
137 | int __must_check (*flush)(struct intel_engine_cs *ring, |
95 | u32 invalidate_domains, |
138 | u32 invalidate_domains, |
96 | u32 flush_domains); |
139 | u32 flush_domains); |
97 | int (*add_request)(struct intel_ring_buffer *ring); |
140 | int (*add_request)(struct intel_engine_cs *ring); |
98 | /* Some chipsets are not quite as coherent as advertised and need |
141 | /* Some chipsets are not quite as coherent as advertised and need |
99 | * an expensive kick to force a true read of the up-to-date seqno. |
142 | * an expensive kick to force a true read of the up-to-date seqno. |
100 | * However, the up-to-date seqno is not always required and the last |
143 | * However, the up-to-date seqno is not always required and the last |
101 | * seen value is good enough. Note that the seqno will always be |
144 | * seen value is good enough. Note that the seqno will always be |
102 | * monotonic, even if not coherent. |
145 | * monotonic, even if not coherent. |
103 | */ |
146 | */ |
104 | u32 (*get_seqno)(struct intel_ring_buffer *ring, |
147 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
105 | bool lazy_coherency); |
148 | bool lazy_coherency); |
106 | void (*set_seqno)(struct intel_ring_buffer *ring, |
149 | void (*set_seqno)(struct intel_engine_cs *ring, |
107 | u32 seqno); |
150 | u32 seqno); |
108 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
151 | int (*dispatch_execbuffer)(struct intel_engine_cs *ring, |
109 | u32 offset, u32 length, |
152 | u64 offset, u32 length, |
110 | unsigned flags); |
153 | unsigned flags); |
111 | #define I915_DISPATCH_SECURE 0x1 |
154 | #define I915_DISPATCH_SECURE 0x1 |
112 | #define I915_DISPATCH_PINNED 0x2 |
155 | #define I915_DISPATCH_PINNED 0x2 |
113 | void (*cleanup)(struct intel_ring_buffer *ring); |
156 | void (*cleanup)(struct intel_engine_cs *ring); |
114 | int (*sync_to)(struct intel_ring_buffer *ring, |
- | |
115 | struct intel_ring_buffer *to, |
- | |
116 | u32 seqno); |
- | |
- | 157 | ||
- | 158 | /* GEN8 signal/wait table - never trust comments! |
|
- | 159 | * signal to signal to signal to signal to signal to |
|
- | 160 | * RCS VCS BCS VECS VCS2 |
|
- | 161 | * -------------------------------------------------------------------- |
|
- | 162 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
|
- | 163 | * |------------------------------------------------------------------- |
|
- | 164 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
|
- | 165 | * |------------------------------------------------------------------- |
|
- | 166 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
|
- | 167 | * |------------------------------------------------------------------- |
|
- | 168 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
|
- | 169 | * |------------------------------------------------------------------- |
|
- | 170 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
|
- | 171 | * |------------------------------------------------------------------- |
|
- | 172 | * |
|
- | 173 | * Generalization: |
|
- | 174 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
|
- | 175 | * ie. transpose of g(x, y) |
|
- | 176 | * |
|
- | 177 | * sync from sync from sync from sync from sync from |
|
- | 178 | * RCS VCS BCS VECS VCS2 |
|
- | 179 | * -------------------------------------------------------------------- |
|
- | 180 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
|
- | 181 | * |------------------------------------------------------------------- |
|
- | 182 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
|
- | 183 | * |------------------------------------------------------------------- |
|
- | 184 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
|
- | 185 | * |------------------------------------------------------------------- |
|
- | 186 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
|
- | 187 | * |------------------------------------------------------------------- |
|
- | 188 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
|
- | 189 | * |------------------------------------------------------------------- |
|
- | 190 | * |
|
- | 191 | * Generalization: |
|
- | 192 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
|
- | 193 | * ie. transpose of f(x, y) |
|
- | 194 | */ |
|
- | 195 | struct { |
|
- | 196 | u32 sync_seqno[I915_NUM_RINGS-1]; |
|
- | 197 | ||
- | 198 | union { |
|
117 | 199 | struct { |
|
118 | /* our mbox written by others */ |
200 | /* our mbox written by others */ |
119 | u32 semaphore_register[I915_NUM_RINGS]; |
201 | u32 wait[I915_NUM_RINGS]; |
120 | /* mboxes this ring signals to */ |
202 | /* mboxes this ring signals to */ |
- | 203 | u32 signal[I915_NUM_RINGS]; |
|
- | 204 | } mbox; |
|
- | 205 | u64 signal_ggtt[I915_NUM_RINGS]; |
|
- | 206 | }; |
|
- | 207 | ||
- | 208 | /* AKA wait() */ |
|
- | 209 | int (*sync_to)(struct intel_engine_cs *ring, |
|
- | 210 | struct intel_engine_cs *to, |
|
- | 211 | u32 seqno); |
|
- | 212 | int (*signal)(struct intel_engine_cs *signaller, |
|
- | 213 | /* num_dwords needed by caller */ |
|
- | 214 | unsigned int num_dwords); |
|
121 | u32 signal_mbox[I915_NUM_RINGS]; |
215 | } semaphore; |
122 | 216 | ||
123 | /** |
217 | /** |
124 | * List of objects currently involved in rendering from the |
218 | * List of objects currently involved in rendering from the |
125 | * ringbuffer. |
219 | * ringbuffer. |
126 | * |
220 | * |
127 | * Includes buffers having the contents of their GPU caches |
221 | * Includes buffers having the contents of their GPU caches |
128 | * flushed, not necessarily primitives. last_rendering_seqno |
222 | * flushed, not necessarily primitives. last_rendering_seqno |
129 | * represents when the rendering involved will be completed. |
223 | * represents when the rendering involved will be completed. |
130 | * |
224 | * |
131 | * A reference is held on the buffer while on this list. |
225 | * A reference is held on the buffer while on this list. |
132 | */ |
226 | */ |
133 | struct list_head active_list; |
227 | struct list_head active_list; |
134 | 228 | ||
135 | /** |
229 | /** |
136 | * List of breadcrumbs associated with GPU requests currently |
230 | * List of breadcrumbs associated with GPU requests currently |
137 | * outstanding. |
231 | * outstanding. |
138 | */ |
232 | */ |
139 | struct list_head request_list; |
233 | struct list_head request_list; |
140 | 234 | ||
141 | /** |
235 | /** |
142 | * Do we have some not yet emitted requests outstanding? |
236 | * Do we have some not yet emitted requests outstanding? |
143 | */ |
237 | */ |
144 | struct drm_i915_gem_request *preallocated_lazy_request; |
238 | struct drm_i915_gem_request *preallocated_lazy_request; |
145 | u32 outstanding_lazy_seqno; |
239 | u32 outstanding_lazy_seqno; |
146 | bool gpu_caches_dirty; |
240 | bool gpu_caches_dirty; |
147 | bool fbc_dirty; |
241 | bool fbc_dirty; |
148 | 242 | ||
149 | wait_queue_head_t irq_queue; |
243 | wait_queue_head_t irq_queue; |
150 | - | ||
151 | /** |
- | |
152 | * Do an explicit TLB flush before MI_SET_CONTEXT |
- | |
153 | */ |
- | |
154 | bool itlb_before_ctx_switch; |
244 | |
155 | struct i915_hw_context *default_context; |
245 | struct intel_context *default_context; |
156 | struct i915_hw_context *last_context; |
246 | struct intel_context *last_context; |
157 | 247 | ||
158 | struct intel_ring_hangcheck hangcheck; |
248 | struct intel_ring_hangcheck hangcheck; |
159 | 249 | ||
160 | struct { |
250 | struct { |
161 | struct drm_i915_gem_object *obj; |
251 | struct drm_i915_gem_object *obj; |
162 | u32 gtt_offset; |
252 | u32 gtt_offset; |
163 | volatile u32 *cpu_page; |
253 | volatile u32 *cpu_page; |
164 | } scratch; |
254 | } scratch; |
- | 255 | ||
- | 256 | bool needs_cmd_parser; |
|
- | 257 | ||
- | 258 | /* |
|
- | 259 | * Table of commands the command parser needs to know about |
|
- | 260 | * for this ring. |
|
- | 261 | */ |
|
- | 262 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
|
- | 263 | ||
- | 264 | /* |
|
- | 265 | * Table of registers allowed in commands that read/write registers. |
|
- | 266 | */ |
|
- | 267 | const u32 *reg_table; |
|
- | 268 | int reg_count; |
|
- | 269 | ||
- | 270 | /* |
|
- | 271 | * Table of registers allowed in commands that read/write registers, but |
|
- | 272 | * only from the DRM master. |
|
- | 273 | */ |
|
- | 274 | const u32 *master_reg_table; |
|
- | 275 | int master_reg_count; |
|
- | 276 | ||
- | 277 | /* |
|
- | 278 | * Returns the bitmask for the length field of the specified command. |
|
- | 279 | * Return 0 for an unrecognized/invalid command. |
|
- | 280 | * |
|
- | 281 | * If the command parser finds an entry for a command in the ring's |
|
- | 282 | * cmd_tables, it gets the command's length based on the table entry. |
|
- | 283 | * If not, it calls this function to determine the per-ring length field |
|
- | 284 | * encoding for the command (i.e. certain opcode ranges use certain bits |
|
- | 285 | * to encode the command length in the header). |
|
- | 286 | */ |
|
- | 287 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
|
165 | }; |
288 | }; |
166 | 289 | ||
167 | static inline bool |
290 | static inline bool |
168 | intel_ring_initialized(struct intel_ring_buffer *ring) |
291 | intel_ring_initialized(struct intel_engine_cs *ring) |
169 | { |
292 | { |
170 | return ring->obj != NULL; |
293 | return ring->buffer && ring->buffer->obj; |
171 | } |
294 | } |
172 | 295 | ||
173 | static inline unsigned |
296 | static inline unsigned |
174 | intel_ring_flag(struct intel_ring_buffer *ring) |
297 | intel_ring_flag(struct intel_engine_cs *ring) |
175 | { |
298 | { |
176 | return 1 << ring->id; |
299 | return 1 << ring->id; |
177 | } |
300 | } |
178 | 301 | ||
179 | static inline u32 |
302 | static inline u32 |
180 | intel_ring_sync_index(struct intel_ring_buffer *ring, |
303 | intel_ring_sync_index(struct intel_engine_cs *ring, |
181 | struct intel_ring_buffer *other) |
304 | struct intel_engine_cs *other) |
182 | { |
305 | { |
183 | int idx; |
306 | int idx; |
184 | 307 | ||
185 | /* |
308 | /* |
186 | * cs -> 0 = vcs, 1 = bcs |
309 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
187 | * vcs -> 0 = bcs, 1 = cs, |
310 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
188 | * bcs -> 0 = cs, 1 = vcs. |
311 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
- | 312 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
|
- | 313 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
|
189 | */ |
314 | */ |
190 | 315 | ||
191 | idx = (other - ring) - 1; |
316 | idx = (other - ring) - 1; |
192 | if (idx < 0) |
317 | if (idx < 0) |
193 | idx += I915_NUM_RINGS; |
318 | idx += I915_NUM_RINGS; |
194 | 319 | ||
195 | return idx; |
320 | return idx; |
196 | } |
321 | } |
197 | 322 | ||
198 | static inline u32 |
323 | static inline u32 |
199 | intel_read_status_page(struct intel_ring_buffer *ring, |
324 | intel_read_status_page(struct intel_engine_cs *ring, |
200 | int reg) |
325 | int reg) |
201 | { |
326 | { |
202 | /* Ensure that the compiler doesn't optimize away the load. */ |
327 | /* Ensure that the compiler doesn't optimize away the load. */ |
203 | barrier(); |
328 | barrier(); |
204 | return ring->status_page.page_addr[reg]; |
329 | return ring->status_page.page_addr[reg]; |
205 | } |
330 | } |
206 | 331 | ||
207 | static inline void |
332 | static inline void |
208 | intel_write_status_page(struct intel_ring_buffer *ring, |
333 | intel_write_status_page(struct intel_engine_cs *ring, |
209 | int reg, u32 value) |
334 | int reg, u32 value) |
210 | { |
335 | { |
211 | ring->status_page.page_addr[reg] = value; |
336 | ring->status_page.page_addr[reg] = value; |
212 | } |
337 | } |
213 | 338 | ||
214 | /** |
339 | /** |
215 | * Reads a dword out of the status page, which is written to from the command |
340 | * Reads a dword out of the status page, which is written to from the command |
216 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
341 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
217 | * MI_STORE_DATA_IMM. |
342 | * MI_STORE_DATA_IMM. |
218 | * |
343 | * |
219 | * The following dwords have a reserved meaning: |
344 | * The following dwords have a reserved meaning: |
220 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
345 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
221 | * 0x04: ring 0 head pointer |
346 | * 0x04: ring 0 head pointer |
222 | * 0x05: ring 1 head pointer (915-class) |
347 | * 0x05: ring 1 head pointer (915-class) |
223 | * 0x06: ring 2 head pointer (915-class) |
348 | * 0x06: ring 2 head pointer (915-class) |
224 | * 0x10-0x1b: Context status DWords (GM45) |
349 | * 0x10-0x1b: Context status DWords (GM45) |
225 | * 0x1f: Last written status offset. (GM45) |
350 | * 0x1f: Last written status offset. (GM45) |
226 | * |
351 | * |
227 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
352 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
228 | */ |
353 | */ |
229 | #define I915_GEM_HWS_INDEX 0x20 |
354 | #define I915_GEM_HWS_INDEX 0x20 |
230 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
355 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
231 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
356 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
- | 357 | ||
232 | 358 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
|
233 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
359 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); |
- | 360 | ||
234 | 361 | int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n); |
|
235 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
362 | int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring); |
236 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
363 | static inline void intel_ring_emit(struct intel_engine_cs *ring, |
- | 364 | u32 data) |
|
237 | u32 data) |
365 | { |
238 | { |
366 | struct intel_ringbuffer *ringbuf = ring->buffer; |
239 | iowrite32(data, ring->virtual_start + ring->tail); |
367 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
240 | ring->tail += 4; |
368 | ringbuf->tail += 4; |
241 | } |
369 | } |
- | 370 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
|
242 | static inline void intel_ring_advance(struct intel_ring_buffer *ring) |
371 | { |
243 | { |
372 | struct intel_ringbuffer *ringbuf = ring->buffer; |
244 | ring->tail &= ring->size - 1; |
373 | ringbuf->tail &= ringbuf->size - 1; |
245 | } |
374 | } |
246 | void __intel_ring_advance(struct intel_ring_buffer *ring); |
375 | void __intel_ring_advance(struct intel_engine_cs *ring); |
247 | 376 | ||
248 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
377 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
249 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno); |
378 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); |
250 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
379 | int intel_ring_flush_all_caches(struct intel_engine_cs *ring); |
251 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); |
380 | int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring); |
252 | 381 | ||
253 | int intel_init_render_ring_buffer(struct drm_device *dev); |
382 | int intel_init_render_ring_buffer(struct drm_device *dev); |
254 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
383 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
- | 384 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
|
255 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
385 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
256 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
386 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
257 | 387 | ||
258 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
388 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
259 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
389 | void intel_ring_setup_status_page(struct intel_engine_cs *ring); |
260 | 390 | ||
261 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
391 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
262 | { |
392 | { |
263 | return ring->tail; |
393 | return ringbuf->tail; |
264 | } |
394 | } |
265 | 395 | ||
266 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
396 | static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring) |
267 | { |
397 | { |
268 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
398 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
269 | return ring->outstanding_lazy_seqno; |
399 | return ring->outstanding_lazy_seqno; |
270 | } |
400 | } |
271 | 401 | ||
272 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
402 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno) |
273 | { |
403 | { |
274 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
404 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
275 | ring->trace_irq_seqno = seqno; |
405 | ring->trace_irq_seqno = seqno; |
276 | } |
406 | } |
277 | 407 | ||
278 | /* DRI warts */ |
408 | /* DRI warts */ |
279 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); |
409 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); |
280 | 410 | ||
281 | #endif /* _INTEL_RINGBUFFER_H_ */><>>><> |
411 | #endif /* _INTEL_RINGBUFFER_H_ */><>>><> |