WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.h


#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_
 
/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64
 
struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};
 
#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
 
#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
 
#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
 
#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
 
#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 
enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};
 
struct intel_ring_hangcheck {
	bool deadlock;
	u32 seqno;
	u32 acthd;
	int score;
	enum intel_ring_hangcheck_action action;
};
 
struct  intel_ring_buffer {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
	} id;
#define I915_NUM_RINGS 4
	u32		mmio_base;
	void		__iomem *virtual_start;
	struct		drm_device *dev;
	struct		drm_i915_gem_object *obj;
 
	u32		head;
	u32		tail;
	int		space;
	int		size;
	int		effective_size;
	struct intel_hw_status_page status_page;
 
	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32		last_retired_head;
 
	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	u32		sync_seqno[I915_NUM_RINGS-1];
	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
	void		(*irq_put)(struct intel_ring_buffer *ring);
 
	int		(*init)(struct intel_ring_buffer *ring);
 
	void		(*write_tail)(struct intel_ring_buffer *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_ring_buffer *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_ring_buffer *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_ring_buffer *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_ring_buffer *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
					       u32 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_ring_buffer *ring);
	int		(*sync_to)(struct intel_ring_buffer *ring,
				   struct intel_ring_buffer *to,
				   u32 seqno);
 
	/* our mbox written by others */
	u32		semaphore_register[I915_NUM_RINGS];
	/* mboxes this ring signals to */
	u32		signal_mbox[I915_NUM_RINGS];
 
	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;
 
	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;
 
	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *preallocated_lazy_request;
	u32 outstanding_lazy_seqno;
	bool gpu_caches_dirty;
	bool fbc_dirty;
 
	wait_queue_head_t irq_queue;
 
	/**
	 * Do an explicit TLB flush before MI_SET_CONTEXT
	 */
	bool itlb_before_ctx_switch;
	struct i915_hw_context *default_context;
	struct i915_hw_context *last_context;
 
	struct intel_ring_hangcheck hangcheck;
 
	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;
};
 
static inline bool
intel_ring_initialized(struct intel_ring_buffer *ring)
{
	return ring->obj != NULL;
}
 
static inline unsigned
intel_ring_flag(struct intel_ring_buffer *ring)
{
	return 1 << ring->id;
}
 
static inline u32
intel_ring_sync_index(struct intel_ring_buffer *ring,
		      struct intel_ring_buffer *other)
{
	int idx;
 
	/*
	 * cs -> 0 = vcs, 1 = bcs
	 * vcs -> 0 = bcs, 1 = cs,
	 * bcs -> 0 = cs, 1 = vcs.
	 */
 
	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;
 
	return idx;
}
 
static inline u32
intel_read_status_page(struct intel_ring_buffer *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}
 
static inline void
intel_write_status_page(struct intel_ring_buffer *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}
 
/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 
int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
static inline void intel_ring_emit(struct intel_ring_buffer *ring,
				   u32 data)
{
	iowrite32(data, ring->virtual_start + ring->tail);
	ring->tail += 4;
}
static inline void intel_ring_advance(struct intel_ring_buffer *ring)
{
	ring->tail &= ring->size - 1;
}
void __intel_ring_advance(struct intel_ring_buffer *ring);
 
int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 
int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);
 
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 
static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
{
	return ring->tail;
}
 
static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
{
	BUG_ON(ring->outstanding_lazy_seqno == 0);
	return ring->outstanding_lazy_seqno;
}
 
static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}
 
/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 
#endif /* _INTEL_RINGBUFFER_H_ */

Rev 4104	Rev 4560
1	#ifndef _INTEL_RINGBUFFER_H_	1	#ifndef _INTEL_RINGBUFFER_H_
2	#define _INTEL_RINGBUFFER_H_	2	#define _INTEL_RINGBUFFER_H_
3		3
4	/*	4	/*
5	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"	5	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
6	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"	6	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
7	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"	7	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
8	*	8	*
9	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same	9	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
10	* cacheline, the Head Pointer must not be greater than the Tail	10	* cacheline, the Head Pointer must not be greater than the Tail
11	* Pointer."	11	* Pointer."
12	*/	12	*/
13	#define I915_RING_FREE_SPACE 64	13	#define I915_RING_FREE_SPACE 64
14		14
15	struct intel_hw_status_page {	15	struct intel_hw_status_page {
16	u32 *page_addr;	16	u32 *page_addr;
17	unsigned int gfx_addr;	17	unsigned int gfx_addr;
18	struct drm_i915_gem_object *obj;	18	struct drm_i915_gem_object *obj;
19	};	19	};
20		20
21	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))	21	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
22	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)	22	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
23		23
24	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))	24	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
25	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)	25	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
26		26
27	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))	27	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
28	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)	28	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
29		29
30	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))	30	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
31	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)	31	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
32		32
33	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))	33	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)	34	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
35		35
36	enum intel_ring_hangcheck_action {	36	enum intel_ring_hangcheck_action {
-		37	HANGCHECK_IDLE = 0,
37	HANGCHECK_WAIT,	38	HANGCHECK_WAIT,
38	HANGCHECK_ACTIVE,	39	HANGCHECK_ACTIVE,
39	HANGCHECK_KICK,	40	HANGCHECK_KICK,
40	HANGCHECK_HUNG,	41	HANGCHECK_HUNG,
41	};	42	};
42		43
43	struct intel_ring_hangcheck {	44	struct intel_ring_hangcheck {
44	bool deadlock;	45	bool deadlock;
45	u32 seqno;	46	u32 seqno;
46	u32 acthd;	47	u32 acthd;
47	int score;	48	int score;
48	enum intel_ring_hangcheck_action action;	49	enum intel_ring_hangcheck_action action;
49	};	50	};
50		51
51	struct intel_ring_buffer {	52	struct intel_ring_buffer {
52	const char *name;	53	const char *name;
53	enum intel_ring_id {	54	enum intel_ring_id {
54	RCS = 0x0,	55	RCS = 0x0,
55	VCS,	56	VCS,
56	BCS,	57	BCS,
57	VECS,	58	VECS,
58	} id;	59	} id;
59	#define I915_NUM_RINGS 4	60	#define I915_NUM_RINGS 4
60	u32 mmio_base;	61	u32 mmio_base;
61	void __iomem *virtual_start;	62	void __iomem *virtual_start;
62	struct drm_device *dev;	63	struct drm_device *dev;
63	struct drm_i915_gem_object *obj;	64	struct drm_i915_gem_object *obj;
64		65
65	u32 head;	66	u32 head;
66	u32 tail;	67	u32 tail;
67	int space;	68	int space;
68	int size;	69	int size;
69	int effective_size;	70	int effective_size;
70	struct intel_hw_status_page status_page;	71	struct intel_hw_status_page status_page;
71		72
72	/** We track the position of the requests in the ring buffer, and	73	/** We track the position of the requests in the ring buffer, and
73	* when each is retired we increment last_retired_head as the GPU	74	* when each is retired we increment last_retired_head as the GPU
74	* must have finished processing the request and so we know we	75	* must have finished processing the request and so we know we
75	* can advance the ringbuffer up to that position.	76	* can advance the ringbuffer up to that position.
76	*	77	*
77	* last_retired_head is set to -1 after the value is consumed so	78	* last_retired_head is set to -1 after the value is consumed so
78	* we can detect new retirements.	79	* we can detect new retirements.
79	*/	80	*/
80	u32 last_retired_head;	81	u32 last_retired_head;
81		82
82	unsigned irq_refcount; /* protected by dev_priv->irq_lock */	83	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
83	u32 irq_enable_mask; /* bitmask to enable ring interrupt */	84	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
84	u32 trace_irq_seqno;	85	u32 trace_irq_seqno;
85	u32 sync_seqno[I915_NUM_RINGS-1];	86	u32 sync_seqno[I915_NUM_RINGS-1];
86	bool __must_check (irq_get)(struct intel_ring_buffer ring);	87	bool __must_check (irq_get)(struct intel_ring_buffer ring);
87	void (irq_put)(struct intel_ring_buffer ring);	88	void (irq_put)(struct intel_ring_buffer ring);
88		89
89	int (init)(struct intel_ring_buffer ring);	90	int (init)(struct intel_ring_buffer ring);
90		91
91	void (write_tail)(struct intel_ring_buffer ring,	92	void (write_tail)(struct intel_ring_buffer ring,
92	u32 value);	93	u32 value);
93	int __must_check (flush)(struct intel_ring_buffer ring,	94	int __must_check (flush)(struct intel_ring_buffer ring,
94	u32 invalidate_domains,	95	u32 invalidate_domains,
95	u32 flush_domains);	96	u32 flush_domains);
96	int (add_request)(struct intel_ring_buffer ring);	97	int (add_request)(struct intel_ring_buffer ring);
97	/* Some chipsets are not quite as coherent as advertised and need	98	/* Some chipsets are not quite as coherent as advertised and need
98	* an expensive kick to force a true read of the up-to-date seqno.	99	* an expensive kick to force a true read of the up-to-date seqno.
99	* However, the up-to-date seqno is not always required and the last	100	* However, the up-to-date seqno is not always required and the last
100	* seen value is good enough. Note that the seqno will always be	101	* seen value is good enough. Note that the seqno will always be
101	* monotonic, even if not coherent.	102	* monotonic, even if not coherent.
102	*/	103	*/
103	u32 (get_seqno)(struct intel_ring_buffer ring,	104	u32 (get_seqno)(struct intel_ring_buffer ring,
104	bool lazy_coherency);	105	bool lazy_coherency);
105	void (set_seqno)(struct intel_ring_buffer ring,	106	void (set_seqno)(struct intel_ring_buffer ring,
106	u32 seqno);	107	u32 seqno);
107	int (dispatch_execbuffer)(struct intel_ring_buffer ring,	108	int (dispatch_execbuffer)(struct intel_ring_buffer ring,
108	u32 offset, u32 length,	109	u32 offset, u32 length,
109	unsigned flags);	110	unsigned flags);
110	#define I915_DISPATCH_SECURE 0x1	111	#define I915_DISPATCH_SECURE 0x1
111	#define I915_DISPATCH_PINNED 0x2	112	#define I915_DISPATCH_PINNED 0x2
112	void (cleanup)(struct intel_ring_buffer ring);	113	void (cleanup)(struct intel_ring_buffer ring);
113	int (sync_to)(struct intel_ring_buffer ring,	114	int (sync_to)(struct intel_ring_buffer ring,
114	struct intel_ring_buffer *to,	115	struct intel_ring_buffer *to,
115	u32 seqno);	116	u32 seqno);
116		117
117	/* our mbox written by others */	118	/* our mbox written by others */
118	u32 semaphore_register[I915_NUM_RINGS];	119	u32 semaphore_register[I915_NUM_RINGS];
119	/* mboxes this ring signals to */	120	/* mboxes this ring signals to */
120	u32 signal_mbox[I915_NUM_RINGS];	121	u32 signal_mbox[I915_NUM_RINGS];
121		122
122	/**	123	/**
123	* List of objects currently involved in rendering from the	124	* List of objects currently involved in rendering from the
124	* ringbuffer.	125	* ringbuffer.
125	*	126	*
126	* Includes buffers having the contents of their GPU caches	127	* Includes buffers having the contents of their GPU caches
127	* flushed, not necessarily primitives. last_rendering_seqno	128	* flushed, not necessarily primitives. last_rendering_seqno
128	* represents when the rendering involved will be completed.	129	* represents when the rendering involved will be completed.
129	*	130	*
130	* A reference is held on the buffer while on this list.	131	* A reference is held on the buffer while on this list.
131	*/	132	*/
132	struct list_head active_list;	133	struct list_head active_list;
133		134
134	/**	135	/**
135	* List of breadcrumbs associated with GPU requests currently	136	* List of breadcrumbs associated with GPU requests currently
136	* outstanding.	137	* outstanding.
137	*/	138	*/
138	struct list_head request_list;	139	struct list_head request_list;
139		140
140	/**	141	/**
141	* Do we have some not yet emitted requests outstanding?	142	* Do we have some not yet emitted requests outstanding?
142	*/	143	*/
-		144	struct drm_i915_gem_request *preallocated_lazy_request;
143	u32 outstanding_lazy_request;	145	u32 outstanding_lazy_seqno;
144	bool gpu_caches_dirty;	146	bool gpu_caches_dirty;
145	bool fbc_dirty;	147	bool fbc_dirty;
146		148
147	wait_queue_head_t irq_queue;	149	wait_queue_head_t irq_queue;
148		150
149	/**	151	/**
150	* Do an explicit TLB flush before MI_SET_CONTEXT	152	* Do an explicit TLB flush before MI_SET_CONTEXT
151	*/	153	*/
152	bool itlb_before_ctx_switch;	154	bool itlb_before_ctx_switch;
153	struct i915_hw_context *default_context;	155	struct i915_hw_context *default_context;
154	struct i915_hw_context *last_context;	156	struct i915_hw_context *last_context;
155		157
156	struct intel_ring_hangcheck hangcheck;	158	struct intel_ring_hangcheck hangcheck;
157		159
158	struct {	160	struct {
159	struct drm_i915_gem_object *obj;	161	struct drm_i915_gem_object *obj;
160	u32 gtt_offset;	162	u32 gtt_offset;
161	volatile u32 *cpu_page;	163	volatile u32 *cpu_page;
162	} scratch;	164	} scratch;
163	};	165	};
164		166
165	static inline bool	167	static inline bool
166	intel_ring_initialized(struct intel_ring_buffer *ring)	168	intel_ring_initialized(struct intel_ring_buffer *ring)
167	{	169	{
168	return ring->obj != NULL;	170	return ring->obj != NULL;
169	}	171	}
170		172
171	static inline unsigned	173	static inline unsigned
172	intel_ring_flag(struct intel_ring_buffer *ring)	174	intel_ring_flag(struct intel_ring_buffer *ring)
173	{	175	{
174	return 1 << ring->id;	176	return 1 << ring->id;
175	}	177	}
176		178
177	static inline u32	179	static inline u32
178	intel_ring_sync_index(struct intel_ring_buffer *ring,	180	intel_ring_sync_index(struct intel_ring_buffer *ring,
179	struct intel_ring_buffer *other)	181	struct intel_ring_buffer *other)
180	{	182	{
181	int idx;	183	int idx;
182		184
183	/*	185	/*
184	* cs -> 0 = vcs, 1 = bcs	186	* cs -> 0 = vcs, 1 = bcs
185	* vcs -> 0 = bcs, 1 = cs,	187	* vcs -> 0 = bcs, 1 = cs,
186	* bcs -> 0 = cs, 1 = vcs.	188	* bcs -> 0 = cs, 1 = vcs.
187	*/	189	*/
188		190
189	idx = (other - ring) - 1;	191	idx = (other - ring) - 1;
190	if (idx < 0)	192	if (idx < 0)
191	idx += I915_NUM_RINGS;	193	idx += I915_NUM_RINGS;
192		194
193	return idx;	195	return idx;
194	}	196	}
195		197
196	static inline u32	198	static inline u32
197	intel_read_status_page(struct intel_ring_buffer *ring,	199	intel_read_status_page(struct intel_ring_buffer *ring,
198	int reg)	200	int reg)
199	{	201	{
200	/* Ensure that the compiler doesn't optimize away the load. */	202	/* Ensure that the compiler doesn't optimize away the load. */
201	barrier();	203	barrier();
202	return ring->status_page.page_addr[reg];	204	return ring->status_page.page_addr[reg];
203	}	205	}
204		206
205	static inline void	207	static inline void
206	intel_write_status_page(struct intel_ring_buffer *ring,	208	intel_write_status_page(struct intel_ring_buffer *ring,
207	int reg, u32 value)	209	int reg, u32 value)
208	{	210	{
209	ring->status_page.page_addr[reg] = value;	211	ring->status_page.page_addr[reg] = value;
210	}	212	}
211		213
212	/**	214	/**
213	* Reads a dword out of the status page, which is written to from the command	215	* Reads a dword out of the status page, which is written to from the command
214	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or	216	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
215	* MI_STORE_DATA_IMM.	217	* MI_STORE_DATA_IMM.
216	*	218	*
217	* The following dwords have a reserved meaning:	219	* The following dwords have a reserved meaning:
218	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.	220	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
219	* 0x04: ring 0 head pointer	221	* 0x04: ring 0 head pointer
220	* 0x05: ring 1 head pointer (915-class)	222	* 0x05: ring 1 head pointer (915-class)
221	* 0x06: ring 2 head pointer (915-class)	223	* 0x06: ring 2 head pointer (915-class)
222	* 0x10-0x1b: Context status DWords (GM45)	224	* 0x10-0x1b: Context status DWords (GM45)
223	* 0x1f: Last written status offset. (GM45)	225	* 0x1f: Last written status offset. (GM45)
224	*	226	*
225	* The area from dword 0x20 to 0x3ff is available for driver usage.	227	* The area from dword 0x20 to 0x3ff is available for driver usage.
226	*/	228	*/
227	#define I915_GEM_HWS_INDEX 0x20	229	#define I915_GEM_HWS_INDEX 0x20
228	#define I915_GEM_HWS_SCRATCH_INDEX 0x30	230	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
229	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)	231	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
230		232
231	void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);	233	void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
232		234
233	int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);	235	int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
234	static inline void intel_ring_emit(struct intel_ring_buffer *ring,	236	static inline void intel_ring_emit(struct intel_ring_buffer *ring,
235	u32 data)	237	u32 data)
236	{	238	{
237	iowrite32(data, ring->virtual_start + ring->tail);	239	iowrite32(data, ring->virtual_start + ring->tail);
238	ring->tail += 4;	240	ring->tail += 4;
239	}	241	}
-		242	static inline void intel_ring_advance(struct intel_ring_buffer *ring)
-		243	{
-		244	ring->tail &= ring->size - 1;
-		245	}
240	void intel_ring_advance(struct intel_ring_buffer *ring);	246	void __intel_ring_advance(struct intel_ring_buffer *ring);
-		247
241	int __must_check intel_ring_idle(struct intel_ring_buffer *ring);	248	int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
242	void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);	249	void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
243	int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);	250	int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
244	int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);	251	int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
245		252
246	int intel_init_render_ring_buffer(struct drm_device *dev);	253	int intel_init_render_ring_buffer(struct drm_device *dev);
247	int intel_init_bsd_ring_buffer(struct drm_device *dev);	254	int intel_init_bsd_ring_buffer(struct drm_device *dev);
248	int intel_init_blt_ring_buffer(struct drm_device *dev);	255	int intel_init_blt_ring_buffer(struct drm_device *dev);
249	int intel_init_vebox_ring_buffer(struct drm_device *dev);	256	int intel_init_vebox_ring_buffer(struct drm_device *dev);
250		257
251	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);	258	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
252	void intel_ring_setup_status_page(struct intel_ring_buffer *ring);	259	void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
253		260
254	static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)	261	static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
255	{	262	{
256	return ring->tail;	263	return ring->tail;
257	}	264	}
258		265
259	static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)	266	static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
260	{	267	{
261	BUG_ON(ring->outstanding_lazy_request == 0);	268	BUG_ON(ring->outstanding_lazy_seqno == 0);
262	return ring->outstanding_lazy_request;	269	return ring->outstanding_lazy_seqno;
263	}	270	}
264		271
265	static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)	272	static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
266	{	273	{
267	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))	274	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
268	ring->trace_irq_seqno = seqno;	275	ring->trace_irq_seqno = seqno;
269	}	276	}
270		277
271	/* DRI warts */	278	/* DRI warts */
272	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);	279	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
273		280
274	#endif /* _INTEL_RINGBUFFER_H_ */	281	#endif /* _INTEL_RINGBUFFER_H_ */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.h – Rev 4104 → 4560