WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.h

 #ifndef _INTEL_RINGBUFFER_H_
 #define _INTEL_RINGBUFFER_H_
-enum {
-    RCS = 0x0,
-    VCS,
-    BCS,
-    I915_NUM_RINGS,
-};
 struct  intel_hw_status_page {
-	u32	__iomem	*page_addr;
+	u32		*page_addr;
 	unsigned int	gfx_addr;
 	struct		drm_i915_gem_object *obj;
 };
 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
 struct  intel_ring_buffer {
 	const char	*name;
 	enum intel_ring_id {
-		RING_RENDER = 0x1,
+		RCS = 0x0,
-		RING_BSD = 0x2,
+		VCS,
-		RING_BLT = 0x4,
+		BCS,
+	} id;
-	} id;
+#define I915_NUM_RINGS 3
 	u32		mmio_base;
 	void		__iomem *virtual_start;
 	struct		drm_device *dev;
 	int		space;
 	int		size;
 	int		effective_size;
 	struct intel_hw_status_page status_page;
+	/** We track the position of the requests in the ring buffer, and
+	 * when each is retired we increment last_retired_head as the GPU
+	 * must have finished processing the request and so we know we
+	 * can advance the ringbuffer up to that position.
+	 *
-	spinlock_t	irq_lock;
+	 * last_retired_head is set to -1 after the value is consumed so
+	 * we can detect new retirements.
-	u32		irq_refcount;
+	 */
+	u32		last_retired_head;
-	u32		irq_mask;
+	u32		irq_refcount;		/* protected by dev_priv->irq_lock */
-	u32		irq_seqno;		/* last seq seem at irq time */
+	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
-	u32		trace_irq_seqno;
-	u32		waiting_seqno;
+	u32		trace_irq_seqno;
 	u32		sync_seqno[I915_NUM_RINGS-1];
 	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
 	void		(*irq_put)(struct intel_ring_buffer *ring);
 	int __must_check (*flush)(struct intel_ring_buffer *ring,
 				  u32	invalidate_domains,
 				  u32	flush_domains);
 	int		(*add_request)(struct intel_ring_buffer *ring,
 				       u32 *seqno);
+	/* Some chipsets are not quite as coherent as advertised and need
+	 * an expensive kick to force a true read of the up-to-date seqno.
+	 * However, the up-to-date seqno is not always required and the last
+	 * seen value is good enough. Note that the seqno will always be
+	 * monotonic, even if not coherent.
+	 */
-	u32		(*get_seqno)(struct intel_ring_buffer *ring);
+	u32		(*get_seqno)(struct intel_ring_buffer *ring,
+				     bool lazy_coherency);
 	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
 					       u32 offset, u32 length);
 	void		(*cleanup)(struct intel_ring_buffer *ring);
 	int		(*sync_to)(struct intel_ring_buffer *ring,
 				   struct intel_ring_buffer *to,
 	 * outstanding.
 	 */
 	struct list_head request_list;
-	/**
-	 * List of objects currently pending a GPU write flush.
-	 *
-	 * All elements on this list will belong to either the
-	 * active_list or flushing_list, last_rendering_seqno can
-	 * be used to differentiate between the two elements.
-	 */
-	struct list_head gpu_write_list;
 	/**
 	 * Do we have some not yet emitted requests outstanding?
 	 */
+	u32 outstanding_lazy_request;
-	u32 outstanding_lazy_request;
+	bool gpu_caches_dirty;
+	wait_queue_head_t irq_queue;
+	/**
+	 * Do an explicit TLB flush before MI_SET_CONTEXT
+	 */
+	bool itlb_before_ctx_switch;
-	wait_queue_head_t irq_queue;
+	struct i915_hw_context *default_context;
-    drm_local_map_t map;
+	struct drm_i915_gem_object *last_context_obj;
+	void *private;
+};
+static inline bool
+intel_ring_initialized(struct intel_ring_buffer *ring)
+{
+	return ring->obj != NULL;
+}
+static inline unsigned
+intel_ring_flag(struct intel_ring_buffer *ring)
+{
-	void *private;
+	return 1 << ring->id;
 };
 static inline u32
 static inline u32
 intel_read_status_page(struct intel_ring_buffer *ring,
 		       int reg)
+{
+	/* Ensure that the compiler doesn't optimize away the load. */
-{
+	barrier();
-	return ioread32(ring->status_page.page_addr + reg);
+	return ring->status_page.page_addr[reg];
+}
 /**
  * 0x10-0x1b: Context status DWords (GM45)
  * 0x1f: Last written status offset. (GM45)
+ *
  * The area from dword 0x20 to 0x3ff is available for driver usage.
  */
-#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
-#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 #define I915_GEM_HWS_INDEX		0x20
-#define I915_BREADCRUMB_INDEX		0x21
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
+}
 void intel_ring_advance(struct intel_ring_buffer *ring);
+u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
-u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
+int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 int intel_init_render_ring_buffer(struct drm_device *dev);
 int intel_init_bsd_ring_buffer(struct drm_device *dev);
+int intel_init_blt_ring_buffer(struct drm_device *dev);
+u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
+void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
-int intel_init_blt_ring_buffer(struct drm_device *dev);
+static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
+{
-u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
+	return ring->tail;
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.h – Rev 2352 → 3031