WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.c


/*
 * Copyright © 2008-2010 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *    Zou Nan hai 
 *    Xiang Hai hao
 *
 */
#define iowrite32(v, addr)      writel((v), (addr))
#define ioread32(addr)          readl(addr)
 
#include "drmP.h"
#include "drm.h"
#include "i915_drv.h"
#include "i915_drm.h"
//#include "i915_trace.h"
#include "intel_drv.h"
 
/*
 * 965+ support PIPE_CONTROL commands, which provide finer grained control
 * over cache flushing.
 */
struct pipe_control {
	struct drm_i915_gem_object *obj;
	volatile u32 *cpu_page;
	u32 gtt_offset;
};
 
static inline int ring_space(struct intel_ring_buffer *ring)
{
	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
	if (space < 0)
		space += ring->size;
	return space;
}
 
static u32 i915_gem_get_seqno(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 seqno;
 
	seqno = dev_priv->next_seqno;
 
	/* reserve 0 for non-seqno */
	if (++dev_priv->next_seqno == 0)
		dev_priv->next_seqno = 1;
 
	return seqno;
}
 
static int
render_ring_flush(struct intel_ring_buffer *ring,
		  u32	invalidate_domains,
		  u32	flush_domains)
{
	struct drm_device *dev = ring->dev;
	u32 cmd;
	int ret;
 
	/*
	 * read/write caches:
	 *
	 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
	 * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
	 * also flushed at 2d versus 3d pipeline switches.
	 *
	 * read-only caches:
	 *
	 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
	 * MI_READ_FLUSH is set, and is always flushed on 965.
	 *
	 * I915_GEM_DOMAIN_COMMAND may not exist?
	 *
	 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
	 * invalidated when MI_EXE_FLUSH is set.
	 *
	 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
	 * invalidated with every MI_FLUSH.
	 *
	 * TLBs:
	 *
	 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
	 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
	 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
	 * are flushed at any MI_FLUSH.
	 */
 
	cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
	if ((invalidate_domains|flush_domains) &
	    I915_GEM_DOMAIN_RENDER)
		cmd &= ~MI_NO_WRITE_FLUSH;
	if (INTEL_INFO(dev)->gen < 4) {
		/*
		 * On the 965, the sampler cache always gets flushed
		 * and this bit is reserved.
		 */
		if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
			cmd |= MI_READ_FLUSH;
	}
	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
		cmd |= MI_EXE_FLUSH;
 
	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
	    (IS_G4X(dev) || IS_GEN5(dev)))
		cmd |= MI_INVALIDATE_ISP;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	return 0;
}
 
/**
 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 * implementing two workarounds on gen6.  From section 1.4.7.1
 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 *
 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 * produced by non-pipelined state commands), software needs to first
 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 * 0.
 *
 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 *
 * And the workaround for these two requires this workaround first:
 *
 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 * BEFORE the pipe-control with a post-sync op and no write-cache
 * flushes.
 *
 * And this last workaround is tricky because of the requirements on
 * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 * volume 2 part 1:
 *
 *     "1 of the following must also be set:
 *      - Render Target Cache Flush Enable ([12] of DW1)
 *      - Depth Cache Flush Enable ([0] of DW1)
 *      - Stall at Pixel Scoreboard ([1] of DW1)
 *      - Depth Stall ([13] of DW1)
 *      - Post-Sync Operation ([13] of DW1)
 *      - Notify Enable ([8] of DW1)"
 *
 * The cache flushes require the workaround flush that triggered this
 * one, so we can't use it.  Depth stall would trigger the same.
 * Post-sync nonzero is what triggered this second workaround, so we
 * can't use that one either.  Notify enable is IRQs, which aren't
 * really our business.  That leaves only stall at scoreboard.
 */
static int
intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc = ring->private;
	u32 scratch_addr = pc->gtt_offset + 128;
	int ret;
 
 
	ret = intel_ring_begin(ring, 6);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
			PIPE_CONTROL_STALL_AT_SCOREBOARD);
	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
	intel_ring_emit(ring, 0); /* low dword */
	intel_ring_emit(ring, 0); /* high dword */
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	ret = intel_ring_begin(ring, 6);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	return 0;
}
 
static int
gen6_render_ring_flush(struct intel_ring_buffer *ring,
                         u32 invalidate_domains, u32 flush_domains)
{
	u32 flags = 0;
	struct pipe_control *pc = ring->private;
	u32 scratch_addr = pc->gtt_offset + 128;
	int ret;
 
	/* Force SNB workarounds for PIPE_CONTROL flushes */
	intel_emit_post_sync_nonzero_flush(ring);
 
	/* Just flush everything.  Experiments have shown that reducing the
	 * number of bits based on the write domains has little performance
	 * impact.
	 */
	flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
	flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
	flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
	flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
	flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
	flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
	flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 
	ret = intel_ring_begin(ring, 6);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
	intel_ring_emit(ring, flags);
	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
	intel_ring_emit(ring, 0); /* lower dword */
	intel_ring_emit(ring, 0); /* uppwer dword */
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	return 0;
}
 
static void ring_write_tail(struct intel_ring_buffer *ring,
			    u32 value)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	I915_WRITE_TAIL(ring, value);
}
 
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
			RING_ACTHD(ring->mmio_base) : ACTHD;
 
	return I915_READ(acthd_reg);
}
 
static int init_ring_common(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj = ring->obj;
	u32 head;
 
	/* Stop the ring if it's running. */
	I915_WRITE_CTL(ring, 0);
	I915_WRITE_HEAD(ring, 0);
	ring->write_tail(ring, 0);
 
	/* Initialize the ring. */
	I915_WRITE_START(ring, obj->gtt_offset);
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
 
	/* G45 ring initialization fails to reset head to zero */
	if (head != 0) {
		DRM_DEBUG_KMS("%s head not reset to zero "
			      "ctl %08x head %08x tail %08x start %08x\n",
			      ring->name,
			      I915_READ_CTL(ring),
			      I915_READ_HEAD(ring),
			      I915_READ_TAIL(ring),
			      I915_READ_START(ring));
 
		I915_WRITE_HEAD(ring, 0);
 
		if (I915_READ_HEAD(ring) & HEAD_ADDR) {
			DRM_ERROR("failed to set %s head to zero "
				  "ctl %08x head %08x tail %08x start %08x\n",
				  ring->name,
				  I915_READ_CTL(ring),
				  I915_READ_HEAD(ring),
				  I915_READ_TAIL(ring),
				  I915_READ_START(ring));
		}
	}
 
	I915_WRITE_CTL(ring,
			((ring->size - PAGE_SIZE) & RING_NR_PAGES)
			| RING_REPORT_64K | RING_VALID);
 
	/* If the head is still not zero, the ring is dead */
	if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
	    I915_READ_START(ring) != obj->gtt_offset ||
	    (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
		DRM_ERROR("%s initialization failed "
				"ctl %08x head %08x tail %08x start %08x\n",
				ring->name,
				I915_READ_CTL(ring),
				I915_READ_HEAD(ring),
				I915_READ_TAIL(ring),
				I915_READ_START(ring));
		return -EIO;
	}
 
    ring->head = I915_READ_HEAD(ring);
    ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
    ring->space = ring_space(ring);
 
 
	return 0;
}
 
static int
init_pipe_control(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc;
	struct drm_i915_gem_object *obj;
	int ret;
 
	if (ring->private)
		return 0;
 
	pc = kmalloc(sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;
 
	obj = i915_gem_alloc_object(ring->dev, 4096);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate seqno page\n");
		ret = -ENOMEM;
		goto err;
	}
 
//   i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
	ret = i915_gem_object_pin(obj, 4096, true);
	if (ret)
		goto err_unref;
 
	pc->gtt_offset = obj->gtt_offset;
    pc->cpu_page =  (void*)MapIoMem(obj->pages[0], 4096, PG_SW);
	if (pc->cpu_page == NULL)
		goto err_unpin;
 
	pc->obj = obj;
	ring->private = pc;
	return 0;
 
err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(&obj->base);
err:
	kfree(pc);
	return ret;
}
 
static void
cleanup_pipe_control(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc = ring->private;
	struct drm_i915_gem_object *obj;
 
	if (!ring->private)
		return;
 
	obj = pc->obj;
//	kunmap(obj->pages[0]);
	i915_gem_object_unpin(obj);
	drm_gem_object_unreference(&obj->base);
 
	kfree(pc);
	ring->private = NULL;
}
 
static int init_render_ring(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret = init_ring_common(ring);
 
	if (INTEL_INFO(dev)->gen > 3) {
		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
		if (IS_GEN6(dev) || IS_GEN7(dev))
			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
		I915_WRITE(MI_MODE, mode);
		if (IS_GEN7(dev))
			I915_WRITE(GFX_MODE_GEN7,
				   GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
				   GFX_MODE_ENABLE(GFX_REPLAY_MODE));
	}
 
	if (INTEL_INFO(dev)->gen >= 5) {
		ret = init_pipe_control(ring);
		if (ret)
			return ret;
	}
 
	if (INTEL_INFO(dev)->gen >= 6) {
		I915_WRITE(INSTPM,
			   INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
	}
 
	return ret;
}
 
static void render_ring_cleanup(struct intel_ring_buffer *ring)
{
	if (!ring->private)
		return;
 
	cleanup_pipe_control(ring);
}
 
static void
update_mboxes(struct intel_ring_buffer *ring,
	    u32 seqno,
	    u32 mmio_offset)
{
	intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
			      MI_SEMAPHORE_GLOBAL_GTT |
			MI_SEMAPHORE_REGISTER |
			MI_SEMAPHORE_UPDATE);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, mmio_offset);
}
 
/**
 * gen6_add_request - Update the semaphore mailbox registers
 *
 * @ring - ring that is adding a request
 * @seqno - return seqno stuck into the ring
 *
 * Update the mailbox registers in the *other* rings with the current seqno.
 * This acts like a signal in the canonical semaphore.
 */
static int
gen6_add_request(struct intel_ring_buffer *ring,
		 u32 *seqno)
{
	u32 mbox1_reg;
	u32 mbox2_reg;
	int ret;
 
	ret = intel_ring_begin(ring, 10);
	if (ret)
		return ret;
 
	mbox1_reg = ring->signal_mbox[0];
	mbox2_reg = ring->signal_mbox[1];
 
	*seqno = i915_gem_get_seqno(ring->dev);
 
	update_mboxes(ring, *seqno, mbox1_reg);
	update_mboxes(ring, *seqno, mbox2_reg);
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, *seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	return 0;
}
 
/**
 * intel_ring_sync - sync the waiter to the signaller on seqno
 *
 * @waiter - ring that is waiting
 * @signaller - ring which has, or will signal
 * @seqno - seqno which the waiter will block on
 */
static int
intel_ring_sync(struct intel_ring_buffer *waiter,
		struct intel_ring_buffer *signaller,
		int ring,
		u32 seqno)
{
	int ret;
	u32 dw1 = MI_SEMAPHORE_MBOX |
		  MI_SEMAPHORE_COMPARE |
		  MI_SEMAPHORE_REGISTER;
 
	ret = intel_ring_begin(waiter, 4);
	if (ret)
		return ret;
 
	intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
	intel_ring_emit(waiter, seqno);
	intel_ring_emit(waiter, 0);
	intel_ring_emit(waiter, MI_NOOP);
	intel_ring_advance(waiter);
 
	return 0;
}
 
/* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
int
render_ring_sync_to(struct intel_ring_buffer *waiter,
		    struct intel_ring_buffer *signaller,
		    u32 seqno)
{
//   WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
	return intel_ring_sync(waiter,
			       signaller,
			       RCS,
			       seqno);
}
 
/* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
int
gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
		      struct intel_ring_buffer *signaller,
		      u32 seqno)
{
//   WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
	return intel_ring_sync(waiter,
			       signaller,
			       VCS,
			       seqno);
}
 
/* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
int
gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
		      struct intel_ring_buffer *signaller,
		      u32 seqno)
{
//   WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
	return intel_ring_sync(waiter,
			       signaller,
			       BCS,
			       seqno);
}
 
 
 
#define PIPE_CONTROL_FLUSH(ring__, addr__)					\
do {									\
	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
		 PIPE_CONTROL_DEPTH_STALL);				\
	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
	intel_ring_emit(ring__, 0);							\
	intel_ring_emit(ring__, 0);							\
} while (0)
 
static int
pc_render_add_request(struct intel_ring_buffer *ring,
		      u32 *result)
{
	struct drm_device *dev = ring->dev;
	u32 seqno = i915_gem_get_seqno(dev);
	struct pipe_control *pc = ring->private;
	u32 scratch_addr = pc->gtt_offset + 128;
	int ret;
 
	/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
	 * incoherent with writes to memory, i.e. completely fubar,
	 * so we need to use PIPE_NOTIFY instead.
	 *
	 * However, we also need to workaround the qword write
	 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
	 * memory before requesting an interrupt.
	 */
	ret = intel_ring_begin(ring, 32);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
			PIPE_CONTROL_WRITE_FLUSH |
			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, 0);
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128; /* write to separate cachelines */
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
			PIPE_CONTROL_WRITE_FLUSH |
			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
			PIPE_CONTROL_NOTIFY);
	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, 0);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
static int
render_ring_add_request(struct intel_ring_buffer *ring,
			u32 *result)
{
	struct drm_device *dev = ring->dev;
	u32 seqno = i915_gem_get_seqno(dev);
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
static u32
gen6_ring_get_seqno(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
 
	/* Workaround to force correct ordering between irq and seqno writes on
	 * ivb (and maybe also on snb) by reading from a CS register (like
	 * ACTHD) before reading the status page. */
	if (IS_GEN7(dev))
		intel_ring_get_active_head(ring);
	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}
 
static u32
ring_get_seqno(struct intel_ring_buffer *ring)
{
	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}
 
static u32
pc_render_get_seqno(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc = ring->private;
	return pc->cpu_page[0];
}
 
static void
ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->gt_irq_mask &= ~mask;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}
 
static void
ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->gt_irq_mask |= mask;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}
 
static void
i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->irq_mask &= ~mask;
	I915_WRITE(IMR, dev_priv->irq_mask);
	POSTING_READ(IMR);
}
 
static void
i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->irq_mask |= mask;
	I915_WRITE(IMR, dev_priv->irq_mask);
	POSTING_READ(IMR);
}
 
static bool
render_ring_get_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
		return false;
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_enable_irq(dev_priv,
					    GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
		else
			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
 
static void
render_ring_put_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_disable_irq(dev_priv,
					     GT_USER_INTERRUPT |
					     GT_PIPE_NOTIFY);
		else
			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
}
 
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	u32 mmio = 0;
 
	/* The ring status page addresses are no longer next to the rest of
	 * the ring registers as of gen7.
	 */
	if (IS_GEN7(dev)) {
		switch (ring->id) {
		case RING_RENDER:
			mmio = RENDER_HWS_PGA_GEN7;
			break;
		case RING_BLT:
			mmio = BLT_HWS_PGA_GEN7;
			break;
		case RING_BSD:
			mmio = BSD_HWS_PGA_GEN7;
			break;
		}
	} else if (IS_GEN6(ring->dev)) {
		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
	} else {
		mmio = RING_HWS_PGA(ring->mmio_base);
	}
 
	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
	POSTING_READ(mmio);
}
 
static int
bsd_ring_flush(struct intel_ring_buffer *ring,
	       u32     invalidate_domains,
	       u32     flush_domains)
{
	int ret;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, MI_FLUSH);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
static int
ring_add_request(struct intel_ring_buffer *ring,
		 u32 *result)
{
	u32 seqno;
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	seqno = i915_gem_get_seqno(ring->dev);
 
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
static bool
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
	       return false;
 
	/* It looks like we need to prevent the gt from suspending while waiting
	 * for an notifiy irq, otherwise irqs seem to get lost on at least the
	 * blt/bsd rings on ivb. */
	if (IS_GEN7(dev))
		gen6_gt_force_wake_get(dev_priv);
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		ring->irq_mask &= ~rflag;
		I915_WRITE_IMR(ring, ring->irq_mask);
		ironlake_enable_irq(dev_priv, gflag);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
 
static void
gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		ring->irq_mask |= rflag;
		I915_WRITE_IMR(ring, ring->irq_mask);
		ironlake_disable_irq(dev_priv, gflag);
	}
	spin_unlock(&ring->irq_lock);
 
	if (IS_GEN7(dev))
		gen6_gt_force_wake_put(dev_priv);
}
 
static bool
bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
		return false;
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		if (IS_G4X(dev))
			i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
		else
			ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
static void
bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		if (IS_G4X(dev))
			i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
		else
			ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
}
 
static int
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
{
	int ret;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring,
			MI_BATCH_BUFFER_START | (2 << 6) |
			MI_BATCH_NON_SECURE_I965);
	intel_ring_emit(ring, offset);
	intel_ring_advance(ring);
 
	return 0;
}
 
static int
render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
				u32 offset, u32 len)
{
	struct drm_device *dev = ring->dev;
	int ret;
 
	if (IS_I830(dev) || IS_845G(dev)) {
		ret = intel_ring_begin(ring, 4);
		if (ret)
			return ret;
 
		intel_ring_emit(ring, MI_BATCH_BUFFER);
		intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
		intel_ring_emit(ring, offset + len - 8);
		intel_ring_emit(ring, 0);
	} else {
		ret = intel_ring_begin(ring, 2);
		if (ret)
			return ret;
 
		if (INTEL_INFO(dev)->gen >= 4) {
			intel_ring_emit(ring,
					MI_BATCH_BUFFER_START | (2 << 6) |
					MI_BATCH_NON_SECURE_I965);
			intel_ring_emit(ring, offset);
		} else {
			intel_ring_emit(ring,
					MI_BATCH_BUFFER_START | (2 << 6));
			intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
		}
	}
	intel_ring_advance(ring);
 
	return 0;
}
 
static void cleanup_status_page(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj;
 
	obj = ring->status_page.obj;
	if (obj == NULL)
		return;
 
	kunmap(obj->pages[0]);
    i915_gem_object_unpin(obj);
	drm_gem_object_unreference(&obj->base);
	ring->status_page.obj = NULL;
 
	memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
}
 
static int init_status_page(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret;
 
	obj = i915_gem_alloc_object(dev, 4096);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate status page\n");
		ret = -ENOMEM;
		goto err;
	}
 
//    i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
	ret = i915_gem_object_pin(obj, 4096, true);
	if (ret != 0) {
		goto err_unref;
	}
 
	ring->status_page.gfx_addr = obj->gtt_offset;
    ring->status_page.page_addr = MapIoMem(obj->pages[0], 4096, PG_SW);
	if (ring->status_page.page_addr == NULL) {
		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
		goto err_unpin;
	}
	ring->status_page.obj = obj;
	memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 
	intel_ring_setup_status_page(ring);
	DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
			ring->name, ring->status_page.gfx_addr);
 
	return 0;
 
err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(&obj->base);
err:
	return ret;
}
 
int intel_init_ring_buffer(struct drm_device *dev,
			   struct intel_ring_buffer *ring)
{
	struct drm_i915_gem_object *obj;
	int ret;
 
	ring->dev = dev;
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
	INIT_LIST_HEAD(&ring->gpu_write_list);
 
//   init_waitqueue_head(&ring->irq_queue);
    spin_lock_init(&ring->irq_lock);
    ring->irq_mask = ~0;
 
	if (I915_NEED_GFX_HWS(dev)) {
       ret = init_status_page(ring);
       if (ret)
           return ret;
	}
 
    obj = i915_gem_alloc_object(dev, ring->size);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate ringbuffer\n");
		ret = -ENOMEM;
		goto err_hws;
	}
 
	ring->obj = obj;
 
    ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
	if (ret)
		goto err_unref;
 
	ring->map.size = ring->size;
    ring->map.offset = get_bus_addr() + obj->gtt_offset;
	ring->map.type = 0;
	ring->map.flags = 0;
	ring->map.mtrr = 0;
 
//   drm_core_ioremap_wc(&ring->map, dev);
 
    ring->map.handle = ioremap(ring->map.offset, ring->map.size);
 
	if (ring->map.handle == NULL) {
		DRM_ERROR("Failed to map ringbuffer.\n");
		ret = -EINVAL;
		goto err_unpin;
	}
 
	ring->virtual_start = ring->map.handle;
	ret = ring->init(ring);
	if (ret)
		goto err_unmap;
 
	/* Workaround an erratum on the i830 which causes a hang if
	 * the TAIL pointer points to within the last 2 cachelines
	 * of the buffer.
	 */
	ring->effective_size = ring->size;
	if (IS_I830(ring->dev))
		ring->effective_size -= 128;
 
	return 0;
 
err_unmap:
 
    FreeKernelSpace(ring->virtual_start);
err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(&obj->base);
	ring->obj = NULL;
err_hws:
//   cleanup_status_page(ring);
	return ret;
}
 
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv;
	int ret;
 
	if (ring->obj == NULL)
		return;
 
	/* Disable the ring buffer. The ring must be idle at this point */
	dev_priv = ring->dev->dev_private;
	ret = intel_wait_ring_idle(ring);
	if (ret)
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
			  ring->name, ret);
 
	I915_WRITE_CTL(ring, 0);
 
//   drm_core_ioremapfree(&ring->map, ring->dev);
 
    i915_gem_object_unpin(ring->obj);
	drm_gem_object_unreference(&ring->obj->base);
	ring->obj = NULL;
 
	if (ring->cleanup)
		ring->cleanup(ring);
 
//   cleanup_status_page(ring);
}
 
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
{
	unsigned int *virt;
	int rem = ring->size - ring->tail;
 
    ENTER();
 
	if (ring->space < rem) {
		int ret = intel_wait_ring_buffer(ring, rem);
		if (ret)
			return ret;
	}
 
	virt = (unsigned int *)(ring->virtual_start + ring->tail);
	rem /= 8;
	while (rem--) {
		*virt++ = MI_NOOP;
		*virt++ = MI_NOOP;
	}
 
	ring->tail = 0;
	ring->space = ring_space(ring);
 
    LEAVE();
	return 0;
}
 
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long end;
	u32 head;
 
    ENTER();
 
	/* If the reported head position has wrapped or hasn't advanced,
	 * fallback to the slow and accurate path.
	 */
	head = intel_read_status_page(ring, 4);
	if (head > ring->head) {
		ring->head = head;
		ring->space = ring_space(ring);
		if (ring->space >= n)
        {
            LEAVE();
			return 0;
        };
	}
 
 
 
	end = jiffies + 3 * HZ;
	do {
		ring->head = I915_READ_HEAD(ring);
		ring->space = ring_space(ring);
		if (ring->space >= n) {
//           trace_i915_ring_wait_end(ring);
            LEAVE();
			return 0;
		}
 
		msleep(1);
		if (atomic_read(&dev_priv->mm.wedged))
        {
            LEAVE();
			return -EAGAIN;
        };
	} while (!time_after(jiffies, end));
 
    LEAVE();
 
	return -EBUSY;
}
 
int intel_ring_begin(struct intel_ring_buffer *ring,
		     int num_dwords)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	int n = 4*num_dwords;
	int ret;
 
//   if (unlikely(atomic_read(&dev_priv->mm.wedged)))
//       return -EIO;
 
	if (unlikely(ring->tail + n > ring->effective_size)) {
		ret = intel_wrap_ring_buffer(ring);
		if (unlikely(ret))
			return ret;
	}
 
	if (unlikely(ring->space < n)) {
		ret = intel_wait_ring_buffer(ring, n);
		if (unlikely(ret))
			return ret;
	}
 
	ring->space -= n;
	return 0;
}
 
void intel_ring_advance(struct intel_ring_buffer *ring)
{
	ring->tail &= ring->size - 1;
	ring->write_tail(ring, ring->tail);
}
 
static const struct intel_ring_buffer render_ring = {
	.name			= "render ring",
	.id			= RING_RENDER,
	.mmio_base		= RENDER_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_render_ring,
    .write_tail     = ring_write_tail,
    .flush          = render_ring_flush,
    .add_request        = render_ring_add_request,
    .get_seqno      = ring_get_seqno,
	.irq_get		= render_ring_get_irq,
	.irq_put		= render_ring_put_irq,
   .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
//       .cleanup            = render_ring_cleanup,
	.sync_to		= render_ring_sync_to,
	.semaphore_register	= {MI_SEMAPHORE_SYNC_INVALID,
				   MI_SEMAPHORE_SYNC_RV,
				   MI_SEMAPHORE_SYNC_RB},
	.signal_mbox		= {GEN6_VRSYNC, GEN6_BRSYNC},
};
 
/* ring buffer for bit-stream decoder */
 
static const struct intel_ring_buffer bsd_ring = {
	.name                   = "bsd ring",
	.id			= RING_BSD,
	.mmio_base		= BSD_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_ring_common,
	.write_tail		= ring_write_tail,
    .flush          = bsd_ring_flush,
    .add_request        = ring_add_request,
    .get_seqno      = ring_get_seqno,
	.irq_get		= bsd_ring_get_irq,
	.irq_put		= bsd_ring_put_irq,
   .dispatch_execbuffer    = ring_dispatch_execbuffer,
};
 
 
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
				     u32 value)
{
       drm_i915_private_t *dev_priv = ring->dev->dev_private;
 
       /* Every tail move must follow the sequence below */
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
       I915_WRITE(GEN6_BSD_RNCID, 0x0);
 
       if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
                               GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
                       50))
               DRM_ERROR("timed out waiting for IDLE Indicator\n");
 
       I915_WRITE_TAIL(ring, value);
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
}
 
static int gen6_ring_flush(struct intel_ring_buffer *ring,
			   u32 invalidate, u32 flush)
{
	uint32_t cmd;
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	cmd = MI_FLUSH_DW;
	if (invalidate & I915_GEM_GPU_DOMAINS)
		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
static int
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
			      u32 offset, u32 len)
{
       int ret;
 
       ret = intel_ring_begin(ring, 2);
       if (ret)
	       return ret;
 
       intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
       /* bit0-7 is the length on GEN6+ */
       intel_ring_emit(ring, offset);
       intel_ring_advance(ring);
 
       return 0;
}
 
static bool
gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_USER_INTERRUPT,
				 GEN6_RENDER_USER_INTERRUPT);
}
 
static void
gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_put_irq(ring,
				 GT_USER_INTERRUPT,
				 GEN6_RENDER_USER_INTERRUPT);
}
 
static bool
gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_GEN6_BSD_USER_INTERRUPT,
				 GEN6_BSD_USER_INTERRUPT);
}
 
static void
gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_put_irq(ring,
				 GT_GEN6_BSD_USER_INTERRUPT,
				 GEN6_BSD_USER_INTERRUPT);
}
 
/* ring buffer for Video Codec for Gen6+ */
static const struct intel_ring_buffer gen6_bsd_ring = {
	.name			= "gen6 bsd ring",
	.id			= RING_BSD,
	.mmio_base		= GEN6_BSD_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_ring_common,
	.write_tail		= gen6_bsd_ring_write_tail,
    .flush          = gen6_ring_flush,
    .add_request        = gen6_add_request,
	.get_seqno		= gen6_ring_get_seqno,
	.irq_get		= gen6_bsd_ring_get_irq,
	.irq_put		= gen6_bsd_ring_put_irq,
   .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
	.sync_to		= gen6_bsd_ring_sync_to,
	.semaphore_register	= {MI_SEMAPHORE_SYNC_VR,
				   MI_SEMAPHORE_SYNC_INVALID,
				   MI_SEMAPHORE_SYNC_VB},
	.signal_mbox		= {GEN6_RVSYNC, GEN6_BVSYNC},
};
 
/* Blitter support (SandyBridge+) */
 
static bool
blt_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_BLT_USER_INTERRUPT,
				 GEN6_BLITTER_USER_INTERRUPT);
}
 
static void
blt_ring_put_irq(struct intel_ring_buffer *ring)
{
	gen6_ring_put_irq(ring,
			  GT_BLT_USER_INTERRUPT,
			  GEN6_BLITTER_USER_INTERRUPT);
}
 
 
/* Workaround for some stepping of SNB,
 * each time when BLT engine ring tail moved,
 * the first command in the ring to be parsed
 * should be MI_BATCH_BUFFER_START
 */
#define NEED_BLT_WORKAROUND(dev) \
	(IS_GEN6(dev) && (dev->pdev->revision < 8))
 
static inline struct drm_i915_gem_object *
to_blt_workaround(struct intel_ring_buffer *ring)
{
	return ring->private;
}
 
static int blt_ring_init(struct intel_ring_buffer *ring)
{
	if (NEED_BLT_WORKAROUND(ring->dev)) {
		struct drm_i915_gem_object *obj;
		u32 *ptr;
		int ret;
 
		obj = i915_gem_alloc_object(ring->dev, 4096);
		if (obj == NULL)
			return -ENOMEM;
 
		ret = i915_gem_object_pin(obj, 4096, true);
		if (ret) {
			drm_gem_object_unreference(&obj->base);
			return ret;
		}
 
        ptr = MapIoMem(obj->pages[0], 4096, PG_SW);
        obj->mapped = ptr;
 
		*ptr++ = MI_BATCH_BUFFER_END;
 
		*ptr++ = MI_NOOP;
 
		ret = i915_gem_object_set_to_gtt_domain(obj, false);
		if (ret) {
           i915_gem_object_unpin(obj);
			drm_gem_object_unreference(&obj->base);
        	FreeKernelSpace(ptr);
        	obj->mapped = NULL;
			return ret;
		}
        FreeKernelSpace(ptr);
        obj->mapped = NULL;
 
		ring->private = obj;
	}
 
	return init_ring_common(ring);
}
 
static int blt_ring_begin(struct intel_ring_buffer *ring,
			  int num_dwords)
{
	if (ring->private) {
		int ret = intel_ring_begin(ring, num_dwords+2);
		if (ret)
			return ret;
 
		intel_ring_emit(ring, MI_BATCH_BUFFER_START);
		intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
 
		return 0;
	} else
		return intel_ring_begin(ring, 4);
}
 
static int blt_ring_flush(struct intel_ring_buffer *ring,
			  u32 invalidate, u32 flush)
{
	uint32_t cmd;
	int ret;
 
	ret = blt_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	cmd = MI_FLUSH_DW;
	if (invalidate & I915_GEM_DOMAIN_RENDER)
		cmd |= MI_INVALIDATE_TLB;
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
static void blt_ring_cleanup(struct intel_ring_buffer *ring)
{
	if (!ring->private)
		return;
 
	i915_gem_object_unpin(ring->private);
	drm_gem_object_unreference(ring->private);
	ring->private = NULL;
}
 
static const struct intel_ring_buffer gen6_blt_ring = {
       .name			= "blt ring",
       .id			= RING_BLT,
       .mmio_base		= BLT_RING_BASE,
       .size			= 32 * PAGE_SIZE,
       .init			= blt_ring_init,
       .write_tail		= ring_write_tail,
       .flush          = blt_ring_flush,
       .add_request        = gen6_add_request,
	.get_seqno		= gen6_ring_get_seqno,
	.irq_get		= blt_ring_get_irq,
	.irq_put		= blt_ring_put_irq,
       .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
//       .cleanup            = blt_ring_cleanup,
	.sync_to		= gen6_blt_ring_sync_to,
	.semaphore_register	= {MI_SEMAPHORE_SYNC_BR,
				   MI_SEMAPHORE_SYNC_BV,
				   MI_SEMAPHORE_SYNC_INVALID},
	.signal_mbox		= {GEN6_RBSYNC, GEN6_VBSYNC},
};
 
int intel_init_render_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 
	*ring = render_ring;
	if (INTEL_INFO(dev)->gen >= 6) {
       ring->add_request = gen6_add_request;
		ring->flush = gen6_render_ring_flush;
		ring->irq_get = gen6_render_ring_get_irq;
		ring->irq_put = gen6_render_ring_put_irq;
		ring->get_seqno = gen6_ring_get_seqno;
	} else if (IS_GEN5(dev)) {
       ring->add_request = pc_render_add_request;
		ring->get_seqno = pc_render_get_seqno;
	}
 
	if (!I915_NEED_GFX_HWS(dev)) {
		ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
		memset(ring->status_page.page_addr, 0, PAGE_SIZE);
	}
 
	return intel_init_ring_buffer(dev, ring);
}
 
 
int intel_init_bsd_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
 
	if (IS_GEN6(dev) || IS_GEN7(dev))
		*ring = gen6_bsd_ring;
	else
		*ring = bsd_ring;
 
	return intel_init_ring_buffer(dev, ring);
}
 
int intel_init_blt_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
 
	*ring = gen6_blt_ring;
 
	return intel_init_ring_buffer(dev, ring);
}

Rev 2342	Rev 2344
1	/*	1	/*
2	* Copyright © 2008-2010 Intel Corporation	2	* Copyright © 2008-2010 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	* Zou Nan hai	25	* Zou Nan hai
26	* Xiang Hai hao	26	* Xiang Hai hao
27	*	27	*
28	*/	28	*/
29	#define iowrite32(v, addr) writel((v), (addr))	29	#define iowrite32(v, addr) writel((v), (addr))
30	#define ioread32(addr) readl(addr)	30	#define ioread32(addr) readl(addr)
31		31
32	#include "drmP.h"	32	#include "drmP.h"
33	#include "drm.h"	33	#include "drm.h"
34	#include "i915_drv.h"	34	#include "i915_drv.h"
35	#include "i915_drm.h"	35	#include "i915_drm.h"
36	//#include "i915_trace.h"	36	//#include "i915_trace.h"
37	#include "intel_drv.h"	37	#include "intel_drv.h"
38		38
39	/*	39	/*
40	* 965+ support PIPE_CONTROL commands, which provide finer grained control	40	* 965+ support PIPE_CONTROL commands, which provide finer grained control
41	* over cache flushing.	41	* over cache flushing.
42	*/	42	*/
43	struct pipe_control {	43	struct pipe_control {
44	struct drm_i915_gem_object *obj;	44	struct drm_i915_gem_object *obj;
45	volatile u32 *cpu_page;	45	volatile u32 *cpu_page;
46	u32 gtt_offset;	46	u32 gtt_offset;
47	};	47	};
48		48
49	static inline int ring_space(struct intel_ring_buffer *ring)	49	static inline int ring_space(struct intel_ring_buffer *ring)
50	{	50	{
51	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);	51	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
52	if (space < 0)	52	if (space < 0)
53	space += ring->size;	53	space += ring->size;
54	return space;	54	return space;
55	}	55	}
56		56
57	static u32 i915_gem_get_seqno(struct drm_device *dev)	57	static u32 i915_gem_get_seqno(struct drm_device *dev)
58	{	58	{
59	drm_i915_private_t *dev_priv = dev->dev_private;	59	drm_i915_private_t *dev_priv = dev->dev_private;
60	u32 seqno;	60	u32 seqno;
61		61
62	seqno = dev_priv->next_seqno;	62	seqno = dev_priv->next_seqno;
63		63
64	/* reserve 0 for non-seqno */	64	/* reserve 0 for non-seqno */
65	if (++dev_priv->next_seqno == 0)	65	if (++dev_priv->next_seqno == 0)
66	dev_priv->next_seqno = 1;	66	dev_priv->next_seqno = 1;
67		67
68	return seqno;	68	return seqno;
69	}	69	}
70		70
71	static int	71	static int
72	render_ring_flush(struct intel_ring_buffer *ring,	72	render_ring_flush(struct intel_ring_buffer *ring,
73	u32 invalidate_domains,	73	u32 invalidate_domains,
74	u32 flush_domains)	74	u32 flush_domains)
75	{	75	{
76	struct drm_device *dev = ring->dev;	76	struct drm_device *dev = ring->dev;
77	u32 cmd;	77	u32 cmd;
78	int ret;	78	int ret;
79		79
80	/*	80	/*
81	* read/write caches:	81	* read/write caches:
82	*	82	*
83	* I915_GEM_DOMAIN_RENDER is always invalidated, but is	83	* I915_GEM_DOMAIN_RENDER is always invalidated, but is
84	* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is	84	* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
85	* also flushed at 2d versus 3d pipeline switches.	85	* also flushed at 2d versus 3d pipeline switches.
86	*	86	*
87	* read-only caches:	87	* read-only caches:
88	*	88	*
89	* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if	89	* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
90	* MI_READ_FLUSH is set, and is always flushed on 965.	90	* MI_READ_FLUSH is set, and is always flushed on 965.
91	*	91	*
92	* I915_GEM_DOMAIN_COMMAND may not exist?	92	* I915_GEM_DOMAIN_COMMAND may not exist?
93	*	93	*
94	* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is	94	* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
95	* invalidated when MI_EXE_FLUSH is set.	95	* invalidated when MI_EXE_FLUSH is set.
96	*	96	*
97	* I915_GEM_DOMAIN_VERTEX, which exists on 965, is	97	* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
98	* invalidated with every MI_FLUSH.	98	* invalidated with every MI_FLUSH.
99	*	99	*
100	* TLBs:	100	* TLBs:
101	*	101	*
102	* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND	102	* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
103	* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and	103	* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
104	* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER	104	* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
105	* are flushed at any MI_FLUSH.	105	* are flushed at any MI_FLUSH.
106	*/	106	*/
107		107
108	cmd = MI_FLUSH \| MI_NO_WRITE_FLUSH;	108	cmd = MI_FLUSH \| MI_NO_WRITE_FLUSH;
109	if ((invalidate_domains\|flush_domains) &	109	if ((invalidate_domains\|flush_domains) &
110	I915_GEM_DOMAIN_RENDER)	110	I915_GEM_DOMAIN_RENDER)
111	cmd &= ~MI_NO_WRITE_FLUSH;	111	cmd &= ~MI_NO_WRITE_FLUSH;
112	if (INTEL_INFO(dev)->gen < 4) {	112	if (INTEL_INFO(dev)->gen < 4) {
113	/*	113	/*
114	* On the 965, the sampler cache always gets flushed	114	* On the 965, the sampler cache always gets flushed
115	* and this bit is reserved.	115	* and this bit is reserved.
116	*/	116	*/
117	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)	117	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
118	cmd \|= MI_READ_FLUSH;	118	cmd \|= MI_READ_FLUSH;
119	}	119	}
120	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)	120	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121	cmd \|= MI_EXE_FLUSH;	121	cmd \|= MI_EXE_FLUSH;
122		122
123	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&	123	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124	(IS_G4X(dev) \|\| IS_GEN5(dev)))	124	(IS_G4X(dev) \|\| IS_GEN5(dev)))
125	cmd \|= MI_INVALIDATE_ISP;	125	cmd \|= MI_INVALIDATE_ISP;
126		126
127	ret = intel_ring_begin(ring, 2);	127	ret = intel_ring_begin(ring, 2);
128	if (ret)	128	if (ret)
129	return ret;	129	return ret;
130		130
131	intel_ring_emit(ring, cmd);	131	intel_ring_emit(ring, cmd);
132	intel_ring_emit(ring, MI_NOOP);	132	intel_ring_emit(ring, MI_NOOP);
133	intel_ring_advance(ring);	133	intel_ring_advance(ring);
134		134
135	return 0;	135	return 0;
136	}	136	}
137		137
138	/**	138	/**
139	* Emits a PIPE_CONTROL with a non-zero post-sync operation, for	139	* Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140	* implementing two workarounds on gen6. From section 1.4.7.1	140	* implementing two workarounds on gen6. From section 1.4.7.1
141	* "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:	141	* "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142	*	142	*
143	* [DevSNB-C+{W/A}] Before any depth stall flush (including those	143	* [DevSNB-C+{W/A}] Before any depth stall flush (including those
144	* produced by non-pipelined state commands), software needs to first	144	* produced by non-pipelined state commands), software needs to first
145	* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=	145	* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146	* 0.	146	* 0.
147	*	147	*
148	* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable	148	* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149	* =1, a PIPE_CONTROL with any non-zero post-sync-op is required.	149	* =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150	*	150	*
151	* And the workaround for these two requires this workaround first:	151	* And the workaround for these two requires this workaround first:
152	*	152	*
153	* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent	153	* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154	* BEFORE the pipe-control with a post-sync op and no write-cache	154	* BEFORE the pipe-control with a post-sync op and no write-cache
155	* flushes.	155	* flushes.
156	*	156	*
157	* And this last workaround is tricky because of the requirements on	157	* And this last workaround is tricky because of the requirements on
158	* that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM	158	* that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159	* volume 2 part 1:	159	* volume 2 part 1:
160	*	160	*
161	* "1 of the following must also be set:	161	* "1 of the following must also be set:
162	* - Render Target Cache Flush Enable ([12] of DW1)	162	* - Render Target Cache Flush Enable ([12] of DW1)
163	* - Depth Cache Flush Enable ([0] of DW1)	163	* - Depth Cache Flush Enable ([0] of DW1)
164	* - Stall at Pixel Scoreboard ([1] of DW1)	164	* - Stall at Pixel Scoreboard ([1] of DW1)
165	* - Depth Stall ([13] of DW1)	165	* - Depth Stall ([13] of DW1)
166	* - Post-Sync Operation ([13] of DW1)	166	* - Post-Sync Operation ([13] of DW1)
167	* - Notify Enable ([8] of DW1)"	167	* - Notify Enable ([8] of DW1)"
168	*	168	*
169	* The cache flushes require the workaround flush that triggered this	169	* The cache flushes require the workaround flush that triggered this
170	* one, so we can't use it. Depth stall would trigger the same.	170	* one, so we can't use it. Depth stall would trigger the same.
171	* Post-sync nonzero is what triggered this second workaround, so we	171	* Post-sync nonzero is what triggered this second workaround, so we
172	* can't use that one either. Notify enable is IRQs, which aren't	172	* can't use that one either. Notify enable is IRQs, which aren't
173	* really our business. That leaves only stall at scoreboard.	173	* really our business. That leaves only stall at scoreboard.
174	*/	174	*/
175	static int	175	static int
176	intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)	176	intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177	{	177	{
178	struct pipe_control *pc = ring->private;	178	struct pipe_control *pc = ring->private;
179	u32 scratch_addr = pc->gtt_offset + 128;	179	u32 scratch_addr = pc->gtt_offset + 128;
180	int ret;	180	int ret;
181		181
182		182
183	ret = intel_ring_begin(ring, 6);	183	ret = intel_ring_begin(ring, 6);
184	if (ret)	184	if (ret)
185	return ret;	185	return ret;
186		186
187	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));	187	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL \|	188	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL \|
189	PIPE_CONTROL_STALL_AT_SCOREBOARD);	189	PIPE_CONTROL_STALL_AT_SCOREBOARD);
190	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT); /* address */	190	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT); /* address */
191	intel_ring_emit(ring, 0); /* low dword */	191	intel_ring_emit(ring, 0); /* low dword */
192	intel_ring_emit(ring, 0); /* high dword */	192	intel_ring_emit(ring, 0); /* high dword */
193	intel_ring_emit(ring, MI_NOOP);	193	intel_ring_emit(ring, MI_NOOP);
194	intel_ring_advance(ring);	194	intel_ring_advance(ring);
195		195
196	ret = intel_ring_begin(ring, 6);	196	ret = intel_ring_begin(ring, 6);
197	if (ret)	197	if (ret)
198	return ret;	198	return ret;
199		199
200	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));	200	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);	201	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT); /* address */	202	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT); /* address */
203	intel_ring_emit(ring, 0);	203	intel_ring_emit(ring, 0);
204	intel_ring_emit(ring, 0);	204	intel_ring_emit(ring, 0);
205	intel_ring_emit(ring, MI_NOOP);	205	intel_ring_emit(ring, MI_NOOP);
206	intel_ring_advance(ring);	206	intel_ring_advance(ring);
207		207
208	return 0;	208	return 0;
209	}	209	}
210		210
211	static int	211	static int
212	gen6_render_ring_flush(struct intel_ring_buffer *ring,	212	gen6_render_ring_flush(struct intel_ring_buffer *ring,
213	u32 invalidate_domains, u32 flush_domains)	213	u32 invalidate_domains, u32 flush_domains)
214	{	214	{
215	u32 flags = 0;	215	u32 flags = 0;
216	struct pipe_control *pc = ring->private;	216	struct pipe_control *pc = ring->private;
217	u32 scratch_addr = pc->gtt_offset + 128;	217	u32 scratch_addr = pc->gtt_offset + 128;
218	int ret;	218	int ret;
219		219
220	/* Force SNB workarounds for PIPE_CONTROL flushes */	220	/* Force SNB workarounds for PIPE_CONTROL flushes */
221	intel_emit_post_sync_nonzero_flush(ring);	221	intel_emit_post_sync_nonzero_flush(ring);
222		222
223	/* Just flush everything. Experiments have shown that reducing the	223	/* Just flush everything. Experiments have shown that reducing the
224	* number of bits based on the write domains has little performance	224	* number of bits based on the write domains has little performance
225	* impact.	225	* impact.
226	*/	226	*/
227	flags \|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;	227	flags \|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
228	flags \|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;	228	flags \|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
229	flags \|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;	229	flags \|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
230	flags \|= PIPE_CONTROL_DEPTH_CACHE_FLUSH;	230	flags \|= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
231	flags \|= PIPE_CONTROL_VF_CACHE_INVALIDATE;	231	flags \|= PIPE_CONTROL_VF_CACHE_INVALIDATE;
232	flags \|= PIPE_CONTROL_CONST_CACHE_INVALIDATE;	232	flags \|= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
233	flags \|= PIPE_CONTROL_STATE_CACHE_INVALIDATE;	233	flags \|= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
234		234
235	ret = intel_ring_begin(ring, 6);	235	ret = intel_ring_begin(ring, 6);
236	if (ret)	236	if (ret)
237	return ret;	237	return ret;
238		238
239	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));	239	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
240	intel_ring_emit(ring, flags);	240	intel_ring_emit(ring, flags);
241	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT);	241	intel_ring_emit(ring, scratch_addr \| PIPE_CONTROL_GLOBAL_GTT);
242	intel_ring_emit(ring, 0); /* lower dword */	242	intel_ring_emit(ring, 0); /* lower dword */
243	intel_ring_emit(ring, 0); /* uppwer dword */	243	intel_ring_emit(ring, 0); /* uppwer dword */
244	intel_ring_emit(ring, MI_NOOP);	244	intel_ring_emit(ring, MI_NOOP);
245	intel_ring_advance(ring);	245	intel_ring_advance(ring);
246		246
247	return 0;	247	return 0;
248	}	248	}
249		249
250	static void ring_write_tail(struct intel_ring_buffer *ring,	250	static void ring_write_tail(struct intel_ring_buffer *ring,
251	u32 value)	251	u32 value)
252	{	252	{
253	drm_i915_private_t *dev_priv = ring->dev->dev_private;	253	drm_i915_private_t *dev_priv = ring->dev->dev_private;
254	I915_WRITE_TAIL(ring, value);	254	I915_WRITE_TAIL(ring, value);
255	}	255	}
256		256
257	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)	257	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
258	{	258	{
259	drm_i915_private_t *dev_priv = ring->dev->dev_private;	259	drm_i915_private_t *dev_priv = ring->dev->dev_private;
260	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?	260	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
261	RING_ACTHD(ring->mmio_base) : ACTHD;	261	RING_ACTHD(ring->mmio_base) : ACTHD;
262		262
263	return I915_READ(acthd_reg);	263	return I915_READ(acthd_reg);
264	}	264	}
265		265
266	static int init_ring_common(struct intel_ring_buffer *ring)	266	static int init_ring_common(struct intel_ring_buffer *ring)
267	{	267	{
268	drm_i915_private_t *dev_priv = ring->dev->dev_private;	268	drm_i915_private_t *dev_priv = ring->dev->dev_private;
269	struct drm_i915_gem_object *obj = ring->obj;	269	struct drm_i915_gem_object *obj = ring->obj;
270	u32 head;	270	u32 head;
271		271
272	/* Stop the ring if it's running. */	272	/* Stop the ring if it's running. */
273	I915_WRITE_CTL(ring, 0);	273	I915_WRITE_CTL(ring, 0);
274	I915_WRITE_HEAD(ring, 0);	274	I915_WRITE_HEAD(ring, 0);
275	ring->write_tail(ring, 0);	275	ring->write_tail(ring, 0);
276		276
277	/* Initialize the ring. */	277	/* Initialize the ring. */
278	I915_WRITE_START(ring, obj->gtt_offset);	278	I915_WRITE_START(ring, obj->gtt_offset);
279	head = I915_READ_HEAD(ring) & HEAD_ADDR;	279	head = I915_READ_HEAD(ring) & HEAD_ADDR;
280		280
281	/* G45 ring initialization fails to reset head to zero */	281	/* G45 ring initialization fails to reset head to zero */
282	if (head != 0) {	282	if (head != 0) {
283	DRM_DEBUG_KMS("%s head not reset to zero "	283	DRM_DEBUG_KMS("%s head not reset to zero "
284	"ctl %08x head %08x tail %08x start %08x\n",	284	"ctl %08x head %08x tail %08x start %08x\n",
285	ring->name,	285	ring->name,
286	I915_READ_CTL(ring),	286	I915_READ_CTL(ring),
287	I915_READ_HEAD(ring),	287	I915_READ_HEAD(ring),
288	I915_READ_TAIL(ring),	288	I915_READ_TAIL(ring),
289	I915_READ_START(ring));	289	I915_READ_START(ring));
290		290
291	I915_WRITE_HEAD(ring, 0);	291	I915_WRITE_HEAD(ring, 0);
292		292
293	if (I915_READ_HEAD(ring) & HEAD_ADDR) {	293	if (I915_READ_HEAD(ring) & HEAD_ADDR) {
294	DRM_ERROR("failed to set %s head to zero "	294	DRM_ERROR("failed to set %s head to zero "
295	"ctl %08x head %08x tail %08x start %08x\n",	295	"ctl %08x head %08x tail %08x start %08x\n",
296	ring->name,	296	ring->name,
297	I915_READ_CTL(ring),	297	I915_READ_CTL(ring),
298	I915_READ_HEAD(ring),	298	I915_READ_HEAD(ring),
299	I915_READ_TAIL(ring),	299	I915_READ_TAIL(ring),
300	I915_READ_START(ring));	300	I915_READ_START(ring));
301	}	301	}
302	}	302	}
303		303
304	I915_WRITE_CTL(ring,	304	I915_WRITE_CTL(ring,
305	((ring->size - PAGE_SIZE) & RING_NR_PAGES)	305	((ring->size - PAGE_SIZE) & RING_NR_PAGES)
306	\| RING_REPORT_64K \| RING_VALID);	306	\| RING_REPORT_64K \| RING_VALID);
307		307
308	/* If the head is still not zero, the ring is dead */	308	/* If the head is still not zero, the ring is dead */
309	if ((I915_READ_CTL(ring) & RING_VALID) == 0 \|\|	309	if ((I915_READ_CTL(ring) & RING_VALID) == 0 \|\|
310	I915_READ_START(ring) != obj->gtt_offset \|\|	310	I915_READ_START(ring) != obj->gtt_offset \|\|
311	(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {	311	(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
312	DRM_ERROR("%s initialization failed "	312	DRM_ERROR("%s initialization failed "
313	"ctl %08x head %08x tail %08x start %08x\n",	313	"ctl %08x head %08x tail %08x start %08x\n",
314	ring->name,	314	ring->name,
315	I915_READ_CTL(ring),	315	I915_READ_CTL(ring),
316	I915_READ_HEAD(ring),	316	I915_READ_HEAD(ring),
317	I915_READ_TAIL(ring),	317	I915_READ_TAIL(ring),
318	I915_READ_START(ring));	318	I915_READ_START(ring));
319	return -EIO;	319	return -EIO;
320	}	320	}
321		321
322	ring->head = I915_READ_HEAD(ring);	322	ring->head = I915_READ_HEAD(ring);
323	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;	323	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
324	ring->space = ring_space(ring);	324	ring->space = ring_space(ring);
325		325
326		326
327	return 0;	327	return 0;
328	}	328	}
329		329
330	static int	330	static int
331	init_pipe_control(struct intel_ring_buffer *ring)	331	init_pipe_control(struct intel_ring_buffer *ring)
332	{	332	{
333	struct pipe_control *pc;	333	struct pipe_control *pc;
334	struct drm_i915_gem_object *obj;	334	struct drm_i915_gem_object *obj;
335	int ret;	335	int ret;
336		336
337	if (ring->private)	337	if (ring->private)
338	return 0;	338	return 0;
339		339
340	pc = kmalloc(sizeof(*pc), GFP_KERNEL);	340	pc = kmalloc(sizeof(*pc), GFP_KERNEL);
341	if (!pc)	341	if (!pc)
342	return -ENOMEM;	342	return -ENOMEM;
343		343
344	obj = i915_gem_alloc_object(ring->dev, 4096);	344	obj = i915_gem_alloc_object(ring->dev, 4096);
345	if (obj == NULL) {	345	if (obj == NULL) {
346	DRM_ERROR("Failed to allocate seqno page\n");	346	DRM_ERROR("Failed to allocate seqno page\n");
347	ret = -ENOMEM;	347	ret = -ENOMEM;
348	goto err;	348	goto err;
349	}	349	}
350		350
351	// i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);	351	// i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
352		352
353	ret = i915_gem_object_pin(obj, 4096, true);	353	ret = i915_gem_object_pin(obj, 4096, true);
354	if (ret)	354	if (ret)
355	goto err_unref;	355	goto err_unref;
356		356
357	pc->gtt_offset = obj->gtt_offset;	357	pc->gtt_offset = obj->gtt_offset;
358	pc->cpu_page = (void*)MapIoMem(obj->pages[0], 4096, PG_SW);	358	pc->cpu_page = (void*)MapIoMem(obj->pages[0], 4096, PG_SW);
359	if (pc->cpu_page == NULL)	359	if (pc->cpu_page == NULL)
360	goto err_unpin;	360	goto err_unpin;
361		361
362	pc->obj = obj;	362	pc->obj = obj;
363	ring->private = pc;	363	ring->private = pc;
364	return 0;	364	return 0;
365		365
366	err_unpin:	366	err_unpin:
367	// i915_gem_object_unpin(obj);	367	i915_gem_object_unpin(obj);
368	err_unref:	368	err_unref:
369	// drm_gem_object_unreference(&obj->base);	369	drm_gem_object_unreference(&obj->base);
370	err:	370	err:
371	kfree(pc);	371	kfree(pc);
372	return ret;	372	return ret;
373	}	373	}
374		374
375	static void	375	static void
376	cleanup_pipe_control(struct intel_ring_buffer *ring)	376	cleanup_pipe_control(struct intel_ring_buffer *ring)
377	{	377	{
378	struct pipe_control *pc = ring->private;	378	struct pipe_control *pc = ring->private;
379	struct drm_i915_gem_object *obj;	379	struct drm_i915_gem_object *obj;
380		380
381	if (!ring->private)	381	if (!ring->private)
382	return;	382	return;
383		383
384	obj = pc->obj;	384	obj = pc->obj;
385	// kunmap(obj->pages[0]);	385	// kunmap(obj->pages[0]);
386	// i915_gem_object_unpin(obj);	386	i915_gem_object_unpin(obj);
387	// drm_gem_object_unreference(&obj->base);	387	drm_gem_object_unreference(&obj->base);
388		388
389	kfree(pc);	389	kfree(pc);
390	ring->private = NULL;	390	ring->private = NULL;
391	}	391	}
392		392
393	static int init_render_ring(struct intel_ring_buffer *ring)	393	static int init_render_ring(struct intel_ring_buffer *ring)
394	{	394	{
395	struct drm_device *dev = ring->dev;	395	struct drm_device *dev = ring->dev;
396	struct drm_i915_private *dev_priv = dev->dev_private;	396	struct drm_i915_private *dev_priv = dev->dev_private;
397	int ret = init_ring_common(ring);	397	int ret = init_ring_common(ring);
398		398
399	if (INTEL_INFO(dev)->gen > 3) {	399	if (INTEL_INFO(dev)->gen > 3) {
400	int mode = VS_TIMER_DISPATCH << 16 \| VS_TIMER_DISPATCH;	400	int mode = VS_TIMER_DISPATCH << 16 \| VS_TIMER_DISPATCH;
401	if (IS_GEN6(dev) \|\| IS_GEN7(dev))	401	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
402	mode \|= MI_FLUSH_ENABLE << 16 \| MI_FLUSH_ENABLE;	402	mode \|= MI_FLUSH_ENABLE << 16 \| MI_FLUSH_ENABLE;
403	I915_WRITE(MI_MODE, mode);	403	I915_WRITE(MI_MODE, mode);
404	if (IS_GEN7(dev))	404	if (IS_GEN7(dev))
405	I915_WRITE(GFX_MODE_GEN7,	405	I915_WRITE(GFX_MODE_GEN7,
406	GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) \|	406	GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) \|
407	GFX_MODE_ENABLE(GFX_REPLAY_MODE));	407	GFX_MODE_ENABLE(GFX_REPLAY_MODE));
408	}	408	}
409		409
410	if (INTEL_INFO(dev)->gen >= 5) {	410	if (INTEL_INFO(dev)->gen >= 5) {
411	ret = init_pipe_control(ring);	411	ret = init_pipe_control(ring);
412	if (ret)	412	if (ret)
413	return ret;	413	return ret;
414	}	414	}
415		415
416	if (INTEL_INFO(dev)->gen >= 6) {	416	if (INTEL_INFO(dev)->gen >= 6) {
417	I915_WRITE(INSTPM,	417	I915_WRITE(INSTPM,
418	INSTPM_FORCE_ORDERING << 16 \| INSTPM_FORCE_ORDERING);	418	INSTPM_FORCE_ORDERING << 16 \| INSTPM_FORCE_ORDERING);
419	}	419	}
420		420
421	return ret;	421	return ret;
422	}	422	}
423		423
424	static void render_ring_cleanup(struct intel_ring_buffer *ring)	424	static void render_ring_cleanup(struct intel_ring_buffer *ring)
425	{	425	{
426	if (!ring->private)	426	if (!ring->private)
427	return;	427	return;
428		428
429	cleanup_pipe_control(ring);	429	cleanup_pipe_control(ring);
430	}	430	}
431		431
432	static void	432	static void
433	update_mboxes(struct intel_ring_buffer *ring,	433	update_mboxes(struct intel_ring_buffer *ring,
434	u32 seqno,	434	u32 seqno,
435	u32 mmio_offset)	435	u32 mmio_offset)
436	{	436	{
437	intel_ring_emit(ring, MI_SEMAPHORE_MBOX \|	437	intel_ring_emit(ring, MI_SEMAPHORE_MBOX \|
438	MI_SEMAPHORE_GLOBAL_GTT \|	438	MI_SEMAPHORE_GLOBAL_GTT \|
439	MI_SEMAPHORE_REGISTER \|	439	MI_SEMAPHORE_REGISTER \|
440	MI_SEMAPHORE_UPDATE);	440	MI_SEMAPHORE_UPDATE);
441	intel_ring_emit(ring, seqno);	441	intel_ring_emit(ring, seqno);
442	intel_ring_emit(ring, mmio_offset);	442	intel_ring_emit(ring, mmio_offset);
443	}	443	}
444		444
445	/**	445	/**
446	* gen6_add_request - Update the semaphore mailbox registers	446	* gen6_add_request - Update the semaphore mailbox registers
447	*	447	*
448	* @ring - ring that is adding a request	448	* @ring - ring that is adding a request
449	* @seqno - return seqno stuck into the ring	449	* @seqno - return seqno stuck into the ring
450	*	450	*
451	* Update the mailbox registers in the other rings with the current seqno.	451	* Update the mailbox registers in the other rings with the current seqno.
452	* This acts like a signal in the canonical semaphore.	452	* This acts like a signal in the canonical semaphore.
453	*/	453	*/
454	static int	454	static int
455	gen6_add_request(struct intel_ring_buffer *ring,	455	gen6_add_request(struct intel_ring_buffer *ring,
456	u32 *seqno)	456	u32 *seqno)
457	{	457	{
458	u32 mbox1_reg;	458	u32 mbox1_reg;
459	u32 mbox2_reg;	459	u32 mbox2_reg;
460	int ret;	460	int ret;
461		461
462	ret = intel_ring_begin(ring, 10);	462	ret = intel_ring_begin(ring, 10);
463	if (ret)	463	if (ret)
464	return ret;	464	return ret;
465		465
466	mbox1_reg = ring->signal_mbox[0];	466	mbox1_reg = ring->signal_mbox[0];
467	mbox2_reg = ring->signal_mbox[1];	467	mbox2_reg = ring->signal_mbox[1];
468		468
469	*seqno = i915_gem_get_seqno(ring->dev);	469	*seqno = i915_gem_get_seqno(ring->dev);
470		470
471	update_mboxes(ring, *seqno, mbox1_reg);	471	update_mboxes(ring, *seqno, mbox1_reg);
472	update_mboxes(ring, *seqno, mbox2_reg);	472	update_mboxes(ring, *seqno, mbox2_reg);
473	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);	473	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
474	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);	474	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
475	intel_ring_emit(ring, *seqno);	475	intel_ring_emit(ring, *seqno);
476	intel_ring_emit(ring, MI_USER_INTERRUPT);	476	intel_ring_emit(ring, MI_USER_INTERRUPT);
477	intel_ring_advance(ring);	477	intel_ring_advance(ring);
478		478
479	return 0;	479	return 0;
480	}	480	}
481		481
482	/**	482	/**
483	* intel_ring_sync - sync the waiter to the signaller on seqno	483	* intel_ring_sync - sync the waiter to the signaller on seqno
484	*	484	*
485	* @waiter - ring that is waiting	485	* @waiter - ring that is waiting
486	* @signaller - ring which has, or will signal	486	* @signaller - ring which has, or will signal
487	* @seqno - seqno which the waiter will block on	487	* @seqno - seqno which the waiter will block on
488	*/	488	*/
489	static int	489	static int
490	intel_ring_sync(struct intel_ring_buffer *waiter,	490	intel_ring_sync(struct intel_ring_buffer *waiter,
491	struct intel_ring_buffer *signaller,	491	struct intel_ring_buffer *signaller,
492	int ring,	492	int ring,
493	u32 seqno)	493	u32 seqno)
494	{	494	{
495	int ret;	495	int ret;
496	u32 dw1 = MI_SEMAPHORE_MBOX \|	496	u32 dw1 = MI_SEMAPHORE_MBOX \|
497	MI_SEMAPHORE_COMPARE \|	497	MI_SEMAPHORE_COMPARE \|
498	MI_SEMAPHORE_REGISTER;	498	MI_SEMAPHORE_REGISTER;
499		499
500	ret = intel_ring_begin(waiter, 4);	500	ret = intel_ring_begin(waiter, 4);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.c – Rev 2342 → 2344