WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.c


/*
 * Copyright © 2008-2010 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *    Zou Nan hai 
 *    Xiang Hai hao
 *
 */
#define iowrite32(v, addr)      writel((v), (addr))
#define ioread32(addr)          readl(addr)
 
#include "drmP.h"
#include "drm.h"
#include "i915_drv.h"
#include "i915_drm.h"
//#include "i915_trace.h"
#include "intel_drv.h"
 
static inline int ring_space(struct intel_ring_buffer *ring)
{
	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
	if (space < 0)
		space += ring->size;
	return space;
}
 
static u32 i915_gem_get_seqno(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 seqno;
 
	seqno = dev_priv->next_seqno;
 
	/* reserve 0 for non-seqno */
	if (++dev_priv->next_seqno == 0)
		dev_priv->next_seqno = 1;
 
	return seqno;
}
 
static int
render_ring_flush(struct intel_ring_buffer *ring,
		  u32	invalidate_domains,
		  u32	flush_domains)
{
	struct drm_device *dev = ring->dev;
	u32 cmd;
	int ret;
 
	/*
	 * read/write caches:
	 *
	 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
	 * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
	 * also flushed at 2d versus 3d pipeline switches.
	 *
	 * read-only caches:
	 *
	 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
	 * MI_READ_FLUSH is set, and is always flushed on 965.
	 *
	 * I915_GEM_DOMAIN_COMMAND may not exist?
	 *
	 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
	 * invalidated when MI_EXE_FLUSH is set.
	 *
	 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
	 * invalidated with every MI_FLUSH.
	 *
	 * TLBs:
	 *
	 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
	 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
	 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
	 * are flushed at any MI_FLUSH.
	 */
 
	cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
	if ((invalidate_domains|flush_domains) &
	    I915_GEM_DOMAIN_RENDER)
		cmd &= ~MI_NO_WRITE_FLUSH;
	if (INTEL_INFO(dev)->gen < 4) {
		/*
		 * On the 965, the sampler cache always gets flushed
		 * and this bit is reserved.
		 */
		if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
			cmd |= MI_READ_FLUSH;
	}
	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
		cmd |= MI_EXE_FLUSH;
 
	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
	    (IS_G4X(dev) || IS_GEN5(dev)))
		cmd |= MI_INVALIDATE_ISP;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	return 0;
}
 
static void ring_write_tail(struct intel_ring_buffer *ring,
			    u32 value)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	I915_WRITE_TAIL(ring, value);
}
 
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
			RING_ACTHD(ring->mmio_base) : ACTHD;
 
	return I915_READ(acthd_reg);
}
 
static int init_ring_common(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj = ring->obj;
	u32 head;
 
    ENTER();
 
	/* Stop the ring if it's running. */
	I915_WRITE_CTL(ring, 0);
	I915_WRITE_HEAD(ring, 0);
	ring->write_tail(ring, 0);
 
	/* Initialize the ring. */
	I915_WRITE_START(ring, obj->gtt_offset);
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
 
	/* G45 ring initialization fails to reset head to zero */
	if (head != 0) {
		DRM_DEBUG_KMS("%s head not reset to zero "
			      "ctl %08x head %08x tail %08x start %08x\n",
			      ring->name,
			      I915_READ_CTL(ring),
			      I915_READ_HEAD(ring),
			      I915_READ_TAIL(ring),
			      I915_READ_START(ring));
 
		I915_WRITE_HEAD(ring, 0);
 
		if (I915_READ_HEAD(ring) & HEAD_ADDR) {
			DRM_ERROR("failed to set %s head to zero "
				  "ctl %08x head %08x tail %08x start %08x\n",
				  ring->name,
				  I915_READ_CTL(ring),
				  I915_READ_HEAD(ring),
				  I915_READ_TAIL(ring),
				  I915_READ_START(ring));
		}
	}
 
	I915_WRITE_CTL(ring,
			((ring->size - PAGE_SIZE) & RING_NR_PAGES)
			| RING_REPORT_64K | RING_VALID);
 
	/* If the head is still not zero, the ring is dead */
	if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
	    I915_READ_START(ring) != obj->gtt_offset ||
	    (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
		DRM_ERROR("%s initialization failed "
				"ctl %08x head %08x tail %08x start %08x\n",
				ring->name,
				I915_READ_CTL(ring),
				I915_READ_HEAD(ring),
				I915_READ_TAIL(ring),
				I915_READ_START(ring));
		return -EIO;
	}
 
    ring->head = I915_READ_HEAD(ring);
    ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
    ring->space = ring_space(ring);
 
    LEAVE();
 
	return 0;
}
 
 
 
/*
 * 965+ support PIPE_CONTROL commands, which provide finer grained control
 * over cache flushing.
 */
struct pipe_control {
	struct drm_i915_gem_object *obj;
	volatile u32 *cpu_page;
	u32 gtt_offset;
};
 
static int
init_pipe_control(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc;
	struct drm_i915_gem_object *obj;
	int ret;
 
	if (ring->private)
		return 0;
 
	pc = kmalloc(sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;
 
	obj = i915_gem_alloc_object(ring->dev, 4096);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate seqno page\n");
		ret = -ENOMEM;
		goto err;
	}
 
//   i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
	ret = i915_gem_object_pin(obj, 4096, true);
	if (ret)
		goto err_unref;
 
	pc->gtt_offset = obj->gtt_offset;
    pc->cpu_page =  (void*)MapIoMem(obj->pages[0], 4096, PG_SW);
	if (pc->cpu_page == NULL)
		goto err_unpin;
 
	pc->obj = obj;
	ring->private = pc;
	return 0;
 
err_unpin:
//   i915_gem_object_unpin(obj);
err_unref:
//   drm_gem_object_unreference(&obj->base);
err:
	kfree(pc);
	return ret;
}
 
static void
cleanup_pipe_control(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc = ring->private;
	struct drm_i915_gem_object *obj;
 
	if (!ring->private)
		return;
 
	obj = pc->obj;
//	kunmap(obj->pages[0]);
//	i915_gem_object_unpin(obj);
//	drm_gem_object_unreference(&obj->base);
 
	kfree(pc);
	ring->private = NULL;
}
 
 
 
static int init_render_ring(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
    ENTER();
 
	int ret = init_ring_common(ring);
 
	if (INTEL_INFO(dev)->gen > 3) {
		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
		if (IS_GEN6(dev) || IS_GEN7(dev))
			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
		I915_WRITE(MI_MODE, mode);
		if (IS_GEN7(dev))
			I915_WRITE(GFX_MODE_GEN7,
				   GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
				   GFX_MODE_ENABLE(GFX_REPLAY_MODE));
	}
 
	if (INTEL_INFO(dev)->gen >= 6) {
	} else if (IS_GEN5(dev)) {
		ret = init_pipe_control(ring);
		if (ret)
			return ret;
	}
 
    LEAVE();
 
	return ret;
}
 
 
 
static void render_ring_cleanup(struct intel_ring_buffer *ring)
{
	if (!ring->private)
		return;
 
	cleanup_pipe_control(ring);
}
 
static void
update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int id;
 
	/*
	 * cs -> 1 = vcs, 0 = bcs
	 * vcs -> 1 = bcs, 0 = cs,
	 * bcs -> 1 = cs, 0 = vcs.
	 */
	id = ring - dev_priv->ring;
	id += 2 - i;
	id %= 3;
 
	intel_ring_emit(ring,
			MI_SEMAPHORE_MBOX |
			MI_SEMAPHORE_REGISTER |
			MI_SEMAPHORE_UPDATE);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring,
			RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
}
 
static int
gen6_add_request(struct intel_ring_buffer *ring,
		 u32 *result)
{
	u32 seqno;
	int ret;
 
	ret = intel_ring_begin(ring, 10);
	if (ret)
		return ret;
 
	seqno = i915_gem_get_seqno(ring->dev);
	update_semaphore(ring, 0, seqno);
	update_semaphore(ring, 1, seqno);
 
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
int
intel_ring_sync(struct intel_ring_buffer *ring,
		struct intel_ring_buffer *to,
		u32 seqno)
{
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	intel_ring_emit(ring,
			MI_SEMAPHORE_MBOX |
			MI_SEMAPHORE_REGISTER |
			intel_ring_sync_index(ring, to) << 17 |
			MI_SEMAPHORE_COMPARE);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
 
	return 0;
}
 
#define PIPE_CONTROL_FLUSH(ring__, addr__)					\
do {									\
	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |		\
		 PIPE_CONTROL_DEPTH_STALL | 2);				\
	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
	intel_ring_emit(ring__, 0);							\
	intel_ring_emit(ring__, 0);							\
} while (0)
 
static int
pc_render_add_request(struct intel_ring_buffer *ring,
		      u32 *result)
{
	struct drm_device *dev = ring->dev;
	u32 seqno = i915_gem_get_seqno(dev);
	struct pipe_control *pc = ring->private;
	u32 scratch_addr = pc->gtt_offset + 128;
	int ret;
 
	/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
	 * incoherent with writes to memory, i.e. completely fubar,
	 * so we need to use PIPE_NOTIFY instead.
	 *
	 * However, we also need to workaround the qword write
	 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
	 * memory before requesting an interrupt.
	 */
	ret = intel_ring_begin(ring, 32);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, 0);
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128; /* write to separate cachelines */
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	scratch_addr += 128;
	PIPE_CONTROL_FLUSH(ring, scratch_addr);
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
			PIPE_CONTROL_NOTIFY);
	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, 0);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
static int
render_ring_add_request(struct intel_ring_buffer *ring,
			u32 *result)
{
	struct drm_device *dev = ring->dev;
	u32 seqno = i915_gem_get_seqno(dev);
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
static u32
ring_get_seqno(struct intel_ring_buffer *ring)
{
	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}
 
static u32
pc_render_get_seqno(struct intel_ring_buffer *ring)
{
	struct pipe_control *pc = ring->private;
	return pc->cpu_page[0];
}
 
static void
ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->gt_irq_mask &= ~mask;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}
 
static void
ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->gt_irq_mask |= mask;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}
 
static void
i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->irq_mask &= ~mask;
	I915_WRITE(IMR, dev_priv->irq_mask);
	POSTING_READ(IMR);
}
 
static void
i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	dev_priv->irq_mask |= mask;
	I915_WRITE(IMR, dev_priv->irq_mask);
	POSTING_READ(IMR);
}
 
#if 0
static bool
render_ring_get_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
		return false;
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_enable_irq(dev_priv,
					    GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
		else
			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
 
static void
render_ring_put_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_disable_irq(dev_priv,
					     GT_USER_INTERRUPT |
					     GT_PIPE_NOTIFY);
		else
			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
}
 
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	u32 mmio = 0;
 
	/* The ring status page addresses are no longer next to the rest of
	 * the ring registers as of gen7.
	 */
	if (IS_GEN7(dev)) {
		switch (ring->id) {
		case RING_RENDER:
			mmio = RENDER_HWS_PGA_GEN7;
			break;
		case RING_BLT:
			mmio = BLT_HWS_PGA_GEN7;
			break;
		case RING_BSD:
			mmio = BSD_HWS_PGA_GEN7;
			break;
		}
	} else if (IS_GEN6(ring->dev)) {
		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
	} else {
		mmio = RING_HWS_PGA(ring->mmio_base);
	}
 
	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
	POSTING_READ(mmio);
}
#endif
 
static int
bsd_ring_flush(struct intel_ring_buffer *ring,
	       u32     invalidate_domains,
	       u32     flush_domains)
{
	int ret;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring, MI_FLUSH);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
 
 
static int
ring_add_request(struct intel_ring_buffer *ring,
		 u32 *result)
{
	u32 seqno;
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	seqno = i915_gem_get_seqno(ring->dev);
 
	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	intel_ring_emit(ring, seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_advance(ring);
 
	*result = seqno;
	return 0;
}
 
#if 0
 
static bool
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
	       return false;
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		ring->irq_mask &= ~rflag;
		I915_WRITE_IMR(ring, ring->irq_mask);
		ironlake_enable_irq(dev_priv, gflag);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
 
static void
gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		ring->irq_mask |= rflag;
		I915_WRITE_IMR(ring, ring->irq_mask);
		ironlake_disable_irq(dev_priv, gflag);
	}
	spin_unlock(&ring->irq_lock);
}
 
static bool
bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	if (!dev->irq_enabled)
		return false;
 
	spin_lock(&ring->irq_lock);
	if (ring->irq_refcount++ == 0) {
		if (IS_G4X(dev))
			i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
		else
			ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
 
	return true;
}
static void
bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	spin_lock(&ring->irq_lock);
	if (--ring->irq_refcount == 0) {
		if (IS_G4X(dev))
			i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
		else
			ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
	}
	spin_unlock(&ring->irq_lock);
}
 
static int
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
{
	int ret;
 
	ret = intel_ring_begin(ring, 2);
	if (ret)
		return ret;
 
	intel_ring_emit(ring,
			MI_BATCH_BUFFER_START | (2 << 6) |
			MI_BATCH_NON_SECURE_I965);
	intel_ring_emit(ring, offset);
	intel_ring_advance(ring);
 
	return 0;
}
 
static int
render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
				u32 offset, u32 len)
{
	struct drm_device *dev = ring->dev;
	int ret;
 
	if (IS_I830(dev) || IS_845G(dev)) {
		ret = intel_ring_begin(ring, 4);
		if (ret)
			return ret;
 
		intel_ring_emit(ring, MI_BATCH_BUFFER);
		intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
		intel_ring_emit(ring, offset + len - 8);
		intel_ring_emit(ring, 0);
	} else {
		ret = intel_ring_begin(ring, 2);
		if (ret)
			return ret;
 
		if (INTEL_INFO(dev)->gen >= 4) {
			intel_ring_emit(ring,
					MI_BATCH_BUFFER_START | (2 << 6) |
					MI_BATCH_NON_SECURE_I965);
			intel_ring_emit(ring, offset);
		} else {
			intel_ring_emit(ring,
					MI_BATCH_BUFFER_START | (2 << 6));
			intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
		}
	}
	intel_ring_advance(ring);
 
	return 0;
}
 
static void cleanup_status_page(struct intel_ring_buffer *ring)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj;
 
	obj = ring->status_page.obj;
	if (obj == NULL)
		return;
 
	kunmap(obj->pages[0]);
//   i915_gem_object_unpin(obj);
//   drm_gem_object_unreference(&obj->base);
	ring->status_page.obj = NULL;
 
	memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
}
 
static int init_status_page(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret;
 
	obj = i915_gem_alloc_object(dev, 4096);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate status page\n");
		ret = -ENOMEM;
		goto err;
	}
 
//   i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
	ret = i915_gem_object_pin(obj, 4096, true);
	if (ret != 0) {
		goto err_unref;
	}
 
	ring->status_page.gfx_addr = obj->gtt_offset;
	ring->status_page.page_addr = kmap(obj->pages[0]);
	if (ring->status_page.page_addr == NULL) {
		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
		goto err_unpin;
	}
	ring->status_page.obj = obj;
	memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 
	intel_ring_setup_status_page(ring);
	DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
			ring->name, ring->status_page.gfx_addr);
 
	return 0;
 
err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(&obj->base);
err:
	return ret;
}
#endif
 
int intel_init_ring_buffer(struct drm_device *dev,
			   struct intel_ring_buffer *ring)
{
    struct drm_i915_gem_object *obj=NULL;
	int ret;
    ENTER();
	ring->dev = dev;
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
	INIT_LIST_HEAD(&ring->gpu_write_list);
 
//   init_waitqueue_head(&ring->irq_queue);
//   spin_lock_init(&ring->irq_lock);
    ring->irq_mask = ~0;
 
	if (I915_NEED_GFX_HWS(dev)) {
//       ret = init_status_page(ring);
//       if (ret)
//           return ret;
	}
 
    obj = i915_gem_alloc_object(dev, ring->size);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate ringbuffer\n");
		ret = -ENOMEM;
		goto err_hws;
	}
 
	ring->obj = obj;
 
    ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
	if (ret)
		goto err_unref;
 
	ring->map.size = ring->size;
    ring->map.offset = get_bus_addr() + obj->gtt_offset;
	ring->map.type = 0;
	ring->map.flags = 0;
	ring->map.mtrr = 0;
 
//   drm_core_ioremap_wc(&ring->map, dev);
 
    ring->map.handle = ioremap(ring->map.offset, ring->map.size);
 
	if (ring->map.handle == NULL) {
		DRM_ERROR("Failed to map ringbuffer.\n");
		ret = -EINVAL;
		goto err_unpin;
	}
 
	ring->virtual_start = ring->map.handle;
	ret = ring->init(ring);
	if (ret)
		goto err_unmap;
 
	/* Workaround an erratum on the i830 which causes a hang if
	 * the TAIL pointer points to within the last 2 cachelines
	 * of the buffer.
	 */
	ring->effective_size = ring->size;
	if (IS_I830(ring->dev))
		ring->effective_size -= 128;
    LEAVE();
	return 0;
 
err_unmap:
//   drm_core_ioremapfree(&ring->map, dev);
    FreeKernelSpace(ring->virtual_start);
err_unpin:
//   i915_gem_object_unpin(obj);
err_unref:
//   drm_gem_object_unreference(&obj->base);
	ring->obj = NULL;
err_hws:
//   cleanup_status_page(ring);
	return ret;
}
 
 
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv;
	int ret;
 
	if (ring->obj == NULL)
		return;
 
	/* Disable the ring buffer. The ring must be idle at this point */
	dev_priv = ring->dev->dev_private;
	ret = intel_wait_ring_idle(ring);
	if (ret)
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
			  ring->name, ret);
 
	I915_WRITE_CTL(ring, 0);
 
//   drm_core_ioremapfree(&ring->map, ring->dev);
 
//   i915_gem_object_unpin(ring->obj);
//   drm_gem_object_unreference(&ring->obj->base);
	ring->obj = NULL;
 
	if (ring->cleanup)
		ring->cleanup(ring);
 
//   cleanup_status_page(ring);
}
 
 
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
{
	unsigned int *virt;
	int rem = ring->size - ring->tail;
 
	if (ring->space < rem) {
		int ret = intel_wait_ring_buffer(ring, rem);
		if (ret)
			return ret;
	}
 
	virt = (unsigned int *)(ring->virtual_start + ring->tail);
	rem /= 8;
	while (rem--) {
		*virt++ = MI_NOOP;
		*virt++ = MI_NOOP;
	}
 
	ring->tail = 0;
	ring->space = ring_space(ring);
 
	return 0;
}
 
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long end;
	u32 head;
 
	/* If the reported head position has wrapped or hasn't advanced,
	 * fallback to the slow and accurate path.
	 */
	head = intel_read_status_page(ring, 4);
	if (head > ring->head) {
		ring->head = head;
		ring->space = ring_space(ring);
		if (ring->space >= n)
			return 0;
	}
 
//   trace_i915_ring_wait_begin(ring);
	end = jiffies + 3 * HZ;
	do {
		ring->head = I915_READ_HEAD(ring);
		ring->space = ring_space(ring);
		if (ring->space >= n) {
//           trace_i915_ring_wait_end(ring);
			return 0;
		}
 
		if (dev->primary->master) {
			struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
			if (master_priv->sarea_priv)
				master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
		}
 
		msleep(1);
		if (atomic_read(&dev_priv->mm.wedged))
			return -EAGAIN;
	} while (!time_after(jiffies, end));
//   trace_i915_ring_wait_end(ring);
	return -EBUSY;
}
 
int intel_ring_begin(struct intel_ring_buffer *ring,
		     int num_dwords)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	int n = 4*num_dwords;
	int ret;
 
	if (unlikely(atomic_read(&dev_priv->mm.wedged)))
		return -EIO;
 
	if (unlikely(ring->tail + n > ring->effective_size)) {
		ret = intel_wrap_ring_buffer(ring);
		if (unlikely(ret))
			return ret;
	}
 
	if (unlikely(ring->space < n)) {
		ret = intel_wait_ring_buffer(ring, n);
		if (unlikely(ret))
			return ret;
	}
 
	ring->space -= n;
	return 0;
}
 
void intel_ring_advance(struct intel_ring_buffer *ring)
{
	ring->tail &= ring->size - 1;
	ring->write_tail(ring, ring->tail);
}
 
 
static const struct intel_ring_buffer render_ring = {
	.name			= "render ring",
	.id			= RING_RENDER,
	.mmio_base		= RENDER_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_render_ring,
    .write_tail     = ring_write_tail,
    .flush          = render_ring_flush,
    .add_request        = render_ring_add_request,
//   .get_seqno      = ring_get_seqno,
//   .irq_get        = render_ring_get_irq,
//   .irq_put        = render_ring_put_irq,
//   .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
//       .cleanup            = render_ring_cleanup,
};
 
/* ring buffer for bit-stream decoder */
 
static const struct intel_ring_buffer bsd_ring = {
	.name                   = "bsd ring",
	.id			= RING_BSD,
	.mmio_base		= BSD_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_ring_common,
	.write_tail		= ring_write_tail,
    .flush          = bsd_ring_flush,
    .add_request        = ring_add_request,
//   .get_seqno      = ring_get_seqno,
//   .irq_get        = bsd_ring_get_irq,
//   .irq_put        = bsd_ring_put_irq,
//   .dispatch_execbuffer    = ring_dispatch_execbuffer,
};
 
 
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
				     u32 value)
{
       drm_i915_private_t *dev_priv = ring->dev->dev_private;
 
       /* Every tail move must follow the sequence below */
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
       I915_WRITE(GEN6_BSD_RNCID, 0x0);
 
       if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
                               GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
                       50))
               DRM_ERROR("timed out waiting for IDLE Indicator\n");
 
       I915_WRITE_TAIL(ring, value);
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
}
 
 
static int gen6_ring_flush(struct intel_ring_buffer *ring,
			   u32 invalidate, u32 flush)
{
	uint32_t cmd;
	int ret;
 
	ret = intel_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	cmd = MI_FLUSH_DW;
	if (invalidate & I915_GEM_GPU_DOMAINS)
		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
#if 0
static int
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
			      u32 offset, u32 len)
{
       int ret;
 
       ret = intel_ring_begin(ring, 2);
       if (ret)
	       return ret;
 
       intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
       /* bit0-7 is the length on GEN6+ */
       intel_ring_emit(ring, offset);
       intel_ring_advance(ring);
 
       return 0;
}
 
static bool
gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_USER_INTERRUPT,
				 GEN6_RENDER_USER_INTERRUPT);
}
 
static void
gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_put_irq(ring,
				 GT_USER_INTERRUPT,
				 GEN6_RENDER_USER_INTERRUPT);
}
 
static bool
gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_GEN6_BSD_USER_INTERRUPT,
				 GEN6_BSD_USER_INTERRUPT);
}
 
static void
gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_put_irq(ring,
				 GT_GEN6_BSD_USER_INTERRUPT,
				 GEN6_BSD_USER_INTERRUPT);
}
 
#endif
 
/* ring buffer for Video Codec for Gen6+ */
static const struct intel_ring_buffer gen6_bsd_ring = {
	.name			= "gen6 bsd ring",
	.id			= RING_BSD,
	.mmio_base		= GEN6_BSD_RING_BASE,
	.size			= 32 * PAGE_SIZE,
	.init			= init_ring_common,
	.write_tail		= gen6_bsd_ring_write_tail,
    .flush          = gen6_ring_flush,
    .add_request        = gen6_add_request,
//   .get_seqno      = ring_get_seqno,
//   .irq_get        = gen6_bsd_ring_get_irq,
//   .irq_put        = gen6_bsd_ring_put_irq,
//   .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
};
 
#if 0
/* Blitter support (SandyBridge+) */
 
static bool
blt_ring_get_irq(struct intel_ring_buffer *ring)
{
	return gen6_ring_get_irq(ring,
				 GT_BLT_USER_INTERRUPT,
				 GEN6_BLITTER_USER_INTERRUPT);
}
 
static void
blt_ring_put_irq(struct intel_ring_buffer *ring)
{
	gen6_ring_put_irq(ring,
			  GT_BLT_USER_INTERRUPT,
			  GEN6_BLITTER_USER_INTERRUPT);
}
#endif
 
 
/* Workaround for some stepping of SNB,
 * each time when BLT engine ring tail moved,
 * the first command in the ring to be parsed
 * should be MI_BATCH_BUFFER_START
 */
#define NEED_BLT_WORKAROUND(dev) \
	(IS_GEN6(dev) && (dev->pdev->revision < 8))
 
static inline struct drm_i915_gem_object *
to_blt_workaround(struct intel_ring_buffer *ring)
{
	return ring->private;
}
 
 
static int blt_ring_init(struct intel_ring_buffer *ring)
{
	if (NEED_BLT_WORKAROUND(ring->dev)) {
		struct drm_i915_gem_object *obj;
		u32 *ptr;
		int ret;
 
		obj = i915_gem_alloc_object(ring->dev, 4096);
		if (obj == NULL)
			return -ENOMEM;
 
		ret = i915_gem_object_pin(obj, 4096, true);
		if (ret) {
//           drm_gem_object_unreference(&obj->base);
			return ret;
		}
 
        ptr = ioremap(obj->pages[0], 4096);
		*ptr++ = MI_BATCH_BUFFER_END;
		*ptr++ = MI_NOOP;
//        iounmap(obj->pages[0]);
 
		ret = i915_gem_object_set_to_gtt_domain(obj, false);
		if (ret) {
//           i915_gem_object_unpin(obj);
//           drm_gem_object_unreference(&obj->base);
			return ret;
		}
 
		ring->private = obj;
	}
 
	return init_ring_common(ring);
}
 
static int blt_ring_begin(struct intel_ring_buffer *ring,
			  int num_dwords)
{
	if (ring->private) {
		int ret = intel_ring_begin(ring, num_dwords+2);
		if (ret)
			return ret;
 
		intel_ring_emit(ring, MI_BATCH_BUFFER_START);
		intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
 
		return 0;
	} else
		return intel_ring_begin(ring, 4);
}
 
static int blt_ring_flush(struct intel_ring_buffer *ring,
			  u32 invalidate, u32 flush)
{
	uint32_t cmd;
	int ret;
 
	ret = blt_ring_begin(ring, 4);
	if (ret)
		return ret;
 
	cmd = MI_FLUSH_DW;
	if (invalidate & I915_GEM_DOMAIN_RENDER)
		cmd |= MI_INVALIDATE_TLB;
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
	return 0;
}
 
static void blt_ring_cleanup(struct intel_ring_buffer *ring)
{
	if (!ring->private)
		return;
 
	i915_gem_object_unpin(ring->private);
	drm_gem_object_unreference(ring->private);
	ring->private = NULL;
}
 
 
static const struct intel_ring_buffer gen6_blt_ring = {
       .name			= "blt ring",
       .id			= RING_BLT,
       .mmio_base		= BLT_RING_BASE,
       .size			= 32 * PAGE_SIZE,
       .init			= blt_ring_init,
       .write_tail		= ring_write_tail,
       .flush          = blt_ring_flush,
       .add_request        = gen6_add_request,
//       .get_seqno      = ring_get_seqno,
//       .irq_get            = blt_ring_get_irq,
//       .irq_put            = blt_ring_put_irq,
//       .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
//       .cleanup            = blt_ring_cleanup,
};
 
 
 
int intel_init_render_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
    ENTER();
	*ring = render_ring;
	if (INTEL_INFO(dev)->gen >= 6) {
       ring->add_request = gen6_add_request;
//       ring->irq_get = gen6_render_ring_get_irq;
//       ring->irq_put = gen6_render_ring_put_irq;
	} else if (IS_GEN5(dev)) {
       ring->add_request = pc_render_add_request;
//       ring->get_seqno = pc_render_get_seqno;
	}
 
	if (!I915_NEED_GFX_HWS(dev)) {
		ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
		memset(ring->status_page.page_addr, 0, PAGE_SIZE);
	}
    LEAVE();
	return intel_init_ring_buffer(dev, ring);
}
 
 
int intel_init_bsd_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
 
	if (IS_GEN6(dev) || IS_GEN7(dev))
		*ring = gen6_bsd_ring;
	else
		*ring = bsd_ring;
 
	return intel_init_ring_buffer(dev, ring);
}
 
int intel_init_blt_ring_buffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
 
	*ring = gen6_blt_ring;
 
	return intel_init_ring_buffer(dev, ring);
}

Rev 2338	Rev 2339
1	/*	1	/*
2	* Copyright © 2008-2010 Intel Corporation	2	* Copyright © 2008-2010 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	* Zou Nan hai	25	* Zou Nan hai
26	* Xiang Hai hao	26	* Xiang Hai hao
27	*	27	*
28	*/	28	*/
29	#define iowrite32(v, addr) writel((v), (addr))	29	#define iowrite32(v, addr) writel((v), (addr))
30	#define ioread32(addr) readl(addr)	30	#define ioread32(addr) readl(addr)
31		31
32	#include "drmP.h"	32	#include "drmP.h"
33	#include "drm.h"	33	#include "drm.h"
34	#include "i915_drv.h"	34	#include "i915_drv.h"
35	#include "i915_drm.h"	35	#include "i915_drm.h"
36	//#include "i915_trace.h"	36	//#include "i915_trace.h"
37	#include "intel_drv.h"	37	#include "intel_drv.h"
38		38
39	static inline int ring_space(struct intel_ring_buffer *ring)	39	static inline int ring_space(struct intel_ring_buffer *ring)
40	{	40	{
41	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);	41	int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
42	if (space < 0)	42	if (space < 0)
43	space += ring->size;	43	space += ring->size;
44	return space;	44	return space;
45	}	45	}
46		46
47	static u32 i915_gem_get_seqno(struct drm_device *dev)	47	static u32 i915_gem_get_seqno(struct drm_device *dev)
48	{	48	{
49	drm_i915_private_t *dev_priv = dev->dev_private;	49	drm_i915_private_t *dev_priv = dev->dev_private;
50	u32 seqno;	50	u32 seqno;
51		51
52	seqno = dev_priv->next_seqno;	52	seqno = dev_priv->next_seqno;
53		53
54	/* reserve 0 for non-seqno */	54	/* reserve 0 for non-seqno */
55	if (++dev_priv->next_seqno == 0)	55	if (++dev_priv->next_seqno == 0)
56	dev_priv->next_seqno = 1;	56	dev_priv->next_seqno = 1;
57		57
58	return seqno;	58	return seqno;
59	}	59	}
60		60
61	static int	61	static int
62	render_ring_flush(struct intel_ring_buffer *ring,	62	render_ring_flush(struct intel_ring_buffer *ring,
63	u32 invalidate_domains,	63	u32 invalidate_domains,
64	u32 flush_domains)	64	u32 flush_domains)
65	{	65	{
66	struct drm_device *dev = ring->dev;	66	struct drm_device *dev = ring->dev;
67	u32 cmd;	67	u32 cmd;
68	int ret;	68	int ret;
69		69
70	/*	70	/*
71	* read/write caches:	71	* read/write caches:
72	*	72	*
73	* I915_GEM_DOMAIN_RENDER is always invalidated, but is	73	* I915_GEM_DOMAIN_RENDER is always invalidated, but is
74	* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is	74	* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
75	* also flushed at 2d versus 3d pipeline switches.	75	* also flushed at 2d versus 3d pipeline switches.
76	*	76	*
77	* read-only caches:	77	* read-only caches:
78	*	78	*
79	* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if	79	* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
80	* MI_READ_FLUSH is set, and is always flushed on 965.	80	* MI_READ_FLUSH is set, and is always flushed on 965.
81	*	81	*
82	* I915_GEM_DOMAIN_COMMAND may not exist?	82	* I915_GEM_DOMAIN_COMMAND may not exist?
83	*	83	*
84	* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is	84	* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
85	* invalidated when MI_EXE_FLUSH is set.	85	* invalidated when MI_EXE_FLUSH is set.
86	*	86	*
87	* I915_GEM_DOMAIN_VERTEX, which exists on 965, is	87	* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
88	* invalidated with every MI_FLUSH.	88	* invalidated with every MI_FLUSH.
89	*	89	*
90	* TLBs:	90	* TLBs:
91	*	91	*
92	* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND	92	* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
93	* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and	93	* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
94	* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER	94	* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
95	* are flushed at any MI_FLUSH.	95	* are flushed at any MI_FLUSH.
96	*/	96	*/
97		97
98	cmd = MI_FLUSH \| MI_NO_WRITE_FLUSH;	98	cmd = MI_FLUSH \| MI_NO_WRITE_FLUSH;
99	if ((invalidate_domains\|flush_domains) &	99	if ((invalidate_domains\|flush_domains) &
100	I915_GEM_DOMAIN_RENDER)	100	I915_GEM_DOMAIN_RENDER)
101	cmd &= ~MI_NO_WRITE_FLUSH;	101	cmd &= ~MI_NO_WRITE_FLUSH;
102	if (INTEL_INFO(dev)->gen < 4) {	102	if (INTEL_INFO(dev)->gen < 4) {
103	/*	103	/*
104	* On the 965, the sampler cache always gets flushed	104	* On the 965, the sampler cache always gets flushed
105	* and this bit is reserved.	105	* and this bit is reserved.
106	*/	106	*/
107	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)	107	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
108	cmd \|= MI_READ_FLUSH;	108	cmd \|= MI_READ_FLUSH;
109	}	109	}
110	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)	110	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
111	cmd \|= MI_EXE_FLUSH;	111	cmd \|= MI_EXE_FLUSH;
112		112
113	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&	113	if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
114	(IS_G4X(dev) \|\| IS_GEN5(dev)))	114	(IS_G4X(dev) \|\| IS_GEN5(dev)))
115	cmd \|= MI_INVALIDATE_ISP;	115	cmd \|= MI_INVALIDATE_ISP;
116		116
117	ret = intel_ring_begin(ring, 2);	117	ret = intel_ring_begin(ring, 2);
118	if (ret)	118	if (ret)
119	return ret;	119	return ret;
120		120
121	intel_ring_emit(ring, cmd);	121	intel_ring_emit(ring, cmd);
122	intel_ring_emit(ring, MI_NOOP);	122	intel_ring_emit(ring, MI_NOOP);
123	intel_ring_advance(ring);	123	intel_ring_advance(ring);
124		124
125	return 0;	125	return 0;
126	}	126	}
127		127
128	static void ring_write_tail(struct intel_ring_buffer *ring,	128	static void ring_write_tail(struct intel_ring_buffer *ring,
129	u32 value)	129	u32 value)
130	{	130	{
131	drm_i915_private_t *dev_priv = ring->dev->dev_private;	131	drm_i915_private_t *dev_priv = ring->dev->dev_private;
132	I915_WRITE_TAIL(ring, value);	132	I915_WRITE_TAIL(ring, value);
133	}	133	}
134		134
135	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)	135	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
136	{	136	{
137	drm_i915_private_t *dev_priv = ring->dev->dev_private;	137	drm_i915_private_t *dev_priv = ring->dev->dev_private;
138	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?	138	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
139	RING_ACTHD(ring->mmio_base) : ACTHD;	139	RING_ACTHD(ring->mmio_base) : ACTHD;
140		140
141	return I915_READ(acthd_reg);	141	return I915_READ(acthd_reg);
142	}	142	}
143		143
144	static int init_ring_common(struct intel_ring_buffer *ring)	144	static int init_ring_common(struct intel_ring_buffer *ring)
145	{	145	{
146	drm_i915_private_t *dev_priv = ring->dev->dev_private;	146	drm_i915_private_t *dev_priv = ring->dev->dev_private;
147	struct drm_i915_gem_object *obj = ring->obj;	147	struct drm_i915_gem_object *obj = ring->obj;
148	u32 head;	148	u32 head;
149		149
150	ENTER();	150	ENTER();
151		151
152	/* Stop the ring if it's running. */	152	/* Stop the ring if it's running. */
153	I915_WRITE_CTL(ring, 0);	153	I915_WRITE_CTL(ring, 0);
154	I915_WRITE_HEAD(ring, 0);	154	I915_WRITE_HEAD(ring, 0);
155	ring->write_tail(ring, 0);	155	ring->write_tail(ring, 0);
156		156
157	/* Initialize the ring. */	157	/* Initialize the ring. */
158	I915_WRITE_START(ring, obj->gtt_offset);	158	I915_WRITE_START(ring, obj->gtt_offset);
159	head = I915_READ_HEAD(ring) & HEAD_ADDR;	159	head = I915_READ_HEAD(ring) & HEAD_ADDR;
160		160
161	/* G45 ring initialization fails to reset head to zero */	161	/* G45 ring initialization fails to reset head to zero */
162	if (head != 0) {	162	if (head != 0) {
163	DRM_DEBUG_KMS("%s head not reset to zero "	163	DRM_DEBUG_KMS("%s head not reset to zero "
164	"ctl %08x head %08x tail %08x start %08x\n",	164	"ctl %08x head %08x tail %08x start %08x\n",
165	ring->name,	165	ring->name,
166	I915_READ_CTL(ring),	166	I915_READ_CTL(ring),
167	I915_READ_HEAD(ring),	167	I915_READ_HEAD(ring),
168	I915_READ_TAIL(ring),	168	I915_READ_TAIL(ring),
169	I915_READ_START(ring));	169	I915_READ_START(ring));
170		170
171	I915_WRITE_HEAD(ring, 0);	171	I915_WRITE_HEAD(ring, 0);
172		172
173	if (I915_READ_HEAD(ring) & HEAD_ADDR) {	173	if (I915_READ_HEAD(ring) & HEAD_ADDR) {
174	DRM_ERROR("failed to set %s head to zero "	174	DRM_ERROR("failed to set %s head to zero "
175	"ctl %08x head %08x tail %08x start %08x\n",	175	"ctl %08x head %08x tail %08x start %08x\n",
176	ring->name,	176	ring->name,
177	I915_READ_CTL(ring),	177	I915_READ_CTL(ring),
178	I915_READ_HEAD(ring),	178	I915_READ_HEAD(ring),
179	I915_READ_TAIL(ring),	179	I915_READ_TAIL(ring),
180	I915_READ_START(ring));	180	I915_READ_START(ring));
181	}	181	}
182	}	182	}
183		183
184	I915_WRITE_CTL(ring,	184	I915_WRITE_CTL(ring,
185	((ring->size - PAGE_SIZE) & RING_NR_PAGES)	185	((ring->size - PAGE_SIZE) & RING_NR_PAGES)
186	\| RING_REPORT_64K \| RING_VALID);	186	\| RING_REPORT_64K \| RING_VALID);
187		187
188	/* If the head is still not zero, the ring is dead */	188	/* If the head is still not zero, the ring is dead */
189	if ((I915_READ_CTL(ring) & RING_VALID) == 0 \|\|	189	if ((I915_READ_CTL(ring) & RING_VALID) == 0 \|\|
190	I915_READ_START(ring) != obj->gtt_offset \|\|	190	I915_READ_START(ring) != obj->gtt_offset \|\|
191	(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {	191	(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
192	DRM_ERROR("%s initialization failed "	192	DRM_ERROR("%s initialization failed "
193	"ctl %08x head %08x tail %08x start %08x\n",	193	"ctl %08x head %08x tail %08x start %08x\n",
194	ring->name,	194	ring->name,
195	I915_READ_CTL(ring),	195	I915_READ_CTL(ring),
196	I915_READ_HEAD(ring),	196	I915_READ_HEAD(ring),
197	I915_READ_TAIL(ring),	197	I915_READ_TAIL(ring),
198	I915_READ_START(ring));	198	I915_READ_START(ring));
199	return -EIO;	199	return -EIO;
200	}	200	}
201		201
202	ring->head = I915_READ_HEAD(ring);	202	ring->head = I915_READ_HEAD(ring);
203	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;	203	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
204	ring->space = ring_space(ring);	204	ring->space = ring_space(ring);
205		205
206	LEAVE();	206	LEAVE();
207		207
208	return 0;	208	return 0;
209	}	209	}
210		-
211	#if 0	-
212		210
213	/*	211	/*
214	* 965+ support PIPE_CONTROL commands, which provide finer grained control	212	* 965+ support PIPE_CONTROL commands, which provide finer grained control
215	* over cache flushing.	213	* over cache flushing.
216	*/	214	*/
217	struct pipe_control {	215	struct pipe_control {
218	struct drm_i915_gem_object *obj;	216	struct drm_i915_gem_object *obj;
219	volatile u32 *cpu_page;	217	volatile u32 *cpu_page;
220	u32 gtt_offset;	218	u32 gtt_offset;
221	};	219	};
222		220
223	static int	221	static int
224	init_pipe_control(struct intel_ring_buffer *ring)	222	init_pipe_control(struct intel_ring_buffer *ring)
225	{	223	{
226	struct pipe_control *pc;	224	struct pipe_control *pc;
227	struct drm_i915_gem_object *obj;	225	struct drm_i915_gem_object *obj;
228	int ret;	226	int ret;
229		227
230	if (ring->private)	228	if (ring->private)
231	return 0;	229	return 0;
232		230
233	pc = kmalloc(sizeof(*pc), GFP_KERNEL);	231	pc = kmalloc(sizeof(*pc), GFP_KERNEL);
234	if (!pc)	232	if (!pc)
235	return -ENOMEM;	233	return -ENOMEM;
236		234
237	obj = i915_gem_alloc_object(ring->dev, 4096);	235	obj = i915_gem_alloc_object(ring->dev, 4096);
238	if (obj == NULL) {	236	if (obj == NULL) {
239	DRM_ERROR("Failed to allocate seqno page\n");	237	DRM_ERROR("Failed to allocate seqno page\n");
240	ret = -ENOMEM;	238	ret = -ENOMEM;
241	goto err;	239	goto err;
242	}	240	}
243		241
244	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);	242	// i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
245		243
246	ret = i915_gem_object_pin(obj, 4096, true);	244	ret = i915_gem_object_pin(obj, 4096, true);
247	if (ret)	245	if (ret)
248	goto err_unref;	246	goto err_unref;
249		247
250	pc->gtt_offset = obj->gtt_offset;	248	pc->gtt_offset = obj->gtt_offset;
251	pc->cpu_page = kmap(obj->pages[0]);	249	pc->cpu_page = (void*)MapIoMem(obj->pages[0], 4096, PG_SW);
252	if (pc->cpu_page == NULL)	250	if (pc->cpu_page == NULL)
253	goto err_unpin;	251	goto err_unpin;
254		252
255	pc->obj = obj;	253	pc->obj = obj;
256	ring->private = pc;	254	ring->private = pc;
257	return 0;	255	return 0;
258		256
259	err_unpin:	257	err_unpin:
260	i915_gem_object_unpin(obj);	258	// i915_gem_object_unpin(obj);
261	err_unref:	259	err_unref:
262	drm_gem_object_unreference(&obj->base);	260	// drm_gem_object_unreference(&obj->base);
263	err:	261	err:
264	kfree(pc);	262	kfree(pc);
265	return ret;	263	return ret;
266	}	264	}
267		265
268	static void	266	static void
269	cleanup_pipe_control(struct intel_ring_buffer *ring)	267	cleanup_pipe_control(struct intel_ring_buffer *ring)
270	{	268	{
271	struct pipe_control *pc = ring->private;	269	struct pipe_control *pc = ring->private;
272	struct drm_i915_gem_object *obj;	270	struct drm_i915_gem_object *obj;
273		271
274	if (!ring->private)	272	if (!ring->private)
275	return;	273	return;
276		274
277	obj = pc->obj;	275	obj = pc->obj;
278	kunmap(obj->pages[0]);	276	// kunmap(obj->pages[0]);
279	i915_gem_object_unpin(obj);	277	// i915_gem_object_unpin(obj);
280	drm_gem_object_unreference(&obj->base);	278	// drm_gem_object_unreference(&obj->base);
281		279
282	kfree(pc);	280	kfree(pc);
283	ring->private = NULL;	281	ring->private = NULL;
284	}	282	}
285		-
286	#endif	-
287		283
288	static int init_render_ring(struct intel_ring_buffer *ring)	284	static int init_render_ring(struct intel_ring_buffer *ring)
289	{	285	{
290	struct drm_device *dev = ring->dev;	286	struct drm_device *dev = ring->dev;
291	struct drm_i915_private *dev_priv = dev->dev_private;	287	struct drm_i915_private *dev_priv = dev->dev_private;
292		288
293	ENTER();	289	ENTER();
294		290
295	int ret = init_ring_common(ring);	291	int ret = init_ring_common(ring);
296		292
297	if (INTEL_INFO(dev)->gen > 3) {	293	if (INTEL_INFO(dev)->gen > 3) {
298	int mode = VS_TIMER_DISPATCH << 16 \| VS_TIMER_DISPATCH;	294	int mode = VS_TIMER_DISPATCH << 16 \| VS_TIMER_DISPATCH;
299	if (IS_GEN6(dev) \|\| IS_GEN7(dev))	295	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
300	mode \|= MI_FLUSH_ENABLE << 16 \| MI_FLUSH_ENABLE;	296	mode \|= MI_FLUSH_ENABLE << 16 \| MI_FLUSH_ENABLE;
301	I915_WRITE(MI_MODE, mode);	297	I915_WRITE(MI_MODE, mode);
302	if (IS_GEN7(dev))	298	if (IS_GEN7(dev))
303	I915_WRITE(GFX_MODE_GEN7,	299	I915_WRITE(GFX_MODE_GEN7,
304	GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) \|	300	GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) \|
305	GFX_MODE_ENABLE(GFX_REPLAY_MODE));	301	GFX_MODE_ENABLE(GFX_REPLAY_MODE));
306	}	302	}
307		303
308	if (INTEL_INFO(dev)->gen >= 6) {	304	if (INTEL_INFO(dev)->gen >= 6) {
309	} else if (IS_GEN5(dev)) {	305	} else if (IS_GEN5(dev)) {
310	// ret = init_pipe_control(ring);	306	ret = init_pipe_control(ring);
311	if (ret)	307	if (ret)
312	return ret;	308	return ret;
313	}	309	}
314		310
315	LEAVE();	311	LEAVE();
316		312
317	return ret;	313	return ret;
318	}	314	}
319		-
320	#if 0	-
321		315
322	static void render_ring_cleanup(struct intel_ring_buffer *ring)	316	static void render_ring_cleanup(struct intel_ring_buffer *ring)
323	{	317	{
324	if (!ring->private)	318	if (!ring->private)
325	return;	319	return;
326		320
327	cleanup_pipe_control(ring);	321	cleanup_pipe_control(ring);
328	}	322	}
329		323
330	static void	324	static void
331	update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)	325	update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
332	{	326	{
333	struct drm_device *dev = ring->dev;	327	struct drm_device *dev = ring->dev;
334	struct drm_i915_private *dev_priv = dev->dev_private;	328	struct drm_i915_private *dev_priv = dev->dev_private;
335	int id;	329	int id;
336		330
337	/*	331	/*
338	* cs -> 1 = vcs, 0 = bcs	332	* cs -> 1 = vcs, 0 = bcs
339	* vcs -> 1 = bcs, 0 = cs,	333	* vcs -> 1 = bcs, 0 = cs,
340	* bcs -> 1 = cs, 0 = vcs.	334	* bcs -> 1 = cs, 0 = vcs.
341	*/	335	*/
342	id = ring - dev_priv->ring;	336	id = ring - dev_priv->ring;
343	id += 2 - i;	337	id += 2 - i;
344	id %= 3;	338	id %= 3;
345		339
346	intel_ring_emit(ring,	340	intel_ring_emit(ring,
347	MI_SEMAPHORE_MBOX \|	341	MI_SEMAPHORE_MBOX \|
348	MI_SEMAPHORE_REGISTER \|	342	MI_SEMAPHORE_REGISTER \|
349	MI_SEMAPHORE_UPDATE);	343	MI_SEMAPHORE_UPDATE);
350	intel_ring_emit(ring, seqno);	344	intel_ring_emit(ring, seqno);
351	intel_ring_emit(ring,	345	intel_ring_emit(ring,
352	RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);	346	RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
353	}	347	}
354		348
355	static int	349	static int
356	gen6_add_request(struct intel_ring_buffer *ring,	350	gen6_add_request(struct intel_ring_buffer *ring,
357	u32 *result)	351	u32 *result)
358	{	352	{
359	u32 seqno;	353	u32 seqno;
360	int ret;	354	int ret;
361		355
362	ret = intel_ring_begin(ring, 10);	356	ret = intel_ring_begin(ring, 10);
363	if (ret)	357	if (ret)
364	return ret;	358	return ret;
365		359
366	seqno = i915_gem_get_seqno(ring->dev);	360	seqno = i915_gem_get_seqno(ring->dev);
367	update_semaphore(ring, 0, seqno);	361	update_semaphore(ring, 0, seqno);
368	update_semaphore(ring, 1, seqno);	362	update_semaphore(ring, 1, seqno);
369		363
370	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);	364	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
371	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);	365	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
372	intel_ring_emit(ring, seqno);	366	intel_ring_emit(ring, seqno);
373	intel_ring_emit(ring, MI_USER_INTERRUPT);	367	intel_ring_emit(ring, MI_USER_INTERRUPT);
374	intel_ring_advance(ring);	368	intel_ring_advance(ring);
375		369
376	*result = seqno;	370	*result = seqno;
377	return 0;	371	return 0;
378	}	372	}
379		373
380	int	374	int
381	intel_ring_sync(struct intel_ring_buffer *ring,	375	intel_ring_sync(struct intel_ring_buffer *ring,
382	struct intel_ring_buffer *to,	376	struct intel_ring_buffer *to,
383	u32 seqno)	377	u32 seqno)
384	{	378	{
385	int ret;	379	int ret;
386		380
387	ret = intel_ring_begin(ring, 4);	381	ret = intel_ring_begin(ring, 4);
388	if (ret)	382	if (ret)
389	return ret;	383	return ret;
390		384
391	intel_ring_emit(ring,	385	intel_ring_emit(ring,
392	MI_SEMAPHORE_MBOX \|	386	MI_SEMAPHORE_MBOX \|
393	MI_SEMAPHORE_REGISTER \|	387	MI_SEMAPHORE_REGISTER \|
394	intel_ring_sync_index(ring, to) << 17 \|	388	intel_ring_sync_index(ring, to) << 17 \|
395	MI_SEMAPHORE_COMPARE);	389	MI_SEMAPHORE_COMPARE);
396	intel_ring_emit(ring, seqno);	390	intel_ring_emit(ring, seqno);
397	intel_ring_emit(ring, 0);	391	intel_ring_emit(ring, 0);
398	intel_ring_emit(ring, MI_NOOP);	392	intel_ring_emit(ring, MI_NOOP);
399	intel_ring_advance(ring);	393	intel_ring_advance(ring);
400		394
401	return 0;	395	return 0;
402	}	396	}
403		397
404	#define PIPE_CONTROL_FLUSH(ring__, addr__) \	398	#define PIPE_CONTROL_FLUSH(ring__, addr__) \
405	do { \	399	do { \
406	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \| \	400	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \| \
407	PIPE_CONTROL_DEPTH_STALL \| 2); \	401	PIPE_CONTROL_DEPTH_STALL \| 2); \
408	intel_ring_emit(ring__, (addr__) \| PIPE_CONTROL_GLOBAL_GTT); \	402	intel_ring_emit(ring__, (addr__) \| PIPE_CONTROL_GLOBAL_GTT); \
409	intel_ring_emit(ring__, 0); \	403	intel_ring_emit(ring__, 0); \
410	intel_ring_emit(ring__, 0); \	404	intel_ring_emit(ring__, 0); \
411	} while (0)	405	} while (0)
412		406
413	static int	407	static int
414	pc_render_add_request(struct intel_ring_buffer *ring,	408	pc_render_add_request(struct intel_ring_buffer *ring,
415	u32 *result)	409	u32 *result)
416	{	410	{
417	struct drm_device *dev = ring->dev;	411	struct drm_device *dev = ring->dev;
418	u32 seqno = i915_gem_get_seqno(dev);	412	u32 seqno = i915_gem_get_seqno(dev);
419	struct pipe_control *pc = ring->private;	413	struct pipe_control *pc = ring->private;
420	u32 scratch_addr = pc->gtt_offset + 128;	414	u32 scratch_addr = pc->gtt_offset + 128;
421	int ret;	415	int ret;
422		416
423	/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently	417	/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
424	* incoherent with writes to memory, i.e. completely fubar,	418	* incoherent with writes to memory, i.e. completely fubar,
425	* so we need to use PIPE_NOTIFY instead.	419	* so we need to use PIPE_NOTIFY instead.
426	*	420	*
427	* However, we also need to workaround the qword write	421	* However, we also need to workaround the qword write
428	* incoherence by flushing the 6 PIPE_NOTIFY buffers out to	422	* incoherence by flushing the 6 PIPE_NOTIFY buffers out to
429	* memory before requesting an interrupt.	423	* memory before requesting an interrupt.
430	*/	424	*/
431	ret = intel_ring_begin(ring, 32);	425	ret = intel_ring_begin(ring, 32);
432	if (ret)	426	if (ret)
433	return ret;	427	return ret;
434		428
435	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|	429	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|
436	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH);	430	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH);
437	intel_ring_emit(ring, pc->gtt_offset \| PIPE_CONTROL_GLOBAL_GTT);	431	intel_ring_emit(ring, pc->gtt_offset \| PIPE_CONTROL_GLOBAL_GTT);
438	intel_ring_emit(ring, seqno);	432	intel_ring_emit(ring, seqno);
439	intel_ring_emit(ring, 0);	433	intel_ring_emit(ring, 0);
440	PIPE_CONTROL_FLUSH(ring, scratch_addr);	434	PIPE_CONTROL_FLUSH(ring, scratch_addr);
441	scratch_addr += 128; /* write to separate cachelines */	435	scratch_addr += 128; /* write to separate cachelines */
442	PIPE_CONTROL_FLUSH(ring, scratch_addr);	436	PIPE_CONTROL_FLUSH(ring, scratch_addr);
443	scratch_addr += 128;	437	scratch_addr += 128;
444	PIPE_CONTROL_FLUSH(ring, scratch_addr);	438	PIPE_CONTROL_FLUSH(ring, scratch_addr);
445	scratch_addr += 128;	439	scratch_addr += 128;
446	PIPE_CONTROL_FLUSH(ring, scratch_addr);	440	PIPE_CONTROL_FLUSH(ring, scratch_addr);
447	scratch_addr += 128;	441	scratch_addr += 128;
448	PIPE_CONTROL_FLUSH(ring, scratch_addr);	442	PIPE_CONTROL_FLUSH(ring, scratch_addr);
449	scratch_addr += 128;	443	scratch_addr += 128;
450	PIPE_CONTROL_FLUSH(ring, scratch_addr);	444	PIPE_CONTROL_FLUSH(ring, scratch_addr);
451	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|	445	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|
452	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH \|	446	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH \|
453	PIPE_CONTROL_NOTIFY);	447	PIPE_CONTROL_NOTIFY);
454	intel_ring_emit(ring, pc->gtt_offset \| PIPE_CONTROL_GLOBAL_GTT);	448	intel_ring_emit(ring, pc->gtt_offset \| PIPE_CONTROL_GLOBAL_GTT);
455	intel_ring_emit(ring, seqno);	449	intel_ring_emit(ring, seqno);
456	intel_ring_emit(ring, 0);	450	intel_ring_emit(ring, 0);
457	intel_ring_advance(ring);	451	intel_ring_advance(ring);
458		452
459	*result = seqno;	453	*result = seqno;
460	return 0;	454	return 0;
461	}	455	}
462		456
463	static int	457	static int
464	render_ring_add_request(struct intel_ring_buffer *ring,	458	render_ring_add_request(struct intel_ring_buffer *ring,
465	u32 *result)	459	u32 *result)
466	{	460	{
467	struct drm_device *dev = ring->dev;	461	struct drm_device *dev = ring->dev;
468	u32 seqno = i915_gem_get_seqno(dev);	462	u32 seqno = i915_gem_get_seqno(dev);
469	int ret;	463	int ret;
470		464
471	ret = intel_ring_begin(ring, 4);	465	ret = intel_ring_begin(ring, 4);
472	if (ret)	466	if (ret)
473	return ret;	467	return ret;
474		468
475	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);	469	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
476	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);	470	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
477	intel_ring_emit(ring, seqno);	471	intel_ring_emit(ring, seqno);
478	intel_ring_emit(ring, MI_USER_INTERRUPT);	472	intel_ring_emit(ring, MI_USER_INTERRUPT);
479	intel_ring_advance(ring);	473	intel_ring_advance(ring);
480		474
481	*result = seqno;	475	*result = seqno;
482	return 0;	476	return 0;
483	}	477	}
484		478
485	static u32	479	static u32
486	ring_get_seqno(struct intel_ring_buffer *ring)	480	ring_get_seqno(struct intel_ring_buffer *ring)
487	{	481	{
488	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);	482	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
489	}	483	}
490		484
491	static u32	485	static u32
492	pc_render_get_seqno(struct intel_ring_buffer *ring)	486	pc_render_get_seqno(struct intel_ring_buffer *ring)
493	{	487	{
494	struct pipe_control *pc = ring->private;	488	struct pipe_control *pc = ring->private;
495	return pc->cpu_page[0];	489	return pc->cpu_page[0];
496	}	490	}
497		491
498	static void	492	static void
499	ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)	493	ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
500	{	494	{

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.c – Rev 2338 → 2339