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Line 206... Line 206...
206
    LEAVE();
206
    LEAVE();
Line 207... Line 207...
207
 
207
 
208
	return 0;
208
	return 0;
Line 209... Line -...
209
}
-
 
210
 
-
 
211
#if 0
209
}
212
 
210
 
213
/*
211
/*
214
 * 965+ support PIPE_CONTROL commands, which provide finer grained control
212
 * 965+ support PIPE_CONTROL commands, which provide finer grained control
215
 * over cache flushing.
213
 * over cache flushing.
Line 239... Line 237...
239
		DRM_ERROR("Failed to allocate seqno page\n");
237
		DRM_ERROR("Failed to allocate seqno page\n");
240
		ret = -ENOMEM;
238
		ret = -ENOMEM;
241
		goto err;
239
		goto err;
242
	}
240
	}
Line 243... Line 241...
243
 
241
 
Line 244... Line 242...
244
	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
242
//   i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
245
 
243
 
246
	ret = i915_gem_object_pin(obj, 4096, true);
244
	ret = i915_gem_object_pin(obj, 4096, true);
Line 247... Line 245...
247
	if (ret)
245
	if (ret)
248
		goto err_unref;
246
		goto err_unref;
249
 
247
 
250
	pc->gtt_offset = obj->gtt_offset;
248
	pc->gtt_offset = obj->gtt_offset;
Line 251... Line 249...
251
	pc->cpu_page =  kmap(obj->pages[0]);
249
    pc->cpu_page =  (void*)MapIoMem(obj->pages[0], 4096, PG_SW);
252
	if (pc->cpu_page == NULL)
250
	if (pc->cpu_page == NULL)
253
		goto err_unpin;
251
		goto err_unpin;
Line 254... Line 252...
254
 
252
 
255
	pc->obj = obj;
253
	pc->obj = obj;
256
	ring->private = pc;
254
	ring->private = pc;
257
	return 0;
255
	return 0;
258
 
256
 
259
err_unpin:
257
err_unpin:
260
	i915_gem_object_unpin(obj);
258
//   i915_gem_object_unpin(obj);
261
err_unref:
259
err_unref:
Line 273... Line 271...
273
 
271
 
274
	if (!ring->private)
272
	if (!ring->private)
Line 275... Line 273...
275
		return;
273
		return;
276
 
274
 
277
	obj = pc->obj;
275
	obj = pc->obj;
278
	kunmap(obj->pages[0]);
276
//	kunmap(obj->pages[0]);
Line 279... Line 277...
279
	i915_gem_object_unpin(obj);
277
//	i915_gem_object_unpin(obj);
280
	drm_gem_object_unreference(&obj->base);
278
//	drm_gem_object_unreference(&obj->base);
281
 
279
 
Line 282... Line -...
282
	kfree(pc);
-
 
283
	ring->private = NULL;
-
 
284
}
280
	kfree(pc);
285
 
281
	ring->private = NULL;
286
#endif
282
}
287
 
283
 
Line 305... Line 301...
305
				   GFX_MODE_ENABLE(GFX_REPLAY_MODE));
301
				   GFX_MODE_ENABLE(GFX_REPLAY_MODE));
306
	}
302
	}
Line 307... Line 303...
307
 
303
 
308
	if (INTEL_INFO(dev)->gen >= 6) {
304
	if (INTEL_INFO(dev)->gen >= 6) {
309
	} else if (IS_GEN5(dev)) {
305
	} else if (IS_GEN5(dev)) {
310
//       ret = init_pipe_control(ring);
306
		ret = init_pipe_control(ring);
311
		if (ret)
307
		if (ret)
312
			return ret;
308
			return ret;
Line 313... Line 309...
313
	}
309
	}
Line 314... Line 310...
314
 
310
 
315
    LEAVE();
311
    LEAVE();
Line 316... Line -...
316
 
-
 
317
	return ret;
-
 
318
}
312
 
319
 
313
	return ret;
320
#if 0
314
}
321
 
315
 
Line 525... Line 519...
525
	dev_priv->irq_mask |= mask;
519
	dev_priv->irq_mask |= mask;
526
	I915_WRITE(IMR, dev_priv->irq_mask);
520
	I915_WRITE(IMR, dev_priv->irq_mask);
527
	POSTING_READ(IMR);
521
	POSTING_READ(IMR);
528
}
522
}
Line -... Line 523...
-
 
523
 
529
 
524
#if 0
530
static bool
525
static bool
531
render_ring_get_irq(struct intel_ring_buffer *ring)
526
render_ring_get_irq(struct intel_ring_buffer *ring)
532
{
527
{
533
	struct drm_device *dev = ring->dev;
528
	struct drm_device *dev = ring->dev;
Line 614... Line 609...
614
	intel_ring_emit(ring, MI_NOOP);
609
	intel_ring_emit(ring, MI_NOOP);
615
	intel_ring_advance(ring);
610
	intel_ring_advance(ring);
616
	return 0;
611
	return 0;
617
}
612
}
Line 618... Line -...
618
 
-
 
619
#if 0
-
 
620
 
613
 
621
static int
614
static int
622
ring_add_request(struct intel_ring_buffer *ring,
615
ring_add_request(struct intel_ring_buffer *ring,
623
		 u32 *result)
616
		 u32 *result)
624
{
617
{
Line 639... Line 632...
639
 
632
 
640
	*result = seqno;
633
	*result = seqno;
641
	return 0;
634
	return 0;
Line -... Line 635...
-
 
635
}
-
 
636
 
642
}
637
#if 0
643
 
638
 
644
static bool
639
static bool
645
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
640
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
646
{
641
{
Line 775... Line 770...
775
	obj = ring->status_page.obj;
770
	obj = ring->status_page.obj;
776
	if (obj == NULL)
771
	if (obj == NULL)
777
		return;
772
		return;
Line 778... Line 773...
778
 
773
 
779
	kunmap(obj->pages[0]);
774
	kunmap(obj->pages[0]);
780
	i915_gem_object_unpin(obj);
775
//   i915_gem_object_unpin(obj);
781
	drm_gem_object_unreference(&obj->base);
776
//   drm_gem_object_unreference(&obj->base);
Line 782... Line 777...
782
	ring->status_page.obj = NULL;
777
	ring->status_page.obj = NULL;
783
 
778
 
Line 796... Line 791...
796
		DRM_ERROR("Failed to allocate status page\n");
791
		DRM_ERROR("Failed to allocate status page\n");
797
		ret = -ENOMEM;
792
		ret = -ENOMEM;
798
		goto err;
793
		goto err;
799
	}
794
	}
Line 800... Line 795...
800
 
795
 
Line 801... Line 796...
801
	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
796
//   i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
802
 
797
 
803
	ret = i915_gem_object_pin(obj, 4096, true);
798
	ret = i915_gem_object_pin(obj, 4096, true);
804
	if (ret != 0) {
799
	if (ret != 0) {
Line 905... Line 900...
905
err_hws:
900
err_hws:
906
//   cleanup_status_page(ring);
901
//   cleanup_status_page(ring);
907
	return ret;
902
	return ret;
908
}
903
}
Line 909... Line -...
909
 
-
 
910
 
904
 
911
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
905
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
912
{
906
{
913
	struct drm_i915_private *dev_priv;
907
	struct drm_i915_private *dev_priv;
Line 935... Line 929...
935
		ring->cleanup(ring);
929
		ring->cleanup(ring);
Line 936... Line 930...
936
 
930
 
937
//   cleanup_status_page(ring);
931
//   cleanup_status_page(ring);
Line 938... Line -...
938
}
-
 
939
 
932
}
940
 
933
 
941
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
934
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
942
{
935
{
Line 1034... Line 1027...
1034
{
1027
{
1035
	ring->tail &= ring->size - 1;
1028
	ring->tail &= ring->size - 1;
1036
	ring->write_tail(ring, ring->tail);
1029
	ring->write_tail(ring, ring->tail);
1037
}
1030
}
Line 1038... Line -...
1038
 
-
 
1039
 
1031
 
1040
static const struct intel_ring_buffer render_ring = {
1032
static const struct intel_ring_buffer render_ring = {
1041
	.name			= "render ring",
1033
	.name			= "render ring",
1042
	.id			= RING_RENDER,
1034
	.id			= RING_RENDER,
1043
	.mmio_base		= RENDER_RING_BASE,
1035
	.mmio_base		= RENDER_RING_BASE,
1044
	.size			= 32 * PAGE_SIZE,
1036
	.size			= 32 * PAGE_SIZE,
1045
	.init			= init_render_ring,
1037
	.init			= init_render_ring,
1046
    .write_tail     = ring_write_tail,
1038
    .write_tail     = ring_write_tail,
1047
    .flush          = render_ring_flush,
1039
    .flush          = render_ring_flush,
1048
//   .add_request        = render_ring_add_request,
1040
    .add_request        = render_ring_add_request,
1049
//   .get_seqno      = ring_get_seqno,
1041
//   .get_seqno      = ring_get_seqno,
1050
//   .irq_get        = render_ring_get_irq,
1042
//   .irq_get        = render_ring_get_irq,
1051
//   .irq_put        = render_ring_put_irq,
1043
//   .irq_put        = render_ring_put_irq,
1052
//   .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1044
//   .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
Line 1061... Line 1053...
1061
	.mmio_base		= BSD_RING_BASE,
1053
	.mmio_base		= BSD_RING_BASE,
1062
	.size			= 32 * PAGE_SIZE,
1054
	.size			= 32 * PAGE_SIZE,
1063
	.init			= init_ring_common,
1055
	.init			= init_ring_common,
1064
	.write_tail		= ring_write_tail,
1056
	.write_tail		= ring_write_tail,
1065
    .flush          = bsd_ring_flush,
1057
    .flush          = bsd_ring_flush,
1066
//   .add_request        = ring_add_request,
1058
    .add_request        = ring_add_request,
1067
//   .get_seqno      = ring_get_seqno,
1059
//   .get_seqno      = ring_get_seqno,
1068
//   .irq_get        = bsd_ring_get_irq,
1060
//   .irq_get        = bsd_ring_get_irq,
1069
//   .irq_put        = bsd_ring_put_irq,
1061
//   .irq_put        = bsd_ring_put_irq,
1070
//   .dispatch_execbuffer    = ring_dispatch_execbuffer,
1062
//   .dispatch_execbuffer    = ring_dispatch_execbuffer,
1071
};
1063
};
Line 1091... Line 1083...
1091
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1083
       I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1092
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1084
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1093
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1085
	       GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1094
}
1086
}
Line 1095... Line -...
1095
 
-
 
1096
 
1087
 
1097
static int gen6_ring_flush(struct intel_ring_buffer *ring,
1088
static int gen6_ring_flush(struct intel_ring_buffer *ring,
1098
			   u32 invalidate, u32 flush)
1089
			   u32 invalidate, u32 flush)
1099
{
1090
{
1100
	uint32_t cmd;
1091
	uint32_t cmd;
Line 1175... Line 1166...
1175
	.mmio_base		= GEN6_BSD_RING_BASE,
1166
	.mmio_base		= GEN6_BSD_RING_BASE,
1176
	.size			= 32 * PAGE_SIZE,
1167
	.size			= 32 * PAGE_SIZE,
1177
	.init			= init_ring_common,
1168
	.init			= init_ring_common,
1178
	.write_tail		= gen6_bsd_ring_write_tail,
1169
	.write_tail		= gen6_bsd_ring_write_tail,
1179
    .flush          = gen6_ring_flush,
1170
    .flush          = gen6_ring_flush,
1180
//   .add_request        = gen6_add_request,
1171
    .add_request        = gen6_add_request,
1181
//   .get_seqno      = ring_get_seqno,
1172
//   .get_seqno      = ring_get_seqno,
1182
//   .irq_get        = gen6_bsd_ring_get_irq,
1173
//   .irq_get        = gen6_bsd_ring_get_irq,
1183
//   .irq_put        = gen6_bsd_ring_put_irq,
1174
//   .irq_put        = gen6_bsd_ring_put_irq,
1184
//   .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1175
//   .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1185
};
1176
};
Line 1217... Line 1208...
1217
to_blt_workaround(struct intel_ring_buffer *ring)
1208
to_blt_workaround(struct intel_ring_buffer *ring)
1218
{
1209
{
1219
	return ring->private;
1210
	return ring->private;
1220
}
1211
}
Line 1221... Line -...
1221
 
-
 
1222
 
1212
 
1223
static int blt_ring_init(struct intel_ring_buffer *ring)
1213
static int blt_ring_init(struct intel_ring_buffer *ring)
1224
{
1214
{
1225
	if (NEED_BLT_WORKAROUND(ring->dev)) {
1215
	if (NEED_BLT_WORKAROUND(ring->dev)) {
1226
		struct drm_i915_gem_object *obj;
1216
		struct drm_i915_gem_object *obj;
Line 1300... Line 1290...
1300
	i915_gem_object_unpin(ring->private);
1290
	i915_gem_object_unpin(ring->private);
1301
	drm_gem_object_unreference(ring->private);
1291
	drm_gem_object_unreference(ring->private);
1302
	ring->private = NULL;
1292
	ring->private = NULL;
1303
}
1293
}
Line 1304... Line -...
1304
 
-
 
1305
 
1294
 
1306
static const struct intel_ring_buffer gen6_blt_ring = {
1295
static const struct intel_ring_buffer gen6_blt_ring = {
1307
       .name			= "blt ring",
1296
       .name			= "blt ring",
1308
       .id			= RING_BLT,
1297
       .id			= RING_BLT,
1309
       .mmio_base		= BLT_RING_BASE,
1298
       .mmio_base		= BLT_RING_BASE,
1310
       .size			= 32 * PAGE_SIZE,
1299
       .size			= 32 * PAGE_SIZE,
1311
       .init			= blt_ring_init,
1300
       .init			= blt_ring_init,
1312
       .write_tail		= ring_write_tail,
1301
       .write_tail		= ring_write_tail,
1313
       .flush          = blt_ring_flush,
1302
       .flush          = blt_ring_flush,
1314
//       .add_request        = gen6_add_request,
1303
       .add_request        = gen6_add_request,
1315
//       .get_seqno      = ring_get_seqno,
1304
//       .get_seqno      = ring_get_seqno,
1316
//       .irq_get            = blt_ring_get_irq,
1305
//       .irq_get            = blt_ring_get_irq,
1317
//       .irq_put            = blt_ring_put_irq,
1306
//       .irq_put            = blt_ring_put_irq,
1318
//       .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1307
//       .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1319
//       .cleanup            = blt_ring_cleanup,
1308
//       .cleanup            = blt_ring_cleanup,
Line 1320... Line -...
1320
};
-
 
1321
 
-
 
1322
 
1309
};
1323
 
1310
 
1324
int intel_init_render_ring_buffer(struct drm_device *dev)
1311
int intel_init_render_ring_buffer(struct drm_device *dev)
1325
{
1312
{
1326
	drm_i915_private_t *dev_priv = dev->dev_private;
1313
	drm_i915_private_t *dev_priv = dev->dev_private;
1327
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1314
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1328
    ENTER();
1315
    ENTER();
1329
	*ring = render_ring;
1316
	*ring = render_ring;
1330
	if (INTEL_INFO(dev)->gen >= 6) {
1317
	if (INTEL_INFO(dev)->gen >= 6) {
1331
//       ring->add_request = gen6_add_request;
1318
       ring->add_request = gen6_add_request;
1332
//       ring->irq_get = gen6_render_ring_get_irq;
1319
//       ring->irq_get = gen6_render_ring_get_irq;
1333
//       ring->irq_put = gen6_render_ring_put_irq;
1320
//       ring->irq_put = gen6_render_ring_put_irq;
1334
	} else if (IS_GEN5(dev)) {
1321
	} else if (IS_GEN5(dev)) {
1335
//       ring->add_request = pc_render_add_request;
1322
       ring->add_request = pc_render_add_request;
Line 1336... Line 1323...
1336
//       ring->get_seqno = pc_render_get_seqno;
1323
//       ring->get_seqno = pc_render_get_seqno;
1337
	}
1324
	}