Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6937 | Rev 7144 | ||
|---|---|---|---|
| Line 223... | Line 223... | ||
| 223 | (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
223 | (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 224 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
224 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 225 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
225 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
| 226 | } |
226 | } |
| Line -... | Line 227... | ||
| - | 227 | ||
| - | 228 | if (dev_priv->psr.link_standby) |
|
| - | 229 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
|
| - | 230 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
|
| 227 | 231 | else |
|
| - | 232 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
|
| 228 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE); |
233 | DP_PSR_ENABLE); |
| Line 229... | Line 234... | ||
| 229 | } |
234 | } |
| 230 | 235 | ||
| 231 | static void vlv_psr_enable_source(struct intel_dp *intel_dp) |
236 | static void vlv_psr_enable_source(struct intel_dp *intel_dp) |
| Line 281... | Line 286... | ||
| 281 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; |
286 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; |
| Line 282... | Line 287... | ||
| 282 | 287 | ||
| 283 | if (IS_HASWELL(dev)) |
288 | if (IS_HASWELL(dev)) |
| Line -... | Line 289... | ||
| - | 289 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
|
| - | 290 | ||
| - | 291 | if (dev_priv->psr.link_standby) |
|
| 284 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
292 | val |= EDP_PSR_LINK_STANDBY; |
| 285 | 293 | ||
| 286 | if (dev_priv->vbt.psr.tp1_wakeup_time > 5) |
294 | if (dev_priv->vbt.psr.tp1_wakeup_time > 5) |
| 287 | val |= EDP_PSR_TP1_TIME_2500us; |
295 | val |= EDP_PSR_TP1_TIME_2500us; |
| 288 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) |
296 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) |
| Line 341... | Line 349... | ||
| 341 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
349 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 342 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
350 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
| Line 343... | Line 351... | ||
| 343 | 351 | ||
| Line -... | Line 352... | ||
| - | 352 | dev_priv->psr.source_ok = false; |
|
| - | 353 | ||
| - | 354 | /* |
|
| - | 355 | * HSW spec explicitly says PSR is tied to port A. |
|
| - | 356 | * BDW+ platforms with DDI implementation of PSR have different |
|
| - | 357 | * PSR registers per transcoder and we only implement transcoder EDP |
|
| - | 358 | * ones. Since by Display design transcoder EDP is tied to port A |
|
| 344 | dev_priv->psr.source_ok = false; |
359 | * we can safely escape based on the port A. |
| 345 | 360 | */ |
|
| 346 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
361 | if (HAS_DDI(dev) && dig_port->port != PORT_A) { |
| 347 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
362 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
| Line 348... | Line 363... | ||
| 348 | return false; |
363 | return false; |
| 349 | } |
364 | } |
| 350 | 365 | ||
| 351 | if (!i915.enable_psr) { |
366 | if (!i915.enable_psr) { |
| Line -... | Line 367... | ||
| - | 367 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
|
| - | 368 | return false; |
|
| - | 369 | } |
|
| - | 370 | ||
| - | 371 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
|
| - | 372 | !dev_priv->psr.link_standby) { |
|
| 352 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
373 | DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n"); |
| 353 | return false; |
374 | return false; |
| 354 | } |
375 | } |
| 355 | 376 | ||
| 356 | if (IS_HASWELL(dev) && |
377 | if (IS_HASWELL(dev) && |
| Line 364... | Line 385... | ||
| 364 | intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
385 | intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
| 365 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
386 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
| 366 | return false; |
387 | return false; |
| 367 | } |
388 | } |
| Line 368... | Line -... | ||
| 368 | - | ||
| 369 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
- | |
| 370 | ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) { |
- | |
| 371 | DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n"); |
- | |
| 372 | return false; |
- | |
| 373 | } |
- | |
| 374 | 389 | ||
| 375 | dev_priv->psr.source_ok = true; |
390 | dev_priv->psr.source_ok = true; |
| 376 | return true; |
391 | return true; |
| Line 377... | Line 392... | ||
| 377 | } |
392 | } |
| Line 800... | Line 815... | ||
| 800 | struct drm_i915_private *dev_priv = dev->dev_private; |
815 | struct drm_i915_private *dev_priv = dev->dev_private; |
| Line 801... | Line 816... | ||
| 801 | 816 | ||
| 802 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
817 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
| Line -... | Line 818... | ||
| - | 818 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; |
|
| - | 819 | ||
| - | 820 | /* Per platform default */ |
|
| - | 821 | if (i915.enable_psr == -1) { |
|
| - | 822 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || |
|
| - | 823 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
|
| - | 824 | i915.enable_psr = 1; |
|
| - | 825 | else |
|
| - | 826 | i915.enable_psr = 0; |
|
| - | 827 | } |
|
| - | 828 | ||
| - | 829 | /* Set link_standby x link_off defaults */ |
|
| - | 830 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
| - | 831 | /* HSW and BDW require workarounds that we don't implement. */ |
|
| - | 832 | dev_priv->psr.link_standby = false; |
|
| - | 833 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
|
| - | 834 | /* On VLV and CHV only standby mode is supported. */ |
|
| - | 835 | dev_priv->psr.link_standby = true; |
|
| - | 836 | else |
|
| - | 837 | /* For new platforms let's respect VBT back again */ |
|
| - | 838 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; |
|
| - | 839 | ||
| - | 840 | /* Override link_standby x link_off defaults */ |
|
| - | 841 | if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) { |
|
| - | 842 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); |
|
| - | 843 | dev_priv->psr.link_standby = true; |
|
| - | 844 | } |
|
| - | 845 | if (i915.enable_psr == 3 && dev_priv->psr.link_standby) { |
|
| - | 846 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); |
|
| - | 847 | dev_priv->psr.link_standby = false; |
|
| 803 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; |
848 | } |
| 804 | 849 | ||
| 805 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |
850 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |