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1 | /* |
1 | /* |
2 | * Copyright © 2012 Intel Corporation |
2 | * Copyright © 2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eugeni Dodonov |
24 | * Eugeni Dodonov |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | //#include |
28 | //#include |
29 | #include "i915_drv.h" |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" |
30 | #include "intel_drv.h" |
31 | //#include "../../../platform/x86/intel_ips.h" |
31 | //#include "../../../platform/x86/intel_ips.h" |
32 | #include |
32 | #include |
33 | 33 | ||
34 | 34 | ||
35 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
35 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
36 | 36 | ||
37 | void getrawmonotonic(struct timespec *ts); |
37 | void getrawmonotonic(struct timespec *ts); |
38 | 38 | ||
39 | /** |
39 | /** |
40 | * RC6 is a special power stage which allows the GPU to enter an very |
40 | * RC6 is a special power stage which allows the GPU to enter an very |
41 | * low-voltage mode when idle, using down to 0V while at this stage. This |
41 | * low-voltage mode when idle, using down to 0V while at this stage. This |
42 | * stage is entered automatically when the GPU is idle when RC6 support is |
42 | * stage is entered automatically when the GPU is idle when RC6 support is |
43 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
43 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
44 | * |
44 | * |
45 | * There are different RC6 modes available in Intel GPU, which differentiate |
45 | * There are different RC6 modes available in Intel GPU, which differentiate |
46 | * among each other with the latency required to enter and leave RC6 and |
46 | * among each other with the latency required to enter and leave RC6 and |
47 | * voltage consumed by the GPU in different states. |
47 | * voltage consumed by the GPU in different states. |
48 | * |
48 | * |
49 | * The combination of the following flags define which states GPU is allowed |
49 | * The combination of the following flags define which states GPU is allowed |
50 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
50 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
51 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
51 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
52 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
52 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
53 | * which brings the most power savings; deeper states save more power, but |
53 | * which brings the most power savings; deeper states save more power, but |
54 | * require higher latency to switch to and wake up. |
54 | * require higher latency to switch to and wake up. |
55 | */ |
55 | */ |
56 | #define INTEL_RC6_ENABLE (1<<0) |
56 | #define INTEL_RC6_ENABLE (1<<0) |
57 | #define INTEL_RC6p_ENABLE (1<<1) |
57 | #define INTEL_RC6p_ENABLE (1<<1) |
58 | #define INTEL_RC6pp_ENABLE (1<<2) |
58 | #define INTEL_RC6pp_ENABLE (1<<2) |
59 | 59 | ||
60 | static void bxt_init_clock_gating(struct drm_device *dev) |
60 | static void bxt_init_clock_gating(struct drm_device *dev) |
61 | { |
61 | { |
62 | struct drm_i915_private *dev_priv = dev->dev_private; |
62 | struct drm_i915_private *dev_priv = dev->dev_private; |
63 | 63 | ||
64 | /* WaDisableSDEUnitClockGating:bxt */ |
64 | /* WaDisableSDEUnitClockGating:bxt */ |
65 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
65 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
66 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
66 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
67 | 67 | ||
68 | /* |
68 | /* |
69 | * FIXME: |
69 | * FIXME: |
70 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
70 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
71 | */ |
71 | */ |
72 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
72 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
73 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
73 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
- | 74 | ||
- | 75 | /* |
|
- | 76 | * Wa: Backlight PWM may stop in the asserted state, causing backlight |
|
- | 77 | * to stay fully on. |
|
- | 78 | */ |
|
- | 79 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
|
- | 80 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | |
|
- | 81 | PWM1_GATING_DIS | PWM2_GATING_DIS); |
|
74 | } |
82 | } |
75 | 83 | ||
76 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
84 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
77 | { |
85 | { |
78 | struct drm_i915_private *dev_priv = dev->dev_private; |
86 | struct drm_i915_private *dev_priv = dev->dev_private; |
79 | u32 tmp; |
87 | u32 tmp; |
80 | 88 | ||
81 | tmp = I915_READ(CLKCFG); |
89 | tmp = I915_READ(CLKCFG); |
82 | 90 | ||
83 | switch (tmp & CLKCFG_FSB_MASK) { |
91 | switch (tmp & CLKCFG_FSB_MASK) { |
84 | case CLKCFG_FSB_533: |
92 | case CLKCFG_FSB_533: |
85 | dev_priv->fsb_freq = 533; /* 133*4 */ |
93 | dev_priv->fsb_freq = 533; /* 133*4 */ |
86 | break; |
94 | break; |
87 | case CLKCFG_FSB_800: |
95 | case CLKCFG_FSB_800: |
88 | dev_priv->fsb_freq = 800; /* 200*4 */ |
96 | dev_priv->fsb_freq = 800; /* 200*4 */ |
89 | break; |
97 | break; |
90 | case CLKCFG_FSB_667: |
98 | case CLKCFG_FSB_667: |
91 | dev_priv->fsb_freq = 667; /* 167*4 */ |
99 | dev_priv->fsb_freq = 667; /* 167*4 */ |
92 | break; |
100 | break; |
93 | case CLKCFG_FSB_400: |
101 | case CLKCFG_FSB_400: |
94 | dev_priv->fsb_freq = 400; /* 100*4 */ |
102 | dev_priv->fsb_freq = 400; /* 100*4 */ |
95 | break; |
103 | break; |
96 | } |
104 | } |
97 | 105 | ||
98 | switch (tmp & CLKCFG_MEM_MASK) { |
106 | switch (tmp & CLKCFG_MEM_MASK) { |
99 | case CLKCFG_MEM_533: |
107 | case CLKCFG_MEM_533: |
100 | dev_priv->mem_freq = 533; |
108 | dev_priv->mem_freq = 533; |
101 | break; |
109 | break; |
102 | case CLKCFG_MEM_667: |
110 | case CLKCFG_MEM_667: |
103 | dev_priv->mem_freq = 667; |
111 | dev_priv->mem_freq = 667; |
104 | break; |
112 | break; |
105 | case CLKCFG_MEM_800: |
113 | case CLKCFG_MEM_800: |
106 | dev_priv->mem_freq = 800; |
114 | dev_priv->mem_freq = 800; |
107 | break; |
115 | break; |
108 | } |
116 | } |
109 | 117 | ||
110 | /* detect pineview DDR3 setting */ |
118 | /* detect pineview DDR3 setting */ |
111 | tmp = I915_READ(CSHRDDR3CTL); |
119 | tmp = I915_READ(CSHRDDR3CTL); |
112 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
120 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
113 | } |
121 | } |
114 | 122 | ||
115 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
123 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
116 | { |
124 | { |
117 | struct drm_i915_private *dev_priv = dev->dev_private; |
125 | struct drm_i915_private *dev_priv = dev->dev_private; |
118 | u16 ddrpll, csipll; |
126 | u16 ddrpll, csipll; |
119 | 127 | ||
120 | ddrpll = I915_READ16(DDRMPLL1); |
128 | ddrpll = I915_READ16(DDRMPLL1); |
121 | csipll = I915_READ16(CSIPLL0); |
129 | csipll = I915_READ16(CSIPLL0); |
122 | 130 | ||
123 | switch (ddrpll & 0xff) { |
131 | switch (ddrpll & 0xff) { |
124 | case 0xc: |
132 | case 0xc: |
125 | dev_priv->mem_freq = 800; |
133 | dev_priv->mem_freq = 800; |
126 | break; |
134 | break; |
127 | case 0x10: |
135 | case 0x10: |
128 | dev_priv->mem_freq = 1066; |
136 | dev_priv->mem_freq = 1066; |
129 | break; |
137 | break; |
130 | case 0x14: |
138 | case 0x14: |
131 | dev_priv->mem_freq = 1333; |
139 | dev_priv->mem_freq = 1333; |
132 | break; |
140 | break; |
133 | case 0x18: |
141 | case 0x18: |
134 | dev_priv->mem_freq = 1600; |
142 | dev_priv->mem_freq = 1600; |
135 | break; |
143 | break; |
136 | default: |
144 | default: |
137 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
145 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
138 | ddrpll & 0xff); |
146 | ddrpll & 0xff); |
139 | dev_priv->mem_freq = 0; |
147 | dev_priv->mem_freq = 0; |
140 | break; |
148 | break; |
141 | } |
149 | } |
142 | 150 | ||
143 | dev_priv->ips.r_t = dev_priv->mem_freq; |
151 | dev_priv->ips.r_t = dev_priv->mem_freq; |
144 | 152 | ||
145 | switch (csipll & 0x3ff) { |
153 | switch (csipll & 0x3ff) { |
146 | case 0x00c: |
154 | case 0x00c: |
147 | dev_priv->fsb_freq = 3200; |
155 | dev_priv->fsb_freq = 3200; |
148 | break; |
156 | break; |
149 | case 0x00e: |
157 | case 0x00e: |
150 | dev_priv->fsb_freq = 3733; |
158 | dev_priv->fsb_freq = 3733; |
151 | break; |
159 | break; |
152 | case 0x010: |
160 | case 0x010: |
153 | dev_priv->fsb_freq = 4266; |
161 | dev_priv->fsb_freq = 4266; |
154 | break; |
162 | break; |
155 | case 0x012: |
163 | case 0x012: |
156 | dev_priv->fsb_freq = 4800; |
164 | dev_priv->fsb_freq = 4800; |
157 | break; |
165 | break; |
158 | case 0x014: |
166 | case 0x014: |
159 | dev_priv->fsb_freq = 5333; |
167 | dev_priv->fsb_freq = 5333; |
160 | break; |
168 | break; |
161 | case 0x016: |
169 | case 0x016: |
162 | dev_priv->fsb_freq = 5866; |
170 | dev_priv->fsb_freq = 5866; |
163 | break; |
171 | break; |
164 | case 0x018: |
172 | case 0x018: |
165 | dev_priv->fsb_freq = 6400; |
173 | dev_priv->fsb_freq = 6400; |
166 | break; |
174 | break; |
167 | default: |
175 | default: |
168 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
176 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
169 | csipll & 0x3ff); |
177 | csipll & 0x3ff); |
170 | dev_priv->fsb_freq = 0; |
178 | dev_priv->fsb_freq = 0; |
171 | break; |
179 | break; |
172 | } |
180 | } |
173 | 181 | ||
174 | if (dev_priv->fsb_freq == 3200) { |
182 | if (dev_priv->fsb_freq == 3200) { |
175 | dev_priv->ips.c_m = 0; |
183 | dev_priv->ips.c_m = 0; |
176 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
184 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
177 | dev_priv->ips.c_m = 1; |
185 | dev_priv->ips.c_m = 1; |
178 | } else { |
186 | } else { |
179 | dev_priv->ips.c_m = 2; |
187 | dev_priv->ips.c_m = 2; |
180 | } |
188 | } |
181 | } |
189 | } |
182 | 190 | ||
183 | static const struct cxsr_latency cxsr_latency_table[] = { |
191 | static const struct cxsr_latency cxsr_latency_table[] = { |
184 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
192 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
185 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
193 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
186 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
194 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
187 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
195 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
188 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
196 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
189 | 197 | ||
190 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
198 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
191 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
199 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
192 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
200 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
193 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
201 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
194 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
202 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
195 | 203 | ||
196 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
204 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
197 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
205 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
198 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
206 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
199 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
207 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
200 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
208 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
201 | 209 | ||
202 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
210 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
203 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
211 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
204 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
212 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
205 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
213 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
206 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
214 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
207 | 215 | ||
208 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
216 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
209 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
217 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
210 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
218 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
211 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
219 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
212 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
220 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
213 | 221 | ||
214 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
222 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
215 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
223 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
216 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
224 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
217 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
225 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
218 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
226 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
219 | }; |
227 | }; |
220 | 228 | ||
221 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
229 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
222 | int is_ddr3, |
230 | int is_ddr3, |
223 | int fsb, |
231 | int fsb, |
224 | int mem) |
232 | int mem) |
225 | { |
233 | { |
226 | const struct cxsr_latency *latency; |
234 | const struct cxsr_latency *latency; |
227 | int i; |
235 | int i; |
228 | 236 | ||
229 | if (fsb == 0 || mem == 0) |
237 | if (fsb == 0 || mem == 0) |
230 | return NULL; |
238 | return NULL; |
231 | 239 | ||
232 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
240 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
233 | latency = &cxsr_latency_table[i]; |
241 | latency = &cxsr_latency_table[i]; |
234 | if (is_desktop == latency->is_desktop && |
242 | if (is_desktop == latency->is_desktop && |
235 | is_ddr3 == latency->is_ddr3 && |
243 | is_ddr3 == latency->is_ddr3 && |
236 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
244 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
237 | return latency; |
245 | return latency; |
238 | } |
246 | } |
239 | 247 | ||
240 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
248 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
241 | 249 | ||
242 | return NULL; |
250 | return NULL; |
243 | } |
251 | } |
244 | 252 | ||
245 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
253 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
246 | { |
254 | { |
247 | u32 val; |
255 | u32 val; |
248 | 256 | ||
249 | mutex_lock(&dev_priv->rps.hw_lock); |
257 | mutex_lock(&dev_priv->rps.hw_lock); |
250 | 258 | ||
251 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
259 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
252 | if (enable) |
260 | if (enable) |
253 | val &= ~FORCE_DDR_HIGH_FREQ; |
261 | val &= ~FORCE_DDR_HIGH_FREQ; |
254 | else |
262 | else |
255 | val |= FORCE_DDR_HIGH_FREQ; |
263 | val |= FORCE_DDR_HIGH_FREQ; |
256 | val &= ~FORCE_DDR_LOW_FREQ; |
264 | val &= ~FORCE_DDR_LOW_FREQ; |
257 | val |= FORCE_DDR_FREQ_REQ_ACK; |
265 | val |= FORCE_DDR_FREQ_REQ_ACK; |
258 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
266 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
259 | 267 | ||
260 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
268 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
261 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) |
269 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) |
262 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); |
270 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); |
263 | 271 | ||
264 | mutex_unlock(&dev_priv->rps.hw_lock); |
272 | mutex_unlock(&dev_priv->rps.hw_lock); |
265 | } |
273 | } |
266 | 274 | ||
267 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
275 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
268 | { |
276 | { |
269 | u32 val; |
277 | u32 val; |
270 | 278 | ||
271 | mutex_lock(&dev_priv->rps.hw_lock); |
279 | mutex_lock(&dev_priv->rps.hw_lock); |
272 | 280 | ||
273 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
281 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
274 | if (enable) |
282 | if (enable) |
275 | val |= DSP_MAXFIFO_PM5_ENABLE; |
283 | val |= DSP_MAXFIFO_PM5_ENABLE; |
276 | else |
284 | else |
277 | val &= ~DSP_MAXFIFO_PM5_ENABLE; |
285 | val &= ~DSP_MAXFIFO_PM5_ENABLE; |
278 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
286 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
279 | 287 | ||
280 | mutex_unlock(&dev_priv->rps.hw_lock); |
288 | mutex_unlock(&dev_priv->rps.hw_lock); |
281 | } |
289 | } |
282 | 290 | ||
283 | #define FW_WM(value, plane) \ |
291 | #define FW_WM(value, plane) \ |
284 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) |
292 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) |
285 | 293 | ||
286 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
294 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
287 | { |
295 | { |
288 | struct drm_device *dev = dev_priv->dev; |
296 | struct drm_device *dev = dev_priv->dev; |
289 | u32 val; |
297 | u32 val; |
290 | 298 | ||
291 | if (IS_VALLEYVIEW(dev)) { |
299 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
292 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
300 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
293 | POSTING_READ(FW_BLC_SELF_VLV); |
301 | POSTING_READ(FW_BLC_SELF_VLV); |
294 | dev_priv->wm.vlv.cxsr = enable; |
302 | dev_priv->wm.vlv.cxsr = enable; |
295 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
303 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
296 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
304 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
297 | POSTING_READ(FW_BLC_SELF); |
305 | POSTING_READ(FW_BLC_SELF); |
298 | } else if (IS_PINEVIEW(dev)) { |
306 | } else if (IS_PINEVIEW(dev)) { |
299 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; |
307 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; |
300 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; |
308 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; |
301 | I915_WRITE(DSPFW3, val); |
309 | I915_WRITE(DSPFW3, val); |
302 | POSTING_READ(DSPFW3); |
310 | POSTING_READ(DSPFW3); |
303 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
311 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
304 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
312 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
305 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); |
313 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); |
306 | I915_WRITE(FW_BLC_SELF, val); |
314 | I915_WRITE(FW_BLC_SELF, val); |
307 | POSTING_READ(FW_BLC_SELF); |
315 | POSTING_READ(FW_BLC_SELF); |
308 | } else if (IS_I915GM(dev)) { |
316 | } else if (IS_I915GM(dev)) { |
309 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
317 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
310 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); |
318 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); |
311 | I915_WRITE(INSTPM, val); |
319 | I915_WRITE(INSTPM, val); |
312 | POSTING_READ(INSTPM); |
320 | POSTING_READ(INSTPM); |
313 | } else { |
321 | } else { |
314 | return; |
322 | return; |
315 | } |
323 | } |
316 | 324 | ||
317 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
325 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
318 | enable ? "enabled" : "disabled"); |
326 | enable ? "enabled" : "disabled"); |
319 | } |
327 | } |
320 | 328 | ||
321 | 329 | ||
322 | /* |
330 | /* |
323 | * Latency for FIFO fetches is dependent on several factors: |
331 | * Latency for FIFO fetches is dependent on several factors: |
324 | * - memory configuration (speed, channels) |
332 | * - memory configuration (speed, channels) |
325 | * - chipset |
333 | * - chipset |
326 | * - current MCH state |
334 | * - current MCH state |
327 | * It can be fairly high in some situations, so here we assume a fairly |
335 | * It can be fairly high in some situations, so here we assume a fairly |
328 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
336 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
329 | * set this value too high, the FIFO will fetch frequently to stay full) |
337 | * set this value too high, the FIFO will fetch frequently to stay full) |
330 | * and power consumption (set it too low to save power and we might see |
338 | * and power consumption (set it too low to save power and we might see |
331 | * FIFO underruns and display "flicker"). |
339 | * FIFO underruns and display "flicker"). |
332 | * |
340 | * |
333 | * A value of 5us seems to be a good balance; safe for very low end |
341 | * A value of 5us seems to be a good balance; safe for very low end |
334 | * platforms but not overly aggressive on lower latency configs. |
342 | * platforms but not overly aggressive on lower latency configs. |
335 | */ |
343 | */ |
336 | static const int pessimal_latency_ns = 5000; |
344 | static const int pessimal_latency_ns = 5000; |
337 | 345 | ||
338 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
346 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
339 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) |
347 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) |
340 | 348 | ||
341 | static int vlv_get_fifo_size(struct drm_device *dev, |
349 | static int vlv_get_fifo_size(struct drm_device *dev, |
342 | enum pipe pipe, int plane) |
350 | enum pipe pipe, int plane) |
343 | { |
351 | { |
344 | struct drm_i915_private *dev_priv = dev->dev_private; |
352 | struct drm_i915_private *dev_priv = dev->dev_private; |
345 | int sprite0_start, sprite1_start, size; |
353 | int sprite0_start, sprite1_start, size; |
346 | 354 | ||
347 | switch (pipe) { |
355 | switch (pipe) { |
348 | uint32_t dsparb, dsparb2, dsparb3; |
356 | uint32_t dsparb, dsparb2, dsparb3; |
349 | case PIPE_A: |
357 | case PIPE_A: |
350 | dsparb = I915_READ(DSPARB); |
358 | dsparb = I915_READ(DSPARB); |
351 | dsparb2 = I915_READ(DSPARB2); |
359 | dsparb2 = I915_READ(DSPARB2); |
352 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); |
360 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); |
353 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); |
361 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); |
354 | break; |
362 | break; |
355 | case PIPE_B: |
363 | case PIPE_B: |
356 | dsparb = I915_READ(DSPARB); |
364 | dsparb = I915_READ(DSPARB); |
357 | dsparb2 = I915_READ(DSPARB2); |
365 | dsparb2 = I915_READ(DSPARB2); |
358 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); |
366 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); |
359 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); |
367 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); |
360 | break; |
368 | break; |
361 | case PIPE_C: |
369 | case PIPE_C: |
362 | dsparb2 = I915_READ(DSPARB2); |
370 | dsparb2 = I915_READ(DSPARB2); |
363 | dsparb3 = I915_READ(DSPARB3); |
371 | dsparb3 = I915_READ(DSPARB3); |
364 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); |
372 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); |
365 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); |
373 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); |
366 | break; |
374 | break; |
367 | default: |
375 | default: |
368 | return 0; |
376 | return 0; |
369 | } |
377 | } |
370 | 378 | ||
371 | switch (plane) { |
379 | switch (plane) { |
372 | case 0: |
380 | case 0: |
373 | size = sprite0_start; |
381 | size = sprite0_start; |
374 | break; |
382 | break; |
375 | case 1: |
383 | case 1: |
376 | size = sprite1_start - sprite0_start; |
384 | size = sprite1_start - sprite0_start; |
377 | break; |
385 | break; |
378 | case 2: |
386 | case 2: |
379 | size = 512 - 1 - sprite1_start; |
387 | size = 512 - 1 - sprite1_start; |
380 | break; |
388 | break; |
381 | default: |
389 | default: |
382 | return 0; |
390 | return 0; |
383 | } |
391 | } |
384 | 392 | ||
385 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", |
393 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", |
386 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", |
394 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", |
387 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), |
395 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), |
388 | size); |
396 | size); |
389 | 397 | ||
390 | return size; |
398 | return size; |
391 | } |
399 | } |
392 | 400 | ||
393 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
401 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
394 | { |
402 | { |
395 | struct drm_i915_private *dev_priv = dev->dev_private; |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
396 | uint32_t dsparb = I915_READ(DSPARB); |
404 | uint32_t dsparb = I915_READ(DSPARB); |
397 | int size; |
405 | int size; |
398 | 406 | ||
399 | size = dsparb & 0x7f; |
407 | size = dsparb & 0x7f; |
400 | if (plane) |
408 | if (plane) |
401 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
409 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
402 | 410 | ||
403 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
411 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
404 | plane ? "B" : "A", size); |
412 | plane ? "B" : "A", size); |
405 | 413 | ||
406 | return size; |
414 | return size; |
407 | } |
415 | } |
408 | 416 | ||
409 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
417 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
410 | { |
418 | { |
411 | struct drm_i915_private *dev_priv = dev->dev_private; |
419 | struct drm_i915_private *dev_priv = dev->dev_private; |
412 | uint32_t dsparb = I915_READ(DSPARB); |
420 | uint32_t dsparb = I915_READ(DSPARB); |
413 | int size; |
421 | int size; |
414 | 422 | ||
415 | size = dsparb & 0x1ff; |
423 | size = dsparb & 0x1ff; |
416 | if (plane) |
424 | if (plane) |
417 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
425 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
418 | size >>= 1; /* Convert to cachelines */ |
426 | size >>= 1; /* Convert to cachelines */ |
419 | 427 | ||
420 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
428 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
421 | plane ? "B" : "A", size); |
429 | plane ? "B" : "A", size); |
422 | 430 | ||
423 | return size; |
431 | return size; |
424 | } |
432 | } |
425 | 433 | ||
426 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
434 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
427 | { |
435 | { |
428 | struct drm_i915_private *dev_priv = dev->dev_private; |
436 | struct drm_i915_private *dev_priv = dev->dev_private; |
429 | uint32_t dsparb = I915_READ(DSPARB); |
437 | uint32_t dsparb = I915_READ(DSPARB); |
430 | int size; |
438 | int size; |
431 | 439 | ||
432 | size = dsparb & 0x7f; |
440 | size = dsparb & 0x7f; |
433 | size >>= 2; /* Convert to cachelines */ |
441 | size >>= 2; /* Convert to cachelines */ |
434 | 442 | ||
435 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
443 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
436 | plane ? "B" : "A", |
444 | plane ? "B" : "A", |
437 | size); |
445 | size); |
438 | 446 | ||
439 | return size; |
447 | return size; |
440 | } |
448 | } |
441 | 449 | ||
442 | /* Pineview has different values for various configs */ |
450 | /* Pineview has different values for various configs */ |
443 | static const struct intel_watermark_params pineview_display_wm = { |
451 | static const struct intel_watermark_params pineview_display_wm = { |
444 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
452 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
445 | .max_wm = PINEVIEW_MAX_WM, |
453 | .max_wm = PINEVIEW_MAX_WM, |
446 | .default_wm = PINEVIEW_DFT_WM, |
454 | .default_wm = PINEVIEW_DFT_WM, |
447 | .guard_size = PINEVIEW_GUARD_WM, |
455 | .guard_size = PINEVIEW_GUARD_WM, |
448 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
456 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
449 | }; |
457 | }; |
450 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
458 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
451 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
459 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
452 | .max_wm = PINEVIEW_MAX_WM, |
460 | .max_wm = PINEVIEW_MAX_WM, |
453 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, |
461 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, |
454 | .guard_size = PINEVIEW_GUARD_WM, |
462 | .guard_size = PINEVIEW_GUARD_WM, |
455 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
463 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
456 | }; |
464 | }; |
457 | static const struct intel_watermark_params pineview_cursor_wm = { |
465 | static const struct intel_watermark_params pineview_cursor_wm = { |
458 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
466 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
459 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
467 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
460 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
468 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
461 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
469 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
462 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
470 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
463 | }; |
471 | }; |
464 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
472 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
465 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
473 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
466 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
474 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
467 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
475 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
468 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
476 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
469 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
477 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
470 | }; |
478 | }; |
471 | static const struct intel_watermark_params g4x_wm_info = { |
479 | static const struct intel_watermark_params g4x_wm_info = { |
472 | .fifo_size = G4X_FIFO_SIZE, |
480 | .fifo_size = G4X_FIFO_SIZE, |
473 | .max_wm = G4X_MAX_WM, |
481 | .max_wm = G4X_MAX_WM, |
474 | .default_wm = G4X_MAX_WM, |
482 | .default_wm = G4X_MAX_WM, |
475 | .guard_size = 2, |
483 | .guard_size = 2, |
476 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
484 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
477 | }; |
485 | }; |
478 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
486 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
479 | .fifo_size = I965_CURSOR_FIFO, |
487 | .fifo_size = I965_CURSOR_FIFO, |
480 | .max_wm = I965_CURSOR_MAX_WM, |
488 | .max_wm = I965_CURSOR_MAX_WM, |
481 | .default_wm = I965_CURSOR_DFT_WM, |
489 | .default_wm = I965_CURSOR_DFT_WM, |
482 | .guard_size = 2, |
490 | .guard_size = 2, |
483 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
491 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
484 | }; |
492 | }; |
485 | static const struct intel_watermark_params valleyview_wm_info = { |
493 | static const struct intel_watermark_params valleyview_wm_info = { |
486 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
494 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
487 | .max_wm = VALLEYVIEW_MAX_WM, |
495 | .max_wm = VALLEYVIEW_MAX_WM, |
488 | .default_wm = VALLEYVIEW_MAX_WM, |
496 | .default_wm = VALLEYVIEW_MAX_WM, |
489 | .guard_size = 2, |
497 | .guard_size = 2, |
490 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
498 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
491 | }; |
499 | }; |
492 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
500 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
493 | .fifo_size = I965_CURSOR_FIFO, |
501 | .fifo_size = I965_CURSOR_FIFO, |
494 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, |
502 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, |
495 | .default_wm = I965_CURSOR_DFT_WM, |
503 | .default_wm = I965_CURSOR_DFT_WM, |
496 | .guard_size = 2, |
504 | .guard_size = 2, |
497 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
505 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
498 | }; |
506 | }; |
499 | static const struct intel_watermark_params i965_cursor_wm_info = { |
507 | static const struct intel_watermark_params i965_cursor_wm_info = { |
500 | .fifo_size = I965_CURSOR_FIFO, |
508 | .fifo_size = I965_CURSOR_FIFO, |
501 | .max_wm = I965_CURSOR_MAX_WM, |
509 | .max_wm = I965_CURSOR_MAX_WM, |
502 | .default_wm = I965_CURSOR_DFT_WM, |
510 | .default_wm = I965_CURSOR_DFT_WM, |
503 | .guard_size = 2, |
511 | .guard_size = 2, |
504 | .cacheline_size = I915_FIFO_LINE_SIZE, |
512 | .cacheline_size = I915_FIFO_LINE_SIZE, |
505 | }; |
513 | }; |
506 | static const struct intel_watermark_params i945_wm_info = { |
514 | static const struct intel_watermark_params i945_wm_info = { |
507 | .fifo_size = I945_FIFO_SIZE, |
515 | .fifo_size = I945_FIFO_SIZE, |
508 | .max_wm = I915_MAX_WM, |
516 | .max_wm = I915_MAX_WM, |
509 | .default_wm = 1, |
517 | .default_wm = 1, |
510 | .guard_size = 2, |
518 | .guard_size = 2, |
511 | .cacheline_size = I915_FIFO_LINE_SIZE, |
519 | .cacheline_size = I915_FIFO_LINE_SIZE, |
512 | }; |
520 | }; |
513 | static const struct intel_watermark_params i915_wm_info = { |
521 | static const struct intel_watermark_params i915_wm_info = { |
514 | .fifo_size = I915_FIFO_SIZE, |
522 | .fifo_size = I915_FIFO_SIZE, |
515 | .max_wm = I915_MAX_WM, |
523 | .max_wm = I915_MAX_WM, |
516 | .default_wm = 1, |
524 | .default_wm = 1, |
517 | .guard_size = 2, |
525 | .guard_size = 2, |
518 | .cacheline_size = I915_FIFO_LINE_SIZE, |
526 | .cacheline_size = I915_FIFO_LINE_SIZE, |
519 | }; |
527 | }; |
520 | static const struct intel_watermark_params i830_a_wm_info = { |
528 | static const struct intel_watermark_params i830_a_wm_info = { |
521 | .fifo_size = I855GM_FIFO_SIZE, |
529 | .fifo_size = I855GM_FIFO_SIZE, |
522 | .max_wm = I915_MAX_WM, |
530 | .max_wm = I915_MAX_WM, |
523 | .default_wm = 1, |
531 | .default_wm = 1, |
524 | .guard_size = 2, |
532 | .guard_size = 2, |
525 | .cacheline_size = I830_FIFO_LINE_SIZE, |
533 | .cacheline_size = I830_FIFO_LINE_SIZE, |
526 | }; |
534 | }; |
527 | static const struct intel_watermark_params i830_bc_wm_info = { |
535 | static const struct intel_watermark_params i830_bc_wm_info = { |
528 | .fifo_size = I855GM_FIFO_SIZE, |
536 | .fifo_size = I855GM_FIFO_SIZE, |
529 | .max_wm = I915_MAX_WM/2, |
537 | .max_wm = I915_MAX_WM/2, |
530 | .default_wm = 1, |
538 | .default_wm = 1, |
531 | .guard_size = 2, |
539 | .guard_size = 2, |
532 | .cacheline_size = I830_FIFO_LINE_SIZE, |
540 | .cacheline_size = I830_FIFO_LINE_SIZE, |
533 | }; |
541 | }; |
534 | static const struct intel_watermark_params i845_wm_info = { |
542 | static const struct intel_watermark_params i845_wm_info = { |
535 | .fifo_size = I830_FIFO_SIZE, |
543 | .fifo_size = I830_FIFO_SIZE, |
536 | .max_wm = I915_MAX_WM, |
544 | .max_wm = I915_MAX_WM, |
537 | .default_wm = 1, |
545 | .default_wm = 1, |
538 | .guard_size = 2, |
546 | .guard_size = 2, |
539 | .cacheline_size = I830_FIFO_LINE_SIZE, |
547 | .cacheline_size = I830_FIFO_LINE_SIZE, |
540 | }; |
548 | }; |
541 | 549 | ||
542 | /** |
550 | /** |
543 | * intel_calculate_wm - calculate watermark level |
551 | * intel_calculate_wm - calculate watermark level |
544 | * @clock_in_khz: pixel clock |
552 | * @clock_in_khz: pixel clock |
545 | * @wm: chip FIFO params |
553 | * @wm: chip FIFO params |
546 | * @pixel_size: display pixel size |
554 | * @pixel_size: display pixel size |
547 | * @latency_ns: memory latency for the platform |
555 | * @latency_ns: memory latency for the platform |
548 | * |
556 | * |
549 | * Calculate the watermark level (the level at which the display plane will |
557 | * Calculate the watermark level (the level at which the display plane will |
550 | * start fetching from memory again). Each chip has a different display |
558 | * start fetching from memory again). Each chip has a different display |
551 | * FIFO size and allocation, so the caller needs to figure that out and pass |
559 | * FIFO size and allocation, so the caller needs to figure that out and pass |
552 | * in the correct intel_watermark_params structure. |
560 | * in the correct intel_watermark_params structure. |
553 | * |
561 | * |
554 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
562 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
555 | * on the pixel size. When it reaches the watermark level, it'll start |
563 | * on the pixel size. When it reaches the watermark level, it'll start |
556 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
564 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
557 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
565 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
558 | * will occur, and a display engine hang could result. |
566 | * will occur, and a display engine hang could result. |
559 | */ |
567 | */ |
560 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
568 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
561 | const struct intel_watermark_params *wm, |
569 | const struct intel_watermark_params *wm, |
562 | int fifo_size, |
570 | int fifo_size, |
563 | int pixel_size, |
571 | int pixel_size, |
564 | unsigned long latency_ns) |
572 | unsigned long latency_ns) |
565 | { |
573 | { |
566 | long entries_required, wm_size; |
574 | long entries_required, wm_size; |
567 | 575 | ||
568 | /* |
576 | /* |
569 | * Note: we need to make sure we don't overflow for various clock & |
577 | * Note: we need to make sure we don't overflow for various clock & |
570 | * latency values. |
578 | * latency values. |
571 | * clocks go from a few thousand to several hundred thousand. |
579 | * clocks go from a few thousand to several hundred thousand. |
572 | * latency is usually a few thousand |
580 | * latency is usually a few thousand |
573 | */ |
581 | */ |
574 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
582 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
575 | 1000; |
583 | 1000; |
576 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
584 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
577 | 585 | ||
578 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
586 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
579 | 587 | ||
580 | wm_size = fifo_size - (entries_required + wm->guard_size); |
588 | wm_size = fifo_size - (entries_required + wm->guard_size); |
581 | 589 | ||
582 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
590 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
583 | 591 | ||
584 | /* Don't promote wm_size to unsigned... */ |
592 | /* Don't promote wm_size to unsigned... */ |
585 | if (wm_size > (long)wm->max_wm) |
593 | if (wm_size > (long)wm->max_wm) |
586 | wm_size = wm->max_wm; |
594 | wm_size = wm->max_wm; |
587 | if (wm_size <= 0) |
595 | if (wm_size <= 0) |
588 | wm_size = wm->default_wm; |
596 | wm_size = wm->default_wm; |
589 | 597 | ||
590 | /* |
598 | /* |
591 | * Bspec seems to indicate that the value shouldn't be lower than |
599 | * Bspec seems to indicate that the value shouldn't be lower than |
592 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. |
600 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. |
593 | * Lets go for 8 which is the burst size since certain platforms |
601 | * Lets go for 8 which is the burst size since certain platforms |
594 | * already use a hardcoded 8 (which is what the spec says should be |
602 | * already use a hardcoded 8 (which is what the spec says should be |
595 | * done). |
603 | * done). |
596 | */ |
604 | */ |
597 | if (wm_size <= 8) |
605 | if (wm_size <= 8) |
598 | wm_size = 8; |
606 | wm_size = 8; |
599 | 607 | ||
600 | return wm_size; |
608 | return wm_size; |
601 | } |
609 | } |
602 | 610 | ||
603 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
611 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
604 | { |
612 | { |
605 | struct drm_crtc *crtc, *enabled = NULL; |
613 | struct drm_crtc *crtc, *enabled = NULL; |
606 | 614 | ||
607 | for_each_crtc(dev, crtc) { |
615 | for_each_crtc(dev, crtc) { |
608 | if (intel_crtc_active(crtc)) { |
616 | if (intel_crtc_active(crtc)) { |
609 | if (enabled) |
617 | if (enabled) |
610 | return NULL; |
618 | return NULL; |
611 | enabled = crtc; |
619 | enabled = crtc; |
612 | } |
620 | } |
613 | } |
621 | } |
614 | 622 | ||
615 | return enabled; |
623 | return enabled; |
616 | } |
624 | } |
617 | 625 | ||
618 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
626 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
619 | { |
627 | { |
620 | struct drm_device *dev = unused_crtc->dev; |
628 | struct drm_device *dev = unused_crtc->dev; |
621 | struct drm_i915_private *dev_priv = dev->dev_private; |
629 | struct drm_i915_private *dev_priv = dev->dev_private; |
622 | struct drm_crtc *crtc; |
630 | struct drm_crtc *crtc; |
623 | const struct cxsr_latency *latency; |
631 | const struct cxsr_latency *latency; |
624 | u32 reg; |
632 | u32 reg; |
625 | unsigned long wm; |
633 | unsigned long wm; |
626 | 634 | ||
627 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
635 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
628 | dev_priv->fsb_freq, dev_priv->mem_freq); |
636 | dev_priv->fsb_freq, dev_priv->mem_freq); |
629 | if (!latency) { |
637 | if (!latency) { |
630 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
638 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
631 | intel_set_memory_cxsr(dev_priv, false); |
639 | intel_set_memory_cxsr(dev_priv, false); |
632 | return; |
640 | return; |
633 | } |
641 | } |
634 | 642 | ||
635 | crtc = single_enabled_crtc(dev); |
643 | crtc = single_enabled_crtc(dev); |
636 | if (crtc) { |
644 | if (crtc) { |
637 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
645 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
638 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
646 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
639 | int clock = adjusted_mode->crtc_clock; |
647 | int clock = adjusted_mode->crtc_clock; |
640 | 648 | ||
641 | /* Display SR */ |
649 | /* Display SR */ |
642 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
650 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
643 | pineview_display_wm.fifo_size, |
651 | pineview_display_wm.fifo_size, |
644 | pixel_size, latency->display_sr); |
652 | pixel_size, latency->display_sr); |
645 | reg = I915_READ(DSPFW1); |
653 | reg = I915_READ(DSPFW1); |
646 | reg &= ~DSPFW_SR_MASK; |
654 | reg &= ~DSPFW_SR_MASK; |
647 | reg |= FW_WM(wm, SR); |
655 | reg |= FW_WM(wm, SR); |
648 | I915_WRITE(DSPFW1, reg); |
656 | I915_WRITE(DSPFW1, reg); |
649 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
657 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
650 | 658 | ||
651 | /* cursor SR */ |
659 | /* cursor SR */ |
652 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
660 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
653 | pineview_display_wm.fifo_size, |
661 | pineview_display_wm.fifo_size, |
654 | pixel_size, latency->cursor_sr); |
662 | pixel_size, latency->cursor_sr); |
655 | reg = I915_READ(DSPFW3); |
663 | reg = I915_READ(DSPFW3); |
656 | reg &= ~DSPFW_CURSOR_SR_MASK; |
664 | reg &= ~DSPFW_CURSOR_SR_MASK; |
657 | reg |= FW_WM(wm, CURSOR_SR); |
665 | reg |= FW_WM(wm, CURSOR_SR); |
658 | I915_WRITE(DSPFW3, reg); |
666 | I915_WRITE(DSPFW3, reg); |
659 | 667 | ||
660 | /* Display HPLL off SR */ |
668 | /* Display HPLL off SR */ |
661 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
669 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
662 | pineview_display_hplloff_wm.fifo_size, |
670 | pineview_display_hplloff_wm.fifo_size, |
663 | pixel_size, latency->display_hpll_disable); |
671 | pixel_size, latency->display_hpll_disable); |
664 | reg = I915_READ(DSPFW3); |
672 | reg = I915_READ(DSPFW3); |
665 | reg &= ~DSPFW_HPLL_SR_MASK; |
673 | reg &= ~DSPFW_HPLL_SR_MASK; |
666 | reg |= FW_WM(wm, HPLL_SR); |
674 | reg |= FW_WM(wm, HPLL_SR); |
667 | I915_WRITE(DSPFW3, reg); |
675 | I915_WRITE(DSPFW3, reg); |
668 | 676 | ||
669 | /* cursor HPLL off SR */ |
677 | /* cursor HPLL off SR */ |
670 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
678 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
671 | pineview_display_hplloff_wm.fifo_size, |
679 | pineview_display_hplloff_wm.fifo_size, |
672 | pixel_size, latency->cursor_hpll_disable); |
680 | pixel_size, latency->cursor_hpll_disable); |
673 | reg = I915_READ(DSPFW3); |
681 | reg = I915_READ(DSPFW3); |
674 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
682 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
675 | reg |= FW_WM(wm, HPLL_CURSOR); |
683 | reg |= FW_WM(wm, HPLL_CURSOR); |
676 | I915_WRITE(DSPFW3, reg); |
684 | I915_WRITE(DSPFW3, reg); |
677 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
685 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
678 | 686 | ||
679 | intel_set_memory_cxsr(dev_priv, true); |
687 | intel_set_memory_cxsr(dev_priv, true); |
680 | } else { |
688 | } else { |
681 | intel_set_memory_cxsr(dev_priv, false); |
689 | intel_set_memory_cxsr(dev_priv, false); |
682 | } |
690 | } |
683 | } |
691 | } |
684 | 692 | ||
685 | static bool g4x_compute_wm0(struct drm_device *dev, |
693 | static bool g4x_compute_wm0(struct drm_device *dev, |
686 | int plane, |
694 | int plane, |
687 | const struct intel_watermark_params *display, |
695 | const struct intel_watermark_params *display, |
688 | int display_latency_ns, |
696 | int display_latency_ns, |
689 | const struct intel_watermark_params *cursor, |
697 | const struct intel_watermark_params *cursor, |
690 | int cursor_latency_ns, |
698 | int cursor_latency_ns, |
691 | int *plane_wm, |
699 | int *plane_wm, |
692 | int *cursor_wm) |
700 | int *cursor_wm) |
693 | { |
701 | { |
694 | struct drm_crtc *crtc; |
702 | struct drm_crtc *crtc; |
695 | const struct drm_display_mode *adjusted_mode; |
703 | const struct drm_display_mode *adjusted_mode; |
696 | int htotal, hdisplay, clock, pixel_size; |
704 | int htotal, hdisplay, clock, pixel_size; |
697 | int line_time_us, line_count; |
705 | int line_time_us, line_count; |
698 | int entries, tlb_miss; |
706 | int entries, tlb_miss; |
699 | 707 | ||
700 | crtc = intel_get_crtc_for_plane(dev, plane); |
708 | crtc = intel_get_crtc_for_plane(dev, plane); |
701 | if (!intel_crtc_active(crtc)) { |
709 | if (!intel_crtc_active(crtc)) { |
702 | *cursor_wm = cursor->guard_size; |
710 | *cursor_wm = cursor->guard_size; |
703 | *plane_wm = display->guard_size; |
711 | *plane_wm = display->guard_size; |
704 | return false; |
712 | return false; |
705 | } |
713 | } |
706 | 714 | ||
707 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
715 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
708 | clock = adjusted_mode->crtc_clock; |
716 | clock = adjusted_mode->crtc_clock; |
709 | htotal = adjusted_mode->crtc_htotal; |
717 | htotal = adjusted_mode->crtc_htotal; |
710 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
718 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
711 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
719 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
712 | 720 | ||
713 | /* Use the small buffer method to calculate plane watermark */ |
721 | /* Use the small buffer method to calculate plane watermark */ |
714 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
722 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
715 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
723 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
716 | if (tlb_miss > 0) |
724 | if (tlb_miss > 0) |
717 | entries += tlb_miss; |
725 | entries += tlb_miss; |
718 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
726 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
719 | *plane_wm = entries + display->guard_size; |
727 | *plane_wm = entries + display->guard_size; |
720 | if (*plane_wm > (int)display->max_wm) |
728 | if (*plane_wm > (int)display->max_wm) |
721 | *plane_wm = display->max_wm; |
729 | *plane_wm = display->max_wm; |
722 | 730 | ||
723 | /* Use the large buffer method to calculate cursor watermark */ |
731 | /* Use the large buffer method to calculate cursor watermark */ |
724 | line_time_us = max(htotal * 1000 / clock, 1); |
732 | line_time_us = max(htotal * 1000 / clock, 1); |
725 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
733 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
726 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
734 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
727 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
735 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
728 | if (tlb_miss > 0) |
736 | if (tlb_miss > 0) |
729 | entries += tlb_miss; |
737 | entries += tlb_miss; |
730 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
738 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
731 | *cursor_wm = entries + cursor->guard_size; |
739 | *cursor_wm = entries + cursor->guard_size; |
732 | if (*cursor_wm > (int)cursor->max_wm) |
740 | if (*cursor_wm > (int)cursor->max_wm) |
733 | *cursor_wm = (int)cursor->max_wm; |
741 | *cursor_wm = (int)cursor->max_wm; |
734 | 742 | ||
735 | return true; |
743 | return true; |
736 | } |
744 | } |
737 | 745 | ||
738 | /* |
746 | /* |
739 | * Check the wm result. |
747 | * Check the wm result. |
740 | * |
748 | * |
741 | * If any calculated watermark values is larger than the maximum value that |
749 | * If any calculated watermark values is larger than the maximum value that |
742 | * can be programmed into the associated watermark register, that watermark |
750 | * can be programmed into the associated watermark register, that watermark |
743 | * must be disabled. |
751 | * must be disabled. |
744 | */ |
752 | */ |
745 | static bool g4x_check_srwm(struct drm_device *dev, |
753 | static bool g4x_check_srwm(struct drm_device *dev, |
746 | int display_wm, int cursor_wm, |
754 | int display_wm, int cursor_wm, |
747 | const struct intel_watermark_params *display, |
755 | const struct intel_watermark_params *display, |
748 | const struct intel_watermark_params *cursor) |
756 | const struct intel_watermark_params *cursor) |
749 | { |
757 | { |
750 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
758 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
751 | display_wm, cursor_wm); |
759 | display_wm, cursor_wm); |
752 | 760 | ||
753 | if (display_wm > display->max_wm) { |
761 | if (display_wm > display->max_wm) { |
754 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
762 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
755 | display_wm, display->max_wm); |
763 | display_wm, display->max_wm); |
756 | return false; |
764 | return false; |
757 | } |
765 | } |
758 | 766 | ||
759 | if (cursor_wm > cursor->max_wm) { |
767 | if (cursor_wm > cursor->max_wm) { |
760 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
768 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
761 | cursor_wm, cursor->max_wm); |
769 | cursor_wm, cursor->max_wm); |
762 | return false; |
770 | return false; |
763 | } |
771 | } |
764 | 772 | ||
765 | if (!(display_wm || cursor_wm)) { |
773 | if (!(display_wm || cursor_wm)) { |
766 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
774 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
767 | return false; |
775 | return false; |
768 | } |
776 | } |
769 | 777 | ||
770 | return true; |
778 | return true; |
771 | } |
779 | } |
772 | 780 | ||
773 | static bool g4x_compute_srwm(struct drm_device *dev, |
781 | static bool g4x_compute_srwm(struct drm_device *dev, |
774 | int plane, |
782 | int plane, |
775 | int latency_ns, |
783 | int latency_ns, |
776 | const struct intel_watermark_params *display, |
784 | const struct intel_watermark_params *display, |
777 | const struct intel_watermark_params *cursor, |
785 | const struct intel_watermark_params *cursor, |
778 | int *display_wm, int *cursor_wm) |
786 | int *display_wm, int *cursor_wm) |
779 | { |
787 | { |
780 | struct drm_crtc *crtc; |
788 | struct drm_crtc *crtc; |
781 | const struct drm_display_mode *adjusted_mode; |
789 | const struct drm_display_mode *adjusted_mode; |
782 | int hdisplay, htotal, pixel_size, clock; |
790 | int hdisplay, htotal, pixel_size, clock; |
783 | unsigned long line_time_us; |
791 | unsigned long line_time_us; |
784 | int line_count, line_size; |
792 | int line_count, line_size; |
785 | int small, large; |
793 | int small, large; |
786 | int entries; |
794 | int entries; |
787 | 795 | ||
788 | if (!latency_ns) { |
796 | if (!latency_ns) { |
789 | *display_wm = *cursor_wm = 0; |
797 | *display_wm = *cursor_wm = 0; |
790 | return false; |
798 | return false; |
791 | } |
799 | } |
792 | 800 | ||
793 | crtc = intel_get_crtc_for_plane(dev, plane); |
801 | crtc = intel_get_crtc_for_plane(dev, plane); |
794 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
802 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
795 | clock = adjusted_mode->crtc_clock; |
803 | clock = adjusted_mode->crtc_clock; |
796 | htotal = adjusted_mode->crtc_htotal; |
804 | htotal = adjusted_mode->crtc_htotal; |
797 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
805 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
798 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
806 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
799 | 807 | ||
800 | line_time_us = max(htotal * 1000 / clock, 1); |
808 | line_time_us = max(htotal * 1000 / clock, 1); |
801 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
809 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
802 | line_size = hdisplay * pixel_size; |
810 | line_size = hdisplay * pixel_size; |
803 | 811 | ||
804 | /* Use the minimum of the small and large buffer method for primary */ |
812 | /* Use the minimum of the small and large buffer method for primary */ |
805 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
813 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
806 | large = line_count * line_size; |
814 | large = line_count * line_size; |
807 | 815 | ||
808 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
816 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
809 | *display_wm = entries + display->guard_size; |
817 | *display_wm = entries + display->guard_size; |
810 | 818 | ||
811 | /* calculate the self-refresh watermark for display cursor */ |
819 | /* calculate the self-refresh watermark for display cursor */ |
812 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
820 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
813 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
821 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
814 | *cursor_wm = entries + cursor->guard_size; |
822 | *cursor_wm = entries + cursor->guard_size; |
815 | 823 | ||
816 | return g4x_check_srwm(dev, |
824 | return g4x_check_srwm(dev, |
817 | *display_wm, *cursor_wm, |
825 | *display_wm, *cursor_wm, |
818 | display, cursor); |
826 | display, cursor); |
819 | } |
827 | } |
820 | 828 | ||
821 | #define FW_WM_VLV(value, plane) \ |
829 | #define FW_WM_VLV(value, plane) \ |
822 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) |
830 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) |
823 | 831 | ||
824 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
832 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
825 | const struct vlv_wm_values *wm) |
833 | const struct vlv_wm_values *wm) |
826 | { |
834 | { |
827 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
835 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
828 | enum pipe pipe = crtc->pipe; |
836 | enum pipe pipe = crtc->pipe; |
829 | 837 | ||
830 | I915_WRITE(VLV_DDL(pipe), |
838 | I915_WRITE(VLV_DDL(pipe), |
831 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | |
839 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | |
832 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | |
840 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | |
833 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | |
841 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | |
834 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); |
842 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); |
835 | 843 | ||
836 | I915_WRITE(DSPFW1, |
844 | I915_WRITE(DSPFW1, |
837 | FW_WM(wm->sr.plane, SR) | |
845 | FW_WM(wm->sr.plane, SR) | |
838 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | |
846 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | |
839 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | |
847 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | |
840 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); |
848 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); |
841 | I915_WRITE(DSPFW2, |
849 | I915_WRITE(DSPFW2, |
842 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
850 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
843 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | |
851 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | |
844 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); |
852 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); |
845 | I915_WRITE(DSPFW3, |
853 | I915_WRITE(DSPFW3, |
846 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
854 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
847 | 855 | ||
848 | if (IS_CHERRYVIEW(dev_priv)) { |
856 | if (IS_CHERRYVIEW(dev_priv)) { |
849 | I915_WRITE(DSPFW7_CHV, |
857 | I915_WRITE(DSPFW7_CHV, |
850 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
858 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
851 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
859 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
852 | I915_WRITE(DSPFW8_CHV, |
860 | I915_WRITE(DSPFW8_CHV, |
853 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
861 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
854 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); |
862 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); |
855 | I915_WRITE(DSPFW9_CHV, |
863 | I915_WRITE(DSPFW9_CHV, |
856 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
864 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
857 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); |
865 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); |
858 | I915_WRITE(DSPHOWM, |
866 | I915_WRITE(DSPHOWM, |
859 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
867 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
860 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | |
868 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | |
861 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | |
869 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | |
862 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | |
870 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | |
863 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
871 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
864 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
872 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
865 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
873 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
866 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
874 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
867 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
875 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
868 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
876 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
869 | } else { |
877 | } else { |
870 | I915_WRITE(DSPFW7, |
878 | I915_WRITE(DSPFW7, |
871 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
879 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
872 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
880 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
873 | I915_WRITE(DSPHOWM, |
881 | I915_WRITE(DSPHOWM, |
874 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
882 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
875 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
883 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
876 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
884 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
877 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
885 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
878 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
886 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
879 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
887 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
880 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
888 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
881 | } |
889 | } |
882 | 890 | ||
883 | /* zero (unused) WM1 watermarks */ |
891 | /* zero (unused) WM1 watermarks */ |
884 | I915_WRITE(DSPFW4, 0); |
892 | I915_WRITE(DSPFW4, 0); |
885 | I915_WRITE(DSPFW5, 0); |
893 | I915_WRITE(DSPFW5, 0); |
886 | I915_WRITE(DSPFW6, 0); |
894 | I915_WRITE(DSPFW6, 0); |
887 | I915_WRITE(DSPHOWM1, 0); |
895 | I915_WRITE(DSPHOWM1, 0); |
888 | 896 | ||
889 | POSTING_READ(DSPFW1); |
897 | POSTING_READ(DSPFW1); |
890 | } |
898 | } |
891 | 899 | ||
892 | #undef FW_WM_VLV |
900 | #undef FW_WM_VLV |
893 | 901 | ||
894 | enum vlv_wm_level { |
902 | enum vlv_wm_level { |
895 | VLV_WM_LEVEL_PM2, |
903 | VLV_WM_LEVEL_PM2, |
896 | VLV_WM_LEVEL_PM5, |
904 | VLV_WM_LEVEL_PM5, |
897 | VLV_WM_LEVEL_DDR_DVFS, |
905 | VLV_WM_LEVEL_DDR_DVFS, |
898 | }; |
906 | }; |
899 | 907 | ||
900 | /* latency must be in 0.1us units. */ |
908 | /* latency must be in 0.1us units. */ |
901 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, |
909 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, |
902 | unsigned int pipe_htotal, |
910 | unsigned int pipe_htotal, |
903 | unsigned int horiz_pixels, |
911 | unsigned int horiz_pixels, |
904 | unsigned int bytes_per_pixel, |
912 | unsigned int bytes_per_pixel, |
905 | unsigned int latency) |
913 | unsigned int latency) |
906 | { |
914 | { |
907 | unsigned int ret; |
915 | unsigned int ret; |
908 | 916 | ||
909 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
917 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
910 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
918 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
911 | ret = DIV_ROUND_UP(ret, 64); |
919 | ret = DIV_ROUND_UP(ret, 64); |
912 | 920 | ||
913 | return ret; |
921 | return ret; |
914 | } |
922 | } |
915 | 923 | ||
916 | static void vlv_setup_wm_latency(struct drm_device *dev) |
924 | static void vlv_setup_wm_latency(struct drm_device *dev) |
917 | { |
925 | { |
918 | struct drm_i915_private *dev_priv = dev->dev_private; |
926 | struct drm_i915_private *dev_priv = dev->dev_private; |
919 | 927 | ||
920 | /* all latencies in usec */ |
928 | /* all latencies in usec */ |
921 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; |
929 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; |
922 | 930 | ||
923 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
931 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
924 | 932 | ||
925 | if (IS_CHERRYVIEW(dev_priv)) { |
933 | if (IS_CHERRYVIEW(dev_priv)) { |
926 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; |
934 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; |
927 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; |
935 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; |
928 | 936 | ||
929 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; |
937 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; |
930 | } |
938 | } |
931 | } |
939 | } |
932 | 940 | ||
933 | static uint16_t vlv_compute_wm_level(struct intel_plane *plane, |
941 | static uint16_t vlv_compute_wm_level(struct intel_plane *plane, |
934 | struct intel_crtc *crtc, |
942 | struct intel_crtc *crtc, |
935 | const struct intel_plane_state *state, |
943 | const struct intel_plane_state *state, |
936 | int level) |
944 | int level) |
937 | { |
945 | { |
938 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
946 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
939 | int clock, htotal, pixel_size, width, wm; |
947 | int clock, htotal, pixel_size, width, wm; |
940 | 948 | ||
941 | if (dev_priv->wm.pri_latency[level] == 0) |
949 | if (dev_priv->wm.pri_latency[level] == 0) |
942 | return USHRT_MAX; |
950 | return USHRT_MAX; |
943 | 951 | ||
944 | if (!state->visible) |
952 | if (!state->visible) |
945 | return 0; |
953 | return 0; |
946 | 954 | ||
947 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
955 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
948 | clock = crtc->config->base.adjusted_mode.crtc_clock; |
956 | clock = crtc->config->base.adjusted_mode.crtc_clock; |
949 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; |
957 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; |
950 | width = crtc->config->pipe_src_w; |
958 | width = crtc->config->pipe_src_w; |
951 | if (WARN_ON(htotal == 0)) |
959 | if (WARN_ON(htotal == 0)) |
952 | htotal = 1; |
960 | htotal = 1; |
953 | 961 | ||
954 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
962 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
955 | /* |
963 | /* |
956 | * FIXME the formula gives values that are |
964 | * FIXME the formula gives values that are |
957 | * too big for the cursor FIFO, and hence we |
965 | * too big for the cursor FIFO, and hence we |
958 | * would never be able to use cursors. For |
966 | * would never be able to use cursors. For |
959 | * now just hardcode the watermark. |
967 | * now just hardcode the watermark. |
960 | */ |
968 | */ |
961 | wm = 63; |
969 | wm = 63; |
962 | } else { |
970 | } else { |
963 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, |
971 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, |
964 | dev_priv->wm.pri_latency[level] * 10); |
972 | dev_priv->wm.pri_latency[level] * 10); |
965 | } |
973 | } |
966 | 974 | ||
967 | return min_t(int, wm, USHRT_MAX); |
975 | return min_t(int, wm, USHRT_MAX); |
968 | } |
976 | } |
969 | 977 | ||
970 | static void vlv_compute_fifo(struct intel_crtc *crtc) |
978 | static void vlv_compute_fifo(struct intel_crtc *crtc) |
971 | { |
979 | { |
972 | struct drm_device *dev = crtc->base.dev; |
980 | struct drm_device *dev = crtc->base.dev; |
973 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
981 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
974 | struct intel_plane *plane; |
982 | struct intel_plane *plane; |
975 | unsigned int total_rate = 0; |
983 | unsigned int total_rate = 0; |
976 | const int fifo_size = 512 - 1; |
984 | const int fifo_size = 512 - 1; |
977 | int fifo_extra, fifo_left = fifo_size; |
985 | int fifo_extra, fifo_left = fifo_size; |
978 | 986 | ||
979 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
987 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
980 | struct intel_plane_state *state = |
988 | struct intel_plane_state *state = |
981 | to_intel_plane_state(plane->base.state); |
989 | to_intel_plane_state(plane->base.state); |
982 | 990 | ||
983 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
991 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
984 | continue; |
992 | continue; |
985 | 993 | ||
986 | if (state->visible) { |
994 | if (state->visible) { |
987 | wm_state->num_active_planes++; |
995 | wm_state->num_active_planes++; |
988 | total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
996 | total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
989 | } |
997 | } |
990 | } |
998 | } |
991 | 999 | ||
992 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1000 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
993 | struct intel_plane_state *state = |
1001 | struct intel_plane_state *state = |
994 | to_intel_plane_state(plane->base.state); |
1002 | to_intel_plane_state(plane->base.state); |
995 | unsigned int rate; |
1003 | unsigned int rate; |
996 | 1004 | ||
997 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
1005 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
998 | plane->wm.fifo_size = 63; |
1006 | plane->wm.fifo_size = 63; |
999 | continue; |
1007 | continue; |
1000 | } |
1008 | } |
1001 | 1009 | ||
1002 | if (!state->visible) { |
1010 | if (!state->visible) { |
1003 | plane->wm.fifo_size = 0; |
1011 | plane->wm.fifo_size = 0; |
1004 | continue; |
1012 | continue; |
1005 | } |
1013 | } |
1006 | 1014 | ||
1007 | rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
1015 | rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
1008 | plane->wm.fifo_size = fifo_size * rate / total_rate; |
1016 | plane->wm.fifo_size = fifo_size * rate / total_rate; |
1009 | fifo_left -= plane->wm.fifo_size; |
1017 | fifo_left -= plane->wm.fifo_size; |
1010 | } |
1018 | } |
1011 | 1019 | ||
1012 | fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); |
1020 | fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); |
1013 | 1021 | ||
1014 | /* spread the remainder evenly */ |
1022 | /* spread the remainder evenly */ |
1015 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1023 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1016 | int plane_extra; |
1024 | int plane_extra; |
1017 | 1025 | ||
1018 | if (fifo_left == 0) |
1026 | if (fifo_left == 0) |
1019 | break; |
1027 | break; |
1020 | 1028 | ||
1021 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
1029 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
1022 | continue; |
1030 | continue; |
1023 | 1031 | ||
1024 | /* give it all to the first plane if none are active */ |
1032 | /* give it all to the first plane if none are active */ |
1025 | if (plane->wm.fifo_size == 0 && |
1033 | if (plane->wm.fifo_size == 0 && |
1026 | wm_state->num_active_planes) |
1034 | wm_state->num_active_planes) |
1027 | continue; |
1035 | continue; |
1028 | 1036 | ||
1029 | plane_extra = min(fifo_extra, fifo_left); |
1037 | plane_extra = min(fifo_extra, fifo_left); |
1030 | plane->wm.fifo_size += plane_extra; |
1038 | plane->wm.fifo_size += plane_extra; |
1031 | fifo_left -= plane_extra; |
1039 | fifo_left -= plane_extra; |
1032 | } |
1040 | } |
1033 | 1041 | ||
1034 | WARN_ON(fifo_left != 0); |
1042 | WARN_ON(fifo_left != 0); |
1035 | } |
1043 | } |
1036 | 1044 | ||
1037 | static void vlv_invert_wms(struct intel_crtc *crtc) |
1045 | static void vlv_invert_wms(struct intel_crtc *crtc) |
1038 | { |
1046 | { |
1039 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1047 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1040 | int level; |
1048 | int level; |
1041 | 1049 | ||
1042 | for (level = 0; level < wm_state->num_levels; level++) { |
1050 | for (level = 0; level < wm_state->num_levels; level++) { |
1043 | struct drm_device *dev = crtc->base.dev; |
1051 | struct drm_device *dev = crtc->base.dev; |
1044 | const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
1052 | const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
1045 | struct intel_plane *plane; |
1053 | struct intel_plane *plane; |
1046 | 1054 | ||
1047 | wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; |
1055 | wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; |
1048 | wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; |
1056 | wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; |
1049 | 1057 | ||
1050 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1058 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1051 | switch (plane->base.type) { |
1059 | switch (plane->base.type) { |
1052 | int sprite; |
1060 | int sprite; |
1053 | case DRM_PLANE_TYPE_CURSOR: |
1061 | case DRM_PLANE_TYPE_CURSOR: |
1054 | wm_state->wm[level].cursor = plane->wm.fifo_size - |
1062 | wm_state->wm[level].cursor = plane->wm.fifo_size - |
1055 | wm_state->wm[level].cursor; |
1063 | wm_state->wm[level].cursor; |
1056 | break; |
1064 | break; |
1057 | case DRM_PLANE_TYPE_PRIMARY: |
1065 | case DRM_PLANE_TYPE_PRIMARY: |
1058 | wm_state->wm[level].primary = plane->wm.fifo_size - |
1066 | wm_state->wm[level].primary = plane->wm.fifo_size - |
1059 | wm_state->wm[level].primary; |
1067 | wm_state->wm[level].primary; |
1060 | break; |
1068 | break; |
1061 | case DRM_PLANE_TYPE_OVERLAY: |
1069 | case DRM_PLANE_TYPE_OVERLAY: |
1062 | sprite = plane->plane; |
1070 | sprite = plane->plane; |
1063 | wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - |
1071 | wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - |
1064 | wm_state->wm[level].sprite[sprite]; |
1072 | wm_state->wm[level].sprite[sprite]; |
1065 | break; |
1073 | break; |
1066 | } |
1074 | } |
1067 | } |
1075 | } |
1068 | } |
1076 | } |
1069 | } |
1077 | } |
1070 | 1078 | ||
1071 | static void vlv_compute_wm(struct intel_crtc *crtc) |
1079 | static void vlv_compute_wm(struct intel_crtc *crtc) |
1072 | { |
1080 | { |
1073 | struct drm_device *dev = crtc->base.dev; |
1081 | struct drm_device *dev = crtc->base.dev; |
1074 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1082 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1075 | struct intel_plane *plane; |
1083 | struct intel_plane *plane; |
1076 | int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
1084 | int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
1077 | int level; |
1085 | int level; |
1078 | 1086 | ||
1079 | memset(wm_state, 0, sizeof(*wm_state)); |
1087 | memset(wm_state, 0, sizeof(*wm_state)); |
1080 | 1088 | ||
1081 | wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; |
1089 | wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; |
1082 | wm_state->num_levels = to_i915(dev)->wm.max_level + 1; |
1090 | wm_state->num_levels = to_i915(dev)->wm.max_level + 1; |
1083 | 1091 | ||
1084 | wm_state->num_active_planes = 0; |
1092 | wm_state->num_active_planes = 0; |
1085 | 1093 | ||
1086 | vlv_compute_fifo(crtc); |
1094 | vlv_compute_fifo(crtc); |
1087 | 1095 | ||
1088 | if (wm_state->num_active_planes != 1) |
1096 | if (wm_state->num_active_planes != 1) |
1089 | wm_state->cxsr = false; |
1097 | wm_state->cxsr = false; |
1090 | 1098 | ||
1091 | if (wm_state->cxsr) { |
1099 | if (wm_state->cxsr) { |
1092 | for (level = 0; level < wm_state->num_levels; level++) { |
1100 | for (level = 0; level < wm_state->num_levels; level++) { |
1093 | wm_state->sr[level].plane = sr_fifo_size; |
1101 | wm_state->sr[level].plane = sr_fifo_size; |
1094 | wm_state->sr[level].cursor = 63; |
1102 | wm_state->sr[level].cursor = 63; |
1095 | } |
1103 | } |
1096 | } |
1104 | } |
1097 | 1105 | ||
1098 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1106 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1099 | struct intel_plane_state *state = |
1107 | struct intel_plane_state *state = |
1100 | to_intel_plane_state(plane->base.state); |
1108 | to_intel_plane_state(plane->base.state); |
1101 | 1109 | ||
1102 | if (!state->visible) |
1110 | if (!state->visible) |
1103 | continue; |
1111 | continue; |
1104 | 1112 | ||
1105 | /* normal watermarks */ |
1113 | /* normal watermarks */ |
1106 | for (level = 0; level < wm_state->num_levels; level++) { |
1114 | for (level = 0; level < wm_state->num_levels; level++) { |
1107 | int wm = vlv_compute_wm_level(plane, crtc, state, level); |
1115 | int wm = vlv_compute_wm_level(plane, crtc, state, level); |
1108 | int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; |
1116 | int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; |
1109 | 1117 | ||
1110 | /* hack */ |
1118 | /* hack */ |
1111 | if (WARN_ON(level == 0 && wm > max_wm)) |
1119 | if (WARN_ON(level == 0 && wm > max_wm)) |
1112 | wm = max_wm; |
1120 | wm = max_wm; |
1113 | 1121 | ||
1114 | if (wm > plane->wm.fifo_size) |
1122 | if (wm > plane->wm.fifo_size) |
1115 | break; |
1123 | break; |
1116 | 1124 | ||
1117 | switch (plane->base.type) { |
1125 | switch (plane->base.type) { |
1118 | int sprite; |
1126 | int sprite; |
1119 | case DRM_PLANE_TYPE_CURSOR: |
1127 | case DRM_PLANE_TYPE_CURSOR: |
1120 | wm_state->wm[level].cursor = wm; |
1128 | wm_state->wm[level].cursor = wm; |
1121 | break; |
1129 | break; |
1122 | case DRM_PLANE_TYPE_PRIMARY: |
1130 | case DRM_PLANE_TYPE_PRIMARY: |
1123 | wm_state->wm[level].primary = wm; |
1131 | wm_state->wm[level].primary = wm; |
1124 | break; |
1132 | break; |
1125 | case DRM_PLANE_TYPE_OVERLAY: |
1133 | case DRM_PLANE_TYPE_OVERLAY: |
1126 | sprite = plane->plane; |
1134 | sprite = plane->plane; |
1127 | wm_state->wm[level].sprite[sprite] = wm; |
1135 | wm_state->wm[level].sprite[sprite] = wm; |
1128 | break; |
1136 | break; |
1129 | } |
1137 | } |
1130 | } |
1138 | } |
1131 | 1139 | ||
1132 | wm_state->num_levels = level; |
1140 | wm_state->num_levels = level; |
1133 | 1141 | ||
1134 | if (!wm_state->cxsr) |
1142 | if (!wm_state->cxsr) |
1135 | continue; |
1143 | continue; |
1136 | 1144 | ||
1137 | /* maxfifo watermarks */ |
1145 | /* maxfifo watermarks */ |
1138 | switch (plane->base.type) { |
1146 | switch (plane->base.type) { |
1139 | int sprite, level; |
1147 | int sprite, level; |
1140 | case DRM_PLANE_TYPE_CURSOR: |
1148 | case DRM_PLANE_TYPE_CURSOR: |
1141 | for (level = 0; level < wm_state->num_levels; level++) |
1149 | for (level = 0; level < wm_state->num_levels; level++) |
1142 | wm_state->sr[level].cursor = |
1150 | wm_state->sr[level].cursor = |
1143 | wm_state->wm[level].cursor; |
1151 | wm_state->wm[level].cursor; |
1144 | break; |
1152 | break; |
1145 | case DRM_PLANE_TYPE_PRIMARY: |
1153 | case DRM_PLANE_TYPE_PRIMARY: |
1146 | for (level = 0; level < wm_state->num_levels; level++) |
1154 | for (level = 0; level < wm_state->num_levels; level++) |
1147 | wm_state->sr[level].plane = |
1155 | wm_state->sr[level].plane = |
1148 | min(wm_state->sr[level].plane, |
1156 | min(wm_state->sr[level].plane, |
1149 | wm_state->wm[level].primary); |
1157 | wm_state->wm[level].primary); |
1150 | break; |
1158 | break; |
1151 | case DRM_PLANE_TYPE_OVERLAY: |
1159 | case DRM_PLANE_TYPE_OVERLAY: |
1152 | sprite = plane->plane; |
1160 | sprite = plane->plane; |
1153 | for (level = 0; level < wm_state->num_levels; level++) |
1161 | for (level = 0; level < wm_state->num_levels; level++) |
1154 | wm_state->sr[level].plane = |
1162 | wm_state->sr[level].plane = |
1155 | min(wm_state->sr[level].plane, |
1163 | min(wm_state->sr[level].plane, |
1156 | wm_state->wm[level].sprite[sprite]); |
1164 | wm_state->wm[level].sprite[sprite]); |
1157 | break; |
1165 | break; |
1158 | } |
1166 | } |
1159 | } |
1167 | } |
1160 | 1168 | ||
1161 | /* clear any (partially) filled invalid levels */ |
1169 | /* clear any (partially) filled invalid levels */ |
1162 | for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { |
1170 | for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { |
1163 | memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); |
1171 | memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); |
1164 | memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); |
1172 | memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); |
1165 | } |
1173 | } |
1166 | 1174 | ||
1167 | vlv_invert_wms(crtc); |
1175 | vlv_invert_wms(crtc); |
1168 | } |
1176 | } |
1169 | 1177 | ||
1170 | #define VLV_FIFO(plane, value) \ |
1178 | #define VLV_FIFO(plane, value) \ |
1171 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) |
1179 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) |
1172 | 1180 | ||
1173 | static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) |
1181 | static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) |
1174 | { |
1182 | { |
1175 | struct drm_device *dev = crtc->base.dev; |
1183 | struct drm_device *dev = crtc->base.dev; |
1176 | struct drm_i915_private *dev_priv = to_i915(dev); |
1184 | struct drm_i915_private *dev_priv = to_i915(dev); |
1177 | struct intel_plane *plane; |
1185 | struct intel_plane *plane; |
1178 | int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; |
1186 | int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; |
1179 | 1187 | ||
1180 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1188 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
1181 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
1189 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
1182 | WARN_ON(plane->wm.fifo_size != 63); |
1190 | WARN_ON(plane->wm.fifo_size != 63); |
1183 | continue; |
1191 | continue; |
1184 | } |
1192 | } |
1185 | 1193 | ||
1186 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
1194 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
1187 | sprite0_start = plane->wm.fifo_size; |
1195 | sprite0_start = plane->wm.fifo_size; |
1188 | else if (plane->plane == 0) |
1196 | else if (plane->plane == 0) |
1189 | sprite1_start = sprite0_start + plane->wm.fifo_size; |
1197 | sprite1_start = sprite0_start + plane->wm.fifo_size; |
1190 | else |
1198 | else |
1191 | fifo_size = sprite1_start + plane->wm.fifo_size; |
1199 | fifo_size = sprite1_start + plane->wm.fifo_size; |
1192 | } |
1200 | } |
1193 | 1201 | ||
1194 | WARN_ON(fifo_size != 512 - 1); |
1202 | WARN_ON(fifo_size != 512 - 1); |
1195 | 1203 | ||
1196 | DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", |
1204 | DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", |
1197 | pipe_name(crtc->pipe), sprite0_start, |
1205 | pipe_name(crtc->pipe), sprite0_start, |
1198 | sprite1_start, fifo_size); |
1206 | sprite1_start, fifo_size); |
1199 | 1207 | ||
1200 | switch (crtc->pipe) { |
1208 | switch (crtc->pipe) { |
1201 | uint32_t dsparb, dsparb2, dsparb3; |
1209 | uint32_t dsparb, dsparb2, dsparb3; |
1202 | case PIPE_A: |
1210 | case PIPE_A: |
1203 | dsparb = I915_READ(DSPARB); |
1211 | dsparb = I915_READ(DSPARB); |
1204 | dsparb2 = I915_READ(DSPARB2); |
1212 | dsparb2 = I915_READ(DSPARB2); |
1205 | 1213 | ||
1206 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | |
1214 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | |
1207 | VLV_FIFO(SPRITEB, 0xff)); |
1215 | VLV_FIFO(SPRITEB, 0xff)); |
1208 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | |
1216 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | |
1209 | VLV_FIFO(SPRITEB, sprite1_start)); |
1217 | VLV_FIFO(SPRITEB, sprite1_start)); |
1210 | 1218 | ||
1211 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | |
1219 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | |
1212 | VLV_FIFO(SPRITEB_HI, 0x1)); |
1220 | VLV_FIFO(SPRITEB_HI, 0x1)); |
1213 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | |
1221 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | |
1214 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); |
1222 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); |
1215 | 1223 | ||
1216 | I915_WRITE(DSPARB, dsparb); |
1224 | I915_WRITE(DSPARB, dsparb); |
1217 | I915_WRITE(DSPARB2, dsparb2); |
1225 | I915_WRITE(DSPARB2, dsparb2); |
1218 | break; |
1226 | break; |
1219 | case PIPE_B: |
1227 | case PIPE_B: |
1220 | dsparb = I915_READ(DSPARB); |
1228 | dsparb = I915_READ(DSPARB); |
1221 | dsparb2 = I915_READ(DSPARB2); |
1229 | dsparb2 = I915_READ(DSPARB2); |
1222 | 1230 | ||
1223 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | |
1231 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | |
1224 | VLV_FIFO(SPRITED, 0xff)); |
1232 | VLV_FIFO(SPRITED, 0xff)); |
1225 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | |
1233 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | |
1226 | VLV_FIFO(SPRITED, sprite1_start)); |
1234 | VLV_FIFO(SPRITED, sprite1_start)); |
1227 | 1235 | ||
1228 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | |
1236 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | |
1229 | VLV_FIFO(SPRITED_HI, 0xff)); |
1237 | VLV_FIFO(SPRITED_HI, 0xff)); |
1230 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | |
1238 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | |
1231 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); |
1239 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); |
1232 | 1240 | ||
1233 | I915_WRITE(DSPARB, dsparb); |
1241 | I915_WRITE(DSPARB, dsparb); |
1234 | I915_WRITE(DSPARB2, dsparb2); |
1242 | I915_WRITE(DSPARB2, dsparb2); |
1235 | break; |
1243 | break; |
1236 | case PIPE_C: |
1244 | case PIPE_C: |
1237 | dsparb3 = I915_READ(DSPARB3); |
1245 | dsparb3 = I915_READ(DSPARB3); |
1238 | dsparb2 = I915_READ(DSPARB2); |
1246 | dsparb2 = I915_READ(DSPARB2); |
1239 | 1247 | ||
1240 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | |
1248 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | |
1241 | VLV_FIFO(SPRITEF, 0xff)); |
1249 | VLV_FIFO(SPRITEF, 0xff)); |
1242 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | |
1250 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | |
1243 | VLV_FIFO(SPRITEF, sprite1_start)); |
1251 | VLV_FIFO(SPRITEF, sprite1_start)); |
1244 | 1252 | ||
1245 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | |
1253 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | |
1246 | VLV_FIFO(SPRITEF_HI, 0xff)); |
1254 | VLV_FIFO(SPRITEF_HI, 0xff)); |
1247 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | |
1255 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | |
1248 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); |
1256 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); |
1249 | 1257 | ||
1250 | I915_WRITE(DSPARB3, dsparb3); |
1258 | I915_WRITE(DSPARB3, dsparb3); |
1251 | I915_WRITE(DSPARB2, dsparb2); |
1259 | I915_WRITE(DSPARB2, dsparb2); |
1252 | break; |
1260 | break; |
1253 | default: |
1261 | default: |
1254 | break; |
1262 | break; |
1255 | } |
1263 | } |
1256 | } |
1264 | } |
1257 | 1265 | ||
1258 | #undef VLV_FIFO |
1266 | #undef VLV_FIFO |
1259 | 1267 | ||
1260 | static void vlv_merge_wm(struct drm_device *dev, |
1268 | static void vlv_merge_wm(struct drm_device *dev, |
1261 | struct vlv_wm_values *wm) |
1269 | struct vlv_wm_values *wm) |
1262 | { |
1270 | { |
1263 | struct intel_crtc *crtc; |
1271 | struct intel_crtc *crtc; |
1264 | int num_active_crtcs = 0; |
1272 | int num_active_crtcs = 0; |
1265 | 1273 | ||
1266 | wm->level = to_i915(dev)->wm.max_level; |
1274 | wm->level = to_i915(dev)->wm.max_level; |
1267 | wm->cxsr = true; |
1275 | wm->cxsr = true; |
1268 | 1276 | ||
1269 | for_each_intel_crtc(dev, crtc) { |
1277 | for_each_intel_crtc(dev, crtc) { |
1270 | const struct vlv_wm_state *wm_state = &crtc->wm_state; |
1278 | const struct vlv_wm_state *wm_state = &crtc->wm_state; |
1271 | 1279 | ||
1272 | if (!crtc->active) |
1280 | if (!crtc->active) |
1273 | continue; |
1281 | continue; |
1274 | 1282 | ||
1275 | if (!wm_state->cxsr) |
1283 | if (!wm_state->cxsr) |
1276 | wm->cxsr = false; |
1284 | wm->cxsr = false; |
1277 | 1285 | ||
1278 | num_active_crtcs++; |
1286 | num_active_crtcs++; |
1279 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); |
1287 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); |
1280 | } |
1288 | } |
1281 | 1289 | ||
1282 | if (num_active_crtcs != 1) |
1290 | if (num_active_crtcs != 1) |
1283 | wm->cxsr = false; |
1291 | wm->cxsr = false; |
1284 | 1292 | ||
1285 | if (num_active_crtcs > 1) |
1293 | if (num_active_crtcs > 1) |
1286 | wm->level = VLV_WM_LEVEL_PM2; |
1294 | wm->level = VLV_WM_LEVEL_PM2; |
1287 | 1295 | ||
1288 | for_each_intel_crtc(dev, crtc) { |
1296 | for_each_intel_crtc(dev, crtc) { |
1289 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1297 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
1290 | enum pipe pipe = crtc->pipe; |
1298 | enum pipe pipe = crtc->pipe; |
1291 | 1299 | ||
1292 | if (!crtc->active) |
1300 | if (!crtc->active) |
1293 | continue; |
1301 | continue; |
1294 | 1302 | ||
1295 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
1303 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
1296 | if (wm->cxsr) |
1304 | if (wm->cxsr) |
1297 | wm->sr = wm_state->sr[wm->level]; |
1305 | wm->sr = wm_state->sr[wm->level]; |
1298 | 1306 | ||
1299 | wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; |
1307 | wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; |
1300 | wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; |
1308 | wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; |
1301 | wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; |
1309 | wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; |
1302 | wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; |
1310 | wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; |
1303 | } |
1311 | } |
1304 | } |
1312 | } |
1305 | 1313 | ||
1306 | static void vlv_update_wm(struct drm_crtc *crtc) |
1314 | static void vlv_update_wm(struct drm_crtc *crtc) |
1307 | { |
1315 | { |
1308 | struct drm_device *dev = crtc->dev; |
1316 | struct drm_device *dev = crtc->dev; |
1309 | struct drm_i915_private *dev_priv = dev->dev_private; |
1317 | struct drm_i915_private *dev_priv = dev->dev_private; |
1310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1311 | enum pipe pipe = intel_crtc->pipe; |
1319 | enum pipe pipe = intel_crtc->pipe; |
1312 | struct vlv_wm_values wm = {}; |
1320 | struct vlv_wm_values wm = {}; |
1313 | 1321 | ||
1314 | vlv_compute_wm(intel_crtc); |
1322 | vlv_compute_wm(intel_crtc); |
1315 | vlv_merge_wm(dev, &wm); |
1323 | vlv_merge_wm(dev, &wm); |
1316 | 1324 | ||
1317 | if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { |
1325 | if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { |
1318 | /* FIXME should be part of crtc atomic commit */ |
1326 | /* FIXME should be part of crtc atomic commit */ |
1319 | vlv_pipe_set_fifo_size(intel_crtc); |
1327 | vlv_pipe_set_fifo_size(intel_crtc); |
1320 | return; |
1328 | return; |
1321 | } |
1329 | } |
1322 | 1330 | ||
1323 | if (wm.level < VLV_WM_LEVEL_DDR_DVFS && |
1331 | if (wm.level < VLV_WM_LEVEL_DDR_DVFS && |
1324 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) |
1332 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) |
1325 | chv_set_memory_dvfs(dev_priv, false); |
1333 | chv_set_memory_dvfs(dev_priv, false); |
1326 | 1334 | ||
1327 | if (wm.level < VLV_WM_LEVEL_PM5 && |
1335 | if (wm.level < VLV_WM_LEVEL_PM5 && |
1328 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) |
1336 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) |
1329 | chv_set_memory_pm5(dev_priv, false); |
1337 | chv_set_memory_pm5(dev_priv, false); |
1330 | 1338 | ||
1331 | if (!wm.cxsr && dev_priv->wm.vlv.cxsr) |
1339 | if (!wm.cxsr && dev_priv->wm.vlv.cxsr) |
1332 | intel_set_memory_cxsr(dev_priv, false); |
1340 | intel_set_memory_cxsr(dev_priv, false); |
1333 | 1341 | ||
1334 | /* FIXME should be part of crtc atomic commit */ |
1342 | /* FIXME should be part of crtc atomic commit */ |
1335 | vlv_pipe_set_fifo_size(intel_crtc); |
1343 | vlv_pipe_set_fifo_size(intel_crtc); |
1336 | 1344 | ||
1337 | vlv_write_wm_values(intel_crtc, &wm); |
1345 | vlv_write_wm_values(intel_crtc, &wm); |
1338 | 1346 | ||
1339 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " |
1347 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " |
1340 | "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", |
1348 | "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", |
1341 | pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, |
1349 | pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, |
1342 | wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], |
1350 | wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], |
1343 | wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); |
1351 | wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); |
1344 | 1352 | ||
1345 | if (wm.cxsr && !dev_priv->wm.vlv.cxsr) |
1353 | if (wm.cxsr && !dev_priv->wm.vlv.cxsr) |
1346 | intel_set_memory_cxsr(dev_priv, true); |
1354 | intel_set_memory_cxsr(dev_priv, true); |
1347 | 1355 | ||
1348 | if (wm.level >= VLV_WM_LEVEL_PM5 && |
1356 | if (wm.level >= VLV_WM_LEVEL_PM5 && |
1349 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) |
1357 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) |
1350 | chv_set_memory_pm5(dev_priv, true); |
1358 | chv_set_memory_pm5(dev_priv, true); |
1351 | 1359 | ||
1352 | if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && |
1360 | if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && |
1353 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) |
1361 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) |
1354 | chv_set_memory_dvfs(dev_priv, true); |
1362 | chv_set_memory_dvfs(dev_priv, true); |
1355 | 1363 | ||
1356 | dev_priv->wm.vlv = wm; |
1364 | dev_priv->wm.vlv = wm; |
1357 | } |
1365 | } |
1358 | 1366 | ||
1359 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1367 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1360 | 1368 | ||
1361 | static void g4x_update_wm(struct drm_crtc *crtc) |
1369 | static void g4x_update_wm(struct drm_crtc *crtc) |
1362 | { |
1370 | { |
1363 | struct drm_device *dev = crtc->dev; |
1371 | struct drm_device *dev = crtc->dev; |
1364 | static const int sr_latency_ns = 12000; |
1372 | static const int sr_latency_ns = 12000; |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; |
1373 | struct drm_i915_private *dev_priv = dev->dev_private; |
1366 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1374 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1367 | int plane_sr, cursor_sr; |
1375 | int plane_sr, cursor_sr; |
1368 | unsigned int enabled = 0; |
1376 | unsigned int enabled = 0; |
1369 | bool cxsr_enabled; |
1377 | bool cxsr_enabled; |
1370 | 1378 | ||
1371 | if (g4x_compute_wm0(dev, PIPE_A, |
1379 | if (g4x_compute_wm0(dev, PIPE_A, |
1372 | &g4x_wm_info, pessimal_latency_ns, |
1380 | &g4x_wm_info, pessimal_latency_ns, |
1373 | &g4x_cursor_wm_info, pessimal_latency_ns, |
1381 | &g4x_cursor_wm_info, pessimal_latency_ns, |
1374 | &planea_wm, &cursora_wm)) |
1382 | &planea_wm, &cursora_wm)) |
1375 | enabled |= 1 << PIPE_A; |
1383 | enabled |= 1 << PIPE_A; |
1376 | 1384 | ||
1377 | if (g4x_compute_wm0(dev, PIPE_B, |
1385 | if (g4x_compute_wm0(dev, PIPE_B, |
1378 | &g4x_wm_info, pessimal_latency_ns, |
1386 | &g4x_wm_info, pessimal_latency_ns, |
1379 | &g4x_cursor_wm_info, pessimal_latency_ns, |
1387 | &g4x_cursor_wm_info, pessimal_latency_ns, |
1380 | &planeb_wm, &cursorb_wm)) |
1388 | &planeb_wm, &cursorb_wm)) |
1381 | enabled |= 1 << PIPE_B; |
1389 | enabled |= 1 << PIPE_B; |
1382 | 1390 | ||
1383 | if (single_plane_enabled(enabled) && |
1391 | if (single_plane_enabled(enabled) && |
1384 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1392 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1385 | sr_latency_ns, |
1393 | sr_latency_ns, |
1386 | &g4x_wm_info, |
1394 | &g4x_wm_info, |
1387 | &g4x_cursor_wm_info, |
1395 | &g4x_cursor_wm_info, |
1388 | &plane_sr, &cursor_sr)) { |
1396 | &plane_sr, &cursor_sr)) { |
1389 | cxsr_enabled = true; |
1397 | cxsr_enabled = true; |
1390 | } else { |
1398 | } else { |
1391 | cxsr_enabled = false; |
1399 | cxsr_enabled = false; |
1392 | intel_set_memory_cxsr(dev_priv, false); |
1400 | intel_set_memory_cxsr(dev_priv, false); |
1393 | plane_sr = cursor_sr = 0; |
1401 | plane_sr = cursor_sr = 0; |
1394 | } |
1402 | } |
1395 | 1403 | ||
1396 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1404 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1397 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1405 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1398 | planea_wm, cursora_wm, |
1406 | planea_wm, cursora_wm, |
1399 | planeb_wm, cursorb_wm, |
1407 | planeb_wm, cursorb_wm, |
1400 | plane_sr, cursor_sr); |
1408 | plane_sr, cursor_sr); |
1401 | 1409 | ||
1402 | I915_WRITE(DSPFW1, |
1410 | I915_WRITE(DSPFW1, |
1403 | FW_WM(plane_sr, SR) | |
1411 | FW_WM(plane_sr, SR) | |
1404 | FW_WM(cursorb_wm, CURSORB) | |
1412 | FW_WM(cursorb_wm, CURSORB) | |
1405 | FW_WM(planeb_wm, PLANEB) | |
1413 | FW_WM(planeb_wm, PLANEB) | |
1406 | FW_WM(planea_wm, PLANEA)); |
1414 | FW_WM(planea_wm, PLANEA)); |
1407 | I915_WRITE(DSPFW2, |
1415 | I915_WRITE(DSPFW2, |
1408 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1416 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1409 | FW_WM(cursora_wm, CURSORA)); |
1417 | FW_WM(cursora_wm, CURSORA)); |
1410 | /* HPLL off in SR has some issues on G4x... disable it */ |
1418 | /* HPLL off in SR has some issues on G4x... disable it */ |
1411 | I915_WRITE(DSPFW3, |
1419 | I915_WRITE(DSPFW3, |
1412 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
1420 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
1413 | FW_WM(cursor_sr, CURSOR_SR)); |
1421 | FW_WM(cursor_sr, CURSOR_SR)); |
1414 | 1422 | ||
1415 | if (cxsr_enabled) |
1423 | if (cxsr_enabled) |
1416 | intel_set_memory_cxsr(dev_priv, true); |
1424 | intel_set_memory_cxsr(dev_priv, true); |
1417 | } |
1425 | } |
1418 | 1426 | ||
1419 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
1427 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
1420 | { |
1428 | { |
1421 | struct drm_device *dev = unused_crtc->dev; |
1429 | struct drm_device *dev = unused_crtc->dev; |
1422 | struct drm_i915_private *dev_priv = dev->dev_private; |
1430 | struct drm_i915_private *dev_priv = dev->dev_private; |
1423 | struct drm_crtc *crtc; |
1431 | struct drm_crtc *crtc; |
1424 | int srwm = 1; |
1432 | int srwm = 1; |
1425 | int cursor_sr = 16; |
1433 | int cursor_sr = 16; |
1426 | bool cxsr_enabled; |
1434 | bool cxsr_enabled; |
1427 | 1435 | ||
1428 | /* Calc sr entries for one plane configs */ |
1436 | /* Calc sr entries for one plane configs */ |
1429 | crtc = single_enabled_crtc(dev); |
1437 | crtc = single_enabled_crtc(dev); |
1430 | if (crtc) { |
1438 | if (crtc) { |
1431 | /* self-refresh has much higher latency */ |
1439 | /* self-refresh has much higher latency */ |
1432 | static const int sr_latency_ns = 12000; |
1440 | static const int sr_latency_ns = 12000; |
1433 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1441 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1434 | int clock = adjusted_mode->crtc_clock; |
1442 | int clock = adjusted_mode->crtc_clock; |
1435 | int htotal = adjusted_mode->crtc_htotal; |
1443 | int htotal = adjusted_mode->crtc_htotal; |
1436 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
1444 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
1437 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
1445 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
1438 | unsigned long line_time_us; |
1446 | unsigned long line_time_us; |
1439 | int entries; |
1447 | int entries; |
1440 | 1448 | ||
1441 | line_time_us = max(htotal * 1000 / clock, 1); |
1449 | line_time_us = max(htotal * 1000 / clock, 1); |
1442 | 1450 | ||
1443 | /* Use ns/us then divide to preserve precision */ |
1451 | /* Use ns/us then divide to preserve precision */ |
1444 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1452 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1445 | pixel_size * hdisplay; |
1453 | pixel_size * hdisplay; |
1446 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1454 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1447 | srwm = I965_FIFO_SIZE - entries; |
1455 | srwm = I965_FIFO_SIZE - entries; |
1448 | if (srwm < 0) |
1456 | if (srwm < 0) |
1449 | srwm = 1; |
1457 | srwm = 1; |
1450 | srwm &= 0x1ff; |
1458 | srwm &= 0x1ff; |
1451 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1459 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1452 | entries, srwm); |
1460 | entries, srwm); |
1453 | 1461 | ||
1454 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1462 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1455 | pixel_size * crtc->cursor->state->crtc_w; |
1463 | pixel_size * crtc->cursor->state->crtc_w; |
1456 | entries = DIV_ROUND_UP(entries, |
1464 | entries = DIV_ROUND_UP(entries, |
1457 | i965_cursor_wm_info.cacheline_size); |
1465 | i965_cursor_wm_info.cacheline_size); |
1458 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1466 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1459 | (entries + i965_cursor_wm_info.guard_size); |
1467 | (entries + i965_cursor_wm_info.guard_size); |
1460 | 1468 | ||
1461 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1469 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1462 | cursor_sr = i965_cursor_wm_info.max_wm; |
1470 | cursor_sr = i965_cursor_wm_info.max_wm; |
1463 | 1471 | ||
1464 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1472 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1465 | "cursor %d\n", srwm, cursor_sr); |
1473 | "cursor %d\n", srwm, cursor_sr); |
1466 | 1474 | ||
1467 | cxsr_enabled = true; |
1475 | cxsr_enabled = true; |
1468 | } else { |
1476 | } else { |
1469 | cxsr_enabled = false; |
1477 | cxsr_enabled = false; |
1470 | /* Turn off self refresh if both pipes are enabled */ |
1478 | /* Turn off self refresh if both pipes are enabled */ |
1471 | intel_set_memory_cxsr(dev_priv, false); |
1479 | intel_set_memory_cxsr(dev_priv, false); |
1472 | } |
1480 | } |
1473 | 1481 | ||
1474 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1482 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1475 | srwm); |
1483 | srwm); |
1476 | 1484 | ||
1477 | /* 965 has limitations... */ |
1485 | /* 965 has limitations... */ |
1478 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1486 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1479 | FW_WM(8, CURSORB) | |
1487 | FW_WM(8, CURSORB) | |
1480 | FW_WM(8, PLANEB) | |
1488 | FW_WM(8, PLANEB) | |
1481 | FW_WM(8, PLANEA)); |
1489 | FW_WM(8, PLANEA)); |
1482 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | |
1490 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | |
1483 | FW_WM(8, PLANEC_OLD)); |
1491 | FW_WM(8, PLANEC_OLD)); |
1484 | /* update cursor SR watermark */ |
1492 | /* update cursor SR watermark */ |
1485 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
1493 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
1486 | 1494 | ||
1487 | if (cxsr_enabled) |
1495 | if (cxsr_enabled) |
1488 | intel_set_memory_cxsr(dev_priv, true); |
1496 | intel_set_memory_cxsr(dev_priv, true); |
1489 | } |
1497 | } |
1490 | 1498 | ||
1491 | #undef FW_WM |
1499 | #undef FW_WM |
1492 | 1500 | ||
1493 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
1501 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
1494 | { |
1502 | { |
1495 | struct drm_device *dev = unused_crtc->dev; |
1503 | struct drm_device *dev = unused_crtc->dev; |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; |
1504 | struct drm_i915_private *dev_priv = dev->dev_private; |
1497 | const struct intel_watermark_params *wm_info; |
1505 | const struct intel_watermark_params *wm_info; |
1498 | uint32_t fwater_lo; |
1506 | uint32_t fwater_lo; |
1499 | uint32_t fwater_hi; |
1507 | uint32_t fwater_hi; |
1500 | int cwm, srwm = 1; |
1508 | int cwm, srwm = 1; |
1501 | int fifo_size; |
1509 | int fifo_size; |
1502 | int planea_wm, planeb_wm; |
1510 | int planea_wm, planeb_wm; |
1503 | struct drm_crtc *crtc, *enabled = NULL; |
1511 | struct drm_crtc *crtc, *enabled = NULL; |
1504 | 1512 | ||
1505 | if (IS_I945GM(dev)) |
1513 | if (IS_I945GM(dev)) |
1506 | wm_info = &i945_wm_info; |
1514 | wm_info = &i945_wm_info; |
1507 | else if (!IS_GEN2(dev)) |
1515 | else if (!IS_GEN2(dev)) |
1508 | wm_info = &i915_wm_info; |
1516 | wm_info = &i915_wm_info; |
1509 | else |
1517 | else |
1510 | wm_info = &i830_a_wm_info; |
1518 | wm_info = &i830_a_wm_info; |
1511 | 1519 | ||
1512 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1520 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1513 | crtc = intel_get_crtc_for_plane(dev, 0); |
1521 | crtc = intel_get_crtc_for_plane(dev, 0); |
1514 | if (intel_crtc_active(crtc)) { |
1522 | if (intel_crtc_active(crtc)) { |
1515 | const struct drm_display_mode *adjusted_mode; |
1523 | const struct drm_display_mode *adjusted_mode; |
1516 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1524 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1517 | if (IS_GEN2(dev)) |
1525 | if (IS_GEN2(dev)) |
1518 | cpp = 4; |
1526 | cpp = 4; |
1519 | 1527 | ||
1520 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1528 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1521 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1529 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1522 | wm_info, fifo_size, cpp, |
1530 | wm_info, fifo_size, cpp, |
1523 | pessimal_latency_ns); |
1531 | pessimal_latency_ns); |
1524 | enabled = crtc; |
1532 | enabled = crtc; |
1525 | } else { |
1533 | } else { |
1526 | planea_wm = fifo_size - wm_info->guard_size; |
1534 | planea_wm = fifo_size - wm_info->guard_size; |
1527 | if (planea_wm > (long)wm_info->max_wm) |
1535 | if (planea_wm > (long)wm_info->max_wm) |
1528 | planea_wm = wm_info->max_wm; |
1536 | planea_wm = wm_info->max_wm; |
1529 | } |
1537 | } |
1530 | 1538 | ||
1531 | if (IS_GEN2(dev)) |
1539 | if (IS_GEN2(dev)) |
1532 | wm_info = &i830_bc_wm_info; |
1540 | wm_info = &i830_bc_wm_info; |
1533 | 1541 | ||
1534 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1542 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1535 | crtc = intel_get_crtc_for_plane(dev, 1); |
1543 | crtc = intel_get_crtc_for_plane(dev, 1); |
1536 | if (intel_crtc_active(crtc)) { |
1544 | if (intel_crtc_active(crtc)) { |
1537 | const struct drm_display_mode *adjusted_mode; |
1545 | const struct drm_display_mode *adjusted_mode; |
1538 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1546 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1539 | if (IS_GEN2(dev)) |
1547 | if (IS_GEN2(dev)) |
1540 | cpp = 4; |
1548 | cpp = 4; |
1541 | 1549 | ||
1542 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1550 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1543 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1551 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1544 | wm_info, fifo_size, cpp, |
1552 | wm_info, fifo_size, cpp, |
1545 | pessimal_latency_ns); |
1553 | pessimal_latency_ns); |
1546 | if (enabled == NULL) |
1554 | if (enabled == NULL) |
1547 | enabled = crtc; |
1555 | enabled = crtc; |
1548 | else |
1556 | else |
1549 | enabled = NULL; |
1557 | enabled = NULL; |
1550 | } else { |
1558 | } else { |
1551 | planeb_wm = fifo_size - wm_info->guard_size; |
1559 | planeb_wm = fifo_size - wm_info->guard_size; |
1552 | if (planeb_wm > (long)wm_info->max_wm) |
1560 | if (planeb_wm > (long)wm_info->max_wm) |
1553 | planeb_wm = wm_info->max_wm; |
1561 | planeb_wm = wm_info->max_wm; |
1554 | } |
1562 | } |
1555 | 1563 | ||
1556 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1564 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1557 | 1565 | ||
1558 | if (IS_I915GM(dev) && enabled) { |
1566 | if (IS_I915GM(dev) && enabled) { |
1559 | struct drm_i915_gem_object *obj; |
1567 | struct drm_i915_gem_object *obj; |
1560 | 1568 | ||
1561 | obj = intel_fb_obj(enabled->primary->state->fb); |
1569 | obj = intel_fb_obj(enabled->primary->state->fb); |
1562 | 1570 | ||
1563 | /* self-refresh seems busted with untiled */ |
1571 | /* self-refresh seems busted with untiled */ |
1564 | if (obj->tiling_mode == I915_TILING_NONE) |
1572 | if (obj->tiling_mode == I915_TILING_NONE) |
1565 | enabled = NULL; |
1573 | enabled = NULL; |
1566 | } |
1574 | } |
1567 | 1575 | ||
1568 | /* |
1576 | /* |
1569 | * Overlay gets an aggressive default since video jitter is bad. |
1577 | * Overlay gets an aggressive default since video jitter is bad. |
1570 | */ |
1578 | */ |
1571 | cwm = 2; |
1579 | cwm = 2; |
1572 | 1580 | ||
1573 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1581 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1574 | intel_set_memory_cxsr(dev_priv, false); |
1582 | intel_set_memory_cxsr(dev_priv, false); |
1575 | 1583 | ||
1576 | /* Calc sr entries for one plane configs */ |
1584 | /* Calc sr entries for one plane configs */ |
1577 | if (HAS_FW_BLC(dev) && enabled) { |
1585 | if (HAS_FW_BLC(dev) && enabled) { |
1578 | /* self-refresh has much higher latency */ |
1586 | /* self-refresh has much higher latency */ |
1579 | static const int sr_latency_ns = 6000; |
1587 | static const int sr_latency_ns = 6000; |
1580 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
1588 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
1581 | int clock = adjusted_mode->crtc_clock; |
1589 | int clock = adjusted_mode->crtc_clock; |
1582 | int htotal = adjusted_mode->crtc_htotal; |
1590 | int htotal = adjusted_mode->crtc_htotal; |
1583 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
1591 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
1584 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
1592 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
1585 | unsigned long line_time_us; |
1593 | unsigned long line_time_us; |
1586 | int entries; |
1594 | int entries; |
1587 | 1595 | ||
1588 | line_time_us = max(htotal * 1000 / clock, 1); |
1596 | line_time_us = max(htotal * 1000 / clock, 1); |
1589 | 1597 | ||
1590 | /* Use ns/us then divide to preserve precision */ |
1598 | /* Use ns/us then divide to preserve precision */ |
1591 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1599 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1592 | pixel_size * hdisplay; |
1600 | pixel_size * hdisplay; |
1593 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1601 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1594 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1602 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1595 | srwm = wm_info->fifo_size - entries; |
1603 | srwm = wm_info->fifo_size - entries; |
1596 | if (srwm < 0) |
1604 | if (srwm < 0) |
1597 | srwm = 1; |
1605 | srwm = 1; |
1598 | 1606 | ||
1599 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1607 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1600 | I915_WRITE(FW_BLC_SELF, |
1608 | I915_WRITE(FW_BLC_SELF, |
1601 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1609 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1602 | else if (IS_I915GM(dev)) |
1610 | else if (IS_I915GM(dev)) |
1603 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1611 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1604 | } |
1612 | } |
1605 | 1613 | ||
1606 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1614 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1607 | planea_wm, planeb_wm, cwm, srwm); |
1615 | planea_wm, planeb_wm, cwm, srwm); |
1608 | 1616 | ||
1609 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1617 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1610 | fwater_hi = (cwm & 0x1f); |
1618 | fwater_hi = (cwm & 0x1f); |
1611 | 1619 | ||
1612 | /* Set request length to 8 cachelines per fetch */ |
1620 | /* Set request length to 8 cachelines per fetch */ |
1613 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1621 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1614 | fwater_hi = fwater_hi | (1 << 8); |
1622 | fwater_hi = fwater_hi | (1 << 8); |
1615 | 1623 | ||
1616 | I915_WRITE(FW_BLC, fwater_lo); |
1624 | I915_WRITE(FW_BLC, fwater_lo); |
1617 | I915_WRITE(FW_BLC2, fwater_hi); |
1625 | I915_WRITE(FW_BLC2, fwater_hi); |
1618 | 1626 | ||
1619 | if (enabled) |
1627 | if (enabled) |
1620 | intel_set_memory_cxsr(dev_priv, true); |
1628 | intel_set_memory_cxsr(dev_priv, true); |
1621 | } |
1629 | } |
1622 | 1630 | ||
1623 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
1631 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
1624 | { |
1632 | { |
1625 | struct drm_device *dev = unused_crtc->dev; |
1633 | struct drm_device *dev = unused_crtc->dev; |
1626 | struct drm_i915_private *dev_priv = dev->dev_private; |
1634 | struct drm_i915_private *dev_priv = dev->dev_private; |
1627 | struct drm_crtc *crtc; |
1635 | struct drm_crtc *crtc; |
1628 | const struct drm_display_mode *adjusted_mode; |
1636 | const struct drm_display_mode *adjusted_mode; |
1629 | uint32_t fwater_lo; |
1637 | uint32_t fwater_lo; |
1630 | int planea_wm; |
1638 | int planea_wm; |
1631 | 1639 | ||
1632 | crtc = single_enabled_crtc(dev); |
1640 | crtc = single_enabled_crtc(dev); |
1633 | if (crtc == NULL) |
1641 | if (crtc == NULL) |
1634 | return; |
1642 | return; |
1635 | 1643 | ||
1636 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1644 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1637 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1645 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
1638 | &i845_wm_info, |
1646 | &i845_wm_info, |
1639 | dev_priv->display.get_fifo_size(dev, 0), |
1647 | dev_priv->display.get_fifo_size(dev, 0), |
1640 | 4, pessimal_latency_ns); |
1648 | 4, pessimal_latency_ns); |
1641 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1649 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1642 | fwater_lo |= (3<<8) | planea_wm; |
1650 | fwater_lo |= (3<<8) | planea_wm; |
1643 | 1651 | ||
1644 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1652 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1645 | 1653 | ||
1646 | I915_WRITE(FW_BLC, fwater_lo); |
1654 | I915_WRITE(FW_BLC, fwater_lo); |
1647 | } |
1655 | } |
1648 | 1656 | ||
1649 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
1657 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
1650 | { |
1658 | { |
1651 | uint32_t pixel_rate; |
1659 | uint32_t pixel_rate; |
1652 | 1660 | ||
1653 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
1661 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
1654 | 1662 | ||
1655 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
1663 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
1656 | * adjust the pixel_rate here. */ |
1664 | * adjust the pixel_rate here. */ |
1657 | 1665 | ||
1658 | if (pipe_config->pch_pfit.enabled) { |
1666 | if (pipe_config->pch_pfit.enabled) { |
1659 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
1667 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
1660 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
1668 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
1661 | 1669 | ||
1662 | pipe_w = pipe_config->pipe_src_w; |
1670 | pipe_w = pipe_config->pipe_src_w; |
1663 | pipe_h = pipe_config->pipe_src_h; |
1671 | pipe_h = pipe_config->pipe_src_h; |
1664 | 1672 | ||
1665 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1673 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1666 | pfit_h = pfit_size & 0xFFFF; |
1674 | pfit_h = pfit_size & 0xFFFF; |
1667 | if (pipe_w < pfit_w) |
1675 | if (pipe_w < pfit_w) |
1668 | pipe_w = pfit_w; |
1676 | pipe_w = pfit_w; |
1669 | if (pipe_h < pfit_h) |
1677 | if (pipe_h < pfit_h) |
1670 | pipe_h = pfit_h; |
1678 | pipe_h = pfit_h; |
1671 | 1679 | ||
1672 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
1680 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
1673 | pfit_w * pfit_h); |
1681 | pfit_w * pfit_h); |
1674 | } |
1682 | } |
1675 | 1683 | ||
1676 | return pixel_rate; |
1684 | return pixel_rate; |
1677 | } |
1685 | } |
1678 | 1686 | ||
1679 | /* latency must be in 0.1us units. */ |
1687 | /* latency must be in 0.1us units. */ |
1680 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
1688 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
1681 | uint32_t latency) |
1689 | uint32_t latency) |
1682 | { |
1690 | { |
1683 | uint64_t ret; |
1691 | uint64_t ret; |
1684 | 1692 | ||
1685 | if (WARN(latency == 0, "Latency value missing\n")) |
1693 | if (WARN(latency == 0, "Latency value missing\n")) |
1686 | return UINT_MAX; |
1694 | return UINT_MAX; |
1687 | 1695 | ||
1688 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1696 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1689 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1697 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1690 | 1698 | ||
1691 | return ret; |
1699 | return ret; |
1692 | } |
1700 | } |
1693 | 1701 | ||
1694 | /* latency must be in 0.1us units. */ |
1702 | /* latency must be in 0.1us units. */ |
1695 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
1703 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
1696 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1704 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1697 | uint32_t latency) |
1705 | uint32_t latency) |
1698 | { |
1706 | { |
1699 | uint32_t ret; |
1707 | uint32_t ret; |
1700 | 1708 | ||
1701 | if (WARN(latency == 0, "Latency value missing\n")) |
1709 | if (WARN(latency == 0, "Latency value missing\n")) |
1702 | return UINT_MAX; |
1710 | return UINT_MAX; |
1703 | 1711 | ||
1704 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1712 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1705 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
1713 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
1706 | ret = DIV_ROUND_UP(ret, 64) + 2; |
1714 | ret = DIV_ROUND_UP(ret, 64) + 2; |
1707 | return ret; |
1715 | return ret; |
1708 | } |
1716 | } |
1709 | 1717 | ||
1710 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
1718 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
1711 | uint8_t bytes_per_pixel) |
1719 | uint8_t bytes_per_pixel) |
1712 | { |
1720 | { |
1713 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
1721 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
1714 | } |
1722 | } |
1715 | - | ||
1716 | struct skl_pipe_wm_parameters { |
- | |
1717 | bool active; |
- | |
1718 | uint32_t pipe_htotal; |
- | |
1719 | uint32_t pixel_rate; /* in KHz */ |
- | |
1720 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; |
- | |
1721 | }; |
- | |
1722 | 1723 | ||
1723 | struct ilk_wm_maximums { |
1724 | struct ilk_wm_maximums { |
1724 | uint16_t pri; |
1725 | uint16_t pri; |
1725 | uint16_t spr; |
1726 | uint16_t spr; |
1726 | uint16_t cur; |
1727 | uint16_t cur; |
1727 | uint16_t fbc; |
1728 | uint16_t fbc; |
1728 | }; |
1729 | }; |
1729 | - | ||
1730 | /* used in computing the new watermarks state */ |
- | |
1731 | struct intel_wm_config { |
- | |
1732 | unsigned int num_pipes_active; |
- | |
1733 | bool sprites_enabled; |
- | |
1734 | bool sprites_scaled; |
- | |
1735 | }; |
- | |
1736 | 1730 | ||
1737 | /* |
1731 | /* |
1738 | * For both WM_PIPE and WM_LP. |
1732 | * For both WM_PIPE and WM_LP. |
1739 | * mem_value must be in 0.1us units. |
1733 | * mem_value must be in 0.1us units. |
1740 | */ |
1734 | */ |
1741 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
1735 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
1742 | const struct intel_plane_state *pstate, |
1736 | const struct intel_plane_state *pstate, |
1743 | uint32_t mem_value, |
1737 | uint32_t mem_value, |
1744 | bool is_lp) |
1738 | bool is_lp) |
1745 | { |
1739 | { |
1746 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1740 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1747 | uint32_t method1, method2; |
1741 | uint32_t method1, method2; |
1748 | 1742 | ||
1749 | if (!cstate->base.active || !pstate->visible) |
1743 | if (!cstate->base.active || !pstate->visible) |
1750 | return 0; |
1744 | return 0; |
1751 | 1745 | ||
1752 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1746 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1753 | 1747 | ||
1754 | if (!is_lp) |
1748 | if (!is_lp) |
1755 | return method1; |
1749 | return method1; |
1756 | 1750 | ||
1757 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1751 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1758 | cstate->base.adjusted_mode.crtc_htotal, |
1752 | cstate->base.adjusted_mode.crtc_htotal, |
1759 | drm_rect_width(&pstate->dst), |
1753 | drm_rect_width(&pstate->dst), |
1760 | bpp, |
1754 | bpp, |
1761 | mem_value); |
1755 | mem_value); |
1762 | 1756 | ||
1763 | return min(method1, method2); |
1757 | return min(method1, method2); |
1764 | } |
1758 | } |
1765 | 1759 | ||
1766 | /* |
1760 | /* |
1767 | * For both WM_PIPE and WM_LP. |
1761 | * For both WM_PIPE and WM_LP. |
1768 | * mem_value must be in 0.1us units. |
1762 | * mem_value must be in 0.1us units. |
1769 | */ |
1763 | */ |
1770 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
1764 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
1771 | const struct intel_plane_state *pstate, |
1765 | const struct intel_plane_state *pstate, |
1772 | uint32_t mem_value) |
1766 | uint32_t mem_value) |
1773 | { |
1767 | { |
1774 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1768 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1775 | uint32_t method1, method2; |
1769 | uint32_t method1, method2; |
1776 | 1770 | ||
1777 | if (!cstate->base.active || !pstate->visible) |
1771 | if (!cstate->base.active || !pstate->visible) |
1778 | return 0; |
1772 | return 0; |
1779 | 1773 | ||
1780 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1774 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1781 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1775 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1782 | cstate->base.adjusted_mode.crtc_htotal, |
1776 | cstate->base.adjusted_mode.crtc_htotal, |
1783 | drm_rect_width(&pstate->dst), |
1777 | drm_rect_width(&pstate->dst), |
1784 | bpp, |
1778 | bpp, |
1785 | mem_value); |
1779 | mem_value); |
1786 | return min(method1, method2); |
1780 | return min(method1, method2); |
1787 | } |
1781 | } |
1788 | 1782 | ||
1789 | /* |
1783 | /* |
1790 | * For both WM_PIPE and WM_LP. |
1784 | * For both WM_PIPE and WM_LP. |
1791 | * mem_value must be in 0.1us units. |
1785 | * mem_value must be in 0.1us units. |
1792 | */ |
1786 | */ |
1793 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
1787 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
1794 | const struct intel_plane_state *pstate, |
1788 | const struct intel_plane_state *pstate, |
1795 | uint32_t mem_value) |
1789 | uint32_t mem_value) |
1796 | { |
1790 | { |
1797 | /* |
1791 | /* |
1798 | * We treat the cursor plane as always-on for the purposes of watermark |
1792 | * We treat the cursor plane as always-on for the purposes of watermark |
1799 | * calculation. Until we have two-stage watermark programming merged, |
1793 | * calculation. Until we have two-stage watermark programming merged, |
1800 | * this is necessary to avoid flickering. |
1794 | * this is necessary to avoid flickering. |
1801 | */ |
1795 | */ |
1802 | int cpp = 4; |
1796 | int cpp = 4; |
1803 | int width = pstate->visible ? pstate->base.crtc_w : 64; |
1797 | int width = pstate->visible ? pstate->base.crtc_w : 64; |
1804 | 1798 | ||
1805 | if (!cstate->base.active) |
1799 | if (!cstate->base.active) |
1806 | return 0; |
1800 | return 0; |
1807 | 1801 | ||
1808 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1802 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1809 | cstate->base.adjusted_mode.crtc_htotal, |
1803 | cstate->base.adjusted_mode.crtc_htotal, |
1810 | width, cpp, mem_value); |
1804 | width, cpp, mem_value); |
1811 | } |
1805 | } |
1812 | 1806 | ||
1813 | /* Only for WM_LP. */ |
1807 | /* Only for WM_LP. */ |
1814 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
1808 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
1815 | const struct intel_plane_state *pstate, |
1809 | const struct intel_plane_state *pstate, |
1816 | uint32_t pri_val) |
1810 | uint32_t pri_val) |
1817 | { |
1811 | { |
1818 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1812 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1819 | 1813 | ||
1820 | if (!cstate->base.active || !pstate->visible) |
1814 | if (!cstate->base.active || !pstate->visible) |
1821 | return 0; |
1815 | return 0; |
1822 | 1816 | ||
1823 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
1817 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
1824 | } |
1818 | } |
1825 | 1819 | ||
1826 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1820 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1827 | { |
1821 | { |
1828 | if (INTEL_INFO(dev)->gen >= 8) |
1822 | if (INTEL_INFO(dev)->gen >= 8) |
1829 | return 3072; |
1823 | return 3072; |
1830 | else if (INTEL_INFO(dev)->gen >= 7) |
1824 | else if (INTEL_INFO(dev)->gen >= 7) |
1831 | return 768; |
1825 | return 768; |
1832 | else |
1826 | else |
1833 | return 512; |
1827 | return 512; |
1834 | } |
1828 | } |
1835 | 1829 | ||
1836 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1830 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1837 | int level, bool is_sprite) |
1831 | int level, bool is_sprite) |
1838 | { |
1832 | { |
1839 | if (INTEL_INFO(dev)->gen >= 8) |
1833 | if (INTEL_INFO(dev)->gen >= 8) |
1840 | /* BDW primary/sprite plane watermarks */ |
1834 | /* BDW primary/sprite plane watermarks */ |
1841 | return level == 0 ? 255 : 2047; |
1835 | return level == 0 ? 255 : 2047; |
1842 | else if (INTEL_INFO(dev)->gen >= 7) |
1836 | else if (INTEL_INFO(dev)->gen >= 7) |
1843 | /* IVB/HSW primary/sprite plane watermarks */ |
1837 | /* IVB/HSW primary/sprite plane watermarks */ |
1844 | return level == 0 ? 127 : 1023; |
1838 | return level == 0 ? 127 : 1023; |
1845 | else if (!is_sprite) |
1839 | else if (!is_sprite) |
1846 | /* ILK/SNB primary plane watermarks */ |
1840 | /* ILK/SNB primary plane watermarks */ |
1847 | return level == 0 ? 127 : 511; |
1841 | return level == 0 ? 127 : 511; |
1848 | else |
1842 | else |
1849 | /* ILK/SNB sprite plane watermarks */ |
1843 | /* ILK/SNB sprite plane watermarks */ |
1850 | return level == 0 ? 63 : 255; |
1844 | return level == 0 ? 63 : 255; |
1851 | } |
1845 | } |
1852 | 1846 | ||
1853 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
1847 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
1854 | int level) |
1848 | int level) |
1855 | { |
1849 | { |
1856 | if (INTEL_INFO(dev)->gen >= 7) |
1850 | if (INTEL_INFO(dev)->gen >= 7) |
1857 | return level == 0 ? 63 : 255; |
1851 | return level == 0 ? 63 : 255; |
1858 | else |
1852 | else |
1859 | return level == 0 ? 31 : 63; |
1853 | return level == 0 ? 31 : 63; |
1860 | } |
1854 | } |
1861 | 1855 | ||
1862 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
1856 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
1863 | { |
1857 | { |
1864 | if (INTEL_INFO(dev)->gen >= 8) |
1858 | if (INTEL_INFO(dev)->gen >= 8) |
1865 | return 31; |
1859 | return 31; |
1866 | else |
1860 | else |
1867 | return 15; |
1861 | return 15; |
1868 | } |
1862 | } |
1869 | 1863 | ||
1870 | /* Calculate the maximum primary/sprite plane watermark */ |
1864 | /* Calculate the maximum primary/sprite plane watermark */ |
1871 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
1865 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
1872 | int level, |
1866 | int level, |
1873 | const struct intel_wm_config *config, |
1867 | const struct intel_wm_config *config, |
1874 | enum intel_ddb_partitioning ddb_partitioning, |
1868 | enum intel_ddb_partitioning ddb_partitioning, |
1875 | bool is_sprite) |
1869 | bool is_sprite) |
1876 | { |
1870 | { |
1877 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
1871 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
1878 | 1872 | ||
1879 | /* if sprites aren't enabled, sprites get nothing */ |
1873 | /* if sprites aren't enabled, sprites get nothing */ |
1880 | if (is_sprite && !config->sprites_enabled) |
1874 | if (is_sprite && !config->sprites_enabled) |
1881 | return 0; |
1875 | return 0; |
1882 | 1876 | ||
1883 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
1877 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
1884 | if (level == 0 || config->num_pipes_active > 1) { |
1878 | if (level == 0 || config->num_pipes_active > 1) { |
1885 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1879 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1886 | 1880 | ||
1887 | /* |
1881 | /* |
1888 | * For some reason the non self refresh |
1882 | * For some reason the non self refresh |
1889 | * FIFO size is only half of the self |
1883 | * FIFO size is only half of the self |
1890 | * refresh FIFO size on ILK/SNB. |
1884 | * refresh FIFO size on ILK/SNB. |
1891 | */ |
1885 | */ |
1892 | if (INTEL_INFO(dev)->gen <= 6) |
1886 | if (INTEL_INFO(dev)->gen <= 6) |
1893 | fifo_size /= 2; |
1887 | fifo_size /= 2; |
1894 | } |
1888 | } |
1895 | 1889 | ||
1896 | if (config->sprites_enabled) { |
1890 | if (config->sprites_enabled) { |
1897 | /* level 0 is always calculated with 1:1 split */ |
1891 | /* level 0 is always calculated with 1:1 split */ |
1898 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
1892 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
1899 | if (is_sprite) |
1893 | if (is_sprite) |
1900 | fifo_size *= 5; |
1894 | fifo_size *= 5; |
1901 | fifo_size /= 6; |
1895 | fifo_size /= 6; |
1902 | } else { |
1896 | } else { |
1903 | fifo_size /= 2; |
1897 | fifo_size /= 2; |
1904 | } |
1898 | } |
1905 | } |
1899 | } |
1906 | 1900 | ||
1907 | /* clamp to max that the registers can hold */ |
1901 | /* clamp to max that the registers can hold */ |
1908 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
1902 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
1909 | } |
1903 | } |
1910 | 1904 | ||
1911 | /* Calculate the maximum cursor plane watermark */ |
1905 | /* Calculate the maximum cursor plane watermark */ |
1912 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
1906 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
1913 | int level, |
1907 | int level, |
1914 | const struct intel_wm_config *config) |
1908 | const struct intel_wm_config *config) |
1915 | { |
1909 | { |
1916 | /* HSW LP1+ watermarks w/ multiple pipes */ |
1910 | /* HSW LP1+ watermarks w/ multiple pipes */ |
1917 | if (level > 0 && config->num_pipes_active > 1) |
1911 | if (level > 0 && config->num_pipes_active > 1) |
1918 | return 64; |
1912 | return 64; |
1919 | 1913 | ||
1920 | /* otherwise just report max that registers can hold */ |
1914 | /* otherwise just report max that registers can hold */ |
1921 | return ilk_cursor_wm_reg_max(dev, level); |
1915 | return ilk_cursor_wm_reg_max(dev, level); |
1922 | } |
1916 | } |
1923 | 1917 | ||
1924 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
1918 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
1925 | int level, |
1919 | int level, |
1926 | const struct intel_wm_config *config, |
1920 | const struct intel_wm_config *config, |
1927 | enum intel_ddb_partitioning ddb_partitioning, |
1921 | enum intel_ddb_partitioning ddb_partitioning, |
1928 | struct ilk_wm_maximums *max) |
1922 | struct ilk_wm_maximums *max) |
1929 | { |
1923 | { |
1930 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1924 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1931 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
1925 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
1932 | max->cur = ilk_cursor_wm_max(dev, level, config); |
1926 | max->cur = ilk_cursor_wm_max(dev, level, config); |
1933 | max->fbc = ilk_fbc_wm_reg_max(dev); |
1927 | max->fbc = ilk_fbc_wm_reg_max(dev); |
1934 | } |
1928 | } |
1935 | 1929 | ||
1936 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1930 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1937 | int level, |
1931 | int level, |
1938 | struct ilk_wm_maximums *max) |
1932 | struct ilk_wm_maximums *max) |
1939 | { |
1933 | { |
1940 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
1934 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
1941 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
1935 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
1942 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
1936 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
1943 | max->fbc = ilk_fbc_wm_reg_max(dev); |
1937 | max->fbc = ilk_fbc_wm_reg_max(dev); |
1944 | } |
1938 | } |
1945 | 1939 | ||
1946 | static bool ilk_validate_wm_level(int level, |
1940 | static bool ilk_validate_wm_level(int level, |
1947 | const struct ilk_wm_maximums *max, |
1941 | const struct ilk_wm_maximums *max, |
1948 | struct intel_wm_level *result) |
1942 | struct intel_wm_level *result) |
1949 | { |
1943 | { |
1950 | bool ret; |
1944 | bool ret; |
1951 | 1945 | ||
1952 | /* already determined to be invalid? */ |
1946 | /* already determined to be invalid? */ |
1953 | if (!result->enable) |
1947 | if (!result->enable) |
1954 | return false; |
1948 | return false; |
1955 | 1949 | ||
1956 | result->enable = result->pri_val <= max->pri && |
1950 | result->enable = result->pri_val <= max->pri && |
1957 | result->spr_val <= max->spr && |
1951 | result->spr_val <= max->spr && |
1958 | result->cur_val <= max->cur; |
1952 | result->cur_val <= max->cur; |
1959 | 1953 | ||
1960 | ret = result->enable; |
1954 | ret = result->enable; |
1961 | 1955 | ||
1962 | /* |
1956 | /* |
1963 | * HACK until we can pre-compute everything, |
1957 | * HACK until we can pre-compute everything, |
1964 | * and thus fail gracefully if LP0 watermarks |
1958 | * and thus fail gracefully if LP0 watermarks |
1965 | * are exceeded... |
1959 | * are exceeded... |
1966 | */ |
1960 | */ |
1967 | if (level == 0 && !result->enable) { |
1961 | if (level == 0 && !result->enable) { |
1968 | if (result->pri_val > max->pri) |
1962 | if (result->pri_val > max->pri) |
1969 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
1963 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
1970 | level, result->pri_val, max->pri); |
1964 | level, result->pri_val, max->pri); |
1971 | if (result->spr_val > max->spr) |
1965 | if (result->spr_val > max->spr) |
1972 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
1966 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
1973 | level, result->spr_val, max->spr); |
1967 | level, result->spr_val, max->spr); |
1974 | if (result->cur_val > max->cur) |
1968 | if (result->cur_val > max->cur) |
1975 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
1969 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
1976 | level, result->cur_val, max->cur); |
1970 | level, result->cur_val, max->cur); |
1977 | 1971 | ||
1978 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
1972 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
1979 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
1973 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
1980 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
1974 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
1981 | result->enable = true; |
1975 | result->enable = true; |
1982 | } |
1976 | } |
1983 | 1977 | ||
1984 | return ret; |
1978 | return ret; |
1985 | } |
1979 | } |
1986 | 1980 | ||
1987 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
1981 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
1988 | const struct intel_crtc *intel_crtc, |
1982 | const struct intel_crtc *intel_crtc, |
1989 | int level, |
1983 | int level, |
1990 | struct intel_crtc_state *cstate, |
1984 | struct intel_crtc_state *cstate, |
- | 1985 | struct intel_plane_state *pristate, |
|
- | 1986 | struct intel_plane_state *sprstate, |
|
- | 1987 | struct intel_plane_state *curstate, |
|
1991 | struct intel_wm_level *result) |
1988 | struct intel_wm_level *result) |
1992 | { |
1989 | { |
1993 | struct intel_plane *intel_plane; |
- | |
1994 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
1990 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
1995 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
1991 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
1996 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
1992 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
1997 | 1993 | ||
1998 | /* WM1+ latency values stored in 0.5us units */ |
1994 | /* WM1+ latency values stored in 0.5us units */ |
1999 | if (level > 0) { |
1995 | if (level > 0) { |
2000 | pri_latency *= 5; |
1996 | pri_latency *= 5; |
2001 | spr_latency *= 5; |
1997 | spr_latency *= 5; |
2002 | cur_latency *= 5; |
1998 | cur_latency *= 5; |
2003 | } |
1999 | } |
2004 | - | ||
2005 | for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { |
- | |
2006 | struct intel_plane_state *pstate = |
- | |
2007 | to_intel_plane_state(intel_plane->base.state); |
- | |
2008 | - | ||
2009 | switch (intel_plane->base.type) { |
- | |
2010 | case DRM_PLANE_TYPE_PRIMARY: |
2000 | |
2011 | result->pri_val = ilk_compute_pri_wm(cstate, pstate, |
2001 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, |
2012 | pri_latency, |
- | |
2013 | level); |
2002 | pri_latency, level); |
2014 | result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, |
- | |
2015 | result->pri_val); |
- | |
2016 | break; |
- | |
2017 | case DRM_PLANE_TYPE_OVERLAY: |
2003 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); |
2018 | result->spr_val = ilk_compute_spr_wm(cstate, pstate, |
- | |
2019 | spr_latency); |
- | |
2020 | break; |
- | |
2021 | case DRM_PLANE_TYPE_CURSOR: |
2004 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); |
2022 | result->cur_val = ilk_compute_cur_wm(cstate, pstate, |
- | |
2023 | cur_latency); |
- | |
2024 | break; |
- | |
2025 | } |
- | |
2026 | } |
- | |
2027 | 2005 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); |
|
2028 | result->enable = true; |
2006 | result->enable = true; |
2029 | } |
2007 | } |
2030 | 2008 | ||
2031 | static uint32_t |
2009 | static uint32_t |
2032 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
2010 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
2033 | { |
2011 | { |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; |
2012 | struct drm_i915_private *dev_priv = dev->dev_private; |
2035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2036 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
2014 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
2037 | u32 linetime, ips_linetime; |
2015 | u32 linetime, ips_linetime; |
2038 | 2016 | ||
2039 | if (!intel_crtc->active) |
2017 | if (!intel_crtc->active) |
2040 | return 0; |
2018 | return 0; |
2041 | 2019 | ||
2042 | /* The WM are computed with base on how long it takes to fill a single |
2020 | /* The WM are computed with base on how long it takes to fill a single |
2043 | * row at the given clock rate, multiplied by 8. |
2021 | * row at the given clock rate, multiplied by 8. |
2044 | * */ |
2022 | * */ |
2045 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2023 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2046 | adjusted_mode->crtc_clock); |
2024 | adjusted_mode->crtc_clock); |
2047 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2025 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2048 | dev_priv->cdclk_freq); |
2026 | dev_priv->cdclk_freq); |
2049 | 2027 | ||
2050 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2028 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2051 | PIPE_WM_LINETIME_TIME(linetime); |
2029 | PIPE_WM_LINETIME_TIME(linetime); |
2052 | } |
2030 | } |
2053 | 2031 | ||
2054 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
2032 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
2055 | { |
2033 | { |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; |
2057 | 2035 | ||
2058 | if (IS_GEN9(dev)) { |
2036 | if (IS_GEN9(dev)) { |
2059 | uint32_t val; |
2037 | uint32_t val; |
2060 | int ret, i; |
2038 | int ret, i; |
2061 | int level, max_level = ilk_wm_max_level(dev); |
2039 | int level, max_level = ilk_wm_max_level(dev); |
2062 | 2040 | ||
2063 | /* read the first set of memory latencies[0:3] */ |
2041 | /* read the first set of memory latencies[0:3] */ |
2064 | val = 0; /* data0 to be programmed to 0 for first set */ |
2042 | val = 0; /* data0 to be programmed to 0 for first set */ |
2065 | mutex_lock(&dev_priv->rps.hw_lock); |
2043 | mutex_lock(&dev_priv->rps.hw_lock); |
2066 | ret = sandybridge_pcode_read(dev_priv, |
2044 | ret = sandybridge_pcode_read(dev_priv, |
2067 | GEN9_PCODE_READ_MEM_LATENCY, |
2045 | GEN9_PCODE_READ_MEM_LATENCY, |
2068 | &val); |
2046 | &val); |
2069 | mutex_unlock(&dev_priv->rps.hw_lock); |
2047 | mutex_unlock(&dev_priv->rps.hw_lock); |
2070 | 2048 | ||
2071 | if (ret) { |
2049 | if (ret) { |
2072 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
2050 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
2073 | return; |
2051 | return; |
2074 | } |
2052 | } |
2075 | 2053 | ||
2076 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
2054 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
2077 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
2055 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
2078 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2056 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2079 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
2057 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
2080 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2058 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2081 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
2059 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
2082 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2060 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2083 | 2061 | ||
2084 | /* read the second set of memory latencies[4:7] */ |
2062 | /* read the second set of memory latencies[4:7] */ |
2085 | val = 1; /* data0 to be programmed to 1 for second set */ |
2063 | val = 1; /* data0 to be programmed to 1 for second set */ |
2086 | mutex_lock(&dev_priv->rps.hw_lock); |
2064 | mutex_lock(&dev_priv->rps.hw_lock); |
2087 | ret = sandybridge_pcode_read(dev_priv, |
2065 | ret = sandybridge_pcode_read(dev_priv, |
2088 | GEN9_PCODE_READ_MEM_LATENCY, |
2066 | GEN9_PCODE_READ_MEM_LATENCY, |
2089 | &val); |
2067 | &val); |
2090 | mutex_unlock(&dev_priv->rps.hw_lock); |
2068 | mutex_unlock(&dev_priv->rps.hw_lock); |
2091 | if (ret) { |
2069 | if (ret) { |
2092 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
2070 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
2093 | return; |
2071 | return; |
2094 | } |
2072 | } |
2095 | 2073 | ||
2096 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
2074 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
2097 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
2075 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
2098 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2076 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2099 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
2077 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
2100 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2078 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2101 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
2079 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
2102 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2080 | GEN9_MEM_LATENCY_LEVEL_MASK; |
2103 | 2081 | ||
2104 | /* |
2082 | /* |
2105 | * If a level n (n > 1) has a 0us latency, all levels m (m >= n) |
- | |
2106 | * need to be disabled. We make sure to sanitize the values out |
- | |
2107 | * of the punit to satisfy this requirement. |
- | |
2108 | */ |
- | |
2109 | for (level = 1; level <= max_level; level++) { |
- | |
2110 | if (wm[level] == 0) { |
- | |
2111 | for (i = level + 1; i <= max_level; i++) |
- | |
2112 | wm[i] = 0; |
- | |
2113 | break; |
- | |
2114 | } |
- | |
2115 | } |
- | |
2116 | - | ||
2117 | /* |
- | |
2118 | * WaWmMemoryReadLatency:skl |
2083 | * WaWmMemoryReadLatency:skl |
2119 | * |
2084 | * |
2120 | * punit doesn't take into account the read latency so we need |
2085 | * punit doesn't take into account the read latency so we need |
2121 | * to add 2us to the various latency levels we retrieve from the |
2086 | * to add 2us to the various latency levels we retrieve from |
- | 2087 | * the punit. |
|
- | 2088 | * - W0 is a bit special in that it's the only level that |
|
- | 2089 | * can't be disabled if we want to have display working, so |
|
- | 2090 | * we always add 2us there. |
|
- | 2091 | * - For levels >=1, punit returns 0us latency when they are |
|
- | 2092 | * disabled, so we respect that and don't add 2us then |
|
- | 2093 | * |
|
- | 2094 | * Additionally, if a level n (n > 1) has a 0us latency, all |
|
- | 2095 | * levels m (m >= n) need to be disabled. We make sure to |
|
2122 | * punit when level 0 response data us 0us. |
2096 | * sanitize the values out of the punit to satisfy this |
- | 2097 | * requirement. |
|
2123 | */ |
2098 | */ |
2124 | if (wm[0] == 0) { |
- | |
2125 | wm[0] += 2; |
2099 | wm[0] += 2; |
2126 | for (level = 1; level <= max_level; level++) { |
2100 | for (level = 1; level <= max_level; level++) |
2127 | if (wm[level] == 0) |
2101 | if (wm[level] != 0) |
2128 | break; |
- | |
2129 | wm[level] += 2; |
2102 | wm[level] += 2; |
2130 | } |
2103 | else { |
- | 2104 | for (i = level + 1; i <= max_level; i++) |
|
2131 | } |
2105 | wm[i] = 0; |
- | 2106 | ||
- | 2107 | break; |
|
2132 | 2108 | } |
|
2133 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2109 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2134 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2110 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2135 | 2111 | ||
2136 | wm[0] = (sskpd >> 56) & 0xFF; |
2112 | wm[0] = (sskpd >> 56) & 0xFF; |
2137 | if (wm[0] == 0) |
2113 | if (wm[0] == 0) |
2138 | wm[0] = sskpd & 0xF; |
2114 | wm[0] = sskpd & 0xF; |
2139 | wm[1] = (sskpd >> 4) & 0xFF; |
2115 | wm[1] = (sskpd >> 4) & 0xFF; |
2140 | wm[2] = (sskpd >> 12) & 0xFF; |
2116 | wm[2] = (sskpd >> 12) & 0xFF; |
2141 | wm[3] = (sskpd >> 20) & 0x1FF; |
2117 | wm[3] = (sskpd >> 20) & 0x1FF; |
2142 | wm[4] = (sskpd >> 32) & 0x1FF; |
2118 | wm[4] = (sskpd >> 32) & 0x1FF; |
2143 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2119 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2144 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2120 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2145 | 2121 | ||
2146 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
2122 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
2147 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
2123 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
2148 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
2124 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
2149 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
2125 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
2150 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2126 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2151 | uint32_t mltr = I915_READ(MLTR_ILK); |
2127 | uint32_t mltr = I915_READ(MLTR_ILK); |
2152 | 2128 | ||
2153 | /* ILK primary LP0 latency is 700 ns */ |
2129 | /* ILK primary LP0 latency is 700 ns */ |
2154 | wm[0] = 7; |
2130 | wm[0] = 7; |
2155 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
2131 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
2156 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
2132 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
2157 | } |
2133 | } |
2158 | } |
2134 | } |
2159 | 2135 | ||
2160 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2136 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2161 | { |
2137 | { |
2162 | /* ILK sprite LP0 latency is 1300 ns */ |
2138 | /* ILK sprite LP0 latency is 1300 ns */ |
2163 | if (INTEL_INFO(dev)->gen == 5) |
2139 | if (INTEL_INFO(dev)->gen == 5) |
2164 | wm[0] = 13; |
2140 | wm[0] = 13; |
2165 | } |
2141 | } |
2166 | 2142 | ||
2167 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2143 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2168 | { |
2144 | { |
2169 | /* ILK cursor LP0 latency is 1300 ns */ |
2145 | /* ILK cursor LP0 latency is 1300 ns */ |
2170 | if (INTEL_INFO(dev)->gen == 5) |
2146 | if (INTEL_INFO(dev)->gen == 5) |
2171 | wm[0] = 13; |
2147 | wm[0] = 13; |
2172 | 2148 | ||
2173 | /* WaDoubleCursorLP3Latency:ivb */ |
2149 | /* WaDoubleCursorLP3Latency:ivb */ |
2174 | if (IS_IVYBRIDGE(dev)) |
2150 | if (IS_IVYBRIDGE(dev)) |
2175 | wm[3] *= 2; |
2151 | wm[3] *= 2; |
2176 | } |
2152 | } |
2177 | 2153 | ||
2178 | int ilk_wm_max_level(const struct drm_device *dev) |
2154 | int ilk_wm_max_level(const struct drm_device *dev) |
2179 | { |
2155 | { |
2180 | /* how many WM levels are we expecting */ |
2156 | /* how many WM levels are we expecting */ |
2181 | if (INTEL_INFO(dev)->gen >= 9) |
2157 | if (INTEL_INFO(dev)->gen >= 9) |
2182 | return 7; |
2158 | return 7; |
2183 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2159 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2184 | return 4; |
2160 | return 4; |
2185 | else if (INTEL_INFO(dev)->gen >= 6) |
2161 | else if (INTEL_INFO(dev)->gen >= 6) |
2186 | return 3; |
2162 | return 3; |
2187 | else |
2163 | else |
2188 | return 2; |
2164 | return 2; |
2189 | } |
2165 | } |
2190 | 2166 | ||
2191 | static void intel_print_wm_latency(struct drm_device *dev, |
2167 | static void intel_print_wm_latency(struct drm_device *dev, |
2192 | const char *name, |
2168 | const char *name, |
2193 | const uint16_t wm[8]) |
2169 | const uint16_t wm[8]) |
2194 | { |
2170 | { |
2195 | int level, max_level = ilk_wm_max_level(dev); |
2171 | int level, max_level = ilk_wm_max_level(dev); |
2196 | 2172 | ||
2197 | for (level = 0; level <= max_level; level++) { |
2173 | for (level = 0; level <= max_level; level++) { |
2198 | unsigned int latency = wm[level]; |
2174 | unsigned int latency = wm[level]; |
2199 | 2175 | ||
2200 | if (latency == 0) { |
2176 | if (latency == 0) { |
2201 | DRM_ERROR("%s WM%d latency not provided\n", |
2177 | DRM_ERROR("%s WM%d latency not provided\n", |
2202 | name, level); |
2178 | name, level); |
2203 | continue; |
2179 | continue; |
2204 | } |
2180 | } |
2205 | 2181 | ||
2206 | /* |
2182 | /* |
2207 | * - latencies are in us on gen9. |
2183 | * - latencies are in us on gen9. |
2208 | * - before then, WM1+ latency values are in 0.5us units |
2184 | * - before then, WM1+ latency values are in 0.5us units |
2209 | */ |
2185 | */ |
2210 | if (IS_GEN9(dev)) |
2186 | if (IS_GEN9(dev)) |
2211 | latency *= 10; |
2187 | latency *= 10; |
2212 | else if (level > 0) |
2188 | else if (level > 0) |
2213 | latency *= 5; |
2189 | latency *= 5; |
2214 | 2190 | ||
2215 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
2191 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
2216 | name, level, wm[level], |
2192 | name, level, wm[level], |
2217 | latency / 10, latency % 10); |
2193 | latency / 10, latency % 10); |
2218 | } |
2194 | } |
2219 | } |
2195 | } |
2220 | 2196 | ||
2221 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2197 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2222 | uint16_t wm[5], uint16_t min) |
2198 | uint16_t wm[5], uint16_t min) |
2223 | { |
2199 | { |
2224 | int level, max_level = ilk_wm_max_level(dev_priv->dev); |
2200 | int level, max_level = ilk_wm_max_level(dev_priv->dev); |
2225 | 2201 | ||
2226 | if (wm[0] >= min) |
2202 | if (wm[0] >= min) |
2227 | return false; |
2203 | return false; |
2228 | 2204 | ||
2229 | wm[0] = max(wm[0], min); |
2205 | wm[0] = max(wm[0], min); |
2230 | for (level = 1; level <= max_level; level++) |
2206 | for (level = 1; level <= max_level; level++) |
2231 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); |
2207 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); |
2232 | 2208 | ||
2233 | return true; |
2209 | return true; |
2234 | } |
2210 | } |
2235 | 2211 | ||
2236 | static void snb_wm_latency_quirk(struct drm_device *dev) |
2212 | static void snb_wm_latency_quirk(struct drm_device *dev) |
2237 | { |
2213 | { |
2238 | struct drm_i915_private *dev_priv = dev->dev_private; |
2214 | struct drm_i915_private *dev_priv = dev->dev_private; |
2239 | bool changed; |
2215 | bool changed; |
2240 | 2216 | ||
2241 | /* |
2217 | /* |
2242 | * The BIOS provided WM memory latency values are often |
2218 | * The BIOS provided WM memory latency values are often |
2243 | * inadequate for high resolution displays. Adjust them. |
2219 | * inadequate for high resolution displays. Adjust them. |
2244 | */ |
2220 | */ |
2245 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | |
2221 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | |
2246 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | |
2222 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | |
2247 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); |
2223 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); |
2248 | 2224 | ||
2249 | if (!changed) |
2225 | if (!changed) |
2250 | return; |
2226 | return; |
2251 | 2227 | ||
2252 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); |
2228 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); |
2253 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
2229 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
2254 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
2230 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
2255 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
2231 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
2256 | } |
2232 | } |
2257 | 2233 | ||
2258 | static void ilk_setup_wm_latency(struct drm_device *dev) |
2234 | static void ilk_setup_wm_latency(struct drm_device *dev) |
2259 | { |
2235 | { |
2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
2236 | struct drm_i915_private *dev_priv = dev->dev_private; |
2261 | 2237 | ||
2262 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
2238 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
2263 | 2239 | ||
2264 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
2240 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
2265 | sizeof(dev_priv->wm.pri_latency)); |
2241 | sizeof(dev_priv->wm.pri_latency)); |
2266 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
2242 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
2267 | sizeof(dev_priv->wm.pri_latency)); |
2243 | sizeof(dev_priv->wm.pri_latency)); |
2268 | 2244 | ||
2269 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
2245 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
2270 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
2246 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
2271 | 2247 | ||
2272 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
2248 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
2273 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
2249 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
2274 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
2250 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
2275 | 2251 | ||
2276 | if (IS_GEN6(dev)) |
2252 | if (IS_GEN6(dev)) |
2277 | snb_wm_latency_quirk(dev); |
2253 | snb_wm_latency_quirk(dev); |
2278 | } |
2254 | } |
2279 | 2255 | ||
2280 | static void skl_setup_wm_latency(struct drm_device *dev) |
2256 | static void skl_setup_wm_latency(struct drm_device *dev) |
2281 | { |
2257 | { |
2282 | struct drm_i915_private *dev_priv = dev->dev_private; |
2258 | struct drm_i915_private *dev_priv = dev->dev_private; |
2283 | 2259 | ||
2284 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); |
2260 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); |
2285 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); |
2261 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); |
2286 | } |
2262 | } |
2287 | - | ||
2288 | static void ilk_compute_wm_config(struct drm_device *dev, |
- | |
2289 | struct intel_wm_config *config) |
- | |
2290 | { |
- | |
2291 | struct intel_crtc *intel_crtc; |
- | |
2292 | - | ||
2293 | /* Compute the currently _active_ config */ |
- | |
2294 | for_each_intel_crtc(dev, intel_crtc) { |
- | |
2295 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
- | |
2296 | - | ||
2297 | if (!wm->pipe_enabled) |
- | |
2298 | continue; |
- | |
2299 | - | ||
2300 | config->sprites_enabled |= wm->sprites_enabled; |
- | |
2301 | config->sprites_scaled |= wm->sprites_scaled; |
- | |
2302 | config->num_pipes_active++; |
- | |
2303 | } |
- | |
2304 | } |
- | |
2305 | 2263 | ||
2306 | /* Compute new watermarks for the pipe */ |
2264 | /* Compute new watermarks for the pipe */ |
2307 | static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, |
2265 | static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc, |
2308 | struct intel_pipe_wm *pipe_wm) |
2266 | struct drm_atomic_state *state) |
2309 | { |
2267 | { |
2310 | struct drm_crtc *crtc = cstate->base.crtc; |
2268 | struct intel_pipe_wm *pipe_wm; |
2311 | struct drm_device *dev = crtc->dev; |
2269 | struct drm_device *dev = intel_crtc->base.dev; |
2312 | const struct drm_i915_private *dev_priv = dev->dev_private; |
2270 | const struct drm_i915_private *dev_priv = dev->dev_private; |
2313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2271 | struct intel_crtc_state *cstate = NULL; |
- | 2272 | struct intel_plane *intel_plane; |
|
- | 2273 | struct drm_plane_state *ps; |
|
2314 | struct intel_plane *intel_plane; |
2274 | struct intel_plane_state *pristate = NULL; |
- | 2275 | struct intel_plane_state *sprstate = NULL; |
|
2315 | struct intel_plane_state *sprstate = NULL; |
2276 | struct intel_plane_state *curstate = NULL; |
2316 | int level, max_level = ilk_wm_max_level(dev); |
2277 | int level, max_level = ilk_wm_max_level(dev); |
2317 | /* LP0 watermark maximums depend on this pipe alone */ |
2278 | /* LP0 watermark maximums depend on this pipe alone */ |
2318 | struct intel_wm_config config = { |
2279 | struct intel_wm_config config = { |
2319 | .num_pipes_active = 1, |
2280 | .num_pipes_active = 1, |
2320 | }; |
2281 | }; |
2321 | struct ilk_wm_maximums max; |
2282 | struct ilk_wm_maximums max; |
- | 2283 | ||
- | 2284 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); |
|
- | 2285 | if (IS_ERR(cstate)) |
|
- | 2286 | return PTR_ERR(cstate); |
|
- | 2287 | ||
- | 2288 | pipe_wm = &cstate->wm.optimal.ilk; |
|
- | 2289 | memset(pipe_wm, 0, sizeof(*pipe_wm)); |
|
2322 | 2290 | ||
- | 2291 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
|
- | 2292 | ps = drm_atomic_get_plane_state(state, |
|
- | 2293 | &intel_plane->base); |
|
- | 2294 | if (IS_ERR(ps)) |
|
- | 2295 | return PTR_ERR(ps); |
|
- | 2296 | ||
- | 2297 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
|
2323 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2298 | pristate = to_intel_plane_state(ps); |
2324 | if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { |
2299 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) |
- | 2300 | sprstate = to_intel_plane_state(ps); |
|
2325 | sprstate = to_intel_plane_state(intel_plane->base.state); |
2301 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
2326 | break; |
- | |
2327 | } |
2302 | curstate = to_intel_plane_state(ps); |
2328 | } |
2303 | } |
2329 | 2304 | ||
2330 | config.sprites_enabled = sprstate->visible; |
2305 | config.sprites_enabled = sprstate->visible; |
2331 | config.sprites_scaled = sprstate->visible && |
2306 | config.sprites_scaled = sprstate->visible && |
2332 | (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || |
2307 | (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || |
2333 | drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); |
2308 | drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); |
2334 | 2309 | ||
2335 | pipe_wm->pipe_enabled = cstate->base.active; |
2310 | pipe_wm->pipe_enabled = cstate->base.active; |
2336 | pipe_wm->sprites_enabled = sprstate->visible; |
2311 | pipe_wm->sprites_enabled = config.sprites_enabled; |
2337 | pipe_wm->sprites_scaled = config.sprites_scaled; |
2312 | pipe_wm->sprites_scaled = config.sprites_scaled; |
2338 | 2313 | ||
2339 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2314 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2340 | if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) |
2315 | if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) |
2341 | max_level = 1; |
2316 | max_level = 1; |
2342 | 2317 | ||
2343 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
2318 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
2344 | if (config.sprites_scaled) |
2319 | if (config.sprites_scaled) |
2345 | max_level = 0; |
2320 | max_level = 0; |
2346 | 2321 | ||
- | 2322 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
|
2347 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); |
2323 | pristate, sprstate, curstate, &pipe_wm->wm[0]); |
2348 | 2324 | ||
- | 2325 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
2349 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2326 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, |
2350 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
2327 | &intel_crtc->base); |
2351 | 2328 | ||
2352 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2329 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2353 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
2330 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
2354 | 2331 | ||
2355 | /* At least LP0 must be valid */ |
2332 | /* At least LP0 must be valid */ |
2356 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2333 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2357 | return false; |
2334 | return -EINVAL; |
2358 | 2335 | ||
2359 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
2336 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
2360 | 2337 | ||
2361 | for (level = 1; level <= max_level; level++) { |
2338 | for (level = 1; level <= max_level; level++) { |
2362 | struct intel_wm_level wm = {}; |
2339 | struct intel_wm_level wm = {}; |
2363 | 2340 | ||
- | 2341 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
|
2364 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); |
2342 | pristate, sprstate, curstate, &wm); |
2365 | 2343 | ||
2366 | /* |
2344 | /* |
2367 | * Disable any watermark level that exceeds the |
2345 | * Disable any watermark level that exceeds the |
2368 | * register maximums since such watermarks are |
2346 | * register maximums since such watermarks are |
2369 | * always invalid. |
2347 | * always invalid. |
2370 | */ |
2348 | */ |
2371 | if (!ilk_validate_wm_level(level, &max, &wm)) |
2349 | if (!ilk_validate_wm_level(level, &max, &wm)) |
2372 | break; |
2350 | break; |
2373 | 2351 | ||
2374 | pipe_wm->wm[level] = wm; |
2352 | pipe_wm->wm[level] = wm; |
2375 | } |
2353 | } |
2376 | 2354 | ||
2377 | return true; |
2355 | return 0; |
2378 | } |
2356 | } |
2379 | 2357 | ||
2380 | /* |
2358 | /* |
2381 | * Merge the watermarks from all active pipes for a specific level. |
2359 | * Merge the watermarks from all active pipes for a specific level. |
2382 | */ |
2360 | */ |
2383 | static void ilk_merge_wm_level(struct drm_device *dev, |
2361 | static void ilk_merge_wm_level(struct drm_device *dev, |
2384 | int level, |
2362 | int level, |
2385 | struct intel_wm_level *ret_wm) |
2363 | struct intel_wm_level *ret_wm) |
2386 | { |
2364 | { |
2387 | const struct intel_crtc *intel_crtc; |
2365 | const struct intel_crtc *intel_crtc; |
2388 | 2366 | ||
2389 | ret_wm->enable = true; |
2367 | ret_wm->enable = true; |
2390 | 2368 | ||
2391 | for_each_intel_crtc(dev, intel_crtc) { |
2369 | for_each_intel_crtc(dev, intel_crtc) { |
- | 2370 | const struct intel_crtc_state *cstate = |
|
- | 2371 | to_intel_crtc_state(intel_crtc->base.state); |
|
2392 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2372 | const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; |
2393 | const struct intel_wm_level *wm = &active->wm[level]; |
2373 | const struct intel_wm_level *wm = &active->wm[level]; |
2394 | 2374 | ||
2395 | if (!active->pipe_enabled) |
2375 | if (!active->pipe_enabled) |
2396 | continue; |
2376 | continue; |
2397 | 2377 | ||
2398 | /* |
2378 | /* |
2399 | * The watermark values may have been used in the past, |
2379 | * The watermark values may have been used in the past, |
2400 | * so we must maintain them in the registers for some |
2380 | * so we must maintain them in the registers for some |
2401 | * time even if the level is now disabled. |
2381 | * time even if the level is now disabled. |
2402 | */ |
2382 | */ |
2403 | if (!wm->enable) |
2383 | if (!wm->enable) |
2404 | ret_wm->enable = false; |
2384 | ret_wm->enable = false; |
2405 | 2385 | ||
2406 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
2386 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
2407 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
2387 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
2408 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
2388 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
2409 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
2389 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
2410 | } |
2390 | } |
2411 | } |
2391 | } |
2412 | 2392 | ||
2413 | /* |
2393 | /* |
2414 | * Merge all low power watermarks for all active pipes. |
2394 | * Merge all low power watermarks for all active pipes. |
2415 | */ |
2395 | */ |
2416 | static void ilk_wm_merge(struct drm_device *dev, |
2396 | static void ilk_wm_merge(struct drm_device *dev, |
2417 | const struct intel_wm_config *config, |
2397 | const struct intel_wm_config *config, |
2418 | const struct ilk_wm_maximums *max, |
2398 | const struct ilk_wm_maximums *max, |
2419 | struct intel_pipe_wm *merged) |
2399 | struct intel_pipe_wm *merged) |
2420 | { |
2400 | { |
2421 | struct drm_i915_private *dev_priv = dev->dev_private; |
2401 | struct drm_i915_private *dev_priv = dev->dev_private; |
2422 | int level, max_level = ilk_wm_max_level(dev); |
2402 | int level, max_level = ilk_wm_max_level(dev); |
2423 | int last_enabled_level = max_level; |
2403 | int last_enabled_level = max_level; |
2424 | 2404 | ||
2425 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2405 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2426 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
2406 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
2427 | config->num_pipes_active > 1) |
2407 | config->num_pipes_active > 1) |
2428 | return; |
2408 | return; |
2429 | 2409 | ||
2430 | /* ILK: FBC WM must be disabled always */ |
2410 | /* ILK: FBC WM must be disabled always */ |
2431 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
2411 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
2432 | 2412 | ||
2433 | /* merge each WM1+ level */ |
2413 | /* merge each WM1+ level */ |
2434 | for (level = 1; level <= max_level; level++) { |
2414 | for (level = 1; level <= max_level; level++) { |
2435 | struct intel_wm_level *wm = &merged->wm[level]; |
2415 | struct intel_wm_level *wm = &merged->wm[level]; |
2436 | 2416 | ||
2437 | ilk_merge_wm_level(dev, level, wm); |
2417 | ilk_merge_wm_level(dev, level, wm); |
2438 | 2418 | ||
2439 | if (level > last_enabled_level) |
2419 | if (level > last_enabled_level) |
2440 | wm->enable = false; |
2420 | wm->enable = false; |
2441 | else if (!ilk_validate_wm_level(level, max, wm)) |
2421 | else if (!ilk_validate_wm_level(level, max, wm)) |
2442 | /* make sure all following levels get disabled */ |
2422 | /* make sure all following levels get disabled */ |
2443 | last_enabled_level = level - 1; |
2423 | last_enabled_level = level - 1; |
2444 | 2424 | ||
2445 | /* |
2425 | /* |
2446 | * The spec says it is preferred to disable |
2426 | * The spec says it is preferred to disable |
2447 | * FBC WMs instead of disabling a WM level. |
2427 | * FBC WMs instead of disabling a WM level. |
2448 | */ |
2428 | */ |
2449 | if (wm->fbc_val > max->fbc) { |
2429 | if (wm->fbc_val > max->fbc) { |
2450 | if (wm->enable) |
2430 | if (wm->enable) |
2451 | merged->fbc_wm_enabled = false; |
2431 | merged->fbc_wm_enabled = false; |
2452 | wm->fbc_val = 0; |
2432 | wm->fbc_val = 0; |
2453 | } |
2433 | } |
2454 | } |
2434 | } |
2455 | 2435 | ||
2456 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
2436 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
2457 | /* |
2437 | /* |
2458 | * FIXME this is racy. FBC might get enabled later. |
2438 | * FIXME this is racy. FBC might get enabled later. |
2459 | * What we should check here is whether FBC can be |
2439 | * What we should check here is whether FBC can be |
2460 | * enabled sometime later. |
2440 | * enabled sometime later. |
2461 | */ |
2441 | */ |
2462 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && |
2442 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && |
2463 | intel_fbc_enabled(dev_priv)) { |
2443 | intel_fbc_is_active(dev_priv)) { |
2464 | for (level = 2; level <= max_level; level++) { |
2444 | for (level = 2; level <= max_level; level++) { |
2465 | struct intel_wm_level *wm = &merged->wm[level]; |
2445 | struct intel_wm_level *wm = &merged->wm[level]; |
2466 | 2446 | ||
2467 | wm->enable = false; |
2447 | wm->enable = false; |
2468 | } |
2448 | } |
2469 | } |
2449 | } |
2470 | } |
2450 | } |
2471 | 2451 | ||
2472 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2452 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2473 | { |
2453 | { |
2474 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
2454 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
2475 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
2455 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
2476 | } |
2456 | } |
2477 | 2457 | ||
2478 | /* The value we need to program into the WM_LPx latency field */ |
2458 | /* The value we need to program into the WM_LPx latency field */ |
2479 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
2459 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
2480 | { |
2460 | { |
2481 | struct drm_i915_private *dev_priv = dev->dev_private; |
2461 | struct drm_i915_private *dev_priv = dev->dev_private; |
2482 | 2462 | ||
2483 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2463 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2484 | return 2 * level; |
2464 | return 2 * level; |
2485 | else |
2465 | else |
2486 | return dev_priv->wm.pri_latency[level]; |
2466 | return dev_priv->wm.pri_latency[level]; |
2487 | } |
2467 | } |
2488 | 2468 | ||
2489 | static void ilk_compute_wm_results(struct drm_device *dev, |
2469 | static void ilk_compute_wm_results(struct drm_device *dev, |
2490 | const struct intel_pipe_wm *merged, |
2470 | const struct intel_pipe_wm *merged, |
2491 | enum intel_ddb_partitioning partitioning, |
2471 | enum intel_ddb_partitioning partitioning, |
2492 | struct ilk_wm_values *results) |
2472 | struct ilk_wm_values *results) |
2493 | { |
2473 | { |
2494 | struct intel_crtc *intel_crtc; |
2474 | struct intel_crtc *intel_crtc; |
2495 | int level, wm_lp; |
2475 | int level, wm_lp; |
2496 | 2476 | ||
2497 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
2477 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
2498 | results->partitioning = partitioning; |
2478 | results->partitioning = partitioning; |
2499 | 2479 | ||
2500 | /* LP1+ register values */ |
2480 | /* LP1+ register values */ |
2501 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
2481 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
2502 | const struct intel_wm_level *r; |
2482 | const struct intel_wm_level *r; |
2503 | 2483 | ||
2504 | level = ilk_wm_lp_to_level(wm_lp, merged); |
2484 | level = ilk_wm_lp_to_level(wm_lp, merged); |
2505 | 2485 | ||
2506 | r = &merged->wm[level]; |
2486 | r = &merged->wm[level]; |
2507 | 2487 | ||
2508 | /* |
2488 | /* |
2509 | * Maintain the watermark values even if the level is |
2489 | * Maintain the watermark values even if the level is |
2510 | * disabled. Doing otherwise could cause underruns. |
2490 | * disabled. Doing otherwise could cause underruns. |
2511 | */ |
2491 | */ |
2512 | results->wm_lp[wm_lp - 1] = |
2492 | results->wm_lp[wm_lp - 1] = |
2513 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
2493 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
2514 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2494 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2515 | r->cur_val; |
2495 | r->cur_val; |
2516 | 2496 | ||
2517 | if (r->enable) |
2497 | if (r->enable) |
2518 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
2498 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
2519 | 2499 | ||
2520 | if (INTEL_INFO(dev)->gen >= 8) |
2500 | if (INTEL_INFO(dev)->gen >= 8) |
2521 | results->wm_lp[wm_lp - 1] |= |
2501 | results->wm_lp[wm_lp - 1] |= |
2522 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
2502 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
2523 | else |
2503 | else |
2524 | results->wm_lp[wm_lp - 1] |= |
2504 | results->wm_lp[wm_lp - 1] |= |
2525 | r->fbc_val << WM1_LP_FBC_SHIFT; |
2505 | r->fbc_val << WM1_LP_FBC_SHIFT; |
2526 | 2506 | ||
2527 | /* |
2507 | /* |
2528 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
2508 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
2529 | * level is disabled. Doing otherwise could cause underruns. |
2509 | * level is disabled. Doing otherwise could cause underruns. |
2530 | */ |
2510 | */ |
2531 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2511 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2532 | WARN_ON(wm_lp != 1); |
2512 | WARN_ON(wm_lp != 1); |
2533 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
2513 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
2534 | } else |
2514 | } else |
2535 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
2515 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
2536 | } |
2516 | } |
2537 | 2517 | ||
2538 | /* LP0 register values */ |
2518 | /* LP0 register values */ |
2539 | for_each_intel_crtc(dev, intel_crtc) { |
2519 | for_each_intel_crtc(dev, intel_crtc) { |
- | 2520 | const struct intel_crtc_state *cstate = |
|
- | 2521 | to_intel_crtc_state(intel_crtc->base.state); |
|
2540 | enum pipe pipe = intel_crtc->pipe; |
2522 | enum pipe pipe = intel_crtc->pipe; |
2541 | const struct intel_wm_level *r = |
2523 | const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0]; |
2542 | &intel_crtc->wm.active.wm[0]; |
- | |
2543 | 2524 | ||
2544 | if (WARN_ON(!r->enable)) |
2525 | if (WARN_ON(!r->enable)) |
2545 | continue; |
2526 | continue; |
2546 | 2527 | ||
2547 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
2528 | results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime; |
2548 | 2529 | ||
2549 | results->wm_pipe[pipe] = |
2530 | results->wm_pipe[pipe] = |
2550 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
2531 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
2551 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
2532 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
2552 | r->cur_val; |
2533 | r->cur_val; |
2553 | } |
2534 | } |
2554 | } |
2535 | } |
2555 | 2536 | ||
2556 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2537 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2557 | * case both are at the same level. Prefer r1 in case they're the same. */ |
2538 | * case both are at the same level. Prefer r1 in case they're the same. */ |
2558 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
2539 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
2559 | struct intel_pipe_wm *r1, |
2540 | struct intel_pipe_wm *r1, |
2560 | struct intel_pipe_wm *r2) |
2541 | struct intel_pipe_wm *r2) |
2561 | { |
2542 | { |
2562 | int level, max_level = ilk_wm_max_level(dev); |
2543 | int level, max_level = ilk_wm_max_level(dev); |
2563 | int level1 = 0, level2 = 0; |
2544 | int level1 = 0, level2 = 0; |
2564 | 2545 | ||
2565 | for (level = 1; level <= max_level; level++) { |
2546 | for (level = 1; level <= max_level; level++) { |
2566 | if (r1->wm[level].enable) |
2547 | if (r1->wm[level].enable) |
2567 | level1 = level; |
2548 | level1 = level; |
2568 | if (r2->wm[level].enable) |
2549 | if (r2->wm[level].enable) |
2569 | level2 = level; |
2550 | level2 = level; |
2570 | } |
2551 | } |
2571 | 2552 | ||
2572 | if (level1 == level2) { |
2553 | if (level1 == level2) { |
2573 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
2554 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
2574 | return r2; |
2555 | return r2; |
2575 | else |
2556 | else |
2576 | return r1; |
2557 | return r1; |
2577 | } else if (level1 > level2) { |
2558 | } else if (level1 > level2) { |
2578 | return r1; |
2559 | return r1; |
2579 | } else { |
2560 | } else { |
2580 | return r2; |
2561 | return r2; |
2581 | } |
2562 | } |
2582 | } |
2563 | } |
2583 | 2564 | ||
2584 | /* dirty bits used to track which watermarks need changes */ |
2565 | /* dirty bits used to track which watermarks need changes */ |
2585 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
2566 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
2586 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
2567 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
2587 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
2568 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
2588 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
2569 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
2589 | #define WM_DIRTY_FBC (1 << 24) |
2570 | #define WM_DIRTY_FBC (1 << 24) |
2590 | #define WM_DIRTY_DDB (1 << 25) |
2571 | #define WM_DIRTY_DDB (1 << 25) |
2591 | 2572 | ||
2592 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
2573 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
2593 | const struct ilk_wm_values *old, |
2574 | const struct ilk_wm_values *old, |
2594 | const struct ilk_wm_values *new) |
2575 | const struct ilk_wm_values *new) |
2595 | { |
2576 | { |
2596 | unsigned int dirty = 0; |
2577 | unsigned int dirty = 0; |
2597 | enum pipe pipe; |
2578 | enum pipe pipe; |
2598 | int wm_lp; |
2579 | int wm_lp; |
2599 | 2580 | ||
2600 | for_each_pipe(dev_priv, pipe) { |
2581 | for_each_pipe(dev_priv, pipe) { |
2601 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2582 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2602 | dirty |= WM_DIRTY_LINETIME(pipe); |
2583 | dirty |= WM_DIRTY_LINETIME(pipe); |
2603 | /* Must disable LP1+ watermarks too */ |
2584 | /* Must disable LP1+ watermarks too */ |
2604 | dirty |= WM_DIRTY_LP_ALL; |
2585 | dirty |= WM_DIRTY_LP_ALL; |
2605 | } |
2586 | } |
2606 | 2587 | ||
2607 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
2588 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
2608 | dirty |= WM_DIRTY_PIPE(pipe); |
2589 | dirty |= WM_DIRTY_PIPE(pipe); |
2609 | /* Must disable LP1+ watermarks too */ |
2590 | /* Must disable LP1+ watermarks too */ |
2610 | dirty |= WM_DIRTY_LP_ALL; |
2591 | dirty |= WM_DIRTY_LP_ALL; |
2611 | } |
2592 | } |
2612 | } |
2593 | } |
2613 | 2594 | ||
2614 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
2595 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
2615 | dirty |= WM_DIRTY_FBC; |
2596 | dirty |= WM_DIRTY_FBC; |
2616 | /* Must disable LP1+ watermarks too */ |
2597 | /* Must disable LP1+ watermarks too */ |
2617 | dirty |= WM_DIRTY_LP_ALL; |
2598 | dirty |= WM_DIRTY_LP_ALL; |
2618 | } |
2599 | } |
2619 | 2600 | ||
2620 | if (old->partitioning != new->partitioning) { |
2601 | if (old->partitioning != new->partitioning) { |
2621 | dirty |= WM_DIRTY_DDB; |
2602 | dirty |= WM_DIRTY_DDB; |
2622 | /* Must disable LP1+ watermarks too */ |
2603 | /* Must disable LP1+ watermarks too */ |
2623 | dirty |= WM_DIRTY_LP_ALL; |
2604 | dirty |= WM_DIRTY_LP_ALL; |
2624 | } |
2605 | } |
2625 | 2606 | ||
2626 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
2607 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
2627 | if (dirty & WM_DIRTY_LP_ALL) |
2608 | if (dirty & WM_DIRTY_LP_ALL) |
2628 | return dirty; |
2609 | return dirty; |
2629 | 2610 | ||
2630 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
2611 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
2631 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
2612 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
2632 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
2613 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
2633 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
2614 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
2634 | break; |
2615 | break; |
2635 | } |
2616 | } |
2636 | 2617 | ||
2637 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
2618 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
2638 | for (; wm_lp <= 3; wm_lp++) |
2619 | for (; wm_lp <= 3; wm_lp++) |
2639 | dirty |= WM_DIRTY_LP(wm_lp); |
2620 | dirty |= WM_DIRTY_LP(wm_lp); |
2640 | 2621 | ||
2641 | return dirty; |
2622 | return dirty; |
2642 | } |
2623 | } |
2643 | 2624 | ||
2644 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2625 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2645 | unsigned int dirty) |
2626 | unsigned int dirty) |
2646 | { |
2627 | { |
2647 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
2628 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
2648 | bool changed = false; |
2629 | bool changed = false; |
2649 | 2630 | ||
2650 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2631 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2651 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
2632 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
2652 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
2633 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
2653 | changed = true; |
2634 | changed = true; |
2654 | } |
2635 | } |
2655 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
2636 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
2656 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
2637 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
2657 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
2638 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
2658 | changed = true; |
2639 | changed = true; |
2659 | } |
2640 | } |
2660 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
2641 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
2661 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
2642 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
2662 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
2643 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
2663 | changed = true; |
2644 | changed = true; |
2664 | } |
2645 | } |
2665 | 2646 | ||
2666 | /* |
2647 | /* |
2667 | * Don't touch WM1S_LP_EN here. |
2648 | * Don't touch WM1S_LP_EN here. |
2668 | * Doing so could cause underruns. |
2649 | * Doing so could cause underruns. |
2669 | */ |
2650 | */ |
2670 | 2651 | ||
2671 | return changed; |
2652 | return changed; |
2672 | } |
2653 | } |
2673 | 2654 | ||
2674 | /* |
2655 | /* |
2675 | * The spec says we shouldn't write when we don't need, because every write |
2656 | * The spec says we shouldn't write when we don't need, because every write |
2676 | * causes WMs to be re-evaluated, expending some power. |
2657 | * causes WMs to be re-evaluated, expending some power. |
2677 | */ |
2658 | */ |
2678 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2659 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2679 | struct ilk_wm_values *results) |
2660 | struct ilk_wm_values *results) |
2680 | { |
2661 | { |
2681 | struct drm_device *dev = dev_priv->dev; |
2662 | struct drm_device *dev = dev_priv->dev; |
2682 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
2663 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
2683 | unsigned int dirty; |
2664 | unsigned int dirty; |
2684 | uint32_t val; |
2665 | uint32_t val; |
2685 | 2666 | ||
2686 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
2667 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
2687 | if (!dirty) |
2668 | if (!dirty) |
2688 | return; |
2669 | return; |
2689 | 2670 | ||
2690 | _ilk_disable_lp_wm(dev_priv, dirty); |
2671 | _ilk_disable_lp_wm(dev_priv, dirty); |
2691 | 2672 | ||
2692 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
2673 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
2693 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
2674 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
2694 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
2675 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
2695 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
2676 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
2696 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
2677 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
2697 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2678 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2698 | 2679 | ||
2699 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
2680 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
2700 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
2681 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
2701 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
2682 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
2702 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
2683 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
2703 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
2684 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
2704 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2685 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2705 | 2686 | ||
2706 | if (dirty & WM_DIRTY_DDB) { |
2687 | if (dirty & WM_DIRTY_DDB) { |
2707 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2688 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2708 | val = I915_READ(WM_MISC); |
2689 | val = I915_READ(WM_MISC); |
2709 | if (results->partitioning == INTEL_DDB_PART_1_2) |
2690 | if (results->partitioning == INTEL_DDB_PART_1_2) |
2710 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
2691 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
2711 | else |
2692 | else |
2712 | val |= WM_MISC_DATA_PARTITION_5_6; |
2693 | val |= WM_MISC_DATA_PARTITION_5_6; |
2713 | I915_WRITE(WM_MISC, val); |
2694 | I915_WRITE(WM_MISC, val); |
2714 | } else { |
2695 | } else { |
2715 | val = I915_READ(DISP_ARB_CTL2); |
2696 | val = I915_READ(DISP_ARB_CTL2); |
2716 | if (results->partitioning == INTEL_DDB_PART_1_2) |
2697 | if (results->partitioning == INTEL_DDB_PART_1_2) |
2717 | val &= ~DISP_DATA_PARTITION_5_6; |
2698 | val &= ~DISP_DATA_PARTITION_5_6; |
2718 | else |
2699 | else |
2719 | val |= DISP_DATA_PARTITION_5_6; |
2700 | val |= DISP_DATA_PARTITION_5_6; |
2720 | I915_WRITE(DISP_ARB_CTL2, val); |
2701 | I915_WRITE(DISP_ARB_CTL2, val); |
2721 | } |
2702 | } |
2722 | } |
2703 | } |
2723 | 2704 | ||
2724 | if (dirty & WM_DIRTY_FBC) { |
2705 | if (dirty & WM_DIRTY_FBC) { |
2725 | val = I915_READ(DISP_ARB_CTL); |
2706 | val = I915_READ(DISP_ARB_CTL); |
2726 | if (results->enable_fbc_wm) |
2707 | if (results->enable_fbc_wm) |
2727 | val &= ~DISP_FBC_WM_DIS; |
2708 | val &= ~DISP_FBC_WM_DIS; |
2728 | else |
2709 | else |
2729 | val |= DISP_FBC_WM_DIS; |
2710 | val |= DISP_FBC_WM_DIS; |
2730 | I915_WRITE(DISP_ARB_CTL, val); |
2711 | I915_WRITE(DISP_ARB_CTL, val); |
2731 | } |
2712 | } |
2732 | 2713 | ||
2733 | if (dirty & WM_DIRTY_LP(1) && |
2714 | if (dirty & WM_DIRTY_LP(1) && |
2734 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
2715 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
2735 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
2716 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
2736 | 2717 | ||
2737 | if (INTEL_INFO(dev)->gen >= 7) { |
2718 | if (INTEL_INFO(dev)->gen >= 7) { |
2738 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2719 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2739 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
2720 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
2740 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
2721 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
2741 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
2722 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
2742 | } |
2723 | } |
2743 | 2724 | ||
2744 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
2725 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
2745 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
2726 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
2746 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
2727 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
2747 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
2728 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
2748 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
2729 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
2749 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
2730 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
2750 | 2731 | ||
2751 | dev_priv->wm.hw = *results; |
2732 | dev_priv->wm.hw = *results; |
2752 | } |
2733 | } |
2753 | 2734 | ||
2754 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2735 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2755 | { |
2736 | { |
2756 | struct drm_i915_private *dev_priv = dev->dev_private; |
2737 | struct drm_i915_private *dev_priv = dev->dev_private; |
2757 | 2738 | ||
2758 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
2739 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
2759 | } |
2740 | } |
2760 | 2741 | ||
2761 | /* |
2742 | /* |
2762 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the |
2743 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the |
2763 | * different active planes. |
2744 | * different active planes. |
2764 | */ |
2745 | */ |
2765 | 2746 | ||
2766 | #define SKL_DDB_SIZE 896 /* in blocks */ |
2747 | #define SKL_DDB_SIZE 896 /* in blocks */ |
2767 | #define BXT_DDB_SIZE 512 |
2748 | #define BXT_DDB_SIZE 512 |
- | 2749 | ||
- | 2750 | /* |
|
- | 2751 | * Return the index of a plane in the SKL DDB and wm result arrays. Primary |
|
- | 2752 | * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and |
|
- | 2753 | * other universal planes are in indices 1..n. Note that this may leave unused |
|
- | 2754 | * indices between the top "sprite" plane and the cursor. |
|
- | 2755 | */ |
|
- | 2756 | static int |
|
- | 2757 | skl_wm_plane_id(const struct intel_plane *plane) |
|
- | 2758 | { |
|
- | 2759 | switch (plane->base.type) { |
|
- | 2760 | case DRM_PLANE_TYPE_PRIMARY: |
|
- | 2761 | return 0; |
|
- | 2762 | case DRM_PLANE_TYPE_CURSOR: |
|
- | 2763 | return PLANE_CURSOR; |
|
- | 2764 | case DRM_PLANE_TYPE_OVERLAY: |
|
- | 2765 | return plane->plane + 1; |
|
- | 2766 | default: |
|
- | 2767 | MISSING_CASE(plane->base.type); |
|
- | 2768 | return plane->plane; |
|
- | 2769 | } |
|
- | 2770 | } |
|
2768 | 2771 | ||
2769 | static void |
2772 | static void |
2770 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, |
2773 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, |
2771 | struct drm_crtc *for_crtc, |
2774 | const struct intel_crtc_state *cstate, |
2772 | const struct intel_wm_config *config, |
- | |
2773 | const struct skl_pipe_wm_parameters *params, |
2775 | const struct intel_wm_config *config, |
2774 | struct skl_ddb_entry *alloc /* out */) |
2776 | struct skl_ddb_entry *alloc /* out */) |
- | 2777 | { |
|
2775 | { |
2778 | struct drm_crtc *for_crtc = cstate->base.crtc; |
2776 | struct drm_crtc *crtc; |
2779 | struct drm_crtc *crtc; |
2777 | unsigned int pipe_size, ddb_size; |
2780 | unsigned int pipe_size, ddb_size; |
2778 | int nth_active_pipe; |
2781 | int nth_active_pipe; |
2779 | 2782 | ||
2780 | if (!params->active) { |
2783 | if (!cstate->base.active) { |
2781 | alloc->start = 0; |
2784 | alloc->start = 0; |
2782 | alloc->end = 0; |
2785 | alloc->end = 0; |
2783 | return; |
2786 | return; |
2784 | } |
2787 | } |
2785 | 2788 | ||
2786 | if (IS_BROXTON(dev)) |
2789 | if (IS_BROXTON(dev)) |
2787 | ddb_size = BXT_DDB_SIZE; |
2790 | ddb_size = BXT_DDB_SIZE; |
2788 | else |
2791 | else |
2789 | ddb_size = SKL_DDB_SIZE; |
2792 | ddb_size = SKL_DDB_SIZE; |
2790 | 2793 | ||
2791 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ |
2794 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ |
2792 | 2795 | ||
2793 | nth_active_pipe = 0; |
2796 | nth_active_pipe = 0; |
2794 | for_each_crtc(dev, crtc) { |
2797 | for_each_crtc(dev, crtc) { |
2795 | if (!to_intel_crtc(crtc)->active) |
2798 | if (!to_intel_crtc(crtc)->active) |
2796 | continue; |
2799 | continue; |
2797 | 2800 | ||
2798 | if (crtc == for_crtc) |
2801 | if (crtc == for_crtc) |
2799 | break; |
2802 | break; |
2800 | 2803 | ||
2801 | nth_active_pipe++; |
2804 | nth_active_pipe++; |
2802 | } |
2805 | } |
2803 | 2806 | ||
2804 | pipe_size = ddb_size / config->num_pipes_active; |
2807 | pipe_size = ddb_size / config->num_pipes_active; |
2805 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; |
2808 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; |
2806 | alloc->end = alloc->start + pipe_size; |
2809 | alloc->end = alloc->start + pipe_size; |
2807 | } |
2810 | } |
2808 | 2811 | ||
2809 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) |
2812 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) |
2810 | { |
2813 | { |
2811 | if (config->num_pipes_active == 1) |
2814 | if (config->num_pipes_active == 1) |
2812 | return 32; |
2815 | return 32; |
2813 | 2816 | ||
2814 | return 8; |
2817 | return 8; |
2815 | } |
2818 | } |
2816 | 2819 | ||
2817 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2820 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2818 | { |
2821 | { |
2819 | entry->start = reg & 0x3ff; |
2822 | entry->start = reg & 0x3ff; |
2820 | entry->end = (reg >> 16) & 0x3ff; |
2823 | entry->end = (reg >> 16) & 0x3ff; |
2821 | if (entry->end) |
2824 | if (entry->end) |
2822 | entry->end += 1; |
2825 | entry->end += 1; |
2823 | } |
2826 | } |
2824 | 2827 | ||
2825 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2828 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2826 | struct skl_ddb_allocation *ddb /* out */) |
2829 | struct skl_ddb_allocation *ddb /* out */) |
2827 | { |
2830 | { |
2828 | enum pipe pipe; |
2831 | enum pipe pipe; |
2829 | int plane; |
2832 | int plane; |
2830 | u32 val; |
2833 | u32 val; |
2831 | 2834 | ||
2832 | memset(ddb, 0, sizeof(*ddb)); |
2835 | memset(ddb, 0, sizeof(*ddb)); |
2833 | 2836 | ||
2834 | for_each_pipe(dev_priv, pipe) { |
2837 | for_each_pipe(dev_priv, pipe) { |
- | 2838 | enum intel_display_power_domain power_domain; |
|
- | 2839 | ||
- | 2840 | power_domain = POWER_DOMAIN_PIPE(pipe); |
|
2835 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) |
2841 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
2836 | continue; |
2842 | continue; |
2837 | 2843 | ||
2838 | for_each_plane(dev_priv, pipe, plane) { |
2844 | for_each_plane(dev_priv, pipe, plane) { |
2839 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2845 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2840 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], |
2846 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], |
2841 | val); |
2847 | val); |
2842 | } |
2848 | } |
2843 | 2849 | ||
2844 | val = I915_READ(CUR_BUF_CFG(pipe)); |
2850 | val = I915_READ(CUR_BUF_CFG(pipe)); |
2845 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], |
2851 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], |
2846 | val); |
2852 | val); |
- | 2853 | ||
- | 2854 | intel_display_power_put(dev_priv, power_domain); |
|
2847 | } |
2855 | } |
2848 | } |
2856 | } |
2849 | 2857 | ||
2850 | static unsigned int |
2858 | static unsigned int |
2851 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) |
2859 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
- | 2860 | const struct drm_plane_state *pstate, |
|
- | 2861 | int y) |
|
2852 | { |
2862 | { |
- | 2863 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
|
- | 2864 | struct drm_framebuffer *fb = pstate->fb; |
|
2853 | 2865 | ||
2854 | /* for planar format */ |
2866 | /* for planar format */ |
2855 | if (p->y_bytes_per_pixel) { |
2867 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
2856 | if (y) /* y-plane data rate */ |
2868 | if (y) /* y-plane data rate */ |
- | 2869 | return intel_crtc->config->pipe_src_w * |
|
- | 2870 | intel_crtc->config->pipe_src_h * |
|
2857 | return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; |
2871 | drm_format_plane_cpp(fb->pixel_format, 0); |
2858 | else /* uv-plane data rate */ |
2872 | else /* uv-plane data rate */ |
- | 2873 | return (intel_crtc->config->pipe_src_w/2) * |
|
- | 2874 | (intel_crtc->config->pipe_src_h/2) * |
|
2859 | return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; |
2875 | drm_format_plane_cpp(fb->pixel_format, 1); |
2860 | } |
2876 | } |
2861 | 2877 | ||
2862 | /* for packed formats */ |
2878 | /* for packed formats */ |
2863 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; |
2879 | return intel_crtc->config->pipe_src_w * |
- | 2880 | intel_crtc->config->pipe_src_h * |
|
- | 2881 | drm_format_plane_cpp(fb->pixel_format, 0); |
|
2864 | } |
2882 | } |
2865 | 2883 | ||
2866 | /* |
2884 | /* |
2867 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching |
2885 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching |
2868 | * a 8192x4096@32bpp framebuffer: |
2886 | * a 8192x4096@32bpp framebuffer: |
2869 | * 3 * 4096 * 8192 * 4 < 2^32 |
2887 | * 3 * 4096 * 8192 * 4 < 2^32 |
2870 | */ |
2888 | */ |
2871 | static unsigned int |
2889 | static unsigned int |
2872 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, |
2890 | skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate) |
2873 | const struct skl_pipe_wm_parameters *params) |
- | |
2874 | { |
2891 | { |
- | 2892 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
|
- | 2893 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 2894 | const struct intel_plane *intel_plane; |
|
2875 | unsigned int total_data_rate = 0; |
2895 | unsigned int total_data_rate = 0; |
2876 | int plane; |
- | |
2877 | 2896 | ||
2878 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2897 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2879 | const struct intel_plane_wm_parameters *p; |
- | |
2880 | 2898 | const struct drm_plane_state *pstate = intel_plane->base.state; |
|
2881 | p = ¶ms->plane[plane]; |
2899 | |
- | 2900 | if (pstate->fb == NULL) |
|
- | 2901 | continue; |
|
- | 2902 | ||
- | 2903 | if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
|
2882 | if (!p->enabled) |
2904 | continue; |
- | 2905 | ||
- | 2906 | /* packed/uv */ |
|
- | 2907 | total_data_rate += skl_plane_relative_data_rate(cstate, |
|
2883 | continue; |
2908 | pstate, |
- | 2909 | 0); |
|
2884 | 2910 | ||
- | 2911 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) |
|
2885 | total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ |
2912 | /* y-plane */ |
2886 | if (p->y_bytes_per_pixel) { |
2913 | total_data_rate += skl_plane_relative_data_rate(cstate, |
2887 | total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ |
2914 | pstate, |
2888 | } |
2915 | 1); |
2889 | } |
2916 | } |
2890 | 2917 | ||
2891 | return total_data_rate; |
2918 | return total_data_rate; |
2892 | } |
2919 | } |
2893 | 2920 | ||
2894 | static void |
2921 | static void |
2895 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, |
2922 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
2896 | const struct intel_wm_config *config, |
- | |
2897 | const struct skl_pipe_wm_parameters *params, |
- | |
2898 | struct skl_ddb_allocation *ddb /* out */) |
2923 | struct skl_ddb_allocation *ddb /* out */) |
2899 | { |
2924 | { |
- | 2925 | struct drm_crtc *crtc = cstate->base.crtc; |
|
2900 | struct drm_device *dev = crtc->dev; |
2926 | struct drm_device *dev = crtc->dev; |
2901 | struct drm_i915_private *dev_priv = dev->dev_private; |
2927 | struct drm_i915_private *dev_priv = to_i915(dev); |
- | 2928 | struct intel_wm_config *config = &dev_priv->wm.config; |
|
2902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 2930 | struct intel_plane *intel_plane; |
|
2903 | enum pipe pipe = intel_crtc->pipe; |
2931 | enum pipe pipe = intel_crtc->pipe; |
2904 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
2932 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
2905 | uint16_t alloc_size, start, cursor_blocks; |
2933 | uint16_t alloc_size, start, cursor_blocks; |
2906 | uint16_t minimum[I915_MAX_PLANES]; |
2934 | uint16_t minimum[I915_MAX_PLANES]; |
2907 | uint16_t y_minimum[I915_MAX_PLANES]; |
2935 | uint16_t y_minimum[I915_MAX_PLANES]; |
2908 | unsigned int total_data_rate; |
2936 | unsigned int total_data_rate; |
2909 | int plane; |
- | |
2910 | 2937 | ||
2911 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
2938 | skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc); |
2912 | alloc_size = skl_ddb_entry_size(alloc); |
2939 | alloc_size = skl_ddb_entry_size(alloc); |
2913 | if (alloc_size == 0) { |
2940 | if (alloc_size == 0) { |
2914 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); |
2941 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); |
2915 | memset(&ddb->plane[pipe][PLANE_CURSOR], 0, |
2942 | memset(&ddb->plane[pipe][PLANE_CURSOR], 0, |
2916 | sizeof(ddb->plane[pipe][PLANE_CURSOR])); |
2943 | sizeof(ddb->plane[pipe][PLANE_CURSOR])); |
2917 | return; |
2944 | return; |
2918 | } |
2945 | } |
2919 | 2946 | ||
2920 | cursor_blocks = skl_cursor_allocation(config); |
2947 | cursor_blocks = skl_cursor_allocation(config); |
2921 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; |
2948 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; |
2922 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; |
2949 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; |
2923 | 2950 | ||
2924 | alloc_size -= cursor_blocks; |
2951 | alloc_size -= cursor_blocks; |
2925 | alloc->end -= cursor_blocks; |
2952 | alloc->end -= cursor_blocks; |
2926 | 2953 | ||
2927 | /* 1. Allocate the mininum required blocks for each active plane */ |
2954 | /* 1. Allocate the mininum required blocks for each active plane */ |
2928 | for_each_plane(dev_priv, pipe, plane) { |
2955 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
- | 2956 | struct drm_plane *plane = &intel_plane->base; |
|
- | 2957 | struct drm_framebuffer *fb = plane->state->fb; |
|
2929 | const struct intel_plane_wm_parameters *p; |
2958 | int id = skl_wm_plane_id(intel_plane); |
2930 | 2959 | ||
2931 | p = ¶ms->plane[plane]; |
2960 | if (fb == NULL) |
- | 2961 | continue; |
|
2932 | if (!p->enabled) |
2962 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
2933 | continue; |
2963 | continue; |
2934 | 2964 | ||
2935 | minimum[plane] = 8; |
2965 | minimum[id] = 8; |
2936 | alloc_size -= minimum[plane]; |
2966 | alloc_size -= minimum[id]; |
2937 | y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; |
2967 | y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0; |
2938 | alloc_size -= y_minimum[plane]; |
2968 | alloc_size -= y_minimum[id]; |
2939 | } |
2969 | } |
2940 | 2970 | ||
2941 | /* |
2971 | /* |
2942 | * 2. Distribute the remaining space in proportion to the amount of |
2972 | * 2. Distribute the remaining space in proportion to the amount of |
2943 | * data each plane needs to fetch from memory. |
2973 | * data each plane needs to fetch from memory. |
2944 | * |
2974 | * |
2945 | * FIXME: we may not allocate every single block here. |
2975 | * FIXME: we may not allocate every single block here. |
2946 | */ |
2976 | */ |
2947 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); |
2977 | total_data_rate = skl_get_total_relative_data_rate(cstate); |
2948 | 2978 | ||
2949 | start = alloc->start; |
2979 | start = alloc->start; |
2950 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2980 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
- | 2981 | struct drm_plane *plane = &intel_plane->base; |
|
2951 | const struct intel_plane_wm_parameters *p; |
2982 | struct drm_plane_state *pstate = intel_plane->base.state; |
2952 | unsigned int data_rate, y_data_rate; |
2983 | unsigned int data_rate, y_data_rate; |
- | 2984 | uint16_t plane_blocks, y_plane_blocks = 0; |
|
2953 | uint16_t plane_blocks, y_plane_blocks = 0; |
2985 | int id = skl_wm_plane_id(intel_plane); |
2954 | 2986 | ||
- | 2987 | if (pstate->fb == NULL) |
|
2955 | p = ¶ms->plane[plane]; |
2988 | continue; |
2956 | if (!p->enabled) |
2989 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
2957 | continue; |
2990 | continue; |
2958 | 2991 | ||
2959 | data_rate = skl_plane_relative_data_rate(p, 0); |
2992 | data_rate = skl_plane_relative_data_rate(cstate, pstate, 0); |
2960 | 2993 | ||
2961 | /* |
2994 | /* |
2962 | * allocation for (packed formats) or (uv-plane part of planar format): |
2995 | * allocation for (packed formats) or (uv-plane part of planar format): |
2963 | * promote the expression to 64 bits to avoid overflowing, the |
2996 | * promote the expression to 64 bits to avoid overflowing, the |
2964 | * result is < available as data_rate / total_data_rate < 1 |
2997 | * result is < available as data_rate / total_data_rate < 1 |
2965 | */ |
2998 | */ |
2966 | plane_blocks = minimum[plane]; |
2999 | plane_blocks = minimum[id]; |
2967 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
3000 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
2968 | total_data_rate); |
3001 | total_data_rate); |
2969 | 3002 | ||
2970 | ddb->plane[pipe][plane].start = start; |
3003 | ddb->plane[pipe][id].start = start; |
2971 | ddb->plane[pipe][plane].end = start + plane_blocks; |
3004 | ddb->plane[pipe][id].end = start + plane_blocks; |
2972 | 3005 | ||
2973 | start += plane_blocks; |
3006 | start += plane_blocks; |
2974 | 3007 | ||
2975 | /* |
3008 | /* |
2976 | * allocation for y_plane part of planar format: |
3009 | * allocation for y_plane part of planar format: |
2977 | */ |
3010 | */ |
2978 | if (p->y_bytes_per_pixel) { |
3011 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) { |
2979 | y_data_rate = skl_plane_relative_data_rate(p, 1); |
3012 | y_data_rate = skl_plane_relative_data_rate(cstate, |
- | 3013 | pstate, |
|
- | 3014 | 1); |
|
2980 | y_plane_blocks = y_minimum[plane]; |
3015 | y_plane_blocks = y_minimum[id]; |
2981 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
3016 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
2982 | total_data_rate); |
3017 | total_data_rate); |
2983 | 3018 | ||
2984 | ddb->y_plane[pipe][plane].start = start; |
3019 | ddb->y_plane[pipe][id].start = start; |
2985 | ddb->y_plane[pipe][plane].end = start + y_plane_blocks; |
3020 | ddb->y_plane[pipe][id].end = start + y_plane_blocks; |
2986 | 3021 | ||
2987 | start += y_plane_blocks; |
3022 | start += y_plane_blocks; |
2988 | } |
3023 | } |
2989 | 3024 | ||
2990 | } |
3025 | } |
2991 | 3026 | ||
2992 | } |
3027 | } |
2993 | 3028 | ||
2994 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
3029 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2995 | { |
3030 | { |
2996 | /* TODO: Take into account the scalers once we support them */ |
3031 | /* TODO: Take into account the scalers once we support them */ |
2997 | return config->base.adjusted_mode.crtc_clock; |
3032 | return config->base.adjusted_mode.crtc_clock; |
2998 | } |
3033 | } |
2999 | 3034 | ||
3000 | /* |
3035 | /* |
3001 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
3036 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
3002 | * for the read latency) and bytes_per_pixel should always be <= 8, so that |
3037 | * for the read latency) and bytes_per_pixel should always be <= 8, so that |
3003 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3038 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3004 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
3039 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
3005 | */ |
3040 | */ |
3006 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
3041 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
3007 | uint32_t latency) |
3042 | uint32_t latency) |
3008 | { |
3043 | { |
3009 | uint32_t wm_intermediate_val, ret; |
3044 | uint32_t wm_intermediate_val, ret; |
3010 | 3045 | ||
3011 | if (latency == 0) |
3046 | if (latency == 0) |
3012 | return UINT_MAX; |
3047 | return UINT_MAX; |
3013 | 3048 | ||
3014 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
3049 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
3015 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3050 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3016 | 3051 | ||
3017 | return ret; |
3052 | return ret; |
3018 | } |
3053 | } |
3019 | 3054 | ||
3020 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
3055 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
3021 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
3056 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
3022 | uint64_t tiling, uint32_t latency) |
3057 | uint64_t tiling, uint32_t latency) |
3023 | { |
3058 | { |
3024 | uint32_t ret; |
3059 | uint32_t ret; |
3025 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3060 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3026 | uint32_t wm_intermediate_val; |
3061 | uint32_t wm_intermediate_val; |
3027 | 3062 | ||
3028 | if (latency == 0) |
3063 | if (latency == 0) |
3029 | return UINT_MAX; |
3064 | return UINT_MAX; |
3030 | 3065 | ||
3031 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; |
3066 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; |
3032 | 3067 | ||
3033 | if (tiling == I915_FORMAT_MOD_Y_TILED || |
3068 | if (tiling == I915_FORMAT_MOD_Y_TILED || |
3034 | tiling == I915_FORMAT_MOD_Yf_TILED) { |
3069 | tiling == I915_FORMAT_MOD_Yf_TILED) { |
3035 | plane_bytes_per_line *= 4; |
3070 | plane_bytes_per_line *= 4; |
3036 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3071 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3037 | plane_blocks_per_line /= 4; |
3072 | plane_blocks_per_line /= 4; |
3038 | } else { |
3073 | } else { |
3039 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3074 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3040 | } |
3075 | } |
3041 | 3076 | ||
3042 | wm_intermediate_val = latency * pixel_rate; |
3077 | wm_intermediate_val = latency * pixel_rate; |
3043 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * |
3078 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * |
3044 | plane_blocks_per_line; |
3079 | plane_blocks_per_line; |
3045 | 3080 | ||
3046 | return ret; |
3081 | return ret; |
3047 | } |
3082 | } |
3048 | 3083 | ||
3049 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
3084 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
3050 | const struct intel_crtc *intel_crtc) |
3085 | const struct intel_crtc *intel_crtc) |
3051 | { |
3086 | { |
3052 | struct drm_device *dev = intel_crtc->base.dev; |
3087 | struct drm_device *dev = intel_crtc->base.dev; |
3053 | struct drm_i915_private *dev_priv = dev->dev_private; |
3088 | struct drm_i915_private *dev_priv = dev->dev_private; |
3054 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; |
3089 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; |
3055 | enum pipe pipe = intel_crtc->pipe; |
- | |
- | 3090 | ||
3056 | 3091 | /* |
|
3057 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], |
- | |
3058 | sizeof(new_ddb->plane[pipe]))) |
3092 | * If ddb allocation of pipes changed, it may require recalculation of |
3059 | return true; |
3093 | * watermarks |
3060 | 3094 | */ |
|
3061 | if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], |
- | |
3062 | sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) |
3095 | if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe))) |
3063 | return true; |
3096 | return true; |
3064 | 3097 | ||
3065 | return false; |
3098 | return false; |
3066 | } |
3099 | } |
3067 | - | ||
3068 | static void skl_compute_wm_global_parameters(struct drm_device *dev, |
- | |
3069 | struct intel_wm_config *config) |
- | |
3070 | { |
- | |
3071 | struct drm_crtc *crtc; |
- | |
3072 | struct drm_plane *plane; |
- | |
3073 | - | ||
3074 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
- | |
3075 | config->num_pipes_active += to_intel_crtc(crtc)->active; |
- | |
3076 | - | ||
3077 | /* FIXME: I don't think we need those two global parameters on SKL */ |
- | |
3078 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
- | |
3079 | struct intel_plane *intel_plane = to_intel_plane(plane); |
- | |
3080 | - | ||
3081 | config->sprites_enabled |= intel_plane->wm.enabled; |
- | |
3082 | config->sprites_scaled |= intel_plane->wm.scaled; |
- | |
3083 | } |
- | |
3084 | } |
- | |
3085 | - | ||
3086 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, |
- | |
3087 | struct skl_pipe_wm_parameters *p) |
- | |
3088 | { |
- | |
3089 | struct drm_device *dev = crtc->dev; |
- | |
3090 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3091 | enum pipe pipe = intel_crtc->pipe; |
- | |
3092 | struct drm_plane *plane; |
- | |
3093 | struct drm_framebuffer *fb; |
- | |
3094 | int i = 1; /* Index for sprite planes start */ |
- | |
3095 | - | ||
3096 | p->active = intel_crtc->active; |
- | |
3097 | if (p->active) { |
- | |
3098 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
- | |
3099 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); |
- | |
3100 | - | ||
3101 | fb = crtc->primary->state->fb; |
- | |
3102 | /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ |
- | |
3103 | if (fb) { |
- | |
3104 | p->plane[0].enabled = true; |
- | |
3105 | p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? |
- | |
3106 | drm_format_plane_cpp(fb->pixel_format, 1) : |
- | |
3107 | drm_format_plane_cpp(fb->pixel_format, 0); |
- | |
3108 | p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? |
- | |
3109 | drm_format_plane_cpp(fb->pixel_format, 0) : 0; |
- | |
3110 | p->plane[0].tiling = fb->modifier[0]; |
- | |
3111 | } else { |
- | |
3112 | p->plane[0].enabled = false; |
- | |
3113 | p->plane[0].bytes_per_pixel = 0; |
- | |
3114 | p->plane[0].y_bytes_per_pixel = 0; |
- | |
3115 | p->plane[0].tiling = DRM_FORMAT_MOD_NONE; |
- | |
3116 | } |
- | |
3117 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; |
- | |
3118 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; |
- | |
3119 | p->plane[0].rotation = crtc->primary->state->rotation; |
- | |
3120 | - | ||
3121 | fb = crtc->cursor->state->fb; |
- | |
3122 | p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; |
- | |
3123 | if (fb) { |
- | |
3124 | p->plane[PLANE_CURSOR].enabled = true; |
- | |
3125 | p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; |
- | |
3126 | p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; |
- | |
3127 | p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; |
- | |
3128 | } else { |
- | |
3129 | p->plane[PLANE_CURSOR].enabled = false; |
- | |
3130 | p->plane[PLANE_CURSOR].bytes_per_pixel = 0; |
- | |
3131 | p->plane[PLANE_CURSOR].horiz_pixels = 64; |
- | |
3132 | p->plane[PLANE_CURSOR].vert_pixels = 64; |
- | |
3133 | } |
- | |
3134 | } |
- | |
3135 | - | ||
3136 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
- | |
3137 | struct intel_plane *intel_plane = to_intel_plane(plane); |
- | |
3138 | - | ||
3139 | if (intel_plane->pipe == pipe && |
- | |
3140 | plane->type == DRM_PLANE_TYPE_OVERLAY) |
- | |
3141 | p->plane[i++] = intel_plane->wm; |
- | |
3142 | } |
- | |
3143 | } |
- | |
3144 | 3100 | ||
3145 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
3101 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
3146 | struct skl_pipe_wm_parameters *p, |
3102 | struct intel_crtc_state *cstate, |
3147 | struct intel_plane_wm_parameters *p_params, |
3103 | struct intel_plane *intel_plane, |
3148 | uint16_t ddb_allocation, |
3104 | uint16_t ddb_allocation, |
3149 | int level, |
3105 | int level, |
3150 | uint16_t *out_blocks, /* out */ |
3106 | uint16_t *out_blocks, /* out */ |
3151 | uint8_t *out_lines /* out */) |
3107 | uint8_t *out_lines /* out */) |
3152 | { |
3108 | { |
- | 3109 | struct drm_plane *plane = &intel_plane->base; |
|
- | 3110 | struct drm_framebuffer *fb = plane->state->fb; |
|
3153 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3111 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3154 | uint32_t method1, method2; |
3112 | uint32_t method1, method2; |
3155 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3113 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3156 | uint32_t res_blocks, res_lines; |
3114 | uint32_t res_blocks, res_lines; |
3157 | uint32_t selected_result; |
3115 | uint32_t selected_result; |
3158 | uint8_t bytes_per_pixel; |
3116 | uint8_t bytes_per_pixel; |
3159 | 3117 | ||
3160 | if (latency == 0 || !p->active || !p_params->enabled) |
3118 | if (latency == 0 || !cstate->base.active || !fb) |
3161 | return false; |
3119 | return false; |
3162 | - | ||
3163 | bytes_per_pixel = p_params->y_bytes_per_pixel ? |
- | |
3164 | p_params->y_bytes_per_pixel : |
3120 | |
3165 | p_params->bytes_per_pixel; |
3121 | bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0); |
3166 | method1 = skl_wm_method1(p->pixel_rate, |
3122 | method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), |
3167 | bytes_per_pixel, |
3123 | bytes_per_pixel, |
3168 | latency); |
3124 | latency); |
3169 | method2 = skl_wm_method2(p->pixel_rate, |
3125 | method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), |
3170 | p->pipe_htotal, |
3126 | cstate->base.adjusted_mode.crtc_htotal, |
3171 | p_params->horiz_pixels, |
3127 | cstate->pipe_src_w, |
3172 | bytes_per_pixel, |
3128 | bytes_per_pixel, |
3173 | p_params->tiling, |
3129 | fb->modifier[0], |
3174 | latency); |
3130 | latency); |
3175 | 3131 | ||
3176 | plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; |
3132 | plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel; |
3177 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3133 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3178 | 3134 | ||
3179 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
3135 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
- | 3136 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { |
|
- | 3137 | uint32_t min_scanlines = 4; |
|
- | 3138 | uint32_t y_tile_minimum; |
|
- | 3139 | if (intel_rotation_90_or_270(plane->state->rotation)) { |
|
3180 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { |
3140 | int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ? |
3181 | uint32_t min_scanlines = 4; |
3141 | drm_format_plane_cpp(fb->pixel_format, 1) : |
3182 | uint32_t y_tile_minimum; |
3142 | drm_format_plane_cpp(fb->pixel_format, 0); |
3183 | if (intel_rotation_90_or_270(p_params->rotation)) { |
3143 | |
3184 | switch (p_params->bytes_per_pixel) { |
3144 | switch (bpp) { |
3185 | case 1: |
3145 | case 1: |
3186 | min_scanlines = 16; |
3146 | min_scanlines = 16; |
3187 | break; |
3147 | break; |
3188 | case 2: |
3148 | case 2: |
3189 | min_scanlines = 8; |
3149 | min_scanlines = 8; |
3190 | break; |
3150 | break; |
3191 | case 8: |
3151 | case 8: |
3192 | WARN(1, "Unsupported pixel depth for rotation"); |
3152 | WARN(1, "Unsupported pixel depth for rotation"); |
3193 | } |
3153 | } |
3194 | } |
3154 | } |
3195 | y_tile_minimum = plane_blocks_per_line * min_scanlines; |
3155 | y_tile_minimum = plane_blocks_per_line * min_scanlines; |
3196 | selected_result = max(method2, y_tile_minimum); |
3156 | selected_result = max(method2, y_tile_minimum); |
3197 | } else { |
3157 | } else { |
3198 | if ((ddb_allocation / plane_blocks_per_line) >= 1) |
3158 | if ((ddb_allocation / plane_blocks_per_line) >= 1) |
3199 | selected_result = min(method1, method2); |
3159 | selected_result = min(method1, method2); |
3200 | else |
3160 | else |
3201 | selected_result = method1; |
3161 | selected_result = method1; |
3202 | } |
3162 | } |
3203 | 3163 | ||
3204 | res_blocks = selected_result + 1; |
3164 | res_blocks = selected_result + 1; |
3205 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); |
3165 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); |
3206 | 3166 | ||
3207 | if (level >= 1 && level <= 7) { |
3167 | if (level >= 1 && level <= 7) { |
3208 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
3168 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
3209 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) |
3169 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) |
3210 | res_lines += 4; |
3170 | res_lines += 4; |
3211 | else |
3171 | else |
3212 | res_blocks++; |
3172 | res_blocks++; |
3213 | } |
3173 | } |
3214 | 3174 | ||
3215 | if (res_blocks >= ddb_allocation || res_lines > 31) |
3175 | if (res_blocks >= ddb_allocation || res_lines > 31) |
3216 | return false; |
3176 | return false; |
3217 | 3177 | ||
3218 | *out_blocks = res_blocks; |
3178 | *out_blocks = res_blocks; |
3219 | *out_lines = res_lines; |
3179 | *out_lines = res_lines; |
3220 | 3180 | ||
3221 | return true; |
3181 | return true; |
3222 | } |
3182 | } |
3223 | 3183 | ||
3224 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, |
3184 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, |
3225 | struct skl_ddb_allocation *ddb, |
3185 | struct skl_ddb_allocation *ddb, |
3226 | struct skl_pipe_wm_parameters *p, |
3186 | struct intel_crtc_state *cstate, |
3227 | enum pipe pipe, |
- | |
3228 | int level, |
3187 | int level, |
3229 | int num_planes, |
- | |
3230 | struct skl_wm_level *result) |
3188 | struct skl_wm_level *result) |
3231 | { |
3189 | { |
- | 3190 | struct drm_device *dev = dev_priv->dev; |
|
- | 3191 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
|
- | 3192 | struct intel_plane *intel_plane; |
|
3232 | uint16_t ddb_blocks; |
3193 | uint16_t ddb_blocks; |
3233 | int i; |
3194 | enum pipe pipe = intel_crtc->pipe; |
- | 3195 | ||
- | 3196 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
|
- | 3197 | int i = skl_wm_plane_id(intel_plane); |
|
3234 | - | ||
3235 | for (i = 0; i < num_planes; i++) { |
3198 | |
3236 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
3199 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
3237 | 3200 | ||
3238 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
3201 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
- | 3202 | cstate, |
|
3239 | p, &p->plane[i], |
3203 | intel_plane, |
3240 | ddb_blocks, |
3204 | ddb_blocks, |
3241 | level, |
3205 | level, |
3242 | &result->plane_res_b[i], |
3206 | &result->plane_res_b[i], |
3243 | &result->plane_res_l[i]); |
3207 | &result->plane_res_l[i]); |
3244 | } |
3208 | } |
3245 | - | ||
3246 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); |
- | |
3247 | result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, |
- | |
3248 | &p->plane[PLANE_CURSOR], |
- | |
3249 | ddb_blocks, level, |
- | |
3250 | &result->plane_res_b[PLANE_CURSOR], |
- | |
3251 | &result->plane_res_l[PLANE_CURSOR]); |
- | |
3252 | } |
3209 | } |
3253 | 3210 | ||
3254 | static uint32_t |
3211 | static uint32_t |
3255 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) |
3212 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
3256 | { |
3213 | { |
3257 | if (!to_intel_crtc(crtc)->active) |
3214 | if (!cstate->base.active) |
3258 | return 0; |
3215 | return 0; |
3259 | 3216 | ||
3260 | if (WARN_ON(p->pixel_rate == 0)) |
3217 | if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) |
3261 | return 0; |
3218 | return 0; |
- | 3219 | ||
3262 | 3220 | return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, |
|
3263 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); |
3221 | skl_pipe_pixel_rate(cstate)); |
3264 | } |
- | |
3265 | 3222 | } |
|
3266 | static void skl_compute_transition_wm(struct drm_crtc *crtc, |
3223 | |
- | 3224 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
|
3267 | struct skl_pipe_wm_parameters *params, |
3225 | struct skl_wm_level *trans_wm /* out */) |
3268 | struct skl_wm_level *trans_wm /* out */) |
3226 | { |
3269 | { |
3227 | struct drm_crtc *crtc = cstate->base.crtc; |
3270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3271 | int i; |
3229 | struct intel_plane *intel_plane; |
3272 | 3230 | ||
3273 | if (!params->active) |
3231 | if (!cstate->base.active) |
3274 | return; |
3232 | return; |
3275 | 3233 | ||
3276 | /* Until we know more, just disable transition WMs */ |
3234 | /* Until we know more, just disable transition WMs */ |
- | 3235 | for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { |
|
3277 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
3236 | int i = skl_wm_plane_id(intel_plane); |
- | 3237 | ||
3278 | trans_wm->plane_en[i] = false; |
3238 | trans_wm->plane_en[i] = false; |
3279 | trans_wm->plane_en[PLANE_CURSOR] = false; |
- | |
- | 3239 | } |
|
3280 | } |
3240 | } |
3281 | 3241 | ||
3282 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
3242 | static void skl_compute_pipe_wm(struct intel_crtc_state *cstate, |
3283 | struct skl_ddb_allocation *ddb, |
- | |
3284 | struct skl_pipe_wm_parameters *params, |
3243 | struct skl_ddb_allocation *ddb, |
3285 | struct skl_pipe_wm *pipe_wm) |
3244 | struct skl_pipe_wm *pipe_wm) |
3286 | { |
3245 | { |
3287 | struct drm_device *dev = crtc->dev; |
3246 | struct drm_device *dev = cstate->base.crtc->dev; |
3288 | const struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3289 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3247 | const struct drm_i915_private *dev_priv = dev->dev_private; |
3290 | int level, max_level = ilk_wm_max_level(dev); |
3248 | int level, max_level = ilk_wm_max_level(dev); |
3291 | 3249 | ||
3292 | for (level = 0; level <= max_level; level++) { |
3250 | for (level = 0; level <= max_level; level++) { |
3293 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, |
3251 | skl_compute_wm_level(dev_priv, ddb, cstate, |
3294 | level, intel_num_planes(intel_crtc), |
- | |
3295 | &pipe_wm->wm[level]); |
3252 | level, &pipe_wm->wm[level]); |
3296 | } |
3253 | } |
3297 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); |
3254 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
3298 | 3255 | ||
3299 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
3256 | skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); |
3300 | } |
3257 | } |
3301 | 3258 | ||
3302 | static void skl_compute_wm_results(struct drm_device *dev, |
3259 | static void skl_compute_wm_results(struct drm_device *dev, |
3303 | struct skl_pipe_wm_parameters *p, |
- | |
3304 | struct skl_pipe_wm *p_wm, |
3260 | struct skl_pipe_wm *p_wm, |
3305 | struct skl_wm_values *r, |
3261 | struct skl_wm_values *r, |
3306 | struct intel_crtc *intel_crtc) |
3262 | struct intel_crtc *intel_crtc) |
3307 | { |
3263 | { |
3308 | int level, max_level = ilk_wm_max_level(dev); |
3264 | int level, max_level = ilk_wm_max_level(dev); |
3309 | enum pipe pipe = intel_crtc->pipe; |
3265 | enum pipe pipe = intel_crtc->pipe; |
3310 | uint32_t temp; |
3266 | uint32_t temp; |
3311 | int i; |
3267 | int i; |
3312 | 3268 | ||
3313 | for (level = 0; level <= max_level; level++) { |
3269 | for (level = 0; level <= max_level; level++) { |
3314 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3270 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3315 | temp = 0; |
3271 | temp = 0; |
3316 | 3272 | ||
3317 | temp |= p_wm->wm[level].plane_res_l[i] << |
3273 | temp |= p_wm->wm[level].plane_res_l[i] << |
3318 | PLANE_WM_LINES_SHIFT; |
3274 | PLANE_WM_LINES_SHIFT; |
3319 | temp |= p_wm->wm[level].plane_res_b[i]; |
3275 | temp |= p_wm->wm[level].plane_res_b[i]; |
3320 | if (p_wm->wm[level].plane_en[i]) |
3276 | if (p_wm->wm[level].plane_en[i]) |
3321 | temp |= PLANE_WM_EN; |
3277 | temp |= PLANE_WM_EN; |
3322 | 3278 | ||
3323 | r->plane[pipe][i][level] = temp; |
3279 | r->plane[pipe][i][level] = temp; |
3324 | } |
3280 | } |
3325 | 3281 | ||
3326 | temp = 0; |
3282 | temp = 0; |
3327 | 3283 | ||
3328 | temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3284 | temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3329 | temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; |
3285 | temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; |
3330 | 3286 | ||
3331 | if (p_wm->wm[level].plane_en[PLANE_CURSOR]) |
3287 | if (p_wm->wm[level].plane_en[PLANE_CURSOR]) |
3332 | temp |= PLANE_WM_EN; |
3288 | temp |= PLANE_WM_EN; |
3333 | 3289 | ||
3334 | r->plane[pipe][PLANE_CURSOR][level] = temp; |
3290 | r->plane[pipe][PLANE_CURSOR][level] = temp; |
3335 | 3291 | ||
3336 | } |
3292 | } |
3337 | 3293 | ||
3338 | /* transition WMs */ |
3294 | /* transition WMs */ |
3339 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3295 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3340 | temp = 0; |
3296 | temp = 0; |
3341 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; |
3297 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; |
3342 | temp |= p_wm->trans_wm.plane_res_b[i]; |
3298 | temp |= p_wm->trans_wm.plane_res_b[i]; |
3343 | if (p_wm->trans_wm.plane_en[i]) |
3299 | if (p_wm->trans_wm.plane_en[i]) |
3344 | temp |= PLANE_WM_EN; |
3300 | temp |= PLANE_WM_EN; |
3345 | 3301 | ||
3346 | r->plane_trans[pipe][i] = temp; |
3302 | r->plane_trans[pipe][i] = temp; |
3347 | } |
3303 | } |
3348 | 3304 | ||
3349 | temp = 0; |
3305 | temp = 0; |
3350 | temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3306 | temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3351 | temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; |
3307 | temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; |
3352 | if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) |
3308 | if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) |
3353 | temp |= PLANE_WM_EN; |
3309 | temp |= PLANE_WM_EN; |
3354 | 3310 | ||
3355 | r->plane_trans[pipe][PLANE_CURSOR] = temp; |
3311 | r->plane_trans[pipe][PLANE_CURSOR] = temp; |
3356 | 3312 | ||
3357 | r->wm_linetime[pipe] = p_wm->linetime; |
3313 | r->wm_linetime[pipe] = p_wm->linetime; |
3358 | } |
3314 | } |
3359 | 3315 | ||
- | 3316 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, |
|
3360 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
3317 | i915_reg_t reg, |
3361 | const struct skl_ddb_entry *entry) |
3318 | const struct skl_ddb_entry *entry) |
3362 | { |
3319 | { |
3363 | if (entry->end) |
3320 | if (entry->end) |
3364 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); |
3321 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); |
3365 | else |
3322 | else |
3366 | I915_WRITE(reg, 0); |
3323 | I915_WRITE(reg, 0); |
3367 | } |
3324 | } |
3368 | 3325 | ||
3369 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3326 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3370 | const struct skl_wm_values *new) |
3327 | const struct skl_wm_values *new) |
3371 | { |
3328 | { |
3372 | struct drm_device *dev = dev_priv->dev; |
3329 | struct drm_device *dev = dev_priv->dev; |
3373 | struct intel_crtc *crtc; |
3330 | struct intel_crtc *crtc; |
3374 | 3331 | ||
3375 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
3332 | for_each_intel_crtc(dev, crtc) { |
3376 | int i, level, max_level = ilk_wm_max_level(dev); |
3333 | int i, level, max_level = ilk_wm_max_level(dev); |
3377 | enum pipe pipe = crtc->pipe; |
3334 | enum pipe pipe = crtc->pipe; |
3378 | 3335 | ||
3379 | if (!new->dirty[pipe]) |
3336 | if (!new->dirty[pipe]) |
3380 | continue; |
3337 | continue; |
3381 | 3338 | ||
3382 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
3339 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
3383 | 3340 | ||
3384 | for (level = 0; level <= max_level; level++) { |
3341 | for (level = 0; level <= max_level; level++) { |
3385 | for (i = 0; i < intel_num_planes(crtc); i++) |
3342 | for (i = 0; i < intel_num_planes(crtc); i++) |
3386 | I915_WRITE(PLANE_WM(pipe, i, level), |
3343 | I915_WRITE(PLANE_WM(pipe, i, level), |
3387 | new->plane[pipe][i][level]); |
3344 | new->plane[pipe][i][level]); |
3388 | I915_WRITE(CUR_WM(pipe, level), |
3345 | I915_WRITE(CUR_WM(pipe, level), |
3389 | new->plane[pipe][PLANE_CURSOR][level]); |
3346 | new->plane[pipe][PLANE_CURSOR][level]); |
3390 | } |
3347 | } |
3391 | for (i = 0; i < intel_num_planes(crtc); i++) |
3348 | for (i = 0; i < intel_num_planes(crtc); i++) |
3392 | I915_WRITE(PLANE_WM_TRANS(pipe, i), |
3349 | I915_WRITE(PLANE_WM_TRANS(pipe, i), |
3393 | new->plane_trans[pipe][i]); |
3350 | new->plane_trans[pipe][i]); |
3394 | I915_WRITE(CUR_WM_TRANS(pipe), |
3351 | I915_WRITE(CUR_WM_TRANS(pipe), |
3395 | new->plane_trans[pipe][PLANE_CURSOR]); |
3352 | new->plane_trans[pipe][PLANE_CURSOR]); |
3396 | 3353 | ||
3397 | for (i = 0; i < intel_num_planes(crtc); i++) { |
3354 | for (i = 0; i < intel_num_planes(crtc); i++) { |
3398 | skl_ddb_entry_write(dev_priv, |
3355 | skl_ddb_entry_write(dev_priv, |
3399 | PLANE_BUF_CFG(pipe, i), |
3356 | PLANE_BUF_CFG(pipe, i), |
3400 | &new->ddb.plane[pipe][i]); |
3357 | &new->ddb.plane[pipe][i]); |
3401 | skl_ddb_entry_write(dev_priv, |
3358 | skl_ddb_entry_write(dev_priv, |
3402 | PLANE_NV12_BUF_CFG(pipe, i), |
3359 | PLANE_NV12_BUF_CFG(pipe, i), |
3403 | &new->ddb.y_plane[pipe][i]); |
3360 | &new->ddb.y_plane[pipe][i]); |
3404 | } |
3361 | } |
3405 | 3362 | ||
3406 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
3363 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
3407 | &new->ddb.plane[pipe][PLANE_CURSOR]); |
3364 | &new->ddb.plane[pipe][PLANE_CURSOR]); |
3408 | } |
3365 | } |
3409 | } |
3366 | } |
3410 | 3367 | ||
3411 | /* |
3368 | /* |
3412 | * When setting up a new DDB allocation arrangement, we need to correctly |
3369 | * When setting up a new DDB allocation arrangement, we need to correctly |
3413 | * sequence the times at which the new allocations for the pipes are taken into |
3370 | * sequence the times at which the new allocations for the pipes are taken into |
3414 | * account or we'll have pipes fetching from space previously allocated to |
3371 | * account or we'll have pipes fetching from space previously allocated to |
3415 | * another pipe. |
3372 | * another pipe. |
3416 | * |
3373 | * |
3417 | * Roughly the sequence looks like: |
3374 | * Roughly the sequence looks like: |
3418 | * 1. re-allocate the pipe(s) with the allocation being reduced and not |
3375 | * 1. re-allocate the pipe(s) with the allocation being reduced and not |
3419 | * overlapping with a previous light-up pipe (another way to put it is: |
3376 | * overlapping with a previous light-up pipe (another way to put it is: |
3420 | * pipes with their new allocation strickly included into their old ones). |
3377 | * pipes with their new allocation strickly included into their old ones). |
3421 | * 2. re-allocate the other pipes that get their allocation reduced |
3378 | * 2. re-allocate the other pipes that get their allocation reduced |
3422 | * 3. allocate the pipes having their allocation increased |
3379 | * 3. allocate the pipes having their allocation increased |
3423 | * |
3380 | * |
3424 | * Steps 1. and 2. are here to take care of the following case: |
3381 | * Steps 1. and 2. are here to take care of the following case: |
3425 | * - Initially DDB looks like this: |
3382 | * - Initially DDB looks like this: |
3426 | * | B | C | |
3383 | * | B | C | |
3427 | * - enable pipe A. |
3384 | * - enable pipe A. |
3428 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C |
3385 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C |
3429 | * allocation |
3386 | * allocation |
3430 | * | A | B | C | |
3387 | * | A | B | C | |
3431 | * |
3388 | * |
3432 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). |
3389 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). |
3433 | */ |
3390 | */ |
3434 | 3391 | ||
3435 | static void |
3392 | static void |
3436 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) |
3393 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) |
3437 | { |
3394 | { |
3438 | int plane; |
3395 | int plane; |
3439 | 3396 | ||
3440 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3397 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3441 | 3398 | ||
3442 | for_each_plane(dev_priv, pipe, plane) { |
3399 | for_each_plane(dev_priv, pipe, plane) { |
3443 | I915_WRITE(PLANE_SURF(pipe, plane), |
3400 | I915_WRITE(PLANE_SURF(pipe, plane), |
3444 | I915_READ(PLANE_SURF(pipe, plane))); |
3401 | I915_READ(PLANE_SURF(pipe, plane))); |
3445 | } |
3402 | } |
3446 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3403 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3447 | } |
3404 | } |
3448 | 3405 | ||
3449 | static bool |
3406 | static bool |
3450 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, |
3407 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, |
3451 | const struct skl_ddb_allocation *new, |
3408 | const struct skl_ddb_allocation *new, |
3452 | enum pipe pipe) |
3409 | enum pipe pipe) |
3453 | { |
3410 | { |
3454 | uint16_t old_size, new_size; |
3411 | uint16_t old_size, new_size; |
3455 | 3412 | ||
3456 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); |
3413 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); |
3457 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); |
3414 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); |
3458 | 3415 | ||
3459 | return old_size != new_size && |
3416 | return old_size != new_size && |
3460 | new->pipe[pipe].start >= old->pipe[pipe].start && |
3417 | new->pipe[pipe].start >= old->pipe[pipe].start && |
3461 | new->pipe[pipe].end <= old->pipe[pipe].end; |
3418 | new->pipe[pipe].end <= old->pipe[pipe].end; |
3462 | } |
3419 | } |
3463 | 3420 | ||
3464 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, |
3421 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, |
3465 | struct skl_wm_values *new_values) |
3422 | struct skl_wm_values *new_values) |
3466 | { |
3423 | { |
3467 | struct drm_device *dev = dev_priv->dev; |
3424 | struct drm_device *dev = dev_priv->dev; |
3468 | struct skl_ddb_allocation *cur_ddb, *new_ddb; |
3425 | struct skl_ddb_allocation *cur_ddb, *new_ddb; |
3469 | bool reallocated[I915_MAX_PIPES] = {}; |
3426 | bool reallocated[I915_MAX_PIPES] = {}; |
3470 | struct intel_crtc *crtc; |
3427 | struct intel_crtc *crtc; |
3471 | enum pipe pipe; |
3428 | enum pipe pipe; |
3472 | 3429 | ||
3473 | new_ddb = &new_values->ddb; |
3430 | new_ddb = &new_values->ddb; |
3474 | cur_ddb = &dev_priv->wm.skl_hw.ddb; |
3431 | cur_ddb = &dev_priv->wm.skl_hw.ddb; |
3475 | 3432 | ||
3476 | /* |
3433 | /* |
3477 | * First pass: flush the pipes with the new allocation contained into |
3434 | * First pass: flush the pipes with the new allocation contained into |
3478 | * the old space. |
3435 | * the old space. |
3479 | * |
3436 | * |
3480 | * We'll wait for the vblank on those pipes to ensure we can safely |
3437 | * We'll wait for the vblank on those pipes to ensure we can safely |
3481 | * re-allocate the freed space without this pipe fetching from it. |
3438 | * re-allocate the freed space without this pipe fetching from it. |
3482 | */ |
3439 | */ |
3483 | for_each_intel_crtc(dev, crtc) { |
3440 | for_each_intel_crtc(dev, crtc) { |
3484 | if (!crtc->active) |
3441 | if (!crtc->active) |
3485 | continue; |
3442 | continue; |
3486 | 3443 | ||
3487 | pipe = crtc->pipe; |
3444 | pipe = crtc->pipe; |
3488 | 3445 | ||
3489 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) |
3446 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) |
3490 | continue; |
3447 | continue; |
3491 | 3448 | ||
3492 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
3449 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
3493 | intel_wait_for_vblank(dev, pipe); |
3450 | intel_wait_for_vblank(dev, pipe); |
3494 | 3451 | ||
3495 | reallocated[pipe] = true; |
3452 | reallocated[pipe] = true; |
3496 | } |
3453 | } |
3497 | 3454 | ||
3498 | 3455 | ||
3499 | /* |
3456 | /* |
3500 | * Second pass: flush the pipes that are having their allocation |
3457 | * Second pass: flush the pipes that are having their allocation |
3501 | * reduced, but overlapping with a previous allocation. |
3458 | * reduced, but overlapping with a previous allocation. |
3502 | * |
3459 | * |
3503 | * Here as well we need to wait for the vblank to make sure the freed |
3460 | * Here as well we need to wait for the vblank to make sure the freed |
3504 | * space is not used anymore. |
3461 | * space is not used anymore. |
3505 | */ |
3462 | */ |
3506 | for_each_intel_crtc(dev, crtc) { |
3463 | for_each_intel_crtc(dev, crtc) { |
3507 | if (!crtc->active) |
3464 | if (!crtc->active) |
3508 | continue; |
3465 | continue; |
3509 | 3466 | ||
3510 | pipe = crtc->pipe; |
3467 | pipe = crtc->pipe; |
3511 | 3468 | ||
3512 | if (reallocated[pipe]) |
3469 | if (reallocated[pipe]) |
3513 | continue; |
3470 | continue; |
3514 | 3471 | ||
3515 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < |
3472 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < |
3516 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { |
3473 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { |
3517 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
3474 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
3518 | intel_wait_for_vblank(dev, pipe); |
3475 | intel_wait_for_vblank(dev, pipe); |
3519 | reallocated[pipe] = true; |
3476 | reallocated[pipe] = true; |
3520 | } |
3477 | } |
3521 | } |
3478 | } |
3522 | 3479 | ||
3523 | /* |
3480 | /* |
3524 | * Third pass: flush the pipes that got more space allocated. |
3481 | * Third pass: flush the pipes that got more space allocated. |
3525 | * |
3482 | * |
3526 | * We don't need to actively wait for the update here, next vblank |
3483 | * We don't need to actively wait for the update here, next vblank |
3527 | * will just get more DDB space with the correct WM values. |
3484 | * will just get more DDB space with the correct WM values. |
3528 | */ |
3485 | */ |
3529 | for_each_intel_crtc(dev, crtc) { |
3486 | for_each_intel_crtc(dev, crtc) { |
3530 | if (!crtc->active) |
3487 | if (!crtc->active) |
3531 | continue; |
3488 | continue; |
3532 | 3489 | ||
3533 | pipe = crtc->pipe; |
3490 | pipe = crtc->pipe; |
3534 | 3491 | ||
3535 | /* |
3492 | /* |
3536 | * At this point, only the pipes more space than before are |
3493 | * At this point, only the pipes more space than before are |
3537 | * left to re-allocate. |
3494 | * left to re-allocate. |
3538 | */ |
3495 | */ |
3539 | if (reallocated[pipe]) |
3496 | if (reallocated[pipe]) |
3540 | continue; |
3497 | continue; |
3541 | 3498 | ||
3542 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
3499 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
3543 | } |
3500 | } |
3544 | } |
3501 | } |
3545 | 3502 | ||
3546 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
3503 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
3547 | struct skl_pipe_wm_parameters *params, |
- | |
3548 | struct intel_wm_config *config, |
- | |
3549 | struct skl_ddb_allocation *ddb, /* out */ |
3504 | struct skl_ddb_allocation *ddb, /* out */ |
3550 | struct skl_pipe_wm *pipe_wm /* out */) |
3505 | struct skl_pipe_wm *pipe_wm /* out */) |
3551 | { |
3506 | { |
3552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 3508 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
|
3553 | - | ||
3554 | skl_compute_wm_pipe_parameters(crtc, params); |
3509 | |
3555 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
3510 | skl_allocate_pipe_ddb(cstate, ddb); |
3556 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
3511 | skl_compute_pipe_wm(cstate, ddb, pipe_wm); |
3557 | 3512 | ||
3558 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) |
3513 | if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm))) |
3559 | return false; |
3514 | return false; |
3560 | 3515 | ||
3561 | intel_crtc->wm.skl_active = *pipe_wm; |
3516 | intel_crtc->wm.active.skl = *pipe_wm; |
3562 | 3517 | ||
3563 | return true; |
3518 | return true; |
3564 | } |
3519 | } |
3565 | 3520 | ||
3566 | static void skl_update_other_pipe_wm(struct drm_device *dev, |
3521 | static void skl_update_other_pipe_wm(struct drm_device *dev, |
3567 | struct drm_crtc *crtc, |
3522 | struct drm_crtc *crtc, |
3568 | struct intel_wm_config *config, |
- | |
3569 | struct skl_wm_values *r) |
3523 | struct skl_wm_values *r) |
3570 | { |
3524 | { |
3571 | struct intel_crtc *intel_crtc; |
3525 | struct intel_crtc *intel_crtc; |
3572 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); |
3526 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); |
3573 | 3527 | ||
3574 | /* |
3528 | /* |
3575 | * If the WM update hasn't changed the allocation for this_crtc (the |
3529 | * If the WM update hasn't changed the allocation for this_crtc (the |
3576 | * crtc we are currently computing the new WM values for), other |
3530 | * crtc we are currently computing the new WM values for), other |
3577 | * enabled crtcs will keep the same allocation and we don't need to |
3531 | * enabled crtcs will keep the same allocation and we don't need to |
3578 | * recompute anything for them. |
3532 | * recompute anything for them. |
3579 | */ |
3533 | */ |
3580 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) |
3534 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) |
3581 | return; |
3535 | return; |
3582 | 3536 | ||
3583 | /* |
3537 | /* |
3584 | * Otherwise, because of this_crtc being freshly enabled/disabled, the |
3538 | * Otherwise, because of this_crtc being freshly enabled/disabled, the |
3585 | * other active pipes need new DDB allocation and WM values. |
3539 | * other active pipes need new DDB allocation and WM values. |
3586 | */ |
3540 | */ |
3587 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
3541 | for_each_intel_crtc(dev, intel_crtc) { |
3588 | base.head) { |
- | |
3589 | struct skl_pipe_wm_parameters params = {}; |
- | |
3590 | struct skl_pipe_wm pipe_wm = {}; |
3542 | struct skl_pipe_wm pipe_wm = {}; |
3591 | bool wm_changed; |
3543 | bool wm_changed; |
3592 | 3544 | ||
3593 | if (this_crtc->pipe == intel_crtc->pipe) |
3545 | if (this_crtc->pipe == intel_crtc->pipe) |
3594 | continue; |
3546 | continue; |
3595 | 3547 | ||
3596 | if (!intel_crtc->active) |
3548 | if (!intel_crtc->active) |
3597 | continue; |
3549 | continue; |
3598 | 3550 | ||
3599 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, |
3551 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, |
3600 | ¶ms, config, |
- | |
3601 | &r->ddb, &pipe_wm); |
3552 | &r->ddb, &pipe_wm); |
3602 | 3553 | ||
3603 | /* |
3554 | /* |
3604 | * If we end up re-computing the other pipe WM values, it's |
3555 | * If we end up re-computing the other pipe WM values, it's |
3605 | * because it was really needed, so we expect the WM values to |
3556 | * because it was really needed, so we expect the WM values to |
3606 | * be different. |
3557 | * be different. |
3607 | */ |
3558 | */ |
3608 | WARN_ON(!wm_changed); |
3559 | WARN_ON(!wm_changed); |
3609 | 3560 | ||
3610 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); |
3561 | skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc); |
3611 | r->dirty[intel_crtc->pipe] = true; |
3562 | r->dirty[intel_crtc->pipe] = true; |
3612 | } |
3563 | } |
3613 | } |
3564 | } |
3614 | 3565 | ||
3615 | static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) |
3566 | static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) |
3616 | { |
3567 | { |
3617 | watermarks->wm_linetime[pipe] = 0; |
3568 | watermarks->wm_linetime[pipe] = 0; |
3618 | memset(watermarks->plane[pipe], 0, |
3569 | memset(watermarks->plane[pipe], 0, |
3619 | sizeof(uint32_t) * 8 * I915_MAX_PLANES); |
3570 | sizeof(uint32_t) * 8 * I915_MAX_PLANES); |
3620 | memset(watermarks->plane_trans[pipe], |
3571 | memset(watermarks->plane_trans[pipe], |
3621 | 0, sizeof(uint32_t) * I915_MAX_PLANES); |
3572 | 0, sizeof(uint32_t) * I915_MAX_PLANES); |
3622 | watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; |
3573 | watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; |
3623 | 3574 | ||
3624 | /* Clear ddb entries for pipe */ |
3575 | /* Clear ddb entries for pipe */ |
3625 | memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); |
3576 | memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); |
3626 | memset(&watermarks->ddb.plane[pipe], 0, |
3577 | memset(&watermarks->ddb.plane[pipe], 0, |
3627 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
3578 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
3628 | memset(&watermarks->ddb.y_plane[pipe], 0, |
3579 | memset(&watermarks->ddb.y_plane[pipe], 0, |
3629 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
3580 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
3630 | memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, |
3581 | memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, |
3631 | sizeof(struct skl_ddb_entry)); |
3582 | sizeof(struct skl_ddb_entry)); |
3632 | 3583 | ||
3633 | } |
3584 | } |
3634 | 3585 | ||
3635 | static void skl_update_wm(struct drm_crtc *crtc) |
3586 | static void skl_update_wm(struct drm_crtc *crtc) |
3636 | { |
3587 | { |
3637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3638 | struct drm_device *dev = crtc->dev; |
3589 | struct drm_device *dev = crtc->dev; |
3639 | struct drm_i915_private *dev_priv = dev->dev_private; |
3590 | struct drm_i915_private *dev_priv = dev->dev_private; |
3640 | struct skl_pipe_wm_parameters params = {}; |
- | |
3641 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
3591 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
3642 | struct skl_pipe_wm pipe_wm = {}; |
3592 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3643 | struct intel_wm_config config = {}; |
3593 | struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl; |
3644 | 3594 | ||
3645 | 3595 | ||
3646 | /* Clear all dirty flags */ |
3596 | /* Clear all dirty flags */ |
3647 | memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); |
3597 | memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); |
3648 | 3598 | ||
3649 | skl_clear_wm(results, intel_crtc->pipe); |
3599 | skl_clear_wm(results, intel_crtc->pipe); |
3650 | - | ||
3651 | skl_compute_wm_global_parameters(dev, &config); |
- | |
3652 | 3600 | ||
3653 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, |
- | |
3654 | &results->ddb, &pipe_wm)) |
3601 | if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm)) |
3655 | return; |
3602 | return; |
3656 | 3603 | ||
3657 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); |
3604 | skl_compute_wm_results(dev, pipe_wm, results, intel_crtc); |
3658 | results->dirty[intel_crtc->pipe] = true; |
3605 | results->dirty[intel_crtc->pipe] = true; |
3659 | 3606 | ||
3660 | skl_update_other_pipe_wm(dev, crtc, &config, results); |
3607 | skl_update_other_pipe_wm(dev, crtc, results); |
3661 | skl_write_wm_values(dev_priv, results); |
3608 | skl_write_wm_values(dev_priv, results); |
3662 | skl_flush_wm_values(dev_priv, results); |
3609 | skl_flush_wm_values(dev_priv, results); |
3663 | 3610 | ||
3664 | /* store the new configuration */ |
3611 | /* store the new configuration */ |
3665 | dev_priv->wm.skl_hw = *results; |
3612 | dev_priv->wm.skl_hw = *results; |
3666 | } |
3613 | } |
3667 | - | ||
3668 | static void |
3614 | |
3669 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, |
- | |
3670 | uint32_t sprite_width, uint32_t sprite_height, |
3615 | static void ilk_compute_wm_config(struct drm_device *dev, |
3671 | int pixel_size, bool enabled, bool scaled) |
3616 | struct intel_wm_config *config) |
3672 | { |
- | |
3673 | struct intel_plane *intel_plane = to_intel_plane(plane); |
3617 | { |
3674 | struct drm_framebuffer *fb = plane->state->fb; |
- | |
3675 | - | ||
3676 | intel_plane->wm.enabled = enabled; |
- | |
3677 | intel_plane->wm.scaled = scaled; |
3618 | struct intel_crtc *crtc; |
3678 | intel_plane->wm.horiz_pixels = sprite_width; |
- | |
3679 | intel_plane->wm.vert_pixels = sprite_height; |
- | |
3680 | intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; |
- | |
3681 | 3619 | ||
3682 | /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ |
- | |
3683 | intel_plane->wm.bytes_per_pixel = |
- | |
3684 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? |
- | |
3685 | drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; |
- | |
3686 | intel_plane->wm.y_bytes_per_pixel = |
- | |
3687 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? |
- | |
3688 | drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; |
- | |
3689 | - | ||
3690 | /* |
- | |
3691 | * Framebuffer can be NULL on plane disable, but it does not |
- | |
3692 | * matter for watermarks if we assume no tiling in that case. |
- | |
3693 | */ |
3620 | /* Compute the currently _active_ config */ |
3694 | if (fb) |
- | |
3695 | intel_plane->wm.tiling = fb->modifier[0]; |
3621 | for_each_intel_crtc(dev, crtc) { |
- | 3622 | const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; |
|
- | 3623 | ||
- | 3624 | if (!wm->pipe_enabled) |
|
- | 3625 | continue; |
|
- | 3626 | ||
- | 3627 | config->sprites_enabled |= wm->sprites_enabled; |
|
3696 | intel_plane->wm.rotation = plane->state->rotation; |
3628 | config->sprites_scaled |= wm->sprites_scaled; |
3697 | 3629 | config->num_pipes_active++; |
|
3698 | skl_update_wm(crtc); |
3630 | } |
3699 | } |
- | |
3700 | - | ||
3701 | static void ilk_update_wm(struct drm_crtc *crtc) |
3631 | } |
3702 | { |
3632 | |
3703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3633 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
- | 3634 | { |
|
3704 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3635 | struct drm_device *dev = dev_priv->dev; |
3705 | struct drm_device *dev = crtc->dev; |
3636 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
3706 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3707 | struct ilk_wm_maximums max; |
- | |
3708 | struct ilk_wm_values results = {}; |
- | |
3709 | enum intel_ddb_partitioning partitioning; |
- | |
3710 | struct intel_pipe_wm pipe_wm = {}; |
- | |
3711 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
- | |
3712 | struct intel_wm_config config = {}; |
- | |
3713 | - | ||
3714 | WARN_ON(cstate->base.active != intel_crtc->active); |
- | |
3715 | - | ||
3716 | intel_compute_pipe_wm(cstate, &pipe_wm); |
- | |
3717 | - | ||
3718 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) |
3637 | struct ilk_wm_maximums max; |
3719 | return; |
3638 | struct intel_wm_config config = {}; |
3720 | 3639 | struct ilk_wm_values results = {}; |
|
3721 | intel_crtc->wm.active = pipe_wm; |
3640 | enum intel_ddb_partitioning partitioning; |
3722 | 3641 | ||
3723 | ilk_compute_wm_config(dev, &config); |
3642 | ilk_compute_wm_config(dev, &config); |
3724 | 3643 | ||
3725 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
3644 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
3726 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
3645 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
3727 | 3646 | ||
3728 | /* 5/6 split only in single pipe config on IVB+ */ |
3647 | /* 5/6 split only in single pipe config on IVB+ */ |
3729 | if (INTEL_INFO(dev)->gen >= 7 && |
3648 | if (INTEL_INFO(dev)->gen >= 7 && |
3730 | config.num_pipes_active == 1 && config.sprites_enabled) { |
3649 | config.num_pipes_active == 1 && config.sprites_enabled) { |
3731 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
3650 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
3732 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
3651 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
3733 | 3652 | ||
3734 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
3653 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
3735 | } else { |
3654 | } else { |
3736 | best_lp_wm = &lp_wm_1_2; |
3655 | best_lp_wm = &lp_wm_1_2; |
3737 | } |
3656 | } |
3738 | 3657 | ||
3739 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
3658 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
3740 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
3659 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
3741 | 3660 | ||
3742 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
3661 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
3743 | 3662 | ||
3744 | ilk_write_wm_values(dev_priv, &results); |
3663 | ilk_write_wm_values(dev_priv, &results); |
3745 | } |
3664 | } |
3746 | - | ||
3747 | static void |
3665 | |
3748 | ilk_update_sprite_wm(struct drm_plane *plane, |
- | |
3749 | struct drm_crtc *crtc, |
- | |
3750 | uint32_t sprite_width, uint32_t sprite_height, |
- | |
3751 | int pixel_size, bool enabled, bool scaled) |
3666 | static void ilk_update_wm(struct drm_crtc *crtc) |
3752 | { |
3667 | { |
3753 | struct drm_device *dev = plane->dev; |
3668 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
- | 3669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3670 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
|
- | 3671 | ||
3754 | struct intel_plane *intel_plane = to_intel_plane(plane); |
3672 | WARN_ON(cstate->base.active != intel_crtc->active); |
3755 | 3673 | ||
3756 | /* |
3674 | /* |
3757 | * IVB workaround: must disable low power watermarks for at least |
3675 | * IVB workaround: must disable low power watermarks for at least |
3758 | * one frame before enabling scaling. LP watermarks can be re-enabled |
3676 | * one frame before enabling scaling. LP watermarks can be re-enabled |
3759 | * when scaling is disabled. |
3677 | * when scaling is disabled. |
3760 | * |
3678 | * |
3761 | * WaCxSRDisabledForSpriteScaling:ivb |
3679 | * WaCxSRDisabledForSpriteScaling:ivb |
3762 | */ |
3680 | */ |
3763 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) |
3681 | if (cstate->disable_lp_wm) { |
- | 3682 | ilk_disable_lp_wm(crtc->dev); |
|
3764 | intel_wait_for_vblank(dev, intel_plane->pipe); |
3683 | intel_wait_for_vblank(crtc->dev, intel_crtc->pipe); |
- | 3684 | } |
|
- | 3685 | ||
- | 3686 | intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk; |
|
3765 | 3687 | ||
3766 | ilk_update_wm(crtc); |
3688 | ilk_program_watermarks(dev_priv); |
3767 | } |
3689 | } |
3768 | 3690 | ||
3769 | static void skl_pipe_wm_active_state(uint32_t val, |
3691 | static void skl_pipe_wm_active_state(uint32_t val, |
3770 | struct skl_pipe_wm *active, |
3692 | struct skl_pipe_wm *active, |
3771 | bool is_transwm, |
3693 | bool is_transwm, |
3772 | bool is_cursor, |
3694 | bool is_cursor, |
3773 | int i, |
3695 | int i, |
3774 | int level) |
3696 | int level) |
3775 | { |
3697 | { |
3776 | bool is_enabled = (val & PLANE_WM_EN) != 0; |
3698 | bool is_enabled = (val & PLANE_WM_EN) != 0; |
3777 | 3699 | ||
3778 | if (!is_transwm) { |
3700 | if (!is_transwm) { |
3779 | if (!is_cursor) { |
3701 | if (!is_cursor) { |
3780 | active->wm[level].plane_en[i] = is_enabled; |
3702 | active->wm[level].plane_en[i] = is_enabled; |
3781 | active->wm[level].plane_res_b[i] = |
3703 | active->wm[level].plane_res_b[i] = |
3782 | val & PLANE_WM_BLOCKS_MASK; |
3704 | val & PLANE_WM_BLOCKS_MASK; |
3783 | active->wm[level].plane_res_l[i] = |
3705 | active->wm[level].plane_res_l[i] = |
3784 | (val >> PLANE_WM_LINES_SHIFT) & |
3706 | (val >> PLANE_WM_LINES_SHIFT) & |
3785 | PLANE_WM_LINES_MASK; |
3707 | PLANE_WM_LINES_MASK; |
3786 | } else { |
3708 | } else { |
3787 | active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; |
3709 | active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; |
3788 | active->wm[level].plane_res_b[PLANE_CURSOR] = |
3710 | active->wm[level].plane_res_b[PLANE_CURSOR] = |
3789 | val & PLANE_WM_BLOCKS_MASK; |
3711 | val & PLANE_WM_BLOCKS_MASK; |
3790 | active->wm[level].plane_res_l[PLANE_CURSOR] = |
3712 | active->wm[level].plane_res_l[PLANE_CURSOR] = |
3791 | (val >> PLANE_WM_LINES_SHIFT) & |
3713 | (val >> PLANE_WM_LINES_SHIFT) & |
3792 | PLANE_WM_LINES_MASK; |
3714 | PLANE_WM_LINES_MASK; |
3793 | } |
3715 | } |
3794 | } else { |
3716 | } else { |
3795 | if (!is_cursor) { |
3717 | if (!is_cursor) { |
3796 | active->trans_wm.plane_en[i] = is_enabled; |
3718 | active->trans_wm.plane_en[i] = is_enabled; |
3797 | active->trans_wm.plane_res_b[i] = |
3719 | active->trans_wm.plane_res_b[i] = |
3798 | val & PLANE_WM_BLOCKS_MASK; |
3720 | val & PLANE_WM_BLOCKS_MASK; |
3799 | active->trans_wm.plane_res_l[i] = |
3721 | active->trans_wm.plane_res_l[i] = |
3800 | (val >> PLANE_WM_LINES_SHIFT) & |
3722 | (val >> PLANE_WM_LINES_SHIFT) & |
3801 | PLANE_WM_LINES_MASK; |
3723 | PLANE_WM_LINES_MASK; |
3802 | } else { |
3724 | } else { |
3803 | active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; |
3725 | active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; |
3804 | active->trans_wm.plane_res_b[PLANE_CURSOR] = |
3726 | active->trans_wm.plane_res_b[PLANE_CURSOR] = |
3805 | val & PLANE_WM_BLOCKS_MASK; |
3727 | val & PLANE_WM_BLOCKS_MASK; |
3806 | active->trans_wm.plane_res_l[PLANE_CURSOR] = |
3728 | active->trans_wm.plane_res_l[PLANE_CURSOR] = |
3807 | (val >> PLANE_WM_LINES_SHIFT) & |
3729 | (val >> PLANE_WM_LINES_SHIFT) & |
3808 | PLANE_WM_LINES_MASK; |
3730 | PLANE_WM_LINES_MASK; |
3809 | } |
3731 | } |
3810 | } |
3732 | } |
3811 | } |
3733 | } |
3812 | 3734 | ||
3813 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3735 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3814 | { |
3736 | { |
3815 | struct drm_device *dev = crtc->dev; |
3737 | struct drm_device *dev = crtc->dev; |
3816 | struct drm_i915_private *dev_priv = dev->dev_private; |
3738 | struct drm_i915_private *dev_priv = dev->dev_private; |
3817 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
3739 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
3818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 3741 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
|
3819 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; |
3742 | struct skl_pipe_wm *active = &cstate->wm.optimal.skl; |
3820 | enum pipe pipe = intel_crtc->pipe; |
3743 | enum pipe pipe = intel_crtc->pipe; |
3821 | int level, i, max_level; |
3744 | int level, i, max_level; |
3822 | uint32_t temp; |
3745 | uint32_t temp; |
3823 | 3746 | ||
3824 | max_level = ilk_wm_max_level(dev); |
3747 | max_level = ilk_wm_max_level(dev); |
3825 | 3748 | ||
3826 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
3749 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
3827 | 3750 | ||
3828 | for (level = 0; level <= max_level; level++) { |
3751 | for (level = 0; level <= max_level; level++) { |
3829 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
3752 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
3830 | hw->plane[pipe][i][level] = |
3753 | hw->plane[pipe][i][level] = |
3831 | I915_READ(PLANE_WM(pipe, i, level)); |
3754 | I915_READ(PLANE_WM(pipe, i, level)); |
3832 | hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); |
3755 | hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); |
3833 | } |
3756 | } |
3834 | 3757 | ||
3835 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
3758 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
3836 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); |
3759 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); |
3837 | hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); |
3760 | hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); |
3838 | 3761 | ||
3839 | if (!intel_crtc->active) |
3762 | if (!intel_crtc->active) |
3840 | return; |
3763 | return; |
3841 | 3764 | ||
3842 | hw->dirty[pipe] = true; |
3765 | hw->dirty[pipe] = true; |
3843 | 3766 | ||
3844 | active->linetime = hw->wm_linetime[pipe]; |
3767 | active->linetime = hw->wm_linetime[pipe]; |
3845 | 3768 | ||
3846 | for (level = 0; level <= max_level; level++) { |
3769 | for (level = 0; level <= max_level; level++) { |
3847 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3770 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3848 | temp = hw->plane[pipe][i][level]; |
3771 | temp = hw->plane[pipe][i][level]; |
3849 | skl_pipe_wm_active_state(temp, active, false, |
3772 | skl_pipe_wm_active_state(temp, active, false, |
3850 | false, i, level); |
3773 | false, i, level); |
3851 | } |
3774 | } |
3852 | temp = hw->plane[pipe][PLANE_CURSOR][level]; |
3775 | temp = hw->plane[pipe][PLANE_CURSOR][level]; |
3853 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
3776 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
3854 | } |
3777 | } |
3855 | 3778 | ||
3856 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3779 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3857 | temp = hw->plane_trans[pipe][i]; |
3780 | temp = hw->plane_trans[pipe][i]; |
3858 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); |
3781 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); |
3859 | } |
3782 | } |
3860 | 3783 | ||
3861 | temp = hw->plane_trans[pipe][PLANE_CURSOR]; |
3784 | temp = hw->plane_trans[pipe][PLANE_CURSOR]; |
3862 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
3785 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
- | 3786 | ||
- | 3787 | intel_crtc->wm.active.skl = *active; |
|
3863 | } |
3788 | } |
3864 | 3789 | ||
3865 | void skl_wm_get_hw_state(struct drm_device *dev) |
3790 | void skl_wm_get_hw_state(struct drm_device *dev) |
3866 | { |
3791 | { |
3867 | struct drm_i915_private *dev_priv = dev->dev_private; |
3792 | struct drm_i915_private *dev_priv = dev->dev_private; |
3868 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3793 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3869 | struct drm_crtc *crtc; |
3794 | struct drm_crtc *crtc; |
3870 | 3795 | ||
3871 | skl_ddb_get_hw_state(dev_priv, ddb); |
3796 | skl_ddb_get_hw_state(dev_priv, ddb); |
3872 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3797 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3873 | skl_pipe_wm_get_hw_state(crtc); |
3798 | skl_pipe_wm_get_hw_state(crtc); |
3874 | } |
3799 | } |
3875 | 3800 | ||
3876 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3801 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3877 | { |
3802 | { |
3878 | struct drm_device *dev = crtc->dev; |
3803 | struct drm_device *dev = crtc->dev; |
3879 | struct drm_i915_private *dev_priv = dev->dev_private; |
3804 | struct drm_i915_private *dev_priv = dev->dev_private; |
3880 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
3805 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
3881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 3807 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
|
3882 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
3808 | struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; |
3883 | enum pipe pipe = intel_crtc->pipe; |
3809 | enum pipe pipe = intel_crtc->pipe; |
3884 | static const unsigned int wm0_pipe_reg[] = { |
3810 | static const i915_reg_t wm0_pipe_reg[] = { |
3885 | [PIPE_A] = WM0_PIPEA_ILK, |
3811 | [PIPE_A] = WM0_PIPEA_ILK, |
3886 | [PIPE_B] = WM0_PIPEB_ILK, |
3812 | [PIPE_B] = WM0_PIPEB_ILK, |
3887 | [PIPE_C] = WM0_PIPEC_IVB, |
3813 | [PIPE_C] = WM0_PIPEC_IVB, |
3888 | }; |
3814 | }; |
3889 | 3815 | ||
3890 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
3816 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
3891 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3817 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3892 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
3818 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
3893 | 3819 | ||
3894 | memset(active, 0, sizeof(*active)); |
3820 | memset(active, 0, sizeof(*active)); |
3895 | 3821 | ||
3896 | active->pipe_enabled = intel_crtc->active; |
3822 | active->pipe_enabled = intel_crtc->active; |
3897 | 3823 | ||
3898 | if (active->pipe_enabled) { |
3824 | if (active->pipe_enabled) { |
3899 | u32 tmp = hw->wm_pipe[pipe]; |
3825 | u32 tmp = hw->wm_pipe[pipe]; |
3900 | 3826 | ||
3901 | /* |
3827 | /* |
3902 | * For active pipes LP0 watermark is marked as |
3828 | * For active pipes LP0 watermark is marked as |
3903 | * enabled, and LP1+ watermaks as disabled since |
3829 | * enabled, and LP1+ watermaks as disabled since |
3904 | * we can't really reverse compute them in case |
3830 | * we can't really reverse compute them in case |
3905 | * multiple pipes are active. |
3831 | * multiple pipes are active. |
3906 | */ |
3832 | */ |
3907 | active->wm[0].enable = true; |
3833 | active->wm[0].enable = true; |
3908 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
3834 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
3909 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
3835 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
3910 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
3836 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
3911 | active->linetime = hw->wm_linetime[pipe]; |
3837 | active->linetime = hw->wm_linetime[pipe]; |
3912 | } else { |
3838 | } else { |
3913 | int level, max_level = ilk_wm_max_level(dev); |
3839 | int level, max_level = ilk_wm_max_level(dev); |
3914 | 3840 | ||
3915 | /* |
3841 | /* |
3916 | * For inactive pipes, all watermark levels |
3842 | * For inactive pipes, all watermark levels |
3917 | * should be marked as enabled but zeroed, |
3843 | * should be marked as enabled but zeroed, |
3918 | * which is what we'd compute them to. |
3844 | * which is what we'd compute them to. |
3919 | */ |
3845 | */ |
3920 | for (level = 0; level <= max_level; level++) |
3846 | for (level = 0; level <= max_level; level++) |
3921 | active->wm[level].enable = true; |
3847 | active->wm[level].enable = true; |
3922 | } |
3848 | } |
- | 3849 | ||
- | 3850 | intel_crtc->wm.active.ilk = *active; |
|
3923 | } |
3851 | } |
3924 | 3852 | ||
3925 | #define _FW_WM(value, plane) \ |
3853 | #define _FW_WM(value, plane) \ |
3926 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) |
3854 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) |
3927 | #define _FW_WM_VLV(value, plane) \ |
3855 | #define _FW_WM_VLV(value, plane) \ |
3928 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) |
3856 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) |
3929 | 3857 | ||
3930 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, |
3858 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, |
3931 | struct vlv_wm_values *wm) |
3859 | struct vlv_wm_values *wm) |
3932 | { |
3860 | { |
3933 | enum pipe pipe; |
3861 | enum pipe pipe; |
3934 | uint32_t tmp; |
3862 | uint32_t tmp; |
3935 | 3863 | ||
3936 | for_each_pipe(dev_priv, pipe) { |
3864 | for_each_pipe(dev_priv, pipe) { |
3937 | tmp = I915_READ(VLV_DDL(pipe)); |
3865 | tmp = I915_READ(VLV_DDL(pipe)); |
3938 | 3866 | ||
3939 | wm->ddl[pipe].primary = |
3867 | wm->ddl[pipe].primary = |
3940 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3868 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3941 | wm->ddl[pipe].cursor = |
3869 | wm->ddl[pipe].cursor = |
3942 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3870 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3943 | wm->ddl[pipe].sprite[0] = |
3871 | wm->ddl[pipe].sprite[0] = |
3944 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3872 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3945 | wm->ddl[pipe].sprite[1] = |
3873 | wm->ddl[pipe].sprite[1] = |
3946 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3874 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
3947 | } |
3875 | } |
3948 | 3876 | ||
3949 | tmp = I915_READ(DSPFW1); |
3877 | tmp = I915_READ(DSPFW1); |
3950 | wm->sr.plane = _FW_WM(tmp, SR); |
3878 | wm->sr.plane = _FW_WM(tmp, SR); |
3951 | wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); |
3879 | wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); |
3952 | wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); |
3880 | wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); |
3953 | wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); |
3881 | wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); |
3954 | 3882 | ||
3955 | tmp = I915_READ(DSPFW2); |
3883 | tmp = I915_READ(DSPFW2); |
3956 | wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); |
3884 | wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); |
3957 | wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); |
3885 | wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); |
3958 | wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); |
3886 | wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); |
3959 | 3887 | ||
3960 | tmp = I915_READ(DSPFW3); |
3888 | tmp = I915_READ(DSPFW3); |
3961 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); |
3889 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); |
3962 | 3890 | ||
3963 | if (IS_CHERRYVIEW(dev_priv)) { |
3891 | if (IS_CHERRYVIEW(dev_priv)) { |
3964 | tmp = I915_READ(DSPFW7_CHV); |
3892 | tmp = I915_READ(DSPFW7_CHV); |
3965 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
3893 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
3966 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
3894 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
3967 | 3895 | ||
3968 | tmp = I915_READ(DSPFW8_CHV); |
3896 | tmp = I915_READ(DSPFW8_CHV); |
3969 | wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); |
3897 | wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); |
3970 | wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); |
3898 | wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); |
3971 | 3899 | ||
3972 | tmp = I915_READ(DSPFW9_CHV); |
3900 | tmp = I915_READ(DSPFW9_CHV); |
3973 | wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); |
3901 | wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); |
3974 | wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); |
3902 | wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); |
3975 | 3903 | ||
3976 | tmp = I915_READ(DSPHOWM); |
3904 | tmp = I915_READ(DSPHOWM); |
3977 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
3905 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
3978 | wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
3906 | wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
3979 | wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; |
3907 | wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; |
3980 | wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; |
3908 | wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; |
3981 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
3909 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
3982 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
3910 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
3983 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
3911 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
3984 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
3912 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
3985 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
3913 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
3986 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
3914 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
3987 | } else { |
3915 | } else { |
3988 | tmp = I915_READ(DSPFW7); |
3916 | tmp = I915_READ(DSPFW7); |
3989 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
3917 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
3990 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
3918 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
3991 | 3919 | ||
3992 | tmp = I915_READ(DSPHOWM); |
3920 | tmp = I915_READ(DSPHOWM); |
3993 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
3921 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
3994 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
3922 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
3995 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
3923 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
3996 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
3924 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
3997 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
3925 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
3998 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
3926 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
3999 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
3927 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
4000 | } |
3928 | } |
4001 | } |
3929 | } |
4002 | 3930 | ||
4003 | #undef _FW_WM |
3931 | #undef _FW_WM |
4004 | #undef _FW_WM_VLV |
3932 | #undef _FW_WM_VLV |
4005 | 3933 | ||
4006 | void vlv_wm_get_hw_state(struct drm_device *dev) |
3934 | void vlv_wm_get_hw_state(struct drm_device *dev) |
4007 | { |
3935 | { |
4008 | struct drm_i915_private *dev_priv = to_i915(dev); |
3936 | struct drm_i915_private *dev_priv = to_i915(dev); |
4009 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; |
3937 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; |
4010 | struct intel_plane *plane; |
3938 | struct intel_plane *plane; |
4011 | enum pipe pipe; |
3939 | enum pipe pipe; |
4012 | u32 val; |
3940 | u32 val; |
4013 | 3941 | ||
4014 | vlv_read_wm_values(dev_priv, wm); |
3942 | vlv_read_wm_values(dev_priv, wm); |
4015 | 3943 | ||
4016 | for_each_intel_plane(dev, plane) { |
3944 | for_each_intel_plane(dev, plane) { |
4017 | switch (plane->base.type) { |
3945 | switch (plane->base.type) { |
4018 | int sprite; |
3946 | int sprite; |
4019 | case DRM_PLANE_TYPE_CURSOR: |
3947 | case DRM_PLANE_TYPE_CURSOR: |
4020 | plane->wm.fifo_size = 63; |
3948 | plane->wm.fifo_size = 63; |
4021 | break; |
3949 | break; |
4022 | case DRM_PLANE_TYPE_PRIMARY: |
3950 | case DRM_PLANE_TYPE_PRIMARY: |
4023 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); |
3951 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); |
4024 | break; |
3952 | break; |
4025 | case DRM_PLANE_TYPE_OVERLAY: |
3953 | case DRM_PLANE_TYPE_OVERLAY: |
4026 | sprite = plane->plane; |
3954 | sprite = plane->plane; |
4027 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); |
3955 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); |
4028 | break; |
3956 | break; |
4029 | } |
3957 | } |
4030 | } |
3958 | } |
4031 | 3959 | ||
4032 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
3960 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4033 | wm->level = VLV_WM_LEVEL_PM2; |
3961 | wm->level = VLV_WM_LEVEL_PM2; |
4034 | 3962 | ||
4035 | if (IS_CHERRYVIEW(dev_priv)) { |
3963 | if (IS_CHERRYVIEW(dev_priv)) { |
4036 | mutex_lock(&dev_priv->rps.hw_lock); |
3964 | mutex_lock(&dev_priv->rps.hw_lock); |
4037 | 3965 | ||
4038 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
3966 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
4039 | if (val & DSP_MAXFIFO_PM5_ENABLE) |
3967 | if (val & DSP_MAXFIFO_PM5_ENABLE) |
4040 | wm->level = VLV_WM_LEVEL_PM5; |
3968 | wm->level = VLV_WM_LEVEL_PM5; |
4041 | 3969 | ||
4042 | /* |
3970 | /* |
4043 | * If DDR DVFS is disabled in the BIOS, Punit |
3971 | * If DDR DVFS is disabled in the BIOS, Punit |
4044 | * will never ack the request. So if that happens |
3972 | * will never ack the request. So if that happens |
4045 | * assume we don't have to enable/disable DDR DVFS |
3973 | * assume we don't have to enable/disable DDR DVFS |
4046 | * dynamically. To test that just set the REQ_ACK |
3974 | * dynamically. To test that just set the REQ_ACK |
4047 | * bit to poke the Punit, but don't change the |
3975 | * bit to poke the Punit, but don't change the |
4048 | * HIGH/LOW bits so that we don't actually change |
3976 | * HIGH/LOW bits so that we don't actually change |
4049 | * the current state. |
3977 | * the current state. |
4050 | */ |
3978 | */ |
4051 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
3979 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
4052 | val |= FORCE_DDR_FREQ_REQ_ACK; |
3980 | val |= FORCE_DDR_FREQ_REQ_ACK; |
4053 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
3981 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
4054 | 3982 | ||
4055 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
3983 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
4056 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { |
3984 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { |
4057 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " |
3985 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " |
4058 | "assuming DDR DVFS is disabled\n"); |
3986 | "assuming DDR DVFS is disabled\n"); |
4059 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; |
3987 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; |
4060 | } else { |
3988 | } else { |
4061 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
3989 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
4062 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) |
3990 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) |
4063 | wm->level = VLV_WM_LEVEL_DDR_DVFS; |
3991 | wm->level = VLV_WM_LEVEL_DDR_DVFS; |
4064 | } |
3992 | } |
4065 | 3993 | ||
4066 | mutex_unlock(&dev_priv->rps.hw_lock); |
3994 | mutex_unlock(&dev_priv->rps.hw_lock); |
4067 | } |
3995 | } |
4068 | 3996 | ||
4069 | for_each_pipe(dev_priv, pipe) |
3997 | for_each_pipe(dev_priv, pipe) |
4070 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
3998 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
4071 | pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, |
3999 | pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, |
4072 | wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); |
4000 | wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); |
4073 | 4001 | ||
4074 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", |
4002 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", |
4075 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); |
4003 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); |
4076 | } |
4004 | } |
4077 | 4005 | ||
4078 | void ilk_wm_get_hw_state(struct drm_device *dev) |
4006 | void ilk_wm_get_hw_state(struct drm_device *dev) |
4079 | { |
4007 | { |
4080 | struct drm_i915_private *dev_priv = dev->dev_private; |
4008 | struct drm_i915_private *dev_priv = dev->dev_private; |
4081 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
4009 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
4082 | struct drm_crtc *crtc; |
4010 | struct drm_crtc *crtc; |
4083 | 4011 | ||
4084 | for_each_crtc(dev, crtc) |
4012 | for_each_crtc(dev, crtc) |
4085 | ilk_pipe_wm_get_hw_state(crtc); |
4013 | ilk_pipe_wm_get_hw_state(crtc); |
4086 | 4014 | ||
4087 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
4015 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
4088 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
4016 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
4089 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
4017 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
4090 | 4018 | ||
4091 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
4019 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
4092 | if (INTEL_INFO(dev)->gen >= 7) { |
4020 | if (INTEL_INFO(dev)->gen >= 7) { |
4093 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
4021 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
4094 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
4022 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
4095 | } |
4023 | } |
4096 | 4024 | ||
4097 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4025 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4098 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
4026 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
4099 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
4027 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
4100 | else if (IS_IVYBRIDGE(dev)) |
4028 | else if (IS_IVYBRIDGE(dev)) |
4101 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
4029 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
4102 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
4030 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
4103 | 4031 | ||
4104 | hw->enable_fbc_wm = |
4032 | hw->enable_fbc_wm = |
4105 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
4033 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
4106 | } |
4034 | } |
4107 | 4035 | ||
4108 | /** |
4036 | /** |
4109 | * intel_update_watermarks - update FIFO watermark values based on current modes |
4037 | * intel_update_watermarks - update FIFO watermark values based on current modes |
4110 | * |
4038 | * |
4111 | * Calculate watermark values for the various WM regs based on current mode |
4039 | * Calculate watermark values for the various WM regs based on current mode |
4112 | * and plane configuration. |
4040 | * and plane configuration. |
4113 | * |
4041 | * |
4114 | * There are several cases to deal with here: |
4042 | * There are several cases to deal with here: |
4115 | * - normal (i.e. non-self-refresh) |
4043 | * - normal (i.e. non-self-refresh) |
4116 | * - self-refresh (SR) mode |
4044 | * - self-refresh (SR) mode |
4117 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
4045 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
4118 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
4046 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
4119 | * lines), so need to account for TLB latency |
4047 | * lines), so need to account for TLB latency |
4120 | * |
4048 | * |
4121 | * The normal calculation is: |
4049 | * The normal calculation is: |
4122 | * watermark = dotclock * bytes per pixel * latency |
4050 | * watermark = dotclock * bytes per pixel * latency |
4123 | * where latency is platform & configuration dependent (we assume pessimal |
4051 | * where latency is platform & configuration dependent (we assume pessimal |
4124 | * values here). |
4052 | * values here). |
4125 | * |
4053 | * |
4126 | * The SR calculation is: |
4054 | * The SR calculation is: |
4127 | * watermark = (trunc(latency/line time)+1) * surface width * |
4055 | * watermark = (trunc(latency/line time)+1) * surface width * |
4128 | * bytes per pixel |
4056 | * bytes per pixel |
4129 | * where |
4057 | * where |
4130 | * line time = htotal / dotclock |
4058 | * line time = htotal / dotclock |
4131 | * surface width = hdisplay for normal plane and 64 for cursor |
4059 | * surface width = hdisplay for normal plane and 64 for cursor |
4132 | * and latency is assumed to be high, as above. |
4060 | * and latency is assumed to be high, as above. |
4133 | * |
4061 | * |
4134 | * The final value programmed to the register should always be rounded up, |
4062 | * The final value programmed to the register should always be rounded up, |
4135 | * and include an extra 2 entries to account for clock crossings. |
4063 | * and include an extra 2 entries to account for clock crossings. |
4136 | * |
4064 | * |
4137 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
4065 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
4138 | * to set the non-SR watermarks to 8. |
4066 | * to set the non-SR watermarks to 8. |
4139 | */ |
4067 | */ |
4140 | void intel_update_watermarks(struct drm_crtc *crtc) |
4068 | void intel_update_watermarks(struct drm_crtc *crtc) |
4141 | { |
4069 | { |
4142 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
4070 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
4143 | 4071 | ||
4144 | if (dev_priv->display.update_wm) |
4072 | if (dev_priv->display.update_wm) |
4145 | dev_priv->display.update_wm(crtc); |
4073 | dev_priv->display.update_wm(crtc); |
4146 | } |
4074 | } |
4147 | - | ||
4148 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
- | |
4149 | struct drm_crtc *crtc, |
- | |
4150 | uint32_t sprite_width, |
- | |
4151 | uint32_t sprite_height, |
- | |
4152 | int pixel_size, |
- | |
4153 | bool enabled, bool scaled) |
- | |
4154 | { |
- | |
4155 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
- | |
4156 | - | ||
4157 | if (dev_priv->display.update_sprite_wm) |
- | |
4158 | dev_priv->display.update_sprite_wm(plane, crtc, |
- | |
4159 | sprite_width, sprite_height, |
- | |
4160 | pixel_size, enabled, scaled); |
- | |
4161 | } |
- | |
4162 | 4075 | ||
4163 | /** |
4076 | /** |
4164 | * Lock protecting IPS related data structures |
4077 | * Lock protecting IPS related data structures |
4165 | */ |
4078 | */ |
4166 | DEFINE_SPINLOCK(mchdev_lock); |
4079 | DEFINE_SPINLOCK(mchdev_lock); |
4167 | 4080 | ||
4168 | /* Global for IPS driver to get at the current i915 device. Protected by |
4081 | /* Global for IPS driver to get at the current i915 device. Protected by |
4169 | * mchdev_lock. */ |
4082 | * mchdev_lock. */ |
4170 | static struct drm_i915_private *i915_mch_dev; |
4083 | static struct drm_i915_private *i915_mch_dev; |
4171 | 4084 | ||
4172 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
4085 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
4173 | { |
4086 | { |
4174 | struct drm_i915_private *dev_priv = dev->dev_private; |
4087 | struct drm_i915_private *dev_priv = dev->dev_private; |
4175 | u16 rgvswctl; |
4088 | u16 rgvswctl; |
4176 | 4089 | ||
4177 | assert_spin_locked(&mchdev_lock); |
4090 | assert_spin_locked(&mchdev_lock); |
4178 | 4091 | ||
4179 | rgvswctl = I915_READ16(MEMSWCTL); |
4092 | rgvswctl = I915_READ16(MEMSWCTL); |
4180 | if (rgvswctl & MEMCTL_CMD_STS) { |
4093 | if (rgvswctl & MEMCTL_CMD_STS) { |
4181 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
4094 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
4182 | return false; /* still busy with another command */ |
4095 | return false; /* still busy with another command */ |
4183 | } |
4096 | } |
4184 | 4097 | ||
4185 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
4098 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
4186 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
4099 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
4187 | I915_WRITE16(MEMSWCTL, rgvswctl); |
4100 | I915_WRITE16(MEMSWCTL, rgvswctl); |
4188 | POSTING_READ16(MEMSWCTL); |
4101 | POSTING_READ16(MEMSWCTL); |
4189 | 4102 | ||
4190 | rgvswctl |= MEMCTL_CMD_STS; |
4103 | rgvswctl |= MEMCTL_CMD_STS; |
4191 | I915_WRITE16(MEMSWCTL, rgvswctl); |
4104 | I915_WRITE16(MEMSWCTL, rgvswctl); |
4192 | 4105 | ||
4193 | return true; |
4106 | return true; |
4194 | } |
4107 | } |
4195 | 4108 | ||
4196 | static void ironlake_enable_drps(struct drm_device *dev) |
4109 | static void ironlake_enable_drps(struct drm_device *dev) |
4197 | { |
4110 | { |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; |
4111 | struct drm_i915_private *dev_priv = dev->dev_private; |
4199 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
4112 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
4200 | u8 fmax, fmin, fstart, vstart; |
4113 | u8 fmax, fmin, fstart, vstart; |
4201 | 4114 | ||
4202 | spin_lock_irq(&mchdev_lock); |
4115 | spin_lock_irq(&mchdev_lock); |
4203 | 4116 | ||
4204 | /* Enable temp reporting */ |
4117 | /* Enable temp reporting */ |
4205 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
4118 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
4206 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
4119 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
4207 | 4120 | ||
4208 | /* 100ms RC evaluation intervals */ |
4121 | /* 100ms RC evaluation intervals */ |
4209 | I915_WRITE(RCUPEI, 100000); |
4122 | I915_WRITE(RCUPEI, 100000); |
4210 | I915_WRITE(RCDNEI, 100000); |
4123 | I915_WRITE(RCDNEI, 100000); |
4211 | 4124 | ||
4212 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
4125 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
4213 | I915_WRITE(RCBMAXAVG, 90000); |
4126 | I915_WRITE(RCBMAXAVG, 90000); |
4214 | I915_WRITE(RCBMINAVG, 80000); |
4127 | I915_WRITE(RCBMINAVG, 80000); |
4215 | 4128 | ||
4216 | I915_WRITE(MEMIHYST, 1); |
4129 | I915_WRITE(MEMIHYST, 1); |
4217 | 4130 | ||
4218 | /* Set up min, max, and cur for interrupt handling */ |
4131 | /* Set up min, max, and cur for interrupt handling */ |
4219 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
4132 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
4220 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
4133 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
4221 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
4134 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
4222 | MEMMODE_FSTART_SHIFT; |
4135 | MEMMODE_FSTART_SHIFT; |
4223 | 4136 | ||
4224 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
4137 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
4225 | PXVFREQ_PX_SHIFT; |
4138 | PXVFREQ_PX_SHIFT; |
4226 | 4139 | ||
4227 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
4140 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
4228 | dev_priv->ips.fstart = fstart; |
4141 | dev_priv->ips.fstart = fstart; |
4229 | 4142 | ||
4230 | dev_priv->ips.max_delay = fstart; |
4143 | dev_priv->ips.max_delay = fstart; |
4231 | dev_priv->ips.min_delay = fmin; |
4144 | dev_priv->ips.min_delay = fmin; |
4232 | dev_priv->ips.cur_delay = fstart; |
4145 | dev_priv->ips.cur_delay = fstart; |
4233 | 4146 | ||
4234 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
4147 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
4235 | fmax, fmin, fstart); |
4148 | fmax, fmin, fstart); |
4236 | 4149 | ||
4237 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
4150 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
4238 | 4151 | ||
4239 | /* |
4152 | /* |
4240 | * Interrupts will be enabled in ironlake_irq_postinstall |
4153 | * Interrupts will be enabled in ironlake_irq_postinstall |
4241 | */ |
4154 | */ |
4242 | 4155 | ||
4243 | I915_WRITE(VIDSTART, vstart); |
4156 | I915_WRITE(VIDSTART, vstart); |
4244 | POSTING_READ(VIDSTART); |
4157 | POSTING_READ(VIDSTART); |
4245 | 4158 | ||
4246 | rgvmodectl |= MEMMODE_SWMODE_EN; |
4159 | rgvmodectl |= MEMMODE_SWMODE_EN; |
4247 | I915_WRITE(MEMMODECTL, rgvmodectl); |
4160 | I915_WRITE(MEMMODECTL, rgvmodectl); |
4248 | 4161 | ||
4249 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
4162 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
4250 | DRM_ERROR("stuck trying to change perf mode\n"); |
4163 | DRM_ERROR("stuck trying to change perf mode\n"); |
4251 | mdelay(1); |
4164 | mdelay(1); |
4252 | 4165 | ||
4253 | ironlake_set_drps(dev, fstart); |
4166 | ironlake_set_drps(dev, fstart); |
4254 | 4167 | ||
4255 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
4168 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
4256 | I915_READ(DDREC) + I915_READ(CSIEC); |
4169 | I915_READ(DDREC) + I915_READ(CSIEC); |
4257 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
4170 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
4258 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
4171 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
4259 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
4172 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
4260 | 4173 | ||
4261 | spin_unlock_irq(&mchdev_lock); |
4174 | spin_unlock_irq(&mchdev_lock); |
4262 | } |
4175 | } |
4263 | 4176 | ||
4264 | static void ironlake_disable_drps(struct drm_device *dev) |
4177 | static void ironlake_disable_drps(struct drm_device *dev) |
4265 | { |
4178 | { |
4266 | struct drm_i915_private *dev_priv = dev->dev_private; |
4179 | struct drm_i915_private *dev_priv = dev->dev_private; |
4267 | u16 rgvswctl; |
4180 | u16 rgvswctl; |
4268 | 4181 | ||
4269 | spin_lock_irq(&mchdev_lock); |
4182 | spin_lock_irq(&mchdev_lock); |
4270 | 4183 | ||
4271 | rgvswctl = I915_READ16(MEMSWCTL); |
4184 | rgvswctl = I915_READ16(MEMSWCTL); |
4272 | 4185 | ||
4273 | /* Ack interrupts, disable EFC interrupt */ |
4186 | /* Ack interrupts, disable EFC interrupt */ |
4274 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
4187 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
4275 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
4188 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
4276 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
4189 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
4277 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
4190 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
4278 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
4191 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
4279 | 4192 | ||
4280 | /* Go back to the starting frequency */ |
4193 | /* Go back to the starting frequency */ |
4281 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
4194 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
4282 | mdelay(1); |
4195 | mdelay(1); |
4283 | rgvswctl |= MEMCTL_CMD_STS; |
4196 | rgvswctl |= MEMCTL_CMD_STS; |
4284 | I915_WRITE(MEMSWCTL, rgvswctl); |
4197 | I915_WRITE(MEMSWCTL, rgvswctl); |
4285 | mdelay(1); |
4198 | mdelay(1); |
4286 | 4199 | ||
4287 | spin_unlock_irq(&mchdev_lock); |
4200 | spin_unlock_irq(&mchdev_lock); |
4288 | } |
4201 | } |
4289 | 4202 | ||
4290 | /* There's a funny hw issue where the hw returns all 0 when reading from |
4203 | /* There's a funny hw issue where the hw returns all 0 when reading from |
4291 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
4204 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
4292 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
4205 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
4293 | * all limits and the gpu stuck at whatever frequency it is at atm). |
4206 | * all limits and the gpu stuck at whatever frequency it is at atm). |
4294 | */ |
4207 | */ |
4295 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
4208 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
4296 | { |
4209 | { |
4297 | u32 limits; |
4210 | u32 limits; |
4298 | 4211 | ||
4299 | /* Only set the down limit when we've reached the lowest level to avoid |
4212 | /* Only set the down limit when we've reached the lowest level to avoid |
4300 | * getting more interrupts, otherwise leave this clear. This prevents a |
4213 | * getting more interrupts, otherwise leave this clear. This prevents a |
4301 | * race in the hw when coming out of rc6: There's a tiny window where |
4214 | * race in the hw when coming out of rc6: There's a tiny window where |
4302 | * the hw runs at the minimal clock before selecting the desired |
4215 | * the hw runs at the minimal clock before selecting the desired |
4303 | * frequency, if the down threshold expires in that window we will not |
4216 | * frequency, if the down threshold expires in that window we will not |
4304 | * receive a down interrupt. */ |
4217 | * receive a down interrupt. */ |
4305 | if (IS_GEN9(dev_priv->dev)) { |
4218 | if (IS_GEN9(dev_priv->dev)) { |
4306 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
4219 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
4307 | if (val <= dev_priv->rps.min_freq_softlimit) |
4220 | if (val <= dev_priv->rps.min_freq_softlimit) |
4308 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; |
4221 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; |
4309 | } else { |
4222 | } else { |
4310 | limits = dev_priv->rps.max_freq_softlimit << 24; |
4223 | limits = dev_priv->rps.max_freq_softlimit << 24; |
4311 | if (val <= dev_priv->rps.min_freq_softlimit) |
4224 | if (val <= dev_priv->rps.min_freq_softlimit) |
4312 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
4225 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
4313 | } |
4226 | } |
4314 | 4227 | ||
4315 | return limits; |
4228 | return limits; |
4316 | } |
4229 | } |
4317 | 4230 | ||
4318 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
4231 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
4319 | { |
4232 | { |
4320 | int new_power; |
4233 | int new_power; |
4321 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
4234 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
4322 | u32 ei_up = 0, ei_down = 0; |
4235 | u32 ei_up = 0, ei_down = 0; |
4323 | 4236 | ||
4324 | new_power = dev_priv->rps.power; |
4237 | new_power = dev_priv->rps.power; |
4325 | switch (dev_priv->rps.power) { |
4238 | switch (dev_priv->rps.power) { |
4326 | case LOW_POWER: |
4239 | case LOW_POWER: |
4327 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
4240 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
4328 | new_power = BETWEEN; |
4241 | new_power = BETWEEN; |
4329 | break; |
4242 | break; |
4330 | 4243 | ||
4331 | case BETWEEN: |
4244 | case BETWEEN: |
4332 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
4245 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
4333 | new_power = LOW_POWER; |
4246 | new_power = LOW_POWER; |
4334 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
4247 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
4335 | new_power = HIGH_POWER; |
4248 | new_power = HIGH_POWER; |
4336 | break; |
4249 | break; |
4337 | 4250 | ||
4338 | case HIGH_POWER: |
4251 | case HIGH_POWER: |
4339 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
4252 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
4340 | new_power = BETWEEN; |
4253 | new_power = BETWEEN; |
4341 | break; |
4254 | break; |
4342 | } |
4255 | } |
4343 | /* Max/min bins are special */ |
4256 | /* Max/min bins are special */ |
4344 | if (val <= dev_priv->rps.min_freq_softlimit) |
4257 | if (val <= dev_priv->rps.min_freq_softlimit) |
4345 | new_power = LOW_POWER; |
4258 | new_power = LOW_POWER; |
4346 | if (val >= dev_priv->rps.max_freq_softlimit) |
4259 | if (val >= dev_priv->rps.max_freq_softlimit) |
4347 | new_power = HIGH_POWER; |
4260 | new_power = HIGH_POWER; |
4348 | if (new_power == dev_priv->rps.power) |
4261 | if (new_power == dev_priv->rps.power) |
4349 | return; |
4262 | return; |
4350 | 4263 | ||
4351 | /* Note the units here are not exactly 1us, but 1280ns. */ |
4264 | /* Note the units here are not exactly 1us, but 1280ns. */ |
4352 | switch (new_power) { |
4265 | switch (new_power) { |
4353 | case LOW_POWER: |
4266 | case LOW_POWER: |
4354 | /* Upclock if more than 95% busy over 16ms */ |
4267 | /* Upclock if more than 95% busy over 16ms */ |
4355 | ei_up = 16000; |
4268 | ei_up = 16000; |
4356 | threshold_up = 95; |
4269 | threshold_up = 95; |
4357 | 4270 | ||
4358 | /* Downclock if less than 85% busy over 32ms */ |
4271 | /* Downclock if less than 85% busy over 32ms */ |
4359 | ei_down = 32000; |
4272 | ei_down = 32000; |
4360 | threshold_down = 85; |
4273 | threshold_down = 85; |
4361 | break; |
4274 | break; |
4362 | 4275 | ||
4363 | case BETWEEN: |
4276 | case BETWEEN: |
4364 | /* Upclock if more than 90% busy over 13ms */ |
4277 | /* Upclock if more than 90% busy over 13ms */ |
4365 | ei_up = 13000; |
4278 | ei_up = 13000; |
4366 | threshold_up = 90; |
4279 | threshold_up = 90; |
4367 | 4280 | ||
4368 | /* Downclock if less than 75% busy over 32ms */ |
4281 | /* Downclock if less than 75% busy over 32ms */ |
4369 | ei_down = 32000; |
4282 | ei_down = 32000; |
4370 | threshold_down = 75; |
4283 | threshold_down = 75; |
4371 | break; |
4284 | break; |
4372 | 4285 | ||
4373 | case HIGH_POWER: |
4286 | case HIGH_POWER: |
4374 | /* Upclock if more than 85% busy over 10ms */ |
4287 | /* Upclock if more than 85% busy over 10ms */ |
4375 | ei_up = 10000; |
4288 | ei_up = 10000; |
4376 | threshold_up = 85; |
4289 | threshold_up = 85; |
4377 | 4290 | ||
4378 | /* Downclock if less than 60% busy over 32ms */ |
4291 | /* Downclock if less than 60% busy over 32ms */ |
4379 | ei_down = 32000; |
4292 | ei_down = 32000; |
4380 | threshold_down = 60; |
4293 | threshold_down = 60; |
4381 | break; |
4294 | break; |
4382 | } |
4295 | } |
4383 | - | ||
4384 | /* When byt can survive without system hang with dynamic |
- | |
4385 | * sw freq adjustments, this restriction can be lifted. |
- | |
4386 | */ |
- | |
4387 | if (IS_VALLEYVIEW(dev_priv)) |
- | |
4388 | goto skip_hw_write; |
- | |
4389 | 4296 | ||
4390 | I915_WRITE(GEN6_RP_UP_EI, |
4297 | I915_WRITE(GEN6_RP_UP_EI, |
4391 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
4298 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
4392 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
4299 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
4393 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); |
4300 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); |
4394 | 4301 | ||
4395 | I915_WRITE(GEN6_RP_DOWN_EI, |
4302 | I915_WRITE(GEN6_RP_DOWN_EI, |
4396 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
4303 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
4397 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
4304 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
4398 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); |
4305 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); |
4399 | 4306 | ||
4400 | I915_WRITE(GEN6_RP_CONTROL, |
4307 | I915_WRITE(GEN6_RP_CONTROL, |
4401 | GEN6_RP_MEDIA_TURBO | |
4308 | GEN6_RP_MEDIA_TURBO | |
4402 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
4309 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
4403 | GEN6_RP_MEDIA_IS_GFX | |
4310 | GEN6_RP_MEDIA_IS_GFX | |
4404 | GEN6_RP_ENABLE | |
4311 | GEN6_RP_ENABLE | |
4405 | GEN6_RP_UP_BUSY_AVG | |
4312 | GEN6_RP_UP_BUSY_AVG | |
4406 | GEN6_RP_DOWN_IDLE_AVG); |
4313 | GEN6_RP_DOWN_IDLE_AVG); |
4407 | - | ||
4408 | skip_hw_write: |
4314 | |
4409 | dev_priv->rps.power = new_power; |
4315 | dev_priv->rps.power = new_power; |
4410 | dev_priv->rps.up_threshold = threshold_up; |
4316 | dev_priv->rps.up_threshold = threshold_up; |
4411 | dev_priv->rps.down_threshold = threshold_down; |
4317 | dev_priv->rps.down_threshold = threshold_down; |
4412 | dev_priv->rps.last_adj = 0; |
4318 | dev_priv->rps.last_adj = 0; |
4413 | } |
4319 | } |
4414 | 4320 | ||
4415 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4321 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4416 | { |
4322 | { |
4417 | u32 mask = 0; |
4323 | u32 mask = 0; |
4418 | - | ||
4419 | /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
4324 | |
4420 | if (val > dev_priv->rps.min_freq_softlimit) |
4325 | if (val > dev_priv->rps.min_freq_softlimit) |
4421 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
4326 | mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
4422 | if (val < dev_priv->rps.max_freq_softlimit) |
4327 | if (val < dev_priv->rps.max_freq_softlimit) |
4423 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
4328 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
4424 | 4329 | ||
4425 | mask &= dev_priv->pm_rps_events; |
4330 | mask &= dev_priv->pm_rps_events; |
4426 | 4331 | ||
4427 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
4332 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
4428 | } |
4333 | } |
4429 | 4334 | ||
4430 | /* gen6_set_rps is called to update the frequency request, but should also be |
4335 | /* gen6_set_rps is called to update the frequency request, but should also be |
4431 | * called when the range (min_delay and max_delay) is modified so that we can |
4336 | * called when the range (min_delay and max_delay) is modified so that we can |
4432 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
4337 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
4433 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
4338 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
4434 | { |
4339 | { |
4435 | struct drm_i915_private *dev_priv = dev->dev_private; |
4340 | struct drm_i915_private *dev_priv = dev->dev_private; |
4436 | 4341 | ||
4437 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4342 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4438 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
4343 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
4439 | return; |
4344 | return; |
4440 | 4345 | ||
4441 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4346 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4442 | WARN_ON(val > dev_priv->rps.max_freq); |
4347 | WARN_ON(val > dev_priv->rps.max_freq); |
4443 | WARN_ON(val < dev_priv->rps.min_freq); |
4348 | WARN_ON(val < dev_priv->rps.min_freq); |
4444 | 4349 | ||
4445 | /* min/max delay may still have been modified so be sure to |
4350 | /* min/max delay may still have been modified so be sure to |
4446 | * write the limits value. |
4351 | * write the limits value. |
4447 | */ |
4352 | */ |
4448 | if (val != dev_priv->rps.cur_freq) { |
4353 | if (val != dev_priv->rps.cur_freq) { |
4449 | gen6_set_rps_thresholds(dev_priv, val); |
4354 | gen6_set_rps_thresholds(dev_priv, val); |
4450 | 4355 | ||
4451 | if (IS_GEN9(dev)) |
4356 | if (IS_GEN9(dev)) |
4452 | I915_WRITE(GEN6_RPNSWREQ, |
4357 | I915_WRITE(GEN6_RPNSWREQ, |
4453 | GEN9_FREQUENCY(val)); |
4358 | GEN9_FREQUENCY(val)); |
4454 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4359 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4455 | I915_WRITE(GEN6_RPNSWREQ, |
4360 | I915_WRITE(GEN6_RPNSWREQ, |
4456 | HSW_FREQUENCY(val)); |
4361 | HSW_FREQUENCY(val)); |
4457 | else |
4362 | else |
4458 | I915_WRITE(GEN6_RPNSWREQ, |
4363 | I915_WRITE(GEN6_RPNSWREQ, |
4459 | GEN6_FREQUENCY(val) | |
4364 | GEN6_FREQUENCY(val) | |
4460 | GEN6_OFFSET(0) | |
4365 | GEN6_OFFSET(0) | |
4461 | GEN6_AGGRESSIVE_TURBO); |
4366 | GEN6_AGGRESSIVE_TURBO); |
4462 | } |
4367 | } |
4463 | 4368 | ||
4464 | /* Make sure we continue to get interrupts |
4369 | /* Make sure we continue to get interrupts |
4465 | * until we hit the minimum or maximum frequencies. |
4370 | * until we hit the minimum or maximum frequencies. |
4466 | */ |
4371 | */ |
4467 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
4372 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
4468 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4373 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4469 | 4374 | ||
4470 | POSTING_READ(GEN6_RPNSWREQ); |
4375 | POSTING_READ(GEN6_RPNSWREQ); |
4471 | 4376 | ||
4472 | dev_priv->rps.cur_freq = val; |
4377 | dev_priv->rps.cur_freq = val; |
4473 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
4378 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
4474 | } |
4379 | } |
4475 | 4380 | ||
4476 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
4381 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
4477 | { |
4382 | { |
4478 | struct drm_i915_private *dev_priv = dev->dev_private; |
4383 | struct drm_i915_private *dev_priv = dev->dev_private; |
4479 | 4384 | ||
4480 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4385 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4481 | WARN_ON(val > dev_priv->rps.max_freq); |
4386 | WARN_ON(val > dev_priv->rps.max_freq); |
4482 | WARN_ON(val < dev_priv->rps.min_freq); |
4387 | WARN_ON(val < dev_priv->rps.min_freq); |
4483 | 4388 | ||
4484 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
4389 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
4485 | "Odd GPU freq value\n")) |
4390 | "Odd GPU freq value\n")) |
4486 | val &= ~1; |
4391 | val &= ~1; |
4487 | 4392 | ||
4488 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4393 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4489 | 4394 | ||
4490 | if (val != dev_priv->rps.cur_freq) { |
4395 | if (val != dev_priv->rps.cur_freq) { |
4491 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
4396 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
4492 | if (!IS_CHERRYVIEW(dev_priv)) |
4397 | if (!IS_CHERRYVIEW(dev_priv)) |
4493 | gen6_set_rps_thresholds(dev_priv, val); |
4398 | gen6_set_rps_thresholds(dev_priv, val); |
4494 | } |
4399 | } |
4495 | 4400 | ||
4496 | dev_priv->rps.cur_freq = val; |
4401 | dev_priv->rps.cur_freq = val; |
4497 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
4402 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
4498 | } |
4403 | } |
4499 | 4404 | ||
4500 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
4405 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
4501 | * |
4406 | * |
4502 | * * If Gfx is Idle, then |
4407 | * * If Gfx is Idle, then |
4503 | * 1. Forcewake Media well. |
4408 | * 1. Forcewake Media well. |
4504 | * 2. Request idle freq. |
4409 | * 2. Request idle freq. |
4505 | * 3. Release Forcewake of Media well. |
4410 | * 3. Release Forcewake of Media well. |
4506 | */ |
4411 | */ |
4507 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
4412 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
4508 | { |
4413 | { |
4509 | u32 val = dev_priv->rps.idle_freq; |
4414 | u32 val = dev_priv->rps.idle_freq; |
4510 | 4415 | ||
4511 | if (dev_priv->rps.cur_freq <= val) |
4416 | if (dev_priv->rps.cur_freq <= val) |
4512 | return; |
4417 | return; |
4513 | 4418 | ||
4514 | /* Wake up the media well, as that takes a lot less |
4419 | /* Wake up the media well, as that takes a lot less |
4515 | * power than the Render well. */ |
4420 | * power than the Render well. */ |
4516 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
4421 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
4517 | valleyview_set_rps(dev_priv->dev, val); |
4422 | valleyview_set_rps(dev_priv->dev, val); |
4518 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
4423 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
4519 | } |
4424 | } |
4520 | 4425 | ||
4521 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
4426 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
4522 | { |
4427 | { |
4523 | mutex_lock(&dev_priv->rps.hw_lock); |
4428 | mutex_lock(&dev_priv->rps.hw_lock); |
4524 | if (dev_priv->rps.enabled) { |
4429 | if (dev_priv->rps.enabled) { |
4525 | if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
4430 | if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) |
4526 | gen6_rps_reset_ei(dev_priv); |
4431 | gen6_rps_reset_ei(dev_priv); |
4527 | I915_WRITE(GEN6_PMINTRMSK, |
4432 | I915_WRITE(GEN6_PMINTRMSK, |
4528 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
4433 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
4529 | } |
4434 | } |
4530 | mutex_unlock(&dev_priv->rps.hw_lock); |
4435 | mutex_unlock(&dev_priv->rps.hw_lock); |
4531 | } |
4436 | } |
4532 | 4437 | ||
4533 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4438 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4534 | { |
4439 | { |
4535 | struct drm_device *dev = dev_priv->dev; |
4440 | struct drm_device *dev = dev_priv->dev; |
4536 | 4441 | ||
4537 | mutex_lock(&dev_priv->rps.hw_lock); |
4442 | mutex_lock(&dev_priv->rps.hw_lock); |
4538 | if (dev_priv->rps.enabled) { |
4443 | if (dev_priv->rps.enabled) { |
4539 | if (IS_VALLEYVIEW(dev)) |
4444 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
4540 | vlv_set_rps_idle(dev_priv); |
4445 | vlv_set_rps_idle(dev_priv); |
4541 | else |
4446 | else |
4542 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4447 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4543 | dev_priv->rps.last_adj = 0; |
4448 | dev_priv->rps.last_adj = 0; |
4544 | I915_WRITE(GEN6_PMINTRMSK, |
4449 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
4545 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
- | |
4546 | } |
4450 | } |
4547 | mutex_unlock(&dev_priv->rps.hw_lock); |
4451 | mutex_unlock(&dev_priv->rps.hw_lock); |
4548 | 4452 | ||
4549 | spin_lock(&dev_priv->rps.client_lock); |
4453 | spin_lock(&dev_priv->rps.client_lock); |
4550 | while (!list_empty(&dev_priv->rps.clients)) |
4454 | while (!list_empty(&dev_priv->rps.clients)) |
4551 | list_del_init(dev_priv->rps.clients.next); |
4455 | list_del_init(dev_priv->rps.clients.next); |
4552 | spin_unlock(&dev_priv->rps.client_lock); |
4456 | spin_unlock(&dev_priv->rps.client_lock); |
4553 | } |
4457 | } |
4554 | 4458 | ||
4555 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
4459 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
4556 | struct intel_rps_client *rps, |
4460 | struct intel_rps_client *rps, |
4557 | unsigned long submitted) |
4461 | unsigned long submitted) |
4558 | { |
4462 | { |
4559 | /* This is intentionally racy! We peek at the state here, then |
4463 | /* This is intentionally racy! We peek at the state here, then |
4560 | * validate inside the RPS worker. |
4464 | * validate inside the RPS worker. |
4561 | */ |
4465 | */ |
4562 | if (!(dev_priv->mm.busy && |
4466 | if (!(dev_priv->mm.busy && |
4563 | dev_priv->rps.enabled && |
4467 | dev_priv->rps.enabled && |
4564 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) |
4468 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) |
4565 | return; |
4469 | return; |
4566 | 4470 | ||
4567 | /* Force a RPS boost (and don't count it against the client) if |
4471 | /* Force a RPS boost (and don't count it against the client) if |
4568 | * the GPU is severely congested. |
4472 | * the GPU is severely congested. |
4569 | */ |
4473 | */ |
4570 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
4474 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
4571 | rps = NULL; |
4475 | rps = NULL; |
4572 | 4476 | ||
4573 | spin_lock(&dev_priv->rps.client_lock); |
4477 | spin_lock(&dev_priv->rps.client_lock); |
4574 | if (rps == NULL || list_empty(&rps->link)) { |
4478 | if (rps == NULL || list_empty(&rps->link)) { |
4575 | spin_lock_irq(&dev_priv->irq_lock); |
4479 | spin_lock_irq(&dev_priv->irq_lock); |
4576 | if (dev_priv->rps.interrupts_enabled) { |
4480 | if (dev_priv->rps.interrupts_enabled) { |
4577 | dev_priv->rps.client_boost = true; |
4481 | dev_priv->rps.client_boost = true; |
4578 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
4482 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
4579 | } |
4483 | } |
4580 | spin_unlock_irq(&dev_priv->irq_lock); |
4484 | spin_unlock_irq(&dev_priv->irq_lock); |
4581 | 4485 | ||
4582 | if (rps != NULL) { |
4486 | if (rps != NULL) { |
4583 | list_add(&rps->link, &dev_priv->rps.clients); |
4487 | list_add(&rps->link, &dev_priv->rps.clients); |
4584 | rps->boosts++; |
4488 | rps->boosts++; |
4585 | } else |
4489 | } else |
4586 | dev_priv->rps.boosts++; |
4490 | dev_priv->rps.boosts++; |
4587 | } |
4491 | } |
4588 | spin_unlock(&dev_priv->rps.client_lock); |
4492 | spin_unlock(&dev_priv->rps.client_lock); |
4589 | } |
4493 | } |
4590 | 4494 | ||
4591 | void intel_set_rps(struct drm_device *dev, u8 val) |
4495 | void intel_set_rps(struct drm_device *dev, u8 val) |
4592 | { |
4496 | { |
4593 | if (IS_VALLEYVIEW(dev)) |
4497 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
4594 | valleyview_set_rps(dev, val); |
4498 | valleyview_set_rps(dev, val); |
4595 | else |
4499 | else |
4596 | gen6_set_rps(dev, val); |
4500 | gen6_set_rps(dev, val); |
4597 | } |
4501 | } |
4598 | 4502 | ||
4599 | static void gen9_disable_rps(struct drm_device *dev) |
4503 | static void gen9_disable_rps(struct drm_device *dev) |
4600 | { |
4504 | { |
4601 | struct drm_i915_private *dev_priv = dev->dev_private; |
4505 | struct drm_i915_private *dev_priv = dev->dev_private; |
4602 | 4506 | ||
4603 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4507 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4604 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4508 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4605 | } |
4509 | } |
4606 | 4510 | ||
4607 | static void gen6_disable_rps(struct drm_device *dev) |
4511 | static void gen6_disable_rps(struct drm_device *dev) |
4608 | { |
4512 | { |
4609 | struct drm_i915_private *dev_priv = dev->dev_private; |
4513 | struct drm_i915_private *dev_priv = dev->dev_private; |
4610 | 4514 | ||
4611 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4515 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4612 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
4516 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
4613 | } |
4517 | } |
4614 | 4518 | ||
4615 | static void cherryview_disable_rps(struct drm_device *dev) |
4519 | static void cherryview_disable_rps(struct drm_device *dev) |
4616 | { |
4520 | { |
4617 | struct drm_i915_private *dev_priv = dev->dev_private; |
4521 | struct drm_i915_private *dev_priv = dev->dev_private; |
4618 | 4522 | ||
4619 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4523 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4620 | } |
4524 | } |
4621 | 4525 | ||
4622 | static void valleyview_disable_rps(struct drm_device *dev) |
4526 | static void valleyview_disable_rps(struct drm_device *dev) |
4623 | { |
4527 | { |
4624 | struct drm_i915_private *dev_priv = dev->dev_private; |
4528 | struct drm_i915_private *dev_priv = dev->dev_private; |
4625 | 4529 | ||
4626 | /* we're doing forcewake before Disabling RC6, |
4530 | /* we're doing forcewake before Disabling RC6, |
4627 | * This what the BIOS expects when going into suspend */ |
4531 | * This what the BIOS expects when going into suspend */ |
4628 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4532 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4629 | 4533 | ||
4630 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4534 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4631 | 4535 | ||
4632 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4536 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4633 | } |
4537 | } |
4634 | 4538 | ||
4635 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4539 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4636 | { |
4540 | { |
4637 | if (IS_VALLEYVIEW(dev)) { |
4541 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4638 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
4542 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
4639 | mode = GEN6_RC_CTL_RC6_ENABLE; |
4543 | mode = GEN6_RC_CTL_RC6_ENABLE; |
4640 | else |
4544 | else |
4641 | mode = 0; |
4545 | mode = 0; |
4642 | } |
4546 | } |
4643 | if (HAS_RC6p(dev)) |
4547 | if (HAS_RC6p(dev)) |
4644 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
4548 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
4645 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
4549 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
4646 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
4550 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
4647 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
4551 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
4648 | 4552 | ||
4649 | else |
4553 | else |
4650 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
4554 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
4651 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); |
4555 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); |
4652 | } |
4556 | } |
4653 | 4557 | ||
4654 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
4558 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
4655 | { |
4559 | { |
4656 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4560 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4657 | if (INTEL_INFO(dev)->gen < 6) |
4561 | if (INTEL_INFO(dev)->gen < 6) |
4658 | return 0; |
4562 | return 0; |
4659 | 4563 | ||
4660 | /* Respect the kernel parameter if it is set */ |
4564 | /* Respect the kernel parameter if it is set */ |
4661 | if (enable_rc6 >= 0) { |
4565 | if (enable_rc6 >= 0) { |
4662 | int mask; |
4566 | int mask; |
4663 | 4567 | ||
4664 | if (HAS_RC6p(dev)) |
4568 | if (HAS_RC6p(dev)) |
4665 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4569 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4666 | INTEL_RC6pp_ENABLE; |
4570 | INTEL_RC6pp_ENABLE; |
4667 | else |
4571 | else |
4668 | mask = INTEL_RC6_ENABLE; |
4572 | mask = INTEL_RC6_ENABLE; |
4669 | 4573 | ||
4670 | if ((enable_rc6 & mask) != enable_rc6) |
4574 | if ((enable_rc6 & mask) != enable_rc6) |
4671 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4575 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4672 | enable_rc6 & mask, enable_rc6, mask); |
4576 | enable_rc6 & mask, enable_rc6, mask); |
4673 | 4577 | ||
4674 | return enable_rc6 & mask; |
4578 | return enable_rc6 & mask; |
4675 | } |
4579 | } |
4676 | 4580 | ||
4677 | if (IS_IVYBRIDGE(dev)) |
4581 | if (IS_IVYBRIDGE(dev)) |
4678 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
4582 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
4679 | 4583 | ||
4680 | return INTEL_RC6_ENABLE; |
4584 | return INTEL_RC6_ENABLE; |
4681 | } |
4585 | } |
4682 | 4586 | ||
4683 | int intel_enable_rc6(const struct drm_device *dev) |
4587 | int intel_enable_rc6(const struct drm_device *dev) |
4684 | { |
4588 | { |
4685 | return i915.enable_rc6; |
4589 | return i915.enable_rc6; |
4686 | } |
4590 | } |
4687 | 4591 | ||
4688 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
4592 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
4689 | { |
4593 | { |
4690 | struct drm_i915_private *dev_priv = dev->dev_private; |
4594 | struct drm_i915_private *dev_priv = dev->dev_private; |
4691 | uint32_t rp_state_cap; |
4595 | uint32_t rp_state_cap; |
4692 | u32 ddcc_status = 0; |
4596 | u32 ddcc_status = 0; |
4693 | int ret; |
4597 | int ret; |
4694 | 4598 | ||
4695 | /* All of these values are in units of 50MHz */ |
4599 | /* All of these values are in units of 50MHz */ |
4696 | dev_priv->rps.cur_freq = 0; |
4600 | dev_priv->rps.cur_freq = 0; |
4697 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
4601 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
4698 | if (IS_BROXTON(dev)) { |
4602 | if (IS_BROXTON(dev)) { |
4699 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
4603 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
4700 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
4604 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
4701 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
4605 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
4702 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; |
4606 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; |
4703 | } else { |
4607 | } else { |
4704 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
4608 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
4705 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
4609 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
4706 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
4610 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
4707 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
4611 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
4708 | } |
4612 | } |
4709 | 4613 | ||
4710 | /* hw_max = RP0 until we check for overclocking */ |
4614 | /* hw_max = RP0 until we check for overclocking */ |
4711 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
4615 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
4712 | 4616 | ||
4713 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
4617 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
4714 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { |
4618 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || |
- | 4619 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
|
4715 | ret = sandybridge_pcode_read(dev_priv, |
4620 | ret = sandybridge_pcode_read(dev_priv, |
4716 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, |
4621 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, |
4717 | &ddcc_status); |
4622 | &ddcc_status); |
4718 | if (0 == ret) |
4623 | if (0 == ret) |
4719 | dev_priv->rps.efficient_freq = |
4624 | dev_priv->rps.efficient_freq = |
4720 | clamp_t(u8, |
4625 | clamp_t(u8, |
4721 | ((ddcc_status >> 8) & 0xff), |
4626 | ((ddcc_status >> 8) & 0xff), |
4722 | dev_priv->rps.min_freq, |
4627 | dev_priv->rps.min_freq, |
4723 | dev_priv->rps.max_freq); |
4628 | dev_priv->rps.max_freq); |
4724 | } |
4629 | } |
4725 | 4630 | ||
4726 | if (IS_SKYLAKE(dev)) { |
4631 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
4727 | /* Store the frequency values in 16.66 MHZ units, which is |
4632 | /* Store the frequency values in 16.66 MHZ units, which is |
4728 | the natural hardware unit for SKL */ |
4633 | the natural hardware unit for SKL */ |
4729 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
4634 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
4730 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; |
4635 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; |
4731 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; |
4636 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; |
4732 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; |
4637 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; |
4733 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; |
4638 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; |
4734 | } |
4639 | } |
4735 | 4640 | ||
4736 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4641 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4737 | 4642 | ||
4738 | /* Preserve min/max settings in case of re-init */ |
4643 | /* Preserve min/max settings in case of re-init */ |
4739 | if (dev_priv->rps.max_freq_softlimit == 0) |
4644 | if (dev_priv->rps.max_freq_softlimit == 0) |
4740 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
4645 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
4741 | 4646 | ||
4742 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4647 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4743 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4648 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4744 | dev_priv->rps.min_freq_softlimit = |
4649 | dev_priv->rps.min_freq_softlimit = |
4745 | max_t(int, dev_priv->rps.efficient_freq, |
4650 | max_t(int, dev_priv->rps.efficient_freq, |
4746 | intel_freq_opcode(dev_priv, 450)); |
4651 | intel_freq_opcode(dev_priv, 450)); |
4747 | else |
4652 | else |
4748 | dev_priv->rps.min_freq_softlimit = |
4653 | dev_priv->rps.min_freq_softlimit = |
4749 | dev_priv->rps.min_freq; |
4654 | dev_priv->rps.min_freq; |
4750 | } |
4655 | } |
4751 | } |
4656 | } |
4752 | 4657 | ||
4753 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
4658 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
4754 | static void gen9_enable_rps(struct drm_device *dev) |
4659 | static void gen9_enable_rps(struct drm_device *dev) |
4755 | { |
4660 | { |
4756 | struct drm_i915_private *dev_priv = dev->dev_private; |
4661 | struct drm_i915_private *dev_priv = dev->dev_private; |
4757 | 4662 | ||
4758 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4663 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4759 | 4664 | ||
4760 | gen6_init_rps_frequencies(dev); |
4665 | gen6_init_rps_frequencies(dev); |
4761 | 4666 | ||
4762 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4667 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4763 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { |
4668 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
4764 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4669 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4765 | return; |
4670 | return; |
4766 | } |
4671 | } |
4767 | 4672 | ||
4768 | /* Program defaults and thresholds for RPS*/ |
4673 | /* Program defaults and thresholds for RPS*/ |
4769 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
4674 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
4770 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); |
4675 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); |
4771 | 4676 | ||
4772 | /* 1 second timeout*/ |
4677 | /* 1 second timeout*/ |
4773 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, |
4678 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, |
4774 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); |
4679 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); |
4775 | 4680 | ||
4776 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
4681 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
4777 | 4682 | ||
4778 | /* Leaning on the below call to gen6_set_rps to program/setup the |
4683 | /* Leaning on the below call to gen6_set_rps to program/setup the |
4779 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, |
4684 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, |
4780 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ |
4685 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ |
4781 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4686 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4782 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
4687 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
4783 | 4688 | ||
4784 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4689 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4785 | } |
4690 | } |
4786 | 4691 | ||
4787 | static void gen9_enable_rc6(struct drm_device *dev) |
4692 | static void gen9_enable_rc6(struct drm_device *dev) |
4788 | { |
4693 | { |
4789 | struct drm_i915_private *dev_priv = dev->dev_private; |
4694 | struct drm_i915_private *dev_priv = dev->dev_private; |
4790 | struct intel_engine_cs *ring; |
4695 | struct intel_engine_cs *ring; |
4791 | uint32_t rc6_mask = 0; |
4696 | uint32_t rc6_mask = 0; |
4792 | int unused; |
4697 | int unused; |
4793 | 4698 | ||
4794 | /* 1a: Software RC state - RC0 */ |
4699 | /* 1a: Software RC state - RC0 */ |
4795 | I915_WRITE(GEN6_RC_STATE, 0); |
4700 | I915_WRITE(GEN6_RC_STATE, 0); |
4796 | 4701 | ||
4797 | /* 1b: Get forcewake during program sequence. Although the driver |
4702 | /* 1b: Get forcewake during program sequence. Although the driver |
4798 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
4703 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
4799 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4704 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4800 | 4705 | ||
4801 | /* 2a: Disable RC states. */ |
4706 | /* 2a: Disable RC states. */ |
4802 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4707 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4803 | 4708 | ||
4804 | /* 2b: Program RC6 thresholds.*/ |
4709 | /* 2b: Program RC6 thresholds.*/ |
4805 | 4710 | ||
4806 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ |
4711 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ |
4807 | if (IS_SKYLAKE(dev)) |
4712 | if (IS_SKYLAKE(dev)) |
4808 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
4713 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
4809 | else |
4714 | else |
4810 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); |
4715 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); |
4811 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4716 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4812 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
4717 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
4813 | for_each_ring(ring, dev_priv, unused) |
4718 | for_each_ring(ring, dev_priv, unused) |
4814 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4719 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4815 | 4720 | ||
4816 | if (HAS_GUC_UCODE(dev)) |
4721 | if (HAS_GUC_UCODE(dev)) |
4817 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
4722 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
4818 | 4723 | ||
4819 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4724 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4820 | 4725 | ||
4821 | /* 2c: Program Coarse Power Gating Policies. */ |
4726 | /* 2c: Program Coarse Power Gating Policies. */ |
4822 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); |
4727 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); |
4823 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
4728 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
4824 | 4729 | ||
4825 | /* 3a: Enable RC6 */ |
4730 | /* 3a: Enable RC6 */ |
4826 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4731 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4827 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4732 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4828 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
4733 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
4829 | "on" : "off"); |
4734 | "on" : "off"); |
4830 | /* WaRsUseTimeoutMode */ |
4735 | /* WaRsUseTimeoutMode */ |
4831 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || |
4736 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
4832 | (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { |
4737 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
4833 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
4738 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
4834 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4739 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4835 | GEN7_RC_CTL_TO_MODE | |
4740 | GEN7_RC_CTL_TO_MODE | |
4836 | rc6_mask); |
4741 | rc6_mask); |
4837 | } else { |
4742 | } else { |
4838 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
4743 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
4839 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4744 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4840 | GEN6_RC_CTL_EI_MODE(1) | |
4745 | GEN6_RC_CTL_EI_MODE(1) | |
4841 | rc6_mask); |
4746 | rc6_mask); |
4842 | } |
4747 | } |
4843 | 4748 | ||
4844 | /* |
4749 | /* |
4845 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. |
4750 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. |
4846 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
4751 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
4847 | */ |
4752 | */ |
4848 | if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || |
4753 | if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || |
4849 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0))) |
4754 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0))) |
4850 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4755 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4851 | else |
4756 | else |
4852 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
4757 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
4853 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); |
4758 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); |
4854 | 4759 | ||
4855 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4760 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4856 | 4761 | ||
4857 | } |
4762 | } |
4858 | 4763 | ||
4859 | static void gen8_enable_rps(struct drm_device *dev) |
4764 | static void gen8_enable_rps(struct drm_device *dev) |
4860 | { |
4765 | { |
4861 | struct drm_i915_private *dev_priv = dev->dev_private; |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; |
4862 | struct intel_engine_cs *ring; |
4767 | struct intel_engine_cs *ring; |
4863 | uint32_t rc6_mask = 0; |
4768 | uint32_t rc6_mask = 0; |
4864 | int unused; |
4769 | int unused; |
4865 | 4770 | ||
4866 | /* 1a: Software RC state - RC0 */ |
4771 | /* 1a: Software RC state - RC0 */ |
4867 | I915_WRITE(GEN6_RC_STATE, 0); |
4772 | I915_WRITE(GEN6_RC_STATE, 0); |
4868 | 4773 | ||
4869 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
4774 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
4870 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
4775 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
4871 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4776 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4872 | 4777 | ||
4873 | /* 2a: Disable RC states. */ |
4778 | /* 2a: Disable RC states. */ |
4874 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4779 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4875 | 4780 | ||
4876 | /* Initialize rps frequencies */ |
4781 | /* Initialize rps frequencies */ |
4877 | gen6_init_rps_frequencies(dev); |
4782 | gen6_init_rps_frequencies(dev); |
4878 | 4783 | ||
4879 | /* 2b: Program RC6 thresholds.*/ |
4784 | /* 2b: Program RC6 thresholds.*/ |
4880 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
4785 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
4881 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4786 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4882 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
4787 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
4883 | for_each_ring(ring, dev_priv, unused) |
4788 | for_each_ring(ring, dev_priv, unused) |
4884 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4789 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4885 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4790 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4886 | if (IS_BROADWELL(dev)) |
4791 | if (IS_BROADWELL(dev)) |
4887 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
4792 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
4888 | else |
4793 | else |
4889 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
4794 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
4890 | 4795 | ||
4891 | /* 3: Enable RC6 */ |
4796 | /* 3: Enable RC6 */ |
4892 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4797 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4893 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4798 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4894 | intel_print_rc6_info(dev, rc6_mask); |
4799 | intel_print_rc6_info(dev, rc6_mask); |
4895 | if (IS_BROADWELL(dev)) |
4800 | if (IS_BROADWELL(dev)) |
4896 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4801 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4897 | GEN7_RC_CTL_TO_MODE | |
4802 | GEN7_RC_CTL_TO_MODE | |
4898 | rc6_mask); |
4803 | rc6_mask); |
4899 | else |
4804 | else |
4900 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4805 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4901 | GEN6_RC_CTL_EI_MODE(1) | |
4806 | GEN6_RC_CTL_EI_MODE(1) | |
4902 | rc6_mask); |
4807 | rc6_mask); |
4903 | 4808 | ||
4904 | /* 4 Program defaults and thresholds for RPS*/ |
4809 | /* 4 Program defaults and thresholds for RPS*/ |
4905 | I915_WRITE(GEN6_RPNSWREQ, |
4810 | I915_WRITE(GEN6_RPNSWREQ, |
4906 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
4811 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
4907 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
4812 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
4908 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
4813 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
4909 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4814 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4910 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
4815 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
4911 | 4816 | ||
4912 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
4817 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
4913 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
4818 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
4914 | dev_priv->rps.max_freq_softlimit << 24 | |
4819 | dev_priv->rps.max_freq_softlimit << 24 | |
4915 | dev_priv->rps.min_freq_softlimit << 16); |
4820 | dev_priv->rps.min_freq_softlimit << 16); |
4916 | 4821 | ||
4917 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
4822 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
4918 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
4823 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
4919 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
4824 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
4920 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
4825 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
4921 | 4826 | ||
4922 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
4827 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
4923 | 4828 | ||
4924 | /* 5: Enable RPS */ |
4829 | /* 5: Enable RPS */ |
4925 | I915_WRITE(GEN6_RP_CONTROL, |
4830 | I915_WRITE(GEN6_RP_CONTROL, |
4926 | GEN6_RP_MEDIA_TURBO | |
4831 | GEN6_RP_MEDIA_TURBO | |
4927 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
4832 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
4928 | GEN6_RP_MEDIA_IS_GFX | |
4833 | GEN6_RP_MEDIA_IS_GFX | |
4929 | GEN6_RP_ENABLE | |
4834 | GEN6_RP_ENABLE | |
4930 | GEN6_RP_UP_BUSY_AVG | |
4835 | GEN6_RP_UP_BUSY_AVG | |
4931 | GEN6_RP_DOWN_IDLE_AVG); |
4836 | GEN6_RP_DOWN_IDLE_AVG); |
4932 | 4837 | ||
4933 | /* 6: Ring frequency + overclocking (our driver does this later */ |
4838 | /* 6: Ring frequency + overclocking (our driver does this later */ |
4934 | 4839 | ||
4935 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4840 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4936 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4841 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4937 | 4842 | ||
4938 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4843 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4939 | } |
4844 | } |
4940 | 4845 | ||
4941 | static void gen6_enable_rps(struct drm_device *dev) |
4846 | static void gen6_enable_rps(struct drm_device *dev) |
4942 | { |
4847 | { |
4943 | struct drm_i915_private *dev_priv = dev->dev_private; |
4848 | struct drm_i915_private *dev_priv = dev->dev_private; |
4944 | struct intel_engine_cs *ring; |
4849 | struct intel_engine_cs *ring; |
4945 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
4850 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
4946 | u32 gtfifodbg; |
4851 | u32 gtfifodbg; |
4947 | int rc6_mode; |
4852 | int rc6_mode; |
4948 | int i, ret; |
4853 | int i, ret; |
4949 | 4854 | ||
4950 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4855 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4951 | 4856 | ||
4952 | /* Here begins a magic sequence of register writes to enable |
4857 | /* Here begins a magic sequence of register writes to enable |
4953 | * auto-downclocking. |
4858 | * auto-downclocking. |
4954 | * |
4859 | * |
4955 | * Perhaps there might be some value in exposing these to |
4860 | * Perhaps there might be some value in exposing these to |
4956 | * userspace... |
4861 | * userspace... |
4957 | */ |
4862 | */ |
4958 | I915_WRITE(GEN6_RC_STATE, 0); |
4863 | I915_WRITE(GEN6_RC_STATE, 0); |
4959 | 4864 | ||
4960 | /* Clear the DBG now so we don't confuse earlier errors */ |
4865 | /* Clear the DBG now so we don't confuse earlier errors */ |
4961 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
4866 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
4962 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
4867 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
4963 | I915_WRITE(GTFIFODBG, gtfifodbg); |
4868 | I915_WRITE(GTFIFODBG, gtfifodbg); |
4964 | } |
4869 | } |
4965 | 4870 | ||
4966 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4871 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
4967 | 4872 | ||
4968 | /* Initialize rps frequencies */ |
4873 | /* Initialize rps frequencies */ |
4969 | gen6_init_rps_frequencies(dev); |
4874 | gen6_init_rps_frequencies(dev); |
4970 | 4875 | ||
4971 | /* disable the counters and set deterministic thresholds */ |
4876 | /* disable the counters and set deterministic thresholds */ |
4972 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4877 | I915_WRITE(GEN6_RC_CONTROL, 0); |
4973 | 4878 | ||
4974 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
4879 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
4975 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
4880 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
4976 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
4881 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
4977 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
4882 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
4978 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
4883 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
4979 | 4884 | ||
4980 | for_each_ring(ring, dev_priv, i) |
4885 | for_each_ring(ring, dev_priv, i) |
4981 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4886 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
4982 | 4887 | ||
4983 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4888 | I915_WRITE(GEN6_RC_SLEEP, 0); |
4984 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
4889 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
4985 | if (IS_IVYBRIDGE(dev)) |
4890 | if (IS_IVYBRIDGE(dev)) |
4986 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4891 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4987 | else |
4892 | else |
4988 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
4893 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
4989 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
4894 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
4990 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4895 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4991 | 4896 | ||
4992 | /* Check if we are enabling RC6 */ |
4897 | /* Check if we are enabling RC6 */ |
4993 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4898 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4994 | if (rc6_mode & INTEL_RC6_ENABLE) |
4899 | if (rc6_mode & INTEL_RC6_ENABLE) |
4995 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
4900 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
4996 | 4901 | ||
4997 | /* We don't use those on Haswell */ |
4902 | /* We don't use those on Haswell */ |
4998 | if (!IS_HASWELL(dev)) { |
4903 | if (!IS_HASWELL(dev)) { |
4999 | if (rc6_mode & INTEL_RC6p_ENABLE) |
4904 | if (rc6_mode & INTEL_RC6p_ENABLE) |
5000 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
4905 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
5001 | 4906 | ||
5002 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4907 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
5003 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
4908 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
5004 | } |
4909 | } |
5005 | 4910 | ||
5006 | intel_print_rc6_info(dev, rc6_mask); |
4911 | intel_print_rc6_info(dev, rc6_mask); |
5007 | 4912 | ||
5008 | I915_WRITE(GEN6_RC_CONTROL, |
4913 | I915_WRITE(GEN6_RC_CONTROL, |
5009 | rc6_mask | |
4914 | rc6_mask | |
5010 | GEN6_RC_CTL_EI_MODE(1) | |
4915 | GEN6_RC_CTL_EI_MODE(1) | |
5011 | GEN6_RC_CTL_HW_ENABLE); |
4916 | GEN6_RC_CTL_HW_ENABLE); |
5012 | 4917 | ||
5013 | /* Power down if completely idle for over 50ms */ |
4918 | /* Power down if completely idle for over 50ms */ |
5014 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
4919 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
5015 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
4920 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
5016 | 4921 | ||
5017 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
4922 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
5018 | if (ret) |
4923 | if (ret) |
5019 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
4924 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
5020 | 4925 | ||
5021 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
4926 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
5022 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
4927 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
5023 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
4928 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
5024 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
4929 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
5025 | (pcu_mbox & 0xff) * 50); |
4930 | (pcu_mbox & 0xff) * 50); |
5026 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
4931 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
5027 | } |
4932 | } |
5028 | 4933 | ||
5029 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4934 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
5030 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4935 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
5031 | 4936 | ||
5032 | rc6vids = 0; |
4937 | rc6vids = 0; |
5033 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
4938 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
5034 | if (IS_GEN6(dev) && ret) { |
4939 | if (IS_GEN6(dev) && ret) { |
5035 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
4940 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
5036 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
4941 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
5037 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
4942 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
5038 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
4943 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
5039 | rc6vids &= 0xffff00; |
4944 | rc6vids &= 0xffff00; |
5040 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
4945 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
5041 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
4946 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
5042 | if (ret) |
4947 | if (ret) |
5043 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
4948 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
5044 | } |
4949 | } |
5045 | 4950 | ||
5046 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4951 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
5047 | } |
4952 | } |
5048 | 4953 | ||
5049 | static void __gen6_update_ring_freq(struct drm_device *dev) |
4954 | static void __gen6_update_ring_freq(struct drm_device *dev) |
5050 | { |
4955 | { |
5051 | struct drm_i915_private *dev_priv = dev->dev_private; |
4956 | struct drm_i915_private *dev_priv = dev->dev_private; |
5052 | int min_freq = 15; |
4957 | int min_freq = 15; |
5053 | unsigned int gpu_freq; |
4958 | unsigned int gpu_freq; |
5054 | unsigned int max_ia_freq, min_ring_freq; |
4959 | unsigned int max_ia_freq, min_ring_freq; |
5055 | unsigned int max_gpu_freq, min_gpu_freq; |
4960 | unsigned int max_gpu_freq, min_gpu_freq; |
5056 | int scaling_factor = 180; |
4961 | int scaling_factor = 180; |
5057 | struct cpufreq_policy *policy; |
4962 | struct cpufreq_policy *policy; |
5058 | 4963 | ||
5059 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4964 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
5060 | 4965 | ||
5061 | max_ia_freq = cpufreq_quick_get_max(0); |
4966 | max_ia_freq = cpufreq_quick_get_max(0); |
5062 | /* |
4967 | /* |
5063 | * Default to measured freq if none found, PCU will ensure we |
4968 | * Default to measured freq if none found, PCU will ensure we |
5064 | * don't go over |
4969 | * don't go over |
5065 | */ |
4970 | */ |
5066 | max_ia_freq = tsc_khz; |
4971 | max_ia_freq = tsc_khz; |
5067 | 4972 | ||
5068 | /* Convert from kHz to MHz */ |
4973 | /* Convert from kHz to MHz */ |
5069 | max_ia_freq /= 1000; |
4974 | max_ia_freq /= 1000; |
5070 | 4975 | ||
5071 | min_ring_freq = I915_READ(DCLK) & 0xf; |
4976 | min_ring_freq = I915_READ(DCLK) & 0xf; |
5072 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4977 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
5073 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
4978 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
5074 | 4979 | ||
5075 | if (IS_SKYLAKE(dev)) { |
4980 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
5076 | /* Convert GT frequency to 50 HZ units */ |
4981 | /* Convert GT frequency to 50 HZ units */ |
5077 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; |
4982 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; |
5078 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; |
4983 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; |
5079 | } else { |
4984 | } else { |
5080 | min_gpu_freq = dev_priv->rps.min_freq; |
4985 | min_gpu_freq = dev_priv->rps.min_freq; |
5081 | max_gpu_freq = dev_priv->rps.max_freq; |
4986 | max_gpu_freq = dev_priv->rps.max_freq; |
5082 | } |
4987 | } |
5083 | 4988 | ||
5084 | /* |
4989 | /* |
5085 | * For each potential GPU frequency, load a ring frequency we'd like |
4990 | * For each potential GPU frequency, load a ring frequency we'd like |
5086 | * to use for memory access. We do this by specifying the IA frequency |
4991 | * to use for memory access. We do this by specifying the IA frequency |
5087 | * the PCU should use as a reference to determine the ring frequency. |
4992 | * the PCU should use as a reference to determine the ring frequency. |
5088 | */ |
4993 | */ |
5089 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
4994 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
5090 | int diff = max_gpu_freq - gpu_freq; |
4995 | int diff = max_gpu_freq - gpu_freq; |
5091 | unsigned int ia_freq = 0, ring_freq = 0; |
4996 | unsigned int ia_freq = 0, ring_freq = 0; |
5092 | 4997 | ||
5093 | if (IS_SKYLAKE(dev)) { |
4998 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
5094 | /* |
4999 | /* |
5095 | * ring_freq = 2 * GT. ring_freq is in 100MHz units |
5000 | * ring_freq = 2 * GT. ring_freq is in 100MHz units |
5096 | * No floor required for ring frequency on SKL. |
5001 | * No floor required for ring frequency on SKL. |
5097 | */ |
5002 | */ |
5098 | ring_freq = gpu_freq; |
5003 | ring_freq = gpu_freq; |
5099 | } else if (INTEL_INFO(dev)->gen >= 8) { |
5004 | } else if (INTEL_INFO(dev)->gen >= 8) { |
5100 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
5005 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
5101 | ring_freq = max(min_ring_freq, gpu_freq); |
5006 | ring_freq = max(min_ring_freq, gpu_freq); |
5102 | } else if (IS_HASWELL(dev)) { |
5007 | } else if (IS_HASWELL(dev)) { |
5103 | ring_freq = mult_frac(gpu_freq, 5, 4); |
5008 | ring_freq = mult_frac(gpu_freq, 5, 4); |
5104 | ring_freq = max(min_ring_freq, ring_freq); |
5009 | ring_freq = max(min_ring_freq, ring_freq); |
5105 | /* leave ia_freq as the default, chosen by cpufreq */ |
5010 | /* leave ia_freq as the default, chosen by cpufreq */ |
5106 | } else { |
5011 | } else { |
5107 | /* On older processors, there is no separate ring |
5012 | /* On older processors, there is no separate ring |
5108 | * clock domain, so in order to boost the bandwidth |
5013 | * clock domain, so in order to boost the bandwidth |
5109 | * of the ring, we need to upclock the CPU (ia_freq). |
5014 | * of the ring, we need to upclock the CPU (ia_freq). |
5110 | * |
5015 | * |
5111 | * For GPU frequencies less than 750MHz, |
5016 | * For GPU frequencies less than 750MHz, |
5112 | * just use the lowest ring freq. |
5017 | * just use the lowest ring freq. |
5113 | */ |
5018 | */ |
5114 | if (gpu_freq < min_freq) |
5019 | if (gpu_freq < min_freq) |
5115 | ia_freq = 800; |
5020 | ia_freq = 800; |
5116 | else |
5021 | else |
5117 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
5022 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
5118 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
5023 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
5119 | } |
5024 | } |
5120 | 5025 | ||
5121 | sandybridge_pcode_write(dev_priv, |
5026 | sandybridge_pcode_write(dev_priv, |
5122 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
5027 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
5123 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
5028 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
5124 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
5029 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
5125 | gpu_freq); |
5030 | gpu_freq); |
5126 | } |
5031 | } |
5127 | } |
5032 | } |
5128 | 5033 | ||
5129 | void gen6_update_ring_freq(struct drm_device *dev) |
5034 | void gen6_update_ring_freq(struct drm_device *dev) |
5130 | { |
5035 | { |
5131 | struct drm_i915_private *dev_priv = dev->dev_private; |
5036 | struct drm_i915_private *dev_priv = dev->dev_private; |
5132 | 5037 | ||
5133 | if (!HAS_CORE_RING_FREQ(dev)) |
5038 | if (!HAS_CORE_RING_FREQ(dev)) |
5134 | return; |
5039 | return; |
5135 | 5040 | ||
5136 | mutex_lock(&dev_priv->rps.hw_lock); |
5041 | mutex_lock(&dev_priv->rps.hw_lock); |
5137 | __gen6_update_ring_freq(dev); |
5042 | __gen6_update_ring_freq(dev); |
5138 | mutex_unlock(&dev_priv->rps.hw_lock); |
5043 | mutex_unlock(&dev_priv->rps.hw_lock); |
5139 | } |
5044 | } |
5140 | 5045 | ||
5141 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
5046 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
5142 | { |
5047 | { |
5143 | struct drm_device *dev = dev_priv->dev; |
5048 | struct drm_device *dev = dev_priv->dev; |
5144 | u32 val, rp0; |
5049 | u32 val, rp0; |
5145 | 5050 | ||
5146 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5051 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5147 | 5052 | ||
5148 | switch (INTEL_INFO(dev)->eu_total) { |
5053 | switch (INTEL_INFO(dev)->eu_total) { |
5149 | case 8: |
5054 | case 8: |
5150 | /* (2 * 4) config */ |
5055 | /* (2 * 4) config */ |
5151 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); |
5056 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); |
5152 | break; |
5057 | break; |
5153 | case 12: |
5058 | case 12: |
5154 | /* (2 * 6) config */ |
5059 | /* (2 * 6) config */ |
5155 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); |
5060 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); |
5156 | break; |
5061 | break; |
5157 | case 16: |
5062 | case 16: |
5158 | /* (2 * 8) config */ |
5063 | /* (2 * 8) config */ |
5159 | default: |
5064 | default: |
5160 | /* Setting (2 * 8) Min RP0 for any other combination */ |
5065 | /* Setting (2 * 8) Min RP0 for any other combination */ |
5161 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); |
5066 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); |
5162 | break; |
5067 | break; |
5163 | } |
5068 | } |
5164 | 5069 | ||
5165 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); |
5070 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); |
5166 | 5071 | ||
5167 | return rp0; |
5072 | return rp0; |
5168 | } |
5073 | } |
5169 | 5074 | ||
5170 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
5075 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
5171 | { |
5076 | { |
5172 | u32 val, rpe; |
5077 | u32 val, rpe; |
5173 | 5078 | ||
5174 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); |
5079 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); |
5175 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; |
5080 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; |
5176 | 5081 | ||
5177 | return rpe; |
5082 | return rpe; |
5178 | } |
5083 | } |
5179 | 5084 | ||
5180 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5085 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5181 | { |
5086 | { |
5182 | u32 val, rp1; |
5087 | u32 val, rp1; |
5183 | 5088 | ||
5184 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5089 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5185 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); |
5090 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); |
5186 | 5091 | ||
5187 | return rp1; |
5092 | return rp1; |
5188 | } |
5093 | } |
5189 | 5094 | ||
5190 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5095 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5191 | { |
5096 | { |
5192 | u32 val, rp1; |
5097 | u32 val, rp1; |
5193 | 5098 | ||
5194 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
5099 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
5195 | 5100 | ||
5196 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; |
5101 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; |
5197 | 5102 | ||
5198 | return rp1; |
5103 | return rp1; |
5199 | } |
5104 | } |
5200 | 5105 | ||
5201 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
5106 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
5202 | { |
5107 | { |
5203 | u32 val, rp0; |
5108 | u32 val, rp0; |
5204 | 5109 | ||
5205 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
5110 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
5206 | 5111 | ||
5207 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
5112 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
5208 | /* Clamp to max */ |
5113 | /* Clamp to max */ |
5209 | rp0 = min_t(u32, rp0, 0xea); |
5114 | rp0 = min_t(u32, rp0, 0xea); |
5210 | 5115 | ||
5211 | return rp0; |
5116 | return rp0; |
5212 | } |
5117 | } |
5213 | 5118 | ||
5214 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
5119 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
5215 | { |
5120 | { |
5216 | u32 val, rpe; |
5121 | u32 val, rpe; |
5217 | 5122 | ||
5218 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
5123 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
5219 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
5124 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
5220 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
5125 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
5221 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
5126 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
5222 | 5127 | ||
5223 | return rpe; |
5128 | return rpe; |
5224 | } |
5129 | } |
5225 | 5130 | ||
5226 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
5131 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
5227 | { |
5132 | { |
- | 5133 | u32 val; |
|
- | 5134 | ||
5228 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
5135 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
- | 5136 | /* |
|
- | 5137 | * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value |
|
- | 5138 | * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on |
|
- | 5139 | * a BYT-M B0 the above register contains 0xbf. Moreover when setting |
|
- | 5140 | * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 |
|
- | 5141 | * to make sure it matches what Punit accepts. |
|
- | 5142 | */ |
|
- | 5143 | return max_t(u32, val, 0xc0); |
|
5229 | } |
5144 | } |
5230 | 5145 | ||
5231 | /* Check that the pctx buffer wasn't move under us. */ |
5146 | /* Check that the pctx buffer wasn't move under us. */ |
5232 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
5147 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
5233 | { |
5148 | { |
5234 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
5149 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
5235 | 5150 | ||
5236 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
5151 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
5237 | dev_priv->vlv_pctx->stolen->start); |
5152 | dev_priv->vlv_pctx->stolen->start); |
5238 | } |
5153 | } |
5239 | 5154 | ||
5240 | 5155 | ||
5241 | /* Check that the pcbr address is not empty. */ |
5156 | /* Check that the pcbr address is not empty. */ |
5242 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) |
5157 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) |
5243 | { |
5158 | { |
5244 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
5159 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
5245 | 5160 | ||
5246 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); |
5161 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); |
5247 | } |
5162 | } |
5248 | 5163 | ||
5249 | static void cherryview_setup_pctx(struct drm_device *dev) |
5164 | static void cherryview_setup_pctx(struct drm_device *dev) |
5250 | { |
5165 | { |
5251 | struct drm_i915_private *dev_priv = dev->dev_private; |
5166 | struct drm_i915_private *dev_priv = dev->dev_private; |
5252 | unsigned long pctx_paddr, paddr; |
5167 | unsigned long pctx_paddr, paddr; |
5253 | struct i915_gtt *gtt = &dev_priv->gtt; |
5168 | struct i915_gtt *gtt = &dev_priv->gtt; |
5254 | u32 pcbr; |
5169 | u32 pcbr; |
5255 | int pctx_size = 32*1024; |
5170 | int pctx_size = 32*1024; |
5256 | 5171 | ||
5257 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5172 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5258 | 5173 | ||
5259 | pcbr = I915_READ(VLV_PCBR); |
5174 | pcbr = I915_READ(VLV_PCBR); |
5260 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
5175 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
5261 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5176 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5262 | paddr = (dev_priv->mm.stolen_base + |
5177 | paddr = (dev_priv->mm.stolen_base + |
5263 | (gtt->stolen_size - pctx_size)); |
5178 | (gtt->stolen_size - pctx_size)); |
5264 | 5179 | ||
5265 | pctx_paddr = (paddr & (~4095)); |
5180 | pctx_paddr = (paddr & (~4095)); |
5266 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5181 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5267 | } |
5182 | } |
5268 | 5183 | ||
5269 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
5184 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
5270 | } |
5185 | } |
5271 | 5186 | ||
5272 | static void valleyview_setup_pctx(struct drm_device *dev) |
5187 | static void valleyview_setup_pctx(struct drm_device *dev) |
5273 | { |
5188 | { |
5274 | struct drm_i915_private *dev_priv = dev->dev_private; |
5189 | struct drm_i915_private *dev_priv = dev->dev_private; |
5275 | struct drm_i915_gem_object *pctx; |
5190 | struct drm_i915_gem_object *pctx; |
5276 | unsigned long pctx_paddr; |
5191 | unsigned long pctx_paddr; |
5277 | u32 pcbr; |
5192 | u32 pcbr; |
5278 | int pctx_size = 24*1024; |
5193 | int pctx_size = 24*1024; |
5279 | 5194 | ||
5280 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5195 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5281 | 5196 | ||
5282 | pcbr = I915_READ(VLV_PCBR); |
5197 | pcbr = I915_READ(VLV_PCBR); |
5283 | if (pcbr) { |
5198 | if (pcbr) { |
5284 | /* BIOS set it up already, grab the pre-alloc'd space */ |
5199 | /* BIOS set it up already, grab the pre-alloc'd space */ |
5285 | int pcbr_offset; |
5200 | int pcbr_offset; |
5286 | 5201 | ||
5287 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
5202 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
5288 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
5203 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
5289 | pcbr_offset, |
5204 | pcbr_offset, |
5290 | I915_GTT_OFFSET_NONE, |
5205 | I915_GTT_OFFSET_NONE, |
5291 | pctx_size); |
5206 | pctx_size); |
5292 | goto out; |
5207 | goto out; |
5293 | } |
5208 | } |
5294 | 5209 | ||
5295 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5210 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5296 | 5211 | ||
5297 | /* |
5212 | /* |
5298 | * From the Gunit register HAS: |
5213 | * From the Gunit register HAS: |
5299 | * The Gfx driver is expected to program this register and ensure |
5214 | * The Gfx driver is expected to program this register and ensure |
5300 | * proper allocation within Gfx stolen memory. For example, this |
5215 | * proper allocation within Gfx stolen memory. For example, this |
5301 | * register should be programmed such than the PCBR range does not |
5216 | * register should be programmed such than the PCBR range does not |
5302 | * overlap with other ranges, such as the frame buffer, protected |
5217 | * overlap with other ranges, such as the frame buffer, protected |
5303 | * memory, or any other relevant ranges. |
5218 | * memory, or any other relevant ranges. |
5304 | */ |
5219 | */ |
5305 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
5220 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
5306 | if (!pctx) { |
5221 | if (!pctx) { |
5307 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
5222 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
5308 | return; |
5223 | return; |
5309 | } |
5224 | } |
5310 | 5225 | ||
5311 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
5226 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
5312 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5227 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5313 | 5228 | ||
5314 | out: |
5229 | out: |
5315 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
5230 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
5316 | dev_priv->vlv_pctx = pctx; |
5231 | dev_priv->vlv_pctx = pctx; |
5317 | } |
5232 | } |
5318 | 5233 | ||
5319 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5234 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5320 | { |
5235 | { |
5321 | struct drm_i915_private *dev_priv = dev->dev_private; |
5236 | struct drm_i915_private *dev_priv = dev->dev_private; |
5322 | 5237 | ||
5323 | if (WARN_ON(!dev_priv->vlv_pctx)) |
5238 | if (WARN_ON(!dev_priv->vlv_pctx)) |
5324 | return; |
5239 | return; |
5325 | 5240 | ||
5326 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
5241 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
5327 | dev_priv->vlv_pctx = NULL; |
5242 | dev_priv->vlv_pctx = NULL; |
5328 | } |
5243 | } |
5329 | 5244 | ||
5330 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
5245 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
5331 | { |
5246 | { |
5332 | struct drm_i915_private *dev_priv = dev->dev_private; |
5247 | struct drm_i915_private *dev_priv = dev->dev_private; |
5333 | u32 val; |
5248 | u32 val; |
5334 | 5249 | ||
5335 | valleyview_setup_pctx(dev); |
5250 | valleyview_setup_pctx(dev); |
5336 | 5251 | ||
5337 | mutex_lock(&dev_priv->rps.hw_lock); |
5252 | mutex_lock(&dev_priv->rps.hw_lock); |
5338 | 5253 | ||
5339 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5254 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5340 | switch ((val >> 6) & 3) { |
5255 | switch ((val >> 6) & 3) { |
5341 | case 0: |
5256 | case 0: |
5342 | case 1: |
5257 | case 1: |
5343 | dev_priv->mem_freq = 800; |
5258 | dev_priv->mem_freq = 800; |
5344 | break; |
5259 | break; |
5345 | case 2: |
5260 | case 2: |
5346 | dev_priv->mem_freq = 1066; |
5261 | dev_priv->mem_freq = 1066; |
5347 | break; |
5262 | break; |
5348 | case 3: |
5263 | case 3: |
5349 | dev_priv->mem_freq = 1333; |
5264 | dev_priv->mem_freq = 1333; |
5350 | break; |
5265 | break; |
5351 | } |
5266 | } |
5352 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
5267 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
5353 | 5268 | ||
5354 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
5269 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
5355 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
5270 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
5356 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
5271 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
5357 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
5272 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
5358 | dev_priv->rps.max_freq); |
5273 | dev_priv->rps.max_freq); |
5359 | 5274 | ||
5360 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
5275 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
5361 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
5276 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
5362 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5277 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5363 | dev_priv->rps.efficient_freq); |
5278 | dev_priv->rps.efficient_freq); |
5364 | 5279 | ||
5365 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
5280 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
5366 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", |
5281 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", |
5367 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
5282 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
5368 | dev_priv->rps.rp1_freq); |
5283 | dev_priv->rps.rp1_freq); |
5369 | 5284 | ||
5370 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
5285 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
5371 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
5286 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
5372 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
5287 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
5373 | dev_priv->rps.min_freq); |
5288 | dev_priv->rps.min_freq); |
5374 | 5289 | ||
5375 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5290 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5376 | 5291 | ||
5377 | /* Preserve min/max settings in case of re-init */ |
5292 | /* Preserve min/max settings in case of re-init */ |
5378 | if (dev_priv->rps.max_freq_softlimit == 0) |
5293 | if (dev_priv->rps.max_freq_softlimit == 0) |
5379 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
5294 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
5380 | 5295 | ||
5381 | if (dev_priv->rps.min_freq_softlimit == 0) |
5296 | if (dev_priv->rps.min_freq_softlimit == 0) |
5382 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
5297 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
5383 | 5298 | ||
5384 | mutex_unlock(&dev_priv->rps.hw_lock); |
5299 | mutex_unlock(&dev_priv->rps.hw_lock); |
5385 | } |
5300 | } |
5386 | 5301 | ||
5387 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
5302 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
5388 | { |
5303 | { |
5389 | struct drm_i915_private *dev_priv = dev->dev_private; |
5304 | struct drm_i915_private *dev_priv = dev->dev_private; |
5390 | u32 val; |
5305 | u32 val; |
5391 | 5306 | ||
5392 | cherryview_setup_pctx(dev); |
5307 | cherryview_setup_pctx(dev); |
5393 | 5308 | ||
5394 | mutex_lock(&dev_priv->rps.hw_lock); |
5309 | mutex_lock(&dev_priv->rps.hw_lock); |
5395 | 5310 | ||
5396 | mutex_lock(&dev_priv->sb_lock); |
5311 | mutex_lock(&dev_priv->sb_lock); |
5397 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
5312 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
5398 | mutex_unlock(&dev_priv->sb_lock); |
5313 | mutex_unlock(&dev_priv->sb_lock); |
5399 | 5314 | ||
5400 | switch ((val >> 2) & 0x7) { |
5315 | switch ((val >> 2) & 0x7) { |
5401 | case 3: |
5316 | case 3: |
5402 | dev_priv->mem_freq = 2000; |
5317 | dev_priv->mem_freq = 2000; |
5403 | break; |
5318 | break; |
5404 | default: |
5319 | default: |
5405 | dev_priv->mem_freq = 1600; |
5320 | dev_priv->mem_freq = 1600; |
5406 | break; |
5321 | break; |
5407 | } |
5322 | } |
5408 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
5323 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
5409 | 5324 | ||
5410 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
5325 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
5411 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
5326 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
5412 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
5327 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
5413 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
5328 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
5414 | dev_priv->rps.max_freq); |
5329 | dev_priv->rps.max_freq); |
5415 | 5330 | ||
5416 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); |
5331 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); |
5417 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
5332 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
5418 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5333 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5419 | dev_priv->rps.efficient_freq); |
5334 | dev_priv->rps.efficient_freq); |
5420 | 5335 | ||
5421 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5336 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5422 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", |
5337 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", |
5423 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
5338 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
5424 | dev_priv->rps.rp1_freq); |
5339 | dev_priv->rps.rp1_freq); |
5425 | 5340 | ||
5426 | /* PUnit validated range is only [RPe, RP0] */ |
5341 | /* PUnit validated range is only [RPe, RP0] */ |
5427 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; |
5342 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; |
5428 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
5343 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
5429 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
5344 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
5430 | dev_priv->rps.min_freq); |
5345 | dev_priv->rps.min_freq); |
5431 | 5346 | ||
5432 | WARN_ONCE((dev_priv->rps.max_freq | |
5347 | WARN_ONCE((dev_priv->rps.max_freq | |
5433 | dev_priv->rps.efficient_freq | |
5348 | dev_priv->rps.efficient_freq | |
5434 | dev_priv->rps.rp1_freq | |
5349 | dev_priv->rps.rp1_freq | |
5435 | dev_priv->rps.min_freq) & 1, |
5350 | dev_priv->rps.min_freq) & 1, |
5436 | "Odd GPU freq values\n"); |
5351 | "Odd GPU freq values\n"); |
5437 | 5352 | ||
5438 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5353 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5439 | 5354 | ||
5440 | /* Preserve min/max settings in case of re-init */ |
5355 | /* Preserve min/max settings in case of re-init */ |
5441 | if (dev_priv->rps.max_freq_softlimit == 0) |
5356 | if (dev_priv->rps.max_freq_softlimit == 0) |
5442 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
5357 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
5443 | 5358 | ||
5444 | if (dev_priv->rps.min_freq_softlimit == 0) |
5359 | if (dev_priv->rps.min_freq_softlimit == 0) |
5445 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
5360 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
5446 | 5361 | ||
5447 | mutex_unlock(&dev_priv->rps.hw_lock); |
5362 | mutex_unlock(&dev_priv->rps.hw_lock); |
5448 | } |
5363 | } |
5449 | 5364 | ||
5450 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5365 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5451 | { |
5366 | { |
5452 | valleyview_cleanup_pctx(dev); |
5367 | valleyview_cleanup_pctx(dev); |
5453 | } |
5368 | } |
5454 | 5369 | ||
5455 | static void cherryview_enable_rps(struct drm_device *dev) |
5370 | static void cherryview_enable_rps(struct drm_device *dev) |
5456 | { |
5371 | { |
5457 | struct drm_i915_private *dev_priv = dev->dev_private; |
5372 | struct drm_i915_private *dev_priv = dev->dev_private; |
5458 | struct intel_engine_cs *ring; |
5373 | struct intel_engine_cs *ring; |
5459 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
5374 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
5460 | int i; |
5375 | int i; |
5461 | 5376 | ||
5462 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
5377 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
5463 | 5378 | ||
5464 | gtfifodbg = I915_READ(GTFIFODBG); |
5379 | gtfifodbg = I915_READ(GTFIFODBG); |
5465 | if (gtfifodbg) { |
5380 | if (gtfifodbg) { |
5466 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5381 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5467 | gtfifodbg); |
5382 | gtfifodbg); |
5468 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5383 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5469 | } |
5384 | } |
5470 | 5385 | ||
5471 | cherryview_check_pctx(dev_priv); |
5386 | cherryview_check_pctx(dev_priv); |
5472 | 5387 | ||
5473 | /* 1a & 1b: Get forcewake during program sequence. Although the driver |
5388 | /* 1a & 1b: Get forcewake during program sequence. Although the driver |
5474 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
5389 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
5475 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5390 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5476 | 5391 | ||
5477 | /* Disable RC states. */ |
5392 | /* Disable RC states. */ |
5478 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5393 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5479 | 5394 | ||
5480 | /* 2a: Program RC6 thresholds.*/ |
5395 | /* 2a: Program RC6 thresholds.*/ |
5481 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
5396 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
5482 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
5397 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
5483 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
5398 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
5484 | 5399 | ||
5485 | for_each_ring(ring, dev_priv, i) |
5400 | for_each_ring(ring, dev_priv, i) |
5486 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
5401 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
5487 | I915_WRITE(GEN6_RC_SLEEP, 0); |
5402 | I915_WRITE(GEN6_RC_SLEEP, 0); |
5488 | 5403 | ||
5489 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
5404 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
5490 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); |
5405 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); |
5491 | 5406 | ||
5492 | /* allows RC6 residency counter to work */ |
5407 | /* allows RC6 residency counter to work */ |
5493 | I915_WRITE(VLV_COUNTER_CONTROL, |
5408 | I915_WRITE(VLV_COUNTER_CONTROL, |
5494 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
5409 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
5495 | VLV_MEDIA_RC6_COUNT_EN | |
5410 | VLV_MEDIA_RC6_COUNT_EN | |
5496 | VLV_RENDER_RC6_COUNT_EN)); |
5411 | VLV_RENDER_RC6_COUNT_EN)); |
5497 | 5412 | ||
5498 | /* For now we assume BIOS is allocating and populating the PCBR */ |
5413 | /* For now we assume BIOS is allocating and populating the PCBR */ |
5499 | pcbr = I915_READ(VLV_PCBR); |
5414 | pcbr = I915_READ(VLV_PCBR); |
5500 | 5415 | ||
5501 | /* 3: Enable RC6 */ |
5416 | /* 3: Enable RC6 */ |
5502 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && |
5417 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && |
5503 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) |
5418 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) |
5504 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
5419 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
5505 | 5420 | ||
5506 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
5421 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
5507 | 5422 | ||
5508 | /* 4 Program defaults and thresholds for RPS*/ |
5423 | /* 4 Program defaults and thresholds for RPS*/ |
5509 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
5424 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
5510 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5425 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5511 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
5426 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
5512 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
5427 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
5513 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
5428 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
5514 | 5429 | ||
5515 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
5430 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
5516 | 5431 | ||
5517 | /* 5: Enable RPS */ |
5432 | /* 5: Enable RPS */ |
5518 | I915_WRITE(GEN6_RP_CONTROL, |
5433 | I915_WRITE(GEN6_RP_CONTROL, |
5519 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
5434 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
5520 | GEN6_RP_MEDIA_IS_GFX | |
5435 | GEN6_RP_MEDIA_IS_GFX | |
5521 | GEN6_RP_ENABLE | |
5436 | GEN6_RP_ENABLE | |
5522 | GEN6_RP_UP_BUSY_AVG | |
5437 | GEN6_RP_UP_BUSY_AVG | |
5523 | GEN6_RP_DOWN_IDLE_AVG); |
5438 | GEN6_RP_DOWN_IDLE_AVG); |
5524 | 5439 | ||
5525 | /* Setting Fixed Bias */ |
5440 | /* Setting Fixed Bias */ |
5526 | val = VLV_OVERRIDE_EN | |
5441 | val = VLV_OVERRIDE_EN | |
5527 | VLV_SOC_TDP_EN | |
5442 | VLV_SOC_TDP_EN | |
5528 | CHV_BIAS_CPU_50_SOC_50; |
5443 | CHV_BIAS_CPU_50_SOC_50; |
5529 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
5444 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
5530 | 5445 | ||
5531 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5446 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5532 | 5447 | ||
5533 | /* RPS code assumes GPLL is used */ |
5448 | /* RPS code assumes GPLL is used */ |
5534 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
5449 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
5535 | 5450 | ||
5536 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
5451 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
5537 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5452 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5538 | 5453 | ||
5539 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
5454 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
5540 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
5455 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
5541 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
5456 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
5542 | dev_priv->rps.cur_freq); |
5457 | dev_priv->rps.cur_freq); |
5543 | 5458 | ||
5544 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
5459 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
5545 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5460 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5546 | dev_priv->rps.efficient_freq); |
5461 | dev_priv->rps.efficient_freq); |
5547 | 5462 | ||
5548 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
5463 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
5549 | 5464 | ||
5550 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
5465 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
5551 | } |
5466 | } |
5552 | 5467 | ||
5553 | static void valleyview_enable_rps(struct drm_device *dev) |
5468 | static void valleyview_enable_rps(struct drm_device *dev) |
5554 | { |
5469 | { |
5555 | struct drm_i915_private *dev_priv = dev->dev_private; |
5470 | struct drm_i915_private *dev_priv = dev->dev_private; |
5556 | struct intel_engine_cs *ring; |
5471 | struct intel_engine_cs *ring; |
5557 | u32 gtfifodbg, val, rc6_mode = 0; |
5472 | u32 gtfifodbg, val, rc6_mode = 0; |
5558 | int i; |
5473 | int i; |
5559 | 5474 | ||
5560 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
5475 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
5561 | 5476 | ||
5562 | valleyview_check_pctx(dev_priv); |
5477 | valleyview_check_pctx(dev_priv); |
5563 | 5478 | ||
5564 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
5479 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
5565 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5480 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5566 | gtfifodbg); |
5481 | gtfifodbg); |
5567 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5482 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5568 | } |
5483 | } |
5569 | 5484 | ||
5570 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
5485 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
5571 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5486 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5572 | 5487 | ||
5573 | /* Disable RC states. */ |
5488 | /* Disable RC states. */ |
5574 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5489 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5575 | 5490 | ||
5576 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
5491 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
5577 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5492 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5578 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
5493 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
5579 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
5494 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
5580 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
5495 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
5581 | 5496 | ||
5582 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
5497 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
5583 | 5498 | ||
5584 | I915_WRITE(GEN6_RP_CONTROL, |
5499 | I915_WRITE(GEN6_RP_CONTROL, |
5585 | GEN6_RP_MEDIA_TURBO | |
5500 | GEN6_RP_MEDIA_TURBO | |
5586 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
5501 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
5587 | GEN6_RP_MEDIA_IS_GFX | |
5502 | GEN6_RP_MEDIA_IS_GFX | |
5588 | GEN6_RP_ENABLE | |
5503 | GEN6_RP_ENABLE | |
5589 | GEN6_RP_UP_BUSY_AVG | |
5504 | GEN6_RP_UP_BUSY_AVG | |
5590 | GEN6_RP_DOWN_IDLE_CONT); |
5505 | GEN6_RP_DOWN_IDLE_CONT); |
5591 | 5506 | ||
5592 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
5507 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
5593 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
5508 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
5594 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
5509 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
5595 | 5510 | ||
5596 | for_each_ring(ring, dev_priv, i) |
5511 | for_each_ring(ring, dev_priv, i) |
5597 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
5512 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
5598 | 5513 | ||
5599 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
5514 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
5600 | 5515 | ||
5601 | /* allows RC6 residency counter to work */ |
5516 | /* allows RC6 residency counter to work */ |
5602 | I915_WRITE(VLV_COUNTER_CONTROL, |
5517 | I915_WRITE(VLV_COUNTER_CONTROL, |
5603 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5518 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5604 | VLV_RENDER_RC0_COUNT_EN | |
5519 | VLV_RENDER_RC0_COUNT_EN | |
5605 | VLV_MEDIA_RC6_COUNT_EN | |
5520 | VLV_MEDIA_RC6_COUNT_EN | |
5606 | VLV_RENDER_RC6_COUNT_EN)); |
5521 | VLV_RENDER_RC6_COUNT_EN)); |
5607 | 5522 | ||
5608 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
5523 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
5609 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
5524 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
5610 | 5525 | ||
5611 | intel_print_rc6_info(dev, rc6_mode); |
5526 | intel_print_rc6_info(dev, rc6_mode); |
5612 | 5527 | ||
5613 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
5528 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
5614 | 5529 | ||
5615 | /* Setting Fixed Bias */ |
5530 | /* Setting Fixed Bias */ |
5616 | val = VLV_OVERRIDE_EN | |
5531 | val = VLV_OVERRIDE_EN | |
5617 | VLV_SOC_TDP_EN | |
5532 | VLV_SOC_TDP_EN | |
5618 | VLV_BIAS_CPU_125_SOC_875; |
5533 | VLV_BIAS_CPU_125_SOC_875; |
5619 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
5534 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
5620 | 5535 | ||
5621 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5536 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5622 | 5537 | ||
5623 | /* RPS code assumes GPLL is used */ |
5538 | /* RPS code assumes GPLL is used */ |
5624 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
5539 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
5625 | 5540 | ||
5626 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
5541 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
5627 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5542 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5628 | 5543 | ||
5629 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
5544 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
5630 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
5545 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
5631 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
5546 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
5632 | dev_priv->rps.cur_freq); |
5547 | dev_priv->rps.cur_freq); |
5633 | 5548 | ||
5634 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
5549 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
5635 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5550 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5636 | dev_priv->rps.efficient_freq); |
5551 | dev_priv->rps.efficient_freq); |
5637 | 5552 | ||
5638 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
5553 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
5639 | 5554 | ||
5640 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
5555 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
5641 | } |
5556 | } |
5642 | 5557 | ||
5643 | static unsigned long intel_pxfreq(u32 vidfreq) |
5558 | static unsigned long intel_pxfreq(u32 vidfreq) |
5644 | { |
5559 | { |
5645 | unsigned long freq; |
5560 | unsigned long freq; |
5646 | int div = (vidfreq & 0x3f0000) >> 16; |
5561 | int div = (vidfreq & 0x3f0000) >> 16; |
5647 | int post = (vidfreq & 0x3000) >> 12; |
5562 | int post = (vidfreq & 0x3000) >> 12; |
5648 | int pre = (vidfreq & 0x7); |
5563 | int pre = (vidfreq & 0x7); |
5649 | 5564 | ||
5650 | if (!pre) |
5565 | if (!pre) |
5651 | return 0; |
5566 | return 0; |
5652 | 5567 | ||
5653 | freq = ((div * 133333) / ((1< |
5568 | freq = ((div * 133333) / ((1< |
5654 | 5569 | ||
5655 | return freq; |
5570 | return freq; |
5656 | } |
5571 | } |
5657 | 5572 | ||
5658 | static const struct cparams { |
5573 | static const struct cparams { |
5659 | u16 i; |
5574 | u16 i; |
5660 | u16 t; |
5575 | u16 t; |
5661 | u16 m; |
5576 | u16 m; |
5662 | u16 c; |
5577 | u16 c; |
5663 | } cparams[] = { |
5578 | } cparams[] = { |
5664 | { 1, 1333, 301, 28664 }, |
5579 | { 1, 1333, 301, 28664 }, |
5665 | { 1, 1066, 294, 24460 }, |
5580 | { 1, 1066, 294, 24460 }, |
5666 | { 1, 800, 294, 25192 }, |
5581 | { 1, 800, 294, 25192 }, |
5667 | { 0, 1333, 276, 27605 }, |
5582 | { 0, 1333, 276, 27605 }, |
5668 | { 0, 1066, 276, 27605 }, |
5583 | { 0, 1066, 276, 27605 }, |
5669 | { 0, 800, 231, 23784 }, |
5584 | { 0, 800, 231, 23784 }, |
5670 | }; |
5585 | }; |
5671 | 5586 | ||
5672 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
5587 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
5673 | { |
5588 | { |
5674 | u64 total_count, diff, ret; |
5589 | u64 total_count, diff, ret; |
5675 | u32 count1, count2, count3, m = 0, c = 0; |
5590 | u32 count1, count2, count3, m = 0, c = 0; |
5676 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
5591 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
5677 | int i; |
5592 | int i; |
5678 | 5593 | ||
5679 | assert_spin_locked(&mchdev_lock); |
5594 | assert_spin_locked(&mchdev_lock); |
5680 | 5595 | ||
5681 | diff1 = now - dev_priv->ips.last_time1; |
5596 | diff1 = now - dev_priv->ips.last_time1; |
5682 | 5597 | ||
5683 | /* Prevent division-by-zero if we are asking too fast. |
5598 | /* Prevent division-by-zero if we are asking too fast. |
5684 | * Also, we don't get interesting results if we are polling |
5599 | * Also, we don't get interesting results if we are polling |
5685 | * faster than once in 10ms, so just return the saved value |
5600 | * faster than once in 10ms, so just return the saved value |
5686 | * in such cases. |
5601 | * in such cases. |
5687 | */ |
5602 | */ |
5688 | if (diff1 <= 10) |
5603 | if (diff1 <= 10) |
5689 | return dev_priv->ips.chipset_power; |
5604 | return dev_priv->ips.chipset_power; |
5690 | 5605 | ||
5691 | count1 = I915_READ(DMIEC); |
5606 | count1 = I915_READ(DMIEC); |
5692 | count2 = I915_READ(DDREC); |
5607 | count2 = I915_READ(DDREC); |
5693 | count3 = I915_READ(CSIEC); |
5608 | count3 = I915_READ(CSIEC); |
5694 | 5609 | ||
5695 | total_count = count1 + count2 + count3; |
5610 | total_count = count1 + count2 + count3; |
5696 | 5611 | ||
5697 | /* FIXME: handle per-counter overflow */ |
5612 | /* FIXME: handle per-counter overflow */ |
5698 | if (total_count < dev_priv->ips.last_count1) { |
5613 | if (total_count < dev_priv->ips.last_count1) { |
5699 | diff = ~0UL - dev_priv->ips.last_count1; |
5614 | diff = ~0UL - dev_priv->ips.last_count1; |
5700 | diff += total_count; |
5615 | diff += total_count; |
5701 | } else { |
5616 | } else { |
5702 | diff = total_count - dev_priv->ips.last_count1; |
5617 | diff = total_count - dev_priv->ips.last_count1; |
5703 | } |
5618 | } |
5704 | 5619 | ||
5705 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
5620 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
5706 | if (cparams[i].i == dev_priv->ips.c_m && |
5621 | if (cparams[i].i == dev_priv->ips.c_m && |
5707 | cparams[i].t == dev_priv->ips.r_t) { |
5622 | cparams[i].t == dev_priv->ips.r_t) { |
5708 | m = cparams[i].m; |
5623 | m = cparams[i].m; |
5709 | c = cparams[i].c; |
5624 | c = cparams[i].c; |
5710 | break; |
5625 | break; |
5711 | } |
5626 | } |
5712 | } |
5627 | } |
5713 | 5628 | ||
5714 | diff = div_u64(diff, diff1); |
5629 | diff = div_u64(diff, diff1); |
5715 | ret = ((m * diff) + c); |
5630 | ret = ((m * diff) + c); |
5716 | ret = div_u64(ret, 10); |
5631 | ret = div_u64(ret, 10); |
5717 | 5632 | ||
5718 | dev_priv->ips.last_count1 = total_count; |
5633 | dev_priv->ips.last_count1 = total_count; |
5719 | dev_priv->ips.last_time1 = now; |
5634 | dev_priv->ips.last_time1 = now; |
5720 | 5635 | ||
5721 | dev_priv->ips.chipset_power = ret; |
5636 | dev_priv->ips.chipset_power = ret; |
5722 | 5637 | ||
5723 | return ret; |
5638 | return ret; |
5724 | } |
5639 | } |
5725 | 5640 | ||
5726 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5641 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5727 | { |
5642 | { |
5728 | struct drm_device *dev = dev_priv->dev; |
5643 | struct drm_device *dev = dev_priv->dev; |
5729 | unsigned long val; |
5644 | unsigned long val; |
5730 | 5645 | ||
5731 | if (INTEL_INFO(dev)->gen != 5) |
5646 | if (INTEL_INFO(dev)->gen != 5) |
5732 | return 0; |
5647 | return 0; |
5733 | 5648 | ||
5734 | spin_lock_irq(&mchdev_lock); |
5649 | spin_lock_irq(&mchdev_lock); |
5735 | 5650 | ||
5736 | val = __i915_chipset_val(dev_priv); |
5651 | val = __i915_chipset_val(dev_priv); |
5737 | 5652 | ||
5738 | spin_unlock_irq(&mchdev_lock); |
5653 | spin_unlock_irq(&mchdev_lock); |
5739 | 5654 | ||
5740 | return val; |
5655 | return val; |
5741 | } |
5656 | } |
5742 | 5657 | ||
5743 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5658 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5744 | { |
5659 | { |
5745 | unsigned long m, x, b; |
5660 | unsigned long m, x, b; |
5746 | u32 tsfs; |
5661 | u32 tsfs; |
5747 | 5662 | ||
5748 | tsfs = I915_READ(TSFS); |
5663 | tsfs = I915_READ(TSFS); |
5749 | 5664 | ||
5750 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
5665 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
5751 | x = I915_READ8(TR1); |
5666 | x = I915_READ8(TR1); |
5752 | 5667 | ||
5753 | b = tsfs & TSFS_INTR_MASK; |
5668 | b = tsfs & TSFS_INTR_MASK; |
5754 | 5669 | ||
5755 | return ((m * x) / 127) - b; |
5670 | return ((m * x) / 127) - b; |
5756 | } |
5671 | } |
5757 | 5672 | ||
5758 | static int _pxvid_to_vd(u8 pxvid) |
5673 | static int _pxvid_to_vd(u8 pxvid) |
5759 | { |
5674 | { |
5760 | if (pxvid == 0) |
5675 | if (pxvid == 0) |
5761 | return 0; |
5676 | return 0; |
5762 | 5677 | ||
5763 | if (pxvid >= 8 && pxvid < 31) |
5678 | if (pxvid >= 8 && pxvid < 31) |
5764 | pxvid = 31; |
5679 | pxvid = 31; |
5765 | 5680 | ||
5766 | return (pxvid + 2) * 125; |
5681 | return (pxvid + 2) * 125; |
5767 | } |
5682 | } |
5768 | 5683 | ||
5769 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
5684 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
5770 | { |
5685 | { |
5771 | struct drm_device *dev = dev_priv->dev; |
5686 | struct drm_device *dev = dev_priv->dev; |
5772 | const int vd = _pxvid_to_vd(pxvid); |
5687 | const int vd = _pxvid_to_vd(pxvid); |
5773 | const int vm = vd - 1125; |
5688 | const int vm = vd - 1125; |
5774 | 5689 | ||
5775 | if (INTEL_INFO(dev)->is_mobile) |
5690 | if (INTEL_INFO(dev)->is_mobile) |
5776 | return vm > 0 ? vm : 0; |
5691 | return vm > 0 ? vm : 0; |
5777 | 5692 | ||
5778 | return vd; |
5693 | return vd; |
5779 | } |
5694 | } |
5780 | 5695 | ||
5781 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5696 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5782 | { |
5697 | { |
5783 | u64 now, diff, diffms; |
5698 | u64 now, diff, diffms; |
5784 | u32 count; |
5699 | u32 count; |
5785 | 5700 | ||
5786 | assert_spin_locked(&mchdev_lock); |
5701 | assert_spin_locked(&mchdev_lock); |
5787 | 5702 | ||
5788 | now = ktime_get_raw_ns(); |
5703 | now = ktime_get_raw_ns(); |
5789 | diffms = now - dev_priv->ips.last_time2; |
5704 | diffms = now - dev_priv->ips.last_time2; |
5790 | do_div(diffms, NSEC_PER_MSEC); |
5705 | do_div(diffms, NSEC_PER_MSEC); |
5791 | 5706 | ||
5792 | /* Don't divide by 0 */ |
5707 | /* Don't divide by 0 */ |
5793 | if (!diffms) |
5708 | if (!diffms) |
5794 | return; |
5709 | return; |
5795 | 5710 | ||
5796 | count = I915_READ(GFXEC); |
5711 | count = I915_READ(GFXEC); |
5797 | 5712 | ||
5798 | if (count < dev_priv->ips.last_count2) { |
5713 | if (count < dev_priv->ips.last_count2) { |
5799 | diff = ~0UL - dev_priv->ips.last_count2; |
5714 | diff = ~0UL - dev_priv->ips.last_count2; |
5800 | diff += count; |
5715 | diff += count; |
5801 | } else { |
5716 | } else { |
5802 | diff = count - dev_priv->ips.last_count2; |
5717 | diff = count - dev_priv->ips.last_count2; |
5803 | } |
5718 | } |
5804 | 5719 | ||
5805 | dev_priv->ips.last_count2 = count; |
5720 | dev_priv->ips.last_count2 = count; |
5806 | dev_priv->ips.last_time2 = now; |
5721 | dev_priv->ips.last_time2 = now; |
5807 | 5722 | ||
5808 | /* More magic constants... */ |
5723 | /* More magic constants... */ |
5809 | diff = diff * 1181; |
5724 | diff = diff * 1181; |
5810 | diff = div_u64(diff, diffms * 10); |
5725 | diff = div_u64(diff, diffms * 10); |
5811 | dev_priv->ips.gfx_power = diff; |
5726 | dev_priv->ips.gfx_power = diff; |
5812 | } |
5727 | } |
5813 | 5728 | ||
5814 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5729 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5815 | { |
5730 | { |
5816 | struct drm_device *dev = dev_priv->dev; |
5731 | struct drm_device *dev = dev_priv->dev; |
5817 | 5732 | ||
5818 | if (INTEL_INFO(dev)->gen != 5) |
5733 | if (INTEL_INFO(dev)->gen != 5) |
5819 | return; |
5734 | return; |
5820 | 5735 | ||
5821 | spin_lock_irq(&mchdev_lock); |
5736 | spin_lock_irq(&mchdev_lock); |
5822 | 5737 | ||
5823 | __i915_update_gfx_val(dev_priv); |
5738 | __i915_update_gfx_val(dev_priv); |
5824 | 5739 | ||
5825 | spin_unlock_irq(&mchdev_lock); |
5740 | spin_unlock_irq(&mchdev_lock); |
5826 | } |
5741 | } |
5827 | 5742 | ||
5828 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
5743 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
5829 | { |
5744 | { |
5830 | unsigned long t, corr, state1, corr2, state2; |
5745 | unsigned long t, corr, state1, corr2, state2; |
5831 | u32 pxvid, ext_v; |
5746 | u32 pxvid, ext_v; |
5832 | 5747 | ||
5833 | assert_spin_locked(&mchdev_lock); |
5748 | assert_spin_locked(&mchdev_lock); |
5834 | 5749 | ||
5835 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
5750 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
5836 | pxvid = (pxvid >> 24) & 0x7f; |
5751 | pxvid = (pxvid >> 24) & 0x7f; |
5837 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
5752 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
5838 | 5753 | ||
5839 | state1 = ext_v; |
5754 | state1 = ext_v; |
5840 | 5755 | ||
5841 | t = i915_mch_val(dev_priv); |
5756 | t = i915_mch_val(dev_priv); |
5842 | 5757 | ||
5843 | /* Revel in the empirically derived constants */ |
5758 | /* Revel in the empirically derived constants */ |
5844 | 5759 | ||
5845 | /* Correction factor in 1/100000 units */ |
5760 | /* Correction factor in 1/100000 units */ |
5846 | if (t > 80) |
5761 | if (t > 80) |
5847 | corr = ((t * 2349) + 135940); |
5762 | corr = ((t * 2349) + 135940); |
5848 | else if (t >= 50) |
5763 | else if (t >= 50) |
5849 | corr = ((t * 964) + 29317); |
5764 | corr = ((t * 964) + 29317); |
5850 | else /* < 50 */ |
5765 | else /* < 50 */ |
5851 | corr = ((t * 301) + 1004); |
5766 | corr = ((t * 301) + 1004); |
5852 | 5767 | ||
5853 | corr = corr * ((150142 * state1) / 10000 - 78642); |
5768 | corr = corr * ((150142 * state1) / 10000 - 78642); |
5854 | corr /= 100000; |
5769 | corr /= 100000; |
5855 | corr2 = (corr * dev_priv->ips.corr); |
5770 | corr2 = (corr * dev_priv->ips.corr); |
5856 | 5771 | ||
5857 | state2 = (corr2 * state1) / 10000; |
5772 | state2 = (corr2 * state1) / 10000; |
5858 | state2 /= 100; /* convert to mW */ |
5773 | state2 /= 100; /* convert to mW */ |
5859 | 5774 | ||
5860 | __i915_update_gfx_val(dev_priv); |
5775 | __i915_update_gfx_val(dev_priv); |
5861 | 5776 | ||
5862 | return dev_priv->ips.gfx_power + state2; |
5777 | return dev_priv->ips.gfx_power + state2; |
5863 | } |
5778 | } |
5864 | 5779 | ||
5865 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5780 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5866 | { |
5781 | { |
5867 | struct drm_device *dev = dev_priv->dev; |
5782 | struct drm_device *dev = dev_priv->dev; |
5868 | unsigned long val; |
5783 | unsigned long val; |
5869 | 5784 | ||
5870 | if (INTEL_INFO(dev)->gen != 5) |
5785 | if (INTEL_INFO(dev)->gen != 5) |
5871 | return 0; |
5786 | return 0; |
5872 | 5787 | ||
5873 | spin_lock_irq(&mchdev_lock); |
5788 | spin_lock_irq(&mchdev_lock); |
5874 | 5789 | ||
5875 | val = __i915_gfx_val(dev_priv); |
5790 | val = __i915_gfx_val(dev_priv); |
5876 | 5791 | ||
5877 | spin_unlock_irq(&mchdev_lock); |
5792 | spin_unlock_irq(&mchdev_lock); |
5878 | 5793 | ||
5879 | return val; |
5794 | return val; |
5880 | } |
5795 | } |
5881 | 5796 | ||
5882 | /** |
5797 | /** |
5883 | * i915_read_mch_val - return value for IPS use |
5798 | * i915_read_mch_val - return value for IPS use |
5884 | * |
5799 | * |
5885 | * Calculate and return a value for the IPS driver to use when deciding whether |
5800 | * Calculate and return a value for the IPS driver to use when deciding whether |
5886 | * we have thermal and power headroom to increase CPU or GPU power budget. |
5801 | * we have thermal and power headroom to increase CPU or GPU power budget. |
5887 | */ |
5802 | */ |
5888 | unsigned long i915_read_mch_val(void) |
5803 | unsigned long i915_read_mch_val(void) |
5889 | { |
5804 | { |
5890 | struct drm_i915_private *dev_priv; |
5805 | struct drm_i915_private *dev_priv; |
5891 | unsigned long chipset_val, graphics_val, ret = 0; |
5806 | unsigned long chipset_val, graphics_val, ret = 0; |
5892 | 5807 | ||
5893 | spin_lock_irq(&mchdev_lock); |
5808 | spin_lock_irq(&mchdev_lock); |
5894 | if (!i915_mch_dev) |
5809 | if (!i915_mch_dev) |
5895 | goto out_unlock; |
5810 | goto out_unlock; |
5896 | dev_priv = i915_mch_dev; |
5811 | dev_priv = i915_mch_dev; |
5897 | 5812 | ||
5898 | chipset_val = __i915_chipset_val(dev_priv); |
5813 | chipset_val = __i915_chipset_val(dev_priv); |
5899 | graphics_val = __i915_gfx_val(dev_priv); |
5814 | graphics_val = __i915_gfx_val(dev_priv); |
5900 | 5815 | ||
5901 | ret = chipset_val + graphics_val; |
5816 | ret = chipset_val + graphics_val; |
5902 | 5817 | ||
5903 | out_unlock: |
5818 | out_unlock: |
5904 | spin_unlock_irq(&mchdev_lock); |
5819 | spin_unlock_irq(&mchdev_lock); |
5905 | 5820 | ||
5906 | return ret; |
5821 | return ret; |
5907 | } |
5822 | } |
5908 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
5823 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
5909 | 5824 | ||
5910 | /** |
5825 | /** |
5911 | * i915_gpu_raise - raise GPU frequency limit |
5826 | * i915_gpu_raise - raise GPU frequency limit |
5912 | * |
5827 | * |
5913 | * Raise the limit; IPS indicates we have thermal headroom. |
5828 | * Raise the limit; IPS indicates we have thermal headroom. |
5914 | */ |
5829 | */ |
5915 | bool i915_gpu_raise(void) |
5830 | bool i915_gpu_raise(void) |
5916 | { |
5831 | { |
5917 | struct drm_i915_private *dev_priv; |
5832 | struct drm_i915_private *dev_priv; |
5918 | bool ret = true; |
5833 | bool ret = true; |
5919 | 5834 | ||
5920 | spin_lock_irq(&mchdev_lock); |
5835 | spin_lock_irq(&mchdev_lock); |
5921 | if (!i915_mch_dev) { |
5836 | if (!i915_mch_dev) { |
5922 | ret = false; |
5837 | ret = false; |
5923 | goto out_unlock; |
5838 | goto out_unlock; |
5924 | } |
5839 | } |
5925 | dev_priv = i915_mch_dev; |
5840 | dev_priv = i915_mch_dev; |
5926 | 5841 | ||
5927 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5842 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5928 | dev_priv->ips.max_delay--; |
5843 | dev_priv->ips.max_delay--; |
5929 | 5844 | ||
5930 | out_unlock: |
5845 | out_unlock: |
5931 | spin_unlock_irq(&mchdev_lock); |
5846 | spin_unlock_irq(&mchdev_lock); |
5932 | 5847 | ||
5933 | return ret; |
5848 | return ret; |
5934 | } |
5849 | } |
5935 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
5850 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
5936 | 5851 | ||
5937 | /** |
5852 | /** |
5938 | * i915_gpu_lower - lower GPU frequency limit |
5853 | * i915_gpu_lower - lower GPU frequency limit |
5939 | * |
5854 | * |
5940 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
5855 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
5941 | * frequency maximum. |
5856 | * frequency maximum. |
5942 | */ |
5857 | */ |
5943 | bool i915_gpu_lower(void) |
5858 | bool i915_gpu_lower(void) |
5944 | { |
5859 | { |
5945 | struct drm_i915_private *dev_priv; |
5860 | struct drm_i915_private *dev_priv; |
5946 | bool ret = true; |
5861 | bool ret = true; |
5947 | 5862 | ||
5948 | spin_lock_irq(&mchdev_lock); |
5863 | spin_lock_irq(&mchdev_lock); |
5949 | if (!i915_mch_dev) { |
5864 | if (!i915_mch_dev) { |
5950 | ret = false; |
5865 | ret = false; |
5951 | goto out_unlock; |
5866 | goto out_unlock; |
5952 | } |
5867 | } |
5953 | dev_priv = i915_mch_dev; |
5868 | dev_priv = i915_mch_dev; |
5954 | 5869 | ||
5955 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5870 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5956 | dev_priv->ips.max_delay++; |
5871 | dev_priv->ips.max_delay++; |
5957 | 5872 | ||
5958 | out_unlock: |
5873 | out_unlock: |
5959 | spin_unlock_irq(&mchdev_lock); |
5874 | spin_unlock_irq(&mchdev_lock); |
5960 | 5875 | ||
5961 | return ret; |
5876 | return ret; |
5962 | } |
5877 | } |
5963 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
5878 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
5964 | 5879 | ||
5965 | /** |
5880 | /** |
5966 | * i915_gpu_busy - indicate GPU business to IPS |
5881 | * i915_gpu_busy - indicate GPU business to IPS |
5967 | * |
5882 | * |
5968 | * Tell the IPS driver whether or not the GPU is busy. |
5883 | * Tell the IPS driver whether or not the GPU is busy. |
5969 | */ |
5884 | */ |
5970 | bool i915_gpu_busy(void) |
5885 | bool i915_gpu_busy(void) |
5971 | { |
5886 | { |
5972 | struct drm_i915_private *dev_priv; |
5887 | struct drm_i915_private *dev_priv; |
5973 | struct intel_engine_cs *ring; |
5888 | struct intel_engine_cs *ring; |
5974 | bool ret = false; |
5889 | bool ret = false; |
5975 | int i; |
5890 | int i; |
5976 | 5891 | ||
5977 | spin_lock_irq(&mchdev_lock); |
5892 | spin_lock_irq(&mchdev_lock); |
5978 | if (!i915_mch_dev) |
5893 | if (!i915_mch_dev) |
5979 | goto out_unlock; |
5894 | goto out_unlock; |
5980 | dev_priv = i915_mch_dev; |
5895 | dev_priv = i915_mch_dev; |
5981 | 5896 | ||
5982 | for_each_ring(ring, dev_priv, i) |
5897 | for_each_ring(ring, dev_priv, i) |
5983 | ret |= !list_empty(&ring->request_list); |
5898 | ret |= !list_empty(&ring->request_list); |
5984 | 5899 | ||
5985 | out_unlock: |
5900 | out_unlock: |
5986 | spin_unlock_irq(&mchdev_lock); |
5901 | spin_unlock_irq(&mchdev_lock); |
5987 | 5902 | ||
5988 | return ret; |
5903 | return ret; |
5989 | } |
5904 | } |
5990 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
5905 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
5991 | 5906 | ||
5992 | /** |
5907 | /** |
5993 | * i915_gpu_turbo_disable - disable graphics turbo |
5908 | * i915_gpu_turbo_disable - disable graphics turbo |
5994 | * |
5909 | * |
5995 | * Disable graphics turbo by resetting the max frequency and setting the |
5910 | * Disable graphics turbo by resetting the max frequency and setting the |
5996 | * current frequency to the default. |
5911 | * current frequency to the default. |
5997 | */ |
5912 | */ |
5998 | bool i915_gpu_turbo_disable(void) |
5913 | bool i915_gpu_turbo_disable(void) |
5999 | { |
5914 | { |
6000 | struct drm_i915_private *dev_priv; |
5915 | struct drm_i915_private *dev_priv; |
6001 | bool ret = true; |
5916 | bool ret = true; |
6002 | 5917 | ||
6003 | spin_lock_irq(&mchdev_lock); |
5918 | spin_lock_irq(&mchdev_lock); |
6004 | if (!i915_mch_dev) { |
5919 | if (!i915_mch_dev) { |
6005 | ret = false; |
5920 | ret = false; |
6006 | goto out_unlock; |
5921 | goto out_unlock; |
6007 | } |
5922 | } |
6008 | dev_priv = i915_mch_dev; |
5923 | dev_priv = i915_mch_dev; |
6009 | 5924 | ||
6010 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
5925 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
6011 | 5926 | ||
6012 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
5927 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
6013 | ret = false; |
5928 | ret = false; |
6014 | 5929 | ||
6015 | out_unlock: |
5930 | out_unlock: |
6016 | spin_unlock_irq(&mchdev_lock); |
5931 | spin_unlock_irq(&mchdev_lock); |
6017 | 5932 | ||
6018 | return ret; |
5933 | return ret; |
6019 | } |
5934 | } |
6020 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
5935 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
6021 | 5936 | ||
6022 | /** |
5937 | /** |
6023 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
5938 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
6024 | * IPS got loaded first. |
5939 | * IPS got loaded first. |
6025 | * |
5940 | * |
6026 | * This awkward dance is so that neither module has to depend on the |
5941 | * This awkward dance is so that neither module has to depend on the |
6027 | * other in order for IPS to do the appropriate communication of |
5942 | * other in order for IPS to do the appropriate communication of |
6028 | * GPU turbo limits to i915. |
5943 | * GPU turbo limits to i915. |
6029 | */ |
5944 | */ |
6030 | static void |
5945 | static void |
6031 | ips_ping_for_i915_load(void) |
5946 | ips_ping_for_i915_load(void) |
6032 | { |
5947 | { |
6033 | void (*link)(void); |
5948 | void (*link)(void); |
6034 | 5949 | ||
6035 | // link = symbol_get(ips_link_to_i915_driver); |
5950 | // link = symbol_get(ips_link_to_i915_driver); |
6036 | // if (link) { |
5951 | // if (link) { |
6037 | // link(); |
5952 | // link(); |
6038 | // symbol_put(ips_link_to_i915_driver); |
5953 | // symbol_put(ips_link_to_i915_driver); |
6039 | // } |
5954 | // } |
6040 | } |
5955 | } |
6041 | 5956 | ||
6042 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
5957 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
6043 | { |
5958 | { |
6044 | /* We only register the i915 ips part with intel-ips once everything is |
5959 | /* We only register the i915 ips part with intel-ips once everything is |
6045 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
5960 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
6046 | spin_lock_irq(&mchdev_lock); |
5961 | spin_lock_irq(&mchdev_lock); |
6047 | i915_mch_dev = dev_priv; |
5962 | i915_mch_dev = dev_priv; |
6048 | spin_unlock_irq(&mchdev_lock); |
5963 | spin_unlock_irq(&mchdev_lock); |
6049 | 5964 | ||
6050 | ips_ping_for_i915_load(); |
5965 | ips_ping_for_i915_load(); |
6051 | } |
5966 | } |
6052 | 5967 | ||
6053 | void intel_gpu_ips_teardown(void) |
5968 | void intel_gpu_ips_teardown(void) |
6054 | { |
5969 | { |
6055 | spin_lock_irq(&mchdev_lock); |
5970 | spin_lock_irq(&mchdev_lock); |
6056 | i915_mch_dev = NULL; |
5971 | i915_mch_dev = NULL; |
6057 | spin_unlock_irq(&mchdev_lock); |
5972 | spin_unlock_irq(&mchdev_lock); |
6058 | } |
5973 | } |
6059 | 5974 | ||
6060 | static void intel_init_emon(struct drm_device *dev) |
5975 | static void intel_init_emon(struct drm_device *dev) |
6061 | { |
5976 | { |
6062 | struct drm_i915_private *dev_priv = dev->dev_private; |
5977 | struct drm_i915_private *dev_priv = dev->dev_private; |
6063 | u32 lcfuse; |
5978 | u32 lcfuse; |
6064 | u8 pxw[16]; |
5979 | u8 pxw[16]; |
6065 | int i; |
5980 | int i; |
6066 | 5981 | ||
6067 | /* Disable to program */ |
5982 | /* Disable to program */ |
6068 | I915_WRITE(ECR, 0); |
5983 | I915_WRITE(ECR, 0); |
6069 | POSTING_READ(ECR); |
5984 | POSTING_READ(ECR); |
6070 | 5985 | ||
6071 | /* Program energy weights for various events */ |
5986 | /* Program energy weights for various events */ |
6072 | I915_WRITE(SDEW, 0x15040d00); |
5987 | I915_WRITE(SDEW, 0x15040d00); |
6073 | I915_WRITE(CSIEW0, 0x007f0000); |
5988 | I915_WRITE(CSIEW0, 0x007f0000); |
6074 | I915_WRITE(CSIEW1, 0x1e220004); |
5989 | I915_WRITE(CSIEW1, 0x1e220004); |
6075 | I915_WRITE(CSIEW2, 0x04000004); |
5990 | I915_WRITE(CSIEW2, 0x04000004); |
6076 | 5991 | ||
6077 | for (i = 0; i < 5; i++) |
5992 | for (i = 0; i < 5; i++) |
6078 | I915_WRITE(PEW(i), 0); |
5993 | I915_WRITE(PEW(i), 0); |
6079 | for (i = 0; i < 3; i++) |
5994 | for (i = 0; i < 3; i++) |
6080 | I915_WRITE(DEW(i), 0); |
5995 | I915_WRITE(DEW(i), 0); |
6081 | 5996 | ||
6082 | /* Program P-state weights to account for frequency power adjustment */ |
5997 | /* Program P-state weights to account for frequency power adjustment */ |
6083 | for (i = 0; i < 16; i++) { |
5998 | for (i = 0; i < 16; i++) { |
6084 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
5999 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
6085 | unsigned long freq = intel_pxfreq(pxvidfreq); |
6000 | unsigned long freq = intel_pxfreq(pxvidfreq); |
6086 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
6001 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
6087 | PXVFREQ_PX_SHIFT; |
6002 | PXVFREQ_PX_SHIFT; |
6088 | unsigned long val; |
6003 | unsigned long val; |
6089 | 6004 | ||
6090 | val = vid * vid; |
6005 | val = vid * vid; |
6091 | val *= (freq / 1000); |
6006 | val *= (freq / 1000); |
6092 | val *= 255; |
6007 | val *= 255; |
6093 | val /= (127*127*900); |
6008 | val /= (127*127*900); |
6094 | if (val > 0xff) |
6009 | if (val > 0xff) |
6095 | DRM_ERROR("bad pxval: %ld\n", val); |
6010 | DRM_ERROR("bad pxval: %ld\n", val); |
6096 | pxw[i] = val; |
6011 | pxw[i] = val; |
6097 | } |
6012 | } |
6098 | /* Render standby states get 0 weight */ |
6013 | /* Render standby states get 0 weight */ |
6099 | pxw[14] = 0; |
6014 | pxw[14] = 0; |
6100 | pxw[15] = 0; |
6015 | pxw[15] = 0; |
6101 | 6016 | ||
6102 | for (i = 0; i < 4; i++) { |
6017 | for (i = 0; i < 4; i++) { |
6103 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
6018 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
6104 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
6019 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
6105 | I915_WRITE(PXW(i), val); |
6020 | I915_WRITE(PXW(i), val); |
6106 | } |
6021 | } |
6107 | 6022 | ||
6108 | /* Adjust magic regs to magic values (more experimental results) */ |
6023 | /* Adjust magic regs to magic values (more experimental results) */ |
6109 | I915_WRITE(OGW0, 0); |
6024 | I915_WRITE(OGW0, 0); |
6110 | I915_WRITE(OGW1, 0); |
6025 | I915_WRITE(OGW1, 0); |
6111 | I915_WRITE(EG0, 0x00007f00); |
6026 | I915_WRITE(EG0, 0x00007f00); |
6112 | I915_WRITE(EG1, 0x0000000e); |
6027 | I915_WRITE(EG1, 0x0000000e); |
6113 | I915_WRITE(EG2, 0x000e0000); |
6028 | I915_WRITE(EG2, 0x000e0000); |
6114 | I915_WRITE(EG3, 0x68000300); |
6029 | I915_WRITE(EG3, 0x68000300); |
6115 | I915_WRITE(EG4, 0x42000000); |
6030 | I915_WRITE(EG4, 0x42000000); |
6116 | I915_WRITE(EG5, 0x00140031); |
6031 | I915_WRITE(EG5, 0x00140031); |
6117 | I915_WRITE(EG6, 0); |
6032 | I915_WRITE(EG6, 0); |
6118 | I915_WRITE(EG7, 0); |
6033 | I915_WRITE(EG7, 0); |
6119 | 6034 | ||
6120 | for (i = 0; i < 8; i++) |
6035 | for (i = 0; i < 8; i++) |
6121 | I915_WRITE(PXWL(i), 0); |
6036 | I915_WRITE(PXWL(i), 0); |
6122 | 6037 | ||
6123 | /* Enable PMON + select events */ |
6038 | /* Enable PMON + select events */ |
6124 | I915_WRITE(ECR, 0x80000019); |
6039 | I915_WRITE(ECR, 0x80000019); |
6125 | 6040 | ||
6126 | lcfuse = I915_READ(LCFUSE02); |
6041 | lcfuse = I915_READ(LCFUSE02); |
6127 | 6042 | ||
6128 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
6043 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
6129 | } |
6044 | } |
6130 | 6045 | ||
6131 | void intel_init_gt_powersave(struct drm_device *dev) |
6046 | void intel_init_gt_powersave(struct drm_device *dev) |
6132 | { |
6047 | { |
- | 6048 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6049 | ||
6133 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
6050 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
- | 6051 | /* |
|
- | 6052 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
|
- | 6053 | * requirement. |
|
- | 6054 | */ |
|
- | 6055 | if (!i915.enable_rc6) { |
|
- | 6056 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
|
- | 6057 | intel_runtime_pm_get(dev_priv); |
|
- | 6058 | } |
|
6134 | 6059 | ||
6135 | if (IS_CHERRYVIEW(dev)) |
6060 | if (IS_CHERRYVIEW(dev)) |
6136 | cherryview_init_gt_powersave(dev); |
6061 | cherryview_init_gt_powersave(dev); |
6137 | else if (IS_VALLEYVIEW(dev)) |
6062 | else if (IS_VALLEYVIEW(dev)) |
6138 | valleyview_init_gt_powersave(dev); |
6063 | valleyview_init_gt_powersave(dev); |
6139 | } |
6064 | } |
6140 | 6065 | ||
6141 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
6066 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
6142 | { |
6067 | { |
- | 6068 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6069 | ||
6143 | if (IS_CHERRYVIEW(dev)) |
6070 | if (IS_CHERRYVIEW(dev)) |
6144 | return; |
6071 | return; |
6145 | else if (IS_VALLEYVIEW(dev)) |
6072 | else if (IS_VALLEYVIEW(dev)) |
6146 | valleyview_cleanup_gt_powersave(dev); |
6073 | valleyview_cleanup_gt_powersave(dev); |
- | 6074 | ||
- | 6075 | if (!i915.enable_rc6) |
|
- | 6076 | intel_runtime_pm_put(dev_priv); |
|
6147 | } |
6077 | } |
6148 | 6078 | ||
6149 | static void gen6_suspend_rps(struct drm_device *dev) |
6079 | static void gen6_suspend_rps(struct drm_device *dev) |
6150 | { |
6080 | { |
6151 | struct drm_i915_private *dev_priv = dev->dev_private; |
6081 | struct drm_i915_private *dev_priv = dev->dev_private; |
6152 | 6082 | ||
6153 | // flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
6083 | // flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
6154 | 6084 | ||
6155 | gen6_disable_rps_interrupts(dev); |
6085 | gen6_disable_rps_interrupts(dev); |
6156 | } |
6086 | } |
6157 | 6087 | ||
6158 | /** |
6088 | /** |
6159 | * intel_suspend_gt_powersave - suspend PM work and helper threads |
6089 | * intel_suspend_gt_powersave - suspend PM work and helper threads |
6160 | * @dev: drm device |
6090 | * @dev: drm device |
6161 | * |
6091 | * |
6162 | * We don't want to disable RC6 or other features here, we just want |
6092 | * We don't want to disable RC6 or other features here, we just want |
6163 | * to make sure any work we've queued has finished and won't bother |
6093 | * to make sure any work we've queued has finished and won't bother |
6164 | * us while we're suspended. |
6094 | * us while we're suspended. |
6165 | */ |
6095 | */ |
6166 | void intel_suspend_gt_powersave(struct drm_device *dev) |
6096 | void intel_suspend_gt_powersave(struct drm_device *dev) |
6167 | { |
6097 | { |
6168 | struct drm_i915_private *dev_priv = dev->dev_private; |
6098 | struct drm_i915_private *dev_priv = dev->dev_private; |
6169 | 6099 | ||
6170 | if (INTEL_INFO(dev)->gen < 6) |
6100 | if (INTEL_INFO(dev)->gen < 6) |
6171 | return; |
6101 | return; |
6172 | 6102 | ||
6173 | gen6_suspend_rps(dev); |
6103 | gen6_suspend_rps(dev); |
6174 | 6104 | ||
6175 | /* Force GPU to min freq during suspend */ |
6105 | /* Force GPU to min freq during suspend */ |
6176 | gen6_rps_idle(dev_priv); |
6106 | gen6_rps_idle(dev_priv); |
6177 | } |
6107 | } |
6178 | 6108 | ||
6179 | void intel_disable_gt_powersave(struct drm_device *dev) |
6109 | void intel_disable_gt_powersave(struct drm_device *dev) |
6180 | { |
6110 | { |
6181 | struct drm_i915_private *dev_priv = dev->dev_private; |
6111 | struct drm_i915_private *dev_priv = dev->dev_private; |
6182 | 6112 | ||
6183 | if (IS_IRONLAKE_M(dev)) { |
6113 | if (IS_IRONLAKE_M(dev)) { |
6184 | ironlake_disable_drps(dev); |
6114 | ironlake_disable_drps(dev); |
6185 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6115 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6186 | intel_suspend_gt_powersave(dev); |
6116 | intel_suspend_gt_powersave(dev); |
6187 | 6117 | ||
6188 | mutex_lock(&dev_priv->rps.hw_lock); |
6118 | mutex_lock(&dev_priv->rps.hw_lock); |
6189 | if (INTEL_INFO(dev)->gen >= 9) |
6119 | if (INTEL_INFO(dev)->gen >= 9) |
6190 | gen9_disable_rps(dev); |
6120 | gen9_disable_rps(dev); |
6191 | else if (IS_CHERRYVIEW(dev)) |
6121 | else if (IS_CHERRYVIEW(dev)) |
6192 | cherryview_disable_rps(dev); |
6122 | cherryview_disable_rps(dev); |
6193 | else if (IS_VALLEYVIEW(dev)) |
6123 | else if (IS_VALLEYVIEW(dev)) |
6194 | valleyview_disable_rps(dev); |
6124 | valleyview_disable_rps(dev); |
6195 | else |
6125 | else |
6196 | gen6_disable_rps(dev); |
6126 | gen6_disable_rps(dev); |
6197 | 6127 | ||
6198 | dev_priv->rps.enabled = false; |
6128 | dev_priv->rps.enabled = false; |
6199 | mutex_unlock(&dev_priv->rps.hw_lock); |
6129 | mutex_unlock(&dev_priv->rps.hw_lock); |
6200 | } |
6130 | } |
6201 | } |
6131 | } |
6202 | 6132 | ||
6203 | static void intel_gen6_powersave_work(struct work_struct *work) |
6133 | static void intel_gen6_powersave_work(struct work_struct *work) |
6204 | { |
6134 | { |
6205 | struct drm_i915_private *dev_priv = |
6135 | struct drm_i915_private *dev_priv = |
6206 | container_of(work, struct drm_i915_private, |
6136 | container_of(work, struct drm_i915_private, |
6207 | rps.delayed_resume_work.work); |
6137 | rps.delayed_resume_work.work); |
6208 | struct drm_device *dev = dev_priv->dev; |
6138 | struct drm_device *dev = dev_priv->dev; |
6209 | 6139 | ||
6210 | mutex_lock(&dev_priv->rps.hw_lock); |
6140 | mutex_lock(&dev_priv->rps.hw_lock); |
6211 | 6141 | ||
6212 | gen6_reset_rps_interrupts(dev); |
6142 | gen6_reset_rps_interrupts(dev); |
6213 | 6143 | ||
6214 | if (IS_CHERRYVIEW(dev)) { |
6144 | if (IS_CHERRYVIEW(dev)) { |
6215 | cherryview_enable_rps(dev); |
6145 | cherryview_enable_rps(dev); |
6216 | } else if (IS_VALLEYVIEW(dev)) { |
6146 | } else if (IS_VALLEYVIEW(dev)) { |
6217 | valleyview_enable_rps(dev); |
6147 | valleyview_enable_rps(dev); |
6218 | } else if (INTEL_INFO(dev)->gen >= 9) { |
6148 | } else if (INTEL_INFO(dev)->gen >= 9) { |
6219 | gen9_enable_rc6(dev); |
6149 | gen9_enable_rc6(dev); |
6220 | gen9_enable_rps(dev); |
6150 | gen9_enable_rps(dev); |
6221 | if (IS_SKYLAKE(dev)) |
6151 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6222 | __gen6_update_ring_freq(dev); |
6152 | __gen6_update_ring_freq(dev); |
6223 | } else if (IS_BROADWELL(dev)) { |
6153 | } else if (IS_BROADWELL(dev)) { |
6224 | gen8_enable_rps(dev); |
6154 | gen8_enable_rps(dev); |
6225 | __gen6_update_ring_freq(dev); |
6155 | __gen6_update_ring_freq(dev); |
6226 | } else { |
6156 | } else { |
6227 | gen6_enable_rps(dev); |
6157 | gen6_enable_rps(dev); |
6228 | __gen6_update_ring_freq(dev); |
6158 | __gen6_update_ring_freq(dev); |
6229 | } |
6159 | } |
6230 | 6160 | ||
6231 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); |
6161 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); |
6232 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); |
6162 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); |
6233 | 6163 | ||
6234 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); |
6164 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); |
6235 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); |
6165 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); |
6236 | 6166 | ||
6237 | dev_priv->rps.enabled = true; |
6167 | dev_priv->rps.enabled = true; |
6238 | 6168 | ||
6239 | gen6_enable_rps_interrupts(dev); |
6169 | gen6_enable_rps_interrupts(dev); |
6240 | 6170 | ||
6241 | mutex_unlock(&dev_priv->rps.hw_lock); |
6171 | mutex_unlock(&dev_priv->rps.hw_lock); |
6242 | 6172 | ||
6243 | intel_runtime_pm_put(dev_priv); |
6173 | intel_runtime_pm_put(dev_priv); |
6244 | } |
6174 | } |
6245 | 6175 | ||
6246 | void intel_enable_gt_powersave(struct drm_device *dev) |
6176 | void intel_enable_gt_powersave(struct drm_device *dev) |
6247 | { |
6177 | { |
6248 | struct drm_i915_private *dev_priv = dev->dev_private; |
6178 | struct drm_i915_private *dev_priv = dev->dev_private; |
6249 | 6179 | ||
6250 | /* Powersaving is controlled by the host when inside a VM */ |
6180 | /* Powersaving is controlled by the host when inside a VM */ |
6251 | if (intel_vgpu_active(dev)) |
6181 | if (intel_vgpu_active(dev)) |
6252 | return; |
6182 | return; |
6253 | 6183 | ||
6254 | if (IS_IRONLAKE_M(dev)) { |
6184 | if (IS_IRONLAKE_M(dev)) { |
6255 | mutex_lock(&dev->struct_mutex); |
6185 | mutex_lock(&dev->struct_mutex); |
6256 | ironlake_enable_drps(dev); |
6186 | ironlake_enable_drps(dev); |
6257 | intel_init_emon(dev); |
6187 | intel_init_emon(dev); |
6258 | mutex_unlock(&dev->struct_mutex); |
6188 | mutex_unlock(&dev->struct_mutex); |
6259 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6189 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6260 | /* |
6190 | /* |
6261 | * PCU communication is slow and this doesn't need to be |
6191 | * PCU communication is slow and this doesn't need to be |
6262 | * done at any specific time, so do this out of our fast path |
6192 | * done at any specific time, so do this out of our fast path |
6263 | * to make resume and init faster. |
6193 | * to make resume and init faster. |
6264 | * |
6194 | * |
6265 | * We depend on the HW RC6 power context save/restore |
6195 | * We depend on the HW RC6 power context save/restore |
6266 | * mechanism when entering D3 through runtime PM suspend. So |
6196 | * mechanism when entering D3 through runtime PM suspend. So |
6267 | * disable RPM until RPS/RC6 is properly setup. We can only |
6197 | * disable RPM until RPS/RC6 is properly setup. We can only |
6268 | * get here via the driver load/system resume/runtime resume |
6198 | * get here via the driver load/system resume/runtime resume |
6269 | * paths, so the _noresume version is enough (and in case of |
6199 | * paths, so the _noresume version is enough (and in case of |
6270 | * runtime resume it's necessary). |
6200 | * runtime resume it's necessary). |
6271 | */ |
6201 | */ |
6272 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
6202 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
6273 | round_jiffies_up_relative(HZ))) |
6203 | round_jiffies_up_relative(HZ))) |
6274 | intel_runtime_pm_get_noresume(dev_priv); |
6204 | intel_runtime_pm_get_noresume(dev_priv); |
6275 | } |
6205 | } |
6276 | } |
6206 | } |
6277 | 6207 | ||
6278 | void intel_reset_gt_powersave(struct drm_device *dev) |
6208 | void intel_reset_gt_powersave(struct drm_device *dev) |
6279 | { |
6209 | { |
6280 | struct drm_i915_private *dev_priv = dev->dev_private; |
6210 | struct drm_i915_private *dev_priv = dev->dev_private; |
6281 | 6211 | ||
6282 | if (INTEL_INFO(dev)->gen < 6) |
6212 | if (INTEL_INFO(dev)->gen < 6) |
6283 | return; |
6213 | return; |
6284 | 6214 | ||
6285 | gen6_suspend_rps(dev); |
6215 | gen6_suspend_rps(dev); |
6286 | dev_priv->rps.enabled = false; |
6216 | dev_priv->rps.enabled = false; |
6287 | } |
6217 | } |
6288 | 6218 | ||
6289 | static void ibx_init_clock_gating(struct drm_device *dev) |
6219 | static void ibx_init_clock_gating(struct drm_device *dev) |
6290 | { |
6220 | { |
6291 | struct drm_i915_private *dev_priv = dev->dev_private; |
6221 | struct drm_i915_private *dev_priv = dev->dev_private; |
6292 | 6222 | ||
6293 | /* |
6223 | /* |
6294 | * On Ibex Peak and Cougar Point, we need to disable clock |
6224 | * On Ibex Peak and Cougar Point, we need to disable clock |
6295 | * gating for the panel power sequencer or it will fail to |
6225 | * gating for the panel power sequencer or it will fail to |
6296 | * start up when no ports are active. |
6226 | * start up when no ports are active. |
6297 | */ |
6227 | */ |
6298 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
6228 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
6299 | } |
6229 | } |
6300 | 6230 | ||
6301 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
6231 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
6302 | { |
6232 | { |
6303 | struct drm_i915_private *dev_priv = dev->dev_private; |
6233 | struct drm_i915_private *dev_priv = dev->dev_private; |
6304 | enum pipe pipe; |
6234 | enum pipe pipe; |
6305 | 6235 | ||
6306 | for_each_pipe(dev_priv, pipe) { |
6236 | for_each_pipe(dev_priv, pipe) { |
6307 | I915_WRITE(DSPCNTR(pipe), |
6237 | I915_WRITE(DSPCNTR(pipe), |
6308 | I915_READ(DSPCNTR(pipe)) | |
6238 | I915_READ(DSPCNTR(pipe)) | |
6309 | DISPPLANE_TRICKLE_FEED_DISABLE); |
6239 | DISPPLANE_TRICKLE_FEED_DISABLE); |
6310 | 6240 | ||
6311 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); |
6241 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); |
6312 | POSTING_READ(DSPSURF(pipe)); |
6242 | POSTING_READ(DSPSURF(pipe)); |
6313 | } |
6243 | } |
6314 | } |
6244 | } |
6315 | 6245 | ||
6316 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
6246 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
6317 | { |
6247 | { |
6318 | struct drm_i915_private *dev_priv = dev->dev_private; |
6248 | struct drm_i915_private *dev_priv = dev->dev_private; |
6319 | 6249 | ||
6320 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
6250 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
6321 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
6251 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
6322 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
6252 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
6323 | 6253 | ||
6324 | /* |
6254 | /* |
6325 | * Don't touch WM1S_LP_EN here. |
6255 | * Don't touch WM1S_LP_EN here. |
6326 | * Doing so could cause underruns. |
6256 | * Doing so could cause underruns. |
6327 | */ |
6257 | */ |
6328 | } |
6258 | } |
6329 | 6259 | ||
6330 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6260 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6331 | { |
6261 | { |
6332 | struct drm_i915_private *dev_priv = dev->dev_private; |
6262 | struct drm_i915_private *dev_priv = dev->dev_private; |
6333 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6263 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6334 | 6264 | ||
6335 | /* |
6265 | /* |
6336 | * Required for FBC |
6266 | * Required for FBC |
6337 | * WaFbcDisableDpfcClockGating:ilk |
6267 | * WaFbcDisableDpfcClockGating:ilk |
6338 | */ |
6268 | */ |
6339 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
6269 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
6340 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
6270 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
6341 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
6271 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
6342 | 6272 | ||
6343 | I915_WRITE(PCH_3DCGDIS0, |
6273 | I915_WRITE(PCH_3DCGDIS0, |
6344 | MARIUNIT_CLOCK_GATE_DISABLE | |
6274 | MARIUNIT_CLOCK_GATE_DISABLE | |
6345 | SVSMUNIT_CLOCK_GATE_DISABLE); |
6275 | SVSMUNIT_CLOCK_GATE_DISABLE); |
6346 | I915_WRITE(PCH_3DCGDIS1, |
6276 | I915_WRITE(PCH_3DCGDIS1, |
6347 | VFMUNIT_CLOCK_GATE_DISABLE); |
6277 | VFMUNIT_CLOCK_GATE_DISABLE); |
6348 | 6278 | ||
6349 | /* |
6279 | /* |
6350 | * According to the spec the following bits should be set in |
6280 | * According to the spec the following bits should be set in |
6351 | * order to enable memory self-refresh |
6281 | * order to enable memory self-refresh |
6352 | * The bit 22/21 of 0x42004 |
6282 | * The bit 22/21 of 0x42004 |
6353 | * The bit 5 of 0x42020 |
6283 | * The bit 5 of 0x42020 |
6354 | * The bit 15 of 0x45000 |
6284 | * The bit 15 of 0x45000 |
6355 | */ |
6285 | */ |
6356 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6286 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6357 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
6287 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
6358 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
6288 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
6359 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6289 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6360 | I915_WRITE(DISP_ARB_CTL, |
6290 | I915_WRITE(DISP_ARB_CTL, |
6361 | (I915_READ(DISP_ARB_CTL) | |
6291 | (I915_READ(DISP_ARB_CTL) | |
6362 | DISP_FBC_WM_DIS)); |
6292 | DISP_FBC_WM_DIS)); |
6363 | 6293 | ||
6364 | ilk_init_lp_watermarks(dev); |
6294 | ilk_init_lp_watermarks(dev); |
6365 | 6295 | ||
6366 | /* |
6296 | /* |
6367 | * Based on the document from hardware guys the following bits |
6297 | * Based on the document from hardware guys the following bits |
6368 | * should be set unconditionally in order to enable FBC. |
6298 | * should be set unconditionally in order to enable FBC. |
6369 | * The bit 22 of 0x42000 |
6299 | * The bit 22 of 0x42000 |
6370 | * The bit 22 of 0x42004 |
6300 | * The bit 22 of 0x42004 |
6371 | * The bit 7,8,9 of 0x42020. |
6301 | * The bit 7,8,9 of 0x42020. |
6372 | */ |
6302 | */ |
6373 | if (IS_IRONLAKE_M(dev)) { |
6303 | if (IS_IRONLAKE_M(dev)) { |
6374 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6304 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6375 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6305 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6376 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
6306 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
6377 | ILK_FBCQ_DIS); |
6307 | ILK_FBCQ_DIS); |
6378 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6308 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6379 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6309 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6380 | ILK_DPARB_GATE); |
6310 | ILK_DPARB_GATE); |
6381 | } |
6311 | } |
6382 | 6312 | ||
6383 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6313 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6384 | 6314 | ||
6385 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6315 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6386 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6316 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6387 | ILK_ELPIN_409_SELECT); |
6317 | ILK_ELPIN_409_SELECT); |
6388 | I915_WRITE(_3D_CHICKEN2, |
6318 | I915_WRITE(_3D_CHICKEN2, |
6389 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
6319 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
6390 | _3D_CHICKEN2_WM_READ_PIPELINED); |
6320 | _3D_CHICKEN2_WM_READ_PIPELINED); |
6391 | 6321 | ||
6392 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
6322 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
6393 | I915_WRITE(CACHE_MODE_0, |
6323 | I915_WRITE(CACHE_MODE_0, |
6394 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
6324 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
6395 | 6325 | ||
6396 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
6326 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
6397 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6327 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6398 | 6328 | ||
6399 | g4x_disable_trickle_feed(dev); |
6329 | g4x_disable_trickle_feed(dev); |
6400 | 6330 | ||
6401 | ibx_init_clock_gating(dev); |
6331 | ibx_init_clock_gating(dev); |
6402 | } |
6332 | } |
6403 | 6333 | ||
6404 | static void cpt_init_clock_gating(struct drm_device *dev) |
6334 | static void cpt_init_clock_gating(struct drm_device *dev) |
6405 | { |
6335 | { |
6406 | struct drm_i915_private *dev_priv = dev->dev_private; |
6336 | struct drm_i915_private *dev_priv = dev->dev_private; |
6407 | int pipe; |
6337 | int pipe; |
6408 | uint32_t val; |
6338 | uint32_t val; |
6409 | 6339 | ||
6410 | /* |
6340 | /* |
6411 | * On Ibex Peak and Cougar Point, we need to disable clock |
6341 | * On Ibex Peak and Cougar Point, we need to disable clock |
6412 | * gating for the panel power sequencer or it will fail to |
6342 | * gating for the panel power sequencer or it will fail to |
6413 | * start up when no ports are active. |
6343 | * start up when no ports are active. |
6414 | */ |
6344 | */ |
6415 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6345 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6416 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
6346 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
6417 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
6347 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
6418 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6348 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6419 | DPLS_EDP_PPS_FIX_DIS); |
6349 | DPLS_EDP_PPS_FIX_DIS); |
6420 | /* The below fixes the weird display corruption, a few pixels shifted |
6350 | /* The below fixes the weird display corruption, a few pixels shifted |
6421 | * downward, on (only) LVDS of some HP laptops with IVY. |
6351 | * downward, on (only) LVDS of some HP laptops with IVY. |
6422 | */ |
6352 | */ |
6423 | for_each_pipe(dev_priv, pipe) { |
6353 | for_each_pipe(dev_priv, pipe) { |
6424 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6354 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6425 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
6355 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
6426 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
6356 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
6427 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
6357 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
6428 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
6358 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
6429 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6359 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6430 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
6360 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
6431 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
6361 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
6432 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6362 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6433 | } |
6363 | } |
6434 | /* WADP0ClockGatingDisable */ |
6364 | /* WADP0ClockGatingDisable */ |
6435 | for_each_pipe(dev_priv, pipe) { |
6365 | for_each_pipe(dev_priv, pipe) { |
6436 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6366 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6437 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
6367 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
6438 | } |
6368 | } |
6439 | } |
6369 | } |
6440 | 6370 | ||
6441 | static void gen6_check_mch_setup(struct drm_device *dev) |
6371 | static void gen6_check_mch_setup(struct drm_device *dev) |
6442 | { |
6372 | { |
6443 | struct drm_i915_private *dev_priv = dev->dev_private; |
6373 | struct drm_i915_private *dev_priv = dev->dev_private; |
6444 | uint32_t tmp; |
6374 | uint32_t tmp; |
6445 | 6375 | ||
6446 | tmp = I915_READ(MCH_SSKPD); |
6376 | tmp = I915_READ(MCH_SSKPD); |
6447 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6377 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6448 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", |
6378 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", |
6449 | tmp); |
6379 | tmp); |
6450 | } |
6380 | } |
6451 | 6381 | ||
6452 | static void gen6_init_clock_gating(struct drm_device *dev) |
6382 | static void gen6_init_clock_gating(struct drm_device *dev) |
6453 | { |
6383 | { |
6454 | struct drm_i915_private *dev_priv = dev->dev_private; |
6384 | struct drm_i915_private *dev_priv = dev->dev_private; |
6455 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6385 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6456 | 6386 | ||
6457 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6387 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6458 | 6388 | ||
6459 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6389 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6460 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6390 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6461 | ILK_ELPIN_409_SELECT); |
6391 | ILK_ELPIN_409_SELECT); |
6462 | 6392 | ||
6463 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
6393 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
6464 | I915_WRITE(_3D_CHICKEN, |
6394 | I915_WRITE(_3D_CHICKEN, |
6465 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
6395 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
6466 | 6396 | ||
6467 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6397 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6468 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6398 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6469 | 6399 | ||
6470 | /* |
6400 | /* |
6471 | * BSpec recoomends 8x4 when MSAA is used, |
6401 | * BSpec recoomends 8x4 when MSAA is used, |
6472 | * however in practice 16x4 seems fastest. |
6402 | * however in practice 16x4 seems fastest. |
6473 | * |
6403 | * |
6474 | * Note that PS/WM thread counts depend on the WIZ hashing |
6404 | * Note that PS/WM thread counts depend on the WIZ hashing |
6475 | * disable bit, which we don't touch here, but it's good |
6405 | * disable bit, which we don't touch here, but it's good |
6476 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6406 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6477 | */ |
6407 | */ |
6478 | I915_WRITE(GEN6_GT_MODE, |
6408 | I915_WRITE(GEN6_GT_MODE, |
6479 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6409 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6480 | 6410 | ||
6481 | ilk_init_lp_watermarks(dev); |
6411 | ilk_init_lp_watermarks(dev); |
6482 | 6412 | ||
6483 | I915_WRITE(CACHE_MODE_0, |
6413 | I915_WRITE(CACHE_MODE_0, |
6484 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6414 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6485 | 6415 | ||
6486 | I915_WRITE(GEN6_UCGCTL1, |
6416 | I915_WRITE(GEN6_UCGCTL1, |
6487 | I915_READ(GEN6_UCGCTL1) | |
6417 | I915_READ(GEN6_UCGCTL1) | |
6488 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
6418 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
6489 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
6419 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
6490 | 6420 | ||
6491 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
6421 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
6492 | * gating disable must be set. Failure to set it results in |
6422 | * gating disable must be set. Failure to set it results in |
6493 | * flickering pixels due to Z write ordering failures after |
6423 | * flickering pixels due to Z write ordering failures after |
6494 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
6424 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
6495 | * Sanctuary and Tropics, and apparently anything else with |
6425 | * Sanctuary and Tropics, and apparently anything else with |
6496 | * alpha test or pixel discard. |
6426 | * alpha test or pixel discard. |
6497 | * |
6427 | * |
6498 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
6428 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
6499 | * but we didn't debug actual testcases to find it out. |
6429 | * but we didn't debug actual testcases to find it out. |
6500 | * |
6430 | * |
6501 | * WaDisableRCCUnitClockGating:snb |
6431 | * WaDisableRCCUnitClockGating:snb |
6502 | * WaDisableRCPBUnitClockGating:snb |
6432 | * WaDisableRCPBUnitClockGating:snb |
6503 | */ |
6433 | */ |
6504 | I915_WRITE(GEN6_UCGCTL2, |
6434 | I915_WRITE(GEN6_UCGCTL2, |
6505 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
6435 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
6506 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
6436 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
6507 | 6437 | ||
6508 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
6438 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
6509 | I915_WRITE(_3D_CHICKEN3, |
6439 | I915_WRITE(_3D_CHICKEN3, |
6510 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
6440 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
6511 | 6441 | ||
6512 | /* |
6442 | /* |
6513 | * Bspec says: |
6443 | * Bspec says: |
6514 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
6444 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
6515 | * 3DSTATE_SF number of SF output attributes is more than 16." |
6445 | * 3DSTATE_SF number of SF output attributes is more than 16." |
6516 | */ |
6446 | */ |
6517 | I915_WRITE(_3D_CHICKEN3, |
6447 | I915_WRITE(_3D_CHICKEN3, |
6518 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
6448 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
6519 | 6449 | ||
6520 | /* |
6450 | /* |
6521 | * According to the spec the following bits should be |
6451 | * According to the spec the following bits should be |
6522 | * set in order to enable memory self-refresh and fbc: |
6452 | * set in order to enable memory self-refresh and fbc: |
6523 | * The bit21 and bit22 of 0x42000 |
6453 | * The bit21 and bit22 of 0x42000 |
6524 | * The bit21 and bit22 of 0x42004 |
6454 | * The bit21 and bit22 of 0x42004 |
6525 | * The bit5 and bit7 of 0x42020 |
6455 | * The bit5 and bit7 of 0x42020 |
6526 | * The bit14 of 0x70180 |
6456 | * The bit14 of 0x70180 |
6527 | * The bit14 of 0x71180 |
6457 | * The bit14 of 0x71180 |
6528 | * |
6458 | * |
6529 | * WaFbcAsynchFlipDisableFbcQueue:snb |
6459 | * WaFbcAsynchFlipDisableFbcQueue:snb |
6530 | */ |
6460 | */ |
6531 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6461 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6532 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
6462 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
6533 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
6463 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
6534 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6464 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6535 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6465 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
6536 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
6466 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
6537 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6467 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6538 | I915_READ(ILK_DSPCLK_GATE_D) | |
6468 | I915_READ(ILK_DSPCLK_GATE_D) | |
6539 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
6469 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
6540 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
6470 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
6541 | 6471 | ||
6542 | g4x_disable_trickle_feed(dev); |
6472 | g4x_disable_trickle_feed(dev); |
6543 | 6473 | ||
6544 | cpt_init_clock_gating(dev); |
6474 | cpt_init_clock_gating(dev); |
6545 | 6475 | ||
6546 | gen6_check_mch_setup(dev); |
6476 | gen6_check_mch_setup(dev); |
6547 | } |
6477 | } |
6548 | 6478 | ||
6549 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
6479 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
6550 | { |
6480 | { |
6551 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
6481 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
6552 | 6482 | ||
6553 | /* |
6483 | /* |
6554 | * WaVSThreadDispatchOverride:ivb,vlv |
6484 | * WaVSThreadDispatchOverride:ivb,vlv |
6555 | * |
6485 | * |
6556 | * This actually overrides the dispatch |
6486 | * This actually overrides the dispatch |
6557 | * mode for all thread types. |
6487 | * mode for all thread types. |
6558 | */ |
6488 | */ |
6559 | reg &= ~GEN7_FF_SCHED_MASK; |
6489 | reg &= ~GEN7_FF_SCHED_MASK; |
6560 | reg |= GEN7_FF_TS_SCHED_HW; |
6490 | reg |= GEN7_FF_TS_SCHED_HW; |
6561 | reg |= GEN7_FF_VS_SCHED_HW; |
6491 | reg |= GEN7_FF_VS_SCHED_HW; |
6562 | reg |= GEN7_FF_DS_SCHED_HW; |
6492 | reg |= GEN7_FF_DS_SCHED_HW; |
6563 | 6493 | ||
6564 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
6494 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
6565 | } |
6495 | } |
6566 | 6496 | ||
6567 | static void lpt_init_clock_gating(struct drm_device *dev) |
6497 | static void lpt_init_clock_gating(struct drm_device *dev) |
6568 | { |
6498 | { |
6569 | struct drm_i915_private *dev_priv = dev->dev_private; |
6499 | struct drm_i915_private *dev_priv = dev->dev_private; |
6570 | 6500 | ||
6571 | /* |
6501 | /* |
6572 | * TODO: this bit should only be enabled when really needed, then |
6502 | * TODO: this bit should only be enabled when really needed, then |
6573 | * disabled when not needed anymore in order to save power. |
6503 | * disabled when not needed anymore in order to save power. |
6574 | */ |
6504 | */ |
6575 | if (HAS_PCH_LPT_LP(dev)) |
6505 | if (HAS_PCH_LPT_LP(dev)) |
6576 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
6506 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
6577 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
6507 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
6578 | PCH_LP_PARTITION_LEVEL_DISABLE); |
6508 | PCH_LP_PARTITION_LEVEL_DISABLE); |
6579 | 6509 | ||
6580 | /* WADPOClockGatingDisable:hsw */ |
6510 | /* WADPOClockGatingDisable:hsw */ |
6581 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
6511 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
6582 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | |
6512 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | |
6583 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
6513 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
6584 | } |
6514 | } |
6585 | 6515 | ||
6586 | static void lpt_suspend_hw(struct drm_device *dev) |
6516 | static void lpt_suspend_hw(struct drm_device *dev) |
6587 | { |
6517 | { |
6588 | struct drm_i915_private *dev_priv = dev->dev_private; |
6518 | struct drm_i915_private *dev_priv = dev->dev_private; |
6589 | 6519 | ||
6590 | if (HAS_PCH_LPT_LP(dev)) { |
6520 | if (HAS_PCH_LPT_LP(dev)) { |
6591 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6521 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6592 | 6522 | ||
6593 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6523 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6594 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6524 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6595 | } |
6525 | } |
6596 | } |
6526 | } |
6597 | 6527 | ||
6598 | static void broadwell_init_clock_gating(struct drm_device *dev) |
6528 | static void broadwell_init_clock_gating(struct drm_device *dev) |
6599 | { |
6529 | { |
6600 | struct drm_i915_private *dev_priv = dev->dev_private; |
6530 | struct drm_i915_private *dev_priv = dev->dev_private; |
6601 | enum pipe pipe; |
6531 | enum pipe pipe; |
6602 | uint32_t misccpctl; |
6532 | uint32_t misccpctl; |
6603 | 6533 | ||
6604 | ilk_init_lp_watermarks(dev); |
6534 | ilk_init_lp_watermarks(dev); |
6605 | 6535 | ||
6606 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
6536 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
6607 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6537 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6608 | 6538 | ||
6609 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
6539 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
6610 | I915_WRITE(CHICKEN_PAR1_1, |
6540 | I915_WRITE(CHICKEN_PAR1_1, |
6611 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
6541 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
6612 | 6542 | ||
6613 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
6543 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
6614 | for_each_pipe(dev_priv, pipe) { |
6544 | for_each_pipe(dev_priv, pipe) { |
6615 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
6545 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
6616 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
6546 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
6617 | BDW_DPRS_MASK_VBLANK_SRD); |
6547 | BDW_DPRS_MASK_VBLANK_SRD); |
6618 | } |
6548 | } |
6619 | 6549 | ||
6620 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6550 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6621 | /* WaDSRefCountFullforceMissDisable:bdw */ |
6551 | /* WaDSRefCountFullforceMissDisable:bdw */ |
6622 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6552 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6623 | I915_READ(GEN7_FF_THREAD_MODE) & |
6553 | I915_READ(GEN7_FF_THREAD_MODE) & |
6624 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
6554 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
6625 | 6555 | ||
6626 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6556 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6627 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
6557 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
6628 | 6558 | ||
6629 | /* WaDisableSDEUnitClockGating:bdw */ |
6559 | /* WaDisableSDEUnitClockGating:bdw */ |
6630 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
6560 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
6631 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
6561 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
6632 | 6562 | ||
6633 | /* |
6563 | /* |
6634 | * WaProgramL3SqcReg1Default:bdw |
6564 | * WaProgramL3SqcReg1Default:bdw |
6635 | * WaTempDisableDOPClkGating:bdw |
6565 | * WaTempDisableDOPClkGating:bdw |
6636 | */ |
6566 | */ |
6637 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
6567 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
6638 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
6568 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
6639 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); |
6569 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); |
6640 | /* |
6570 | /* |
6641 | * Wait at least 100 clocks before re-enabling clock gating. See |
6571 | * Wait at least 100 clocks before re-enabling clock gating. See |
6642 | * the definition of L3SQCREG1 in BSpec. |
6572 | * the definition of L3SQCREG1 in BSpec. |
6643 | */ |
6573 | */ |
6644 | POSTING_READ(GEN8_L3SQCREG1); |
6574 | POSTING_READ(GEN8_L3SQCREG1); |
6645 | udelay(1); |
6575 | udelay(1); |
6646 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
6576 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
6647 | 6577 | ||
6648 | /* |
6578 | /* |
6649 | * WaGttCachingOffByDefault:bdw |
6579 | * WaGttCachingOffByDefault:bdw |
6650 | * GTT cache may not work with big pages, so if those |
6580 | * GTT cache may not work with big pages, so if those |
6651 | * are ever enabled GTT cache may need to be disabled. |
6581 | * are ever enabled GTT cache may need to be disabled. |
6652 | */ |
6582 | */ |
6653 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
6583 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
6654 | 6584 | ||
6655 | lpt_init_clock_gating(dev); |
6585 | lpt_init_clock_gating(dev); |
6656 | } |
6586 | } |
6657 | 6587 | ||
6658 | static void haswell_init_clock_gating(struct drm_device *dev) |
6588 | static void haswell_init_clock_gating(struct drm_device *dev) |
6659 | { |
6589 | { |
6660 | struct drm_i915_private *dev_priv = dev->dev_private; |
6590 | struct drm_i915_private *dev_priv = dev->dev_private; |
6661 | 6591 | ||
6662 | ilk_init_lp_watermarks(dev); |
6592 | ilk_init_lp_watermarks(dev); |
6663 | 6593 | ||
6664 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6594 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6665 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
6595 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
6666 | I915_WRITE(HSW_ROW_CHICKEN3, |
6596 | I915_WRITE(HSW_ROW_CHICKEN3, |
6667 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
6597 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
6668 | 6598 | ||
6669 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
6599 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
6670 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6600 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6671 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6601 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6672 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6602 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6673 | 6603 | ||
6674 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6604 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6675 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6605 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6676 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
6606 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
6677 | 6607 | ||
6678 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6608 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6679 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6609 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6680 | 6610 | ||
6681 | /* enable HiZ Raw Stall Optimization */ |
6611 | /* enable HiZ Raw Stall Optimization */ |
6682 | I915_WRITE(CACHE_MODE_0_GEN7, |
6612 | I915_WRITE(CACHE_MODE_0_GEN7, |
6683 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
6613 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
6684 | 6614 | ||
6685 | /* WaDisable4x2SubspanOptimization:hsw */ |
6615 | /* WaDisable4x2SubspanOptimization:hsw */ |
6686 | I915_WRITE(CACHE_MODE_1, |
6616 | I915_WRITE(CACHE_MODE_1, |
6687 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6617 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6688 | 6618 | ||
6689 | /* |
6619 | /* |
6690 | * BSpec recommends 8x4 when MSAA is used, |
6620 | * BSpec recommends 8x4 when MSAA is used, |
6691 | * however in practice 16x4 seems fastest. |
6621 | * however in practice 16x4 seems fastest. |
6692 | * |
6622 | * |
6693 | * Note that PS/WM thread counts depend on the WIZ hashing |
6623 | * Note that PS/WM thread counts depend on the WIZ hashing |
6694 | * disable bit, which we don't touch here, but it's good |
6624 | * disable bit, which we don't touch here, but it's good |
6695 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6625 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6696 | */ |
6626 | */ |
6697 | I915_WRITE(GEN7_GT_MODE, |
6627 | I915_WRITE(GEN7_GT_MODE, |
6698 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6628 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6699 | 6629 | ||
6700 | /* WaSampleCChickenBitEnable:hsw */ |
6630 | /* WaSampleCChickenBitEnable:hsw */ |
6701 | I915_WRITE(HALF_SLICE_CHICKEN3, |
6631 | I915_WRITE(HALF_SLICE_CHICKEN3, |
6702 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); |
6632 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); |
6703 | 6633 | ||
6704 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
6634 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
6705 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6635 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6706 | 6636 | ||
6707 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6637 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6708 | I915_WRITE(CHICKEN_PAR1_1, |
6638 | I915_WRITE(CHICKEN_PAR1_1, |
6709 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
6639 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
6710 | 6640 | ||
6711 | lpt_init_clock_gating(dev); |
6641 | lpt_init_clock_gating(dev); |
6712 | } |
6642 | } |
6713 | 6643 | ||
6714 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6644 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6715 | { |
6645 | { |
6716 | struct drm_i915_private *dev_priv = dev->dev_private; |
6646 | struct drm_i915_private *dev_priv = dev->dev_private; |
6717 | uint32_t snpcr; |
6647 | uint32_t snpcr; |
6718 | 6648 | ||
6719 | ilk_init_lp_watermarks(dev); |
6649 | ilk_init_lp_watermarks(dev); |
6720 | 6650 | ||
6721 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6651 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6722 | 6652 | ||
6723 | /* WaDisableEarlyCull:ivb */ |
6653 | /* WaDisableEarlyCull:ivb */ |
6724 | I915_WRITE(_3D_CHICKEN3, |
6654 | I915_WRITE(_3D_CHICKEN3, |
6725 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
6655 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
6726 | 6656 | ||
6727 | /* WaDisableBackToBackFlipFix:ivb */ |
6657 | /* WaDisableBackToBackFlipFix:ivb */ |
6728 | I915_WRITE(IVB_CHICKEN3, |
6658 | I915_WRITE(IVB_CHICKEN3, |
6729 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
6659 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
6730 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
6660 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
6731 | 6661 | ||
6732 | /* WaDisablePSDDualDispatchEnable:ivb */ |
6662 | /* WaDisablePSDDualDispatchEnable:ivb */ |
6733 | if (IS_IVB_GT1(dev)) |
6663 | if (IS_IVB_GT1(dev)) |
6734 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
6664 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
6735 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
6665 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
6736 | 6666 | ||
6737 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6667 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6738 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6668 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6739 | 6669 | ||
6740 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6670 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6741 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6671 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6742 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
6672 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
6743 | 6673 | ||
6744 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6674 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6745 | I915_WRITE(GEN7_L3CNTLREG1, |
6675 | I915_WRITE(GEN7_L3CNTLREG1, |
6746 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
6676 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
6747 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
6677 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
6748 | GEN7_WA_L3_CHICKEN_MODE); |
6678 | GEN7_WA_L3_CHICKEN_MODE); |
6749 | if (IS_IVB_GT1(dev)) |
6679 | if (IS_IVB_GT1(dev)) |
6750 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6680 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6751 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6681 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6752 | else { |
6682 | else { |
6753 | /* must write both registers */ |
6683 | /* must write both registers */ |
6754 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6684 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6755 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6685 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6756 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6686 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6757 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6687 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6758 | } |
6688 | } |
6759 | 6689 | ||
6760 | /* WaForceL3Serialization:ivb */ |
6690 | /* WaForceL3Serialization:ivb */ |
6761 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6691 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6762 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
6692 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
6763 | 6693 | ||
6764 | /* |
6694 | /* |
6765 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
6695 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
6766 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
6696 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
6767 | */ |
6697 | */ |
6768 | I915_WRITE(GEN6_UCGCTL2, |
6698 | I915_WRITE(GEN6_UCGCTL2, |
6769 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
6699 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
6770 | 6700 | ||
6771 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6701 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6772 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6702 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6773 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6703 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6774 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6704 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6775 | 6705 | ||
6776 | g4x_disable_trickle_feed(dev); |
6706 | g4x_disable_trickle_feed(dev); |
6777 | 6707 | ||
6778 | gen7_setup_fixed_func_scheduler(dev_priv); |
6708 | gen7_setup_fixed_func_scheduler(dev_priv); |
6779 | 6709 | ||
6780 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6710 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6781 | /* enable HiZ Raw Stall Optimization */ |
6711 | /* enable HiZ Raw Stall Optimization */ |
6782 | I915_WRITE(CACHE_MODE_0_GEN7, |
6712 | I915_WRITE(CACHE_MODE_0_GEN7, |
6783 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
6713 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
6784 | } |
6714 | } |
6785 | 6715 | ||
6786 | /* WaDisable4x2SubspanOptimization:ivb */ |
6716 | /* WaDisable4x2SubspanOptimization:ivb */ |
6787 | I915_WRITE(CACHE_MODE_1, |
6717 | I915_WRITE(CACHE_MODE_1, |
6788 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6718 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6789 | 6719 | ||
6790 | /* |
6720 | /* |
6791 | * BSpec recommends 8x4 when MSAA is used, |
6721 | * BSpec recommends 8x4 when MSAA is used, |
6792 | * however in practice 16x4 seems fastest. |
6722 | * however in practice 16x4 seems fastest. |
6793 | * |
6723 | * |
6794 | * Note that PS/WM thread counts depend on the WIZ hashing |
6724 | * Note that PS/WM thread counts depend on the WIZ hashing |
6795 | * disable bit, which we don't touch here, but it's good |
6725 | * disable bit, which we don't touch here, but it's good |
6796 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6726 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6797 | */ |
6727 | */ |
6798 | I915_WRITE(GEN7_GT_MODE, |
6728 | I915_WRITE(GEN7_GT_MODE, |
6799 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6729 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6800 | 6730 | ||
6801 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6731 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6802 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
6732 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
6803 | snpcr |= GEN6_MBC_SNPCR_MED; |
6733 | snpcr |= GEN6_MBC_SNPCR_MED; |
6804 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
6734 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
6805 | 6735 | ||
6806 | if (!HAS_PCH_NOP(dev)) |
6736 | if (!HAS_PCH_NOP(dev)) |
6807 | cpt_init_clock_gating(dev); |
6737 | cpt_init_clock_gating(dev); |
6808 | 6738 | ||
6809 | gen6_check_mch_setup(dev); |
6739 | gen6_check_mch_setup(dev); |
6810 | } |
6740 | } |
6811 | 6741 | ||
6812 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6742 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6813 | { |
6743 | { |
6814 | u32 val; |
- | |
6815 | - | ||
6816 | /* |
- | |
6817 | * On driver load, a pipe may be active and driving a DSI display. |
- | |
6818 | * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck |
- | |
6819 | * (and never recovering) in this case. intel_dsi_post_disable() will |
- | |
6820 | * clear it when we turn off the display. |
- | |
6821 | */ |
- | |
6822 | val = I915_READ(DSPCLK_GATE_D); |
- | |
6823 | val &= DPOUNIT_CLOCK_GATE_DISABLE; |
- | |
6824 | val |= VRHUNIT_CLOCK_GATE_DISABLE; |
6744 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6825 | I915_WRITE(DSPCLK_GATE_D, val); |
- | |
6826 | 6745 | ||
6827 | /* |
6746 | /* |
6828 | * Disable trickle feed and enable pnd deadline calculation |
6747 | * Disable trickle feed and enable pnd deadline calculation |
6829 | */ |
6748 | */ |
6830 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6749 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6831 | I915_WRITE(CBR1_VLV, 0); |
6750 | I915_WRITE(CBR1_VLV, 0); |
6832 | } |
6751 | } |
6833 | 6752 | ||
6834 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6753 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6835 | { |
6754 | { |
6836 | struct drm_i915_private *dev_priv = dev->dev_private; |
6755 | struct drm_i915_private *dev_priv = dev->dev_private; |
6837 | 6756 | ||
6838 | vlv_init_display_clock_gating(dev_priv); |
6757 | vlv_init_display_clock_gating(dev_priv); |
6839 | 6758 | ||
6840 | /* WaDisableEarlyCull:vlv */ |
6759 | /* WaDisableEarlyCull:vlv */ |
6841 | I915_WRITE(_3D_CHICKEN3, |
6760 | I915_WRITE(_3D_CHICKEN3, |
6842 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
6761 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
6843 | 6762 | ||
6844 | /* WaDisableBackToBackFlipFix:vlv */ |
6763 | /* WaDisableBackToBackFlipFix:vlv */ |
6845 | I915_WRITE(IVB_CHICKEN3, |
6764 | I915_WRITE(IVB_CHICKEN3, |
6846 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
6765 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
6847 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
6766 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
6848 | 6767 | ||
6849 | /* WaPsdDispatchEnable:vlv */ |
6768 | /* WaPsdDispatchEnable:vlv */ |
6850 | /* WaDisablePSDDualDispatchEnable:vlv */ |
6769 | /* WaDisablePSDDualDispatchEnable:vlv */ |
6851 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
6770 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
6852 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6771 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6853 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
6772 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
6854 | 6773 | ||
6855 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6774 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6856 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6775 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6857 | 6776 | ||
6858 | /* WaForceL3Serialization:vlv */ |
6777 | /* WaForceL3Serialization:vlv */ |
6859 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6778 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6860 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
6779 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
6861 | 6780 | ||
6862 | /* WaDisableDopClockGating:vlv */ |
6781 | /* WaDisableDopClockGating:vlv */ |
6863 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6782 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6864 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6783 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
6865 | 6784 | ||
6866 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6785 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6867 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6786 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6868 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6787 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
6869 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6788 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
6870 | 6789 | ||
6871 | gen7_setup_fixed_func_scheduler(dev_priv); |
6790 | gen7_setup_fixed_func_scheduler(dev_priv); |
6872 | 6791 | ||
6873 | /* |
6792 | /* |
6874 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
6793 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
6875 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
6794 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
6876 | */ |
6795 | */ |
6877 | I915_WRITE(GEN6_UCGCTL2, |
6796 | I915_WRITE(GEN6_UCGCTL2, |
6878 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
6797 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
6879 | 6798 | ||
6880 | /* WaDisableL3Bank2xClockGate:vlv |
6799 | /* WaDisableL3Bank2xClockGate:vlv |
6881 | * Disabling L3 clock gating- MMIO 940c[25] = 1 |
6800 | * Disabling L3 clock gating- MMIO 940c[25] = 1 |
6882 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ |
6801 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ |
6883 | I915_WRITE(GEN7_UCGCTL4, |
6802 | I915_WRITE(GEN7_UCGCTL4, |
6884 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
6803 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
6885 | 6804 | ||
6886 | /* |
6805 | /* |
6887 | * BSpec says this must be set, even though |
6806 | * BSpec says this must be set, even though |
6888 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
6807 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
6889 | */ |
6808 | */ |
6890 | I915_WRITE(CACHE_MODE_1, |
6809 | I915_WRITE(CACHE_MODE_1, |
6891 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6810 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
6892 | 6811 | ||
6893 | /* |
6812 | /* |
6894 | * BSpec recommends 8x4 when MSAA is used, |
6813 | * BSpec recommends 8x4 when MSAA is used, |
6895 | * however in practice 16x4 seems fastest. |
6814 | * however in practice 16x4 seems fastest. |
6896 | * |
6815 | * |
6897 | * Note that PS/WM thread counts depend on the WIZ hashing |
6816 | * Note that PS/WM thread counts depend on the WIZ hashing |
6898 | * disable bit, which we don't touch here, but it's good |
6817 | * disable bit, which we don't touch here, but it's good |
6899 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6818 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
6900 | */ |
6819 | */ |
6901 | I915_WRITE(GEN7_GT_MODE, |
6820 | I915_WRITE(GEN7_GT_MODE, |
6902 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6821 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
6903 | 6822 | ||
6904 | /* |
6823 | /* |
6905 | * WaIncreaseL3CreditsForVLVB0:vlv |
6824 | * WaIncreaseL3CreditsForVLVB0:vlv |
6906 | * This is the hardware default actually. |
6825 | * This is the hardware default actually. |
6907 | */ |
6826 | */ |
6908 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
6827 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
6909 | 6828 | ||
6910 | /* |
6829 | /* |
6911 | * WaDisableVLVClockGating_VBIIssue:vlv |
6830 | * WaDisableVLVClockGating_VBIIssue:vlv |
6912 | * Disable clock gating on th GCFG unit to prevent a delay |
6831 | * Disable clock gating on th GCFG unit to prevent a delay |
6913 | * in the reporting of vblank events. |
6832 | * in the reporting of vblank events. |
6914 | */ |
6833 | */ |
6915 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6834 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6916 | } |
6835 | } |
6917 | 6836 | ||
6918 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6837 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6919 | { |
6838 | { |
6920 | struct drm_i915_private *dev_priv = dev->dev_private; |
6839 | struct drm_i915_private *dev_priv = dev->dev_private; |
6921 | 6840 | ||
6922 | vlv_init_display_clock_gating(dev_priv); |
6841 | vlv_init_display_clock_gating(dev_priv); |
6923 | 6842 | ||
6924 | /* WaVSRefCountFullforceMissDisable:chv */ |
6843 | /* WaVSRefCountFullforceMissDisable:chv */ |
6925 | /* WaDSRefCountFullforceMissDisable:chv */ |
6844 | /* WaDSRefCountFullforceMissDisable:chv */ |
6926 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6845 | I915_WRITE(GEN7_FF_THREAD_MODE, |
6927 | I915_READ(GEN7_FF_THREAD_MODE) & |
6846 | I915_READ(GEN7_FF_THREAD_MODE) & |
6928 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
6847 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
6929 | 6848 | ||
6930 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ |
6849 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ |
6931 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6850 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6932 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
6851 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
6933 | 6852 | ||
6934 | /* WaDisableCSUnitClockGating:chv */ |
6853 | /* WaDisableCSUnitClockGating:chv */ |
6935 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
6854 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
6936 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
6855 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
6937 | 6856 | ||
6938 | /* WaDisableSDEUnitClockGating:chv */ |
6857 | /* WaDisableSDEUnitClockGating:chv */ |
6939 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
6858 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
6940 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
6859 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
6941 | 6860 | ||
6942 | /* |
6861 | /* |
6943 | * GTT cache may not work with big pages, so if those |
6862 | * GTT cache may not work with big pages, so if those |
6944 | * are ever enabled GTT cache may need to be disabled. |
6863 | * are ever enabled GTT cache may need to be disabled. |
6945 | */ |
6864 | */ |
6946 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
6865 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
6947 | } |
6866 | } |
6948 | 6867 | ||
6949 | static void g4x_init_clock_gating(struct drm_device *dev) |
6868 | static void g4x_init_clock_gating(struct drm_device *dev) |
6950 | { |
6869 | { |
6951 | struct drm_i915_private *dev_priv = dev->dev_private; |
6870 | struct drm_i915_private *dev_priv = dev->dev_private; |
6952 | uint32_t dspclk_gate; |
6871 | uint32_t dspclk_gate; |
6953 | 6872 | ||
6954 | I915_WRITE(RENCLK_GATE_D1, 0); |
6873 | I915_WRITE(RENCLK_GATE_D1, 0); |
6955 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
6874 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
6956 | GS_UNIT_CLOCK_GATE_DISABLE | |
6875 | GS_UNIT_CLOCK_GATE_DISABLE | |
6957 | CL_UNIT_CLOCK_GATE_DISABLE); |
6876 | CL_UNIT_CLOCK_GATE_DISABLE); |
6958 | I915_WRITE(RAMCLK_GATE_D, 0); |
6877 | I915_WRITE(RAMCLK_GATE_D, 0); |
6959 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
6878 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
6960 | OVRUNIT_CLOCK_GATE_DISABLE | |
6879 | OVRUNIT_CLOCK_GATE_DISABLE | |
6961 | OVCUNIT_CLOCK_GATE_DISABLE; |
6880 | OVCUNIT_CLOCK_GATE_DISABLE; |
6962 | if (IS_GM45(dev)) |
6881 | if (IS_GM45(dev)) |
6963 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
6882 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
6964 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
6883 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
6965 | 6884 | ||
6966 | /* WaDisableRenderCachePipelinedFlush */ |
6885 | /* WaDisableRenderCachePipelinedFlush */ |
6967 | I915_WRITE(CACHE_MODE_0, |
6886 | I915_WRITE(CACHE_MODE_0, |
6968 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
6887 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
6969 | 6888 | ||
6970 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6889 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6971 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6890 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6972 | 6891 | ||
6973 | g4x_disable_trickle_feed(dev); |
6892 | g4x_disable_trickle_feed(dev); |
6974 | } |
6893 | } |
6975 | 6894 | ||
6976 | static void crestline_init_clock_gating(struct drm_device *dev) |
6895 | static void crestline_init_clock_gating(struct drm_device *dev) |
6977 | { |
6896 | { |
6978 | struct drm_i915_private *dev_priv = dev->dev_private; |
6897 | struct drm_i915_private *dev_priv = dev->dev_private; |
6979 | 6898 | ||
6980 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
6899 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
6981 | I915_WRITE(RENCLK_GATE_D2, 0); |
6900 | I915_WRITE(RENCLK_GATE_D2, 0); |
6982 | I915_WRITE(DSPCLK_GATE_D, 0); |
6901 | I915_WRITE(DSPCLK_GATE_D, 0); |
6983 | I915_WRITE(RAMCLK_GATE_D, 0); |
6902 | I915_WRITE(RAMCLK_GATE_D, 0); |
6984 | I915_WRITE16(DEUC, 0); |
6903 | I915_WRITE16(DEUC, 0); |
6985 | I915_WRITE(MI_ARB_STATE, |
6904 | I915_WRITE(MI_ARB_STATE, |
6986 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
6905 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
6987 | 6906 | ||
6988 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
6907 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
6989 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6908 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6990 | } |
6909 | } |
6991 | 6910 | ||
6992 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6911 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6993 | { |
6912 | { |
6994 | struct drm_i915_private *dev_priv = dev->dev_private; |
6913 | struct drm_i915_private *dev_priv = dev->dev_private; |
6995 | 6914 | ||
6996 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
6915 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
6997 | I965_RCC_CLOCK_GATE_DISABLE | |
6916 | I965_RCC_CLOCK_GATE_DISABLE | |
6998 | I965_RCPB_CLOCK_GATE_DISABLE | |
6917 | I965_RCPB_CLOCK_GATE_DISABLE | |
6999 | I965_ISC_CLOCK_GATE_DISABLE | |
6918 | I965_ISC_CLOCK_GATE_DISABLE | |
7000 | I965_FBC_CLOCK_GATE_DISABLE); |
6919 | I965_FBC_CLOCK_GATE_DISABLE); |
7001 | I915_WRITE(RENCLK_GATE_D2, 0); |
6920 | I915_WRITE(RENCLK_GATE_D2, 0); |
7002 | I915_WRITE(MI_ARB_STATE, |
6921 | I915_WRITE(MI_ARB_STATE, |
7003 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
6922 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
7004 | 6923 | ||
7005 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
6924 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
7006 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
6925 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
7007 | } |
6926 | } |
7008 | 6927 | ||
7009 | static void gen3_init_clock_gating(struct drm_device *dev) |
6928 | static void gen3_init_clock_gating(struct drm_device *dev) |
7010 | { |
6929 | { |
7011 | struct drm_i915_private *dev_priv = dev->dev_private; |
6930 | struct drm_i915_private *dev_priv = dev->dev_private; |
7012 | u32 dstate = I915_READ(D_STATE); |
6931 | u32 dstate = I915_READ(D_STATE); |
7013 | 6932 | ||
7014 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
6933 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
7015 | DSTATE_DOT_CLOCK_GATING; |
6934 | DSTATE_DOT_CLOCK_GATING; |
7016 | I915_WRITE(D_STATE, dstate); |
6935 | I915_WRITE(D_STATE, dstate); |
7017 | 6936 | ||
7018 | if (IS_PINEVIEW(dev)) |
6937 | if (IS_PINEVIEW(dev)) |
7019 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
6938 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
7020 | 6939 | ||
7021 | /* IIR "flip pending" means done if this bit is set */ |
6940 | /* IIR "flip pending" means done if this bit is set */ |
7022 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
6941 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
7023 | 6942 | ||
7024 | /* interrupts should cause a wake up from C3 */ |
6943 | /* interrupts should cause a wake up from C3 */ |
7025 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
6944 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
7026 | 6945 | ||
7027 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
6946 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
7028 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
6947 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
7029 | 6948 | ||
7030 | I915_WRITE(MI_ARB_STATE, |
6949 | I915_WRITE(MI_ARB_STATE, |
7031 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
6950 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
7032 | } |
6951 | } |
7033 | 6952 | ||
7034 | static void i85x_init_clock_gating(struct drm_device *dev) |
6953 | static void i85x_init_clock_gating(struct drm_device *dev) |
7035 | { |
6954 | { |
7036 | struct drm_i915_private *dev_priv = dev->dev_private; |
6955 | struct drm_i915_private *dev_priv = dev->dev_private; |
7037 | 6956 | ||
7038 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
6957 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
7039 | 6958 | ||
7040 | /* interrupts should cause a wake up from C3 */ |
6959 | /* interrupts should cause a wake up from C3 */ |
7041 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | |
6960 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | |
7042 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); |
6961 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); |
7043 | 6962 | ||
7044 | I915_WRITE(MEM_MODE, |
6963 | I915_WRITE(MEM_MODE, |
7045 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); |
6964 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); |
7046 | } |
6965 | } |
7047 | 6966 | ||
7048 | static void i830_init_clock_gating(struct drm_device *dev) |
6967 | static void i830_init_clock_gating(struct drm_device *dev) |
7049 | { |
6968 | { |
7050 | struct drm_i915_private *dev_priv = dev->dev_private; |
6969 | struct drm_i915_private *dev_priv = dev->dev_private; |
7051 | 6970 | ||
7052 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
6971 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
7053 | 6972 | ||
7054 | I915_WRITE(MEM_MODE, |
6973 | I915_WRITE(MEM_MODE, |
7055 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | |
6974 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | |
7056 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); |
6975 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); |
7057 | } |
6976 | } |
7058 | 6977 | ||
7059 | void intel_init_clock_gating(struct drm_device *dev) |
6978 | void intel_init_clock_gating(struct drm_device *dev) |
7060 | { |
6979 | { |
7061 | struct drm_i915_private *dev_priv = dev->dev_private; |
6980 | struct drm_i915_private *dev_priv = dev->dev_private; |
7062 | 6981 | ||
7063 | if (dev_priv->display.init_clock_gating) |
6982 | if (dev_priv->display.init_clock_gating) |
7064 | dev_priv->display.init_clock_gating(dev); |
6983 | dev_priv->display.init_clock_gating(dev); |
7065 | } |
6984 | } |
7066 | 6985 | ||
7067 | void intel_suspend_hw(struct drm_device *dev) |
6986 | void intel_suspend_hw(struct drm_device *dev) |
7068 | { |
6987 | { |
7069 | if (HAS_PCH_LPT(dev)) |
6988 | if (HAS_PCH_LPT(dev)) |
7070 | lpt_suspend_hw(dev); |
6989 | lpt_suspend_hw(dev); |
7071 | } |
6990 | } |
7072 | 6991 | ||
7073 | /* Set up chip specific power management-related functions */ |
6992 | /* Set up chip specific power management-related functions */ |
7074 | void intel_init_pm(struct drm_device *dev) |
6993 | void intel_init_pm(struct drm_device *dev) |
7075 | { |
6994 | { |
7076 | struct drm_i915_private *dev_priv = dev->dev_private; |
6995 | struct drm_i915_private *dev_priv = dev->dev_private; |
7077 | 6996 | ||
7078 | intel_fbc_init(dev_priv); |
6997 | intel_fbc_init(dev_priv); |
7079 | 6998 | ||
7080 | /* For cxsr */ |
6999 | /* For cxsr */ |
7081 | if (IS_PINEVIEW(dev)) |
7000 | if (IS_PINEVIEW(dev)) |
7082 | i915_pineview_get_mem_freq(dev); |
7001 | i915_pineview_get_mem_freq(dev); |
7083 | else if (IS_GEN5(dev)) |
7002 | else if (IS_GEN5(dev)) |
7084 | i915_ironlake_get_mem_freq(dev); |
7003 | i915_ironlake_get_mem_freq(dev); |
7085 | 7004 | ||
7086 | /* For FIFO watermark updates */ |
7005 | /* For FIFO watermark updates */ |
7087 | if (INTEL_INFO(dev)->gen >= 9) { |
7006 | if (INTEL_INFO(dev)->gen >= 9) { |
7088 | skl_setup_wm_latency(dev); |
7007 | skl_setup_wm_latency(dev); |
7089 | 7008 | ||
7090 | if (IS_BROXTON(dev)) |
7009 | if (IS_BROXTON(dev)) |
7091 | dev_priv->display.init_clock_gating = |
7010 | dev_priv->display.init_clock_gating = |
7092 | bxt_init_clock_gating; |
7011 | bxt_init_clock_gating; |
7093 | dev_priv->display.update_wm = skl_update_wm; |
7012 | dev_priv->display.update_wm = skl_update_wm; |
7094 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; |
- | |
7095 | } else if (HAS_PCH_SPLIT(dev)) { |
7013 | } else if (HAS_PCH_SPLIT(dev)) { |
7096 | ilk_setup_wm_latency(dev); |
7014 | ilk_setup_wm_latency(dev); |
7097 | 7015 | ||
7098 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
7016 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
7099 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
7017 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
7100 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
7018 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
7101 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
7019 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
7102 | dev_priv->display.update_wm = ilk_update_wm; |
7020 | dev_priv->display.update_wm = ilk_update_wm; |
7103 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; |
7021 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
7104 | } else { |
7022 | } else { |
7105 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
7023 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
7106 | "Disable CxSR\n"); |
7024 | "Disable CxSR\n"); |
7107 | } |
7025 | } |
7108 | 7026 | ||
7109 | if (IS_GEN5(dev)) |
7027 | if (IS_GEN5(dev)) |
7110 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
7028 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
7111 | else if (IS_GEN6(dev)) |
7029 | else if (IS_GEN6(dev)) |
7112 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
7030 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
7113 | else if (IS_IVYBRIDGE(dev)) |
7031 | else if (IS_IVYBRIDGE(dev)) |
7114 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
7032 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
7115 | else if (IS_HASWELL(dev)) |
7033 | else if (IS_HASWELL(dev)) |
7116 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
7034 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
7117 | else if (INTEL_INFO(dev)->gen == 8) |
7035 | else if (INTEL_INFO(dev)->gen == 8) |
7118 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
7036 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
7119 | } else if (IS_CHERRYVIEW(dev)) { |
7037 | } else if (IS_CHERRYVIEW(dev)) { |
7120 | vlv_setup_wm_latency(dev); |
7038 | vlv_setup_wm_latency(dev); |
7121 | 7039 | ||
7122 | dev_priv->display.update_wm = vlv_update_wm; |
7040 | dev_priv->display.update_wm = vlv_update_wm; |
7123 | dev_priv->display.init_clock_gating = |
7041 | dev_priv->display.init_clock_gating = |
7124 | cherryview_init_clock_gating; |
7042 | cherryview_init_clock_gating; |
7125 | } else if (IS_VALLEYVIEW(dev)) { |
7043 | } else if (IS_VALLEYVIEW(dev)) { |
7126 | vlv_setup_wm_latency(dev); |
7044 | vlv_setup_wm_latency(dev); |
7127 | 7045 | ||
7128 | dev_priv->display.update_wm = vlv_update_wm; |
7046 | dev_priv->display.update_wm = vlv_update_wm; |
7129 | dev_priv->display.init_clock_gating = |
7047 | dev_priv->display.init_clock_gating = |
7130 | valleyview_init_clock_gating; |
7048 | valleyview_init_clock_gating; |
7131 | } else if (IS_PINEVIEW(dev)) { |
7049 | } else if (IS_PINEVIEW(dev)) { |
7132 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
7050 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
7133 | dev_priv->is_ddr3, |
7051 | dev_priv->is_ddr3, |
7134 | dev_priv->fsb_freq, |
7052 | dev_priv->fsb_freq, |
7135 | dev_priv->mem_freq)) { |
7053 | dev_priv->mem_freq)) { |
7136 | DRM_INFO("failed to find known CxSR latency " |
7054 | DRM_INFO("failed to find known CxSR latency " |
7137 | "(found ddr%s fsb freq %d, mem freq %d), " |
7055 | "(found ddr%s fsb freq %d, mem freq %d), " |
7138 | "disabling CxSR\n", |
7056 | "disabling CxSR\n", |
7139 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
7057 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
7140 | dev_priv->fsb_freq, dev_priv->mem_freq); |
7058 | dev_priv->fsb_freq, dev_priv->mem_freq); |
7141 | /* Disable CxSR and never update its watermark again */ |
7059 | /* Disable CxSR and never update its watermark again */ |
7142 | intel_set_memory_cxsr(dev_priv, false); |
7060 | intel_set_memory_cxsr(dev_priv, false); |
7143 | dev_priv->display.update_wm = NULL; |
7061 | dev_priv->display.update_wm = NULL; |
7144 | } else |
7062 | } else |
7145 | dev_priv->display.update_wm = pineview_update_wm; |
7063 | dev_priv->display.update_wm = pineview_update_wm; |
7146 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
7064 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
7147 | } else if (IS_G4X(dev)) { |
7065 | } else if (IS_G4X(dev)) { |
7148 | dev_priv->display.update_wm = g4x_update_wm; |
7066 | dev_priv->display.update_wm = g4x_update_wm; |
7149 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
7067 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
7150 | } else if (IS_GEN4(dev)) { |
7068 | } else if (IS_GEN4(dev)) { |
7151 | dev_priv->display.update_wm = i965_update_wm; |
7069 | dev_priv->display.update_wm = i965_update_wm; |
7152 | if (IS_CRESTLINE(dev)) |
7070 | if (IS_CRESTLINE(dev)) |
7153 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
7071 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
7154 | else if (IS_BROADWATER(dev)) |
7072 | else if (IS_BROADWATER(dev)) |
7155 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
7073 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
7156 | } else if (IS_GEN3(dev)) { |
7074 | } else if (IS_GEN3(dev)) { |
7157 | dev_priv->display.update_wm = i9xx_update_wm; |
7075 | dev_priv->display.update_wm = i9xx_update_wm; |
7158 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
7076 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
7159 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
7077 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
7160 | } else if (IS_GEN2(dev)) { |
7078 | } else if (IS_GEN2(dev)) { |
7161 | if (INTEL_INFO(dev)->num_pipes == 1) { |
7079 | if (INTEL_INFO(dev)->num_pipes == 1) { |
7162 | dev_priv->display.update_wm = i845_update_wm; |
7080 | dev_priv->display.update_wm = i845_update_wm; |
7163 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
7081 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
7164 | } else { |
7082 | } else { |
7165 | dev_priv->display.update_wm = i9xx_update_wm; |
7083 | dev_priv->display.update_wm = i9xx_update_wm; |
7166 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
7084 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
7167 | } |
7085 | } |
7168 | 7086 | ||
7169 | if (IS_I85X(dev) || IS_I865G(dev)) |
7087 | if (IS_I85X(dev) || IS_I865G(dev)) |
7170 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
7088 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
7171 | else |
7089 | else |
7172 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
7090 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
7173 | } else { |
7091 | } else { |
7174 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
7092 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
7175 | } |
7093 | } |
7176 | } |
7094 | } |
7177 | 7095 | ||
7178 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
7096 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
7179 | { |
7097 | { |
7180 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
7098 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
7181 | 7099 | ||
7182 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
7100 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
7183 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
7101 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
7184 | return -EAGAIN; |
7102 | return -EAGAIN; |
7185 | } |
7103 | } |
7186 | 7104 | ||
7187 | I915_WRITE(GEN6_PCODE_DATA, *val); |
7105 | I915_WRITE(GEN6_PCODE_DATA, *val); |
7188 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
7106 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
7189 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7107 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7190 | 7108 | ||
7191 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
7109 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
7192 | 500)) { |
7110 | 500)) { |
7193 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
7111 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
7194 | return -ETIMEDOUT; |
7112 | return -ETIMEDOUT; |
7195 | } |
7113 | } |
7196 | 7114 | ||
7197 | *val = I915_READ(GEN6_PCODE_DATA); |
7115 | *val = I915_READ(GEN6_PCODE_DATA); |
7198 | I915_WRITE(GEN6_PCODE_DATA, 0); |
7116 | I915_WRITE(GEN6_PCODE_DATA, 0); |
7199 | 7117 | ||
7200 | return 0; |
7118 | return 0; |
7201 | } |
7119 | } |
7202 | 7120 | ||
7203 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
7121 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
7204 | { |
7122 | { |
7205 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
7123 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
7206 | 7124 | ||
7207 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
7125 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
7208 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
7126 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
7209 | return -EAGAIN; |
7127 | return -EAGAIN; |
7210 | } |
7128 | } |
7211 | 7129 | ||
7212 | I915_WRITE(GEN6_PCODE_DATA, val); |
7130 | I915_WRITE(GEN6_PCODE_DATA, val); |
7213 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7131 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7214 | 7132 | ||
7215 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
7133 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
7216 | 500)) { |
7134 | 500)) { |
7217 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
7135 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
7218 | return -ETIMEDOUT; |
7136 | return -ETIMEDOUT; |
7219 | } |
7137 | } |
7220 | 7138 | ||
7221 | I915_WRITE(GEN6_PCODE_DATA, 0); |
7139 | I915_WRITE(GEN6_PCODE_DATA, 0); |
7222 | 7140 | ||
7223 | return 0; |
7141 | return 0; |
7224 | } |
7142 | } |
7225 | 7143 | ||
7226 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
7144 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
7227 | { |
7145 | { |
7228 | switch (czclk_freq) { |
7146 | switch (czclk_freq) { |
7229 | case 200: |
7147 | case 200: |
7230 | return 10; |
7148 | return 10; |
7231 | case 267: |
7149 | case 267: |
7232 | return 12; |
7150 | return 12; |
7233 | case 320: |
7151 | case 320: |
7234 | case 333: |
7152 | case 333: |
7235 | return 16; |
7153 | return 16; |
7236 | case 400: |
7154 | case 400: |
7237 | return 20; |
7155 | return 20; |
7238 | default: |
7156 | default: |
7239 | return -1; |
7157 | return -1; |
7240 | } |
7158 | } |
7241 | } |
7159 | } |
7242 | 7160 | ||
7243 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7161 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7244 | { |
7162 | { |
7245 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7163 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7246 | 7164 | ||
7247 | div = vlv_gpu_freq_div(czclk_freq); |
7165 | div = vlv_gpu_freq_div(czclk_freq); |
7248 | if (div < 0) |
7166 | if (div < 0) |
7249 | return div; |
7167 | return div; |
7250 | 7168 | ||
7251 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); |
7169 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); |
7252 | } |
7170 | } |
7253 | 7171 | ||
7254 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7172 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7255 | { |
7173 | { |
7256 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7174 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7257 | 7175 | ||
7258 | mul = vlv_gpu_freq_div(czclk_freq); |
7176 | mul = vlv_gpu_freq_div(czclk_freq); |
7259 | if (mul < 0) |
7177 | if (mul < 0) |
7260 | return mul; |
7178 | return mul; |
7261 | 7179 | ||
7262 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
7180 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
7263 | } |
7181 | } |
7264 | 7182 | ||
7265 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7183 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7266 | { |
7184 | { |
7267 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7185 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7268 | 7186 | ||
7269 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
7187 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
7270 | if (div < 0) |
7188 | if (div < 0) |
7271 | return div; |
7189 | return div; |
7272 | 7190 | ||
7273 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
7191 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
7274 | } |
7192 | } |
7275 | 7193 | ||
7276 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7194 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7277 | { |
7195 | { |
7278 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7196 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7279 | 7197 | ||
7280 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
7198 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
7281 | if (mul < 0) |
7199 | if (mul < 0) |
7282 | return mul; |
7200 | return mul; |
7283 | 7201 | ||
7284 | /* CHV needs even values */ |
7202 | /* CHV needs even values */ |
7285 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
7203 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
7286 | } |
7204 | } |
7287 | 7205 | ||
7288 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7206 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7289 | { |
7207 | { |
7290 | if (IS_GEN9(dev_priv->dev)) |
7208 | if (IS_GEN9(dev_priv->dev)) |
7291 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
7209 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
7292 | GEN9_FREQ_SCALER); |
7210 | GEN9_FREQ_SCALER); |
7293 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
7211 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
7294 | return chv_gpu_freq(dev_priv, val); |
7212 | return chv_gpu_freq(dev_priv, val); |
7295 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
7213 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
7296 | return byt_gpu_freq(dev_priv, val); |
7214 | return byt_gpu_freq(dev_priv, val); |
7297 | else |
7215 | else |
7298 | return val * GT_FREQUENCY_MULTIPLIER; |
7216 | return val * GT_FREQUENCY_MULTIPLIER; |
7299 | } |
7217 | } |
7300 | 7218 | ||
7301 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7219 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7302 | { |
7220 | { |
7303 | if (IS_GEN9(dev_priv->dev)) |
7221 | if (IS_GEN9(dev_priv->dev)) |
7304 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
7222 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
7305 | GT_FREQUENCY_MULTIPLIER); |
7223 | GT_FREQUENCY_MULTIPLIER); |
7306 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
7224 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
7307 | return chv_freq_opcode(dev_priv, val); |
7225 | return chv_freq_opcode(dev_priv, val); |
7308 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
7226 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
7309 | return byt_freq_opcode(dev_priv, val); |
7227 | return byt_freq_opcode(dev_priv, val); |
7310 | else |
7228 | else |
7311 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
7229 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
7312 | } |
7230 | } |
7313 | 7231 | ||
7314 | struct request_boost { |
7232 | struct request_boost { |
7315 | struct work_struct work; |
7233 | struct work_struct work; |
7316 | struct drm_i915_gem_request *req; |
7234 | struct drm_i915_gem_request *req; |
7317 | }; |
7235 | }; |
7318 | 7236 | ||
7319 | static void __intel_rps_boost_work(struct work_struct *work) |
7237 | static void __intel_rps_boost_work(struct work_struct *work) |
7320 | { |
7238 | { |
7321 | struct request_boost *boost = container_of(work, struct request_boost, work); |
7239 | struct request_boost *boost = container_of(work, struct request_boost, work); |
7322 | struct drm_i915_gem_request *req = boost->req; |
7240 | struct drm_i915_gem_request *req = boost->req; |
7323 | 7241 | ||
7324 | if (!i915_gem_request_completed(req, true)) |
7242 | if (!i915_gem_request_completed(req, true)) |
7325 | gen6_rps_boost(to_i915(req->ring->dev), NULL, |
7243 | gen6_rps_boost(to_i915(req->ring->dev), NULL, |
7326 | req->emitted_jiffies); |
7244 | req->emitted_jiffies); |
7327 | 7245 | ||
7328 | i915_gem_request_unreference__unlocked(req); |
7246 | i915_gem_request_unreference__unlocked(req); |
7329 | kfree(boost); |
7247 | kfree(boost); |
7330 | } |
7248 | } |
7331 | 7249 | ||
7332 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
7250 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
7333 | struct drm_i915_gem_request *req) |
7251 | struct drm_i915_gem_request *req) |
7334 | { |
7252 | { |
7335 | struct request_boost *boost; |
7253 | struct request_boost *boost; |
7336 | 7254 | ||
7337 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
7255 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
7338 | return; |
7256 | return; |
7339 | 7257 | ||
7340 | if (i915_gem_request_completed(req, true)) |
7258 | if (i915_gem_request_completed(req, true)) |
7341 | return; |
7259 | return; |
7342 | 7260 | ||
7343 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
7261 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
7344 | if (boost == NULL) |
7262 | if (boost == NULL) |
7345 | return; |
7263 | return; |
7346 | 7264 | ||
7347 | i915_gem_request_reference(req); |
7265 | i915_gem_request_reference(req); |
7348 | boost->req = req; |
7266 | boost->req = req; |
7349 | 7267 | ||
7350 | INIT_WORK(&boost->work, __intel_rps_boost_work); |
7268 | INIT_WORK(&boost->work, __intel_rps_boost_work); |
7351 | queue_work(to_i915(dev)->wq, &boost->work); |
7269 | queue_work(to_i915(dev)->wq, &boost->work); |
7352 | } |
7270 | } |
7353 | 7271 | ||
7354 | void intel_pm_setup(struct drm_device *dev) |
7272 | void intel_pm_setup(struct drm_device *dev) |
7355 | { |
7273 | { |
7356 | struct drm_i915_private *dev_priv = dev->dev_private; |
7274 | struct drm_i915_private *dev_priv = dev->dev_private; |
7357 | 7275 | ||
7358 | mutex_init(&dev_priv->rps.hw_lock); |
7276 | mutex_init(&dev_priv->rps.hw_lock); |
7359 | spin_lock_init(&dev_priv->rps.client_lock); |
7277 | spin_lock_init(&dev_priv->rps.client_lock); |
7360 | 7278 | ||
7361 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7279 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7362 | intel_gen6_powersave_work); |
7280 | intel_gen6_powersave_work); |
7363 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
7281 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
7364 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
7282 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
7365 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); |
7283 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); |
7366 | 7284 | ||
7367 | dev_priv->pm.suspended = false; |
7285 | dev_priv->pm.suspended = false; |
- | 7286 | atomic_set(&dev_priv->pm.wakeref_count, 0); |
|
- | 7287 | atomic_set(&dev_priv->pm.atomic_seq, 0); |
|
7368 | }>>>>>><>>>>>>><>><>><>>>>>>>>>>>=> |
7288 | }>>>>>><>>>>>>><>><>><>>>>>>>>>>>=> |
7369 | >=>>>>=>><>><>><>>><> |
7289 | >=>>>>=>><>><>><>>><> |
7370 | >< |
7290 | >< |
7371 | >>=>=>>>=>=>>>>>>=>=>><>><>><>><>><>=>><>><>=>><>><>><>><>=>=>=>=>=>=>=>=>=>=>=>=>=>=>=>>>8)><8)>><>><>><>><>>>><>><>>>>>><>>>>>>>>><>><>><>><>><>=>=>><>><>>=>2) |
7291 | >>=>=>=>=>>>>=>=>><>><>><>><>><>=>><>><>=>><>><>><>><>=>=>=>=>=>=>=>=>=>=>=>=>=>=>>>8)><8)>><>><>><>><>>>><>><>>>>>><>>>>>>>>><>><>><>><>><>=>=>><>><>>=>2) |
7372 | 7292 | ||
7373 | static><2) |
7293 | static><2) |
7374 | 7294 | ||
7375 | static>1) |
7295 | static>1) |
7376 | #define><1) |
7296 | #define><1) |
7377 | #define>0) |
7297 | #define>0) |
7378 | #define><0) |
7298 | #define><0) |
7379 | #define> |
7299 | #define> |