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| Rev 6084 | Rev 6660 | ||
|---|---|---|---|
| Line 1792... | Line 1792... | ||
| 1792 | */ |
1792 | */ |
| 1793 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
1793 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
| 1794 | const struct intel_plane_state *pstate, |
1794 | const struct intel_plane_state *pstate, |
| 1795 | uint32_t mem_value) |
1795 | uint32_t mem_value) |
| 1796 | { |
1796 | { |
| - | 1797 | /* |
|
| - | 1798 | * We treat the cursor plane as always-on for the purposes of watermark |
|
| - | 1799 | * calculation. Until we have two-stage watermark programming merged, |
|
| - | 1800 | * this is necessary to avoid flickering. |
|
| - | 1801 | */ |
|
| - | 1802 | int cpp = 4; |
|
| 1797 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1803 | int width = pstate->visible ? pstate->base.crtc_w : 64; |
| Line 1798... | Line 1804... | ||
| 1798 | 1804 | ||
| 1799 | if (!cstate->base.active || !pstate->visible) |
1805 | if (!cstate->base.active) |
| Line 1800... | Line 1806... | ||
| 1800 | return 0; |
1806 | return 0; |
| 1801 | 1807 | ||
| 1802 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
- | |
| 1803 | cstate->base.adjusted_mode.crtc_htotal, |
- | |
| 1804 | drm_rect_width(&pstate->dst), |
1808 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
| 1805 | bpp, |
1809 | cstate->base.adjusted_mode.crtc_htotal, |
| Line 1806... | Line 1810... | ||
| 1806 | mem_value); |
1810 | width, cpp, mem_value); |
| 1807 | } |
1811 | } |
| 1808 | 1812 | ||
| Line 3883... | Line 3887... | ||
| 3883 | 3887 | ||
| 3884 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
3888 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
| 3885 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3889 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| Line -... | Line 3890... | ||
| - | 3890 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
|
| - | 3891 | ||
| 3886 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
3892 | memset(active, 0, sizeof(*active)); |
| Line 3887... | Line 3893... | ||
| 3887 | 3893 | ||
| 3888 | active->pipe_enabled = intel_crtc->active; |
3894 | active->pipe_enabled = intel_crtc->active; |
| Line 4523... | Line 4529... | ||
| 4523 | if (IS_VALLEYVIEW(dev)) |
4529 | if (IS_VALLEYVIEW(dev)) |
| 4524 | vlv_set_rps_idle(dev_priv); |
4530 | vlv_set_rps_idle(dev_priv); |
| 4525 | else |
4531 | else |
| 4526 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
4532 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
| 4527 | dev_priv->rps.last_adj = 0; |
4533 | dev_priv->rps.last_adj = 0; |
| 4528 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
4534 | I915_WRITE(GEN6_PMINTRMSK, |
| - | 4535 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
|
| 4529 | } |
4536 | } |
| 4530 | mutex_unlock(&dev_priv->rps.hw_lock); |
4537 | mutex_unlock(&dev_priv->rps.hw_lock); |
| Line 4531... | Line 4538... | ||
| 4531 | 4538 | ||
| 4532 | spin_lock(&dev_priv->rps.client_lock); |
4539 | spin_lock(&dev_priv->rps.client_lock); |
| Line 6618... | Line 6625... | ||
| 6618 | * WaTempDisableDOPClkGating:bdw |
6625 | * WaTempDisableDOPClkGating:bdw |
| 6619 | */ |
6626 | */ |
| 6620 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
6627 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 6621 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
6628 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 6622 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); |
6629 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); |
| - | 6630 | /* |
|
| - | 6631 | * Wait at least 100 clocks before re-enabling clock gating. See |
|
| - | 6632 | * the definition of L3SQCREG1 in BSpec. |
|
| - | 6633 | */ |
|
| - | 6634 | POSTING_READ(GEN8_L3SQCREG1); |
|
| - | 6635 | udelay(1); |
|
| 6623 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
6636 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| Line 6624... | Line 6637... | ||
| 6624 | 6637 | ||
| 6625 | /* |
6638 | /* |
| 6626 | * WaGttCachingOffByDefault:bdw |
6639 | * WaGttCachingOffByDefault:bdw |