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Rev 3480 | Rev 3482 | ||
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Line 280... | Line 280... | ||
280 | return false; |
280 | return false; |
Line 281... | Line 281... | ||
281 | 281 | ||
282 | return dev_priv->display.fbc_enabled(dev); |
282 | return dev_priv->display.fbc_enabled(dev); |
Line 283... | Line -... | ||
283 | } |
- | |
284 | 283 | } |
|
285 | #if 0 |
284 | |
286 | static void intel_fbc_work_fn(struct work_struct *__work) |
285 | static void intel_fbc_work_fn(struct work_struct *__work) |
287 | { |
286 | { |
288 | struct intel_fbc_work *work = |
287 | struct intel_fbc_work *work = |
Line 321... | Line 320... | ||
321 | 320 | ||
322 | /* Synchronisation is provided by struct_mutex and checking of |
321 | /* Synchronisation is provided by struct_mutex and checking of |
323 | * dev_priv->fbc_work, so we can perform the cancellation |
322 | * dev_priv->fbc_work, so we can perform the cancellation |
324 | * entirely asynchronously. |
323 | * entirely asynchronously. |
325 | */ |
324 | */ |
326 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
325 | // if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
327 | /* tasklet was killed before being run, clean up */ |
326 | /* tasklet was killed before being run, clean up */ |
Line 328... | Line 327... | ||
328 | kfree(dev_priv->fbc_work); |
327 | // kfree(dev_priv->fbc_work); |
329 | 328 | ||
330 | /* Mark the work as no longer wanted so that if it does |
329 | /* Mark the work as no longer wanted so that if it does |
331 | * wake-up (because the work was already running and waiting |
330 | * wake-up (because the work was already running and waiting |
332 | * for our mutex), it will discover that is no longer |
331 | * for our mutex), it will discover that is no longer |
333 | * necessary to run. |
332 | * necessary to run. |
334 | */ |
333 | */ |
335 | dev_priv->fbc_work = NULL; |
- | |
Line 336... | Line 334... | ||
336 | } |
334 | dev_priv->fbc_work = NULL; |
337 | #endif |
335 | } |
338 | 336 | ||
339 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
337 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
340 | { |
338 | { |
Line 341... | Line 339... | ||
341 | struct intel_fbc_work *work; |
339 | struct intel_fbc_work *work; |
342 | struct drm_device *dev = crtc->dev; |
340 | struct drm_device *dev = crtc->dev; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
341 | struct drm_i915_private *dev_priv = dev->dev_private; |
344 | 342 | ||
Line 345... | Line 343... | ||
345 | // if (!dev_priv->display.enable_fbc) |
343 | if (!dev_priv->display.enable_fbc) |
346 | return; |
344 | return; |
347 | #if 0 |
345 | |
Line 372... | Line 370... | ||
372 | * following the termination of the page-flipping sequence |
370 | * following the termination of the page-flipping sequence |
373 | * and indeed performing the enable as a co-routine and not |
371 | * and indeed performing the enable as a co-routine and not |
374 | * waiting synchronously upon the vblank. |
372 | * waiting synchronously upon the vblank. |
375 | */ |
373 | */ |
376 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
374 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
377 | #endif |
- | |
378 | - | ||
379 | } |
375 | } |
Line 380... | Line 376... | ||
380 | 376 | ||
381 | void intel_disable_fbc(struct drm_device *dev) |
377 | void intel_disable_fbc(struct drm_device *dev) |
382 | { |
378 | { |
Line 383... | Line 379... | ||
383 | struct drm_i915_private *dev_priv = dev->dev_private; |
379 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 384... | Line 380... | ||
384 | 380 | ||
385 | // intel_cancel_fbc_work(dev_priv); |
381 | intel_cancel_fbc_work(dev_priv); |
Line 386... | Line 382... | ||
386 | 382 | ||
387 | // if (!dev_priv->display.disable_fbc) |
383 | if (!dev_priv->display.disable_fbc) |
388 | // return; |
384 | return; |
Line 389... | Line 385... | ||
389 | 385 | ||
390 | // dev_priv->display.disable_fbc(dev); |
386 | dev_priv->display.disable_fbc(dev); |
Line 418... | Line 414... | ||
418 | struct drm_framebuffer *fb; |
414 | struct drm_framebuffer *fb; |
419 | struct intel_framebuffer *intel_fb; |
415 | struct intel_framebuffer *intel_fb; |
420 | struct drm_i915_gem_object *obj; |
416 | struct drm_i915_gem_object *obj; |
421 | int enable_fbc; |
417 | int enable_fbc; |
Line -... | Line 418... | ||
- | 418 | ||
- | 419 | ENTER(); |
|
422 | 420 | ||
423 | if (!i915_powersave) |
421 | if (!i915_powersave) |
Line 424... | Line 422... | ||
424 | return; |
422 | return; |
425 | 423 | ||
Line 548... | Line 546... | ||
548 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
546 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
549 | intel_disable_fbc(dev); |
547 | intel_disable_fbc(dev); |
550 | } |
548 | } |
Line 551... | Line 549... | ||
551 | 549 | ||
- | 550 | intel_enable_fbc(crtc, 500); |
|
- | 551 | LEAVE(); |
|
552 | intel_enable_fbc(crtc, 500); |
552 | |
Line 553... | Line 553... | ||
553 | return; |
553 | return; |
554 | 554 | ||
555 | out_disable: |
555 | out_disable: |
556 | /* Multiple disables should be harmless */ |
556 | /* Multiple disables should be harmless */ |
557 | if (intel_fbc_enabled(dev)) { |
557 | if (intel_fbc_enabled(dev)) { |
558 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
558 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
559 | intel_disable_fbc(dev); |
559 | intel_disable_fbc(dev); |
- | 560 | } |
|
560 | } |
561 | i915_gem_stolen_cleanup_compression(dev); |
Line 561... | Line 562... | ||
561 | i915_gem_stolen_cleanup_compression(dev); |
562 | LEAVE(); |
562 | } |
563 | } |
563 | 564 | ||
Line 2409... | Line 2410... | ||
2409 | 2410 | ||
2410 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2411 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2411 | I915_READ(0x112e0); |
2412 | I915_READ(0x112e0); |
2412 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2413 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2413 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
2414 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
Line 2414... | Line 2415... | ||
2414 | // getrawmonotonic(&dev_priv->ips.last_time2); |
2415 | getrawmonotonic(&dev_priv->ips.last_time2); |
2415 | 2416 | ||
Line 2416... | Line 2417... | ||
2416 | spin_unlock_irq(&mchdev_lock); |
2417 | spin_unlock_irq(&mchdev_lock); |
Line 2688... | Line 2689... | ||
2688 | } |
2689 | } |
Line 2689... | Line 2690... | ||
2689 | 2690 | ||
2690 | gen6_gt_force_wake_put(dev_priv); |
2691 | gen6_gt_force_wake_put(dev_priv); |
Line 2691... | Line -... | ||
2691 | } |
- | |
2692 | 2692 | } |
|
2693 | #if 0 |
2693 | |
2694 | static void gen6_update_ring_freq(struct drm_device *dev) |
2694 | static void gen6_update_ring_freq(struct drm_device *dev) |
2695 | { |
2695 | { |
2696 | struct drm_i915_private *dev_priv = dev->dev_private; |
2696 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2735... | Line 2735... | ||
2735 | sandybridge_pcode_write(dev_priv, |
2735 | sandybridge_pcode_write(dev_priv, |
2736 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
2736 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
2737 | ia_freq | gpu_freq); |
2737 | ia_freq | gpu_freq); |
2738 | } |
2738 | } |
2739 | } |
2739 | } |
2740 | #endif |
- | |
Line 2741... | Line 2740... | ||
2741 | 2740 | ||
2742 | void ironlake_teardown_rc6(struct drm_device *dev) |
2741 | void ironlake_teardown_rc6(struct drm_device *dev) |
2743 | { |
2742 | { |
Line 3464... | Line 3463... | ||
3464 | 3463 | ||
3465 | if (IS_IRONLAKE_M(dev)) { |
3464 | if (IS_IRONLAKE_M(dev)) { |
3466 | ironlake_disable_drps(dev); |
3465 | ironlake_disable_drps(dev); |
3467 | ironlake_disable_rc6(dev); |
3466 | ironlake_disable_rc6(dev); |
- | 3467 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
|
- | 3468 | // cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
|
3468 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3469 | mutex_lock(&dev_priv->rps.hw_lock); |
3469 | gen6_disable_rps(dev); |
3470 | gen6_disable_rps(dev); |
3470 | mutex_unlock(&dev_priv->rps.hw_lock); |
3471 | mutex_unlock(&dev_priv->rps.hw_lock); |
3471 | } |
3472 | } |
Line -... | Line 3473... | ||
- | 3473 | } |
|
- | 3474 | ||
- | 3475 | static void intel_gen6_powersave_work(struct work_struct *work) |
|
- | 3476 | { |
|
- | 3477 | struct drm_i915_private *dev_priv = |
|
- | 3478 | container_of(work, struct drm_i915_private, |
|
- | 3479 | rps.delayed_resume_work.work); |
|
- | 3480 | struct drm_device *dev = dev_priv->dev; |
|
- | 3481 | ||
- | 3482 | ENTER(); |
|
- | 3483 | ||
- | 3484 | mutex_lock(&dev_priv->rps.hw_lock); |
|
- | 3485 | gen6_enable_rps(dev); |
|
- | 3486 | gen6_update_ring_freq(dev); |
|
- | 3487 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 3488 | ||
- | 3489 | LEAVE(); |
|
3472 | } |
3490 | } |
3473 | 3491 | ||
3474 | void intel_enable_gt_powersave(struct drm_device *dev) |
3492 | void intel_enable_gt_powersave(struct drm_device *dev) |
Line 3475... | Line 3493... | ||
3475 | { |
3493 | { |
Line 3483... | Line 3501... | ||
3483 | /* |
3501 | /* |
3484 | * PCU communication is slow and this doesn't need to be |
3502 | * PCU communication is slow and this doesn't need to be |
3485 | * done at any specific time, so do this out of our fast path |
3503 | * done at any specific time, so do this out of our fast path |
3486 | * to make resume and init faster. |
3504 | * to make resume and init faster. |
3487 | */ |
3505 | */ |
3488 | // schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
3506 | schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
3489 | // round_jiffies_up_relative(HZ)); |
3507 | round_jiffies_up_relative(HZ)); |
3490 | } |
3508 | } |
3491 | } |
3509 | } |
Line 3492... | Line 3510... | ||
3492 | 3510 | ||
3493 | static void ibx_init_clock_gating(struct drm_device *dev) |
3511 | static void ibx_init_clock_gating(struct drm_device *dev) |
Line 4087... | Line 4105... | ||
4087 | uint32_t tmp; |
4105 | uint32_t tmp; |
Line 4088... | Line 4106... | ||
4088 | 4106 | ||
4089 | if (!IS_HASWELL(dev)) |
4107 | if (!IS_HASWELL(dev)) |
Line -... | Line 4108... | ||
- | 4108 | return; |
|
- | 4109 | ||
- | 4110 | if (!i915_disable_power_well && !enable) |
|
4090 | return; |
4111 | return; |
4091 | 4112 | ||
4092 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
4113 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
Line 4093... | Line 4114... | ||
4093 | is_enabled = tmp & HSW_PWR_WELL_STATE; |
4114 | is_enabled = tmp & HSW_PWR_WELL_STATE; |
Line 4466... | Line 4487... | ||
4466 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; |
4487 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; |
4467 | } else if (IS_GEN6(dev)) { |
4488 | } else if (IS_GEN6(dev)) { |
4468 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4489 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4469 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
4490 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
4470 | } |
4491 | } |
- | 4492 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
|
- | 4493 | intel_gen6_powersave_work); |
|
4471 | } |
4494 | } |
Line 4472... | Line 4495... | ||
4472 | 4495 | ||
4473 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4496 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4474 | { |
4497 | { |