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1 | /* |
1 | /* |
2 | * Copyright © 2012 Intel Corporation |
2 | * Copyright © 2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eugeni Dodonov |
24 | * Eugeni Dodonov |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #define iowrite32(v, addr) writel((v), (addr)) |
28 | #define iowrite32(v, addr) writel((v), (addr)) |
29 | #define ioread32(addr) readl(addr) |
29 | #define ioread32(addr) readl(addr) |
30 | 30 | ||
31 | //#include |
31 | //#include |
32 | #include "i915_drv.h" |
32 | #include "i915_drv.h" |
33 | #include "intel_drv.h" |
33 | #include "intel_drv.h" |
34 | #include |
34 | #include |
35 | //#include "../../../platform/x86/intel_ips.h" |
35 | //#include "../../../platform/x86/intel_ips.h" |
36 | #include |
36 | #include |
37 | 37 | ||
38 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
38 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
39 | 39 | ||
40 | #define assert_spin_locked(x) |
40 | #define assert_spin_locked(x) |
41 | 41 | ||
42 | void getrawmonotonic(struct timespec *ts); |
42 | void getrawmonotonic(struct timespec *ts); |
43 | void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec); |
43 | void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec); |
44 | 44 | ||
45 | static inline struct timespec timespec_sub(struct timespec lhs, |
45 | static inline struct timespec timespec_sub(struct timespec lhs, |
46 | struct timespec rhs) |
46 | struct timespec rhs) |
47 | { |
47 | { |
48 | struct timespec ts_delta; |
48 | struct timespec ts_delta; |
49 | set_normalized_timespec(&ts_delta, lhs.tv_sec - rhs.tv_sec, |
49 | set_normalized_timespec(&ts_delta, lhs.tv_sec - rhs.tv_sec, |
50 | lhs.tv_nsec - rhs.tv_nsec); |
50 | lhs.tv_nsec - rhs.tv_nsec); |
51 | return ts_delta; |
51 | return ts_delta; |
52 | } |
52 | } |
53 | 53 | ||
54 | 54 | ||
55 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
55 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
56 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
56 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
57 | * during in-memory transfers and, therefore, reduce the power packet. |
57 | * during in-memory transfers and, therefore, reduce the power packet. |
58 | * |
58 | * |
59 | * The benefits of FBC are mostly visible with solid backgrounds and |
59 | * The benefits of FBC are mostly visible with solid backgrounds and |
60 | * variation-less patterns. |
60 | * variation-less patterns. |
61 | * |
61 | * |
62 | * FBC-related functionality can be enabled by the means of the |
62 | * FBC-related functionality can be enabled by the means of the |
63 | * i915.i915_enable_fbc parameter |
63 | * i915.i915_enable_fbc parameter |
64 | */ |
64 | */ |
65 | 65 | ||
66 | static bool intel_crtc_active(struct drm_crtc *crtc) |
66 | static bool intel_crtc_active(struct drm_crtc *crtc) |
67 | { |
67 | { |
68 | /* Be paranoid as we can arrive here with only partial |
68 | /* Be paranoid as we can arrive here with only partial |
69 | * state retrieved from the hardware during setup. |
69 | * state retrieved from the hardware during setup. |
70 | */ |
70 | */ |
71 | return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; |
71 | return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; |
72 | } |
72 | } |
73 | 73 | ||
74 | static void i8xx_disable_fbc(struct drm_device *dev) |
74 | static void i8xx_disable_fbc(struct drm_device *dev) |
75 | { |
75 | { |
76 | struct drm_i915_private *dev_priv = dev->dev_private; |
76 | struct drm_i915_private *dev_priv = dev->dev_private; |
77 | u32 fbc_ctl; |
77 | u32 fbc_ctl; |
78 | 78 | ||
79 | /* Disable compression */ |
79 | /* Disable compression */ |
80 | fbc_ctl = I915_READ(FBC_CONTROL); |
80 | fbc_ctl = I915_READ(FBC_CONTROL); |
81 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
81 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
82 | return; |
82 | return; |
83 | 83 | ||
84 | fbc_ctl &= ~FBC_CTL_EN; |
84 | fbc_ctl &= ~FBC_CTL_EN; |
85 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
85 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
86 | 86 | ||
87 | /* Wait for compressing bit to clear */ |
87 | /* Wait for compressing bit to clear */ |
88 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
88 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
89 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
89 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
90 | return; |
90 | return; |
91 | } |
91 | } |
92 | 92 | ||
93 | DRM_DEBUG_KMS("disabled FBC\n"); |
93 | DRM_DEBUG_KMS("disabled FBC\n"); |
94 | } |
94 | } |
95 | 95 | ||
96 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
96 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
97 | { |
97 | { |
98 | struct drm_device *dev = crtc->dev; |
98 | struct drm_device *dev = crtc->dev; |
99 | struct drm_i915_private *dev_priv = dev->dev_private; |
99 | struct drm_i915_private *dev_priv = dev->dev_private; |
100 | struct drm_framebuffer *fb = crtc->fb; |
100 | struct drm_framebuffer *fb = crtc->fb; |
101 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
101 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
102 | struct drm_i915_gem_object *obj = intel_fb->obj; |
102 | struct drm_i915_gem_object *obj = intel_fb->obj; |
103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
104 | int cfb_pitch; |
104 | int cfb_pitch; |
105 | int plane, i; |
105 | int plane, i; |
106 | u32 fbc_ctl, fbc_ctl2; |
106 | u32 fbc_ctl, fbc_ctl2; |
107 | 107 | ||
108 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
108 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
109 | if (fb->pitches[0] < cfb_pitch) |
109 | if (fb->pitches[0] < cfb_pitch) |
110 | cfb_pitch = fb->pitches[0]; |
110 | cfb_pitch = fb->pitches[0]; |
111 | 111 | ||
112 | /* FBC_CTL wants 64B units */ |
112 | /* FBC_CTL wants 64B units */ |
113 | cfb_pitch = (cfb_pitch / 64) - 1; |
113 | cfb_pitch = (cfb_pitch / 64) - 1; |
114 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
114 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
115 | 115 | ||
116 | /* Clear old tags */ |
116 | /* Clear old tags */ |
117 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
117 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
118 | I915_WRITE(FBC_TAG + (i * 4), 0); |
118 | I915_WRITE(FBC_TAG + (i * 4), 0); |
119 | 119 | ||
120 | /* Set it up... */ |
120 | /* Set it up... */ |
121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
122 | fbc_ctl2 |= plane; |
122 | fbc_ctl2 |= plane; |
123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
125 | 125 | ||
126 | /* enable it... */ |
126 | /* enable it... */ |
127 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
127 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
128 | if (IS_I945GM(dev)) |
128 | if (IS_I945GM(dev)) |
129 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
129 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
130 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
130 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
131 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
131 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
132 | fbc_ctl |= obj->fence_reg; |
132 | fbc_ctl |= obj->fence_reg; |
133 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
133 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
134 | 134 | ||
135 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
135 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
136 | cfb_pitch, crtc->y, intel_crtc->plane); |
136 | cfb_pitch, crtc->y, intel_crtc->plane); |
137 | } |
137 | } |
138 | 138 | ||
139 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
139 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
140 | { |
140 | { |
141 | struct drm_i915_private *dev_priv = dev->dev_private; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; |
142 | 142 | ||
143 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
143 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
144 | } |
144 | } |
145 | 145 | ||
146 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
146 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
147 | { |
147 | { |
148 | struct drm_device *dev = crtc->dev; |
148 | struct drm_device *dev = crtc->dev; |
149 | struct drm_i915_private *dev_priv = dev->dev_private; |
149 | struct drm_i915_private *dev_priv = dev->dev_private; |
150 | struct drm_framebuffer *fb = crtc->fb; |
150 | struct drm_framebuffer *fb = crtc->fb; |
151 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
151 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
152 | struct drm_i915_gem_object *obj = intel_fb->obj; |
152 | struct drm_i915_gem_object *obj = intel_fb->obj; |
153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
154 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
154 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
155 | unsigned long stall_watermark = 200; |
155 | unsigned long stall_watermark = 200; |
156 | u32 dpfc_ctl; |
156 | u32 dpfc_ctl; |
157 | 157 | ||
158 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
158 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
159 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
159 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
160 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
160 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
161 | 161 | ||
162 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
162 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
163 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
163 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
164 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
164 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
166 | 166 | ||
167 | /* enable it... */ |
167 | /* enable it... */ |
168 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
168 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
169 | 169 | ||
170 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
170 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
171 | } |
171 | } |
172 | 172 | ||
173 | static void g4x_disable_fbc(struct drm_device *dev) |
173 | static void g4x_disable_fbc(struct drm_device *dev) |
174 | { |
174 | { |
175 | struct drm_i915_private *dev_priv = dev->dev_private; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; |
176 | u32 dpfc_ctl; |
176 | u32 dpfc_ctl; |
177 | 177 | ||
178 | /* Disable compression */ |
178 | /* Disable compression */ |
179 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
179 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
180 | if (dpfc_ctl & DPFC_CTL_EN) { |
180 | if (dpfc_ctl & DPFC_CTL_EN) { |
181 | dpfc_ctl &= ~DPFC_CTL_EN; |
181 | dpfc_ctl &= ~DPFC_CTL_EN; |
182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
183 | 183 | ||
184 | DRM_DEBUG_KMS("disabled FBC\n"); |
184 | DRM_DEBUG_KMS("disabled FBC\n"); |
185 | } |
185 | } |
186 | } |
186 | } |
187 | 187 | ||
188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
189 | { |
189 | { |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
191 | 191 | ||
192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
193 | } |
193 | } |
194 | 194 | ||
195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
196 | { |
196 | { |
197 | struct drm_i915_private *dev_priv = dev->dev_private; |
197 | struct drm_i915_private *dev_priv = dev->dev_private; |
198 | u32 blt_ecoskpd; |
198 | u32 blt_ecoskpd; |
199 | 199 | ||
200 | /* Make sure blitter notifies FBC of writes */ |
200 | /* Make sure blitter notifies FBC of writes */ |
201 | gen6_gt_force_wake_get(dev_priv); |
201 | gen6_gt_force_wake_get(dev_priv); |
202 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
202 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
203 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
203 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
204 | GEN6_BLITTER_LOCK_SHIFT; |
204 | GEN6_BLITTER_LOCK_SHIFT; |
205 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
205 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
206 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
206 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
207 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
207 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
208 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
208 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
209 | GEN6_BLITTER_LOCK_SHIFT); |
209 | GEN6_BLITTER_LOCK_SHIFT); |
210 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
210 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
211 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
211 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
212 | gen6_gt_force_wake_put(dev_priv); |
212 | gen6_gt_force_wake_put(dev_priv); |
213 | } |
213 | } |
214 | 214 | ||
215 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
215 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
216 | { |
216 | { |
217 | struct drm_device *dev = crtc->dev; |
217 | struct drm_device *dev = crtc->dev; |
218 | struct drm_i915_private *dev_priv = dev->dev_private; |
218 | struct drm_i915_private *dev_priv = dev->dev_private; |
219 | struct drm_framebuffer *fb = crtc->fb; |
219 | struct drm_framebuffer *fb = crtc->fb; |
220 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
220 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
221 | struct drm_i915_gem_object *obj = intel_fb->obj; |
221 | struct drm_i915_gem_object *obj = intel_fb->obj; |
222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
223 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
223 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
224 | unsigned long stall_watermark = 200; |
224 | unsigned long stall_watermark = 200; |
225 | u32 dpfc_ctl; |
225 | u32 dpfc_ctl; |
226 | 226 | ||
227 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
227 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
228 | dpfc_ctl &= DPFC_RESERVED; |
228 | dpfc_ctl &= DPFC_RESERVED; |
229 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
229 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
230 | /* Set persistent mode for front-buffer rendering, ala X. */ |
230 | /* Set persistent mode for front-buffer rendering, ala X. */ |
231 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
231 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
232 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
232 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
233 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
233 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
234 | 234 | ||
235 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
235 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
236 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
236 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
237 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
237 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
238 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
238 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
239 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
239 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
240 | /* enable it... */ |
240 | /* enable it... */ |
241 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
241 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
242 | 242 | ||
243 | if (IS_GEN6(dev)) { |
243 | if (IS_GEN6(dev)) { |
244 | I915_WRITE(SNB_DPFC_CTL_SA, |
244 | I915_WRITE(SNB_DPFC_CTL_SA, |
245 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
245 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
246 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
246 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
247 | sandybridge_blit_fbc_update(dev); |
247 | sandybridge_blit_fbc_update(dev); |
248 | } |
248 | } |
249 | 249 | ||
250 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
250 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
251 | } |
251 | } |
252 | 252 | ||
253 | static void ironlake_disable_fbc(struct drm_device *dev) |
253 | static void ironlake_disable_fbc(struct drm_device *dev) |
254 | { |
254 | { |
255 | struct drm_i915_private *dev_priv = dev->dev_private; |
255 | struct drm_i915_private *dev_priv = dev->dev_private; |
256 | u32 dpfc_ctl; |
256 | u32 dpfc_ctl; |
257 | 257 | ||
258 | /* Disable compression */ |
258 | /* Disable compression */ |
259 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
259 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
260 | if (dpfc_ctl & DPFC_CTL_EN) { |
260 | if (dpfc_ctl & DPFC_CTL_EN) { |
261 | dpfc_ctl &= ~DPFC_CTL_EN; |
261 | dpfc_ctl &= ~DPFC_CTL_EN; |
262 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
262 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
263 | 263 | ||
264 | DRM_DEBUG_KMS("disabled FBC\n"); |
264 | DRM_DEBUG_KMS("disabled FBC\n"); |
265 | } |
265 | } |
266 | } |
266 | } |
267 | 267 | ||
268 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
268 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
269 | { |
269 | { |
270 | struct drm_i915_private *dev_priv = dev->dev_private; |
270 | struct drm_i915_private *dev_priv = dev->dev_private; |
271 | 271 | ||
272 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
272 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
273 | } |
273 | } |
274 | 274 | ||
275 | bool intel_fbc_enabled(struct drm_device *dev) |
275 | bool intel_fbc_enabled(struct drm_device *dev) |
276 | { |
276 | { |
277 | struct drm_i915_private *dev_priv = dev->dev_private; |
277 | struct drm_i915_private *dev_priv = dev->dev_private; |
278 | 278 | ||
279 | if (!dev_priv->display.fbc_enabled) |
279 | if (!dev_priv->display.fbc_enabled) |
280 | return false; |
280 | return false; |
281 | 281 | ||
282 | return dev_priv->display.fbc_enabled(dev); |
282 | return dev_priv->display.fbc_enabled(dev); |
283 | } |
283 | } |
284 | 284 | ||
285 | #if 0 |
285 | #if 0 |
286 | static void intel_fbc_work_fn(struct work_struct *__work) |
286 | static void intel_fbc_work_fn(struct work_struct *__work) |
287 | { |
287 | { |
288 | struct intel_fbc_work *work = |
288 | struct intel_fbc_work *work = |
289 | container_of(to_delayed_work(__work), |
289 | container_of(to_delayed_work(__work), |
290 | struct intel_fbc_work, work); |
290 | struct intel_fbc_work, work); |
291 | struct drm_device *dev = work->crtc->dev; |
291 | struct drm_device *dev = work->crtc->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; |
293 | 293 | ||
294 | mutex_lock(&dev->struct_mutex); |
294 | mutex_lock(&dev->struct_mutex); |
295 | if (work == dev_priv->fbc_work) { |
295 | if (work == dev_priv->fbc_work) { |
296 | /* Double check that we haven't switched fb without cancelling |
296 | /* Double check that we haven't switched fb without cancelling |
297 | * the prior work. |
297 | * the prior work. |
298 | */ |
298 | */ |
299 | if (work->crtc->fb == work->fb) { |
299 | if (work->crtc->fb == work->fb) { |
300 | dev_priv->display.enable_fbc(work->crtc, |
300 | dev_priv->display.enable_fbc(work->crtc, |
301 | work->interval); |
301 | work->interval); |
302 | 302 | ||
303 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
303 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
304 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
304 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
305 | dev_priv->cfb_y = work->crtc->y; |
305 | dev_priv->cfb_y = work->crtc->y; |
306 | } |
306 | } |
307 | 307 | ||
308 | dev_priv->fbc_work = NULL; |
308 | dev_priv->fbc_work = NULL; |
309 | } |
309 | } |
310 | mutex_unlock(&dev->struct_mutex); |
310 | mutex_unlock(&dev->struct_mutex); |
311 | 311 | ||
312 | kfree(work); |
312 | kfree(work); |
313 | } |
313 | } |
314 | 314 | ||
315 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
315 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
316 | { |
316 | { |
317 | if (dev_priv->fbc_work == NULL) |
317 | if (dev_priv->fbc_work == NULL) |
318 | return; |
318 | return; |
319 | 319 | ||
320 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
320 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
321 | 321 | ||
322 | /* Synchronisation is provided by struct_mutex and checking of |
322 | /* Synchronisation is provided by struct_mutex and checking of |
323 | * dev_priv->fbc_work, so we can perform the cancellation |
323 | * dev_priv->fbc_work, so we can perform the cancellation |
324 | * entirely asynchronously. |
324 | * entirely asynchronously. |
325 | */ |
325 | */ |
326 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
326 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
327 | /* tasklet was killed before being run, clean up */ |
327 | /* tasklet was killed before being run, clean up */ |
328 | kfree(dev_priv->fbc_work); |
328 | kfree(dev_priv->fbc_work); |
329 | 329 | ||
330 | /* Mark the work as no longer wanted so that if it does |
330 | /* Mark the work as no longer wanted so that if it does |
331 | * wake-up (because the work was already running and waiting |
331 | * wake-up (because the work was already running and waiting |
332 | * for our mutex), it will discover that is no longer |
332 | * for our mutex), it will discover that is no longer |
333 | * necessary to run. |
333 | * necessary to run. |
334 | */ |
334 | */ |
335 | dev_priv->fbc_work = NULL; |
335 | dev_priv->fbc_work = NULL; |
336 | } |
336 | } |
337 | #endif |
337 | #endif |
338 | 338 | ||
339 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
339 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
340 | { |
340 | { |
341 | struct intel_fbc_work *work; |
341 | struct intel_fbc_work *work; |
342 | struct drm_device *dev = crtc->dev; |
342 | struct drm_device *dev = crtc->dev; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
344 | 344 | ||
345 | // if (!dev_priv->display.enable_fbc) |
345 | // if (!dev_priv->display.enable_fbc) |
346 | return; |
346 | return; |
347 | #if 0 |
347 | #if 0 |
348 | intel_cancel_fbc_work(dev_priv); |
348 | intel_cancel_fbc_work(dev_priv); |
349 | 349 | ||
350 | work = kzalloc(sizeof *work, GFP_KERNEL); |
350 | work = kzalloc(sizeof *work, GFP_KERNEL); |
351 | if (work == NULL) { |
351 | if (work == NULL) { |
352 | dev_priv->display.enable_fbc(crtc, interval); |
352 | dev_priv->display.enable_fbc(crtc, interval); |
353 | return; |
353 | return; |
354 | } |
354 | } |
355 | 355 | ||
356 | work->crtc = crtc; |
356 | work->crtc = crtc; |
357 | work->fb = crtc->fb; |
357 | work->fb = crtc->fb; |
358 | work->interval = interval; |
358 | work->interval = interval; |
359 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
359 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
360 | 360 | ||
361 | dev_priv->fbc_work = work; |
361 | dev_priv->fbc_work = work; |
362 | 362 | ||
363 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
363 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
364 | 364 | ||
365 | /* Delay the actual enabling to let pageflipping cease and the |
365 | /* Delay the actual enabling to let pageflipping cease and the |
366 | * display to settle before starting the compression. Note that |
366 | * display to settle before starting the compression. Note that |
367 | * this delay also serves a second purpose: it allows for a |
367 | * this delay also serves a second purpose: it allows for a |
368 | * vblank to pass after disabling the FBC before we attempt |
368 | * vblank to pass after disabling the FBC before we attempt |
369 | * to modify the control registers. |
369 | * to modify the control registers. |
370 | * |
370 | * |
371 | * A more complicated solution would involve tracking vblanks |
371 | * A more complicated solution would involve tracking vblanks |
372 | * following the termination of the page-flipping sequence |
372 | * following the termination of the page-flipping sequence |
373 | * and indeed performing the enable as a co-routine and not |
373 | * and indeed performing the enable as a co-routine and not |
374 | * waiting synchronously upon the vblank. |
374 | * waiting synchronously upon the vblank. |
375 | */ |
375 | */ |
376 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
376 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
377 | #endif |
377 | #endif |
378 | 378 | ||
379 | } |
379 | } |
380 | 380 | ||
381 | void intel_disable_fbc(struct drm_device *dev) |
381 | void intel_disable_fbc(struct drm_device *dev) |
382 | { |
382 | { |
383 | struct drm_i915_private *dev_priv = dev->dev_private; |
383 | struct drm_i915_private *dev_priv = dev->dev_private; |
384 | 384 | ||
385 | // intel_cancel_fbc_work(dev_priv); |
385 | // intel_cancel_fbc_work(dev_priv); |
386 | 386 | ||
387 | // if (!dev_priv->display.disable_fbc) |
387 | // if (!dev_priv->display.disable_fbc) |
388 | // return; |
388 | // return; |
389 | 389 | ||
390 | // dev_priv->display.disable_fbc(dev); |
390 | // dev_priv->display.disable_fbc(dev); |
391 | dev_priv->cfb_plane = -1; |
391 | dev_priv->cfb_plane = -1; |
392 | } |
392 | } |
393 | 393 | ||
394 | /** |
394 | /** |
395 | * intel_update_fbc - enable/disable FBC as needed |
395 | * intel_update_fbc - enable/disable FBC as needed |
396 | * @dev: the drm_device |
396 | * @dev: the drm_device |
397 | * |
397 | * |
398 | * Set up the framebuffer compression hardware at mode set time. We |
398 | * Set up the framebuffer compression hardware at mode set time. We |
399 | * enable it if possible: |
399 | * enable it if possible: |
400 | * - plane A only (on pre-965) |
400 | * - plane A only (on pre-965) |
401 | * - no pixel mulitply/line duplication |
401 | * - no pixel mulitply/line duplication |
402 | * - no alpha buffer discard |
402 | * - no alpha buffer discard |
403 | * - no dual wide |
403 | * - no dual wide |
404 | * - framebuffer <= 2048 in width, 1536 in height |
404 | * - framebuffer <= 2048 in width, 1536 in height |
405 | * |
405 | * |
406 | * We can't assume that any compression will take place (worst case), |
406 | * We can't assume that any compression will take place (worst case), |
407 | * so the compressed buffer has to be the same size as the uncompressed |
407 | * so the compressed buffer has to be the same size as the uncompressed |
408 | * one. It also must reside (along with the line length buffer) in |
408 | * one. It also must reside (along with the line length buffer) in |
409 | * stolen memory. |
409 | * stolen memory. |
410 | * |
410 | * |
411 | * We need to enable/disable FBC on a global basis. |
411 | * We need to enable/disable FBC on a global basis. |
412 | */ |
412 | */ |
413 | void intel_update_fbc(struct drm_device *dev) |
413 | void intel_update_fbc(struct drm_device *dev) |
414 | { |
414 | { |
415 | struct drm_i915_private *dev_priv = dev->dev_private; |
415 | struct drm_i915_private *dev_priv = dev->dev_private; |
416 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
416 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
417 | struct intel_crtc *intel_crtc; |
417 | struct intel_crtc *intel_crtc; |
418 | struct drm_framebuffer *fb; |
418 | struct drm_framebuffer *fb; |
419 | struct intel_framebuffer *intel_fb; |
419 | struct intel_framebuffer *intel_fb; |
420 | struct drm_i915_gem_object *obj; |
420 | struct drm_i915_gem_object *obj; |
421 | int enable_fbc; |
421 | int enable_fbc; |
422 | 422 | ||
423 | if (!i915_powersave) |
423 | if (!i915_powersave) |
424 | return; |
424 | return; |
425 | 425 | ||
426 | if (!I915_HAS_FBC(dev)) |
426 | if (!I915_HAS_FBC(dev)) |
427 | return; |
427 | return; |
428 | 428 | ||
429 | /* |
429 | /* |
430 | * If FBC is already on, we just have to verify that we can |
430 | * If FBC is already on, we just have to verify that we can |
431 | * keep it that way... |
431 | * keep it that way... |
432 | * Need to disable if: |
432 | * Need to disable if: |
433 | * - more than one pipe is active |
433 | * - more than one pipe is active |
434 | * - changing FBC params (stride, fence, mode) |
434 | * - changing FBC params (stride, fence, mode) |
435 | * - new fb is too large to fit in compressed buffer |
435 | * - new fb is too large to fit in compressed buffer |
436 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
436 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
437 | */ |
437 | */ |
438 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
438 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
439 | if (intel_crtc_active(tmp_crtc) && |
439 | if (intel_crtc_active(tmp_crtc) && |
440 | !to_intel_crtc(tmp_crtc)->primary_disabled) { |
440 | !to_intel_crtc(tmp_crtc)->primary_disabled) { |
441 | if (crtc) { |
441 | if (crtc) { |
442 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
442 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
443 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
443 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
444 | goto out_disable; |
444 | goto out_disable; |
445 | } |
445 | } |
446 | crtc = tmp_crtc; |
446 | crtc = tmp_crtc; |
447 | } |
447 | } |
448 | } |
448 | } |
449 | 449 | ||
450 | if (!crtc || crtc->fb == NULL) { |
450 | if (!crtc || crtc->fb == NULL) { |
451 | DRM_DEBUG_KMS("no output, disabling\n"); |
451 | DRM_DEBUG_KMS("no output, disabling\n"); |
452 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
452 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
453 | goto out_disable; |
453 | goto out_disable; |
454 | } |
454 | } |
455 | 455 | ||
456 | intel_crtc = to_intel_crtc(crtc); |
456 | intel_crtc = to_intel_crtc(crtc); |
457 | fb = crtc->fb; |
457 | fb = crtc->fb; |
458 | intel_fb = to_intel_framebuffer(fb); |
458 | intel_fb = to_intel_framebuffer(fb); |
459 | obj = intel_fb->obj; |
459 | obj = intel_fb->obj; |
460 | 460 | ||
461 | enable_fbc = i915_enable_fbc; |
461 | enable_fbc = i915_enable_fbc; |
462 | if (enable_fbc < 0) { |
462 | if (enable_fbc < 0) { |
463 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
463 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
464 | enable_fbc = 1; |
464 | enable_fbc = 1; |
465 | if (INTEL_INFO(dev)->gen <= 6) |
465 | if (INTEL_INFO(dev)->gen <= 6) |
466 | enable_fbc = 0; |
466 | enable_fbc = 0; |
467 | } |
467 | } |
468 | if (!enable_fbc) { |
468 | if (!enable_fbc) { |
469 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
469 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
470 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
470 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
471 | goto out_disable; |
471 | goto out_disable; |
472 | } |
472 | } |
473 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
- | |
474 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
- | |
475 | "compression\n"); |
- | |
476 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
- | |
477 | goto out_disable; |
- | |
478 | } |
- | |
479 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
473 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
480 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
474 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
481 | DRM_DEBUG_KMS("mode incompatible with compression, " |
475 | DRM_DEBUG_KMS("mode incompatible with compression, " |
482 | "disabling\n"); |
476 | "disabling\n"); |
483 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
477 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
484 | goto out_disable; |
478 | goto out_disable; |
485 | } |
479 | } |
486 | if ((crtc->mode.hdisplay > 2048) || |
480 | if ((crtc->mode.hdisplay > 2048) || |
487 | (crtc->mode.vdisplay > 1536)) { |
481 | (crtc->mode.vdisplay > 1536)) { |
488 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
482 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
489 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
483 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
490 | goto out_disable; |
484 | goto out_disable; |
491 | } |
485 | } |
492 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
486 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
493 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
487 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
494 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
488 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
495 | goto out_disable; |
489 | goto out_disable; |
496 | } |
490 | } |
497 | 491 | ||
498 | /* The use of a CPU fence is mandatory in order to detect writes |
492 | /* The use of a CPU fence is mandatory in order to detect writes |
499 | * by the CPU to the scanout and trigger updates to the FBC. |
493 | * by the CPU to the scanout and trigger updates to the FBC. |
500 | */ |
494 | */ |
501 | if (obj->tiling_mode != I915_TILING_X || |
495 | if (obj->tiling_mode != I915_TILING_X || |
502 | obj->fence_reg == I915_FENCE_REG_NONE) { |
496 | obj->fence_reg == I915_FENCE_REG_NONE) { |
503 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
497 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
504 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
498 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
505 | goto out_disable; |
499 | goto out_disable; |
506 | } |
500 | } |
507 | 501 | ||
508 | /* If the kernel debugger is active, always disable compression */ |
502 | /* If the kernel debugger is active, always disable compression */ |
509 | if (in_dbg_master()) |
503 | if (in_dbg_master()) |
510 | goto out_disable; |
504 | goto out_disable; |
- | 505 | ||
- | 506 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
|
- | 507 | DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size); |
|
- | 508 | DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); |
|
- | 509 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
|
- | 510 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
|
- | 511 | goto out_disable; |
|
- | 512 | } |
|
511 | 513 | ||
512 | /* If the scanout has not changed, don't modify the FBC settings. |
514 | /* If the scanout has not changed, don't modify the FBC settings. |
513 | * Note that we make the fundamental assumption that the fb->obj |
515 | * Note that we make the fundamental assumption that the fb->obj |
514 | * cannot be unpinned (and have its GTT offset and fence revoked) |
516 | * cannot be unpinned (and have its GTT offset and fence revoked) |
515 | * without first being decoupled from the scanout and FBC disabled. |
517 | * without first being decoupled from the scanout and FBC disabled. |
516 | */ |
518 | */ |
517 | if (dev_priv->cfb_plane == intel_crtc->plane && |
519 | if (dev_priv->cfb_plane == intel_crtc->plane && |
518 | dev_priv->cfb_fb == fb->base.id && |
520 | dev_priv->cfb_fb == fb->base.id && |
519 | dev_priv->cfb_y == crtc->y) |
521 | dev_priv->cfb_y == crtc->y) |
520 | return; |
522 | return; |
521 | 523 | ||
522 | if (intel_fbc_enabled(dev)) { |
524 | if (intel_fbc_enabled(dev)) { |
523 | /* We update FBC along two paths, after changing fb/crtc |
525 | /* We update FBC along two paths, after changing fb/crtc |
524 | * configuration (modeswitching) and after page-flipping |
526 | * configuration (modeswitching) and after page-flipping |
525 | * finishes. For the latter, we know that not only did |
527 | * finishes. For the latter, we know that not only did |
526 | * we disable the FBC at the start of the page-flip |
528 | * we disable the FBC at the start of the page-flip |
527 | * sequence, but also more than one vblank has passed. |
529 | * sequence, but also more than one vblank has passed. |
528 | * |
530 | * |
529 | * For the former case of modeswitching, it is possible |
531 | * For the former case of modeswitching, it is possible |
530 | * to switch between two FBC valid configurations |
532 | * to switch between two FBC valid configurations |
531 | * instantaneously so we do need to disable the FBC |
533 | * instantaneously so we do need to disable the FBC |
532 | * before we can modify its control registers. We also |
534 | * before we can modify its control registers. We also |
533 | * have to wait for the next vblank for that to take |
535 | * have to wait for the next vblank for that to take |
534 | * effect. However, since we delay enabling FBC we can |
536 | * effect. However, since we delay enabling FBC we can |
535 | * assume that a vblank has passed since disabling and |
537 | * assume that a vblank has passed since disabling and |
536 | * that we can safely alter the registers in the deferred |
538 | * that we can safely alter the registers in the deferred |
537 | * callback. |
539 | * callback. |
538 | * |
540 | * |
539 | * In the scenario that we go from a valid to invalid |
541 | * In the scenario that we go from a valid to invalid |
540 | * and then back to valid FBC configuration we have |
542 | * and then back to valid FBC configuration we have |
541 | * no strict enforcement that a vblank occurred since |
543 | * no strict enforcement that a vblank occurred since |
542 | * disabling the FBC. However, along all current pipe |
544 | * disabling the FBC. However, along all current pipe |
543 | * disabling paths we do need to wait for a vblank at |
545 | * disabling paths we do need to wait for a vblank at |
544 | * some point. And we wait before enabling FBC anyway. |
546 | * some point. And we wait before enabling FBC anyway. |
545 | */ |
547 | */ |
546 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
548 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
547 | intel_disable_fbc(dev); |
549 | intel_disable_fbc(dev); |
548 | } |
550 | } |
549 | 551 | ||
550 | intel_enable_fbc(crtc, 500); |
552 | intel_enable_fbc(crtc, 500); |
551 | return; |
553 | return; |
552 | 554 | ||
553 | out_disable: |
555 | out_disable: |
554 | /* Multiple disables should be harmless */ |
556 | /* Multiple disables should be harmless */ |
555 | if (intel_fbc_enabled(dev)) { |
557 | if (intel_fbc_enabled(dev)) { |
556 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
558 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
557 | intel_disable_fbc(dev); |
559 | intel_disable_fbc(dev); |
558 | } |
560 | } |
- | 561 | i915_gem_stolen_cleanup_compression(dev); |
|
559 | } |
562 | } |
560 | 563 | ||
561 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
564 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
562 | { |
565 | { |
563 | drm_i915_private_t *dev_priv = dev->dev_private; |
566 | drm_i915_private_t *dev_priv = dev->dev_private; |
564 | u32 tmp; |
567 | u32 tmp; |
565 | 568 | ||
566 | tmp = I915_READ(CLKCFG); |
569 | tmp = I915_READ(CLKCFG); |
567 | 570 | ||
568 | switch (tmp & CLKCFG_FSB_MASK) { |
571 | switch (tmp & CLKCFG_FSB_MASK) { |
569 | case CLKCFG_FSB_533: |
572 | case CLKCFG_FSB_533: |
570 | dev_priv->fsb_freq = 533; /* 133*4 */ |
573 | dev_priv->fsb_freq = 533; /* 133*4 */ |
571 | break; |
574 | break; |
572 | case CLKCFG_FSB_800: |
575 | case CLKCFG_FSB_800: |
573 | dev_priv->fsb_freq = 800; /* 200*4 */ |
576 | dev_priv->fsb_freq = 800; /* 200*4 */ |
574 | break; |
577 | break; |
575 | case CLKCFG_FSB_667: |
578 | case CLKCFG_FSB_667: |
576 | dev_priv->fsb_freq = 667; /* 167*4 */ |
579 | dev_priv->fsb_freq = 667; /* 167*4 */ |
577 | break; |
580 | break; |
578 | case CLKCFG_FSB_400: |
581 | case CLKCFG_FSB_400: |
579 | dev_priv->fsb_freq = 400; /* 100*4 */ |
582 | dev_priv->fsb_freq = 400; /* 100*4 */ |
580 | break; |
583 | break; |
581 | } |
584 | } |
582 | 585 | ||
583 | switch (tmp & CLKCFG_MEM_MASK) { |
586 | switch (tmp & CLKCFG_MEM_MASK) { |
584 | case CLKCFG_MEM_533: |
587 | case CLKCFG_MEM_533: |
585 | dev_priv->mem_freq = 533; |
588 | dev_priv->mem_freq = 533; |
586 | break; |
589 | break; |
587 | case CLKCFG_MEM_667: |
590 | case CLKCFG_MEM_667: |
588 | dev_priv->mem_freq = 667; |
591 | dev_priv->mem_freq = 667; |
589 | break; |
592 | break; |
590 | case CLKCFG_MEM_800: |
593 | case CLKCFG_MEM_800: |
591 | dev_priv->mem_freq = 800; |
594 | dev_priv->mem_freq = 800; |
592 | break; |
595 | break; |
593 | } |
596 | } |
594 | 597 | ||
595 | /* detect pineview DDR3 setting */ |
598 | /* detect pineview DDR3 setting */ |
596 | tmp = I915_READ(CSHRDDR3CTL); |
599 | tmp = I915_READ(CSHRDDR3CTL); |
597 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
600 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
598 | } |
601 | } |
599 | 602 | ||
600 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
603 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
601 | { |
604 | { |
602 | drm_i915_private_t *dev_priv = dev->dev_private; |
605 | drm_i915_private_t *dev_priv = dev->dev_private; |
603 | u16 ddrpll, csipll; |
606 | u16 ddrpll, csipll; |
604 | 607 | ||
605 | ddrpll = I915_READ16(DDRMPLL1); |
608 | ddrpll = I915_READ16(DDRMPLL1); |
606 | csipll = I915_READ16(CSIPLL0); |
609 | csipll = I915_READ16(CSIPLL0); |
607 | 610 | ||
608 | switch (ddrpll & 0xff) { |
611 | switch (ddrpll & 0xff) { |
609 | case 0xc: |
612 | case 0xc: |
610 | dev_priv->mem_freq = 800; |
613 | dev_priv->mem_freq = 800; |
611 | break; |
614 | break; |
612 | case 0x10: |
615 | case 0x10: |
613 | dev_priv->mem_freq = 1066; |
616 | dev_priv->mem_freq = 1066; |
614 | break; |
617 | break; |
615 | case 0x14: |
618 | case 0x14: |
616 | dev_priv->mem_freq = 1333; |
619 | dev_priv->mem_freq = 1333; |
617 | break; |
620 | break; |
618 | case 0x18: |
621 | case 0x18: |
619 | dev_priv->mem_freq = 1600; |
622 | dev_priv->mem_freq = 1600; |
620 | break; |
623 | break; |
621 | default: |
624 | default: |
622 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
625 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
623 | ddrpll & 0xff); |
626 | ddrpll & 0xff); |
624 | dev_priv->mem_freq = 0; |
627 | dev_priv->mem_freq = 0; |
625 | break; |
628 | break; |
626 | } |
629 | } |
627 | 630 | ||
628 | dev_priv->ips.r_t = dev_priv->mem_freq; |
631 | dev_priv->ips.r_t = dev_priv->mem_freq; |
629 | 632 | ||
630 | switch (csipll & 0x3ff) { |
633 | switch (csipll & 0x3ff) { |
631 | case 0x00c: |
634 | case 0x00c: |
632 | dev_priv->fsb_freq = 3200; |
635 | dev_priv->fsb_freq = 3200; |
633 | break; |
636 | break; |
634 | case 0x00e: |
637 | case 0x00e: |
635 | dev_priv->fsb_freq = 3733; |
638 | dev_priv->fsb_freq = 3733; |
636 | break; |
639 | break; |
637 | case 0x010: |
640 | case 0x010: |
638 | dev_priv->fsb_freq = 4266; |
641 | dev_priv->fsb_freq = 4266; |
639 | break; |
642 | break; |
640 | case 0x012: |
643 | case 0x012: |
641 | dev_priv->fsb_freq = 4800; |
644 | dev_priv->fsb_freq = 4800; |
642 | break; |
645 | break; |
643 | case 0x014: |
646 | case 0x014: |
644 | dev_priv->fsb_freq = 5333; |
647 | dev_priv->fsb_freq = 5333; |
645 | break; |
648 | break; |
646 | case 0x016: |
649 | case 0x016: |
647 | dev_priv->fsb_freq = 5866; |
650 | dev_priv->fsb_freq = 5866; |
648 | break; |
651 | break; |
649 | case 0x018: |
652 | case 0x018: |
650 | dev_priv->fsb_freq = 6400; |
653 | dev_priv->fsb_freq = 6400; |
651 | break; |
654 | break; |
652 | default: |
655 | default: |
653 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
656 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
654 | csipll & 0x3ff); |
657 | csipll & 0x3ff); |
655 | dev_priv->fsb_freq = 0; |
658 | dev_priv->fsb_freq = 0; |
656 | break; |
659 | break; |
657 | } |
660 | } |
658 | 661 | ||
659 | if (dev_priv->fsb_freq == 3200) { |
662 | if (dev_priv->fsb_freq == 3200) { |
660 | dev_priv->ips.c_m = 0; |
663 | dev_priv->ips.c_m = 0; |
661 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
664 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
662 | dev_priv->ips.c_m = 1; |
665 | dev_priv->ips.c_m = 1; |
663 | } else { |
666 | } else { |
664 | dev_priv->ips.c_m = 2; |
667 | dev_priv->ips.c_m = 2; |
665 | } |
668 | } |
666 | } |
669 | } |
667 | 670 | ||
668 | static const struct cxsr_latency cxsr_latency_table[] = { |
671 | static const struct cxsr_latency cxsr_latency_table[] = { |
669 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
672 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
670 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
673 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
671 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
674 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
672 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
675 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
673 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
676 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
674 | 677 | ||
675 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
678 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
676 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
679 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
677 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
680 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
678 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
681 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
679 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
682 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
680 | 683 | ||
681 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
684 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
682 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
685 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
683 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
686 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
684 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
687 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
685 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
688 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
686 | 689 | ||
687 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
690 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
688 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
691 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
689 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
692 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
690 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
693 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
691 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
694 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
692 | 695 | ||
693 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
696 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
694 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
697 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
695 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
698 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
696 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
699 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
697 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
700 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
698 | 701 | ||
699 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
702 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
700 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
703 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
701 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
704 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
702 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
705 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
703 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
706 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
704 | }; |
707 | }; |
705 | 708 | ||
706 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
709 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
707 | int is_ddr3, |
710 | int is_ddr3, |
708 | int fsb, |
711 | int fsb, |
709 | int mem) |
712 | int mem) |
710 | { |
713 | { |
711 | const struct cxsr_latency *latency; |
714 | const struct cxsr_latency *latency; |
712 | int i; |
715 | int i; |
713 | 716 | ||
714 | if (fsb == 0 || mem == 0) |
717 | if (fsb == 0 || mem == 0) |
715 | return NULL; |
718 | return NULL; |
716 | 719 | ||
717 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
720 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
718 | latency = &cxsr_latency_table[i]; |
721 | latency = &cxsr_latency_table[i]; |
719 | if (is_desktop == latency->is_desktop && |
722 | if (is_desktop == latency->is_desktop && |
720 | is_ddr3 == latency->is_ddr3 && |
723 | is_ddr3 == latency->is_ddr3 && |
721 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
724 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
722 | return latency; |
725 | return latency; |
723 | } |
726 | } |
724 | 727 | ||
725 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
728 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
726 | 729 | ||
727 | return NULL; |
730 | return NULL; |
728 | } |
731 | } |
729 | 732 | ||
730 | static void pineview_disable_cxsr(struct drm_device *dev) |
733 | static void pineview_disable_cxsr(struct drm_device *dev) |
731 | { |
734 | { |
732 | struct drm_i915_private *dev_priv = dev->dev_private; |
735 | struct drm_i915_private *dev_priv = dev->dev_private; |
733 | 736 | ||
734 | /* deactivate cxsr */ |
737 | /* deactivate cxsr */ |
735 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
738 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
736 | } |
739 | } |
737 | 740 | ||
738 | /* |
741 | /* |
739 | * Latency for FIFO fetches is dependent on several factors: |
742 | * Latency for FIFO fetches is dependent on several factors: |
740 | * - memory configuration (speed, channels) |
743 | * - memory configuration (speed, channels) |
741 | * - chipset |
744 | * - chipset |
742 | * - current MCH state |
745 | * - current MCH state |
743 | * It can be fairly high in some situations, so here we assume a fairly |
746 | * It can be fairly high in some situations, so here we assume a fairly |
744 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
747 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
745 | * set this value too high, the FIFO will fetch frequently to stay full) |
748 | * set this value too high, the FIFO will fetch frequently to stay full) |
746 | * and power consumption (set it too low to save power and we might see |
749 | * and power consumption (set it too low to save power and we might see |
747 | * FIFO underruns and display "flicker"). |
750 | * FIFO underruns and display "flicker"). |
748 | * |
751 | * |
749 | * A value of 5us seems to be a good balance; safe for very low end |
752 | * A value of 5us seems to be a good balance; safe for very low end |
750 | * platforms but not overly aggressive on lower latency configs. |
753 | * platforms but not overly aggressive on lower latency configs. |
751 | */ |
754 | */ |
752 | static const int latency_ns = 5000; |
755 | static const int latency_ns = 5000; |
753 | 756 | ||
754 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
757 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
755 | { |
758 | { |
756 | struct drm_i915_private *dev_priv = dev->dev_private; |
759 | struct drm_i915_private *dev_priv = dev->dev_private; |
757 | uint32_t dsparb = I915_READ(DSPARB); |
760 | uint32_t dsparb = I915_READ(DSPARB); |
758 | int size; |
761 | int size; |
759 | 762 | ||
760 | size = dsparb & 0x7f; |
763 | size = dsparb & 0x7f; |
761 | if (plane) |
764 | if (plane) |
762 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
765 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
763 | 766 | ||
764 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
767 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
765 | plane ? "B" : "A", size); |
768 | plane ? "B" : "A", size); |
766 | 769 | ||
767 | return size; |
770 | return size; |
768 | } |
771 | } |
769 | 772 | ||
770 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
773 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
771 | { |
774 | { |
772 | struct drm_i915_private *dev_priv = dev->dev_private; |
775 | struct drm_i915_private *dev_priv = dev->dev_private; |
773 | uint32_t dsparb = I915_READ(DSPARB); |
776 | uint32_t dsparb = I915_READ(DSPARB); |
774 | int size; |
777 | int size; |
775 | 778 | ||
776 | size = dsparb & 0x1ff; |
779 | size = dsparb & 0x1ff; |
777 | if (plane) |
780 | if (plane) |
778 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
781 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
779 | size >>= 1; /* Convert to cachelines */ |
782 | size >>= 1; /* Convert to cachelines */ |
780 | 783 | ||
781 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
784 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
782 | plane ? "B" : "A", size); |
785 | plane ? "B" : "A", size); |
783 | 786 | ||
784 | return size; |
787 | return size; |
785 | } |
788 | } |
786 | 789 | ||
787 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
790 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
788 | { |
791 | { |
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | struct drm_i915_private *dev_priv = dev->dev_private; |
790 | uint32_t dsparb = I915_READ(DSPARB); |
793 | uint32_t dsparb = I915_READ(DSPARB); |
791 | int size; |
794 | int size; |
792 | 795 | ||
793 | size = dsparb & 0x7f; |
796 | size = dsparb & 0x7f; |
794 | size >>= 2; /* Convert to cachelines */ |
797 | size >>= 2; /* Convert to cachelines */ |
795 | 798 | ||
796 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
799 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
797 | plane ? "B" : "A", |
800 | plane ? "B" : "A", |
798 | size); |
801 | size); |
799 | 802 | ||
800 | return size; |
803 | return size; |
801 | } |
804 | } |
802 | 805 | ||
803 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
806 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
804 | { |
807 | { |
805 | struct drm_i915_private *dev_priv = dev->dev_private; |
808 | struct drm_i915_private *dev_priv = dev->dev_private; |
806 | uint32_t dsparb = I915_READ(DSPARB); |
809 | uint32_t dsparb = I915_READ(DSPARB); |
807 | int size; |
810 | int size; |
808 | 811 | ||
809 | size = dsparb & 0x7f; |
812 | size = dsparb & 0x7f; |
810 | size >>= 1; /* Convert to cachelines */ |
813 | size >>= 1; /* Convert to cachelines */ |
811 | 814 | ||
812 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
815 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
813 | plane ? "B" : "A", size); |
816 | plane ? "B" : "A", size); |
814 | 817 | ||
815 | return size; |
818 | return size; |
816 | } |
819 | } |
817 | 820 | ||
818 | /* Pineview has different values for various configs */ |
821 | /* Pineview has different values for various configs */ |
819 | static const struct intel_watermark_params pineview_display_wm = { |
822 | static const struct intel_watermark_params pineview_display_wm = { |
820 | PINEVIEW_DISPLAY_FIFO, |
823 | PINEVIEW_DISPLAY_FIFO, |
821 | PINEVIEW_MAX_WM, |
824 | PINEVIEW_MAX_WM, |
822 | PINEVIEW_DFT_WM, |
825 | PINEVIEW_DFT_WM, |
823 | PINEVIEW_GUARD_WM, |
826 | PINEVIEW_GUARD_WM, |
824 | PINEVIEW_FIFO_LINE_SIZE |
827 | PINEVIEW_FIFO_LINE_SIZE |
825 | }; |
828 | }; |
826 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
829 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
827 | PINEVIEW_DISPLAY_FIFO, |
830 | PINEVIEW_DISPLAY_FIFO, |
828 | PINEVIEW_MAX_WM, |
831 | PINEVIEW_MAX_WM, |
829 | PINEVIEW_DFT_HPLLOFF_WM, |
832 | PINEVIEW_DFT_HPLLOFF_WM, |
830 | PINEVIEW_GUARD_WM, |
833 | PINEVIEW_GUARD_WM, |
831 | PINEVIEW_FIFO_LINE_SIZE |
834 | PINEVIEW_FIFO_LINE_SIZE |
832 | }; |
835 | }; |
833 | static const struct intel_watermark_params pineview_cursor_wm = { |
836 | static const struct intel_watermark_params pineview_cursor_wm = { |
834 | PINEVIEW_CURSOR_FIFO, |
837 | PINEVIEW_CURSOR_FIFO, |
835 | PINEVIEW_CURSOR_MAX_WM, |
838 | PINEVIEW_CURSOR_MAX_WM, |
836 | PINEVIEW_CURSOR_DFT_WM, |
839 | PINEVIEW_CURSOR_DFT_WM, |
837 | PINEVIEW_CURSOR_GUARD_WM, |
840 | PINEVIEW_CURSOR_GUARD_WM, |
838 | PINEVIEW_FIFO_LINE_SIZE, |
841 | PINEVIEW_FIFO_LINE_SIZE, |
839 | }; |
842 | }; |
840 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
843 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
841 | PINEVIEW_CURSOR_FIFO, |
844 | PINEVIEW_CURSOR_FIFO, |
842 | PINEVIEW_CURSOR_MAX_WM, |
845 | PINEVIEW_CURSOR_MAX_WM, |
843 | PINEVIEW_CURSOR_DFT_WM, |
846 | PINEVIEW_CURSOR_DFT_WM, |
844 | PINEVIEW_CURSOR_GUARD_WM, |
847 | PINEVIEW_CURSOR_GUARD_WM, |
845 | PINEVIEW_FIFO_LINE_SIZE |
848 | PINEVIEW_FIFO_LINE_SIZE |
846 | }; |
849 | }; |
847 | static const struct intel_watermark_params g4x_wm_info = { |
850 | static const struct intel_watermark_params g4x_wm_info = { |
848 | G4X_FIFO_SIZE, |
851 | G4X_FIFO_SIZE, |
849 | G4X_MAX_WM, |
852 | G4X_MAX_WM, |
850 | G4X_MAX_WM, |
853 | G4X_MAX_WM, |
851 | 2, |
854 | 2, |
852 | G4X_FIFO_LINE_SIZE, |
855 | G4X_FIFO_LINE_SIZE, |
853 | }; |
856 | }; |
854 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
857 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
855 | I965_CURSOR_FIFO, |
858 | I965_CURSOR_FIFO, |
856 | I965_CURSOR_MAX_WM, |
859 | I965_CURSOR_MAX_WM, |
857 | I965_CURSOR_DFT_WM, |
860 | I965_CURSOR_DFT_WM, |
858 | 2, |
861 | 2, |
859 | G4X_FIFO_LINE_SIZE, |
862 | G4X_FIFO_LINE_SIZE, |
860 | }; |
863 | }; |
861 | static const struct intel_watermark_params valleyview_wm_info = { |
864 | static const struct intel_watermark_params valleyview_wm_info = { |
862 | VALLEYVIEW_FIFO_SIZE, |
865 | VALLEYVIEW_FIFO_SIZE, |
863 | VALLEYVIEW_MAX_WM, |
866 | VALLEYVIEW_MAX_WM, |
864 | VALLEYVIEW_MAX_WM, |
867 | VALLEYVIEW_MAX_WM, |
865 | 2, |
868 | 2, |
866 | G4X_FIFO_LINE_SIZE, |
869 | G4X_FIFO_LINE_SIZE, |
867 | }; |
870 | }; |
868 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
871 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
869 | I965_CURSOR_FIFO, |
872 | I965_CURSOR_FIFO, |
870 | VALLEYVIEW_CURSOR_MAX_WM, |
873 | VALLEYVIEW_CURSOR_MAX_WM, |
871 | I965_CURSOR_DFT_WM, |
874 | I965_CURSOR_DFT_WM, |
872 | 2, |
875 | 2, |
873 | G4X_FIFO_LINE_SIZE, |
876 | G4X_FIFO_LINE_SIZE, |
874 | }; |
877 | }; |
875 | static const struct intel_watermark_params i965_cursor_wm_info = { |
878 | static const struct intel_watermark_params i965_cursor_wm_info = { |
876 | I965_CURSOR_FIFO, |
879 | I965_CURSOR_FIFO, |
877 | I965_CURSOR_MAX_WM, |
880 | I965_CURSOR_MAX_WM, |
878 | I965_CURSOR_DFT_WM, |
881 | I965_CURSOR_DFT_WM, |
879 | 2, |
882 | 2, |
880 | I915_FIFO_LINE_SIZE, |
883 | I915_FIFO_LINE_SIZE, |
881 | }; |
884 | }; |
882 | static const struct intel_watermark_params i945_wm_info = { |
885 | static const struct intel_watermark_params i945_wm_info = { |
883 | I945_FIFO_SIZE, |
886 | I945_FIFO_SIZE, |
884 | I915_MAX_WM, |
887 | I915_MAX_WM, |
885 | 1, |
888 | 1, |
886 | 2, |
889 | 2, |
887 | I915_FIFO_LINE_SIZE |
890 | I915_FIFO_LINE_SIZE |
888 | }; |
891 | }; |
889 | static const struct intel_watermark_params i915_wm_info = { |
892 | static const struct intel_watermark_params i915_wm_info = { |
890 | I915_FIFO_SIZE, |
893 | I915_FIFO_SIZE, |
891 | I915_MAX_WM, |
894 | I915_MAX_WM, |
892 | 1, |
895 | 1, |
893 | 2, |
896 | 2, |
894 | I915_FIFO_LINE_SIZE |
897 | I915_FIFO_LINE_SIZE |
895 | }; |
898 | }; |
896 | static const struct intel_watermark_params i855_wm_info = { |
899 | static const struct intel_watermark_params i855_wm_info = { |
897 | I855GM_FIFO_SIZE, |
900 | I855GM_FIFO_SIZE, |
898 | I915_MAX_WM, |
901 | I915_MAX_WM, |
899 | 1, |
902 | 1, |
900 | 2, |
903 | 2, |
901 | I830_FIFO_LINE_SIZE |
904 | I830_FIFO_LINE_SIZE |
902 | }; |
905 | }; |
903 | static const struct intel_watermark_params i830_wm_info = { |
906 | static const struct intel_watermark_params i830_wm_info = { |
904 | I830_FIFO_SIZE, |
907 | I830_FIFO_SIZE, |
905 | I915_MAX_WM, |
908 | I915_MAX_WM, |
906 | 1, |
909 | 1, |
907 | 2, |
910 | 2, |
908 | I830_FIFO_LINE_SIZE |
911 | I830_FIFO_LINE_SIZE |
909 | }; |
912 | }; |
910 | 913 | ||
911 | static const struct intel_watermark_params ironlake_display_wm_info = { |
914 | static const struct intel_watermark_params ironlake_display_wm_info = { |
912 | ILK_DISPLAY_FIFO, |
915 | ILK_DISPLAY_FIFO, |
913 | ILK_DISPLAY_MAXWM, |
916 | ILK_DISPLAY_MAXWM, |
914 | ILK_DISPLAY_DFTWM, |
917 | ILK_DISPLAY_DFTWM, |
915 | 2, |
918 | 2, |
916 | ILK_FIFO_LINE_SIZE |
919 | ILK_FIFO_LINE_SIZE |
917 | }; |
920 | }; |
918 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
921 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
919 | ILK_CURSOR_FIFO, |
922 | ILK_CURSOR_FIFO, |
920 | ILK_CURSOR_MAXWM, |
923 | ILK_CURSOR_MAXWM, |
921 | ILK_CURSOR_DFTWM, |
924 | ILK_CURSOR_DFTWM, |
922 | 2, |
925 | 2, |
923 | ILK_FIFO_LINE_SIZE |
926 | ILK_FIFO_LINE_SIZE |
924 | }; |
927 | }; |
925 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
928 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
926 | ILK_DISPLAY_SR_FIFO, |
929 | ILK_DISPLAY_SR_FIFO, |
927 | ILK_DISPLAY_MAX_SRWM, |
930 | ILK_DISPLAY_MAX_SRWM, |
928 | ILK_DISPLAY_DFT_SRWM, |
931 | ILK_DISPLAY_DFT_SRWM, |
929 | 2, |
932 | 2, |
930 | ILK_FIFO_LINE_SIZE |
933 | ILK_FIFO_LINE_SIZE |
931 | }; |
934 | }; |
932 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
935 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
933 | ILK_CURSOR_SR_FIFO, |
936 | ILK_CURSOR_SR_FIFO, |
934 | ILK_CURSOR_MAX_SRWM, |
937 | ILK_CURSOR_MAX_SRWM, |
935 | ILK_CURSOR_DFT_SRWM, |
938 | ILK_CURSOR_DFT_SRWM, |
936 | 2, |
939 | 2, |
937 | ILK_FIFO_LINE_SIZE |
940 | ILK_FIFO_LINE_SIZE |
938 | }; |
941 | }; |
939 | 942 | ||
940 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
943 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
941 | SNB_DISPLAY_FIFO, |
944 | SNB_DISPLAY_FIFO, |
942 | SNB_DISPLAY_MAXWM, |
945 | SNB_DISPLAY_MAXWM, |
943 | SNB_DISPLAY_DFTWM, |
946 | SNB_DISPLAY_DFTWM, |
944 | 2, |
947 | 2, |
945 | SNB_FIFO_LINE_SIZE |
948 | SNB_FIFO_LINE_SIZE |
946 | }; |
949 | }; |
947 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
950 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
948 | SNB_CURSOR_FIFO, |
951 | SNB_CURSOR_FIFO, |
949 | SNB_CURSOR_MAXWM, |
952 | SNB_CURSOR_MAXWM, |
950 | SNB_CURSOR_DFTWM, |
953 | SNB_CURSOR_DFTWM, |
951 | 2, |
954 | 2, |
952 | SNB_FIFO_LINE_SIZE |
955 | SNB_FIFO_LINE_SIZE |
953 | }; |
956 | }; |
954 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
957 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
955 | SNB_DISPLAY_SR_FIFO, |
958 | SNB_DISPLAY_SR_FIFO, |
956 | SNB_DISPLAY_MAX_SRWM, |
959 | SNB_DISPLAY_MAX_SRWM, |
957 | SNB_DISPLAY_DFT_SRWM, |
960 | SNB_DISPLAY_DFT_SRWM, |
958 | 2, |
961 | 2, |
959 | SNB_FIFO_LINE_SIZE |
962 | SNB_FIFO_LINE_SIZE |
960 | }; |
963 | }; |
961 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
964 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
962 | SNB_CURSOR_SR_FIFO, |
965 | SNB_CURSOR_SR_FIFO, |
963 | SNB_CURSOR_MAX_SRWM, |
966 | SNB_CURSOR_MAX_SRWM, |
964 | SNB_CURSOR_DFT_SRWM, |
967 | SNB_CURSOR_DFT_SRWM, |
965 | 2, |
968 | 2, |
966 | SNB_FIFO_LINE_SIZE |
969 | SNB_FIFO_LINE_SIZE |
967 | }; |
970 | }; |
968 | 971 | ||
969 | 972 | ||
970 | /** |
973 | /** |
971 | * intel_calculate_wm - calculate watermark level |
974 | * intel_calculate_wm - calculate watermark level |
972 | * @clock_in_khz: pixel clock |
975 | * @clock_in_khz: pixel clock |
973 | * @wm: chip FIFO params |
976 | * @wm: chip FIFO params |
974 | * @pixel_size: display pixel size |
977 | * @pixel_size: display pixel size |
975 | * @latency_ns: memory latency for the platform |
978 | * @latency_ns: memory latency for the platform |
976 | * |
979 | * |
977 | * Calculate the watermark level (the level at which the display plane will |
980 | * Calculate the watermark level (the level at which the display plane will |
978 | * start fetching from memory again). Each chip has a different display |
981 | * start fetching from memory again). Each chip has a different display |
979 | * FIFO size and allocation, so the caller needs to figure that out and pass |
982 | * FIFO size and allocation, so the caller needs to figure that out and pass |
980 | * in the correct intel_watermark_params structure. |
983 | * in the correct intel_watermark_params structure. |
981 | * |
984 | * |
982 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
985 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
983 | * on the pixel size. When it reaches the watermark level, it'll start |
986 | * on the pixel size. When it reaches the watermark level, it'll start |
984 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
987 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
985 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
988 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
986 | * will occur, and a display engine hang could result. |
989 | * will occur, and a display engine hang could result. |
987 | */ |
990 | */ |
988 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
991 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
989 | const struct intel_watermark_params *wm, |
992 | const struct intel_watermark_params *wm, |
990 | int fifo_size, |
993 | int fifo_size, |
991 | int pixel_size, |
994 | int pixel_size, |
992 | unsigned long latency_ns) |
995 | unsigned long latency_ns) |
993 | { |
996 | { |
994 | long entries_required, wm_size; |
997 | long entries_required, wm_size; |
995 | 998 | ||
996 | /* |
999 | /* |
997 | * Note: we need to make sure we don't overflow for various clock & |
1000 | * Note: we need to make sure we don't overflow for various clock & |
998 | * latency values. |
1001 | * latency values. |
999 | * clocks go from a few thousand to several hundred thousand. |
1002 | * clocks go from a few thousand to several hundred thousand. |
1000 | * latency is usually a few thousand |
1003 | * latency is usually a few thousand |
1001 | */ |
1004 | */ |
1002 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
1005 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
1003 | 1000; |
1006 | 1000; |
1004 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
1007 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
1005 | 1008 | ||
1006 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
1009 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
1007 | 1010 | ||
1008 | wm_size = fifo_size - (entries_required + wm->guard_size); |
1011 | wm_size = fifo_size - (entries_required + wm->guard_size); |
1009 | 1012 | ||
1010 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
1013 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
1011 | 1014 | ||
1012 | /* Don't promote wm_size to unsigned... */ |
1015 | /* Don't promote wm_size to unsigned... */ |
1013 | if (wm_size > (long)wm->max_wm) |
1016 | if (wm_size > (long)wm->max_wm) |
1014 | wm_size = wm->max_wm; |
1017 | wm_size = wm->max_wm; |
1015 | if (wm_size <= 0) |
1018 | if (wm_size <= 0) |
1016 | wm_size = wm->default_wm; |
1019 | wm_size = wm->default_wm; |
1017 | return wm_size; |
1020 | return wm_size; |
1018 | } |
1021 | } |
1019 | 1022 | ||
1020 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
1023 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
1021 | { |
1024 | { |
1022 | struct drm_crtc *crtc, *enabled = NULL; |
1025 | struct drm_crtc *crtc, *enabled = NULL; |
1023 | 1026 | ||
1024 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1027 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1025 | if (intel_crtc_active(crtc)) { |
1028 | if (intel_crtc_active(crtc)) { |
1026 | if (enabled) |
1029 | if (enabled) |
1027 | return NULL; |
1030 | return NULL; |
1028 | enabled = crtc; |
1031 | enabled = crtc; |
1029 | } |
1032 | } |
1030 | } |
1033 | } |
1031 | 1034 | ||
1032 | return enabled; |
1035 | return enabled; |
1033 | } |
1036 | } |
1034 | 1037 | ||
1035 | static void pineview_update_wm(struct drm_device *dev) |
1038 | static void pineview_update_wm(struct drm_device *dev) |
1036 | { |
1039 | { |
1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
1040 | struct drm_i915_private *dev_priv = dev->dev_private; |
1038 | struct drm_crtc *crtc; |
1041 | struct drm_crtc *crtc; |
1039 | const struct cxsr_latency *latency; |
1042 | const struct cxsr_latency *latency; |
1040 | u32 reg; |
1043 | u32 reg; |
1041 | unsigned long wm; |
1044 | unsigned long wm; |
1042 | 1045 | ||
1043 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
1046 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
1044 | dev_priv->fsb_freq, dev_priv->mem_freq); |
1047 | dev_priv->fsb_freq, dev_priv->mem_freq); |
1045 | if (!latency) { |
1048 | if (!latency) { |
1046 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
1049 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
1047 | pineview_disable_cxsr(dev); |
1050 | pineview_disable_cxsr(dev); |
1048 | return; |
1051 | return; |
1049 | } |
1052 | } |
1050 | 1053 | ||
1051 | crtc = single_enabled_crtc(dev); |
1054 | crtc = single_enabled_crtc(dev); |
1052 | if (crtc) { |
1055 | if (crtc) { |
1053 | int clock = crtc->mode.clock; |
1056 | int clock = crtc->mode.clock; |
1054 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1057 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1055 | 1058 | ||
1056 | /* Display SR */ |
1059 | /* Display SR */ |
1057 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
1060 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
1058 | pineview_display_wm.fifo_size, |
1061 | pineview_display_wm.fifo_size, |
1059 | pixel_size, latency->display_sr); |
1062 | pixel_size, latency->display_sr); |
1060 | reg = I915_READ(DSPFW1); |
1063 | reg = I915_READ(DSPFW1); |
1061 | reg &= ~DSPFW_SR_MASK; |
1064 | reg &= ~DSPFW_SR_MASK; |
1062 | reg |= wm << DSPFW_SR_SHIFT; |
1065 | reg |= wm << DSPFW_SR_SHIFT; |
1063 | I915_WRITE(DSPFW1, reg); |
1066 | I915_WRITE(DSPFW1, reg); |
1064 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
1067 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
1065 | 1068 | ||
1066 | /* cursor SR */ |
1069 | /* cursor SR */ |
1067 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
1070 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
1068 | pineview_display_wm.fifo_size, |
1071 | pineview_display_wm.fifo_size, |
1069 | pixel_size, latency->cursor_sr); |
1072 | pixel_size, latency->cursor_sr); |
1070 | reg = I915_READ(DSPFW3); |
1073 | reg = I915_READ(DSPFW3); |
1071 | reg &= ~DSPFW_CURSOR_SR_MASK; |
1074 | reg &= ~DSPFW_CURSOR_SR_MASK; |
1072 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
1075 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
1073 | I915_WRITE(DSPFW3, reg); |
1076 | I915_WRITE(DSPFW3, reg); |
1074 | 1077 | ||
1075 | /* Display HPLL off SR */ |
1078 | /* Display HPLL off SR */ |
1076 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
1079 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
1077 | pineview_display_hplloff_wm.fifo_size, |
1080 | pineview_display_hplloff_wm.fifo_size, |
1078 | pixel_size, latency->display_hpll_disable); |
1081 | pixel_size, latency->display_hpll_disable); |
1079 | reg = I915_READ(DSPFW3); |
1082 | reg = I915_READ(DSPFW3); |
1080 | reg &= ~DSPFW_HPLL_SR_MASK; |
1083 | reg &= ~DSPFW_HPLL_SR_MASK; |
1081 | reg |= wm & DSPFW_HPLL_SR_MASK; |
1084 | reg |= wm & DSPFW_HPLL_SR_MASK; |
1082 | I915_WRITE(DSPFW3, reg); |
1085 | I915_WRITE(DSPFW3, reg); |
1083 | 1086 | ||
1084 | /* cursor HPLL off SR */ |
1087 | /* cursor HPLL off SR */ |
1085 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
1088 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
1086 | pineview_display_hplloff_wm.fifo_size, |
1089 | pineview_display_hplloff_wm.fifo_size, |
1087 | pixel_size, latency->cursor_hpll_disable); |
1090 | pixel_size, latency->cursor_hpll_disable); |
1088 | reg = I915_READ(DSPFW3); |
1091 | reg = I915_READ(DSPFW3); |
1089 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
1092 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
1090 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
1093 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
1091 | I915_WRITE(DSPFW3, reg); |
1094 | I915_WRITE(DSPFW3, reg); |
1092 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
1095 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
1093 | 1096 | ||
1094 | /* activate cxsr */ |
1097 | /* activate cxsr */ |
1095 | I915_WRITE(DSPFW3, |
1098 | I915_WRITE(DSPFW3, |
1096 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
1099 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
1097 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
1100 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
1098 | } else { |
1101 | } else { |
1099 | pineview_disable_cxsr(dev); |
1102 | pineview_disable_cxsr(dev); |
1100 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
1103 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
1101 | } |
1104 | } |
1102 | } |
1105 | } |
1103 | 1106 | ||
1104 | static bool g4x_compute_wm0(struct drm_device *dev, |
1107 | static bool g4x_compute_wm0(struct drm_device *dev, |
1105 | int plane, |
1108 | int plane, |
1106 | const struct intel_watermark_params *display, |
1109 | const struct intel_watermark_params *display, |
1107 | int display_latency_ns, |
1110 | int display_latency_ns, |
1108 | const struct intel_watermark_params *cursor, |
1111 | const struct intel_watermark_params *cursor, |
1109 | int cursor_latency_ns, |
1112 | int cursor_latency_ns, |
1110 | int *plane_wm, |
1113 | int *plane_wm, |
1111 | int *cursor_wm) |
1114 | int *cursor_wm) |
1112 | { |
1115 | { |
1113 | struct drm_crtc *crtc; |
1116 | struct drm_crtc *crtc; |
1114 | int htotal, hdisplay, clock, pixel_size; |
1117 | int htotal, hdisplay, clock, pixel_size; |
1115 | int line_time_us, line_count; |
1118 | int line_time_us, line_count; |
1116 | int entries, tlb_miss; |
1119 | int entries, tlb_miss; |
1117 | 1120 | ||
1118 | crtc = intel_get_crtc_for_plane(dev, plane); |
1121 | crtc = intel_get_crtc_for_plane(dev, plane); |
1119 | if (!intel_crtc_active(crtc)) { |
1122 | if (!intel_crtc_active(crtc)) { |
1120 | *cursor_wm = cursor->guard_size; |
1123 | *cursor_wm = cursor->guard_size; |
1121 | *plane_wm = display->guard_size; |
1124 | *plane_wm = display->guard_size; |
1122 | return false; |
1125 | return false; |
1123 | } |
1126 | } |
1124 | 1127 | ||
1125 | htotal = crtc->mode.htotal; |
1128 | htotal = crtc->mode.htotal; |
1126 | hdisplay = crtc->mode.hdisplay; |
1129 | hdisplay = crtc->mode.hdisplay; |
1127 | clock = crtc->mode.clock; |
1130 | clock = crtc->mode.clock; |
1128 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1131 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1129 | 1132 | ||
1130 | /* Use the small buffer method to calculate plane watermark */ |
1133 | /* Use the small buffer method to calculate plane watermark */ |
1131 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
1134 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
1132 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
1135 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
1133 | if (tlb_miss > 0) |
1136 | if (tlb_miss > 0) |
1134 | entries += tlb_miss; |
1137 | entries += tlb_miss; |
1135 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
1138 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
1136 | *plane_wm = entries + display->guard_size; |
1139 | *plane_wm = entries + display->guard_size; |
1137 | if (*plane_wm > (int)display->max_wm) |
1140 | if (*plane_wm > (int)display->max_wm) |
1138 | *plane_wm = display->max_wm; |
1141 | *plane_wm = display->max_wm; |
1139 | 1142 | ||
1140 | /* Use the large buffer method to calculate cursor watermark */ |
1143 | /* Use the large buffer method to calculate cursor watermark */ |
1141 | line_time_us = ((htotal * 1000) / clock); |
1144 | line_time_us = ((htotal * 1000) / clock); |
1142 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
1145 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
1143 | entries = line_count * 64 * pixel_size; |
1146 | entries = line_count * 64 * pixel_size; |
1144 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1147 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1145 | if (tlb_miss > 0) |
1148 | if (tlb_miss > 0) |
1146 | entries += tlb_miss; |
1149 | entries += tlb_miss; |
1147 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1150 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1148 | *cursor_wm = entries + cursor->guard_size; |
1151 | *cursor_wm = entries + cursor->guard_size; |
1149 | if (*cursor_wm > (int)cursor->max_wm) |
1152 | if (*cursor_wm > (int)cursor->max_wm) |
1150 | *cursor_wm = (int)cursor->max_wm; |
1153 | *cursor_wm = (int)cursor->max_wm; |
1151 | 1154 | ||
1152 | return true; |
1155 | return true; |
1153 | } |
1156 | } |
1154 | 1157 | ||
1155 | /* |
1158 | /* |
1156 | * Check the wm result. |
1159 | * Check the wm result. |
1157 | * |
1160 | * |
1158 | * If any calculated watermark values is larger than the maximum value that |
1161 | * If any calculated watermark values is larger than the maximum value that |
1159 | * can be programmed into the associated watermark register, that watermark |
1162 | * can be programmed into the associated watermark register, that watermark |
1160 | * must be disabled. |
1163 | * must be disabled. |
1161 | */ |
1164 | */ |
1162 | static bool g4x_check_srwm(struct drm_device *dev, |
1165 | static bool g4x_check_srwm(struct drm_device *dev, |
1163 | int display_wm, int cursor_wm, |
1166 | int display_wm, int cursor_wm, |
1164 | const struct intel_watermark_params *display, |
1167 | const struct intel_watermark_params *display, |
1165 | const struct intel_watermark_params *cursor) |
1168 | const struct intel_watermark_params *cursor) |
1166 | { |
1169 | { |
1167 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
1170 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
1168 | display_wm, cursor_wm); |
1171 | display_wm, cursor_wm); |
1169 | 1172 | ||
1170 | if (display_wm > display->max_wm) { |
1173 | if (display_wm > display->max_wm) { |
1171 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
1174 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
1172 | display_wm, display->max_wm); |
1175 | display_wm, display->max_wm); |
1173 | return false; |
1176 | return false; |
1174 | } |
1177 | } |
1175 | 1178 | ||
1176 | if (cursor_wm > cursor->max_wm) { |
1179 | if (cursor_wm > cursor->max_wm) { |
1177 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
1180 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
1178 | cursor_wm, cursor->max_wm); |
1181 | cursor_wm, cursor->max_wm); |
1179 | return false; |
1182 | return false; |
1180 | } |
1183 | } |
1181 | 1184 | ||
1182 | if (!(display_wm || cursor_wm)) { |
1185 | if (!(display_wm || cursor_wm)) { |
1183 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
1186 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
1184 | return false; |
1187 | return false; |
1185 | } |
1188 | } |
1186 | 1189 | ||
1187 | return true; |
1190 | return true; |
1188 | } |
1191 | } |
1189 | 1192 | ||
1190 | static bool g4x_compute_srwm(struct drm_device *dev, |
1193 | static bool g4x_compute_srwm(struct drm_device *dev, |
1191 | int plane, |
1194 | int plane, |
1192 | int latency_ns, |
1195 | int latency_ns, |
1193 | const struct intel_watermark_params *display, |
1196 | const struct intel_watermark_params *display, |
1194 | const struct intel_watermark_params *cursor, |
1197 | const struct intel_watermark_params *cursor, |
1195 | int *display_wm, int *cursor_wm) |
1198 | int *display_wm, int *cursor_wm) |
1196 | { |
1199 | { |
1197 | struct drm_crtc *crtc; |
1200 | struct drm_crtc *crtc; |
1198 | int hdisplay, htotal, pixel_size, clock; |
1201 | int hdisplay, htotal, pixel_size, clock; |
1199 | unsigned long line_time_us; |
1202 | unsigned long line_time_us; |
1200 | int line_count, line_size; |
1203 | int line_count, line_size; |
1201 | int small, large; |
1204 | int small, large; |
1202 | int entries; |
1205 | int entries; |
1203 | 1206 | ||
1204 | if (!latency_ns) { |
1207 | if (!latency_ns) { |
1205 | *display_wm = *cursor_wm = 0; |
1208 | *display_wm = *cursor_wm = 0; |
1206 | return false; |
1209 | return false; |
1207 | } |
1210 | } |
1208 | 1211 | ||
1209 | crtc = intel_get_crtc_for_plane(dev, plane); |
1212 | crtc = intel_get_crtc_for_plane(dev, plane); |
1210 | hdisplay = crtc->mode.hdisplay; |
1213 | hdisplay = crtc->mode.hdisplay; |
1211 | htotal = crtc->mode.htotal; |
1214 | htotal = crtc->mode.htotal; |
1212 | clock = crtc->mode.clock; |
1215 | clock = crtc->mode.clock; |
1213 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1216 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1214 | 1217 | ||
1215 | line_time_us = (htotal * 1000) / clock; |
1218 | line_time_us = (htotal * 1000) / clock; |
1216 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1219 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1217 | line_size = hdisplay * pixel_size; |
1220 | line_size = hdisplay * pixel_size; |
1218 | 1221 | ||
1219 | /* Use the minimum of the small and large buffer method for primary */ |
1222 | /* Use the minimum of the small and large buffer method for primary */ |
1220 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1223 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1221 | large = line_count * line_size; |
1224 | large = line_count * line_size; |
1222 | 1225 | ||
1223 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1226 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1224 | *display_wm = entries + display->guard_size; |
1227 | *display_wm = entries + display->guard_size; |
1225 | 1228 | ||
1226 | /* calculate the self-refresh watermark for display cursor */ |
1229 | /* calculate the self-refresh watermark for display cursor */ |
1227 | entries = line_count * pixel_size * 64; |
1230 | entries = line_count * pixel_size * 64; |
1228 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1231 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1229 | *cursor_wm = entries + cursor->guard_size; |
1232 | *cursor_wm = entries + cursor->guard_size; |
1230 | 1233 | ||
1231 | return g4x_check_srwm(dev, |
1234 | return g4x_check_srwm(dev, |
1232 | *display_wm, *cursor_wm, |
1235 | *display_wm, *cursor_wm, |
1233 | display, cursor); |
1236 | display, cursor); |
1234 | } |
1237 | } |
1235 | 1238 | ||
1236 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
1239 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
1237 | int plane, |
1240 | int plane, |
1238 | int *plane_prec_mult, |
1241 | int *plane_prec_mult, |
1239 | int *plane_dl, |
1242 | int *plane_dl, |
1240 | int *cursor_prec_mult, |
1243 | int *cursor_prec_mult, |
1241 | int *cursor_dl) |
1244 | int *cursor_dl) |
1242 | { |
1245 | { |
1243 | struct drm_crtc *crtc; |
1246 | struct drm_crtc *crtc; |
1244 | int clock, pixel_size; |
1247 | int clock, pixel_size; |
1245 | int entries; |
1248 | int entries; |
1246 | 1249 | ||
1247 | crtc = intel_get_crtc_for_plane(dev, plane); |
1250 | crtc = intel_get_crtc_for_plane(dev, plane); |
1248 | if (!intel_crtc_active(crtc)) |
1251 | if (!intel_crtc_active(crtc)) |
1249 | return false; |
1252 | return false; |
1250 | 1253 | ||
1251 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
1254 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
1252 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
1255 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
1253 | 1256 | ||
1254 | entries = (clock / 1000) * pixel_size; |
1257 | entries = (clock / 1000) * pixel_size; |
1255 | *plane_prec_mult = (entries > 256) ? |
1258 | *plane_prec_mult = (entries > 256) ? |
1256 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1259 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1257 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
1260 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
1258 | pixel_size); |
1261 | pixel_size); |
1259 | 1262 | ||
1260 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
1263 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
1261 | *cursor_prec_mult = (entries > 256) ? |
1264 | *cursor_prec_mult = (entries > 256) ? |
1262 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1265 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1263 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
1266 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
1264 | 1267 | ||
1265 | return true; |
1268 | return true; |
1266 | } |
1269 | } |
1267 | 1270 | ||
1268 | /* |
1271 | /* |
1269 | * Update drain latency registers of memory arbiter |
1272 | * Update drain latency registers of memory arbiter |
1270 | * |
1273 | * |
1271 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
1274 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
1272 | * to be programmed. Each plane has a drain latency multiplier and a drain |
1275 | * to be programmed. Each plane has a drain latency multiplier and a drain |
1273 | * latency value. |
1276 | * latency value. |
1274 | */ |
1277 | */ |
1275 | 1278 | ||
1276 | static void vlv_update_drain_latency(struct drm_device *dev) |
1279 | static void vlv_update_drain_latency(struct drm_device *dev) |
1277 | { |
1280 | { |
1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
1281 | struct drm_i915_private *dev_priv = dev->dev_private; |
1279 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
1282 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
1280 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
1283 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
1281 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
1284 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
1282 | either 16 or 32 */ |
1285 | either 16 or 32 */ |
1283 | 1286 | ||
1284 | /* For plane A, Cursor A */ |
1287 | /* For plane A, Cursor A */ |
1285 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
1288 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
1286 | &cursor_prec_mult, &cursora_dl)) { |
1289 | &cursor_prec_mult, &cursora_dl)) { |
1287 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1290 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1288 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
1291 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
1289 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1292 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1290 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
1293 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
1291 | 1294 | ||
1292 | I915_WRITE(VLV_DDL1, cursora_prec | |
1295 | I915_WRITE(VLV_DDL1, cursora_prec | |
1293 | (cursora_dl << DDL_CURSORA_SHIFT) | |
1296 | (cursora_dl << DDL_CURSORA_SHIFT) | |
1294 | planea_prec | planea_dl); |
1297 | planea_prec | planea_dl); |
1295 | } |
1298 | } |
1296 | 1299 | ||
1297 | /* For plane B, Cursor B */ |
1300 | /* For plane B, Cursor B */ |
1298 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
1301 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
1299 | &cursor_prec_mult, &cursorb_dl)) { |
1302 | &cursor_prec_mult, &cursorb_dl)) { |
1300 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1303 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1301 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
1304 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
1302 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1305 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1303 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
1306 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
1304 | 1307 | ||
1305 | I915_WRITE(VLV_DDL2, cursorb_prec | |
1308 | I915_WRITE(VLV_DDL2, cursorb_prec | |
1306 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
1309 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
1307 | planeb_prec | planeb_dl); |
1310 | planeb_prec | planeb_dl); |
1308 | } |
1311 | } |
1309 | } |
1312 | } |
1310 | 1313 | ||
1311 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1314 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1312 | 1315 | ||
1313 | static void valleyview_update_wm(struct drm_device *dev) |
1316 | static void valleyview_update_wm(struct drm_device *dev) |
1314 | { |
1317 | { |
1315 | static const int sr_latency_ns = 12000; |
1318 | static const int sr_latency_ns = 12000; |
1316 | struct drm_i915_private *dev_priv = dev->dev_private; |
1319 | struct drm_i915_private *dev_priv = dev->dev_private; |
1317 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1320 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1318 | int plane_sr, cursor_sr; |
1321 | int plane_sr, cursor_sr; |
1319 | int ignore_plane_sr, ignore_cursor_sr; |
1322 | int ignore_plane_sr, ignore_cursor_sr; |
1320 | unsigned int enabled = 0; |
1323 | unsigned int enabled = 0; |
1321 | 1324 | ||
1322 | vlv_update_drain_latency(dev); |
1325 | vlv_update_drain_latency(dev); |
1323 | 1326 | ||
1324 | if (g4x_compute_wm0(dev, 0, |
1327 | if (g4x_compute_wm0(dev, 0, |
1325 | &valleyview_wm_info, latency_ns, |
1328 | &valleyview_wm_info, latency_ns, |
1326 | &valleyview_cursor_wm_info, latency_ns, |
1329 | &valleyview_cursor_wm_info, latency_ns, |
1327 | &planea_wm, &cursora_wm)) |
1330 | &planea_wm, &cursora_wm)) |
1328 | enabled |= 1; |
1331 | enabled |= 1; |
1329 | 1332 | ||
1330 | if (g4x_compute_wm0(dev, 1, |
1333 | if (g4x_compute_wm0(dev, 1, |
1331 | &valleyview_wm_info, latency_ns, |
1334 | &valleyview_wm_info, latency_ns, |
1332 | &valleyview_cursor_wm_info, latency_ns, |
1335 | &valleyview_cursor_wm_info, latency_ns, |
1333 | &planeb_wm, &cursorb_wm)) |
1336 | &planeb_wm, &cursorb_wm)) |
1334 | enabled |= 2; |
1337 | enabled |= 2; |
1335 | 1338 | ||
1336 | if (single_plane_enabled(enabled) && |
1339 | if (single_plane_enabled(enabled) && |
1337 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1340 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1338 | sr_latency_ns, |
1341 | sr_latency_ns, |
1339 | &valleyview_wm_info, |
1342 | &valleyview_wm_info, |
1340 | &valleyview_cursor_wm_info, |
1343 | &valleyview_cursor_wm_info, |
1341 | &plane_sr, &ignore_cursor_sr) && |
1344 | &plane_sr, &ignore_cursor_sr) && |
1342 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1345 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1343 | 2*sr_latency_ns, |
1346 | 2*sr_latency_ns, |
1344 | &valleyview_wm_info, |
1347 | &valleyview_wm_info, |
1345 | &valleyview_cursor_wm_info, |
1348 | &valleyview_cursor_wm_info, |
1346 | &ignore_plane_sr, &cursor_sr)) { |
1349 | &ignore_plane_sr, &cursor_sr)) { |
1347 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
1350 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
1348 | } else { |
1351 | } else { |
1349 | I915_WRITE(FW_BLC_SELF_VLV, |
1352 | I915_WRITE(FW_BLC_SELF_VLV, |
1350 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
1353 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
1351 | plane_sr = cursor_sr = 0; |
1354 | plane_sr = cursor_sr = 0; |
1352 | } |
1355 | } |
1353 | 1356 | ||
1354 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1357 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1355 | planea_wm, cursora_wm, |
1358 | planea_wm, cursora_wm, |
1356 | planeb_wm, cursorb_wm, |
1359 | planeb_wm, cursorb_wm, |
1357 | plane_sr, cursor_sr); |
1360 | plane_sr, cursor_sr); |
1358 | 1361 | ||
1359 | I915_WRITE(DSPFW1, |
1362 | I915_WRITE(DSPFW1, |
1360 | (plane_sr << DSPFW_SR_SHIFT) | |
1363 | (plane_sr << DSPFW_SR_SHIFT) | |
1361 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1364 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1362 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1365 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1363 | planea_wm); |
1366 | planea_wm); |
1364 | I915_WRITE(DSPFW2, |
1367 | I915_WRITE(DSPFW2, |
1365 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1368 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1366 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1369 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1367 | I915_WRITE(DSPFW3, |
1370 | I915_WRITE(DSPFW3, |
1368 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1371 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1369 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1372 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1370 | } |
1373 | } |
1371 | 1374 | ||
1372 | static void g4x_update_wm(struct drm_device *dev) |
1375 | static void g4x_update_wm(struct drm_device *dev) |
1373 | { |
1376 | { |
1374 | static const int sr_latency_ns = 12000; |
1377 | static const int sr_latency_ns = 12000; |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
1378 | struct drm_i915_private *dev_priv = dev->dev_private; |
1376 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1379 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1377 | int plane_sr, cursor_sr; |
1380 | int plane_sr, cursor_sr; |
1378 | unsigned int enabled = 0; |
1381 | unsigned int enabled = 0; |
1379 | 1382 | ||
1380 | if (g4x_compute_wm0(dev, 0, |
1383 | if (g4x_compute_wm0(dev, 0, |
1381 | &g4x_wm_info, latency_ns, |
1384 | &g4x_wm_info, latency_ns, |
1382 | &g4x_cursor_wm_info, latency_ns, |
1385 | &g4x_cursor_wm_info, latency_ns, |
1383 | &planea_wm, &cursora_wm)) |
1386 | &planea_wm, &cursora_wm)) |
1384 | enabled |= 1; |
1387 | enabled |= 1; |
1385 | 1388 | ||
1386 | if (g4x_compute_wm0(dev, 1, |
1389 | if (g4x_compute_wm0(dev, 1, |
1387 | &g4x_wm_info, latency_ns, |
1390 | &g4x_wm_info, latency_ns, |
1388 | &g4x_cursor_wm_info, latency_ns, |
1391 | &g4x_cursor_wm_info, latency_ns, |
1389 | &planeb_wm, &cursorb_wm)) |
1392 | &planeb_wm, &cursorb_wm)) |
1390 | enabled |= 2; |
1393 | enabled |= 2; |
1391 | 1394 | ||
1392 | if (single_plane_enabled(enabled) && |
1395 | if (single_plane_enabled(enabled) && |
1393 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1396 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1394 | sr_latency_ns, |
1397 | sr_latency_ns, |
1395 | &g4x_wm_info, |
1398 | &g4x_wm_info, |
1396 | &g4x_cursor_wm_info, |
1399 | &g4x_cursor_wm_info, |
1397 | &plane_sr, &cursor_sr)) { |
1400 | &plane_sr, &cursor_sr)) { |
1398 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1401 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1399 | } else { |
1402 | } else { |
1400 | I915_WRITE(FW_BLC_SELF, |
1403 | I915_WRITE(FW_BLC_SELF, |
1401 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
1404 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
1402 | plane_sr = cursor_sr = 0; |
1405 | plane_sr = cursor_sr = 0; |
1403 | } |
1406 | } |
1404 | 1407 | ||
1405 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1408 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1406 | planea_wm, cursora_wm, |
1409 | planea_wm, cursora_wm, |
1407 | planeb_wm, cursorb_wm, |
1410 | planeb_wm, cursorb_wm, |
1408 | plane_sr, cursor_sr); |
1411 | plane_sr, cursor_sr); |
1409 | 1412 | ||
1410 | I915_WRITE(DSPFW1, |
1413 | I915_WRITE(DSPFW1, |
1411 | (plane_sr << DSPFW_SR_SHIFT) | |
1414 | (plane_sr << DSPFW_SR_SHIFT) | |
1412 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1415 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1413 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1416 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1414 | planea_wm); |
1417 | planea_wm); |
1415 | I915_WRITE(DSPFW2, |
1418 | I915_WRITE(DSPFW2, |
1416 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1419 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1417 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1420 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1418 | /* HPLL off in SR has some issues on G4x... disable it */ |
1421 | /* HPLL off in SR has some issues on G4x... disable it */ |
1419 | I915_WRITE(DSPFW3, |
1422 | I915_WRITE(DSPFW3, |
1420 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
1423 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
1421 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1424 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1422 | } |
1425 | } |
1423 | 1426 | ||
1424 | static void i965_update_wm(struct drm_device *dev) |
1427 | static void i965_update_wm(struct drm_device *dev) |
1425 | { |
1428 | { |
1426 | struct drm_i915_private *dev_priv = dev->dev_private; |
1429 | struct drm_i915_private *dev_priv = dev->dev_private; |
1427 | struct drm_crtc *crtc; |
1430 | struct drm_crtc *crtc; |
1428 | int srwm = 1; |
1431 | int srwm = 1; |
1429 | int cursor_sr = 16; |
1432 | int cursor_sr = 16; |
1430 | 1433 | ||
1431 | /* Calc sr entries for one plane configs */ |
1434 | /* Calc sr entries for one plane configs */ |
1432 | crtc = single_enabled_crtc(dev); |
1435 | crtc = single_enabled_crtc(dev); |
1433 | if (crtc) { |
1436 | if (crtc) { |
1434 | /* self-refresh has much higher latency */ |
1437 | /* self-refresh has much higher latency */ |
1435 | static const int sr_latency_ns = 12000; |
1438 | static const int sr_latency_ns = 12000; |
1436 | int clock = crtc->mode.clock; |
1439 | int clock = crtc->mode.clock; |
1437 | int htotal = crtc->mode.htotal; |
1440 | int htotal = crtc->mode.htotal; |
1438 | int hdisplay = crtc->mode.hdisplay; |
1441 | int hdisplay = crtc->mode.hdisplay; |
1439 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1442 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1440 | unsigned long line_time_us; |
1443 | unsigned long line_time_us; |
1441 | int entries; |
1444 | int entries; |
1442 | 1445 | ||
1443 | line_time_us = ((htotal * 1000) / clock); |
1446 | line_time_us = ((htotal * 1000) / clock); |
1444 | 1447 | ||
1445 | /* Use ns/us then divide to preserve precision */ |
1448 | /* Use ns/us then divide to preserve precision */ |
1446 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1449 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1447 | pixel_size * hdisplay; |
1450 | pixel_size * hdisplay; |
1448 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1451 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1449 | srwm = I965_FIFO_SIZE - entries; |
1452 | srwm = I965_FIFO_SIZE - entries; |
1450 | if (srwm < 0) |
1453 | if (srwm < 0) |
1451 | srwm = 1; |
1454 | srwm = 1; |
1452 | srwm &= 0x1ff; |
1455 | srwm &= 0x1ff; |
1453 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1456 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1454 | entries, srwm); |
1457 | entries, srwm); |
1455 | 1458 | ||
1456 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1459 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1457 | pixel_size * 64; |
1460 | pixel_size * 64; |
1458 | entries = DIV_ROUND_UP(entries, |
1461 | entries = DIV_ROUND_UP(entries, |
1459 | i965_cursor_wm_info.cacheline_size); |
1462 | i965_cursor_wm_info.cacheline_size); |
1460 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1463 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1461 | (entries + i965_cursor_wm_info.guard_size); |
1464 | (entries + i965_cursor_wm_info.guard_size); |
1462 | 1465 | ||
1463 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1466 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1464 | cursor_sr = i965_cursor_wm_info.max_wm; |
1467 | cursor_sr = i965_cursor_wm_info.max_wm; |
1465 | 1468 | ||
1466 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1469 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1467 | "cursor %d\n", srwm, cursor_sr); |
1470 | "cursor %d\n", srwm, cursor_sr); |
1468 | 1471 | ||
1469 | if (IS_CRESTLINE(dev)) |
1472 | if (IS_CRESTLINE(dev)) |
1470 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1473 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1471 | } else { |
1474 | } else { |
1472 | /* Turn off self refresh if both pipes are enabled */ |
1475 | /* Turn off self refresh if both pipes are enabled */ |
1473 | if (IS_CRESTLINE(dev)) |
1476 | if (IS_CRESTLINE(dev)) |
1474 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
1477 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
1475 | & ~FW_BLC_SELF_EN); |
1478 | & ~FW_BLC_SELF_EN); |
1476 | } |
1479 | } |
1477 | 1480 | ||
1478 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1481 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1479 | srwm); |
1482 | srwm); |
1480 | 1483 | ||
1481 | /* 965 has limitations... */ |
1484 | /* 965 has limitations... */ |
1482 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
1485 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
1483 | (8 << 16) | (8 << 8) | (8 << 0)); |
1486 | (8 << 16) | (8 << 8) | (8 << 0)); |
1484 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
1487 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
1485 | /* update cursor SR watermark */ |
1488 | /* update cursor SR watermark */ |
1486 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1489 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1487 | } |
1490 | } |
1488 | 1491 | ||
1489 | static void i9xx_update_wm(struct drm_device *dev) |
1492 | static void i9xx_update_wm(struct drm_device *dev) |
1490 | { |
1493 | { |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; |
1492 | const struct intel_watermark_params *wm_info; |
1495 | const struct intel_watermark_params *wm_info; |
1493 | uint32_t fwater_lo; |
1496 | uint32_t fwater_lo; |
1494 | uint32_t fwater_hi; |
1497 | uint32_t fwater_hi; |
1495 | int cwm, srwm = 1; |
1498 | int cwm, srwm = 1; |
1496 | int fifo_size; |
1499 | int fifo_size; |
1497 | int planea_wm, planeb_wm; |
1500 | int planea_wm, planeb_wm; |
1498 | struct drm_crtc *crtc, *enabled = NULL; |
1501 | struct drm_crtc *crtc, *enabled = NULL; |
1499 | 1502 | ||
1500 | if (IS_I945GM(dev)) |
1503 | if (IS_I945GM(dev)) |
1501 | wm_info = &i945_wm_info; |
1504 | wm_info = &i945_wm_info; |
1502 | else if (!IS_GEN2(dev)) |
1505 | else if (!IS_GEN2(dev)) |
1503 | wm_info = &i915_wm_info; |
1506 | wm_info = &i915_wm_info; |
1504 | else |
1507 | else |
1505 | wm_info = &i855_wm_info; |
1508 | wm_info = &i855_wm_info; |
1506 | 1509 | ||
1507 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1510 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1508 | crtc = intel_get_crtc_for_plane(dev, 0); |
1511 | crtc = intel_get_crtc_for_plane(dev, 0); |
1509 | if (intel_crtc_active(crtc)) { |
1512 | if (intel_crtc_active(crtc)) { |
1510 | int cpp = crtc->fb->bits_per_pixel / 8; |
1513 | int cpp = crtc->fb->bits_per_pixel / 8; |
1511 | if (IS_GEN2(dev)) |
1514 | if (IS_GEN2(dev)) |
1512 | cpp = 4; |
1515 | cpp = 4; |
1513 | 1516 | ||
1514 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
1517 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
1515 | wm_info, fifo_size, cpp, |
1518 | wm_info, fifo_size, cpp, |
1516 | latency_ns); |
1519 | latency_ns); |
1517 | enabled = crtc; |
1520 | enabled = crtc; |
1518 | } else |
1521 | } else |
1519 | planea_wm = fifo_size - wm_info->guard_size; |
1522 | planea_wm = fifo_size - wm_info->guard_size; |
1520 | 1523 | ||
1521 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1524 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1522 | crtc = intel_get_crtc_for_plane(dev, 1); |
1525 | crtc = intel_get_crtc_for_plane(dev, 1); |
1523 | if (intel_crtc_active(crtc)) { |
1526 | if (intel_crtc_active(crtc)) { |
1524 | int cpp = crtc->fb->bits_per_pixel / 8; |
1527 | int cpp = crtc->fb->bits_per_pixel / 8; |
1525 | if (IS_GEN2(dev)) |
1528 | if (IS_GEN2(dev)) |
1526 | cpp = 4; |
1529 | cpp = 4; |
1527 | 1530 | ||
1528 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
1531 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
1529 | wm_info, fifo_size, cpp, |
1532 | wm_info, fifo_size, cpp, |
1530 | latency_ns); |
1533 | latency_ns); |
1531 | if (enabled == NULL) |
1534 | if (enabled == NULL) |
1532 | enabled = crtc; |
1535 | enabled = crtc; |
1533 | else |
1536 | else |
1534 | enabled = NULL; |
1537 | enabled = NULL; |
1535 | } else |
1538 | } else |
1536 | planeb_wm = fifo_size - wm_info->guard_size; |
1539 | planeb_wm = fifo_size - wm_info->guard_size; |
1537 | 1540 | ||
1538 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1541 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1539 | 1542 | ||
1540 | /* |
1543 | /* |
1541 | * Overlay gets an aggressive default since video jitter is bad. |
1544 | * Overlay gets an aggressive default since video jitter is bad. |
1542 | */ |
1545 | */ |
1543 | cwm = 2; |
1546 | cwm = 2; |
1544 | 1547 | ||
1545 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1548 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1546 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1549 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1547 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
1550 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
1548 | else if (IS_I915GM(dev)) |
1551 | else if (IS_I915GM(dev)) |
1549 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
1552 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
1550 | 1553 | ||
1551 | /* Calc sr entries for one plane configs */ |
1554 | /* Calc sr entries for one plane configs */ |
1552 | if (HAS_FW_BLC(dev) && enabled) { |
1555 | if (HAS_FW_BLC(dev) && enabled) { |
1553 | /* self-refresh has much higher latency */ |
1556 | /* self-refresh has much higher latency */ |
1554 | static const int sr_latency_ns = 6000; |
1557 | static const int sr_latency_ns = 6000; |
1555 | int clock = enabled->mode.clock; |
1558 | int clock = enabled->mode.clock; |
1556 | int htotal = enabled->mode.htotal; |
1559 | int htotal = enabled->mode.htotal; |
1557 | int hdisplay = enabled->mode.hdisplay; |
1560 | int hdisplay = enabled->mode.hdisplay; |
1558 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1561 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1559 | unsigned long line_time_us; |
1562 | unsigned long line_time_us; |
1560 | int entries; |
1563 | int entries; |
1561 | 1564 | ||
1562 | line_time_us = (htotal * 1000) / clock; |
1565 | line_time_us = (htotal * 1000) / clock; |
1563 | 1566 | ||
1564 | /* Use ns/us then divide to preserve precision */ |
1567 | /* Use ns/us then divide to preserve precision */ |
1565 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1568 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1566 | pixel_size * hdisplay; |
1569 | pixel_size * hdisplay; |
1567 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1570 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1568 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1571 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1569 | srwm = wm_info->fifo_size - entries; |
1572 | srwm = wm_info->fifo_size - entries; |
1570 | if (srwm < 0) |
1573 | if (srwm < 0) |
1571 | srwm = 1; |
1574 | srwm = 1; |
1572 | 1575 | ||
1573 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1576 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1574 | I915_WRITE(FW_BLC_SELF, |
1577 | I915_WRITE(FW_BLC_SELF, |
1575 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1578 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1576 | else if (IS_I915GM(dev)) |
1579 | else if (IS_I915GM(dev)) |
1577 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1580 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1578 | } |
1581 | } |
1579 | 1582 | ||
1580 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1583 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1581 | planea_wm, planeb_wm, cwm, srwm); |
1584 | planea_wm, planeb_wm, cwm, srwm); |
1582 | 1585 | ||
1583 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1586 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1584 | fwater_hi = (cwm & 0x1f); |
1587 | fwater_hi = (cwm & 0x1f); |
1585 | 1588 | ||
1586 | /* Set request length to 8 cachelines per fetch */ |
1589 | /* Set request length to 8 cachelines per fetch */ |
1587 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1590 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1588 | fwater_hi = fwater_hi | (1 << 8); |
1591 | fwater_hi = fwater_hi | (1 << 8); |
1589 | 1592 | ||
1590 | I915_WRITE(FW_BLC, fwater_lo); |
1593 | I915_WRITE(FW_BLC, fwater_lo); |
1591 | I915_WRITE(FW_BLC2, fwater_hi); |
1594 | I915_WRITE(FW_BLC2, fwater_hi); |
1592 | 1595 | ||
1593 | if (HAS_FW_BLC(dev)) { |
1596 | if (HAS_FW_BLC(dev)) { |
1594 | if (enabled) { |
1597 | if (enabled) { |
1595 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1598 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1596 | I915_WRITE(FW_BLC_SELF, |
1599 | I915_WRITE(FW_BLC_SELF, |
1597 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
1600 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
1598 | else if (IS_I915GM(dev)) |
1601 | else if (IS_I915GM(dev)) |
1599 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
1602 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
1600 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
1603 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
1601 | } else |
1604 | } else |
1602 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
1605 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
1603 | } |
1606 | } |
1604 | } |
1607 | } |
1605 | 1608 | ||
1606 | static void i830_update_wm(struct drm_device *dev) |
1609 | static void i830_update_wm(struct drm_device *dev) |
1607 | { |
1610 | { |
1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; |
1609 | struct drm_crtc *crtc; |
1612 | struct drm_crtc *crtc; |
1610 | uint32_t fwater_lo; |
1613 | uint32_t fwater_lo; |
1611 | int planea_wm; |
1614 | int planea_wm; |
1612 | 1615 | ||
1613 | crtc = single_enabled_crtc(dev); |
1616 | crtc = single_enabled_crtc(dev); |
1614 | if (crtc == NULL) |
1617 | if (crtc == NULL) |
1615 | return; |
1618 | return; |
1616 | 1619 | ||
1617 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
1620 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
1618 | dev_priv->display.get_fifo_size(dev, 0), |
1621 | dev_priv->display.get_fifo_size(dev, 0), |
1619 | 4, latency_ns); |
1622 | 4, latency_ns); |
1620 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1623 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1621 | fwater_lo |= (3<<8) | planea_wm; |
1624 | fwater_lo |= (3<<8) | planea_wm; |
1622 | 1625 | ||
1623 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1626 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1624 | 1627 | ||
1625 | I915_WRITE(FW_BLC, fwater_lo); |
1628 | I915_WRITE(FW_BLC, fwater_lo); |
1626 | } |
1629 | } |
1627 | 1630 | ||
1628 | #define ILK_LP0_PLANE_LATENCY 700 |
1631 | #define ILK_LP0_PLANE_LATENCY 700 |
1629 | #define ILK_LP0_CURSOR_LATENCY 1300 |
1632 | #define ILK_LP0_CURSOR_LATENCY 1300 |
1630 | 1633 | ||
1631 | /* |
1634 | /* |
1632 | * Check the wm result. |
1635 | * Check the wm result. |
1633 | * |
1636 | * |
1634 | * If any calculated watermark values is larger than the maximum value that |
1637 | * If any calculated watermark values is larger than the maximum value that |
1635 | * can be programmed into the associated watermark register, that watermark |
1638 | * can be programmed into the associated watermark register, that watermark |
1636 | * must be disabled. |
1639 | * must be disabled. |
1637 | */ |
1640 | */ |
1638 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
1641 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
1639 | int fbc_wm, int display_wm, int cursor_wm, |
1642 | int fbc_wm, int display_wm, int cursor_wm, |
1640 | const struct intel_watermark_params *display, |
1643 | const struct intel_watermark_params *display, |
1641 | const struct intel_watermark_params *cursor) |
1644 | const struct intel_watermark_params *cursor) |
1642 | { |
1645 | { |
1643 | struct drm_i915_private *dev_priv = dev->dev_private; |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; |
1644 | 1647 | ||
1645 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
1648 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
1646 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
1649 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
1647 | 1650 | ||
1648 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
1651 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
1649 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
1652 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
1650 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1653 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1651 | 1654 | ||
1652 | /* fbc has it's own way to disable FBC WM */ |
1655 | /* fbc has it's own way to disable FBC WM */ |
1653 | I915_WRITE(DISP_ARB_CTL, |
1656 | I915_WRITE(DISP_ARB_CTL, |
1654 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
1657 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
1655 | return false; |
1658 | return false; |
1656 | } |
1659 | } |
1657 | 1660 | ||
1658 | if (display_wm > display->max_wm) { |
1661 | if (display_wm > display->max_wm) { |
1659 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
1662 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
1660 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1663 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1661 | return false; |
1664 | return false; |
1662 | } |
1665 | } |
1663 | 1666 | ||
1664 | if (cursor_wm > cursor->max_wm) { |
1667 | if (cursor_wm > cursor->max_wm) { |
1665 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
1668 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
1666 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1669 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1667 | return false; |
1670 | return false; |
1668 | } |
1671 | } |
1669 | 1672 | ||
1670 | if (!(fbc_wm || display_wm || cursor_wm)) { |
1673 | if (!(fbc_wm || display_wm || cursor_wm)) { |
1671 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
1674 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
1672 | return false; |
1675 | return false; |
1673 | } |
1676 | } |
1674 | 1677 | ||
1675 | return true; |
1678 | return true; |
1676 | } |
1679 | } |
1677 | 1680 | ||
1678 | /* |
1681 | /* |
1679 | * Compute watermark values of WM[1-3], |
1682 | * Compute watermark values of WM[1-3], |
1680 | */ |
1683 | */ |
1681 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
1684 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
1682 | int latency_ns, |
1685 | int latency_ns, |
1683 | const struct intel_watermark_params *display, |
1686 | const struct intel_watermark_params *display, |
1684 | const struct intel_watermark_params *cursor, |
1687 | const struct intel_watermark_params *cursor, |
1685 | int *fbc_wm, int *display_wm, int *cursor_wm) |
1688 | int *fbc_wm, int *display_wm, int *cursor_wm) |
1686 | { |
1689 | { |
1687 | struct drm_crtc *crtc; |
1690 | struct drm_crtc *crtc; |
1688 | unsigned long line_time_us; |
1691 | unsigned long line_time_us; |
1689 | int hdisplay, htotal, pixel_size, clock; |
1692 | int hdisplay, htotal, pixel_size, clock; |
1690 | int line_count, line_size; |
1693 | int line_count, line_size; |
1691 | int small, large; |
1694 | int small, large; |
1692 | int entries; |
1695 | int entries; |
1693 | 1696 | ||
1694 | if (!latency_ns) { |
1697 | if (!latency_ns) { |
1695 | *fbc_wm = *display_wm = *cursor_wm = 0; |
1698 | *fbc_wm = *display_wm = *cursor_wm = 0; |
1696 | return false; |
1699 | return false; |
1697 | } |
1700 | } |
1698 | 1701 | ||
1699 | crtc = intel_get_crtc_for_plane(dev, plane); |
1702 | crtc = intel_get_crtc_for_plane(dev, plane); |
1700 | hdisplay = crtc->mode.hdisplay; |
1703 | hdisplay = crtc->mode.hdisplay; |
1701 | htotal = crtc->mode.htotal; |
1704 | htotal = crtc->mode.htotal; |
1702 | clock = crtc->mode.clock; |
1705 | clock = crtc->mode.clock; |
1703 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1706 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1704 | 1707 | ||
1705 | line_time_us = (htotal * 1000) / clock; |
1708 | line_time_us = (htotal * 1000) / clock; |
1706 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1709 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1707 | line_size = hdisplay * pixel_size; |
1710 | line_size = hdisplay * pixel_size; |
1708 | 1711 | ||
1709 | /* Use the minimum of the small and large buffer method for primary */ |
1712 | /* Use the minimum of the small and large buffer method for primary */ |
1710 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1713 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1711 | large = line_count * line_size; |
1714 | large = line_count * line_size; |
1712 | 1715 | ||
1713 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1716 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1714 | *display_wm = entries + display->guard_size; |
1717 | *display_wm = entries + display->guard_size; |
1715 | 1718 | ||
1716 | /* |
1719 | /* |
1717 | * Spec says: |
1720 | * Spec says: |
1718 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
1721 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
1719 | */ |
1722 | */ |
1720 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
1723 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
1721 | 1724 | ||
1722 | /* calculate the self-refresh watermark for display cursor */ |
1725 | /* calculate the self-refresh watermark for display cursor */ |
1723 | entries = line_count * pixel_size * 64; |
1726 | entries = line_count * pixel_size * 64; |
1724 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1727 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1725 | *cursor_wm = entries + cursor->guard_size; |
1728 | *cursor_wm = entries + cursor->guard_size; |
1726 | 1729 | ||
1727 | return ironlake_check_srwm(dev, level, |
1730 | return ironlake_check_srwm(dev, level, |
1728 | *fbc_wm, *display_wm, *cursor_wm, |
1731 | *fbc_wm, *display_wm, *cursor_wm, |
1729 | display, cursor); |
1732 | display, cursor); |
1730 | } |
1733 | } |
1731 | 1734 | ||
1732 | static void ironlake_update_wm(struct drm_device *dev) |
1735 | static void ironlake_update_wm(struct drm_device *dev) |
1733 | { |
1736 | { |
1734 | struct drm_i915_private *dev_priv = dev->dev_private; |
1737 | struct drm_i915_private *dev_priv = dev->dev_private; |
1735 | int fbc_wm, plane_wm, cursor_wm; |
1738 | int fbc_wm, plane_wm, cursor_wm; |
1736 | unsigned int enabled; |
1739 | unsigned int enabled; |
1737 | 1740 | ||
1738 | enabled = 0; |
1741 | enabled = 0; |
1739 | if (g4x_compute_wm0(dev, 0, |
1742 | if (g4x_compute_wm0(dev, 0, |
1740 | &ironlake_display_wm_info, |
1743 | &ironlake_display_wm_info, |
1741 | ILK_LP0_PLANE_LATENCY, |
1744 | ILK_LP0_PLANE_LATENCY, |
1742 | &ironlake_cursor_wm_info, |
1745 | &ironlake_cursor_wm_info, |
1743 | ILK_LP0_CURSOR_LATENCY, |
1746 | ILK_LP0_CURSOR_LATENCY, |
1744 | &plane_wm, &cursor_wm)) { |
1747 | &plane_wm, &cursor_wm)) { |
1745 | I915_WRITE(WM0_PIPEA_ILK, |
1748 | I915_WRITE(WM0_PIPEA_ILK, |
1746 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1749 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1747 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1750 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1748 | " plane %d, " "cursor: %d\n", |
1751 | " plane %d, " "cursor: %d\n", |
1749 | plane_wm, cursor_wm); |
1752 | plane_wm, cursor_wm); |
1750 | enabled |= 1; |
1753 | enabled |= 1; |
1751 | } |
1754 | } |
1752 | 1755 | ||
1753 | if (g4x_compute_wm0(dev, 1, |
1756 | if (g4x_compute_wm0(dev, 1, |
1754 | &ironlake_display_wm_info, |
1757 | &ironlake_display_wm_info, |
1755 | ILK_LP0_PLANE_LATENCY, |
1758 | ILK_LP0_PLANE_LATENCY, |
1756 | &ironlake_cursor_wm_info, |
1759 | &ironlake_cursor_wm_info, |
1757 | ILK_LP0_CURSOR_LATENCY, |
1760 | ILK_LP0_CURSOR_LATENCY, |
1758 | &plane_wm, &cursor_wm)) { |
1761 | &plane_wm, &cursor_wm)) { |
1759 | I915_WRITE(WM0_PIPEB_ILK, |
1762 | I915_WRITE(WM0_PIPEB_ILK, |
1760 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1763 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1761 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1764 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1762 | " plane %d, cursor: %d\n", |
1765 | " plane %d, cursor: %d\n", |
1763 | plane_wm, cursor_wm); |
1766 | plane_wm, cursor_wm); |
1764 | enabled |= 2; |
1767 | enabled |= 2; |
1765 | } |
1768 | } |
1766 | 1769 | ||
1767 | /* |
1770 | /* |
1768 | * Calculate and update the self-refresh watermark only when one |
1771 | * Calculate and update the self-refresh watermark only when one |
1769 | * display plane is used. |
1772 | * display plane is used. |
1770 | */ |
1773 | */ |
1771 | I915_WRITE(WM3_LP_ILK, 0); |
1774 | I915_WRITE(WM3_LP_ILK, 0); |
1772 | I915_WRITE(WM2_LP_ILK, 0); |
1775 | I915_WRITE(WM2_LP_ILK, 0); |
1773 | I915_WRITE(WM1_LP_ILK, 0); |
1776 | I915_WRITE(WM1_LP_ILK, 0); |
1774 | 1777 | ||
1775 | if (!single_plane_enabled(enabled)) |
1778 | if (!single_plane_enabled(enabled)) |
1776 | return; |
1779 | return; |
1777 | enabled = ffs(enabled) - 1; |
1780 | enabled = ffs(enabled) - 1; |
1778 | 1781 | ||
1779 | /* WM1 */ |
1782 | /* WM1 */ |
1780 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1783 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1781 | ILK_READ_WM1_LATENCY() * 500, |
1784 | ILK_READ_WM1_LATENCY() * 500, |
1782 | &ironlake_display_srwm_info, |
1785 | &ironlake_display_srwm_info, |
1783 | &ironlake_cursor_srwm_info, |
1786 | &ironlake_cursor_srwm_info, |
1784 | &fbc_wm, &plane_wm, &cursor_wm)) |
1787 | &fbc_wm, &plane_wm, &cursor_wm)) |
1785 | return; |
1788 | return; |
1786 | 1789 | ||
1787 | I915_WRITE(WM1_LP_ILK, |
1790 | I915_WRITE(WM1_LP_ILK, |
1788 | WM1_LP_SR_EN | |
1791 | WM1_LP_SR_EN | |
1789 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1792 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1790 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1793 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1791 | (plane_wm << WM1_LP_SR_SHIFT) | |
1794 | (plane_wm << WM1_LP_SR_SHIFT) | |
1792 | cursor_wm); |
1795 | cursor_wm); |
1793 | 1796 | ||
1794 | /* WM2 */ |
1797 | /* WM2 */ |
1795 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1798 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1796 | ILK_READ_WM2_LATENCY() * 500, |
1799 | ILK_READ_WM2_LATENCY() * 500, |
1797 | &ironlake_display_srwm_info, |
1800 | &ironlake_display_srwm_info, |
1798 | &ironlake_cursor_srwm_info, |
1801 | &ironlake_cursor_srwm_info, |
1799 | &fbc_wm, &plane_wm, &cursor_wm)) |
1802 | &fbc_wm, &plane_wm, &cursor_wm)) |
1800 | return; |
1803 | return; |
1801 | 1804 | ||
1802 | I915_WRITE(WM2_LP_ILK, |
1805 | I915_WRITE(WM2_LP_ILK, |
1803 | WM2_LP_EN | |
1806 | WM2_LP_EN | |
1804 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1807 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1805 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1808 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1806 | (plane_wm << WM1_LP_SR_SHIFT) | |
1809 | (plane_wm << WM1_LP_SR_SHIFT) | |
1807 | cursor_wm); |
1810 | cursor_wm); |
1808 | 1811 | ||
1809 | /* |
1812 | /* |
1810 | * WM3 is unsupported on ILK, probably because we don't have latency |
1813 | * WM3 is unsupported on ILK, probably because we don't have latency |
1811 | * data for that power state |
1814 | * data for that power state |
1812 | */ |
1815 | */ |
1813 | } |
1816 | } |
1814 | 1817 | ||
1815 | static void sandybridge_update_wm(struct drm_device *dev) |
1818 | static void sandybridge_update_wm(struct drm_device *dev) |
1816 | { |
1819 | { |
1817 | struct drm_i915_private *dev_priv = dev->dev_private; |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
1818 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1821 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1819 | u32 val; |
1822 | u32 val; |
1820 | int fbc_wm, plane_wm, cursor_wm; |
1823 | int fbc_wm, plane_wm, cursor_wm; |
1821 | unsigned int enabled; |
1824 | unsigned int enabled; |
1822 | 1825 | ||
1823 | enabled = 0; |
1826 | enabled = 0; |
1824 | if (g4x_compute_wm0(dev, 0, |
1827 | if (g4x_compute_wm0(dev, 0, |
1825 | &sandybridge_display_wm_info, latency, |
1828 | &sandybridge_display_wm_info, latency, |
1826 | &sandybridge_cursor_wm_info, latency, |
1829 | &sandybridge_cursor_wm_info, latency, |
1827 | &plane_wm, &cursor_wm)) { |
1830 | &plane_wm, &cursor_wm)) { |
1828 | val = I915_READ(WM0_PIPEA_ILK); |
1831 | val = I915_READ(WM0_PIPEA_ILK); |
1829 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1832 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1830 | I915_WRITE(WM0_PIPEA_ILK, val | |
1833 | I915_WRITE(WM0_PIPEA_ILK, val | |
1831 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1834 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1832 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1835 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1833 | " plane %d, " "cursor: %d\n", |
1836 | " plane %d, " "cursor: %d\n", |
1834 | plane_wm, cursor_wm); |
1837 | plane_wm, cursor_wm); |
1835 | enabled |= 1; |
1838 | enabled |= 1; |
1836 | } |
1839 | } |
1837 | 1840 | ||
1838 | if (g4x_compute_wm0(dev, 1, |
1841 | if (g4x_compute_wm0(dev, 1, |
1839 | &sandybridge_display_wm_info, latency, |
1842 | &sandybridge_display_wm_info, latency, |
1840 | &sandybridge_cursor_wm_info, latency, |
1843 | &sandybridge_cursor_wm_info, latency, |
1841 | &plane_wm, &cursor_wm)) { |
1844 | &plane_wm, &cursor_wm)) { |
1842 | val = I915_READ(WM0_PIPEB_ILK); |
1845 | val = I915_READ(WM0_PIPEB_ILK); |
1843 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1846 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1844 | I915_WRITE(WM0_PIPEB_ILK, val | |
1847 | I915_WRITE(WM0_PIPEB_ILK, val | |
1845 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1848 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1846 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1849 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1847 | " plane %d, cursor: %d\n", |
1850 | " plane %d, cursor: %d\n", |
1848 | plane_wm, cursor_wm); |
1851 | plane_wm, cursor_wm); |
1849 | enabled |= 2; |
1852 | enabled |= 2; |
1850 | } |
1853 | } |
1851 | 1854 | ||
1852 | /* |
1855 | /* |
1853 | * Calculate and update the self-refresh watermark only when one |
1856 | * Calculate and update the self-refresh watermark only when one |
1854 | * display plane is used. |
1857 | * display plane is used. |
1855 | * |
1858 | * |
1856 | * SNB support 3 levels of watermark. |
1859 | * SNB support 3 levels of watermark. |
1857 | * |
1860 | * |
1858 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1861 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1859 | * and disabled in the descending order |
1862 | * and disabled in the descending order |
1860 | * |
1863 | * |
1861 | */ |
1864 | */ |
1862 | I915_WRITE(WM3_LP_ILK, 0); |
1865 | I915_WRITE(WM3_LP_ILK, 0); |
1863 | I915_WRITE(WM2_LP_ILK, 0); |
1866 | I915_WRITE(WM2_LP_ILK, 0); |
1864 | I915_WRITE(WM1_LP_ILK, 0); |
1867 | I915_WRITE(WM1_LP_ILK, 0); |
1865 | 1868 | ||
1866 | if (!single_plane_enabled(enabled) || |
1869 | if (!single_plane_enabled(enabled) || |
1867 | dev_priv->sprite_scaling_enabled) |
1870 | dev_priv->sprite_scaling_enabled) |
1868 | return; |
1871 | return; |
1869 | enabled = ffs(enabled) - 1; |
1872 | enabled = ffs(enabled) - 1; |
1870 | 1873 | ||
1871 | /* WM1 */ |
1874 | /* WM1 */ |
1872 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1875 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1873 | SNB_READ_WM1_LATENCY() * 500, |
1876 | SNB_READ_WM1_LATENCY() * 500, |
1874 | &sandybridge_display_srwm_info, |
1877 | &sandybridge_display_srwm_info, |
1875 | &sandybridge_cursor_srwm_info, |
1878 | &sandybridge_cursor_srwm_info, |
1876 | &fbc_wm, &plane_wm, &cursor_wm)) |
1879 | &fbc_wm, &plane_wm, &cursor_wm)) |
1877 | return; |
1880 | return; |
1878 | 1881 | ||
1879 | I915_WRITE(WM1_LP_ILK, |
1882 | I915_WRITE(WM1_LP_ILK, |
1880 | WM1_LP_SR_EN | |
1883 | WM1_LP_SR_EN | |
1881 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1884 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1882 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1885 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1883 | (plane_wm << WM1_LP_SR_SHIFT) | |
1886 | (plane_wm << WM1_LP_SR_SHIFT) | |
1884 | cursor_wm); |
1887 | cursor_wm); |
1885 | 1888 | ||
1886 | /* WM2 */ |
1889 | /* WM2 */ |
1887 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1890 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1888 | SNB_READ_WM2_LATENCY() * 500, |
1891 | SNB_READ_WM2_LATENCY() * 500, |
1889 | &sandybridge_display_srwm_info, |
1892 | &sandybridge_display_srwm_info, |
1890 | &sandybridge_cursor_srwm_info, |
1893 | &sandybridge_cursor_srwm_info, |
1891 | &fbc_wm, &plane_wm, &cursor_wm)) |
1894 | &fbc_wm, &plane_wm, &cursor_wm)) |
1892 | return; |
1895 | return; |
1893 | 1896 | ||
1894 | I915_WRITE(WM2_LP_ILK, |
1897 | I915_WRITE(WM2_LP_ILK, |
1895 | WM2_LP_EN | |
1898 | WM2_LP_EN | |
1896 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1899 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1897 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1900 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1898 | (plane_wm << WM1_LP_SR_SHIFT) | |
1901 | (plane_wm << WM1_LP_SR_SHIFT) | |
1899 | cursor_wm); |
1902 | cursor_wm); |
1900 | 1903 | ||
1901 | /* WM3 */ |
1904 | /* WM3 */ |
1902 | if (!ironlake_compute_srwm(dev, 3, enabled, |
1905 | if (!ironlake_compute_srwm(dev, 3, enabled, |
1903 | SNB_READ_WM3_LATENCY() * 500, |
1906 | SNB_READ_WM3_LATENCY() * 500, |
1904 | &sandybridge_display_srwm_info, |
1907 | &sandybridge_display_srwm_info, |
1905 | &sandybridge_cursor_srwm_info, |
1908 | &sandybridge_cursor_srwm_info, |
1906 | &fbc_wm, &plane_wm, &cursor_wm)) |
1909 | &fbc_wm, &plane_wm, &cursor_wm)) |
1907 | return; |
1910 | return; |
1908 | 1911 | ||
1909 | I915_WRITE(WM3_LP_ILK, |
1912 | I915_WRITE(WM3_LP_ILK, |
1910 | WM3_LP_EN | |
1913 | WM3_LP_EN | |
1911 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1914 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1912 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1915 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1913 | (plane_wm << WM1_LP_SR_SHIFT) | |
1916 | (plane_wm << WM1_LP_SR_SHIFT) | |
1914 | cursor_wm); |
1917 | cursor_wm); |
1915 | } |
1918 | } |
1916 | 1919 | ||
1917 | static void ivybridge_update_wm(struct drm_device *dev) |
1920 | static void ivybridge_update_wm(struct drm_device *dev) |
1918 | { |
1921 | { |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; |
1922 | struct drm_i915_private *dev_priv = dev->dev_private; |
1920 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1923 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1921 | u32 val; |
1924 | u32 val; |
1922 | int fbc_wm, plane_wm, cursor_wm; |
1925 | int fbc_wm, plane_wm, cursor_wm; |
1923 | int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; |
1926 | int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; |
1924 | unsigned int enabled; |
1927 | unsigned int enabled; |
1925 | 1928 | ||
1926 | enabled = 0; |
1929 | enabled = 0; |
1927 | if (g4x_compute_wm0(dev, 0, |
1930 | if (g4x_compute_wm0(dev, 0, |
1928 | &sandybridge_display_wm_info, latency, |
1931 | &sandybridge_display_wm_info, latency, |
1929 | &sandybridge_cursor_wm_info, latency, |
1932 | &sandybridge_cursor_wm_info, latency, |
1930 | &plane_wm, &cursor_wm)) { |
1933 | &plane_wm, &cursor_wm)) { |
1931 | val = I915_READ(WM0_PIPEA_ILK); |
1934 | val = I915_READ(WM0_PIPEA_ILK); |
1932 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1935 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1933 | I915_WRITE(WM0_PIPEA_ILK, val | |
1936 | I915_WRITE(WM0_PIPEA_ILK, val | |
1934 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1937 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1935 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1938 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1936 | " plane %d, " "cursor: %d\n", |
1939 | " plane %d, " "cursor: %d\n", |
1937 | plane_wm, cursor_wm); |
1940 | plane_wm, cursor_wm); |
1938 | enabled |= 1; |
1941 | enabled |= 1; |
1939 | } |
1942 | } |
1940 | 1943 | ||
1941 | if (g4x_compute_wm0(dev, 1, |
1944 | if (g4x_compute_wm0(dev, 1, |
1942 | &sandybridge_display_wm_info, latency, |
1945 | &sandybridge_display_wm_info, latency, |
1943 | &sandybridge_cursor_wm_info, latency, |
1946 | &sandybridge_cursor_wm_info, latency, |
1944 | &plane_wm, &cursor_wm)) { |
1947 | &plane_wm, &cursor_wm)) { |
1945 | val = I915_READ(WM0_PIPEB_ILK); |
1948 | val = I915_READ(WM0_PIPEB_ILK); |
1946 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1949 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1947 | I915_WRITE(WM0_PIPEB_ILK, val | |
1950 | I915_WRITE(WM0_PIPEB_ILK, val | |
1948 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1951 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1949 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1952 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1950 | " plane %d, cursor: %d\n", |
1953 | " plane %d, cursor: %d\n", |
1951 | plane_wm, cursor_wm); |
1954 | plane_wm, cursor_wm); |
1952 | enabled |= 2; |
1955 | enabled |= 2; |
1953 | } |
1956 | } |
1954 | 1957 | ||
1955 | if (g4x_compute_wm0(dev, 2, |
1958 | if (g4x_compute_wm0(dev, 2, |
1956 | &sandybridge_display_wm_info, latency, |
1959 | &sandybridge_display_wm_info, latency, |
1957 | &sandybridge_cursor_wm_info, latency, |
1960 | &sandybridge_cursor_wm_info, latency, |
1958 | &plane_wm, &cursor_wm)) { |
1961 | &plane_wm, &cursor_wm)) { |
1959 | val = I915_READ(WM0_PIPEC_IVB); |
1962 | val = I915_READ(WM0_PIPEC_IVB); |
1960 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1963 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1961 | I915_WRITE(WM0_PIPEC_IVB, val | |
1964 | I915_WRITE(WM0_PIPEC_IVB, val | |
1962 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1965 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1963 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
1966 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
1964 | " plane %d, cursor: %d\n", |
1967 | " plane %d, cursor: %d\n", |
1965 | plane_wm, cursor_wm); |
1968 | plane_wm, cursor_wm); |
1966 | enabled |= 3; |
1969 | enabled |= 3; |
1967 | } |
1970 | } |
1968 | 1971 | ||
1969 | /* |
1972 | /* |
1970 | * Calculate and update the self-refresh watermark only when one |
1973 | * Calculate and update the self-refresh watermark only when one |
1971 | * display plane is used. |
1974 | * display plane is used. |
1972 | * |
1975 | * |
1973 | * SNB support 3 levels of watermark. |
1976 | * SNB support 3 levels of watermark. |
1974 | * |
1977 | * |
1975 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1978 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1976 | * and disabled in the descending order |
1979 | * and disabled in the descending order |
1977 | * |
1980 | * |
1978 | */ |
1981 | */ |
1979 | I915_WRITE(WM3_LP_ILK, 0); |
1982 | I915_WRITE(WM3_LP_ILK, 0); |
1980 | I915_WRITE(WM2_LP_ILK, 0); |
1983 | I915_WRITE(WM2_LP_ILK, 0); |
1981 | I915_WRITE(WM1_LP_ILK, 0); |
1984 | I915_WRITE(WM1_LP_ILK, 0); |
1982 | 1985 | ||
1983 | if (!single_plane_enabled(enabled) || |
1986 | if (!single_plane_enabled(enabled) || |
1984 | dev_priv->sprite_scaling_enabled) |
1987 | dev_priv->sprite_scaling_enabled) |
1985 | return; |
1988 | return; |
1986 | enabled = ffs(enabled) - 1; |
1989 | enabled = ffs(enabled) - 1; |
1987 | 1990 | ||
1988 | /* WM1 */ |
1991 | /* WM1 */ |
1989 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1992 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1990 | SNB_READ_WM1_LATENCY() * 500, |
1993 | SNB_READ_WM1_LATENCY() * 500, |
1991 | &sandybridge_display_srwm_info, |
1994 | &sandybridge_display_srwm_info, |
1992 | &sandybridge_cursor_srwm_info, |
1995 | &sandybridge_cursor_srwm_info, |
1993 | &fbc_wm, &plane_wm, &cursor_wm)) |
1996 | &fbc_wm, &plane_wm, &cursor_wm)) |
1994 | return; |
1997 | return; |
1995 | 1998 | ||
1996 | I915_WRITE(WM1_LP_ILK, |
1999 | I915_WRITE(WM1_LP_ILK, |
1997 | WM1_LP_SR_EN | |
2000 | WM1_LP_SR_EN | |
1998 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2001 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1999 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2002 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2000 | (plane_wm << WM1_LP_SR_SHIFT) | |
2003 | (plane_wm << WM1_LP_SR_SHIFT) | |
2001 | cursor_wm); |
2004 | cursor_wm); |
2002 | 2005 | ||
2003 | /* WM2 */ |
2006 | /* WM2 */ |
2004 | if (!ironlake_compute_srwm(dev, 2, enabled, |
2007 | if (!ironlake_compute_srwm(dev, 2, enabled, |
2005 | SNB_READ_WM2_LATENCY() * 500, |
2008 | SNB_READ_WM2_LATENCY() * 500, |
2006 | &sandybridge_display_srwm_info, |
2009 | &sandybridge_display_srwm_info, |
2007 | &sandybridge_cursor_srwm_info, |
2010 | &sandybridge_cursor_srwm_info, |
2008 | &fbc_wm, &plane_wm, &cursor_wm)) |
2011 | &fbc_wm, &plane_wm, &cursor_wm)) |
2009 | return; |
2012 | return; |
2010 | 2013 | ||
2011 | I915_WRITE(WM2_LP_ILK, |
2014 | I915_WRITE(WM2_LP_ILK, |
2012 | WM2_LP_EN | |
2015 | WM2_LP_EN | |
2013 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2016 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2014 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2017 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2015 | (plane_wm << WM1_LP_SR_SHIFT) | |
2018 | (plane_wm << WM1_LP_SR_SHIFT) | |
2016 | cursor_wm); |
2019 | cursor_wm); |
2017 | 2020 | ||
2018 | /* WM3, note we have to correct the cursor latency */ |
2021 | /* WM3, note we have to correct the cursor latency */ |
2019 | if (!ironlake_compute_srwm(dev, 3, enabled, |
2022 | if (!ironlake_compute_srwm(dev, 3, enabled, |
2020 | SNB_READ_WM3_LATENCY() * 500, |
2023 | SNB_READ_WM3_LATENCY() * 500, |
2021 | &sandybridge_display_srwm_info, |
2024 | &sandybridge_display_srwm_info, |
2022 | &sandybridge_cursor_srwm_info, |
2025 | &sandybridge_cursor_srwm_info, |
2023 | &fbc_wm, &plane_wm, &ignore_cursor_wm) || |
2026 | &fbc_wm, &plane_wm, &ignore_cursor_wm) || |
2024 | !ironlake_compute_srwm(dev, 3, enabled, |
2027 | !ironlake_compute_srwm(dev, 3, enabled, |
2025 | 2 * SNB_READ_WM3_LATENCY() * 500, |
2028 | 2 * SNB_READ_WM3_LATENCY() * 500, |
2026 | &sandybridge_display_srwm_info, |
2029 | &sandybridge_display_srwm_info, |
2027 | &sandybridge_cursor_srwm_info, |
2030 | &sandybridge_cursor_srwm_info, |
2028 | &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) |
2031 | &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) |
2029 | return; |
2032 | return; |
2030 | 2033 | ||
2031 | I915_WRITE(WM3_LP_ILK, |
2034 | I915_WRITE(WM3_LP_ILK, |
2032 | WM3_LP_EN | |
2035 | WM3_LP_EN | |
2033 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2036 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2034 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2037 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2035 | (plane_wm << WM1_LP_SR_SHIFT) | |
2038 | (plane_wm << WM1_LP_SR_SHIFT) | |
2036 | cursor_wm); |
2039 | cursor_wm); |
2037 | } |
2040 | } |
2038 | 2041 | ||
2039 | static void |
2042 | static void |
2040 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, |
2043 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, |
2041 | struct drm_display_mode *mode) |
2044 | struct drm_display_mode *mode) |
2042 | { |
2045 | { |
2043 | struct drm_i915_private *dev_priv = dev->dev_private; |
2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
2044 | u32 temp; |
2047 | u32 temp; |
2045 | 2048 | ||
2046 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); |
2049 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); |
2047 | temp &= ~PIPE_WM_LINETIME_MASK; |
2050 | temp &= ~PIPE_WM_LINETIME_MASK; |
2048 | 2051 | ||
2049 | /* The WM are computed with base on how long it takes to fill a single |
2052 | /* The WM are computed with base on how long it takes to fill a single |
2050 | * row at the given clock rate, multiplied by 8. |
2053 | * row at the given clock rate, multiplied by 8. |
2051 | * */ |
2054 | * */ |
2052 | temp |= PIPE_WM_LINETIME_TIME( |
2055 | temp |= PIPE_WM_LINETIME_TIME( |
2053 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); |
2056 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); |
2054 | 2057 | ||
2055 | /* IPS watermarks are only used by pipe A, and are ignored by |
2058 | /* IPS watermarks are only used by pipe A, and are ignored by |
2056 | * pipes B and C. They are calculated similarly to the common |
2059 | * pipes B and C. They are calculated similarly to the common |
2057 | * linetime values, except that we are using CD clock frequency |
2060 | * linetime values, except that we are using CD clock frequency |
2058 | * in MHz instead of pixel rate for the division. |
2061 | * in MHz instead of pixel rate for the division. |
2059 | * |
2062 | * |
2060 | * This is a placeholder for the IPS watermark calculation code. |
2063 | * This is a placeholder for the IPS watermark calculation code. |
2061 | */ |
2064 | */ |
2062 | 2065 | ||
2063 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); |
2066 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); |
2064 | } |
2067 | } |
2065 | 2068 | ||
2066 | static bool |
2069 | static bool |
2067 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
2070 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
2068 | uint32_t sprite_width, int pixel_size, |
2071 | uint32_t sprite_width, int pixel_size, |
2069 | const struct intel_watermark_params *display, |
2072 | const struct intel_watermark_params *display, |
2070 | int display_latency_ns, int *sprite_wm) |
2073 | int display_latency_ns, int *sprite_wm) |
2071 | { |
2074 | { |
2072 | struct drm_crtc *crtc; |
2075 | struct drm_crtc *crtc; |
2073 | int clock; |
2076 | int clock; |
2074 | int entries, tlb_miss; |
2077 | int entries, tlb_miss; |
2075 | 2078 | ||
2076 | crtc = intel_get_crtc_for_plane(dev, plane); |
2079 | crtc = intel_get_crtc_for_plane(dev, plane); |
2077 | if (!intel_crtc_active(crtc)) { |
2080 | if (!intel_crtc_active(crtc)) { |
2078 | *sprite_wm = display->guard_size; |
2081 | *sprite_wm = display->guard_size; |
2079 | return false; |
2082 | return false; |
2080 | } |
2083 | } |
2081 | 2084 | ||
2082 | clock = crtc->mode.clock; |
2085 | clock = crtc->mode.clock; |
2083 | 2086 | ||
2084 | /* Use the small buffer method to calculate the sprite watermark */ |
2087 | /* Use the small buffer method to calculate the sprite watermark */ |
2085 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
2088 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
2086 | tlb_miss = display->fifo_size*display->cacheline_size - |
2089 | tlb_miss = display->fifo_size*display->cacheline_size - |
2087 | sprite_width * 8; |
2090 | sprite_width * 8; |
2088 | if (tlb_miss > 0) |
2091 | if (tlb_miss > 0) |
2089 | entries += tlb_miss; |
2092 | entries += tlb_miss; |
2090 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
2093 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
2091 | *sprite_wm = entries + display->guard_size; |
2094 | *sprite_wm = entries + display->guard_size; |
2092 | if (*sprite_wm > (int)display->max_wm) |
2095 | if (*sprite_wm > (int)display->max_wm) |
2093 | *sprite_wm = display->max_wm; |
2096 | *sprite_wm = display->max_wm; |
2094 | 2097 | ||
2095 | return true; |
2098 | return true; |
2096 | } |
2099 | } |
2097 | 2100 | ||
2098 | static bool |
2101 | static bool |
2099 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
2102 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
2100 | uint32_t sprite_width, int pixel_size, |
2103 | uint32_t sprite_width, int pixel_size, |
2101 | const struct intel_watermark_params *display, |
2104 | const struct intel_watermark_params *display, |
2102 | int latency_ns, int *sprite_wm) |
2105 | int latency_ns, int *sprite_wm) |
2103 | { |
2106 | { |
2104 | struct drm_crtc *crtc; |
2107 | struct drm_crtc *crtc; |
2105 | unsigned long line_time_us; |
2108 | unsigned long line_time_us; |
2106 | int clock; |
2109 | int clock; |
2107 | int line_count, line_size; |
2110 | int line_count, line_size; |
2108 | int small, large; |
2111 | int small, large; |
2109 | int entries; |
2112 | int entries; |
2110 | 2113 | ||
2111 | if (!latency_ns) { |
2114 | if (!latency_ns) { |
2112 | *sprite_wm = 0; |
2115 | *sprite_wm = 0; |
2113 | return false; |
2116 | return false; |
2114 | } |
2117 | } |
2115 | 2118 | ||
2116 | crtc = intel_get_crtc_for_plane(dev, plane); |
2119 | crtc = intel_get_crtc_for_plane(dev, plane); |
2117 | clock = crtc->mode.clock; |
2120 | clock = crtc->mode.clock; |
2118 | if (!clock) { |
2121 | if (!clock) { |
2119 | *sprite_wm = 0; |
2122 | *sprite_wm = 0; |
2120 | return false; |
2123 | return false; |
2121 | } |
2124 | } |
2122 | 2125 | ||
2123 | line_time_us = (sprite_width * 1000) / clock; |
2126 | line_time_us = (sprite_width * 1000) / clock; |
2124 | if (!line_time_us) { |
2127 | if (!line_time_us) { |
2125 | *sprite_wm = 0; |
2128 | *sprite_wm = 0; |
2126 | return false; |
2129 | return false; |
2127 | } |
2130 | } |
2128 | 2131 | ||
2129 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
2132 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
2130 | line_size = sprite_width * pixel_size; |
2133 | line_size = sprite_width * pixel_size; |
2131 | 2134 | ||
2132 | /* Use the minimum of the small and large buffer method for primary */ |
2135 | /* Use the minimum of the small and large buffer method for primary */ |
2133 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
2136 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
2134 | large = line_count * line_size; |
2137 | large = line_count * line_size; |
2135 | 2138 | ||
2136 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
2139 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
2137 | *sprite_wm = entries + display->guard_size; |
2140 | *sprite_wm = entries + display->guard_size; |
2138 | 2141 | ||
2139 | return *sprite_wm > 0x3ff ? false : true; |
2142 | return *sprite_wm > 0x3ff ? false : true; |
2140 | } |
2143 | } |
2141 | 2144 | ||
2142 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
2145 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
2143 | uint32_t sprite_width, int pixel_size) |
2146 | uint32_t sprite_width, int pixel_size) |
2144 | { |
2147 | { |
2145 | struct drm_i915_private *dev_priv = dev->dev_private; |
2148 | struct drm_i915_private *dev_priv = dev->dev_private; |
2146 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
2149 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
2147 | u32 val; |
2150 | u32 val; |
2148 | int sprite_wm, reg; |
2151 | int sprite_wm, reg; |
2149 | int ret; |
2152 | int ret; |
2150 | 2153 | ||
2151 | switch (pipe) { |
2154 | switch (pipe) { |
2152 | case 0: |
2155 | case 0: |
2153 | reg = WM0_PIPEA_ILK; |
2156 | reg = WM0_PIPEA_ILK; |
2154 | break; |
2157 | break; |
2155 | case 1: |
2158 | case 1: |
2156 | reg = WM0_PIPEB_ILK; |
2159 | reg = WM0_PIPEB_ILK; |
2157 | break; |
2160 | break; |
2158 | case 2: |
2161 | case 2: |
2159 | reg = WM0_PIPEC_IVB; |
2162 | reg = WM0_PIPEC_IVB; |
2160 | break; |
2163 | break; |
2161 | default: |
2164 | default: |
2162 | return; /* bad pipe */ |
2165 | return; /* bad pipe */ |
2163 | } |
2166 | } |
2164 | 2167 | ||
2165 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
2168 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
2166 | &sandybridge_display_wm_info, |
2169 | &sandybridge_display_wm_info, |
2167 | latency, &sprite_wm); |
2170 | latency, &sprite_wm); |
2168 | if (!ret) { |
2171 | if (!ret) { |
2169 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
2172 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
2170 | pipe); |
2173 | pipe); |
2171 | return; |
2174 | return; |
2172 | } |
2175 | } |
2173 | 2176 | ||
2174 | val = I915_READ(reg); |
2177 | val = I915_READ(reg); |
2175 | val &= ~WM0_PIPE_SPRITE_MASK; |
2178 | val &= ~WM0_PIPE_SPRITE_MASK; |
2176 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
2179 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
2177 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
2180 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
2178 | 2181 | ||
2179 | 2182 | ||
2180 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2183 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2181 | pixel_size, |
2184 | pixel_size, |
2182 | &sandybridge_display_srwm_info, |
2185 | &sandybridge_display_srwm_info, |
2183 | SNB_READ_WM1_LATENCY() * 500, |
2186 | SNB_READ_WM1_LATENCY() * 500, |
2184 | &sprite_wm); |
2187 | &sprite_wm); |
2185 | if (!ret) { |
2188 | if (!ret) { |
2186 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
2189 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
2187 | pipe); |
2190 | pipe); |
2188 | return; |
2191 | return; |
2189 | } |
2192 | } |
2190 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
2193 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
2191 | 2194 | ||
2192 | /* Only IVB has two more LP watermarks for sprite */ |
2195 | /* Only IVB has two more LP watermarks for sprite */ |
2193 | if (!IS_IVYBRIDGE(dev)) |
2196 | if (!IS_IVYBRIDGE(dev)) |
2194 | return; |
2197 | return; |
2195 | 2198 | ||
2196 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2199 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2197 | pixel_size, |
2200 | pixel_size, |
2198 | &sandybridge_display_srwm_info, |
2201 | &sandybridge_display_srwm_info, |
2199 | SNB_READ_WM2_LATENCY() * 500, |
2202 | SNB_READ_WM2_LATENCY() * 500, |
2200 | &sprite_wm); |
2203 | &sprite_wm); |
2201 | if (!ret) { |
2204 | if (!ret) { |
2202 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
2205 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
2203 | pipe); |
2206 | pipe); |
2204 | return; |
2207 | return; |
2205 | } |
2208 | } |
2206 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
2209 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
2207 | 2210 | ||
2208 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2211 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2209 | pixel_size, |
2212 | pixel_size, |
2210 | &sandybridge_display_srwm_info, |
2213 | &sandybridge_display_srwm_info, |
2211 | SNB_READ_WM3_LATENCY() * 500, |
2214 | SNB_READ_WM3_LATENCY() * 500, |
2212 | &sprite_wm); |
2215 | &sprite_wm); |
2213 | if (!ret) { |
2216 | if (!ret) { |
2214 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
2217 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
2215 | pipe); |
2218 | pipe); |
2216 | return; |
2219 | return; |
2217 | } |
2220 | } |
2218 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
2221 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
2219 | } |
2222 | } |
2220 | 2223 | ||
2221 | /** |
2224 | /** |
2222 | * intel_update_watermarks - update FIFO watermark values based on current modes |
2225 | * intel_update_watermarks - update FIFO watermark values based on current modes |
2223 | * |
2226 | * |
2224 | * Calculate watermark values for the various WM regs based on current mode |
2227 | * Calculate watermark values for the various WM regs based on current mode |
2225 | * and plane configuration. |
2228 | * and plane configuration. |
2226 | * |
2229 | * |
2227 | * There are several cases to deal with here: |
2230 | * There are several cases to deal with here: |
2228 | * - normal (i.e. non-self-refresh) |
2231 | * - normal (i.e. non-self-refresh) |
2229 | * - self-refresh (SR) mode |
2232 | * - self-refresh (SR) mode |
2230 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
2233 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
2231 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
2234 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
2232 | * lines), so need to account for TLB latency |
2235 | * lines), so need to account for TLB latency |
2233 | * |
2236 | * |
2234 | * The normal calculation is: |
2237 | * The normal calculation is: |
2235 | * watermark = dotclock * bytes per pixel * latency |
2238 | * watermark = dotclock * bytes per pixel * latency |
2236 | * where latency is platform & configuration dependent (we assume pessimal |
2239 | * where latency is platform & configuration dependent (we assume pessimal |
2237 | * values here). |
2240 | * values here). |
2238 | * |
2241 | * |
2239 | * The SR calculation is: |
2242 | * The SR calculation is: |
2240 | * watermark = (trunc(latency/line time)+1) * surface width * |
2243 | * watermark = (trunc(latency/line time)+1) * surface width * |
2241 | * bytes per pixel |
2244 | * bytes per pixel |
2242 | * where |
2245 | * where |
2243 | * line time = htotal / dotclock |
2246 | * line time = htotal / dotclock |
2244 | * surface width = hdisplay for normal plane and 64 for cursor |
2247 | * surface width = hdisplay for normal plane and 64 for cursor |
2245 | * and latency is assumed to be high, as above. |
2248 | * and latency is assumed to be high, as above. |
2246 | * |
2249 | * |
2247 | * The final value programmed to the register should always be rounded up, |
2250 | * The final value programmed to the register should always be rounded up, |
2248 | * and include an extra 2 entries to account for clock crossings. |
2251 | * and include an extra 2 entries to account for clock crossings. |
2249 | * |
2252 | * |
2250 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
2253 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
2251 | * to set the non-SR watermarks to 8. |
2254 | * to set the non-SR watermarks to 8. |
2252 | */ |
2255 | */ |
2253 | void intel_update_watermarks(struct drm_device *dev) |
2256 | void intel_update_watermarks(struct drm_device *dev) |
2254 | { |
2257 | { |
2255 | struct drm_i915_private *dev_priv = dev->dev_private; |
2258 | struct drm_i915_private *dev_priv = dev->dev_private; |
2256 | 2259 | ||
2257 | if (dev_priv->display.update_wm) |
2260 | if (dev_priv->display.update_wm) |
2258 | dev_priv->display.update_wm(dev); |
2261 | dev_priv->display.update_wm(dev); |
2259 | } |
2262 | } |
2260 | 2263 | ||
2261 | void intel_update_linetime_watermarks(struct drm_device *dev, |
2264 | void intel_update_linetime_watermarks(struct drm_device *dev, |
2262 | int pipe, struct drm_display_mode *mode) |
2265 | int pipe, struct drm_display_mode *mode) |
2263 | { |
2266 | { |
2264 | struct drm_i915_private *dev_priv = dev->dev_private; |
2267 | struct drm_i915_private *dev_priv = dev->dev_private; |
2265 | 2268 | ||
2266 | if (dev_priv->display.update_linetime_wm) |
2269 | if (dev_priv->display.update_linetime_wm) |
2267 | dev_priv->display.update_linetime_wm(dev, pipe, mode); |
2270 | dev_priv->display.update_linetime_wm(dev, pipe, mode); |
2268 | } |
2271 | } |
2269 | 2272 | ||
2270 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
2273 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
2271 | uint32_t sprite_width, int pixel_size) |
2274 | uint32_t sprite_width, int pixel_size) |
2272 | { |
2275 | { |
2273 | struct drm_i915_private *dev_priv = dev->dev_private; |
2276 | struct drm_i915_private *dev_priv = dev->dev_private; |
2274 | 2277 | ||
2275 | if (dev_priv->display.update_sprite_wm) |
2278 | if (dev_priv->display.update_sprite_wm) |
2276 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
2279 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
2277 | pixel_size); |
2280 | pixel_size); |
2278 | } |
2281 | } |
2279 | 2282 | ||
2280 | static struct drm_i915_gem_object * |
2283 | static struct drm_i915_gem_object * |
2281 | intel_alloc_context_page(struct drm_device *dev) |
2284 | intel_alloc_context_page(struct drm_device *dev) |
2282 | { |
2285 | { |
2283 | struct drm_i915_gem_object *ctx; |
2286 | struct drm_i915_gem_object *ctx; |
2284 | int ret; |
2287 | int ret; |
2285 | 2288 | ||
2286 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2289 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2287 | 2290 | ||
2288 | ctx = i915_gem_alloc_object(dev, 4096); |
2291 | ctx = i915_gem_alloc_object(dev, 4096); |
2289 | if (!ctx) { |
2292 | if (!ctx) { |
2290 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
2293 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
2291 | return NULL; |
2294 | return NULL; |
2292 | } |
2295 | } |
2293 | 2296 | ||
2294 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
2297 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
2295 | if (ret) { |
2298 | if (ret) { |
2296 | DRM_ERROR("failed to pin power context: %d\n", ret); |
2299 | DRM_ERROR("failed to pin power context: %d\n", ret); |
2297 | goto err_unref; |
2300 | goto err_unref; |
2298 | } |
2301 | } |
2299 | 2302 | ||
2300 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
2303 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
2301 | if (ret) { |
2304 | if (ret) { |
2302 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
2305 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
2303 | goto err_unpin; |
2306 | goto err_unpin; |
2304 | } |
2307 | } |
2305 | 2308 | ||
2306 | return ctx; |
2309 | return ctx; |
2307 | 2310 | ||
2308 | err_unpin: |
2311 | err_unpin: |
2309 | i915_gem_object_unpin(ctx); |
2312 | i915_gem_object_unpin(ctx); |
2310 | err_unref: |
2313 | err_unref: |
2311 | drm_gem_object_unreference(&ctx->base); |
2314 | drm_gem_object_unreference(&ctx->base); |
2312 | mutex_unlock(&dev->struct_mutex); |
- | |
2313 | return NULL; |
2315 | return NULL; |
2314 | } |
2316 | } |
2315 | 2317 | ||
2316 | /** |
2318 | /** |
2317 | * Lock protecting IPS related data structures |
2319 | * Lock protecting IPS related data structures |
2318 | */ |
2320 | */ |
2319 | DEFINE_SPINLOCK(mchdev_lock); |
2321 | DEFINE_SPINLOCK(mchdev_lock); |
2320 | 2322 | ||
2321 | /* Global for IPS driver to get at the current i915 device. Protected by |
2323 | /* Global for IPS driver to get at the current i915 device. Protected by |
2322 | * mchdev_lock. */ |
2324 | * mchdev_lock. */ |
2323 | static struct drm_i915_private *i915_mch_dev; |
2325 | static struct drm_i915_private *i915_mch_dev; |
2324 | 2326 | ||
2325 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2327 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2326 | { |
2328 | { |
2327 | struct drm_i915_private *dev_priv = dev->dev_private; |
2329 | struct drm_i915_private *dev_priv = dev->dev_private; |
2328 | u16 rgvswctl; |
2330 | u16 rgvswctl; |
2329 | 2331 | ||
2330 | assert_spin_locked(&mchdev_lock); |
2332 | assert_spin_locked(&mchdev_lock); |
2331 | 2333 | ||
2332 | rgvswctl = I915_READ16(MEMSWCTL); |
2334 | rgvswctl = I915_READ16(MEMSWCTL); |
2333 | if (rgvswctl & MEMCTL_CMD_STS) { |
2335 | if (rgvswctl & MEMCTL_CMD_STS) { |
2334 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
2336 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
2335 | return false; /* still busy with another command */ |
2337 | return false; /* still busy with another command */ |
2336 | } |
2338 | } |
2337 | 2339 | ||
2338 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
2340 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
2339 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
2341 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
2340 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2342 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2341 | POSTING_READ16(MEMSWCTL); |
2343 | POSTING_READ16(MEMSWCTL); |
2342 | 2344 | ||
2343 | rgvswctl |= MEMCTL_CMD_STS; |
2345 | rgvswctl |= MEMCTL_CMD_STS; |
2344 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2346 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2345 | 2347 | ||
2346 | return true; |
2348 | return true; |
2347 | } |
2349 | } |
2348 | 2350 | ||
2349 | static void ironlake_enable_drps(struct drm_device *dev) |
2351 | static void ironlake_enable_drps(struct drm_device *dev) |
2350 | { |
2352 | { |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; |
2353 | struct drm_i915_private *dev_priv = dev->dev_private; |
2352 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
2354 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
2353 | u8 fmax, fmin, fstart, vstart; |
2355 | u8 fmax, fmin, fstart, vstart; |
2354 | 2356 | ||
2355 | spin_lock_irq(&mchdev_lock); |
2357 | spin_lock_irq(&mchdev_lock); |
2356 | 2358 | ||
2357 | /* Enable temp reporting */ |
2359 | /* Enable temp reporting */ |
2358 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
2360 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
2359 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
2361 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
2360 | 2362 | ||
2361 | /* 100ms RC evaluation intervals */ |
2363 | /* 100ms RC evaluation intervals */ |
2362 | I915_WRITE(RCUPEI, 100000); |
2364 | I915_WRITE(RCUPEI, 100000); |
2363 | I915_WRITE(RCDNEI, 100000); |
2365 | I915_WRITE(RCDNEI, 100000); |
2364 | 2366 | ||
2365 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
2367 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
2366 | I915_WRITE(RCBMAXAVG, 90000); |
2368 | I915_WRITE(RCBMAXAVG, 90000); |
2367 | I915_WRITE(RCBMINAVG, 80000); |
2369 | I915_WRITE(RCBMINAVG, 80000); |
2368 | 2370 | ||
2369 | I915_WRITE(MEMIHYST, 1); |
2371 | I915_WRITE(MEMIHYST, 1); |
2370 | 2372 | ||
2371 | /* Set up min, max, and cur for interrupt handling */ |
2373 | /* Set up min, max, and cur for interrupt handling */ |
2372 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
2374 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
2373 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
2375 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
2374 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
2376 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
2375 | MEMMODE_FSTART_SHIFT; |
2377 | MEMMODE_FSTART_SHIFT; |
2376 | 2378 | ||
2377 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
2379 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
2378 | PXVFREQ_PX_SHIFT; |
2380 | PXVFREQ_PX_SHIFT; |
2379 | 2381 | ||
2380 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2382 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2381 | dev_priv->ips.fstart = fstart; |
2383 | dev_priv->ips.fstart = fstart; |
2382 | 2384 | ||
2383 | dev_priv->ips.max_delay = fstart; |
2385 | dev_priv->ips.max_delay = fstart; |
2384 | dev_priv->ips.min_delay = fmin; |
2386 | dev_priv->ips.min_delay = fmin; |
2385 | dev_priv->ips.cur_delay = fstart; |
2387 | dev_priv->ips.cur_delay = fstart; |
2386 | 2388 | ||
2387 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
2389 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
2388 | fmax, fmin, fstart); |
2390 | fmax, fmin, fstart); |
2389 | 2391 | ||
2390 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
2392 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
2391 | 2393 | ||
2392 | /* |
2394 | /* |
2393 | * Interrupts will be enabled in ironlake_irq_postinstall |
2395 | * Interrupts will be enabled in ironlake_irq_postinstall |
2394 | */ |
2396 | */ |
2395 | 2397 | ||
2396 | I915_WRITE(VIDSTART, vstart); |
2398 | I915_WRITE(VIDSTART, vstart); |
2397 | POSTING_READ(VIDSTART); |
2399 | POSTING_READ(VIDSTART); |
2398 | 2400 | ||
2399 | rgvmodectl |= MEMMODE_SWMODE_EN; |
2401 | rgvmodectl |= MEMMODE_SWMODE_EN; |
2400 | I915_WRITE(MEMMODECTL, rgvmodectl); |
2402 | I915_WRITE(MEMMODECTL, rgvmodectl); |
2401 | 2403 | ||
2402 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2404 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2403 | DRM_ERROR("stuck trying to change perf mode\n"); |
2405 | DRM_ERROR("stuck trying to change perf mode\n"); |
2404 | mdelay(1); |
2406 | mdelay(1); |
2405 | 2407 | ||
2406 | ironlake_set_drps(dev, fstart); |
2408 | ironlake_set_drps(dev, fstart); |
2407 | 2409 | ||
2408 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2410 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2409 | I915_READ(0x112e0); |
2411 | I915_READ(0x112e0); |
2410 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2412 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2411 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
2413 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
2412 | // getrawmonotonic(&dev_priv->ips.last_time2); |
2414 | // getrawmonotonic(&dev_priv->ips.last_time2); |
2413 | 2415 | ||
2414 | spin_unlock_irq(&mchdev_lock); |
2416 | spin_unlock_irq(&mchdev_lock); |
2415 | } |
2417 | } |
2416 | 2418 | ||
2417 | static void ironlake_disable_drps(struct drm_device *dev) |
2419 | static void ironlake_disable_drps(struct drm_device *dev) |
2418 | { |
2420 | { |
2419 | struct drm_i915_private *dev_priv = dev->dev_private; |
2421 | struct drm_i915_private *dev_priv = dev->dev_private; |
2420 | u16 rgvswctl; |
2422 | u16 rgvswctl; |
2421 | 2423 | ||
2422 | spin_lock_irq(&mchdev_lock); |
2424 | spin_lock_irq(&mchdev_lock); |
2423 | 2425 | ||
2424 | rgvswctl = I915_READ16(MEMSWCTL); |
2426 | rgvswctl = I915_READ16(MEMSWCTL); |
2425 | 2427 | ||
2426 | /* Ack interrupts, disable EFC interrupt */ |
2428 | /* Ack interrupts, disable EFC interrupt */ |
2427 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
2429 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
2428 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
2430 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
2429 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
2431 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
2430 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
2432 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
2431 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
2433 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
2432 | 2434 | ||
2433 | /* Go back to the starting frequency */ |
2435 | /* Go back to the starting frequency */ |
2434 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
2436 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
2435 | mdelay(1); |
2437 | mdelay(1); |
2436 | rgvswctl |= MEMCTL_CMD_STS; |
2438 | rgvswctl |= MEMCTL_CMD_STS; |
2437 | I915_WRITE(MEMSWCTL, rgvswctl); |
2439 | I915_WRITE(MEMSWCTL, rgvswctl); |
2438 | mdelay(1); |
2440 | mdelay(1); |
2439 | 2441 | ||
2440 | spin_unlock_irq(&mchdev_lock); |
2442 | spin_unlock_irq(&mchdev_lock); |
2441 | } |
2443 | } |
2442 | 2444 | ||
2443 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2445 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2444 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
2446 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
2445 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
2447 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
2446 | * all limits and the gpu stuck at whatever frequency it is at atm). |
2448 | * all limits and the gpu stuck at whatever frequency it is at atm). |
2447 | */ |
2449 | */ |
2448 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
2450 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
2449 | { |
2451 | { |
2450 | u32 limits; |
2452 | u32 limits; |
2451 | 2453 | ||
2452 | limits = 0; |
2454 | limits = 0; |
2453 | 2455 | ||
2454 | if (*val >= dev_priv->rps.max_delay) |
2456 | if (*val >= dev_priv->rps.max_delay) |
2455 | *val = dev_priv->rps.max_delay; |
2457 | *val = dev_priv->rps.max_delay; |
2456 | limits |= dev_priv->rps.max_delay << 24; |
2458 | limits |= dev_priv->rps.max_delay << 24; |
2457 | 2459 | ||
2458 | /* Only set the down limit when we've reached the lowest level to avoid |
2460 | /* Only set the down limit when we've reached the lowest level to avoid |
2459 | * getting more interrupts, otherwise leave this clear. This prevents a |
2461 | * getting more interrupts, otherwise leave this clear. This prevents a |
2460 | * race in the hw when coming out of rc6: There's a tiny window where |
2462 | * race in the hw when coming out of rc6: There's a tiny window where |
2461 | * the hw runs at the minimal clock before selecting the desired |
2463 | * the hw runs at the minimal clock before selecting the desired |
2462 | * frequency, if the down threshold expires in that window we will not |
2464 | * frequency, if the down threshold expires in that window we will not |
2463 | * receive a down interrupt. */ |
2465 | * receive a down interrupt. */ |
2464 | if (*val <= dev_priv->rps.min_delay) { |
2466 | if (*val <= dev_priv->rps.min_delay) { |
2465 | *val = dev_priv->rps.min_delay; |
2467 | *val = dev_priv->rps.min_delay; |
2466 | limits |= dev_priv->rps.min_delay << 16; |
2468 | limits |= dev_priv->rps.min_delay << 16; |
2467 | } |
2469 | } |
2468 | 2470 | ||
2469 | return limits; |
2471 | return limits; |
2470 | } |
2472 | } |
2471 | 2473 | ||
2472 | void gen6_set_rps(struct drm_device *dev, u8 val) |
2474 | void gen6_set_rps(struct drm_device *dev, u8 val) |
2473 | { |
2475 | { |
2474 | struct drm_i915_private *dev_priv = dev->dev_private; |
2476 | struct drm_i915_private *dev_priv = dev->dev_private; |
2475 | u32 limits = gen6_rps_limits(dev_priv, &val); |
2477 | u32 limits = gen6_rps_limits(dev_priv, &val); |
2476 | 2478 | ||
2477 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2479 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2478 | WARN_ON(val > dev_priv->rps.max_delay); |
2480 | WARN_ON(val > dev_priv->rps.max_delay); |
2479 | WARN_ON(val < dev_priv->rps.min_delay); |
2481 | WARN_ON(val < dev_priv->rps.min_delay); |
2480 | 2482 | ||
2481 | if (val == dev_priv->rps.cur_delay) |
2483 | if (val == dev_priv->rps.cur_delay) |
2482 | return; |
2484 | return; |
2483 | 2485 | ||
2484 | I915_WRITE(GEN6_RPNSWREQ, |
2486 | I915_WRITE(GEN6_RPNSWREQ, |
2485 | GEN6_FREQUENCY(val) | |
2487 | GEN6_FREQUENCY(val) | |
2486 | GEN6_OFFSET(0) | |
2488 | GEN6_OFFSET(0) | |
2487 | GEN6_AGGRESSIVE_TURBO); |
2489 | GEN6_AGGRESSIVE_TURBO); |
2488 | 2490 | ||
2489 | /* Make sure we continue to get interrupts |
2491 | /* Make sure we continue to get interrupts |
2490 | * until we hit the minimum or maximum frequencies. |
2492 | * until we hit the minimum or maximum frequencies. |
2491 | */ |
2493 | */ |
2492 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
2494 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
2493 | 2495 | ||
2494 | POSTING_READ(GEN6_RPNSWREQ); |
2496 | POSTING_READ(GEN6_RPNSWREQ); |
2495 | 2497 | ||
2496 | dev_priv->rps.cur_delay = val; |
2498 | dev_priv->rps.cur_delay = val; |
2497 | 2499 | ||
2498 | trace_intel_gpu_freq_change(val * 50); |
2500 | trace_intel_gpu_freq_change(val * 50); |
2499 | } |
2501 | } |
2500 | 2502 | ||
2501 | static void gen6_disable_rps(struct drm_device *dev) |
2503 | static void gen6_disable_rps(struct drm_device *dev) |
2502 | { |
2504 | { |
2503 | struct drm_i915_private *dev_priv = dev->dev_private; |
2505 | struct drm_i915_private *dev_priv = dev->dev_private; |
2504 | 2506 | ||
2505 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2507 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2506 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2508 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2507 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
2509 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
2508 | I915_WRITE(GEN6_PMIER, 0); |
2510 | I915_WRITE(GEN6_PMIER, 0); |
2509 | /* Complete PM interrupt masking here doesn't race with the rps work |
2511 | /* Complete PM interrupt masking here doesn't race with the rps work |
2510 | * item again unmasking PM interrupts because that is using a different |
2512 | * item again unmasking PM interrupts because that is using a different |
2511 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
2513 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
2512 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
2514 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
2513 | 2515 | ||
2514 | spin_lock_irq(&dev_priv->rps.lock); |
2516 | spin_lock_irq(&dev_priv->rps.lock); |
2515 | dev_priv->rps.pm_iir = 0; |
2517 | dev_priv->rps.pm_iir = 0; |
2516 | spin_unlock_irq(&dev_priv->rps.lock); |
2518 | spin_unlock_irq(&dev_priv->rps.lock); |
2517 | 2519 | ||
2518 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
2520 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
2519 | } |
2521 | } |
2520 | 2522 | ||
2521 | int intel_enable_rc6(const struct drm_device *dev) |
2523 | int intel_enable_rc6(const struct drm_device *dev) |
2522 | { |
2524 | { |
2523 | /* Respect the kernel parameter if it is set */ |
2525 | /* Respect the kernel parameter if it is set */ |
2524 | if (i915_enable_rc6 >= 0) |
2526 | if (i915_enable_rc6 >= 0) |
2525 | return i915_enable_rc6; |
2527 | return i915_enable_rc6; |
2526 | 2528 | ||
2527 | /* Disable RC6 on Ironlake */ |
2529 | /* Disable RC6 on Ironlake */ |
2528 | if (INTEL_INFO(dev)->gen == 5) |
2530 | if (INTEL_INFO(dev)->gen == 5) |
2529 | return 0; |
2531 | return 0; |
2530 | 2532 | ||
2531 | if (IS_HASWELL(dev)) { |
2533 | if (IS_HASWELL(dev)) { |
2532 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
2534 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
2533 | return INTEL_RC6_ENABLE; |
2535 | return INTEL_RC6_ENABLE; |
2534 | } |
2536 | } |
2535 | 2537 | ||
2536 | /* snb/ivb have more than one rc6 state. */ |
2538 | /* snb/ivb have more than one rc6 state. */ |
2537 | if (INTEL_INFO(dev)->gen == 6) { |
2539 | if (INTEL_INFO(dev)->gen == 6) { |
2538 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
2540 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
2539 | return INTEL_RC6_ENABLE; |
2541 | return INTEL_RC6_ENABLE; |
2540 | } |
2542 | } |
2541 | 2543 | ||
2542 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
2544 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
2543 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
2545 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
2544 | } |
2546 | } |
2545 | 2547 | ||
2546 | static void gen6_enable_rps(struct drm_device *dev) |
2548 | static void gen6_enable_rps(struct drm_device *dev) |
2547 | { |
2549 | { |
2548 | struct drm_i915_private *dev_priv = dev->dev_private; |
2550 | struct drm_i915_private *dev_priv = dev->dev_private; |
2549 | struct intel_ring_buffer *ring; |
2551 | struct intel_ring_buffer *ring; |
2550 | u32 rp_state_cap; |
2552 | u32 rp_state_cap; |
2551 | u32 gt_perf_status; |
2553 | u32 gt_perf_status; |
2552 | u32 rc6vids, pcu_mbox, rc6_mask = 0; |
2554 | u32 rc6vids, pcu_mbox, rc6_mask = 0; |
2553 | u32 gtfifodbg; |
2555 | u32 gtfifodbg; |
2554 | int rc6_mode; |
2556 | int rc6_mode; |
2555 | int i, ret; |
2557 | int i, ret; |
2556 | 2558 | ||
2557 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2559 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2558 | 2560 | ||
2559 | /* Here begins a magic sequence of register writes to enable |
2561 | /* Here begins a magic sequence of register writes to enable |
2560 | * auto-downclocking. |
2562 | * auto-downclocking. |
2561 | * |
2563 | * |
2562 | * Perhaps there might be some value in exposing these to |
2564 | * Perhaps there might be some value in exposing these to |
2563 | * userspace... |
2565 | * userspace... |
2564 | */ |
2566 | */ |
2565 | I915_WRITE(GEN6_RC_STATE, 0); |
2567 | I915_WRITE(GEN6_RC_STATE, 0); |
2566 | 2568 | ||
2567 | /* Clear the DBG now so we don't confuse earlier errors */ |
2569 | /* Clear the DBG now so we don't confuse earlier errors */ |
2568 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
2570 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
2569 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
2571 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
2570 | I915_WRITE(GTFIFODBG, gtfifodbg); |
2572 | I915_WRITE(GTFIFODBG, gtfifodbg); |
2571 | } |
2573 | } |
2572 | 2574 | ||
2573 | gen6_gt_force_wake_get(dev_priv); |
2575 | gen6_gt_force_wake_get(dev_priv); |
2574 | 2576 | ||
2575 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
2577 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
2576 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
2578 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
2577 | 2579 | ||
2578 | /* In units of 100MHz */ |
2580 | /* In units of 100MHz */ |
2579 | dev_priv->rps.max_delay = rp_state_cap & 0xff; |
2581 | dev_priv->rps.max_delay = rp_state_cap & 0xff; |
2580 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
2582 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
2581 | dev_priv->rps.cur_delay = 0; |
2583 | dev_priv->rps.cur_delay = 0; |
2582 | 2584 | ||
2583 | /* disable the counters and set deterministic thresholds */ |
2585 | /* disable the counters and set deterministic thresholds */ |
2584 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2586 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2585 | 2587 | ||
2586 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
2588 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
2587 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
2589 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
2588 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
2590 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
2589 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
2591 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
2590 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
2592 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
2591 | 2593 | ||
2592 | for_each_ring(ring, dev_priv, i) |
2594 | for_each_ring(ring, dev_priv, i) |
2593 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
2595 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
2594 | 2596 | ||
2595 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2597 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2596 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2598 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2597 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2599 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2598 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
2600 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2599 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2601 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2600 | 2602 | ||
2601 | /* Check if we are enabling RC6 */ |
2603 | /* Check if we are enabling RC6 */ |
2602 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
2604 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
2603 | if (rc6_mode & INTEL_RC6_ENABLE) |
2605 | if (rc6_mode & INTEL_RC6_ENABLE) |
2604 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
2606 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
2605 | 2607 | ||
2606 | /* We don't use those on Haswell */ |
2608 | /* We don't use those on Haswell */ |
2607 | if (!IS_HASWELL(dev)) { |
2609 | if (!IS_HASWELL(dev)) { |
2608 | if (rc6_mode & INTEL_RC6p_ENABLE) |
2610 | if (rc6_mode & INTEL_RC6p_ENABLE) |
2609 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
2611 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
2610 | 2612 | ||
2611 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
2613 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
2612 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
2614 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
2613 | } |
2615 | } |
2614 | 2616 | ||
2615 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
2617 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
2616 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
2618 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
2617 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
2619 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
2618 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
2620 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
2619 | 2621 | ||
2620 | I915_WRITE(GEN6_RC_CONTROL, |
2622 | I915_WRITE(GEN6_RC_CONTROL, |
2621 | rc6_mask | |
2623 | rc6_mask | |
2622 | GEN6_RC_CTL_EI_MODE(1) | |
2624 | GEN6_RC_CTL_EI_MODE(1) | |
2623 | GEN6_RC_CTL_HW_ENABLE); |
2625 | GEN6_RC_CTL_HW_ENABLE); |
2624 | 2626 | ||
2625 | I915_WRITE(GEN6_RPNSWREQ, |
2627 | I915_WRITE(GEN6_RPNSWREQ, |
2626 | GEN6_FREQUENCY(10) | |
2628 | GEN6_FREQUENCY(10) | |
2627 | GEN6_OFFSET(0) | |
2629 | GEN6_OFFSET(0) | |
2628 | GEN6_AGGRESSIVE_TURBO); |
2630 | GEN6_AGGRESSIVE_TURBO); |
2629 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
2631 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
2630 | GEN6_FREQUENCY(12)); |
2632 | GEN6_FREQUENCY(12)); |
2631 | 2633 | ||
2632 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2634 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2633 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
2635 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
2634 | dev_priv->rps.max_delay << 24 | |
2636 | dev_priv->rps.max_delay << 24 | |
2635 | dev_priv->rps.min_delay << 16); |
2637 | dev_priv->rps.min_delay << 16); |
2636 | 2638 | ||
2637 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
2639 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
2638 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
2640 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
2639 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
2641 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
2640 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
2642 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
2641 | 2643 | ||
2642 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2644 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2643 | I915_WRITE(GEN6_RP_CONTROL, |
2645 | I915_WRITE(GEN6_RP_CONTROL, |
2644 | GEN6_RP_MEDIA_TURBO | |
2646 | GEN6_RP_MEDIA_TURBO | |
2645 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
2647 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
2646 | GEN6_RP_MEDIA_IS_GFX | |
2648 | GEN6_RP_MEDIA_IS_GFX | |
2647 | GEN6_RP_ENABLE | |
2649 | GEN6_RP_ENABLE | |
2648 | GEN6_RP_UP_BUSY_AVG | |
2650 | GEN6_RP_UP_BUSY_AVG | |
2649 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
2651 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
2650 | 2652 | ||
2651 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
2653 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
2652 | if (!ret) { |
2654 | if (!ret) { |
2653 | pcu_mbox = 0; |
2655 | pcu_mbox = 0; |
2654 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
2656 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
2655 | if (ret && pcu_mbox & (1<<31)) { /* OC supported */ |
2657 | if (ret && pcu_mbox & (1<<31)) { /* OC supported */ |
2656 | dev_priv->rps.max_delay = pcu_mbox & 0xff; |
2658 | dev_priv->rps.max_delay = pcu_mbox & 0xff; |
2657 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
2659 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
2658 | } |
2660 | } |
2659 | } else { |
2661 | } else { |
2660 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
2662 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
2661 | } |
2663 | } |
2662 | 2664 | ||
2663 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
2665 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
2664 | 2666 | ||
2665 | /* requires MSI enabled */ |
2667 | /* requires MSI enabled */ |
2666 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
2668 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
2667 | spin_lock_irq(&dev_priv->rps.lock); |
2669 | spin_lock_irq(&dev_priv->rps.lock); |
2668 | WARN_ON(dev_priv->rps.pm_iir != 0); |
2670 | WARN_ON(dev_priv->rps.pm_iir != 0); |
2669 | I915_WRITE(GEN6_PMIMR, 0); |
2671 | I915_WRITE(GEN6_PMIMR, 0); |
2670 | spin_unlock_irq(&dev_priv->rps.lock); |
2672 | spin_unlock_irq(&dev_priv->rps.lock); |
2671 | /* enable all PM interrupts */ |
2673 | /* enable all PM interrupts */ |
2672 | I915_WRITE(GEN6_PMINTRMSK, 0); |
2674 | I915_WRITE(GEN6_PMINTRMSK, 0); |
2673 | 2675 | ||
2674 | rc6vids = 0; |
2676 | rc6vids = 0; |
2675 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
2677 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
2676 | if (IS_GEN6(dev) && ret) { |
2678 | if (IS_GEN6(dev) && ret) { |
2677 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
2679 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
2678 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
2680 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
2679 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
2681 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
2680 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
2682 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
2681 | rc6vids &= 0xffff00; |
2683 | rc6vids &= 0xffff00; |
2682 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
2684 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
2683 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
2685 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
2684 | if (ret) |
2686 | if (ret) |
2685 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
2687 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
2686 | } |
2688 | } |
2687 | 2689 | ||
2688 | gen6_gt_force_wake_put(dev_priv); |
2690 | gen6_gt_force_wake_put(dev_priv); |
2689 | } |
2691 | } |
2690 | 2692 | ||
2691 | #if 0 |
2693 | #if 0 |
2692 | static void gen6_update_ring_freq(struct drm_device *dev) |
2694 | static void gen6_update_ring_freq(struct drm_device *dev) |
2693 | { |
2695 | { |
2694 | struct drm_i915_private *dev_priv = dev->dev_private; |
2696 | struct drm_i915_private *dev_priv = dev->dev_private; |
2695 | int min_freq = 15; |
2697 | int min_freq = 15; |
2696 | int gpu_freq; |
2698 | int gpu_freq; |
2697 | unsigned int ia_freq, max_ia_freq; |
2699 | unsigned int ia_freq, max_ia_freq; |
2698 | int scaling_factor = 180; |
2700 | int scaling_factor = 180; |
2699 | 2701 | ||
2700 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2702 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2701 | 2703 | ||
2702 | max_ia_freq = cpufreq_quick_get_max(0); |
2704 | max_ia_freq = cpufreq_quick_get_max(0); |
2703 | /* |
2705 | /* |
2704 | * Default to measured freq if none found, PCU will ensure we don't go |
2706 | * Default to measured freq if none found, PCU will ensure we don't go |
2705 | * over |
2707 | * over |
2706 | */ |
2708 | */ |
2707 | if (!max_ia_freq) |
2709 | if (!max_ia_freq) |
2708 | max_ia_freq = tsc_khz; |
2710 | max_ia_freq = tsc_khz; |
2709 | 2711 | ||
2710 | /* Convert from kHz to MHz */ |
2712 | /* Convert from kHz to MHz */ |
2711 | max_ia_freq /= 1000; |
2713 | max_ia_freq /= 1000; |
2712 | 2714 | ||
2713 | /* |
2715 | /* |
2714 | * For each potential GPU frequency, load a ring frequency we'd like |
2716 | * For each potential GPU frequency, load a ring frequency we'd like |
2715 | * to use for memory access. We do this by specifying the IA frequency |
2717 | * to use for memory access. We do this by specifying the IA frequency |
2716 | * the PCU should use as a reference to determine the ring frequency. |
2718 | * the PCU should use as a reference to determine the ring frequency. |
2717 | */ |
2719 | */ |
2718 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
2720 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
2719 | gpu_freq--) { |
2721 | gpu_freq--) { |
2720 | int diff = dev_priv->rps.max_delay - gpu_freq; |
2722 | int diff = dev_priv->rps.max_delay - gpu_freq; |
2721 | 2723 | ||
2722 | /* |
2724 | /* |
2723 | * For GPU frequencies less than 750MHz, just use the lowest |
2725 | * For GPU frequencies less than 750MHz, just use the lowest |
2724 | * ring freq. |
2726 | * ring freq. |
2725 | */ |
2727 | */ |
2726 | if (gpu_freq < min_freq) |
2728 | if (gpu_freq < min_freq) |
2727 | ia_freq = 800; |
2729 | ia_freq = 800; |
2728 | else |
2730 | else |
2729 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
2731 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
2730 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
2732 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
2731 | ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; |
2733 | ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; |
2732 | 2734 | ||
2733 | sandybridge_pcode_write(dev_priv, |
2735 | sandybridge_pcode_write(dev_priv, |
2734 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
2736 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
2735 | ia_freq | gpu_freq); |
2737 | ia_freq | gpu_freq); |
2736 | } |
2738 | } |
2737 | } |
2739 | } |
2738 | #endif |
2740 | #endif |
2739 | 2741 | ||
2740 | void ironlake_teardown_rc6(struct drm_device *dev) |
2742 | void ironlake_teardown_rc6(struct drm_device *dev) |
2741 | { |
2743 | { |
2742 | struct drm_i915_private *dev_priv = dev->dev_private; |
2744 | struct drm_i915_private *dev_priv = dev->dev_private; |
2743 | 2745 | ||
2744 | if (dev_priv->ips.renderctx) { |
2746 | if (dev_priv->ips.renderctx) { |
2745 | i915_gem_object_unpin(dev_priv->ips.renderctx); |
2747 | i915_gem_object_unpin(dev_priv->ips.renderctx); |
2746 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
2748 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
2747 | dev_priv->ips.renderctx = NULL; |
2749 | dev_priv->ips.renderctx = NULL; |
2748 | } |
2750 | } |
2749 | 2751 | ||
2750 | if (dev_priv->ips.pwrctx) { |
2752 | if (dev_priv->ips.pwrctx) { |
2751 | i915_gem_object_unpin(dev_priv->ips.pwrctx); |
2753 | i915_gem_object_unpin(dev_priv->ips.pwrctx); |
2752 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
2754 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
2753 | dev_priv->ips.pwrctx = NULL; |
2755 | dev_priv->ips.pwrctx = NULL; |
2754 | } |
2756 | } |
2755 | } |
2757 | } |
2756 | 2758 | ||
2757 | static void ironlake_disable_rc6(struct drm_device *dev) |
2759 | static void ironlake_disable_rc6(struct drm_device *dev) |
2758 | { |
2760 | { |
2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
2761 | struct drm_i915_private *dev_priv = dev->dev_private; |
2760 | 2762 | ||
2761 | if (I915_READ(PWRCTXA)) { |
2763 | if (I915_READ(PWRCTXA)) { |
2762 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
2764 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
2763 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
2765 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
2764 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
2766 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
2765 | 50); |
2767 | 50); |
2766 | 2768 | ||
2767 | I915_WRITE(PWRCTXA, 0); |
2769 | I915_WRITE(PWRCTXA, 0); |
2768 | POSTING_READ(PWRCTXA); |
2770 | POSTING_READ(PWRCTXA); |
2769 | 2771 | ||
2770 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2772 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2771 | POSTING_READ(RSTDBYCTL); |
2773 | POSTING_READ(RSTDBYCTL); |
2772 | } |
2774 | } |
2773 | } |
2775 | } |
2774 | 2776 | ||
2775 | static int ironlake_setup_rc6(struct drm_device *dev) |
2777 | static int ironlake_setup_rc6(struct drm_device *dev) |
2776 | { |
2778 | { |
2777 | struct drm_i915_private *dev_priv = dev->dev_private; |
2779 | struct drm_i915_private *dev_priv = dev->dev_private; |
2778 | 2780 | ||
2779 | if (dev_priv->ips.renderctx == NULL) |
2781 | if (dev_priv->ips.renderctx == NULL) |
2780 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
2782 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
2781 | if (!dev_priv->ips.renderctx) |
2783 | if (!dev_priv->ips.renderctx) |
2782 | return -ENOMEM; |
2784 | return -ENOMEM; |
2783 | 2785 | ||
2784 | if (dev_priv->ips.pwrctx == NULL) |
2786 | if (dev_priv->ips.pwrctx == NULL) |
2785 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
2787 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
2786 | if (!dev_priv->ips.pwrctx) { |
2788 | if (!dev_priv->ips.pwrctx) { |
2787 | ironlake_teardown_rc6(dev); |
2789 | ironlake_teardown_rc6(dev); |
2788 | return -ENOMEM; |
2790 | return -ENOMEM; |
2789 | } |
2791 | } |
2790 | 2792 | ||
2791 | return 0; |
2793 | return 0; |
2792 | } |
2794 | } |
2793 | 2795 | ||
2794 | static void ironlake_enable_rc6(struct drm_device *dev) |
2796 | static void ironlake_enable_rc6(struct drm_device *dev) |
2795 | { |
2797 | { |
2796 | struct drm_i915_private *dev_priv = dev->dev_private; |
2798 | struct drm_i915_private *dev_priv = dev->dev_private; |
2797 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
2799 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
2798 | bool was_interruptible; |
2800 | bool was_interruptible; |
2799 | int ret; |
2801 | int ret; |
2800 | 2802 | ||
2801 | /* rc6 disabled by default due to repeated reports of hanging during |
2803 | /* rc6 disabled by default due to repeated reports of hanging during |
2802 | * boot and resume. |
2804 | * boot and resume. |
2803 | */ |
2805 | */ |
2804 | if (!intel_enable_rc6(dev)) |
2806 | if (!intel_enable_rc6(dev)) |
2805 | return; |
2807 | return; |
2806 | 2808 | ||
2807 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2809 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2808 | 2810 | ||
2809 | ret = ironlake_setup_rc6(dev); |
2811 | ret = ironlake_setup_rc6(dev); |
2810 | if (ret) |
2812 | if (ret) |
2811 | return; |
2813 | return; |
2812 | 2814 | ||
2813 | was_interruptible = dev_priv->mm.interruptible; |
2815 | was_interruptible = dev_priv->mm.interruptible; |
2814 | dev_priv->mm.interruptible = false; |
2816 | dev_priv->mm.interruptible = false; |
2815 | 2817 | ||
2816 | /* |
2818 | /* |
2817 | * GPU can automatically power down the render unit if given a page |
2819 | * GPU can automatically power down the render unit if given a page |
2818 | * to save state. |
2820 | * to save state. |
2819 | */ |
2821 | */ |
2820 | ret = intel_ring_begin(ring, 6); |
2822 | ret = intel_ring_begin(ring, 6); |
2821 | if (ret) { |
2823 | if (ret) { |
2822 | ironlake_teardown_rc6(dev); |
2824 | ironlake_teardown_rc6(dev); |
2823 | dev_priv->mm.interruptible = was_interruptible; |
2825 | dev_priv->mm.interruptible = was_interruptible; |
2824 | return; |
2826 | return; |
2825 | } |
2827 | } |
2826 | 2828 | ||
2827 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
2829 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
2828 | intel_ring_emit(ring, MI_SET_CONTEXT); |
2830 | intel_ring_emit(ring, MI_SET_CONTEXT); |
2829 | intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | |
2831 | intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | |
2830 | MI_MM_SPACE_GTT | |
2832 | MI_MM_SPACE_GTT | |
2831 | MI_SAVE_EXT_STATE_EN | |
2833 | MI_SAVE_EXT_STATE_EN | |
2832 | MI_RESTORE_EXT_STATE_EN | |
2834 | MI_RESTORE_EXT_STATE_EN | |
2833 | MI_RESTORE_INHIBIT); |
2835 | MI_RESTORE_INHIBIT); |
2834 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
2836 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
2835 | intel_ring_emit(ring, MI_NOOP); |
2837 | intel_ring_emit(ring, MI_NOOP); |
2836 | intel_ring_emit(ring, MI_FLUSH); |
2838 | intel_ring_emit(ring, MI_FLUSH); |
2837 | intel_ring_advance(ring); |
2839 | intel_ring_advance(ring); |
2838 | 2840 | ||
2839 | /* |
2841 | /* |
2840 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
2842 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
2841 | * does an implicit flush, combined with MI_FLUSH above, it should be |
2843 | * does an implicit flush, combined with MI_FLUSH above, it should be |
2842 | * safe to assume that renderctx is valid |
2844 | * safe to assume that renderctx is valid |
2843 | */ |
2845 | */ |
2844 | ret = intel_ring_idle(ring); |
2846 | ret = intel_ring_idle(ring); |
2845 | dev_priv->mm.interruptible = was_interruptible; |
2847 | dev_priv->mm.interruptible = was_interruptible; |
2846 | if (ret) { |
2848 | if (ret) { |
2847 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
2849 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
2848 | ironlake_teardown_rc6(dev); |
2850 | ironlake_teardown_rc6(dev); |
2849 | return; |
2851 | return; |
2850 | } |
2852 | } |
2851 | 2853 | ||
2852 | I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); |
2854 | I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); |
2853 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2855 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2854 | } |
2856 | } |
2855 | 2857 | ||
2856 | static unsigned long intel_pxfreq(u32 vidfreq) |
2858 | static unsigned long intel_pxfreq(u32 vidfreq) |
2857 | { |
2859 | { |
2858 | unsigned long freq; |
2860 | unsigned long freq; |
2859 | int div = (vidfreq & 0x3f0000) >> 16; |
2861 | int div = (vidfreq & 0x3f0000) >> 16; |
2860 | int post = (vidfreq & 0x3000) >> 12; |
2862 | int post = (vidfreq & 0x3000) >> 12; |
2861 | int pre = (vidfreq & 0x7); |
2863 | int pre = (vidfreq & 0x7); |
2862 | 2864 | ||
2863 | if (!pre) |
2865 | if (!pre) |
2864 | return 0; |
2866 | return 0; |
2865 | 2867 | ||
2866 | freq = ((div * 133333) / ((1< |
2868 | freq = ((div * 133333) / ((1< |
2867 | 2869 | ||
2868 | return freq; |
2870 | return freq; |
2869 | } |
2871 | } |
2870 | 2872 | ||
2871 | static const struct cparams { |
2873 | static const struct cparams { |
2872 | u16 i; |
2874 | u16 i; |
2873 | u16 t; |
2875 | u16 t; |
2874 | u16 m; |
2876 | u16 m; |
2875 | u16 c; |
2877 | u16 c; |
2876 | } cparams[] = { |
2878 | } cparams[] = { |
2877 | { 1, 1333, 301, 28664 }, |
2879 | { 1, 1333, 301, 28664 }, |
2878 | { 1, 1066, 294, 24460 }, |
2880 | { 1, 1066, 294, 24460 }, |
2879 | { 1, 800, 294, 25192 }, |
2881 | { 1, 800, 294, 25192 }, |
2880 | { 0, 1333, 276, 27605 }, |
2882 | { 0, 1333, 276, 27605 }, |
2881 | { 0, 1066, 276, 27605 }, |
2883 | { 0, 1066, 276, 27605 }, |
2882 | { 0, 800, 231, 23784 }, |
2884 | { 0, 800, 231, 23784 }, |
2883 | }; |
2885 | }; |
2884 | 2886 | ||
2885 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
2887 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
2886 | { |
2888 | { |
2887 | u64 total_count, diff, ret; |
2889 | u64 total_count, diff, ret; |
2888 | u32 count1, count2, count3, m = 0, c = 0; |
2890 | u32 count1, count2, count3, m = 0, c = 0; |
2889 | unsigned long now = jiffies_to_msecs(GetTimerTicks()), diff1; |
2891 | unsigned long now = jiffies_to_msecs(GetTimerTicks()), diff1; |
2890 | int i; |
2892 | int i; |
2891 | 2893 | ||
2892 | assert_spin_locked(&mchdev_lock); |
2894 | assert_spin_locked(&mchdev_lock); |
2893 | 2895 | ||
2894 | diff1 = now - dev_priv->ips.last_time1; |
2896 | diff1 = now - dev_priv->ips.last_time1; |
2895 | 2897 | ||
2896 | /* Prevent division-by-zero if we are asking too fast. |
2898 | /* Prevent division-by-zero if we are asking too fast. |
2897 | * Also, we don't get interesting results if we are polling |
2899 | * Also, we don't get interesting results if we are polling |
2898 | * faster than once in 10ms, so just return the saved value |
2900 | * faster than once in 10ms, so just return the saved value |
2899 | * in such cases. |
2901 | * in such cases. |
2900 | */ |
2902 | */ |
2901 | if (diff1 <= 10) |
2903 | if (diff1 <= 10) |
2902 | return dev_priv->ips.chipset_power; |
2904 | return dev_priv->ips.chipset_power; |
2903 | 2905 | ||
2904 | count1 = I915_READ(DMIEC); |
2906 | count1 = I915_READ(DMIEC); |
2905 | count2 = I915_READ(DDREC); |
2907 | count2 = I915_READ(DDREC); |
2906 | count3 = I915_READ(CSIEC); |
2908 | count3 = I915_READ(CSIEC); |
2907 | 2909 | ||
2908 | total_count = count1 + count2 + count3; |
2910 | total_count = count1 + count2 + count3; |
2909 | 2911 | ||
2910 | /* FIXME: handle per-counter overflow */ |
2912 | /* FIXME: handle per-counter overflow */ |
2911 | if (total_count < dev_priv->ips.last_count1) { |
2913 | if (total_count < dev_priv->ips.last_count1) { |
2912 | diff = ~0UL - dev_priv->ips.last_count1; |
2914 | diff = ~0UL - dev_priv->ips.last_count1; |
2913 | diff += total_count; |
2915 | diff += total_count; |
2914 | } else { |
2916 | } else { |
2915 | diff = total_count - dev_priv->ips.last_count1; |
2917 | diff = total_count - dev_priv->ips.last_count1; |
2916 | } |
2918 | } |
2917 | 2919 | ||
2918 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
2920 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
2919 | if (cparams[i].i == dev_priv->ips.c_m && |
2921 | if (cparams[i].i == dev_priv->ips.c_m && |
2920 | cparams[i].t == dev_priv->ips.r_t) { |
2922 | cparams[i].t == dev_priv->ips.r_t) { |
2921 | m = cparams[i].m; |
2923 | m = cparams[i].m; |
2922 | c = cparams[i].c; |
2924 | c = cparams[i].c; |
2923 | break; |
2925 | break; |
2924 | } |
2926 | } |
2925 | } |
2927 | } |
2926 | 2928 | ||
2927 | diff = div_u64(diff, diff1); |
2929 | diff = div_u64(diff, diff1); |
2928 | ret = ((m * diff) + c); |
2930 | ret = ((m * diff) + c); |
2929 | ret = div_u64(ret, 10); |
2931 | ret = div_u64(ret, 10); |
2930 | 2932 | ||
2931 | dev_priv->ips.last_count1 = total_count; |
2933 | dev_priv->ips.last_count1 = total_count; |
2932 | dev_priv->ips.last_time1 = now; |
2934 | dev_priv->ips.last_time1 = now; |
2933 | 2935 | ||
2934 | dev_priv->ips.chipset_power = ret; |
2936 | dev_priv->ips.chipset_power = ret; |
2935 | 2937 | ||
2936 | return ret; |
2938 | return ret; |
2937 | } |
2939 | } |
2938 | 2940 | ||
2939 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
2941 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
2940 | { |
2942 | { |
2941 | unsigned long val; |
2943 | unsigned long val; |
2942 | 2944 | ||
2943 | if (dev_priv->info->gen != 5) |
2945 | if (dev_priv->info->gen != 5) |
2944 | return 0; |
2946 | return 0; |
2945 | 2947 | ||
2946 | spin_lock_irq(&mchdev_lock); |
2948 | spin_lock_irq(&mchdev_lock); |
2947 | 2949 | ||
2948 | val = __i915_chipset_val(dev_priv); |
2950 | val = __i915_chipset_val(dev_priv); |
2949 | 2951 | ||
2950 | spin_unlock_irq(&mchdev_lock); |
2952 | spin_unlock_irq(&mchdev_lock); |
2951 | 2953 | ||
2952 | return val; |
2954 | return val; |
2953 | } |
2955 | } |
2954 | 2956 | ||
2955 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
2957 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
2956 | { |
2958 | { |
2957 | unsigned long m, x, b; |
2959 | unsigned long m, x, b; |
2958 | u32 tsfs; |
2960 | u32 tsfs; |
2959 | 2961 | ||
2960 | tsfs = I915_READ(TSFS); |
2962 | tsfs = I915_READ(TSFS); |
2961 | 2963 | ||
2962 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
2964 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
2963 | x = I915_READ8(TR1); |
2965 | x = I915_READ8(TR1); |
2964 | 2966 | ||
2965 | b = tsfs & TSFS_INTR_MASK; |
2967 | b = tsfs & TSFS_INTR_MASK; |
2966 | 2968 | ||
2967 | return ((m * x) / 127) - b; |
2969 | return ((m * x) / 127) - b; |
2968 | } |
2970 | } |
2969 | 2971 | ||
2970 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
2972 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
2971 | { |
2973 | { |
2972 | static const struct v_table { |
2974 | static const struct v_table { |
2973 | u16 vd; /* in .1 mil */ |
2975 | u16 vd; /* in .1 mil */ |
2974 | u16 vm; /* in .1 mil */ |
2976 | u16 vm; /* in .1 mil */ |
2975 | } v_table[] = { |
2977 | } v_table[] = { |
2976 | { 0, 0, }, |
2978 | { 0, 0, }, |
2977 | { 375, 0, }, |
2979 | { 375, 0, }, |
2978 | { 500, 0, }, |
2980 | { 500, 0, }, |
2979 | { 625, 0, }, |
2981 | { 625, 0, }, |
2980 | { 750, 0, }, |
2982 | { 750, 0, }, |
2981 | { 875, 0, }, |
2983 | { 875, 0, }, |
2982 | { 1000, 0, }, |
2984 | { 1000, 0, }, |
2983 | { 1125, 0, }, |
2985 | { 1125, 0, }, |
2984 | { 4125, 3000, }, |
2986 | { 4125, 3000, }, |
2985 | { 4125, 3000, }, |
2987 | { 4125, 3000, }, |
2986 | { 4125, 3000, }, |
2988 | { 4125, 3000, }, |
2987 | { 4125, 3000, }, |
2989 | { 4125, 3000, }, |
2988 | { 4125, 3000, }, |
2990 | { 4125, 3000, }, |
2989 | { 4125, 3000, }, |
2991 | { 4125, 3000, }, |
2990 | { 4125, 3000, }, |
2992 | { 4125, 3000, }, |
2991 | { 4125, 3000, }, |
2993 | { 4125, 3000, }, |
2992 | { 4125, 3000, }, |
2994 | { 4125, 3000, }, |
2993 | { 4125, 3000, }, |
2995 | { 4125, 3000, }, |
2994 | { 4125, 3000, }, |
2996 | { 4125, 3000, }, |
2995 | { 4125, 3000, }, |
2997 | { 4125, 3000, }, |
2996 | { 4125, 3000, }, |
2998 | { 4125, 3000, }, |
2997 | { 4125, 3000, }, |
2999 | { 4125, 3000, }, |
2998 | { 4125, 3000, }, |
3000 | { 4125, 3000, }, |
2999 | { 4125, 3000, }, |
3001 | { 4125, 3000, }, |
3000 | { 4125, 3000, }, |
3002 | { 4125, 3000, }, |
3001 | { 4125, 3000, }, |
3003 | { 4125, 3000, }, |
3002 | { 4125, 3000, }, |
3004 | { 4125, 3000, }, |
3003 | { 4125, 3000, }, |
3005 | { 4125, 3000, }, |
3004 | { 4125, 3000, }, |
3006 | { 4125, 3000, }, |
3005 | { 4125, 3000, }, |
3007 | { 4125, 3000, }, |
3006 | { 4125, 3000, }, |
3008 | { 4125, 3000, }, |
3007 | { 4125, 3000, }, |
3009 | { 4125, 3000, }, |
3008 | { 4250, 3125, }, |
3010 | { 4250, 3125, }, |
3009 | { 4375, 3250, }, |
3011 | { 4375, 3250, }, |
3010 | { 4500, 3375, }, |
3012 | { 4500, 3375, }, |
3011 | { 4625, 3500, }, |
3013 | { 4625, 3500, }, |
3012 | { 4750, 3625, }, |
3014 | { 4750, 3625, }, |
3013 | { 4875, 3750, }, |
3015 | { 4875, 3750, }, |
3014 | { 5000, 3875, }, |
3016 | { 5000, 3875, }, |
3015 | { 5125, 4000, }, |
3017 | { 5125, 4000, }, |
3016 | { 5250, 4125, }, |
3018 | { 5250, 4125, }, |
3017 | { 5375, 4250, }, |
3019 | { 5375, 4250, }, |
3018 | { 5500, 4375, }, |
3020 | { 5500, 4375, }, |
3019 | { 5625, 4500, }, |
3021 | { 5625, 4500, }, |
3020 | { 5750, 4625, }, |
3022 | { 5750, 4625, }, |
3021 | { 5875, 4750, }, |
3023 | { 5875, 4750, }, |
3022 | { 6000, 4875, }, |
3024 | { 6000, 4875, }, |
3023 | { 6125, 5000, }, |
3025 | { 6125, 5000, }, |
3024 | { 6250, 5125, }, |
3026 | { 6250, 5125, }, |
3025 | { 6375, 5250, }, |
3027 | { 6375, 5250, }, |
3026 | { 6500, 5375, }, |
3028 | { 6500, 5375, }, |
3027 | { 6625, 5500, }, |
3029 | { 6625, 5500, }, |
3028 | { 6750, 5625, }, |
3030 | { 6750, 5625, }, |
3029 | { 6875, 5750, }, |
3031 | { 6875, 5750, }, |
3030 | { 7000, 5875, }, |
3032 | { 7000, 5875, }, |
3031 | { 7125, 6000, }, |
3033 | { 7125, 6000, }, |
3032 | { 7250, 6125, }, |
3034 | { 7250, 6125, }, |
3033 | { 7375, 6250, }, |
3035 | { 7375, 6250, }, |
3034 | { 7500, 6375, }, |
3036 | { 7500, 6375, }, |
3035 | { 7625, 6500, }, |
3037 | { 7625, 6500, }, |
3036 | { 7750, 6625, }, |
3038 | { 7750, 6625, }, |
3037 | { 7875, 6750, }, |
3039 | { 7875, 6750, }, |
3038 | { 8000, 6875, }, |
3040 | { 8000, 6875, }, |
3039 | { 8125, 7000, }, |
3041 | { 8125, 7000, }, |
3040 | { 8250, 7125, }, |
3042 | { 8250, 7125, }, |
3041 | { 8375, 7250, }, |
3043 | { 8375, 7250, }, |
3042 | { 8500, 7375, }, |
3044 | { 8500, 7375, }, |
3043 | { 8625, 7500, }, |
3045 | { 8625, 7500, }, |
3044 | { 8750, 7625, }, |
3046 | { 8750, 7625, }, |
3045 | { 8875, 7750, }, |
3047 | { 8875, 7750, }, |
3046 | { 9000, 7875, }, |
3048 | { 9000, 7875, }, |
3047 | { 9125, 8000, }, |
3049 | { 9125, 8000, }, |
3048 | { 9250, 8125, }, |
3050 | { 9250, 8125, }, |
3049 | { 9375, 8250, }, |
3051 | { 9375, 8250, }, |
3050 | { 9500, 8375, }, |
3052 | { 9500, 8375, }, |
3051 | { 9625, 8500, }, |
3053 | { 9625, 8500, }, |
3052 | { 9750, 8625, }, |
3054 | { 9750, 8625, }, |
3053 | { 9875, 8750, }, |
3055 | { 9875, 8750, }, |
3054 | { 10000, 8875, }, |
3056 | { 10000, 8875, }, |
3055 | { 10125, 9000, }, |
3057 | { 10125, 9000, }, |
3056 | { 10250, 9125, }, |
3058 | { 10250, 9125, }, |
3057 | { 10375, 9250, }, |
3059 | { 10375, 9250, }, |
3058 | { 10500, 9375, }, |
3060 | { 10500, 9375, }, |
3059 | { 10625, 9500, }, |
3061 | { 10625, 9500, }, |
3060 | { 10750, 9625, }, |
3062 | { 10750, 9625, }, |
3061 | { 10875, 9750, }, |
3063 | { 10875, 9750, }, |
3062 | { 11000, 9875, }, |
3064 | { 11000, 9875, }, |
3063 | { 11125, 10000, }, |
3065 | { 11125, 10000, }, |
3064 | { 11250, 10125, }, |
3066 | { 11250, 10125, }, |
3065 | { 11375, 10250, }, |
3067 | { 11375, 10250, }, |
3066 | { 11500, 10375, }, |
3068 | { 11500, 10375, }, |
3067 | { 11625, 10500, }, |
3069 | { 11625, 10500, }, |
3068 | { 11750, 10625, }, |
3070 | { 11750, 10625, }, |
3069 | { 11875, 10750, }, |
3071 | { 11875, 10750, }, |
3070 | { 12000, 10875, }, |
3072 | { 12000, 10875, }, |
3071 | { 12125, 11000, }, |
3073 | { 12125, 11000, }, |
3072 | { 12250, 11125, }, |
3074 | { 12250, 11125, }, |
3073 | { 12375, 11250, }, |
3075 | { 12375, 11250, }, |
3074 | { 12500, 11375, }, |
3076 | { 12500, 11375, }, |
3075 | { 12625, 11500, }, |
3077 | { 12625, 11500, }, |
3076 | { 12750, 11625, }, |
3078 | { 12750, 11625, }, |
3077 | { 12875, 11750, }, |
3079 | { 12875, 11750, }, |
3078 | { 13000, 11875, }, |
3080 | { 13000, 11875, }, |
3079 | { 13125, 12000, }, |
3081 | { 13125, 12000, }, |
3080 | { 13250, 12125, }, |
3082 | { 13250, 12125, }, |
3081 | { 13375, 12250, }, |
3083 | { 13375, 12250, }, |
3082 | { 13500, 12375, }, |
3084 | { 13500, 12375, }, |
3083 | { 13625, 12500, }, |
3085 | { 13625, 12500, }, |
3084 | { 13750, 12625, }, |
3086 | { 13750, 12625, }, |
3085 | { 13875, 12750, }, |
3087 | { 13875, 12750, }, |
3086 | { 14000, 12875, }, |
3088 | { 14000, 12875, }, |
3087 | { 14125, 13000, }, |
3089 | { 14125, 13000, }, |
3088 | { 14250, 13125, }, |
3090 | { 14250, 13125, }, |
3089 | { 14375, 13250, }, |
3091 | { 14375, 13250, }, |
3090 | { 14500, 13375, }, |
3092 | { 14500, 13375, }, |
3091 | { 14625, 13500, }, |
3093 | { 14625, 13500, }, |
3092 | { 14750, 13625, }, |
3094 | { 14750, 13625, }, |
3093 | { 14875, 13750, }, |
3095 | { 14875, 13750, }, |
3094 | { 15000, 13875, }, |
3096 | { 15000, 13875, }, |
3095 | { 15125, 14000, }, |
3097 | { 15125, 14000, }, |
3096 | { 15250, 14125, }, |
3098 | { 15250, 14125, }, |
3097 | { 15375, 14250, }, |
3099 | { 15375, 14250, }, |
3098 | { 15500, 14375, }, |
3100 | { 15500, 14375, }, |
3099 | { 15625, 14500, }, |
3101 | { 15625, 14500, }, |
3100 | { 15750, 14625, }, |
3102 | { 15750, 14625, }, |
3101 | { 15875, 14750, }, |
3103 | { 15875, 14750, }, |
3102 | { 16000, 14875, }, |
3104 | { 16000, 14875, }, |
3103 | { 16125, 15000, }, |
3105 | { 16125, 15000, }, |
3104 | }; |
3106 | }; |
3105 | if (dev_priv->info->is_mobile) |
3107 | if (dev_priv->info->is_mobile) |
3106 | return v_table[pxvid].vm; |
3108 | return v_table[pxvid].vm; |
3107 | else |
3109 | else |
3108 | return v_table[pxvid].vd; |
3110 | return v_table[pxvid].vd; |
3109 | } |
3111 | } |
3110 | 3112 | ||
3111 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3113 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3112 | { |
3114 | { |
3113 | struct timespec now, diff1; |
3115 | struct timespec now, diff1; |
3114 | u64 diff; |
3116 | u64 diff; |
3115 | unsigned long diffms; |
3117 | unsigned long diffms; |
3116 | u32 count; |
3118 | u32 count; |
3117 | 3119 | ||
3118 | assert_spin_locked(&mchdev_lock); |
3120 | assert_spin_locked(&mchdev_lock); |
3119 | 3121 | ||
3120 | getrawmonotonic(&now); |
3122 | getrawmonotonic(&now); |
3121 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
3123 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
3122 | 3124 | ||
3123 | /* Don't divide by 0 */ |
3125 | /* Don't divide by 0 */ |
3124 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
3126 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
3125 | if (!diffms) |
3127 | if (!diffms) |
3126 | return; |
3128 | return; |
3127 | 3129 | ||
3128 | count = I915_READ(GFXEC); |
3130 | count = I915_READ(GFXEC); |
3129 | 3131 | ||
3130 | if (count < dev_priv->ips.last_count2) { |
3132 | if (count < dev_priv->ips.last_count2) { |
3131 | diff = ~0UL - dev_priv->ips.last_count2; |
3133 | diff = ~0UL - dev_priv->ips.last_count2; |
3132 | diff += count; |
3134 | diff += count; |
3133 | } else { |
3135 | } else { |
3134 | diff = count - dev_priv->ips.last_count2; |
3136 | diff = count - dev_priv->ips.last_count2; |
3135 | } |
3137 | } |
3136 | 3138 | ||
3137 | dev_priv->ips.last_count2 = count; |
3139 | dev_priv->ips.last_count2 = count; |
3138 | dev_priv->ips.last_time2 = now; |
3140 | dev_priv->ips.last_time2 = now; |
3139 | 3141 | ||
3140 | /* More magic constants... */ |
3142 | /* More magic constants... */ |
3141 | diff = diff * 1181; |
3143 | diff = diff * 1181; |
3142 | diff = div_u64(diff, diffms * 10); |
3144 | diff = div_u64(diff, diffms * 10); |
3143 | dev_priv->ips.gfx_power = diff; |
3145 | dev_priv->ips.gfx_power = diff; |
3144 | } |
3146 | } |
3145 | 3147 | ||
3146 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3148 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3147 | { |
3149 | { |
3148 | if (dev_priv->info->gen != 5) |
3150 | if (dev_priv->info->gen != 5) |
3149 | return; |
3151 | return; |
3150 | 3152 | ||
3151 | spin_lock_irq(&mchdev_lock); |
3153 | spin_lock_irq(&mchdev_lock); |
3152 | 3154 | ||
3153 | __i915_update_gfx_val(dev_priv); |
3155 | __i915_update_gfx_val(dev_priv); |
3154 | 3156 | ||
3155 | spin_unlock_irq(&mchdev_lock); |
3157 | spin_unlock_irq(&mchdev_lock); |
3156 | } |
3158 | } |
3157 | 3159 | ||
3158 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
3160 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
3159 | { |
3161 | { |
3160 | unsigned long t, corr, state1, corr2, state2; |
3162 | unsigned long t, corr, state1, corr2, state2; |
3161 | u32 pxvid, ext_v; |
3163 | u32 pxvid, ext_v; |
3162 | 3164 | ||
3163 | assert_spin_locked(&mchdev_lock); |
3165 | assert_spin_locked(&mchdev_lock); |
3164 | 3166 | ||
3165 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
3167 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
3166 | pxvid = (pxvid >> 24) & 0x7f; |
3168 | pxvid = (pxvid >> 24) & 0x7f; |
3167 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
3169 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
3168 | 3170 | ||
3169 | state1 = ext_v; |
3171 | state1 = ext_v; |
3170 | 3172 | ||
3171 | t = i915_mch_val(dev_priv); |
3173 | t = i915_mch_val(dev_priv); |
3172 | 3174 | ||
3173 | /* Revel in the empirically derived constants */ |
3175 | /* Revel in the empirically derived constants */ |
3174 | 3176 | ||
3175 | /* Correction factor in 1/100000 units */ |
3177 | /* Correction factor in 1/100000 units */ |
3176 | if (t > 80) |
3178 | if (t > 80) |
3177 | corr = ((t * 2349) + 135940); |
3179 | corr = ((t * 2349) + 135940); |
3178 | else if (t >= 50) |
3180 | else if (t >= 50) |
3179 | corr = ((t * 964) + 29317); |
3181 | corr = ((t * 964) + 29317); |
3180 | else /* < 50 */ |
3182 | else /* < 50 */ |
3181 | corr = ((t * 301) + 1004); |
3183 | corr = ((t * 301) + 1004); |
3182 | 3184 | ||
3183 | corr = corr * ((150142 * state1) / 10000 - 78642); |
3185 | corr = corr * ((150142 * state1) / 10000 - 78642); |
3184 | corr /= 100000; |
3186 | corr /= 100000; |
3185 | corr2 = (corr * dev_priv->ips.corr); |
3187 | corr2 = (corr * dev_priv->ips.corr); |
3186 | 3188 | ||
3187 | state2 = (corr2 * state1) / 10000; |
3189 | state2 = (corr2 * state1) / 10000; |
3188 | state2 /= 100; /* convert to mW */ |
3190 | state2 /= 100; /* convert to mW */ |
3189 | 3191 | ||
3190 | __i915_update_gfx_val(dev_priv); |
3192 | __i915_update_gfx_val(dev_priv); |
3191 | 3193 | ||
3192 | return dev_priv->ips.gfx_power + state2; |
3194 | return dev_priv->ips.gfx_power + state2; |
3193 | } |
3195 | } |
3194 | 3196 | ||
3195 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
3197 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
3196 | { |
3198 | { |
3197 | unsigned long val; |
3199 | unsigned long val; |
3198 | 3200 | ||
3199 | if (dev_priv->info->gen != 5) |
3201 | if (dev_priv->info->gen != 5) |
3200 | return 0; |
3202 | return 0; |
3201 | 3203 | ||
3202 | spin_lock_irq(&mchdev_lock); |
3204 | spin_lock_irq(&mchdev_lock); |
3203 | 3205 | ||
3204 | val = __i915_gfx_val(dev_priv); |
3206 | val = __i915_gfx_val(dev_priv); |
3205 | 3207 | ||
3206 | spin_unlock_irq(&mchdev_lock); |
3208 | spin_unlock_irq(&mchdev_lock); |
3207 | 3209 | ||
3208 | return val; |
3210 | return val; |
3209 | } |
3211 | } |
3210 | 3212 | ||
3211 | /** |
3213 | /** |
3212 | * i915_read_mch_val - return value for IPS use |
3214 | * i915_read_mch_val - return value for IPS use |
3213 | * |
3215 | * |
3214 | * Calculate and return a value for the IPS driver to use when deciding whether |
3216 | * Calculate and return a value for the IPS driver to use when deciding whether |
3215 | * we have thermal and power headroom to increase CPU or GPU power budget. |
3217 | * we have thermal and power headroom to increase CPU or GPU power budget. |
3216 | */ |
3218 | */ |
3217 | unsigned long i915_read_mch_val(void) |
3219 | unsigned long i915_read_mch_val(void) |
3218 | { |
3220 | { |
3219 | struct drm_i915_private *dev_priv; |
3221 | struct drm_i915_private *dev_priv; |
3220 | unsigned long chipset_val, graphics_val, ret = 0; |
3222 | unsigned long chipset_val, graphics_val, ret = 0; |
3221 | 3223 | ||
3222 | spin_lock_irq(&mchdev_lock); |
3224 | spin_lock_irq(&mchdev_lock); |
3223 | if (!i915_mch_dev) |
3225 | if (!i915_mch_dev) |
3224 | goto out_unlock; |
3226 | goto out_unlock; |
3225 | dev_priv = i915_mch_dev; |
3227 | dev_priv = i915_mch_dev; |
3226 | 3228 | ||
3227 | chipset_val = __i915_chipset_val(dev_priv); |
3229 | chipset_val = __i915_chipset_val(dev_priv); |
3228 | graphics_val = __i915_gfx_val(dev_priv); |
3230 | graphics_val = __i915_gfx_val(dev_priv); |
3229 | 3231 | ||
3230 | ret = chipset_val + graphics_val; |
3232 | ret = chipset_val + graphics_val; |
3231 | 3233 | ||
3232 | out_unlock: |
3234 | out_unlock: |
3233 | spin_unlock_irq(&mchdev_lock); |
3235 | spin_unlock_irq(&mchdev_lock); |
3234 | 3236 | ||
3235 | return ret; |
3237 | return ret; |
3236 | } |
3238 | } |
3237 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
3239 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
3238 | 3240 | ||
3239 | /** |
3241 | /** |
3240 | * i915_gpu_raise - raise GPU frequency limit |
3242 | * i915_gpu_raise - raise GPU frequency limit |
3241 | * |
3243 | * |
3242 | * Raise the limit; IPS indicates we have thermal headroom. |
3244 | * Raise the limit; IPS indicates we have thermal headroom. |
3243 | */ |
3245 | */ |
3244 | bool i915_gpu_raise(void) |
3246 | bool i915_gpu_raise(void) |
3245 | { |
3247 | { |
3246 | struct drm_i915_private *dev_priv; |
3248 | struct drm_i915_private *dev_priv; |
3247 | bool ret = true; |
3249 | bool ret = true; |
3248 | 3250 | ||
3249 | spin_lock_irq(&mchdev_lock); |
3251 | spin_lock_irq(&mchdev_lock); |
3250 | if (!i915_mch_dev) { |
3252 | if (!i915_mch_dev) { |
3251 | ret = false; |
3253 | ret = false; |
3252 | goto out_unlock; |
3254 | goto out_unlock; |
3253 | } |
3255 | } |
3254 | dev_priv = i915_mch_dev; |
3256 | dev_priv = i915_mch_dev; |
3255 | 3257 | ||
3256 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
3258 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
3257 | dev_priv->ips.max_delay--; |
3259 | dev_priv->ips.max_delay--; |
3258 | 3260 | ||
3259 | out_unlock: |
3261 | out_unlock: |
3260 | spin_unlock_irq(&mchdev_lock); |
3262 | spin_unlock_irq(&mchdev_lock); |
3261 | 3263 | ||
3262 | return ret; |
3264 | return ret; |
3263 | } |
3265 | } |
3264 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
3266 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
3265 | 3267 | ||
3266 | /** |
3268 | /** |
3267 | * i915_gpu_lower - lower GPU frequency limit |
3269 | * i915_gpu_lower - lower GPU frequency limit |
3268 | * |
3270 | * |
3269 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
3271 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
3270 | * frequency maximum. |
3272 | * frequency maximum. |
3271 | */ |
3273 | */ |
3272 | bool i915_gpu_lower(void) |
3274 | bool i915_gpu_lower(void) |
3273 | { |
3275 | { |
3274 | struct drm_i915_private *dev_priv; |
3276 | struct drm_i915_private *dev_priv; |
3275 | bool ret = true; |
3277 | bool ret = true; |
3276 | 3278 | ||
3277 | spin_lock_irq(&mchdev_lock); |
3279 | spin_lock_irq(&mchdev_lock); |
3278 | if (!i915_mch_dev) { |
3280 | if (!i915_mch_dev) { |
3279 | ret = false; |
3281 | ret = false; |
3280 | goto out_unlock; |
3282 | goto out_unlock; |
3281 | } |
3283 | } |
3282 | dev_priv = i915_mch_dev; |
3284 | dev_priv = i915_mch_dev; |
3283 | 3285 | ||
3284 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
3286 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
3285 | dev_priv->ips.max_delay++; |
3287 | dev_priv->ips.max_delay++; |
3286 | 3288 | ||
3287 | out_unlock: |
3289 | out_unlock: |
3288 | spin_unlock_irq(&mchdev_lock); |
3290 | spin_unlock_irq(&mchdev_lock); |
3289 | 3291 | ||
3290 | return ret; |
3292 | return ret; |
3291 | } |
3293 | } |
3292 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
3294 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
3293 | 3295 | ||
3294 | /** |
3296 | /** |
3295 | * i915_gpu_busy - indicate GPU business to IPS |
3297 | * i915_gpu_busy - indicate GPU business to IPS |
3296 | * |
3298 | * |
3297 | * Tell the IPS driver whether or not the GPU is busy. |
3299 | * Tell the IPS driver whether or not the GPU is busy. |
3298 | */ |
3300 | */ |
3299 | bool i915_gpu_busy(void) |
3301 | bool i915_gpu_busy(void) |
3300 | { |
3302 | { |
3301 | struct drm_i915_private *dev_priv; |
3303 | struct drm_i915_private *dev_priv; |
3302 | struct intel_ring_buffer *ring; |
3304 | struct intel_ring_buffer *ring; |
3303 | bool ret = false; |
3305 | bool ret = false; |
3304 | int i; |
3306 | int i; |
3305 | 3307 | ||
3306 | spin_lock_irq(&mchdev_lock); |
3308 | spin_lock_irq(&mchdev_lock); |
3307 | if (!i915_mch_dev) |
3309 | if (!i915_mch_dev) |
3308 | goto out_unlock; |
3310 | goto out_unlock; |
3309 | dev_priv = i915_mch_dev; |
3311 | dev_priv = i915_mch_dev; |
3310 | 3312 | ||
3311 | for_each_ring(ring, dev_priv, i) |
3313 | for_each_ring(ring, dev_priv, i) |
3312 | ret |= !list_empty(&ring->request_list); |
3314 | ret |= !list_empty(&ring->request_list); |
3313 | 3315 | ||
3314 | out_unlock: |
3316 | out_unlock: |
3315 | spin_unlock_irq(&mchdev_lock); |
3317 | spin_unlock_irq(&mchdev_lock); |
3316 | 3318 | ||
3317 | return ret; |
3319 | return ret; |
3318 | } |
3320 | } |
3319 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
3321 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
3320 | 3322 | ||
3321 | /** |
3323 | /** |
3322 | * i915_gpu_turbo_disable - disable graphics turbo |
3324 | * i915_gpu_turbo_disable - disable graphics turbo |
3323 | * |
3325 | * |
3324 | * Disable graphics turbo by resetting the max frequency and setting the |
3326 | * Disable graphics turbo by resetting the max frequency and setting the |
3325 | * current frequency to the default. |
3327 | * current frequency to the default. |
3326 | */ |
3328 | */ |
3327 | bool i915_gpu_turbo_disable(void) |
3329 | bool i915_gpu_turbo_disable(void) |
3328 | { |
3330 | { |
3329 | struct drm_i915_private *dev_priv; |
3331 | struct drm_i915_private *dev_priv; |
3330 | bool ret = true; |
3332 | bool ret = true; |
3331 | 3333 | ||
3332 | spin_lock_irq(&mchdev_lock); |
3334 | spin_lock_irq(&mchdev_lock); |
3333 | if (!i915_mch_dev) { |
3335 | if (!i915_mch_dev) { |
3334 | ret = false; |
3336 | ret = false; |
3335 | goto out_unlock; |
3337 | goto out_unlock; |
3336 | } |
3338 | } |
3337 | dev_priv = i915_mch_dev; |
3339 | dev_priv = i915_mch_dev; |
3338 | 3340 | ||
3339 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
3341 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
3340 | 3342 | ||
3341 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
3343 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
3342 | ret = false; |
3344 | ret = false; |
3343 | 3345 | ||
3344 | out_unlock: |
3346 | out_unlock: |
3345 | spin_unlock_irq(&mchdev_lock); |
3347 | spin_unlock_irq(&mchdev_lock); |
3346 | 3348 | ||
3347 | return ret; |
3349 | return ret; |
3348 | } |
3350 | } |
3349 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
3351 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
3350 | 3352 | ||
3351 | /** |
3353 | /** |
3352 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
3354 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
3353 | * IPS got loaded first. |
3355 | * IPS got loaded first. |
3354 | * |
3356 | * |
3355 | * This awkward dance is so that neither module has to depend on the |
3357 | * This awkward dance is so that neither module has to depend on the |
3356 | * other in order for IPS to do the appropriate communication of |
3358 | * other in order for IPS to do the appropriate communication of |
3357 | * GPU turbo limits to i915. |
3359 | * GPU turbo limits to i915. |
3358 | */ |
3360 | */ |
3359 | static void |
3361 | static void |
3360 | ips_ping_for_i915_load(void) |
3362 | ips_ping_for_i915_load(void) |
3361 | { |
3363 | { |
3362 | void (*link)(void); |
3364 | void (*link)(void); |
3363 | 3365 | ||
3364 | // link = symbol_get(ips_link_to_i915_driver); |
3366 | // link = symbol_get(ips_link_to_i915_driver); |
3365 | // if (link) { |
3367 | // if (link) { |
3366 | // link(); |
3368 | // link(); |
3367 | // symbol_put(ips_link_to_i915_driver); |
3369 | // symbol_put(ips_link_to_i915_driver); |
3368 | // } |
3370 | // } |
3369 | } |
3371 | } |
3370 | 3372 | ||
3371 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
3373 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
3372 | { |
3374 | { |
3373 | /* We only register the i915 ips part with intel-ips once everything is |
3375 | /* We only register the i915 ips part with intel-ips once everything is |
3374 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
3376 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
3375 | spin_lock_irq(&mchdev_lock); |
3377 | spin_lock_irq(&mchdev_lock); |
3376 | i915_mch_dev = dev_priv; |
3378 | i915_mch_dev = dev_priv; |
3377 | spin_unlock_irq(&mchdev_lock); |
3379 | spin_unlock_irq(&mchdev_lock); |
3378 | 3380 | ||
3379 | ips_ping_for_i915_load(); |
3381 | ips_ping_for_i915_load(); |
3380 | } |
3382 | } |
3381 | 3383 | ||
3382 | void intel_gpu_ips_teardown(void) |
3384 | void intel_gpu_ips_teardown(void) |
3383 | { |
3385 | { |
3384 | spin_lock_irq(&mchdev_lock); |
3386 | spin_lock_irq(&mchdev_lock); |
3385 | i915_mch_dev = NULL; |
3387 | i915_mch_dev = NULL; |
3386 | spin_unlock_irq(&mchdev_lock); |
3388 | spin_unlock_irq(&mchdev_lock); |
3387 | } |
3389 | } |
3388 | static void intel_init_emon(struct drm_device *dev) |
3390 | static void intel_init_emon(struct drm_device *dev) |
3389 | { |
3391 | { |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
3392 | struct drm_i915_private *dev_priv = dev->dev_private; |
3391 | u32 lcfuse; |
3393 | u32 lcfuse; |
3392 | u8 pxw[16]; |
3394 | u8 pxw[16]; |
3393 | int i; |
3395 | int i; |
3394 | 3396 | ||
3395 | /* Disable to program */ |
3397 | /* Disable to program */ |
3396 | I915_WRITE(ECR, 0); |
3398 | I915_WRITE(ECR, 0); |
3397 | POSTING_READ(ECR); |
3399 | POSTING_READ(ECR); |
3398 | 3400 | ||
3399 | /* Program energy weights for various events */ |
3401 | /* Program energy weights for various events */ |
3400 | I915_WRITE(SDEW, 0x15040d00); |
3402 | I915_WRITE(SDEW, 0x15040d00); |
3401 | I915_WRITE(CSIEW0, 0x007f0000); |
3403 | I915_WRITE(CSIEW0, 0x007f0000); |
3402 | I915_WRITE(CSIEW1, 0x1e220004); |
3404 | I915_WRITE(CSIEW1, 0x1e220004); |
3403 | I915_WRITE(CSIEW2, 0x04000004); |
3405 | I915_WRITE(CSIEW2, 0x04000004); |
3404 | 3406 | ||
3405 | for (i = 0; i < 5; i++) |
3407 | for (i = 0; i < 5; i++) |
3406 | I915_WRITE(PEW + (i * 4), 0); |
3408 | I915_WRITE(PEW + (i * 4), 0); |
3407 | for (i = 0; i < 3; i++) |
3409 | for (i = 0; i < 3; i++) |
3408 | I915_WRITE(DEW + (i * 4), 0); |
3410 | I915_WRITE(DEW + (i * 4), 0); |
3409 | 3411 | ||
3410 | /* Program P-state weights to account for frequency power adjustment */ |
3412 | /* Program P-state weights to account for frequency power adjustment */ |
3411 | for (i = 0; i < 16; i++) { |
3413 | for (i = 0; i < 16; i++) { |
3412 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
3414 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
3413 | unsigned long freq = intel_pxfreq(pxvidfreq); |
3415 | unsigned long freq = intel_pxfreq(pxvidfreq); |
3414 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
3416 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
3415 | PXVFREQ_PX_SHIFT; |
3417 | PXVFREQ_PX_SHIFT; |
3416 | unsigned long val; |
3418 | unsigned long val; |
3417 | 3419 | ||
3418 | val = vid * vid; |
3420 | val = vid * vid; |
3419 | val *= (freq / 1000); |
3421 | val *= (freq / 1000); |
3420 | val *= 255; |
3422 | val *= 255; |
3421 | val /= (127*127*900); |
3423 | val /= (127*127*900); |
3422 | if (val > 0xff) |
3424 | if (val > 0xff) |
3423 | DRM_ERROR("bad pxval: %ld\n", val); |
3425 | DRM_ERROR("bad pxval: %ld\n", val); |
3424 | pxw[i] = val; |
3426 | pxw[i] = val; |
3425 | } |
3427 | } |
3426 | /* Render standby states get 0 weight */ |
3428 | /* Render standby states get 0 weight */ |
3427 | pxw[14] = 0; |
3429 | pxw[14] = 0; |
3428 | pxw[15] = 0; |
3430 | pxw[15] = 0; |
3429 | 3431 | ||
3430 | for (i = 0; i < 4; i++) { |
3432 | for (i = 0; i < 4; i++) { |
3431 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
3433 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
3432 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
3434 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
3433 | I915_WRITE(PXW + (i * 4), val); |
3435 | I915_WRITE(PXW + (i * 4), val); |
3434 | } |
3436 | } |
3435 | 3437 | ||
3436 | /* Adjust magic regs to magic values (more experimental results) */ |
3438 | /* Adjust magic regs to magic values (more experimental results) */ |
3437 | I915_WRITE(OGW0, 0); |
3439 | I915_WRITE(OGW0, 0); |
3438 | I915_WRITE(OGW1, 0); |
3440 | I915_WRITE(OGW1, 0); |
3439 | I915_WRITE(EG0, 0x00007f00); |
3441 | I915_WRITE(EG0, 0x00007f00); |
3440 | I915_WRITE(EG1, 0x0000000e); |
3442 | I915_WRITE(EG1, 0x0000000e); |
3441 | I915_WRITE(EG2, 0x000e0000); |
3443 | I915_WRITE(EG2, 0x000e0000); |
3442 | I915_WRITE(EG3, 0x68000300); |
3444 | I915_WRITE(EG3, 0x68000300); |
3443 | I915_WRITE(EG4, 0x42000000); |
3445 | I915_WRITE(EG4, 0x42000000); |
3444 | I915_WRITE(EG5, 0x00140031); |
3446 | I915_WRITE(EG5, 0x00140031); |
3445 | I915_WRITE(EG6, 0); |
3447 | I915_WRITE(EG6, 0); |
3446 | I915_WRITE(EG7, 0); |
3448 | I915_WRITE(EG7, 0); |
3447 | 3449 | ||
3448 | for (i = 0; i < 8; i++) |
3450 | for (i = 0; i < 8; i++) |
3449 | I915_WRITE(PXWL + (i * 4), 0); |
3451 | I915_WRITE(PXWL + (i * 4), 0); |
3450 | 3452 | ||
3451 | /* Enable PMON + select events */ |
3453 | /* Enable PMON + select events */ |
3452 | I915_WRITE(ECR, 0x80000019); |
3454 | I915_WRITE(ECR, 0x80000019); |
3453 | 3455 | ||
3454 | lcfuse = I915_READ(LCFUSE02); |
3456 | lcfuse = I915_READ(LCFUSE02); |
3455 | 3457 | ||
3456 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
3458 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
3457 | } |
3459 | } |
3458 | 3460 | ||
3459 | void intel_disable_gt_powersave(struct drm_device *dev) |
3461 | void intel_disable_gt_powersave(struct drm_device *dev) |
3460 | { |
3462 | { |
3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
3463 | struct drm_i915_private *dev_priv = dev->dev_private; |
3462 | 3464 | ||
3463 | if (IS_IRONLAKE_M(dev)) { |
3465 | if (IS_IRONLAKE_M(dev)) { |
3464 | ironlake_disable_drps(dev); |
3466 | ironlake_disable_drps(dev); |
3465 | ironlake_disable_rc6(dev); |
3467 | ironlake_disable_rc6(dev); |
3466 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3468 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3467 | gen6_disable_rps(dev); |
3469 | gen6_disable_rps(dev); |
- | 3470 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
3468 | } |
3471 | } |
3469 | } |
3472 | } |
3470 | 3473 | ||
3471 | void intel_enable_gt_powersave(struct drm_device *dev) |
3474 | void intel_enable_gt_powersave(struct drm_device *dev) |
3472 | { |
3475 | { |
3473 | struct drm_i915_private *dev_priv = dev->dev_private; |
3476 | struct drm_i915_private *dev_priv = dev->dev_private; |
3474 | 3477 | ||
3475 | if (IS_IRONLAKE_M(dev)) { |
3478 | if (IS_IRONLAKE_M(dev)) { |
3476 | ironlake_enable_drps(dev); |
3479 | ironlake_enable_drps(dev); |
3477 | ironlake_enable_rc6(dev); |
3480 | ironlake_enable_rc6(dev); |
3478 | intel_init_emon(dev); |
3481 | intel_init_emon(dev); |
3479 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3482 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3480 | /* |
3483 | /* |
3481 | * PCU communication is slow and this doesn't need to be |
3484 | * PCU communication is slow and this doesn't need to be |
3482 | * done at any specific time, so do this out of our fast path |
3485 | * done at any specific time, so do this out of our fast path |
3483 | * to make resume and init faster. |
3486 | * to make resume and init faster. |
3484 | */ |
3487 | */ |
3485 | // schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
3488 | // schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
3486 | // round_jiffies_up_relative(HZ)); |
3489 | // round_jiffies_up_relative(HZ)); |
3487 | } |
3490 | } |
3488 | } |
3491 | } |
3489 | 3492 | ||
3490 | static void ibx_init_clock_gating(struct drm_device *dev) |
3493 | static void ibx_init_clock_gating(struct drm_device *dev) |
3491 | { |
3494 | { |
3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; |
3493 | 3496 | ||
3494 | /* |
3497 | /* |
3495 | * On Ibex Peak and Cougar Point, we need to disable clock |
3498 | * On Ibex Peak and Cougar Point, we need to disable clock |
3496 | * gating for the panel power sequencer or it will fail to |
3499 | * gating for the panel power sequencer or it will fail to |
3497 | * start up when no ports are active. |
3500 | * start up when no ports are active. |
3498 | */ |
3501 | */ |
3499 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
3502 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
3500 | } |
3503 | } |
3501 | 3504 | ||
3502 | static void ironlake_init_clock_gating(struct drm_device *dev) |
3505 | static void ironlake_init_clock_gating(struct drm_device *dev) |
3503 | { |
3506 | { |
3504 | struct drm_i915_private *dev_priv = dev->dev_private; |
3507 | struct drm_i915_private *dev_priv = dev->dev_private; |
3505 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3508 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3506 | 3509 | ||
3507 | /* Required for FBC */ |
3510 | /* Required for FBC */ |
3508 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3511 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3509 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
3512 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
3510 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
3513 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
3511 | 3514 | ||
3512 | I915_WRITE(PCH_3DCGDIS0, |
3515 | I915_WRITE(PCH_3DCGDIS0, |
3513 | MARIUNIT_CLOCK_GATE_DISABLE | |
3516 | MARIUNIT_CLOCK_GATE_DISABLE | |
3514 | SVSMUNIT_CLOCK_GATE_DISABLE); |
3517 | SVSMUNIT_CLOCK_GATE_DISABLE); |
3515 | I915_WRITE(PCH_3DCGDIS1, |
3518 | I915_WRITE(PCH_3DCGDIS1, |
3516 | VFMUNIT_CLOCK_GATE_DISABLE); |
3519 | VFMUNIT_CLOCK_GATE_DISABLE); |
3517 | 3520 | ||
3518 | /* |
3521 | /* |
3519 | * According to the spec the following bits should be set in |
3522 | * According to the spec the following bits should be set in |
3520 | * order to enable memory self-refresh |
3523 | * order to enable memory self-refresh |
3521 | * The bit 22/21 of 0x42004 |
3524 | * The bit 22/21 of 0x42004 |
3522 | * The bit 5 of 0x42020 |
3525 | * The bit 5 of 0x42020 |
3523 | * The bit 15 of 0x45000 |
3526 | * The bit 15 of 0x45000 |
3524 | */ |
3527 | */ |
3525 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3528 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3526 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
3529 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
3527 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
3530 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
3528 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
3531 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
3529 | I915_WRITE(DISP_ARB_CTL, |
3532 | I915_WRITE(DISP_ARB_CTL, |
3530 | (I915_READ(DISP_ARB_CTL) | |
3533 | (I915_READ(DISP_ARB_CTL) | |
3531 | DISP_FBC_WM_DIS)); |
3534 | DISP_FBC_WM_DIS)); |
3532 | I915_WRITE(WM3_LP_ILK, 0); |
3535 | I915_WRITE(WM3_LP_ILK, 0); |
3533 | I915_WRITE(WM2_LP_ILK, 0); |
3536 | I915_WRITE(WM2_LP_ILK, 0); |
3534 | I915_WRITE(WM1_LP_ILK, 0); |
3537 | I915_WRITE(WM1_LP_ILK, 0); |
3535 | 3538 | ||
3536 | /* |
3539 | /* |
3537 | * Based on the document from hardware guys the following bits |
3540 | * Based on the document from hardware guys the following bits |
3538 | * should be set unconditionally in order to enable FBC. |
3541 | * should be set unconditionally in order to enable FBC. |
3539 | * The bit 22 of 0x42000 |
3542 | * The bit 22 of 0x42000 |
3540 | * The bit 22 of 0x42004 |
3543 | * The bit 22 of 0x42004 |
3541 | * The bit 7,8,9 of 0x42020. |
3544 | * The bit 7,8,9 of 0x42020. |
3542 | */ |
3545 | */ |
3543 | if (IS_IRONLAKE_M(dev)) { |
3546 | if (IS_IRONLAKE_M(dev)) { |
3544 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3547 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3545 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3548 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3546 | ILK_FBCQ_DIS); |
3549 | ILK_FBCQ_DIS); |
3547 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3550 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3548 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3551 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3549 | ILK_DPARB_GATE); |
3552 | ILK_DPARB_GATE); |
3550 | } |
3553 | } |
3551 | 3554 | ||
3552 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3555 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3553 | 3556 | ||
3554 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3557 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3555 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3558 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3556 | ILK_ELPIN_409_SELECT); |
3559 | ILK_ELPIN_409_SELECT); |
3557 | I915_WRITE(_3D_CHICKEN2, |
3560 | I915_WRITE(_3D_CHICKEN2, |
3558 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
3561 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
3559 | _3D_CHICKEN2_WM_READ_PIPELINED); |
3562 | _3D_CHICKEN2_WM_READ_PIPELINED); |
3560 | 3563 | ||
3561 | /* WaDisableRenderCachePipelinedFlush */ |
3564 | /* WaDisableRenderCachePipelinedFlush */ |
3562 | I915_WRITE(CACHE_MODE_0, |
3565 | I915_WRITE(CACHE_MODE_0, |
3563 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
3566 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
3564 | 3567 | ||
3565 | ibx_init_clock_gating(dev); |
3568 | ibx_init_clock_gating(dev); |
3566 | } |
3569 | } |
3567 | 3570 | ||
3568 | static void cpt_init_clock_gating(struct drm_device *dev) |
3571 | static void cpt_init_clock_gating(struct drm_device *dev) |
3569 | { |
3572 | { |
3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
3573 | struct drm_i915_private *dev_priv = dev->dev_private; |
3571 | int pipe; |
3574 | int pipe; |
3572 | 3575 | ||
3573 | /* |
3576 | /* |
3574 | * On Ibex Peak and Cougar Point, we need to disable clock |
3577 | * On Ibex Peak and Cougar Point, we need to disable clock |
3575 | * gating for the panel power sequencer or it will fail to |
3578 | * gating for the panel power sequencer or it will fail to |
3576 | * start up when no ports are active. |
3579 | * start up when no ports are active. |
3577 | */ |
3580 | */ |
3578 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
3581 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
3579 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
3582 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
3580 | DPLS_EDP_PPS_FIX_DIS); |
3583 | DPLS_EDP_PPS_FIX_DIS); |
3581 | /* The below fixes the weird display corruption, a few pixels shifted |
3584 | /* The below fixes the weird display corruption, a few pixels shifted |
3582 | * downward, on (only) LVDS of some HP laptops with IVY. |
3585 | * downward, on (only) LVDS of some HP laptops with IVY. |
3583 | */ |
3586 | */ |
3584 | for_each_pipe(pipe) |
3587 | for_each_pipe(pipe) |
3585 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); |
3588 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); |
3586 | /* WADP0ClockGatingDisable */ |
3589 | /* WADP0ClockGatingDisable */ |
3587 | for_each_pipe(pipe) { |
3590 | for_each_pipe(pipe) { |
3588 | I915_WRITE(TRANS_CHICKEN1(pipe), |
3591 | I915_WRITE(TRANS_CHICKEN1(pipe), |
3589 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
3592 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
3590 | } |
3593 | } |
3591 | } |
3594 | } |
- | 3595 | ||
- | 3596 | static void gen6_check_mch_setup(struct drm_device *dev) |
|
- | 3597 | { |
|
- | 3598 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3599 | uint32_t tmp; |
|
- | 3600 | ||
- | 3601 | tmp = I915_READ(MCH_SSKPD); |
|
- | 3602 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { |
|
- | 3603 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); |
|
- | 3604 | DRM_INFO("This can cause pipe underruns and display issues.\n"); |
|
- | 3605 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); |
|
- | 3606 | } |
|
- | 3607 | } |
|
3592 | 3608 | ||
3593 | static void gen6_init_clock_gating(struct drm_device *dev) |
3609 | static void gen6_init_clock_gating(struct drm_device *dev) |
3594 | { |
3610 | { |
3595 | struct drm_i915_private *dev_priv = dev->dev_private; |
3611 | struct drm_i915_private *dev_priv = dev->dev_private; |
3596 | int pipe; |
3612 | int pipe; |
3597 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3613 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3598 | 3614 | ||
3599 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3615 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3600 | 3616 | ||
3601 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3617 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3602 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3618 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3603 | ILK_ELPIN_409_SELECT); |
3619 | ILK_ELPIN_409_SELECT); |
3604 | 3620 | ||
3605 | /* WaDisableHiZPlanesWhenMSAAEnabled */ |
3621 | /* WaDisableHiZPlanesWhenMSAAEnabled */ |
3606 | I915_WRITE(_3D_CHICKEN, |
3622 | I915_WRITE(_3D_CHICKEN, |
3607 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
3623 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
3608 | 3624 | ||
3609 | /* WaSetupGtModeTdRowDispatch */ |
3625 | /* WaSetupGtModeTdRowDispatch */ |
3610 | if (IS_SNB_GT1(dev)) |
3626 | if (IS_SNB_GT1(dev)) |
3611 | I915_WRITE(GEN6_GT_MODE, |
3627 | I915_WRITE(GEN6_GT_MODE, |
3612 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
3628 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
3613 | 3629 | ||
3614 | I915_WRITE(WM3_LP_ILK, 0); |
3630 | I915_WRITE(WM3_LP_ILK, 0); |
3615 | I915_WRITE(WM2_LP_ILK, 0); |
3631 | I915_WRITE(WM2_LP_ILK, 0); |
3616 | I915_WRITE(WM1_LP_ILK, 0); |
3632 | I915_WRITE(WM1_LP_ILK, 0); |
3617 | 3633 | ||
3618 | I915_WRITE(CACHE_MODE_0, |
3634 | I915_WRITE(CACHE_MODE_0, |
3619 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
3635 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
3620 | 3636 | ||
3621 | I915_WRITE(GEN6_UCGCTL1, |
3637 | I915_WRITE(GEN6_UCGCTL1, |
3622 | I915_READ(GEN6_UCGCTL1) | |
3638 | I915_READ(GEN6_UCGCTL1) | |
3623 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
3639 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
3624 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
3640 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
3625 | 3641 | ||
3626 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3642 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3627 | * gating disable must be set. Failure to set it results in |
3643 | * gating disable must be set. Failure to set it results in |
3628 | * flickering pixels due to Z write ordering failures after |
3644 | * flickering pixels due to Z write ordering failures after |
3629 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3645 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3630 | * Sanctuary and Tropics, and apparently anything else with |
3646 | * Sanctuary and Tropics, and apparently anything else with |
3631 | * alpha test or pixel discard. |
3647 | * alpha test or pixel discard. |
3632 | * |
3648 | * |
3633 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3649 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3634 | * but we didn't debug actual testcases to find it out. |
3650 | * but we didn't debug actual testcases to find it out. |
3635 | * |
3651 | * |
3636 | * Also apply WaDisableVDSUnitClockGating and |
3652 | * Also apply WaDisableVDSUnitClockGating and |
3637 | * WaDisableRCPBUnitClockGating. |
3653 | * WaDisableRCPBUnitClockGating. |
3638 | */ |
3654 | */ |
3639 | I915_WRITE(GEN6_UCGCTL2, |
3655 | I915_WRITE(GEN6_UCGCTL2, |
3640 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3656 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3641 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3657 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3642 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3658 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3643 | 3659 | ||
3644 | /* Bspec says we need to always set all mask bits. */ |
3660 | /* Bspec says we need to always set all mask bits. */ |
3645 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3661 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3646 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
3662 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
3647 | 3663 | ||
3648 | /* |
3664 | /* |
3649 | * According to the spec the following bits should be |
3665 | * According to the spec the following bits should be |
3650 | * set in order to enable memory self-refresh and fbc: |
3666 | * set in order to enable memory self-refresh and fbc: |
3651 | * The bit21 and bit22 of 0x42000 |
3667 | * The bit21 and bit22 of 0x42000 |
3652 | * The bit21 and bit22 of 0x42004 |
3668 | * The bit21 and bit22 of 0x42004 |
3653 | * The bit5 and bit7 of 0x42020 |
3669 | * The bit5 and bit7 of 0x42020 |
3654 | * The bit14 of 0x70180 |
3670 | * The bit14 of 0x70180 |
3655 | * The bit14 of 0x71180 |
3671 | * The bit14 of 0x71180 |
3656 | */ |
3672 | */ |
3657 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3673 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3658 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3674 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3659 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
3675 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
3660 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3676 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3661 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3677 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3662 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
3678 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
3663 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3679 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3664 | I915_READ(ILK_DSPCLK_GATE_D) | |
3680 | I915_READ(ILK_DSPCLK_GATE_D) | |
3665 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
3681 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
3666 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
3682 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
3667 | 3683 | ||
3668 | /* WaMbcDriverBootEnable */ |
3684 | /* WaMbcDriverBootEnable */ |
3669 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3685 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3670 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3686 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3671 | 3687 | ||
3672 | for_each_pipe(pipe) { |
3688 | for_each_pipe(pipe) { |
3673 | I915_WRITE(DSPCNTR(pipe), |
3689 | I915_WRITE(DSPCNTR(pipe), |
3674 | I915_READ(DSPCNTR(pipe)) | |
3690 | I915_READ(DSPCNTR(pipe)) | |
3675 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3691 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3676 | intel_flush_display_plane(dev_priv, pipe); |
3692 | intel_flush_display_plane(dev_priv, pipe); |
3677 | } |
3693 | } |
3678 | 3694 | ||
3679 | /* The default value should be 0x200 according to docs, but the two |
3695 | /* The default value should be 0x200 according to docs, but the two |
3680 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3696 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3681 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3697 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3682 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
3698 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
3683 | 3699 | ||
3684 | cpt_init_clock_gating(dev); |
3700 | cpt_init_clock_gating(dev); |
- | 3701 | ||
- | 3702 | gen6_check_mch_setup(dev); |
|
3685 | } |
3703 | } |
3686 | 3704 | ||
3687 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
3705 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
3688 | { |
3706 | { |
3689 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
3707 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
3690 | 3708 | ||
3691 | reg &= ~GEN7_FF_SCHED_MASK; |
3709 | reg &= ~GEN7_FF_SCHED_MASK; |
3692 | reg |= GEN7_FF_TS_SCHED_HW; |
3710 | reg |= GEN7_FF_TS_SCHED_HW; |
3693 | reg |= GEN7_FF_VS_SCHED_HW; |
3711 | reg |= GEN7_FF_VS_SCHED_HW; |
3694 | reg |= GEN7_FF_DS_SCHED_HW; |
3712 | reg |= GEN7_FF_DS_SCHED_HW; |
- | 3713 | ||
- | 3714 | /* WaVSRefCountFullforceMissDisable */ |
|
- | 3715 | if (IS_HASWELL(dev_priv->dev)) |
|
- | 3716 | reg &= ~GEN7_FF_VS_REF_CNT_FFME; |
|
3695 | 3717 | ||
3696 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3718 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3697 | } |
3719 | } |
3698 | 3720 | ||
3699 | static void lpt_init_clock_gating(struct drm_device *dev) |
3721 | static void lpt_init_clock_gating(struct drm_device *dev) |
3700 | { |
3722 | { |
3701 | struct drm_i915_private *dev_priv = dev->dev_private; |
3723 | struct drm_i915_private *dev_priv = dev->dev_private; |
3702 | 3724 | ||
3703 | /* |
3725 | /* |
3704 | * TODO: this bit should only be enabled when really needed, then |
3726 | * TODO: this bit should only be enabled when really needed, then |
3705 | * disabled when not needed anymore in order to save power. |
3727 | * disabled when not needed anymore in order to save power. |
3706 | */ |
3728 | */ |
3707 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
3729 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
3708 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
3730 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
3709 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
3731 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
3710 | PCH_LP_PARTITION_LEVEL_DISABLE); |
3732 | PCH_LP_PARTITION_LEVEL_DISABLE); |
3711 | } |
3733 | } |
3712 | 3734 | ||
3713 | static void haswell_init_clock_gating(struct drm_device *dev) |
3735 | static void haswell_init_clock_gating(struct drm_device *dev) |
3714 | { |
3736 | { |
3715 | struct drm_i915_private *dev_priv = dev->dev_private; |
3737 | struct drm_i915_private *dev_priv = dev->dev_private; |
3716 | int pipe; |
3738 | int pipe; |
3717 | 3739 | ||
3718 | I915_WRITE(WM3_LP_ILK, 0); |
3740 | I915_WRITE(WM3_LP_ILK, 0); |
3719 | I915_WRITE(WM2_LP_ILK, 0); |
3741 | I915_WRITE(WM2_LP_ILK, 0); |
3720 | I915_WRITE(WM1_LP_ILK, 0); |
3742 | I915_WRITE(WM1_LP_ILK, 0); |
3721 | 3743 | ||
3722 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3744 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3723 | * This implements the WaDisableRCZUnitClockGating workaround. |
3745 | * This implements the WaDisableRCZUnitClockGating workaround. |
3724 | */ |
3746 | */ |
3725 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
3747 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
3726 | 3748 | ||
3727 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3749 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3728 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3750 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3729 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3751 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3730 | 3752 | ||
3731 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3753 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3732 | I915_WRITE(GEN7_L3CNTLREG1, |
3754 | I915_WRITE(GEN7_L3CNTLREG1, |
3733 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3755 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3734 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3756 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3735 | GEN7_WA_L3_CHICKEN_MODE); |
3757 | GEN7_WA_L3_CHICKEN_MODE); |
3736 | 3758 | ||
3737 | /* This is required by WaCatErrorRejectionIssue */ |
3759 | /* This is required by WaCatErrorRejectionIssue */ |
3738 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3760 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3739 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3761 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3740 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3762 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3741 | 3763 | ||
3742 | for_each_pipe(pipe) { |
3764 | for_each_pipe(pipe) { |
3743 | I915_WRITE(DSPCNTR(pipe), |
3765 | I915_WRITE(DSPCNTR(pipe), |
3744 | I915_READ(DSPCNTR(pipe)) | |
3766 | I915_READ(DSPCNTR(pipe)) | |
3745 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3767 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3746 | intel_flush_display_plane(dev_priv, pipe); |
3768 | intel_flush_display_plane(dev_priv, pipe); |
3747 | } |
3769 | } |
3748 | 3770 | ||
3749 | gen7_setup_fixed_func_scheduler(dev_priv); |
3771 | gen7_setup_fixed_func_scheduler(dev_priv); |
3750 | 3772 | ||
3751 | /* WaDisable4x2SubspanOptimization */ |
3773 | /* WaDisable4x2SubspanOptimization */ |
3752 | I915_WRITE(CACHE_MODE_1, |
3774 | I915_WRITE(CACHE_MODE_1, |
3753 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3775 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3754 | 3776 | ||
3755 | /* WaMbcDriverBootEnable */ |
3777 | /* WaMbcDriverBootEnable */ |
3756 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3778 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3757 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3779 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3758 | 3780 | ||
3759 | /* XXX: This is a workaround for early silicon revisions and should be |
3781 | /* XXX: This is a workaround for early silicon revisions and should be |
3760 | * removed later. |
3782 | * removed later. |
3761 | */ |
3783 | */ |
3762 | I915_WRITE(WM_DBG, |
3784 | I915_WRITE(WM_DBG, |
3763 | I915_READ(WM_DBG) | |
3785 | I915_READ(WM_DBG) | |
3764 | WM_DBG_DISALLOW_MULTIPLE_LP | |
3786 | WM_DBG_DISALLOW_MULTIPLE_LP | |
3765 | WM_DBG_DISALLOW_SPRITE | |
3787 | WM_DBG_DISALLOW_SPRITE | |
3766 | WM_DBG_DISALLOW_MAXFIFO); |
3788 | WM_DBG_DISALLOW_MAXFIFO); |
3767 | 3789 | ||
3768 | lpt_init_clock_gating(dev); |
3790 | lpt_init_clock_gating(dev); |
3769 | } |
3791 | } |
3770 | 3792 | ||
3771 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
3793 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
3772 | { |
3794 | { |
3773 | struct drm_i915_private *dev_priv = dev->dev_private; |
3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
3774 | int pipe; |
3796 | int pipe; |
3775 | uint32_t snpcr; |
3797 | uint32_t snpcr; |
3776 | 3798 | ||
3777 | I915_WRITE(WM3_LP_ILK, 0); |
3799 | I915_WRITE(WM3_LP_ILK, 0); |
3778 | I915_WRITE(WM2_LP_ILK, 0); |
3800 | I915_WRITE(WM2_LP_ILK, 0); |
3779 | I915_WRITE(WM1_LP_ILK, 0); |
3801 | I915_WRITE(WM1_LP_ILK, 0); |
3780 | 3802 | ||
3781 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3803 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3782 | 3804 | ||
3783 | /* WaDisableEarlyCull */ |
3805 | /* WaDisableEarlyCull */ |
3784 | I915_WRITE(_3D_CHICKEN3, |
3806 | I915_WRITE(_3D_CHICKEN3, |
3785 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
3807 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
3786 | 3808 | ||
3787 | /* WaDisableBackToBackFlipFix */ |
3809 | /* WaDisableBackToBackFlipFix */ |
3788 | I915_WRITE(IVB_CHICKEN3, |
3810 | I915_WRITE(IVB_CHICKEN3, |
3789 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3811 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3790 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3812 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3791 | 3813 | ||
3792 | /* WaDisablePSDDualDispatchEnable */ |
3814 | /* WaDisablePSDDualDispatchEnable */ |
3793 | if (IS_IVB_GT1(dev)) |
3815 | if (IS_IVB_GT1(dev)) |
3794 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
3816 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
3795 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3817 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3796 | else |
3818 | else |
3797 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, |
3819 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, |
3798 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3820 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3799 | 3821 | ||
3800 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3822 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3801 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3823 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3802 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3824 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3803 | 3825 | ||
3804 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3826 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3805 | I915_WRITE(GEN7_L3CNTLREG1, |
3827 | I915_WRITE(GEN7_L3CNTLREG1, |
3806 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3828 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3807 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3829 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3808 | GEN7_WA_L3_CHICKEN_MODE); |
3830 | GEN7_WA_L3_CHICKEN_MODE); |
3809 | if (IS_IVB_GT1(dev)) |
3831 | if (IS_IVB_GT1(dev)) |
3810 | I915_WRITE(GEN7_ROW_CHICKEN2, |
3832 | I915_WRITE(GEN7_ROW_CHICKEN2, |
3811 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3833 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3812 | else |
3834 | else |
3813 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
3835 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
3814 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3836 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3815 | 3837 | ||
3816 | 3838 | ||
3817 | /* WaForceL3Serialization */ |
3839 | /* WaForceL3Serialization */ |
3818 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3840 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3819 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3841 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3820 | 3842 | ||
3821 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3843 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3822 | * gating disable must be set. Failure to set it results in |
3844 | * gating disable must be set. Failure to set it results in |
3823 | * flickering pixels due to Z write ordering failures after |
3845 | * flickering pixels due to Z write ordering failures after |
3824 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3846 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3825 | * Sanctuary and Tropics, and apparently anything else with |
3847 | * Sanctuary and Tropics, and apparently anything else with |
3826 | * alpha test or pixel discard. |
3848 | * alpha test or pixel discard. |
3827 | * |
3849 | * |
3828 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3850 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3829 | * but we didn't debug actual testcases to find it out. |
3851 | * but we didn't debug actual testcases to find it out. |
3830 | * |
3852 | * |
3831 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3853 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3832 | * This implements the WaDisableRCZUnitClockGating workaround. |
3854 | * This implements the WaDisableRCZUnitClockGating workaround. |
3833 | */ |
3855 | */ |
3834 | I915_WRITE(GEN6_UCGCTL2, |
3856 | I915_WRITE(GEN6_UCGCTL2, |
3835 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3857 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3836 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3858 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3837 | 3859 | ||
3838 | /* This is required by WaCatErrorRejectionIssue */ |
3860 | /* This is required by WaCatErrorRejectionIssue */ |
3839 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3861 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3840 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3862 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3841 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3863 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3842 | 3864 | ||
3843 | for_each_pipe(pipe) { |
3865 | for_each_pipe(pipe) { |
3844 | I915_WRITE(DSPCNTR(pipe), |
3866 | I915_WRITE(DSPCNTR(pipe), |
3845 | I915_READ(DSPCNTR(pipe)) | |
3867 | I915_READ(DSPCNTR(pipe)) | |
3846 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3868 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3847 | intel_flush_display_plane(dev_priv, pipe); |
3869 | intel_flush_display_plane(dev_priv, pipe); |
3848 | } |
3870 | } |
3849 | 3871 | ||
3850 | /* WaMbcDriverBootEnable */ |
3872 | /* WaMbcDriverBootEnable */ |
3851 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3873 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3852 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3874 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3853 | 3875 | ||
3854 | gen7_setup_fixed_func_scheduler(dev_priv); |
3876 | gen7_setup_fixed_func_scheduler(dev_priv); |
3855 | 3877 | ||
3856 | /* WaDisable4x2SubspanOptimization */ |
3878 | /* WaDisable4x2SubspanOptimization */ |
3857 | I915_WRITE(CACHE_MODE_1, |
3879 | I915_WRITE(CACHE_MODE_1, |
3858 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3880 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3859 | 3881 | ||
3860 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
3882 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
3861 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3883 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3862 | snpcr |= GEN6_MBC_SNPCR_MED; |
3884 | snpcr |= GEN6_MBC_SNPCR_MED; |
3863 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
3885 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
3864 | 3886 | ||
3865 | cpt_init_clock_gating(dev); |
3887 | cpt_init_clock_gating(dev); |
- | 3888 | ||
- | 3889 | gen6_check_mch_setup(dev); |
|
3866 | } |
3890 | } |
3867 | 3891 | ||
3868 | static void valleyview_init_clock_gating(struct drm_device *dev) |
3892 | static void valleyview_init_clock_gating(struct drm_device *dev) |
3869 | { |
3893 | { |
3870 | struct drm_i915_private *dev_priv = dev->dev_private; |
3894 | struct drm_i915_private *dev_priv = dev->dev_private; |
3871 | int pipe; |
3895 | int pipe; |
3872 | 3896 | ||
3873 | I915_WRITE(WM3_LP_ILK, 0); |
3897 | I915_WRITE(WM3_LP_ILK, 0); |
3874 | I915_WRITE(WM2_LP_ILK, 0); |
3898 | I915_WRITE(WM2_LP_ILK, 0); |
3875 | I915_WRITE(WM1_LP_ILK, 0); |
3899 | I915_WRITE(WM1_LP_ILK, 0); |
3876 | 3900 | ||
3877 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3901 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3878 | 3902 | ||
3879 | /* WaDisableEarlyCull */ |
3903 | /* WaDisableEarlyCull */ |
3880 | I915_WRITE(_3D_CHICKEN3, |
3904 | I915_WRITE(_3D_CHICKEN3, |
3881 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
3905 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
3882 | 3906 | ||
3883 | /* WaDisableBackToBackFlipFix */ |
3907 | /* WaDisableBackToBackFlipFix */ |
3884 | I915_WRITE(IVB_CHICKEN3, |
3908 | I915_WRITE(IVB_CHICKEN3, |
3885 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3909 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3886 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3910 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3887 | 3911 | ||
3888 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
3912 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
3889 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3913 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
3890 | 3914 | ||
3891 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3915 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3892 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3916 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3893 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3917 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3894 | 3918 | ||
3895 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3919 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3896 | I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); |
3920 | I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); |
3897 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
3921 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
3898 | 3922 | ||
3899 | /* WaForceL3Serialization */ |
3923 | /* WaForceL3Serialization */ |
3900 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3924 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3901 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3925 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3902 | 3926 | ||
3903 | /* WaDisableDopClockGating */ |
3927 | /* WaDisableDopClockGating */ |
3904 | I915_WRITE(GEN7_ROW_CHICKEN2, |
3928 | I915_WRITE(GEN7_ROW_CHICKEN2, |
3905 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3929 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
3906 | 3930 | ||
3907 | /* WaForceL3Serialization */ |
3931 | /* WaForceL3Serialization */ |
3908 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3932 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
3909 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3933 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
3910 | 3934 | ||
3911 | /* This is required by WaCatErrorRejectionIssue */ |
3935 | /* This is required by WaCatErrorRejectionIssue */ |
3912 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3936 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3913 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3937 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3914 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3938 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3915 | 3939 | ||
3916 | /* WaMbcDriverBootEnable */ |
3940 | /* WaMbcDriverBootEnable */ |
3917 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3941 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3918 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3942 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3919 | 3943 | ||
3920 | 3944 | ||
3921 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3945 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3922 | * gating disable must be set. Failure to set it results in |
3946 | * gating disable must be set. Failure to set it results in |
3923 | * flickering pixels due to Z write ordering failures after |
3947 | * flickering pixels due to Z write ordering failures after |
3924 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3948 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3925 | * Sanctuary and Tropics, and apparently anything else with |
3949 | * Sanctuary and Tropics, and apparently anything else with |
3926 | * alpha test or pixel discard. |
3950 | * alpha test or pixel discard. |
3927 | * |
3951 | * |
3928 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3952 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3929 | * but we didn't debug actual testcases to find it out. |
3953 | * but we didn't debug actual testcases to find it out. |
3930 | * |
3954 | * |
3931 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3955 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3932 | * This implements the WaDisableRCZUnitClockGating workaround. |
3956 | * This implements the WaDisableRCZUnitClockGating workaround. |
3933 | * |
3957 | * |
3934 | * Also apply WaDisableVDSUnitClockGating and |
3958 | * Also apply WaDisableVDSUnitClockGating and |
3935 | * WaDisableRCPBUnitClockGating. |
3959 | * WaDisableRCPBUnitClockGating. |
3936 | */ |
3960 | */ |
3937 | I915_WRITE(GEN6_UCGCTL2, |
3961 | I915_WRITE(GEN6_UCGCTL2, |
3938 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3962 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3939 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
3963 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
3940 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3964 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3941 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3965 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3942 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3966 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3943 | 3967 | ||
3944 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
3968 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
3945 | 3969 | ||
3946 | for_each_pipe(pipe) { |
3970 | for_each_pipe(pipe) { |
3947 | I915_WRITE(DSPCNTR(pipe), |
3971 | I915_WRITE(DSPCNTR(pipe), |
3948 | I915_READ(DSPCNTR(pipe)) | |
3972 | I915_READ(DSPCNTR(pipe)) | |
3949 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3973 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3950 | intel_flush_display_plane(dev_priv, pipe); |
3974 | intel_flush_display_plane(dev_priv, pipe); |
3951 | } |
3975 | } |
3952 | 3976 | ||
3953 | I915_WRITE(CACHE_MODE_1, |
3977 | I915_WRITE(CACHE_MODE_1, |
3954 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3978 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3955 | 3979 | ||
3956 | /* |
3980 | /* |
3957 | * On ValleyView, the GUnit needs to signal the GT |
3981 | * On ValleyView, the GUnit needs to signal the GT |
3958 | * when flip and other events complete. So enable |
3982 | * when flip and other events complete. So enable |
3959 | * all the GUnit->GT interrupts here |
3983 | * all the GUnit->GT interrupts here |
3960 | */ |
3984 | */ |
3961 | I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | |
3985 | I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | |
3962 | PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | |
3986 | PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | |
3963 | SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | |
3987 | SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | |
3964 | PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | |
3988 | PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | |
3965 | PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | |
3989 | PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | |
3966 | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | |
3990 | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | |
3967 | PLANEA_FLIPDONE_INT_EN); |
3991 | PLANEA_FLIPDONE_INT_EN); |
3968 | 3992 | ||
3969 | /* |
3993 | /* |
3970 | * WaDisableVLVClockGating_VBIIssue |
3994 | * WaDisableVLVClockGating_VBIIssue |
3971 | * Disable clock gating on th GCFG unit to prevent a delay |
3995 | * Disable clock gating on th GCFG unit to prevent a delay |
3972 | * in the reporting of vblank events. |
3996 | * in the reporting of vblank events. |
3973 | */ |
3997 | */ |
3974 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
3998 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
3975 | } |
3999 | } |
3976 | 4000 | ||
3977 | static void g4x_init_clock_gating(struct drm_device *dev) |
4001 | static void g4x_init_clock_gating(struct drm_device *dev) |
3978 | { |
4002 | { |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; |
4003 | struct drm_i915_private *dev_priv = dev->dev_private; |
3980 | uint32_t dspclk_gate; |
4004 | uint32_t dspclk_gate; |
3981 | 4005 | ||
3982 | I915_WRITE(RENCLK_GATE_D1, 0); |
4006 | I915_WRITE(RENCLK_GATE_D1, 0); |
3983 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
4007 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
3984 | GS_UNIT_CLOCK_GATE_DISABLE | |
4008 | GS_UNIT_CLOCK_GATE_DISABLE | |
3985 | CL_UNIT_CLOCK_GATE_DISABLE); |
4009 | CL_UNIT_CLOCK_GATE_DISABLE); |
3986 | I915_WRITE(RAMCLK_GATE_D, 0); |
4010 | I915_WRITE(RAMCLK_GATE_D, 0); |
3987 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
4011 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
3988 | OVRUNIT_CLOCK_GATE_DISABLE | |
4012 | OVRUNIT_CLOCK_GATE_DISABLE | |
3989 | OVCUNIT_CLOCK_GATE_DISABLE; |
4013 | OVCUNIT_CLOCK_GATE_DISABLE; |
3990 | if (IS_GM45(dev)) |
4014 | if (IS_GM45(dev)) |
3991 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
4015 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
3992 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
4016 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
3993 | 4017 | ||
3994 | /* WaDisableRenderCachePipelinedFlush */ |
4018 | /* WaDisableRenderCachePipelinedFlush */ |
3995 | I915_WRITE(CACHE_MODE_0, |
4019 | I915_WRITE(CACHE_MODE_0, |
3996 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
4020 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
3997 | } |
4021 | } |
3998 | 4022 | ||
3999 | static void crestline_init_clock_gating(struct drm_device *dev) |
4023 | static void crestline_init_clock_gating(struct drm_device *dev) |
4000 | { |
4024 | { |
4001 | struct drm_i915_private *dev_priv = dev->dev_private; |
4025 | struct drm_i915_private *dev_priv = dev->dev_private; |
4002 | 4026 | ||
4003 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
4027 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
4004 | I915_WRITE(RENCLK_GATE_D2, 0); |
4028 | I915_WRITE(RENCLK_GATE_D2, 0); |
4005 | I915_WRITE(DSPCLK_GATE_D, 0); |
4029 | I915_WRITE(DSPCLK_GATE_D, 0); |
4006 | I915_WRITE(RAMCLK_GATE_D, 0); |
4030 | I915_WRITE(RAMCLK_GATE_D, 0); |
4007 | I915_WRITE16(DEUC, 0); |
4031 | I915_WRITE16(DEUC, 0); |
4008 | } |
4032 | } |
4009 | 4033 | ||
4010 | static void broadwater_init_clock_gating(struct drm_device *dev) |
4034 | static void broadwater_init_clock_gating(struct drm_device *dev) |
4011 | { |
4035 | { |
4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
4036 | struct drm_i915_private *dev_priv = dev->dev_private; |
4013 | 4037 | ||
4014 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
4038 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
4015 | I965_RCC_CLOCK_GATE_DISABLE | |
4039 | I965_RCC_CLOCK_GATE_DISABLE | |
4016 | I965_RCPB_CLOCK_GATE_DISABLE | |
4040 | I965_RCPB_CLOCK_GATE_DISABLE | |
4017 | I965_ISC_CLOCK_GATE_DISABLE | |
4041 | I965_ISC_CLOCK_GATE_DISABLE | |
4018 | I965_FBC_CLOCK_GATE_DISABLE); |
4042 | I965_FBC_CLOCK_GATE_DISABLE); |
4019 | I915_WRITE(RENCLK_GATE_D2, 0); |
4043 | I915_WRITE(RENCLK_GATE_D2, 0); |
4020 | } |
4044 | } |
4021 | 4045 | ||
4022 | static void gen3_init_clock_gating(struct drm_device *dev) |
4046 | static void gen3_init_clock_gating(struct drm_device *dev) |
4023 | { |
4047 | { |
4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
4048 | struct drm_i915_private *dev_priv = dev->dev_private; |
4025 | u32 dstate = I915_READ(D_STATE); |
4049 | u32 dstate = I915_READ(D_STATE); |
4026 | 4050 | ||
4027 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
4051 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
4028 | DSTATE_DOT_CLOCK_GATING; |
4052 | DSTATE_DOT_CLOCK_GATING; |
4029 | I915_WRITE(D_STATE, dstate); |
4053 | I915_WRITE(D_STATE, dstate); |
4030 | 4054 | ||
4031 | if (IS_PINEVIEW(dev)) |
4055 | if (IS_PINEVIEW(dev)) |
4032 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
4056 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
4033 | 4057 | ||
4034 | /* IIR "flip pending" means done if this bit is set */ |
4058 | /* IIR "flip pending" means done if this bit is set */ |
4035 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
4059 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
4036 | } |
4060 | } |
4037 | 4061 | ||
4038 | static void i85x_init_clock_gating(struct drm_device *dev) |
4062 | static void i85x_init_clock_gating(struct drm_device *dev) |
4039 | { |
4063 | { |
4040 | struct drm_i915_private *dev_priv = dev->dev_private; |
4064 | struct drm_i915_private *dev_priv = dev->dev_private; |
4041 | 4065 | ||
4042 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
4066 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
4043 | } |
4067 | } |
4044 | 4068 | ||
4045 | static void i830_init_clock_gating(struct drm_device *dev) |
4069 | static void i830_init_clock_gating(struct drm_device *dev) |
4046 | { |
4070 | { |
4047 | struct drm_i915_private *dev_priv = dev->dev_private; |
4071 | struct drm_i915_private *dev_priv = dev->dev_private; |
4048 | 4072 | ||
4049 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
4073 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
4050 | } |
4074 | } |
4051 | 4075 | ||
4052 | void intel_init_clock_gating(struct drm_device *dev) |
4076 | void intel_init_clock_gating(struct drm_device *dev) |
4053 | { |
4077 | { |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
4078 | struct drm_i915_private *dev_priv = dev->dev_private; |
4055 | 4079 | ||
4056 | dev_priv->display.init_clock_gating(dev); |
4080 | dev_priv->display.init_clock_gating(dev); |
4057 | } |
4081 | } |
4058 | - | ||
4059 | /* Starting with Haswell, we have different power wells for |
- | |
4060 | * different parts of the GPU. This attempts to enable them all. |
- | |
4061 | */ |
4082 | |
4062 | void intel_init_power_wells(struct drm_device *dev) |
4083 | void intel_set_power_well(struct drm_device *dev, bool enable) |
4063 | { |
4084 | { |
4064 | struct drm_i915_private *dev_priv = dev->dev_private; |
4085 | struct drm_i915_private *dev_priv = dev->dev_private; |
4065 | unsigned long power_wells[] = { |
- | |
4066 | HSW_PWR_WELL_CTL1, |
- | |
4067 | HSW_PWR_WELL_CTL2, |
- | |
4068 | HSW_PWR_WELL_CTL4 |
- | |
4069 | }; |
4086 | bool is_enabled, enable_requested; |
4070 | int i; |
4087 | uint32_t tmp; |
4071 | 4088 | ||
4072 | if (!IS_HASWELL(dev)) |
4089 | if (!IS_HASWELL(dev)) |
4073 | return; |
4090 | return; |
4074 | 4091 | ||
- | 4092 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
|
- | 4093 | is_enabled = tmp & HSW_PWR_WELL_STATE; |
|
4075 | mutex_lock(&dev->struct_mutex); |
4094 | enable_requested = tmp & HSW_PWR_WELL_ENABLE; |
- | 4095 | ||
4076 | 4096 | if (enable) { |
|
4077 | for (i = 0; i < ARRAY_SIZE(power_wells); i++) { |
4097 | if (!enable_requested) |
4078 | int well = I915_READ(power_wells[i]); |
4098 | I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); |
- | 4099 | ||
- | 4100 | if (!is_enabled) { |
|
- | 4101 | DRM_DEBUG_KMS("Enabling power well\n"); |
|
4079 | 4102 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
|
4080 | if ((well & HSW_PWR_WELL_STATE) == 0) { |
4103 | HSW_PWR_WELL_STATE), 20)) |
- | 4104 | DRM_ERROR("Timeout enabling power well\n"); |
|
- | 4105 | } |
|
- | 4106 | } else { |
|
4081 | I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); |
4107 | if (enable_requested) { |
4082 | if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) |
4108 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
4083 | DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); |
4109 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
4084 | } |
4110 | } |
- | 4111 | } |
|
- | 4112 | } |
|
- | 4113 | ||
- | 4114 | /* |
|
- | 4115 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
|
- | 4116 | * when not needed anymore. We have 4 registers that can request the power well |
|
- | 4117 | * to be enabled, and it will only be disabled if none of the registers is |
|
- | 4118 | * requesting it to be enabled. |
|
- | 4119 | */ |
|
- | 4120 | void intel_init_power_well(struct drm_device *dev) |
|
- | 4121 | { |
|
- | 4122 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4123 | ||
- | 4124 | if (!IS_HASWELL(dev)) |
|
- | 4125 | return; |
|
- | 4126 | ||
- | 4127 | /* For now, we need the power well to be always enabled. */ |
|
- | 4128 | intel_set_power_well(dev, true); |
|
- | 4129 | ||
- | 4130 | /* We're taking over the BIOS, so clear any requests made by it since |
|
4085 | } |
4131 | * the driver is in charge now. */ |
4086 | 4132 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) |
|
4087 | mutex_unlock(&dev->struct_mutex); |
4133 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
4088 | } |
4134 | } |
4089 | 4135 | ||
4090 | /* Set up chip specific power management-related functions */ |
4136 | /* Set up chip specific power management-related functions */ |
4091 | void intel_init_pm(struct drm_device *dev) |
4137 | void intel_init_pm(struct drm_device *dev) |
4092 | { |
4138 | { |
4093 | struct drm_i915_private *dev_priv = dev->dev_private; |
4139 | struct drm_i915_private *dev_priv = dev->dev_private; |
4094 | 4140 | ||
4095 | if (I915_HAS_FBC(dev)) { |
4141 | if (I915_HAS_FBC(dev)) { |
4096 | if (HAS_PCH_SPLIT(dev)) { |
4142 | if (HAS_PCH_SPLIT(dev)) { |
4097 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
4143 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
4098 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
4144 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
4099 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
4145 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
4100 | } else if (IS_GM45(dev)) { |
4146 | } else if (IS_GM45(dev)) { |
4101 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
4147 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
4102 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
4148 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
4103 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
4149 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
4104 | } else if (IS_CRESTLINE(dev)) { |
4150 | } else if (IS_CRESTLINE(dev)) { |
4105 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
4151 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
4106 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
4152 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
4107 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
4153 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
4108 | } |
4154 | } |
4109 | /* 855GM needs testing */ |
4155 | /* 855GM needs testing */ |
4110 | } |
4156 | } |
4111 | 4157 | ||
4112 | /* For cxsr */ |
4158 | /* For cxsr */ |
4113 | if (IS_PINEVIEW(dev)) |
4159 | if (IS_PINEVIEW(dev)) |
4114 | i915_pineview_get_mem_freq(dev); |
4160 | i915_pineview_get_mem_freq(dev); |
4115 | else if (IS_GEN5(dev)) |
4161 | else if (IS_GEN5(dev)) |
4116 | i915_ironlake_get_mem_freq(dev); |
4162 | i915_ironlake_get_mem_freq(dev); |
4117 | 4163 | ||
4118 | /* For FIFO watermark updates */ |
4164 | /* For FIFO watermark updates */ |
4119 | if (HAS_PCH_SPLIT(dev)) { |
4165 | if (HAS_PCH_SPLIT(dev)) { |
4120 | if (IS_GEN5(dev)) { |
4166 | if (IS_GEN5(dev)) { |
4121 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
4167 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
4122 | dev_priv->display.update_wm = ironlake_update_wm; |
4168 | dev_priv->display.update_wm = ironlake_update_wm; |
4123 | else { |
4169 | else { |
4124 | DRM_DEBUG_KMS("Failed to get proper latency. " |
4170 | DRM_DEBUG_KMS("Failed to get proper latency. " |
4125 | "Disable CxSR\n"); |
4171 | "Disable CxSR\n"); |
4126 | dev_priv->display.update_wm = NULL; |
4172 | dev_priv->display.update_wm = NULL; |
4127 | } |
4173 | } |
4128 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
4174 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
4129 | } else if (IS_GEN6(dev)) { |
4175 | } else if (IS_GEN6(dev)) { |
4130 | if (SNB_READ_WM0_LATENCY()) { |
4176 | if (SNB_READ_WM0_LATENCY()) { |
4131 | dev_priv->display.update_wm = sandybridge_update_wm; |
4177 | dev_priv->display.update_wm = sandybridge_update_wm; |
4132 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4178 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4133 | } else { |
4179 | } else { |
4134 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4180 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4135 | "Disable CxSR\n"); |
4181 | "Disable CxSR\n"); |
4136 | dev_priv->display.update_wm = NULL; |
4182 | dev_priv->display.update_wm = NULL; |
4137 | } |
4183 | } |
4138 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
4184 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
4139 | } else if (IS_IVYBRIDGE(dev)) { |
4185 | } else if (IS_IVYBRIDGE(dev)) { |
4140 | /* FIXME: detect B0+ stepping and use auto training */ |
4186 | /* FIXME: detect B0+ stepping and use auto training */ |
4141 | if (SNB_READ_WM0_LATENCY()) { |
4187 | if (SNB_READ_WM0_LATENCY()) { |
4142 | dev_priv->display.update_wm = ivybridge_update_wm; |
4188 | dev_priv->display.update_wm = ivybridge_update_wm; |
4143 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4189 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4144 | } else { |
4190 | } else { |
4145 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4191 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4146 | "Disable CxSR\n"); |
4192 | "Disable CxSR\n"); |
4147 | dev_priv->display.update_wm = NULL; |
4193 | dev_priv->display.update_wm = NULL; |
4148 | } |
4194 | } |
4149 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
4195 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
4150 | } else if (IS_HASWELL(dev)) { |
4196 | } else if (IS_HASWELL(dev)) { |
4151 | if (SNB_READ_WM0_LATENCY()) { |
4197 | if (SNB_READ_WM0_LATENCY()) { |
4152 | dev_priv->display.update_wm = sandybridge_update_wm; |
4198 | dev_priv->display.update_wm = sandybridge_update_wm; |
4153 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4199 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4154 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
4200 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
4155 | } else { |
4201 | } else { |
4156 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4202 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4157 | "Disable CxSR\n"); |
4203 | "Disable CxSR\n"); |
4158 | dev_priv->display.update_wm = NULL; |
4204 | dev_priv->display.update_wm = NULL; |
4159 | } |
4205 | } |
4160 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
4206 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
4161 | } else |
4207 | } else |
4162 | dev_priv->display.update_wm = NULL; |
4208 | dev_priv->display.update_wm = NULL; |
4163 | } else if (IS_VALLEYVIEW(dev)) { |
4209 | } else if (IS_VALLEYVIEW(dev)) { |
4164 | dev_priv->display.update_wm = valleyview_update_wm; |
4210 | dev_priv->display.update_wm = valleyview_update_wm; |
4165 | dev_priv->display.init_clock_gating = |
4211 | dev_priv->display.init_clock_gating = |
4166 | valleyview_init_clock_gating; |
4212 | valleyview_init_clock_gating; |
4167 | } else if (IS_PINEVIEW(dev)) { |
4213 | } else if (IS_PINEVIEW(dev)) { |
4168 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
4214 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
4169 | dev_priv->is_ddr3, |
4215 | dev_priv->is_ddr3, |
4170 | dev_priv->fsb_freq, |
4216 | dev_priv->fsb_freq, |
4171 | dev_priv->mem_freq)) { |
4217 | dev_priv->mem_freq)) { |
4172 | DRM_INFO("failed to find known CxSR latency " |
4218 | DRM_INFO("failed to find known CxSR latency " |
4173 | "(found ddr%s fsb freq %d, mem freq %d), " |
4219 | "(found ddr%s fsb freq %d, mem freq %d), " |
4174 | "disabling CxSR\n", |
4220 | "disabling CxSR\n", |
4175 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
4221 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
4176 | dev_priv->fsb_freq, dev_priv->mem_freq); |
4222 | dev_priv->fsb_freq, dev_priv->mem_freq); |
4177 | /* Disable CxSR and never update its watermark again */ |
4223 | /* Disable CxSR and never update its watermark again */ |
4178 | pineview_disable_cxsr(dev); |
4224 | pineview_disable_cxsr(dev); |
4179 | dev_priv->display.update_wm = NULL; |
4225 | dev_priv->display.update_wm = NULL; |
4180 | } else |
4226 | } else |
4181 | dev_priv->display.update_wm = pineview_update_wm; |
4227 | dev_priv->display.update_wm = pineview_update_wm; |
4182 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4228 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4183 | } else if (IS_G4X(dev)) { |
4229 | } else if (IS_G4X(dev)) { |
4184 | dev_priv->display.update_wm = g4x_update_wm; |
4230 | dev_priv->display.update_wm = g4x_update_wm; |
4185 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
4231 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
4186 | } else if (IS_GEN4(dev)) { |
4232 | } else if (IS_GEN4(dev)) { |
4187 | dev_priv->display.update_wm = i965_update_wm; |
4233 | dev_priv->display.update_wm = i965_update_wm; |
4188 | if (IS_CRESTLINE(dev)) |
4234 | if (IS_CRESTLINE(dev)) |
4189 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
4235 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
4190 | else if (IS_BROADWATER(dev)) |
4236 | else if (IS_BROADWATER(dev)) |
4191 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
4237 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
4192 | } else if (IS_GEN3(dev)) { |
4238 | } else if (IS_GEN3(dev)) { |
4193 | dev_priv->display.update_wm = i9xx_update_wm; |
4239 | dev_priv->display.update_wm = i9xx_update_wm; |
4194 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
4240 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
4195 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4241 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4196 | } else if (IS_I865G(dev)) { |
4242 | } else if (IS_I865G(dev)) { |
4197 | dev_priv->display.update_wm = i830_update_wm; |
4243 | dev_priv->display.update_wm = i830_update_wm; |
4198 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4244 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4199 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4245 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4200 | } else if (IS_I85X(dev)) { |
4246 | } else if (IS_I85X(dev)) { |
4201 | dev_priv->display.update_wm = i9xx_update_wm; |
4247 | dev_priv->display.update_wm = i9xx_update_wm; |
4202 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
4248 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
4203 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4249 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4204 | } else { |
4250 | } else { |
4205 | dev_priv->display.update_wm = i830_update_wm; |
4251 | dev_priv->display.update_wm = i830_update_wm; |
4206 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
4252 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
4207 | if (IS_845G(dev)) |
4253 | if (IS_845G(dev)) |
4208 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
4254 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
4209 | else |
4255 | else |
4210 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4256 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4211 | } |
4257 | } |
4212 | } |
4258 | } |
4213 | 4259 | ||
4214 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
4260 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
4215 | { |
4261 | { |
4216 | u32 gt_thread_status_mask; |
4262 | u32 gt_thread_status_mask; |
4217 | 4263 | ||
4218 | if (IS_HASWELL(dev_priv->dev)) |
4264 | if (IS_HASWELL(dev_priv->dev)) |
4219 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
4265 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
4220 | else |
4266 | else |
4221 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
4267 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
4222 | 4268 | ||
4223 | /* w/a for a sporadic read returning 0 by waiting for the GT |
4269 | /* w/a for a sporadic read returning 0 by waiting for the GT |
4224 | * thread to wake up. |
4270 | * thread to wake up. |
4225 | */ |
4271 | */ |
4226 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
4272 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
4227 | DRM_ERROR("GT thread status wait timed out\n"); |
4273 | DRM_ERROR("GT thread status wait timed out\n"); |
4228 | } |
4274 | } |
4229 | 4275 | ||
4230 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
4276 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
4231 | { |
4277 | { |
4232 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4278 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4233 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4279 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4234 | } |
4280 | } |
4235 | 4281 | ||
4236 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4282 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4237 | { |
4283 | { |
4238 | u32 forcewake_ack; |
4284 | u32 forcewake_ack; |
4239 | 4285 | ||
4240 | if (IS_HASWELL(dev_priv->dev)) |
4286 | if (IS_HASWELL(dev_priv->dev)) |
4241 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4287 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4242 | else |
4288 | else |
4243 | forcewake_ack = FORCEWAKE_ACK; |
4289 | forcewake_ack = FORCEWAKE_ACK; |
4244 | 4290 | ||
4245 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4291 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4246 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4292 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4247 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4293 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4248 | 4294 | ||
4249 | I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); |
4295 | I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); |
4250 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4296 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4251 | 4297 | ||
4252 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4298 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4253 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4299 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4254 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4300 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4255 | 4301 | ||
4256 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4302 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4257 | } |
4303 | } |
4258 | 4304 | ||
4259 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
4305 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
4260 | { |
4306 | { |
4261 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
4307 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
4262 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4308 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4263 | POSTING_READ(ECOBUS); |
4309 | POSTING_READ(ECOBUS); |
4264 | } |
4310 | } |
4265 | 4311 | ||
4266 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
4312 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
4267 | { |
4313 | { |
4268 | u32 forcewake_ack; |
4314 | u32 forcewake_ack; |
4269 | 4315 | ||
4270 | if (IS_HASWELL(dev_priv->dev)) |
4316 | if (IS_HASWELL(dev_priv->dev)) |
4271 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4317 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4272 | else |
4318 | else |
4273 | forcewake_ack = FORCEWAKE_MT_ACK; |
4319 | forcewake_ack = FORCEWAKE_MT_ACK; |
4274 | 4320 | ||
4275 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4321 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4276 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4322 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4277 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4323 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4278 | 4324 | ||
4279 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
4325 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
4280 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4326 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4281 | POSTING_READ(ECOBUS); |
4327 | POSTING_READ(ECOBUS); |
4282 | 4328 | ||
4283 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4329 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4284 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4330 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4285 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4331 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4286 | 4332 | ||
4287 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4333 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4288 | } |
4334 | } |
4289 | 4335 | ||
4290 | /* |
4336 | /* |
4291 | * Generally this is called implicitly by the register read function. However, |
4337 | * Generally this is called implicitly by the register read function. However, |
4292 | * if some sequence requires the GT to not power down then this function should |
4338 | * if some sequence requires the GT to not power down then this function should |
4293 | * be called at the beginning of the sequence followed by a call to |
4339 | * be called at the beginning of the sequence followed by a call to |
4294 | * gen6_gt_force_wake_put() at the end of the sequence. |
4340 | * gen6_gt_force_wake_put() at the end of the sequence. |
4295 | */ |
4341 | */ |
4296 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4342 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4297 | { |
4343 | { |
4298 | unsigned long irqflags; |
4344 | unsigned long irqflags; |
4299 | 4345 | ||
4300 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4346 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4301 | if (dev_priv->forcewake_count++ == 0) |
4347 | if (dev_priv->forcewake_count++ == 0) |
4302 | dev_priv->gt.force_wake_get(dev_priv); |
4348 | dev_priv->gt.force_wake_get(dev_priv); |
4303 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4349 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4304 | } |
4350 | } |
4305 | 4351 | ||
4306 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
4352 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
4307 | { |
4353 | { |
4308 | u32 gtfifodbg; |
4354 | u32 gtfifodbg; |
4309 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
4355 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
4310 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
4356 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
4311 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
4357 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
4312 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
4358 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
4313 | } |
4359 | } |
4314 | 4360 | ||
4315 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4361 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4316 | { |
4362 | { |
4317 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4363 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4318 | /* something from same cacheline, but !FORCEWAKE */ |
4364 | /* something from same cacheline, but !FORCEWAKE */ |
4319 | POSTING_READ(ECOBUS); |
4365 | POSTING_READ(ECOBUS); |
4320 | gen6_gt_check_fifodbg(dev_priv); |
4366 | gen6_gt_check_fifodbg(dev_priv); |
4321 | } |
4367 | } |
4322 | 4368 | ||
4323 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
4369 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
4324 | { |
4370 | { |
4325 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4371 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4326 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4372 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4327 | POSTING_READ(ECOBUS); |
4373 | POSTING_READ(ECOBUS); |
4328 | gen6_gt_check_fifodbg(dev_priv); |
4374 | gen6_gt_check_fifodbg(dev_priv); |
4329 | } |
4375 | } |
4330 | 4376 | ||
4331 | /* |
4377 | /* |
4332 | * see gen6_gt_force_wake_get() |
4378 | * see gen6_gt_force_wake_get() |
4333 | */ |
4379 | */ |
4334 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4380 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4335 | { |
4381 | { |
4336 | unsigned long irqflags; |
4382 | unsigned long irqflags; |
4337 | 4383 | ||
4338 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4384 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4339 | if (--dev_priv->forcewake_count == 0) |
4385 | if (--dev_priv->forcewake_count == 0) |
4340 | dev_priv->gt.force_wake_put(dev_priv); |
4386 | dev_priv->gt.force_wake_put(dev_priv); |
4341 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4387 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4342 | } |
4388 | } |
4343 | 4389 | ||
4344 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
4390 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
4345 | { |
4391 | { |
4346 | int ret = 0; |
4392 | int ret = 0; |
4347 | 4393 | ||
4348 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
4394 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
4349 | int loop = 500; |
4395 | int loop = 500; |
4350 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4396 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4351 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
4397 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
4352 | udelay(10); |
4398 | udelay(10); |
4353 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4399 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4354 | } |
4400 | } |
4355 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
4401 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
4356 | ++ret; |
4402 | ++ret; |
4357 | dev_priv->gt_fifo_count = fifo; |
4403 | dev_priv->gt_fifo_count = fifo; |
4358 | } |
4404 | } |
4359 | dev_priv->gt_fifo_count--; |
4405 | dev_priv->gt_fifo_count--; |
4360 | 4406 | ||
4361 | return ret; |
4407 | return ret; |
4362 | } |
4408 | } |
4363 | 4409 | ||
4364 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
4410 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
4365 | { |
4411 | { |
4366 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); |
4412 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); |
4367 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
4413 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
4368 | POSTING_READ(FORCEWAKE_ACK_VLV); |
4414 | POSTING_READ(FORCEWAKE_ACK_VLV); |
4369 | } |
4415 | } |
4370 | 4416 | ||
4371 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
4417 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
4372 | { |
4418 | { |
4373 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, |
4419 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, |
4374 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4420 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4375 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4421 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4376 | 4422 | ||
4377 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
4423 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
4378 | 4424 | ||
4379 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), |
4425 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), |
4380 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4426 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4381 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4427 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4382 | 4428 | ||
4383 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4429 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4384 | } |
4430 | } |
4385 | 4431 | ||
4386 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
4432 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
4387 | { |
4433 | { |
4388 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4434 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4389 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
4435 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
4390 | POSTING_READ(FORCEWAKE_ACK_VLV); |
4436 | POSTING_READ(FORCEWAKE_ACK_VLV); |
4391 | gen6_gt_check_fifodbg(dev_priv); |
4437 | gen6_gt_check_fifodbg(dev_priv); |
4392 | } |
4438 | } |
4393 | 4439 | ||
4394 | void intel_gt_reset(struct drm_device *dev) |
4440 | void intel_gt_reset(struct drm_device *dev) |
4395 | { |
4441 | { |
4396 | struct drm_i915_private *dev_priv = dev->dev_private; |
4442 | struct drm_i915_private *dev_priv = dev->dev_private; |
4397 | 4443 | ||
4398 | if (IS_VALLEYVIEW(dev)) { |
4444 | if (IS_VALLEYVIEW(dev)) { |
4399 | vlv_force_wake_reset(dev_priv); |
4445 | vlv_force_wake_reset(dev_priv); |
4400 | } else if (INTEL_INFO(dev)->gen >= 6) { |
4446 | } else if (INTEL_INFO(dev)->gen >= 6) { |
4401 | __gen6_gt_force_wake_reset(dev_priv); |
4447 | __gen6_gt_force_wake_reset(dev_priv); |
4402 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
4448 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
4403 | __gen6_gt_force_wake_mt_reset(dev_priv); |
4449 | __gen6_gt_force_wake_mt_reset(dev_priv); |
4404 | } |
4450 | } |
4405 | } |
4451 | } |
4406 | 4452 | ||
4407 | void intel_gt_init(struct drm_device *dev) |
4453 | void intel_gt_init(struct drm_device *dev) |
4408 | { |
4454 | { |
4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
4455 | struct drm_i915_private *dev_priv = dev->dev_private; |
4410 | 4456 | ||
4411 | spin_lock_init(&dev_priv->gt_lock); |
4457 | spin_lock_init(&dev_priv->gt_lock); |
4412 | 4458 | ||
4413 | intel_gt_reset(dev); |
4459 | intel_gt_reset(dev); |
4414 | 4460 | ||
4415 | if (IS_VALLEYVIEW(dev)) { |
4461 | if (IS_VALLEYVIEW(dev)) { |
4416 | dev_priv->gt.force_wake_get = vlv_force_wake_get; |
4462 | dev_priv->gt.force_wake_get = vlv_force_wake_get; |
4417 | dev_priv->gt.force_wake_put = vlv_force_wake_put; |
4463 | dev_priv->gt.force_wake_put = vlv_force_wake_put; |
4418 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4464 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4419 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; |
4465 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; |
4420 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; |
4466 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; |
4421 | } else if (IS_GEN6(dev)) { |
4467 | } else if (IS_GEN6(dev)) { |
4422 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4468 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4423 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
4469 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
4424 | } |
4470 | } |
4425 | } |
4471 | } |
4426 | 4472 | ||
4427 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4473 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4428 | { |
4474 | { |
4429 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4475 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4430 | 4476 | ||
4431 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
4477 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
4432 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
4478 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
4433 | return -EAGAIN; |
4479 | return -EAGAIN; |
4434 | } |
4480 | } |
4435 | 4481 | ||
4436 | I915_WRITE(GEN6_PCODE_DATA, *val); |
4482 | I915_WRITE(GEN6_PCODE_DATA, *val); |
4437 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
4483 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
4438 | 4484 | ||
4439 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
4485 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
4440 | 500)) { |
4486 | 500)) { |
4441 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
4487 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
4442 | return -ETIMEDOUT; |
4488 | return -ETIMEDOUT; |
4443 | } |
4489 | } |
4444 | 4490 | ||
4445 | *val = I915_READ(GEN6_PCODE_DATA); |
4491 | *val = I915_READ(GEN6_PCODE_DATA); |
4446 | I915_WRITE(GEN6_PCODE_DATA, 0); |
4492 | I915_WRITE(GEN6_PCODE_DATA, 0); |
4447 | 4493 | ||
4448 | return 0; |
4494 | return 0; |
4449 | } |
4495 | } |
4450 | 4496 | ||
4451 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
4497 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
4452 | { |
4498 | { |
4453 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4499 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4454 | 4500 | ||
4455 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
4501 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
4456 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
4502 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
4457 | return -EAGAIN; |
4503 | return -EAGAIN; |
4458 | } |
4504 | } |
4459 | 4505 | ||
4460 | I915_WRITE(GEN6_PCODE_DATA, val); |
4506 | I915_WRITE(GEN6_PCODE_DATA, val); |
4461 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
4507 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
4462 | 4508 | ||
4463 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
4509 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
4464 | 500)) { |
4510 | 500)) { |
4465 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
4511 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
4466 | return -ETIMEDOUT; |
4512 | return -ETIMEDOUT; |
4467 | } |
4513 | } |
4468 | 4514 | ||
4469 | I915_WRITE(GEN6_PCODE_DATA, 0); |
4515 | I915_WRITE(GEN6_PCODE_DATA, 0); |
4470 | 4516 | ||
4471 | return 0; |
4517 | return 0; |
4472 | }=>>=>>>><>><>>><>><>><>>>>>>>>>>=> |
4518 | }=>>=>>><>><>>><>><>><>>>>>>>>>>=> |
4473 | >< |
4519 | >< |
4474 | > |
4520 | > |
4475 | >< |
4521 | >< |
4476 | >><>><>><>><>>> |
4522 | >><>><>><>><>>> |