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Rev 3243 | Rev 3480 | ||
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Line 468... | Line 468... | ||
468 | if (!enable_fbc) { |
468 | if (!enable_fbc) { |
469 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
469 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
470 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
470 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
471 | goto out_disable; |
471 | goto out_disable; |
472 | } |
472 | } |
473 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
- | |
474 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
- | |
475 | "compression\n"); |
- | |
476 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
- | |
477 | goto out_disable; |
- | |
478 | } |
- | |
479 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
473 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
480 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
474 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
481 | DRM_DEBUG_KMS("mode incompatible with compression, " |
475 | DRM_DEBUG_KMS("mode incompatible with compression, " |
482 | "disabling\n"); |
476 | "disabling\n"); |
483 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
477 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
Line 507... | Line 501... | ||
507 | 501 | ||
508 | /* If the kernel debugger is active, always disable compression */ |
502 | /* If the kernel debugger is active, always disable compression */ |
509 | if (in_dbg_master()) |
503 | if (in_dbg_master()) |
Line -... | Line 504... | ||
- | 504 | goto out_disable; |
|
- | 505 | ||
- | 506 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
|
- | 507 | DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size); |
|
- | 508 | DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); |
|
- | 509 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
|
- | 510 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
|
- | 511 | goto out_disable; |
|
510 | goto out_disable; |
512 | } |
511 | 513 | ||
512 | /* If the scanout has not changed, don't modify the FBC settings. |
514 | /* If the scanout has not changed, don't modify the FBC settings. |
513 | * Note that we make the fundamental assumption that the fb->obj |
515 | * Note that we make the fundamental assumption that the fb->obj |
514 | * cannot be unpinned (and have its GTT offset and fence revoked) |
516 | * cannot be unpinned (and have its GTT offset and fence revoked) |
Line 554... | Line 556... | ||
554 | /* Multiple disables should be harmless */ |
556 | /* Multiple disables should be harmless */ |
555 | if (intel_fbc_enabled(dev)) { |
557 | if (intel_fbc_enabled(dev)) { |
556 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
558 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
557 | intel_disable_fbc(dev); |
559 | intel_disable_fbc(dev); |
558 | } |
560 | } |
- | 561 | i915_gem_stolen_cleanup_compression(dev); |
|
559 | } |
562 | } |
Line 560... | Line 563... | ||
560 | 563 | ||
561 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
564 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
562 | { |
565 | { |
Line 2307... | Line 2310... | ||
2307 | 2310 | ||
2308 | err_unpin: |
2311 | err_unpin: |
2309 | i915_gem_object_unpin(ctx); |
2312 | i915_gem_object_unpin(ctx); |
2310 | err_unref: |
2313 | err_unref: |
2311 | drm_gem_object_unreference(&ctx->base); |
- | |
2312 | mutex_unlock(&dev->struct_mutex); |
2314 | drm_gem_object_unreference(&ctx->base); |
2313 | return NULL; |
2315 | return NULL; |
Line 2314... | Line 2316... | ||
2314 | } |
2316 | } |
2315 | 2317 | ||
Line 2593... | Line 2595... | ||
2593 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
2595 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Line 2594... | Line 2596... | ||
2594 | 2596 | ||
2595 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2597 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2596 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2598 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2597 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2599 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2598 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
2600 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Line 2599... | Line 2601... | ||
2599 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2601 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2600 | 2602 | ||
2601 | /* Check if we are enabling RC6 */ |
2603 | /* Check if we are enabling RC6 */ |
Line 3463... | Line 3465... | ||
3463 | if (IS_IRONLAKE_M(dev)) { |
3465 | if (IS_IRONLAKE_M(dev)) { |
3464 | ironlake_disable_drps(dev); |
3466 | ironlake_disable_drps(dev); |
3465 | ironlake_disable_rc6(dev); |
3467 | ironlake_disable_rc6(dev); |
3466 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3468 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3467 | gen6_disable_rps(dev); |
3469 | gen6_disable_rps(dev); |
- | 3470 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
3468 | } |
3471 | } |
3469 | } |
3472 | } |
Line 3470... | Line 3473... | ||
3470 | 3473 | ||
3471 | void intel_enable_gt_powersave(struct drm_device *dev) |
3474 | void intel_enable_gt_powersave(struct drm_device *dev) |
Line 3588... | Line 3591... | ||
3588 | I915_WRITE(TRANS_CHICKEN1(pipe), |
3591 | I915_WRITE(TRANS_CHICKEN1(pipe), |
3589 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
3592 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
3590 | } |
3593 | } |
3591 | } |
3594 | } |
Line -... | Line 3595... | ||
- | 3595 | ||
- | 3596 | static void gen6_check_mch_setup(struct drm_device *dev) |
|
- | 3597 | { |
|
- | 3598 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3599 | uint32_t tmp; |
|
- | 3600 | ||
- | 3601 | tmp = I915_READ(MCH_SSKPD); |
|
- | 3602 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { |
|
- | 3603 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); |
|
- | 3604 | DRM_INFO("This can cause pipe underruns and display issues.\n"); |
|
- | 3605 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); |
|
- | 3606 | } |
|
- | 3607 | } |
|
3592 | 3608 | ||
3593 | static void gen6_init_clock_gating(struct drm_device *dev) |
3609 | static void gen6_init_clock_gating(struct drm_device *dev) |
3594 | { |
3610 | { |
3595 | struct drm_i915_private *dev_priv = dev->dev_private; |
3611 | struct drm_i915_private *dev_priv = dev->dev_private; |
3596 | int pipe; |
3612 | int pipe; |
Line 3680... | Line 3696... | ||
3680 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3696 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3681 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3697 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3682 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
3698 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
Line 3683... | Line 3699... | ||
3683 | 3699 | ||
- | 3700 | cpt_init_clock_gating(dev); |
|
- | 3701 | ||
3684 | cpt_init_clock_gating(dev); |
3702 | gen6_check_mch_setup(dev); |
Line 3685... | Line 3703... | ||
3685 | } |
3703 | } |
3686 | 3704 | ||
3687 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
3705 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
Line 3691... | Line 3709... | ||
3691 | reg &= ~GEN7_FF_SCHED_MASK; |
3709 | reg &= ~GEN7_FF_SCHED_MASK; |
3692 | reg |= GEN7_FF_TS_SCHED_HW; |
3710 | reg |= GEN7_FF_TS_SCHED_HW; |
3693 | reg |= GEN7_FF_VS_SCHED_HW; |
3711 | reg |= GEN7_FF_VS_SCHED_HW; |
3694 | reg |= GEN7_FF_DS_SCHED_HW; |
3712 | reg |= GEN7_FF_DS_SCHED_HW; |
Line -... | Line 3713... | ||
- | 3713 | ||
- | 3714 | /* WaVSRefCountFullforceMissDisable */ |
|
- | 3715 | if (IS_HASWELL(dev_priv->dev)) |
|
- | 3716 | reg &= ~GEN7_FF_VS_REF_CNT_FFME; |
|
3695 | 3717 | ||
3696 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3718 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
Line 3697... | Line 3719... | ||
3697 | } |
3719 | } |
3698 | 3720 | ||
Line 3861... | Line 3883... | ||
3861 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3883 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3862 | snpcr |= GEN6_MBC_SNPCR_MED; |
3884 | snpcr |= GEN6_MBC_SNPCR_MED; |
3863 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
3885 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Line 3864... | Line 3886... | ||
3864 | 3886 | ||
- | 3887 | cpt_init_clock_gating(dev); |
|
- | 3888 | ||
3865 | cpt_init_clock_gating(dev); |
3889 | gen6_check_mch_setup(dev); |
Line 3866... | Line 3890... | ||
3866 | } |
3890 | } |
3867 | 3891 | ||
3868 | static void valleyview_init_clock_gating(struct drm_device *dev) |
3892 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Line 4054... | Line 4078... | ||
4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
4078 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 4055... | Line 4079... | ||
4055 | 4079 | ||
4056 | dev_priv->display.init_clock_gating(dev); |
4080 | dev_priv->display.init_clock_gating(dev); |
Line 4057... | Line -... | ||
4057 | } |
- | |
4058 | - | ||
4059 | /* Starting with Haswell, we have different power wells for |
- | |
4060 | * different parts of the GPU. This attempts to enable them all. |
4081 | } |
4061 | */ |
4082 | |
4062 | void intel_init_power_wells(struct drm_device *dev) |
4083 | void intel_set_power_well(struct drm_device *dev, bool enable) |
4063 | { |
4084 | { |
4064 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4065 | unsigned long power_wells[] = { |
- | |
4066 | HSW_PWR_WELL_CTL1, |
- | |
4067 | HSW_PWR_WELL_CTL2, |
- | |
4068 | HSW_PWR_WELL_CTL4 |
4085 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 4069... | Line 4086... | ||
4069 | }; |
4086 | bool is_enabled, enable_requested; |
4070 | int i; |
4087 | uint32_t tmp; |
Line 4071... | Line 4088... | ||
4071 | 4088 | ||
- | 4089 | if (!IS_HASWELL(dev)) |
|
- | 4090 | return; |
|
4072 | if (!IS_HASWELL(dev)) |
4091 | |
- | 4092 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
|
4073 | return; |
4093 | is_enabled = tmp & HSW_PWR_WELL_STATE; |
4074 | 4094 | enable_requested = tmp & HSW_PWR_WELL_ENABLE; |
|
4075 | mutex_lock(&dev->struct_mutex); |
4095 | |
- | 4096 | if (enable) { |
|
- | 4097 | if (!enable_requested) |
|
- | 4098 | I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); |
|
4076 | 4099 | ||
4077 | for (i = 0; i < ARRAY_SIZE(power_wells); i++) { |
4100 | if (!is_enabled) { |
- | 4101 | DRM_DEBUG_KMS("Enabling power well\n"); |
|
- | 4102 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
|
- | 4103 | HSW_PWR_WELL_STATE), 20)) |
|
4078 | int well = I915_READ(power_wells[i]); |
4104 | DRM_ERROR("Timeout enabling power well\n"); |
4079 | 4105 | } |
|
4080 | if ((well & HSW_PWR_WELL_STATE) == 0) { |
4106 | } else { |
4081 | I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); |
4107 | if (enable_requested) { |
- | 4108 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
|
- | 4109 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
|
- | 4110 | } |
|
- | 4111 | } |
|
- | 4112 | } |
|
- | 4113 | ||
- | 4114 | /* |
|
- | 4115 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
|
- | 4116 | * when not needed anymore. We have 4 registers that can request the power well |
|
- | 4117 | * to be enabled, and it will only be disabled if none of the registers is |
|
- | 4118 | * requesting it to be enabled. |
|
- | 4119 | */ |
|
- | 4120 | void intel_init_power_well(struct drm_device *dev) |
|
- | 4121 | { |
|
- | 4122 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4123 | ||
- | 4124 | if (!IS_HASWELL(dev)) |
|
Line -... | Line 4125... | ||
- | 4125 | return; |
|
- | 4126 | ||
- | 4127 | /* For now, we need the power well to be always enabled. */ |
|
4082 | if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) |
4128 | intel_set_power_well(dev, true); |
4083 | DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); |
4129 | |
Line 4084... | Line 4130... | ||
4084 | } |
4130 | /* We're taking over the BIOS, so clear any requests made by it since |
4085 | } |
4131 | * the driver is in charge now. */ |
4086 | 4132 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) |