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1 | /* |
1 | /* |
2 | * Copyright © 2012 Intel Corporation |
2 | * Copyright © 2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eugeni Dodonov |
24 | * Eugeni Dodonov |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #define iowrite32(v, addr) writel((v), (addr)) |
28 | #define iowrite32(v, addr) writel((v), (addr)) |
29 | #define ioread32(addr) readl(addr) |
29 | #define ioread32(addr) readl(addr) |
30 | 30 | ||
31 | //#include |
31 | //#include |
32 | #include "i915_drv.h" |
32 | #include "i915_drv.h" |
33 | #include "intel_drv.h" |
33 | #include "intel_drv.h" |
34 | #include |
34 | #include |
35 | //#include "../../../platform/x86/intel_ips.h" |
35 | //#include "../../../platform/x86/intel_ips.h" |
36 | #include |
36 | #include |
37 | 37 | ||
38 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
38 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
39 | 39 | ||
40 | #define assert_spin_locked(x) |
40 | #define assert_spin_locked(x) |
41 | 41 | ||
42 | void getrawmonotonic(struct timespec *ts); |
42 | void getrawmonotonic(struct timespec *ts); |
43 | void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec); |
43 | void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec); |
44 | 44 | ||
45 | static inline struct timespec timespec_sub(struct timespec lhs, |
45 | static inline struct timespec timespec_sub(struct timespec lhs, |
46 | struct timespec rhs) |
46 | struct timespec rhs) |
47 | { |
47 | { |
48 | struct timespec ts_delta; |
48 | struct timespec ts_delta; |
49 | set_normalized_timespec(&ts_delta, lhs.tv_sec - rhs.tv_sec, |
49 | set_normalized_timespec(&ts_delta, lhs.tv_sec - rhs.tv_sec, |
50 | lhs.tv_nsec - rhs.tv_nsec); |
50 | lhs.tv_nsec - rhs.tv_nsec); |
51 | return ts_delta; |
51 | return ts_delta; |
52 | } |
52 | } |
53 | 53 | ||
54 | 54 | ||
55 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
55 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
56 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
56 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
57 | * during in-memory transfers and, therefore, reduce the power packet. |
57 | * during in-memory transfers and, therefore, reduce the power packet. |
58 | * |
58 | * |
59 | * The benefits of FBC are mostly visible with solid backgrounds and |
59 | * The benefits of FBC are mostly visible with solid backgrounds and |
60 | * variation-less patterns. |
60 | * variation-less patterns. |
61 | * |
61 | * |
62 | * FBC-related functionality can be enabled by the means of the |
62 | * FBC-related functionality can be enabled by the means of the |
63 | * i915.i915_enable_fbc parameter |
63 | * i915.i915_enable_fbc parameter |
64 | */ |
64 | */ |
- | 65 | ||
- | 66 | static bool intel_crtc_active(struct drm_crtc *crtc) |
|
- | 67 | { |
|
- | 68 | /* Be paranoid as we can arrive here with only partial |
|
- | 69 | * state retrieved from the hardware during setup. |
|
- | 70 | */ |
|
- | 71 | return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; |
|
- | 72 | } |
|
65 | 73 | ||
66 | static void i8xx_disable_fbc(struct drm_device *dev) |
74 | static void i8xx_disable_fbc(struct drm_device *dev) |
67 | { |
75 | { |
68 | struct drm_i915_private *dev_priv = dev->dev_private; |
76 | struct drm_i915_private *dev_priv = dev->dev_private; |
69 | u32 fbc_ctl; |
77 | u32 fbc_ctl; |
70 | 78 | ||
71 | /* Disable compression */ |
79 | /* Disable compression */ |
72 | fbc_ctl = I915_READ(FBC_CONTROL); |
80 | fbc_ctl = I915_READ(FBC_CONTROL); |
73 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
81 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
74 | return; |
82 | return; |
75 | 83 | ||
76 | fbc_ctl &= ~FBC_CTL_EN; |
84 | fbc_ctl &= ~FBC_CTL_EN; |
77 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
85 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
78 | 86 | ||
79 | /* Wait for compressing bit to clear */ |
87 | /* Wait for compressing bit to clear */ |
80 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
88 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
81 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
89 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
82 | return; |
90 | return; |
83 | } |
91 | } |
84 | 92 | ||
85 | DRM_DEBUG_KMS("disabled FBC\n"); |
93 | DRM_DEBUG_KMS("disabled FBC\n"); |
86 | } |
94 | } |
87 | 95 | ||
88 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
96 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
89 | { |
97 | { |
90 | struct drm_device *dev = crtc->dev; |
98 | struct drm_device *dev = crtc->dev; |
91 | struct drm_i915_private *dev_priv = dev->dev_private; |
99 | struct drm_i915_private *dev_priv = dev->dev_private; |
92 | struct drm_framebuffer *fb = crtc->fb; |
100 | struct drm_framebuffer *fb = crtc->fb; |
93 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
101 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
94 | struct drm_i915_gem_object *obj = intel_fb->obj; |
102 | struct drm_i915_gem_object *obj = intel_fb->obj; |
95 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
96 | int cfb_pitch; |
104 | int cfb_pitch; |
97 | int plane, i; |
105 | int plane, i; |
98 | u32 fbc_ctl, fbc_ctl2; |
106 | u32 fbc_ctl, fbc_ctl2; |
99 | 107 | ||
100 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
108 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
101 | if (fb->pitches[0] < cfb_pitch) |
109 | if (fb->pitches[0] < cfb_pitch) |
102 | cfb_pitch = fb->pitches[0]; |
110 | cfb_pitch = fb->pitches[0]; |
103 | 111 | ||
104 | /* FBC_CTL wants 64B units */ |
112 | /* FBC_CTL wants 64B units */ |
105 | cfb_pitch = (cfb_pitch / 64) - 1; |
113 | cfb_pitch = (cfb_pitch / 64) - 1; |
106 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
114 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
107 | 115 | ||
108 | /* Clear old tags */ |
116 | /* Clear old tags */ |
109 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
117 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
110 | I915_WRITE(FBC_TAG + (i * 4), 0); |
118 | I915_WRITE(FBC_TAG + (i * 4), 0); |
111 | 119 | ||
112 | /* Set it up... */ |
120 | /* Set it up... */ |
113 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
114 | fbc_ctl2 |= plane; |
122 | fbc_ctl2 |= plane; |
115 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
116 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
117 | 125 | ||
118 | /* enable it... */ |
126 | /* enable it... */ |
119 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
127 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
120 | if (IS_I945GM(dev)) |
128 | if (IS_I945GM(dev)) |
121 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
129 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
122 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
130 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
123 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
131 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
124 | fbc_ctl |= obj->fence_reg; |
132 | fbc_ctl |= obj->fence_reg; |
125 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
133 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
126 | 134 | ||
127 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
135 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
128 | cfb_pitch, crtc->y, intel_crtc->plane); |
136 | cfb_pitch, crtc->y, intel_crtc->plane); |
129 | } |
137 | } |
130 | 138 | ||
131 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
139 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
132 | { |
140 | { |
133 | struct drm_i915_private *dev_priv = dev->dev_private; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; |
134 | 142 | ||
135 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
143 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
136 | } |
144 | } |
137 | 145 | ||
138 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
146 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
139 | { |
147 | { |
140 | struct drm_device *dev = crtc->dev; |
148 | struct drm_device *dev = crtc->dev; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; |
149 | struct drm_i915_private *dev_priv = dev->dev_private; |
142 | struct drm_framebuffer *fb = crtc->fb; |
150 | struct drm_framebuffer *fb = crtc->fb; |
143 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
151 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
144 | struct drm_i915_gem_object *obj = intel_fb->obj; |
152 | struct drm_i915_gem_object *obj = intel_fb->obj; |
145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
146 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
154 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
147 | unsigned long stall_watermark = 200; |
155 | unsigned long stall_watermark = 200; |
148 | u32 dpfc_ctl; |
156 | u32 dpfc_ctl; |
149 | 157 | ||
150 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
158 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
151 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
159 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
152 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
160 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
153 | 161 | ||
154 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
162 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
155 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
163 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
156 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
164 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
157 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
158 | 166 | ||
159 | /* enable it... */ |
167 | /* enable it... */ |
160 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
168 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
161 | 169 | ||
162 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
170 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
163 | } |
171 | } |
164 | 172 | ||
165 | static void g4x_disable_fbc(struct drm_device *dev) |
173 | static void g4x_disable_fbc(struct drm_device *dev) |
166 | { |
174 | { |
167 | struct drm_i915_private *dev_priv = dev->dev_private; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; |
168 | u32 dpfc_ctl; |
176 | u32 dpfc_ctl; |
169 | 177 | ||
170 | /* Disable compression */ |
178 | /* Disable compression */ |
171 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
179 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
172 | if (dpfc_ctl & DPFC_CTL_EN) { |
180 | if (dpfc_ctl & DPFC_CTL_EN) { |
173 | dpfc_ctl &= ~DPFC_CTL_EN; |
181 | dpfc_ctl &= ~DPFC_CTL_EN; |
174 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
175 | 183 | ||
176 | DRM_DEBUG_KMS("disabled FBC\n"); |
184 | DRM_DEBUG_KMS("disabled FBC\n"); |
177 | } |
185 | } |
178 | } |
186 | } |
179 | 187 | ||
180 | static bool g4x_fbc_enabled(struct drm_device *dev) |
188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
181 | { |
189 | { |
182 | struct drm_i915_private *dev_priv = dev->dev_private; |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
183 | 191 | ||
184 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
185 | } |
193 | } |
186 | 194 | ||
187 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
188 | { |
196 | { |
189 | struct drm_i915_private *dev_priv = dev->dev_private; |
197 | struct drm_i915_private *dev_priv = dev->dev_private; |
190 | u32 blt_ecoskpd; |
198 | u32 blt_ecoskpd; |
191 | 199 | ||
192 | /* Make sure blitter notifies FBC of writes */ |
200 | /* Make sure blitter notifies FBC of writes */ |
193 | gen6_gt_force_wake_get(dev_priv); |
201 | gen6_gt_force_wake_get(dev_priv); |
194 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
202 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
195 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
203 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
196 | GEN6_BLITTER_LOCK_SHIFT; |
204 | GEN6_BLITTER_LOCK_SHIFT; |
197 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
205 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
198 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
206 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
199 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
207 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
200 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
208 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
201 | GEN6_BLITTER_LOCK_SHIFT); |
209 | GEN6_BLITTER_LOCK_SHIFT); |
202 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
210 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
203 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
211 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
204 | gen6_gt_force_wake_put(dev_priv); |
212 | gen6_gt_force_wake_put(dev_priv); |
205 | } |
213 | } |
206 | 214 | ||
207 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
215 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
208 | { |
216 | { |
209 | struct drm_device *dev = crtc->dev; |
217 | struct drm_device *dev = crtc->dev; |
210 | struct drm_i915_private *dev_priv = dev->dev_private; |
218 | struct drm_i915_private *dev_priv = dev->dev_private; |
211 | struct drm_framebuffer *fb = crtc->fb; |
219 | struct drm_framebuffer *fb = crtc->fb; |
212 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
220 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
213 | struct drm_i915_gem_object *obj = intel_fb->obj; |
221 | struct drm_i915_gem_object *obj = intel_fb->obj; |
214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
215 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
223 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
216 | unsigned long stall_watermark = 200; |
224 | unsigned long stall_watermark = 200; |
217 | u32 dpfc_ctl; |
225 | u32 dpfc_ctl; |
218 | 226 | ||
219 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
227 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
220 | dpfc_ctl &= DPFC_RESERVED; |
228 | dpfc_ctl &= DPFC_RESERVED; |
221 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
229 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
222 | /* Set persistent mode for front-buffer rendering, ala X. */ |
230 | /* Set persistent mode for front-buffer rendering, ala X. */ |
223 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
231 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
224 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
232 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
225 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
233 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
226 | 234 | ||
227 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
235 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
228 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
236 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
229 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
237 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
230 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
238 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
231 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
239 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
232 | /* enable it... */ |
240 | /* enable it... */ |
233 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
241 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
234 | 242 | ||
235 | if (IS_GEN6(dev)) { |
243 | if (IS_GEN6(dev)) { |
236 | I915_WRITE(SNB_DPFC_CTL_SA, |
244 | I915_WRITE(SNB_DPFC_CTL_SA, |
237 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
245 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
238 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
246 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
239 | sandybridge_blit_fbc_update(dev); |
247 | sandybridge_blit_fbc_update(dev); |
240 | } |
248 | } |
241 | 249 | ||
242 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
250 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
243 | } |
251 | } |
244 | 252 | ||
245 | static void ironlake_disable_fbc(struct drm_device *dev) |
253 | static void ironlake_disable_fbc(struct drm_device *dev) |
246 | { |
254 | { |
247 | struct drm_i915_private *dev_priv = dev->dev_private; |
255 | struct drm_i915_private *dev_priv = dev->dev_private; |
248 | u32 dpfc_ctl; |
256 | u32 dpfc_ctl; |
249 | 257 | ||
250 | /* Disable compression */ |
258 | /* Disable compression */ |
251 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
259 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
252 | if (dpfc_ctl & DPFC_CTL_EN) { |
260 | if (dpfc_ctl & DPFC_CTL_EN) { |
253 | dpfc_ctl &= ~DPFC_CTL_EN; |
261 | dpfc_ctl &= ~DPFC_CTL_EN; |
254 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
262 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
255 | 263 | ||
256 | DRM_DEBUG_KMS("disabled FBC\n"); |
264 | DRM_DEBUG_KMS("disabled FBC\n"); |
257 | } |
265 | } |
258 | } |
266 | } |
259 | 267 | ||
260 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
268 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
261 | { |
269 | { |
262 | struct drm_i915_private *dev_priv = dev->dev_private; |
270 | struct drm_i915_private *dev_priv = dev->dev_private; |
263 | 271 | ||
264 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
272 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
265 | } |
273 | } |
266 | 274 | ||
267 | bool intel_fbc_enabled(struct drm_device *dev) |
275 | bool intel_fbc_enabled(struct drm_device *dev) |
268 | { |
276 | { |
269 | struct drm_i915_private *dev_priv = dev->dev_private; |
277 | struct drm_i915_private *dev_priv = dev->dev_private; |
270 | 278 | ||
271 | if (!dev_priv->display.fbc_enabled) |
279 | if (!dev_priv->display.fbc_enabled) |
272 | return false; |
280 | return false; |
273 | 281 | ||
274 | return dev_priv->display.fbc_enabled(dev); |
282 | return dev_priv->display.fbc_enabled(dev); |
275 | } |
283 | } |
276 | 284 | ||
277 | #if 0 |
285 | #if 0 |
278 | static void intel_fbc_work_fn(struct work_struct *__work) |
286 | static void intel_fbc_work_fn(struct work_struct *__work) |
279 | { |
287 | { |
280 | struct intel_fbc_work *work = |
288 | struct intel_fbc_work *work = |
281 | container_of(to_delayed_work(__work), |
289 | container_of(to_delayed_work(__work), |
282 | struct intel_fbc_work, work); |
290 | struct intel_fbc_work, work); |
283 | struct drm_device *dev = work->crtc->dev; |
291 | struct drm_device *dev = work->crtc->dev; |
284 | struct drm_i915_private *dev_priv = dev->dev_private; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; |
285 | 293 | ||
286 | mutex_lock(&dev->struct_mutex); |
294 | mutex_lock(&dev->struct_mutex); |
287 | if (work == dev_priv->fbc_work) { |
295 | if (work == dev_priv->fbc_work) { |
288 | /* Double check that we haven't switched fb without cancelling |
296 | /* Double check that we haven't switched fb without cancelling |
289 | * the prior work. |
297 | * the prior work. |
290 | */ |
298 | */ |
291 | if (work->crtc->fb == work->fb) { |
299 | if (work->crtc->fb == work->fb) { |
292 | dev_priv->display.enable_fbc(work->crtc, |
300 | dev_priv->display.enable_fbc(work->crtc, |
293 | work->interval); |
301 | work->interval); |
294 | 302 | ||
295 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
303 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
296 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
304 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
297 | dev_priv->cfb_y = work->crtc->y; |
305 | dev_priv->cfb_y = work->crtc->y; |
298 | } |
306 | } |
299 | 307 | ||
300 | dev_priv->fbc_work = NULL; |
308 | dev_priv->fbc_work = NULL; |
301 | } |
309 | } |
302 | mutex_unlock(&dev->struct_mutex); |
310 | mutex_unlock(&dev->struct_mutex); |
303 | 311 | ||
304 | kfree(work); |
312 | kfree(work); |
305 | } |
313 | } |
306 | 314 | ||
307 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
315 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
308 | { |
316 | { |
309 | if (dev_priv->fbc_work == NULL) |
317 | if (dev_priv->fbc_work == NULL) |
310 | return; |
318 | return; |
311 | 319 | ||
312 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
320 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
313 | 321 | ||
314 | /* Synchronisation is provided by struct_mutex and checking of |
322 | /* Synchronisation is provided by struct_mutex and checking of |
315 | * dev_priv->fbc_work, so we can perform the cancellation |
323 | * dev_priv->fbc_work, so we can perform the cancellation |
316 | * entirely asynchronously. |
324 | * entirely asynchronously. |
317 | */ |
325 | */ |
318 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
326 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
319 | /* tasklet was killed before being run, clean up */ |
327 | /* tasklet was killed before being run, clean up */ |
320 | kfree(dev_priv->fbc_work); |
328 | kfree(dev_priv->fbc_work); |
321 | 329 | ||
322 | /* Mark the work as no longer wanted so that if it does |
330 | /* Mark the work as no longer wanted so that if it does |
323 | * wake-up (because the work was already running and waiting |
331 | * wake-up (because the work was already running and waiting |
324 | * for our mutex), it will discover that is no longer |
332 | * for our mutex), it will discover that is no longer |
325 | * necessary to run. |
333 | * necessary to run. |
326 | */ |
334 | */ |
327 | dev_priv->fbc_work = NULL; |
335 | dev_priv->fbc_work = NULL; |
328 | } |
336 | } |
329 | #endif |
337 | #endif |
330 | 338 | ||
331 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
339 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
332 | { |
340 | { |
333 | struct intel_fbc_work *work; |
341 | struct intel_fbc_work *work; |
334 | struct drm_device *dev = crtc->dev; |
342 | struct drm_device *dev = crtc->dev; |
335 | struct drm_i915_private *dev_priv = dev->dev_private; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
336 | 344 | ||
337 | // if (!dev_priv->display.enable_fbc) |
345 | // if (!dev_priv->display.enable_fbc) |
338 | return; |
346 | return; |
339 | #if 0 |
347 | #if 0 |
340 | intel_cancel_fbc_work(dev_priv); |
348 | intel_cancel_fbc_work(dev_priv); |
341 | 349 | ||
342 | work = kzalloc(sizeof *work, GFP_KERNEL); |
350 | work = kzalloc(sizeof *work, GFP_KERNEL); |
343 | if (work == NULL) { |
351 | if (work == NULL) { |
344 | dev_priv->display.enable_fbc(crtc, interval); |
352 | dev_priv->display.enable_fbc(crtc, interval); |
345 | return; |
353 | return; |
346 | } |
354 | } |
347 | 355 | ||
348 | work->crtc = crtc; |
356 | work->crtc = crtc; |
349 | work->fb = crtc->fb; |
357 | work->fb = crtc->fb; |
350 | work->interval = interval; |
358 | work->interval = interval; |
351 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
359 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
352 | 360 | ||
353 | dev_priv->fbc_work = work; |
361 | dev_priv->fbc_work = work; |
354 | 362 | ||
355 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
363 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
356 | 364 | ||
357 | /* Delay the actual enabling to let pageflipping cease and the |
365 | /* Delay the actual enabling to let pageflipping cease and the |
358 | * display to settle before starting the compression. Note that |
366 | * display to settle before starting the compression. Note that |
359 | * this delay also serves a second purpose: it allows for a |
367 | * this delay also serves a second purpose: it allows for a |
360 | * vblank to pass after disabling the FBC before we attempt |
368 | * vblank to pass after disabling the FBC before we attempt |
361 | * to modify the control registers. |
369 | * to modify the control registers. |
362 | * |
370 | * |
363 | * A more complicated solution would involve tracking vblanks |
371 | * A more complicated solution would involve tracking vblanks |
364 | * following the termination of the page-flipping sequence |
372 | * following the termination of the page-flipping sequence |
365 | * and indeed performing the enable as a co-routine and not |
373 | * and indeed performing the enable as a co-routine and not |
366 | * waiting synchronously upon the vblank. |
374 | * waiting synchronously upon the vblank. |
367 | */ |
375 | */ |
368 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
376 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
369 | #endif |
377 | #endif |
370 | 378 | ||
371 | } |
379 | } |
372 | 380 | ||
373 | void intel_disable_fbc(struct drm_device *dev) |
381 | void intel_disable_fbc(struct drm_device *dev) |
374 | { |
382 | { |
375 | struct drm_i915_private *dev_priv = dev->dev_private; |
383 | struct drm_i915_private *dev_priv = dev->dev_private; |
376 | 384 | ||
377 | // intel_cancel_fbc_work(dev_priv); |
385 | // intel_cancel_fbc_work(dev_priv); |
378 | 386 | ||
379 | // if (!dev_priv->display.disable_fbc) |
387 | // if (!dev_priv->display.disable_fbc) |
380 | // return; |
388 | // return; |
381 | 389 | ||
382 | // dev_priv->display.disable_fbc(dev); |
390 | // dev_priv->display.disable_fbc(dev); |
383 | dev_priv->cfb_plane = -1; |
391 | dev_priv->cfb_plane = -1; |
384 | } |
392 | } |
385 | 393 | ||
386 | /** |
394 | /** |
387 | * intel_update_fbc - enable/disable FBC as needed |
395 | * intel_update_fbc - enable/disable FBC as needed |
388 | * @dev: the drm_device |
396 | * @dev: the drm_device |
389 | * |
397 | * |
390 | * Set up the framebuffer compression hardware at mode set time. We |
398 | * Set up the framebuffer compression hardware at mode set time. We |
391 | * enable it if possible: |
399 | * enable it if possible: |
392 | * - plane A only (on pre-965) |
400 | * - plane A only (on pre-965) |
393 | * - no pixel mulitply/line duplication |
401 | * - no pixel mulitply/line duplication |
394 | * - no alpha buffer discard |
402 | * - no alpha buffer discard |
395 | * - no dual wide |
403 | * - no dual wide |
396 | * - framebuffer <= 2048 in width, 1536 in height |
404 | * - framebuffer <= 2048 in width, 1536 in height |
397 | * |
405 | * |
398 | * We can't assume that any compression will take place (worst case), |
406 | * We can't assume that any compression will take place (worst case), |
399 | * so the compressed buffer has to be the same size as the uncompressed |
407 | * so the compressed buffer has to be the same size as the uncompressed |
400 | * one. It also must reside (along with the line length buffer) in |
408 | * one. It also must reside (along with the line length buffer) in |
401 | * stolen memory. |
409 | * stolen memory. |
402 | * |
410 | * |
403 | * We need to enable/disable FBC on a global basis. |
411 | * We need to enable/disable FBC on a global basis. |
404 | */ |
412 | */ |
405 | void intel_update_fbc(struct drm_device *dev) |
413 | void intel_update_fbc(struct drm_device *dev) |
406 | { |
414 | { |
407 | struct drm_i915_private *dev_priv = dev->dev_private; |
415 | struct drm_i915_private *dev_priv = dev->dev_private; |
408 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
416 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
409 | struct intel_crtc *intel_crtc; |
417 | struct intel_crtc *intel_crtc; |
410 | struct drm_framebuffer *fb; |
418 | struct drm_framebuffer *fb; |
411 | struct intel_framebuffer *intel_fb; |
419 | struct intel_framebuffer *intel_fb; |
412 | struct drm_i915_gem_object *obj; |
420 | struct drm_i915_gem_object *obj; |
413 | int enable_fbc; |
421 | int enable_fbc; |
414 | 422 | ||
415 | if (!i915_powersave) |
423 | if (!i915_powersave) |
416 | return; |
424 | return; |
417 | 425 | ||
418 | if (!I915_HAS_FBC(dev)) |
426 | if (!I915_HAS_FBC(dev)) |
419 | return; |
427 | return; |
420 | 428 | ||
421 | /* |
429 | /* |
422 | * If FBC is already on, we just have to verify that we can |
430 | * If FBC is already on, we just have to verify that we can |
423 | * keep it that way... |
431 | * keep it that way... |
424 | * Need to disable if: |
432 | * Need to disable if: |
425 | * - more than one pipe is active |
433 | * - more than one pipe is active |
426 | * - changing FBC params (stride, fence, mode) |
434 | * - changing FBC params (stride, fence, mode) |
427 | * - new fb is too large to fit in compressed buffer |
435 | * - new fb is too large to fit in compressed buffer |
428 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
436 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
429 | */ |
437 | */ |
430 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
438 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
431 | if (tmp_crtc->enabled && |
439 | if (intel_crtc_active(tmp_crtc) && |
432 | !to_intel_crtc(tmp_crtc)->primary_disabled && |
440 | !to_intel_crtc(tmp_crtc)->primary_disabled) { |
433 | tmp_crtc->fb) { |
- | |
434 | if (crtc) { |
441 | if (crtc) { |
435 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
442 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
436 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
443 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
437 | goto out_disable; |
444 | goto out_disable; |
438 | } |
445 | } |
439 | crtc = tmp_crtc; |
446 | crtc = tmp_crtc; |
440 | } |
447 | } |
441 | } |
448 | } |
442 | 449 | ||
443 | if (!crtc || crtc->fb == NULL) { |
450 | if (!crtc || crtc->fb == NULL) { |
444 | DRM_DEBUG_KMS("no output, disabling\n"); |
451 | DRM_DEBUG_KMS("no output, disabling\n"); |
445 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
452 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
446 | goto out_disable; |
453 | goto out_disable; |
447 | } |
454 | } |
448 | 455 | ||
449 | intel_crtc = to_intel_crtc(crtc); |
456 | intel_crtc = to_intel_crtc(crtc); |
450 | fb = crtc->fb; |
457 | fb = crtc->fb; |
451 | intel_fb = to_intel_framebuffer(fb); |
458 | intel_fb = to_intel_framebuffer(fb); |
452 | obj = intel_fb->obj; |
459 | obj = intel_fb->obj; |
453 | 460 | ||
454 | enable_fbc = i915_enable_fbc; |
461 | enable_fbc = i915_enable_fbc; |
455 | if (enable_fbc < 0) { |
462 | if (enable_fbc < 0) { |
456 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
463 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
457 | enable_fbc = 1; |
464 | enable_fbc = 1; |
458 | if (INTEL_INFO(dev)->gen <= 6) |
465 | if (INTEL_INFO(dev)->gen <= 6) |
459 | enable_fbc = 0; |
466 | enable_fbc = 0; |
460 | } |
467 | } |
461 | if (!enable_fbc) { |
468 | if (!enable_fbc) { |
462 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
469 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
463 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
470 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
464 | goto out_disable; |
471 | goto out_disable; |
465 | } |
472 | } |
466 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
473 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
467 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
474 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
468 | "compression\n"); |
475 | "compression\n"); |
469 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
476 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
470 | goto out_disable; |
477 | goto out_disable; |
471 | } |
478 | } |
472 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
479 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
473 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
480 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
474 | DRM_DEBUG_KMS("mode incompatible with compression, " |
481 | DRM_DEBUG_KMS("mode incompatible with compression, " |
475 | "disabling\n"); |
482 | "disabling\n"); |
476 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
483 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
477 | goto out_disable; |
484 | goto out_disable; |
478 | } |
485 | } |
479 | if ((crtc->mode.hdisplay > 2048) || |
486 | if ((crtc->mode.hdisplay > 2048) || |
480 | (crtc->mode.vdisplay > 1536)) { |
487 | (crtc->mode.vdisplay > 1536)) { |
481 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
488 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
482 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
489 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
483 | goto out_disable; |
490 | goto out_disable; |
484 | } |
491 | } |
485 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
492 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
486 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
493 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
487 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
494 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
488 | goto out_disable; |
495 | goto out_disable; |
489 | } |
496 | } |
490 | 497 | ||
491 | /* The use of a CPU fence is mandatory in order to detect writes |
498 | /* The use of a CPU fence is mandatory in order to detect writes |
492 | * by the CPU to the scanout and trigger updates to the FBC. |
499 | * by the CPU to the scanout and trigger updates to the FBC. |
493 | */ |
500 | */ |
494 | if (obj->tiling_mode != I915_TILING_X || |
501 | if (obj->tiling_mode != I915_TILING_X || |
495 | obj->fence_reg == I915_FENCE_REG_NONE) { |
502 | obj->fence_reg == I915_FENCE_REG_NONE) { |
496 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
503 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
497 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
504 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
498 | goto out_disable; |
505 | goto out_disable; |
499 | } |
506 | } |
500 | 507 | ||
501 | /* If the kernel debugger is active, always disable compression */ |
508 | /* If the kernel debugger is active, always disable compression */ |
502 | if (in_dbg_master()) |
509 | if (in_dbg_master()) |
503 | goto out_disable; |
510 | goto out_disable; |
504 | 511 | ||
505 | /* If the scanout has not changed, don't modify the FBC settings. |
512 | /* If the scanout has not changed, don't modify the FBC settings. |
506 | * Note that we make the fundamental assumption that the fb->obj |
513 | * Note that we make the fundamental assumption that the fb->obj |
507 | * cannot be unpinned (and have its GTT offset and fence revoked) |
514 | * cannot be unpinned (and have its GTT offset and fence revoked) |
508 | * without first being decoupled from the scanout and FBC disabled. |
515 | * without first being decoupled from the scanout and FBC disabled. |
509 | */ |
516 | */ |
510 | if (dev_priv->cfb_plane == intel_crtc->plane && |
517 | if (dev_priv->cfb_plane == intel_crtc->plane && |
511 | dev_priv->cfb_fb == fb->base.id && |
518 | dev_priv->cfb_fb == fb->base.id && |
512 | dev_priv->cfb_y == crtc->y) |
519 | dev_priv->cfb_y == crtc->y) |
513 | return; |
520 | return; |
514 | 521 | ||
515 | if (intel_fbc_enabled(dev)) { |
522 | if (intel_fbc_enabled(dev)) { |
516 | /* We update FBC along two paths, after changing fb/crtc |
523 | /* We update FBC along two paths, after changing fb/crtc |
517 | * configuration (modeswitching) and after page-flipping |
524 | * configuration (modeswitching) and after page-flipping |
518 | * finishes. For the latter, we know that not only did |
525 | * finishes. For the latter, we know that not only did |
519 | * we disable the FBC at the start of the page-flip |
526 | * we disable the FBC at the start of the page-flip |
520 | * sequence, but also more than one vblank has passed. |
527 | * sequence, but also more than one vblank has passed. |
521 | * |
528 | * |
522 | * For the former case of modeswitching, it is possible |
529 | * For the former case of modeswitching, it is possible |
523 | * to switch between two FBC valid configurations |
530 | * to switch between two FBC valid configurations |
524 | * instantaneously so we do need to disable the FBC |
531 | * instantaneously so we do need to disable the FBC |
525 | * before we can modify its control registers. We also |
532 | * before we can modify its control registers. We also |
526 | * have to wait for the next vblank for that to take |
533 | * have to wait for the next vblank for that to take |
527 | * effect. However, since we delay enabling FBC we can |
534 | * effect. However, since we delay enabling FBC we can |
528 | * assume that a vblank has passed since disabling and |
535 | * assume that a vblank has passed since disabling and |
529 | * that we can safely alter the registers in the deferred |
536 | * that we can safely alter the registers in the deferred |
530 | * callback. |
537 | * callback. |
531 | * |
538 | * |
532 | * In the scenario that we go from a valid to invalid |
539 | * In the scenario that we go from a valid to invalid |
533 | * and then back to valid FBC configuration we have |
540 | * and then back to valid FBC configuration we have |
534 | * no strict enforcement that a vblank occurred since |
541 | * no strict enforcement that a vblank occurred since |
535 | * disabling the FBC. However, along all current pipe |
542 | * disabling the FBC. However, along all current pipe |
536 | * disabling paths we do need to wait for a vblank at |
543 | * disabling paths we do need to wait for a vblank at |
537 | * some point. And we wait before enabling FBC anyway. |
544 | * some point. And we wait before enabling FBC anyway. |
538 | */ |
545 | */ |
539 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
546 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
540 | intel_disable_fbc(dev); |
547 | intel_disable_fbc(dev); |
541 | } |
548 | } |
542 | 549 | ||
543 | intel_enable_fbc(crtc, 500); |
550 | intel_enable_fbc(crtc, 500); |
544 | return; |
551 | return; |
545 | 552 | ||
546 | out_disable: |
553 | out_disable: |
547 | /* Multiple disables should be harmless */ |
554 | /* Multiple disables should be harmless */ |
548 | if (intel_fbc_enabled(dev)) { |
555 | if (intel_fbc_enabled(dev)) { |
549 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
556 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
550 | intel_disable_fbc(dev); |
557 | intel_disable_fbc(dev); |
551 | } |
558 | } |
552 | } |
559 | } |
553 | 560 | ||
554 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
561 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
555 | { |
562 | { |
556 | drm_i915_private_t *dev_priv = dev->dev_private; |
563 | drm_i915_private_t *dev_priv = dev->dev_private; |
557 | u32 tmp; |
564 | u32 tmp; |
558 | 565 | ||
559 | tmp = I915_READ(CLKCFG); |
566 | tmp = I915_READ(CLKCFG); |
560 | 567 | ||
561 | switch (tmp & CLKCFG_FSB_MASK) { |
568 | switch (tmp & CLKCFG_FSB_MASK) { |
562 | case CLKCFG_FSB_533: |
569 | case CLKCFG_FSB_533: |
563 | dev_priv->fsb_freq = 533; /* 133*4 */ |
570 | dev_priv->fsb_freq = 533; /* 133*4 */ |
564 | break; |
571 | break; |
565 | case CLKCFG_FSB_800: |
572 | case CLKCFG_FSB_800: |
566 | dev_priv->fsb_freq = 800; /* 200*4 */ |
573 | dev_priv->fsb_freq = 800; /* 200*4 */ |
567 | break; |
574 | break; |
568 | case CLKCFG_FSB_667: |
575 | case CLKCFG_FSB_667: |
569 | dev_priv->fsb_freq = 667; /* 167*4 */ |
576 | dev_priv->fsb_freq = 667; /* 167*4 */ |
570 | break; |
577 | break; |
571 | case CLKCFG_FSB_400: |
578 | case CLKCFG_FSB_400: |
572 | dev_priv->fsb_freq = 400; /* 100*4 */ |
579 | dev_priv->fsb_freq = 400; /* 100*4 */ |
573 | break; |
580 | break; |
574 | } |
581 | } |
575 | 582 | ||
576 | switch (tmp & CLKCFG_MEM_MASK) { |
583 | switch (tmp & CLKCFG_MEM_MASK) { |
577 | case CLKCFG_MEM_533: |
584 | case CLKCFG_MEM_533: |
578 | dev_priv->mem_freq = 533; |
585 | dev_priv->mem_freq = 533; |
579 | break; |
586 | break; |
580 | case CLKCFG_MEM_667: |
587 | case CLKCFG_MEM_667: |
581 | dev_priv->mem_freq = 667; |
588 | dev_priv->mem_freq = 667; |
582 | break; |
589 | break; |
583 | case CLKCFG_MEM_800: |
590 | case CLKCFG_MEM_800: |
584 | dev_priv->mem_freq = 800; |
591 | dev_priv->mem_freq = 800; |
585 | break; |
592 | break; |
586 | } |
593 | } |
587 | 594 | ||
588 | /* detect pineview DDR3 setting */ |
595 | /* detect pineview DDR3 setting */ |
589 | tmp = I915_READ(CSHRDDR3CTL); |
596 | tmp = I915_READ(CSHRDDR3CTL); |
590 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
597 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
591 | } |
598 | } |
592 | 599 | ||
593 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
600 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
594 | { |
601 | { |
595 | drm_i915_private_t *dev_priv = dev->dev_private; |
602 | drm_i915_private_t *dev_priv = dev->dev_private; |
596 | u16 ddrpll, csipll; |
603 | u16 ddrpll, csipll; |
597 | 604 | ||
598 | ddrpll = I915_READ16(DDRMPLL1); |
605 | ddrpll = I915_READ16(DDRMPLL1); |
599 | csipll = I915_READ16(CSIPLL0); |
606 | csipll = I915_READ16(CSIPLL0); |
600 | 607 | ||
601 | switch (ddrpll & 0xff) { |
608 | switch (ddrpll & 0xff) { |
602 | case 0xc: |
609 | case 0xc: |
603 | dev_priv->mem_freq = 800; |
610 | dev_priv->mem_freq = 800; |
604 | break; |
611 | break; |
605 | case 0x10: |
612 | case 0x10: |
606 | dev_priv->mem_freq = 1066; |
613 | dev_priv->mem_freq = 1066; |
607 | break; |
614 | break; |
608 | case 0x14: |
615 | case 0x14: |
609 | dev_priv->mem_freq = 1333; |
616 | dev_priv->mem_freq = 1333; |
610 | break; |
617 | break; |
611 | case 0x18: |
618 | case 0x18: |
612 | dev_priv->mem_freq = 1600; |
619 | dev_priv->mem_freq = 1600; |
613 | break; |
620 | break; |
614 | default: |
621 | default: |
615 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
622 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
616 | ddrpll & 0xff); |
623 | ddrpll & 0xff); |
617 | dev_priv->mem_freq = 0; |
624 | dev_priv->mem_freq = 0; |
618 | break; |
625 | break; |
619 | } |
626 | } |
620 | 627 | ||
621 | dev_priv->ips.r_t = dev_priv->mem_freq; |
628 | dev_priv->ips.r_t = dev_priv->mem_freq; |
622 | 629 | ||
623 | switch (csipll & 0x3ff) { |
630 | switch (csipll & 0x3ff) { |
624 | case 0x00c: |
631 | case 0x00c: |
625 | dev_priv->fsb_freq = 3200; |
632 | dev_priv->fsb_freq = 3200; |
626 | break; |
633 | break; |
627 | case 0x00e: |
634 | case 0x00e: |
628 | dev_priv->fsb_freq = 3733; |
635 | dev_priv->fsb_freq = 3733; |
629 | break; |
636 | break; |
630 | case 0x010: |
637 | case 0x010: |
631 | dev_priv->fsb_freq = 4266; |
638 | dev_priv->fsb_freq = 4266; |
632 | break; |
639 | break; |
633 | case 0x012: |
640 | case 0x012: |
634 | dev_priv->fsb_freq = 4800; |
641 | dev_priv->fsb_freq = 4800; |
635 | break; |
642 | break; |
636 | case 0x014: |
643 | case 0x014: |
637 | dev_priv->fsb_freq = 5333; |
644 | dev_priv->fsb_freq = 5333; |
638 | break; |
645 | break; |
639 | case 0x016: |
646 | case 0x016: |
640 | dev_priv->fsb_freq = 5866; |
647 | dev_priv->fsb_freq = 5866; |
641 | break; |
648 | break; |
642 | case 0x018: |
649 | case 0x018: |
643 | dev_priv->fsb_freq = 6400; |
650 | dev_priv->fsb_freq = 6400; |
644 | break; |
651 | break; |
645 | default: |
652 | default: |
646 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
653 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
647 | csipll & 0x3ff); |
654 | csipll & 0x3ff); |
648 | dev_priv->fsb_freq = 0; |
655 | dev_priv->fsb_freq = 0; |
649 | break; |
656 | break; |
650 | } |
657 | } |
651 | 658 | ||
652 | if (dev_priv->fsb_freq == 3200) { |
659 | if (dev_priv->fsb_freq == 3200) { |
653 | dev_priv->ips.c_m = 0; |
660 | dev_priv->ips.c_m = 0; |
654 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
661 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
655 | dev_priv->ips.c_m = 1; |
662 | dev_priv->ips.c_m = 1; |
656 | } else { |
663 | } else { |
657 | dev_priv->ips.c_m = 2; |
664 | dev_priv->ips.c_m = 2; |
658 | } |
665 | } |
659 | } |
666 | } |
660 | 667 | ||
661 | static const struct cxsr_latency cxsr_latency_table[] = { |
668 | static const struct cxsr_latency cxsr_latency_table[] = { |
662 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
669 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
663 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
670 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
664 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
671 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
665 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
672 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
666 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
673 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
667 | 674 | ||
668 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
675 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
669 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
676 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
670 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
677 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
671 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
678 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
672 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
679 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
673 | 680 | ||
674 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
681 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
675 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
682 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
676 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
683 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
677 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
684 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
678 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
685 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
679 | 686 | ||
680 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
687 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
681 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
688 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
682 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
689 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
683 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
690 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
684 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
691 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
685 | 692 | ||
686 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
693 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
687 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
694 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
688 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
695 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
689 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
696 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
690 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
697 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
691 | 698 | ||
692 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
699 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
693 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
700 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
694 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
701 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
695 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
702 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
696 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
703 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
697 | }; |
704 | }; |
698 | 705 | ||
699 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
706 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
700 | int is_ddr3, |
707 | int is_ddr3, |
701 | int fsb, |
708 | int fsb, |
702 | int mem) |
709 | int mem) |
703 | { |
710 | { |
704 | const struct cxsr_latency *latency; |
711 | const struct cxsr_latency *latency; |
705 | int i; |
712 | int i; |
706 | 713 | ||
707 | if (fsb == 0 || mem == 0) |
714 | if (fsb == 0 || mem == 0) |
708 | return NULL; |
715 | return NULL; |
709 | 716 | ||
710 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
717 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
711 | latency = &cxsr_latency_table[i]; |
718 | latency = &cxsr_latency_table[i]; |
712 | if (is_desktop == latency->is_desktop && |
719 | if (is_desktop == latency->is_desktop && |
713 | is_ddr3 == latency->is_ddr3 && |
720 | is_ddr3 == latency->is_ddr3 && |
714 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
721 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
715 | return latency; |
722 | return latency; |
716 | } |
723 | } |
717 | 724 | ||
718 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
725 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
719 | 726 | ||
720 | return NULL; |
727 | return NULL; |
721 | } |
728 | } |
722 | 729 | ||
723 | static void pineview_disable_cxsr(struct drm_device *dev) |
730 | static void pineview_disable_cxsr(struct drm_device *dev) |
724 | { |
731 | { |
725 | struct drm_i915_private *dev_priv = dev->dev_private; |
732 | struct drm_i915_private *dev_priv = dev->dev_private; |
726 | 733 | ||
727 | /* deactivate cxsr */ |
734 | /* deactivate cxsr */ |
728 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
735 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
729 | } |
736 | } |
730 | 737 | ||
731 | /* |
738 | /* |
732 | * Latency for FIFO fetches is dependent on several factors: |
739 | * Latency for FIFO fetches is dependent on several factors: |
733 | * - memory configuration (speed, channels) |
740 | * - memory configuration (speed, channels) |
734 | * - chipset |
741 | * - chipset |
735 | * - current MCH state |
742 | * - current MCH state |
736 | * It can be fairly high in some situations, so here we assume a fairly |
743 | * It can be fairly high in some situations, so here we assume a fairly |
737 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
744 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
738 | * set this value too high, the FIFO will fetch frequently to stay full) |
745 | * set this value too high, the FIFO will fetch frequently to stay full) |
739 | * and power consumption (set it too low to save power and we might see |
746 | * and power consumption (set it too low to save power and we might see |
740 | * FIFO underruns and display "flicker"). |
747 | * FIFO underruns and display "flicker"). |
741 | * |
748 | * |
742 | * A value of 5us seems to be a good balance; safe for very low end |
749 | * A value of 5us seems to be a good balance; safe for very low end |
743 | * platforms but not overly aggressive on lower latency configs. |
750 | * platforms but not overly aggressive on lower latency configs. |
744 | */ |
751 | */ |
745 | static const int latency_ns = 5000; |
752 | static const int latency_ns = 5000; |
746 | 753 | ||
747 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
754 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
748 | { |
755 | { |
749 | struct drm_i915_private *dev_priv = dev->dev_private; |
756 | struct drm_i915_private *dev_priv = dev->dev_private; |
750 | uint32_t dsparb = I915_READ(DSPARB); |
757 | uint32_t dsparb = I915_READ(DSPARB); |
751 | int size; |
758 | int size; |
752 | 759 | ||
753 | size = dsparb & 0x7f; |
760 | size = dsparb & 0x7f; |
754 | if (plane) |
761 | if (plane) |
755 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
762 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
756 | 763 | ||
757 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
764 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
758 | plane ? "B" : "A", size); |
765 | plane ? "B" : "A", size); |
759 | 766 | ||
760 | return size; |
767 | return size; |
761 | } |
768 | } |
762 | 769 | ||
763 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
770 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
764 | { |
771 | { |
765 | struct drm_i915_private *dev_priv = dev->dev_private; |
772 | struct drm_i915_private *dev_priv = dev->dev_private; |
766 | uint32_t dsparb = I915_READ(DSPARB); |
773 | uint32_t dsparb = I915_READ(DSPARB); |
767 | int size; |
774 | int size; |
768 | 775 | ||
769 | size = dsparb & 0x1ff; |
776 | size = dsparb & 0x1ff; |
770 | if (plane) |
777 | if (plane) |
771 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
778 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
772 | size >>= 1; /* Convert to cachelines */ |
779 | size >>= 1; /* Convert to cachelines */ |
773 | 780 | ||
774 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
781 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
775 | plane ? "B" : "A", size); |
782 | plane ? "B" : "A", size); |
776 | 783 | ||
777 | return size; |
784 | return size; |
778 | } |
785 | } |
779 | 786 | ||
780 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
787 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
781 | { |
788 | { |
782 | struct drm_i915_private *dev_priv = dev->dev_private; |
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
783 | uint32_t dsparb = I915_READ(DSPARB); |
790 | uint32_t dsparb = I915_READ(DSPARB); |
784 | int size; |
791 | int size; |
785 | 792 | ||
786 | size = dsparb & 0x7f; |
793 | size = dsparb & 0x7f; |
787 | size >>= 2; /* Convert to cachelines */ |
794 | size >>= 2; /* Convert to cachelines */ |
788 | 795 | ||
789 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
796 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
790 | plane ? "B" : "A", |
797 | plane ? "B" : "A", |
791 | size); |
798 | size); |
792 | 799 | ||
793 | return size; |
800 | return size; |
794 | } |
801 | } |
795 | 802 | ||
796 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
803 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
797 | { |
804 | { |
798 | struct drm_i915_private *dev_priv = dev->dev_private; |
805 | struct drm_i915_private *dev_priv = dev->dev_private; |
799 | uint32_t dsparb = I915_READ(DSPARB); |
806 | uint32_t dsparb = I915_READ(DSPARB); |
800 | int size; |
807 | int size; |
801 | 808 | ||
802 | size = dsparb & 0x7f; |
809 | size = dsparb & 0x7f; |
803 | size >>= 1; /* Convert to cachelines */ |
810 | size >>= 1; /* Convert to cachelines */ |
804 | 811 | ||
805 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
812 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
806 | plane ? "B" : "A", size); |
813 | plane ? "B" : "A", size); |
807 | 814 | ||
808 | return size; |
815 | return size; |
809 | } |
816 | } |
810 | 817 | ||
811 | /* Pineview has different values for various configs */ |
818 | /* Pineview has different values for various configs */ |
812 | static const struct intel_watermark_params pineview_display_wm = { |
819 | static const struct intel_watermark_params pineview_display_wm = { |
813 | PINEVIEW_DISPLAY_FIFO, |
820 | PINEVIEW_DISPLAY_FIFO, |
814 | PINEVIEW_MAX_WM, |
821 | PINEVIEW_MAX_WM, |
815 | PINEVIEW_DFT_WM, |
822 | PINEVIEW_DFT_WM, |
816 | PINEVIEW_GUARD_WM, |
823 | PINEVIEW_GUARD_WM, |
817 | PINEVIEW_FIFO_LINE_SIZE |
824 | PINEVIEW_FIFO_LINE_SIZE |
818 | }; |
825 | }; |
819 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
826 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
820 | PINEVIEW_DISPLAY_FIFO, |
827 | PINEVIEW_DISPLAY_FIFO, |
821 | PINEVIEW_MAX_WM, |
828 | PINEVIEW_MAX_WM, |
822 | PINEVIEW_DFT_HPLLOFF_WM, |
829 | PINEVIEW_DFT_HPLLOFF_WM, |
823 | PINEVIEW_GUARD_WM, |
830 | PINEVIEW_GUARD_WM, |
824 | PINEVIEW_FIFO_LINE_SIZE |
831 | PINEVIEW_FIFO_LINE_SIZE |
825 | }; |
832 | }; |
826 | static const struct intel_watermark_params pineview_cursor_wm = { |
833 | static const struct intel_watermark_params pineview_cursor_wm = { |
827 | PINEVIEW_CURSOR_FIFO, |
834 | PINEVIEW_CURSOR_FIFO, |
828 | PINEVIEW_CURSOR_MAX_WM, |
835 | PINEVIEW_CURSOR_MAX_WM, |
829 | PINEVIEW_CURSOR_DFT_WM, |
836 | PINEVIEW_CURSOR_DFT_WM, |
830 | PINEVIEW_CURSOR_GUARD_WM, |
837 | PINEVIEW_CURSOR_GUARD_WM, |
831 | PINEVIEW_FIFO_LINE_SIZE, |
838 | PINEVIEW_FIFO_LINE_SIZE, |
832 | }; |
839 | }; |
833 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
840 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
834 | PINEVIEW_CURSOR_FIFO, |
841 | PINEVIEW_CURSOR_FIFO, |
835 | PINEVIEW_CURSOR_MAX_WM, |
842 | PINEVIEW_CURSOR_MAX_WM, |
836 | PINEVIEW_CURSOR_DFT_WM, |
843 | PINEVIEW_CURSOR_DFT_WM, |
837 | PINEVIEW_CURSOR_GUARD_WM, |
844 | PINEVIEW_CURSOR_GUARD_WM, |
838 | PINEVIEW_FIFO_LINE_SIZE |
845 | PINEVIEW_FIFO_LINE_SIZE |
839 | }; |
846 | }; |
840 | static const struct intel_watermark_params g4x_wm_info = { |
847 | static const struct intel_watermark_params g4x_wm_info = { |
841 | G4X_FIFO_SIZE, |
848 | G4X_FIFO_SIZE, |
842 | G4X_MAX_WM, |
849 | G4X_MAX_WM, |
843 | G4X_MAX_WM, |
850 | G4X_MAX_WM, |
844 | 2, |
851 | 2, |
845 | G4X_FIFO_LINE_SIZE, |
852 | G4X_FIFO_LINE_SIZE, |
846 | }; |
853 | }; |
847 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
854 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
848 | I965_CURSOR_FIFO, |
855 | I965_CURSOR_FIFO, |
849 | I965_CURSOR_MAX_WM, |
856 | I965_CURSOR_MAX_WM, |
850 | I965_CURSOR_DFT_WM, |
857 | I965_CURSOR_DFT_WM, |
851 | 2, |
858 | 2, |
852 | G4X_FIFO_LINE_SIZE, |
859 | G4X_FIFO_LINE_SIZE, |
853 | }; |
860 | }; |
854 | static const struct intel_watermark_params valleyview_wm_info = { |
861 | static const struct intel_watermark_params valleyview_wm_info = { |
855 | VALLEYVIEW_FIFO_SIZE, |
862 | VALLEYVIEW_FIFO_SIZE, |
856 | VALLEYVIEW_MAX_WM, |
863 | VALLEYVIEW_MAX_WM, |
857 | VALLEYVIEW_MAX_WM, |
864 | VALLEYVIEW_MAX_WM, |
858 | 2, |
865 | 2, |
859 | G4X_FIFO_LINE_SIZE, |
866 | G4X_FIFO_LINE_SIZE, |
860 | }; |
867 | }; |
861 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
868 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
862 | I965_CURSOR_FIFO, |
869 | I965_CURSOR_FIFO, |
863 | VALLEYVIEW_CURSOR_MAX_WM, |
870 | VALLEYVIEW_CURSOR_MAX_WM, |
864 | I965_CURSOR_DFT_WM, |
871 | I965_CURSOR_DFT_WM, |
865 | 2, |
872 | 2, |
866 | G4X_FIFO_LINE_SIZE, |
873 | G4X_FIFO_LINE_SIZE, |
867 | }; |
874 | }; |
868 | static const struct intel_watermark_params i965_cursor_wm_info = { |
875 | static const struct intel_watermark_params i965_cursor_wm_info = { |
869 | I965_CURSOR_FIFO, |
876 | I965_CURSOR_FIFO, |
870 | I965_CURSOR_MAX_WM, |
877 | I965_CURSOR_MAX_WM, |
871 | I965_CURSOR_DFT_WM, |
878 | I965_CURSOR_DFT_WM, |
872 | 2, |
879 | 2, |
873 | I915_FIFO_LINE_SIZE, |
880 | I915_FIFO_LINE_SIZE, |
874 | }; |
881 | }; |
875 | static const struct intel_watermark_params i945_wm_info = { |
882 | static const struct intel_watermark_params i945_wm_info = { |
876 | I945_FIFO_SIZE, |
883 | I945_FIFO_SIZE, |
877 | I915_MAX_WM, |
884 | I915_MAX_WM, |
878 | 1, |
885 | 1, |
879 | 2, |
886 | 2, |
880 | I915_FIFO_LINE_SIZE |
887 | I915_FIFO_LINE_SIZE |
881 | }; |
888 | }; |
882 | static const struct intel_watermark_params i915_wm_info = { |
889 | static const struct intel_watermark_params i915_wm_info = { |
883 | I915_FIFO_SIZE, |
890 | I915_FIFO_SIZE, |
884 | I915_MAX_WM, |
891 | I915_MAX_WM, |
885 | 1, |
892 | 1, |
886 | 2, |
893 | 2, |
887 | I915_FIFO_LINE_SIZE |
894 | I915_FIFO_LINE_SIZE |
888 | }; |
895 | }; |
889 | static const struct intel_watermark_params i855_wm_info = { |
896 | static const struct intel_watermark_params i855_wm_info = { |
890 | I855GM_FIFO_SIZE, |
897 | I855GM_FIFO_SIZE, |
891 | I915_MAX_WM, |
898 | I915_MAX_WM, |
892 | 1, |
899 | 1, |
893 | 2, |
900 | 2, |
894 | I830_FIFO_LINE_SIZE |
901 | I830_FIFO_LINE_SIZE |
895 | }; |
902 | }; |
896 | static const struct intel_watermark_params i830_wm_info = { |
903 | static const struct intel_watermark_params i830_wm_info = { |
897 | I830_FIFO_SIZE, |
904 | I830_FIFO_SIZE, |
898 | I915_MAX_WM, |
905 | I915_MAX_WM, |
899 | 1, |
906 | 1, |
900 | 2, |
907 | 2, |
901 | I830_FIFO_LINE_SIZE |
908 | I830_FIFO_LINE_SIZE |
902 | }; |
909 | }; |
903 | 910 | ||
904 | static const struct intel_watermark_params ironlake_display_wm_info = { |
911 | static const struct intel_watermark_params ironlake_display_wm_info = { |
905 | ILK_DISPLAY_FIFO, |
912 | ILK_DISPLAY_FIFO, |
906 | ILK_DISPLAY_MAXWM, |
913 | ILK_DISPLAY_MAXWM, |
907 | ILK_DISPLAY_DFTWM, |
914 | ILK_DISPLAY_DFTWM, |
908 | 2, |
915 | 2, |
909 | ILK_FIFO_LINE_SIZE |
916 | ILK_FIFO_LINE_SIZE |
910 | }; |
917 | }; |
911 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
918 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
912 | ILK_CURSOR_FIFO, |
919 | ILK_CURSOR_FIFO, |
913 | ILK_CURSOR_MAXWM, |
920 | ILK_CURSOR_MAXWM, |
914 | ILK_CURSOR_DFTWM, |
921 | ILK_CURSOR_DFTWM, |
915 | 2, |
922 | 2, |
916 | ILK_FIFO_LINE_SIZE |
923 | ILK_FIFO_LINE_SIZE |
917 | }; |
924 | }; |
918 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
925 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
919 | ILK_DISPLAY_SR_FIFO, |
926 | ILK_DISPLAY_SR_FIFO, |
920 | ILK_DISPLAY_MAX_SRWM, |
927 | ILK_DISPLAY_MAX_SRWM, |
921 | ILK_DISPLAY_DFT_SRWM, |
928 | ILK_DISPLAY_DFT_SRWM, |
922 | 2, |
929 | 2, |
923 | ILK_FIFO_LINE_SIZE |
930 | ILK_FIFO_LINE_SIZE |
924 | }; |
931 | }; |
925 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
932 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
926 | ILK_CURSOR_SR_FIFO, |
933 | ILK_CURSOR_SR_FIFO, |
927 | ILK_CURSOR_MAX_SRWM, |
934 | ILK_CURSOR_MAX_SRWM, |
928 | ILK_CURSOR_DFT_SRWM, |
935 | ILK_CURSOR_DFT_SRWM, |
929 | 2, |
936 | 2, |
930 | ILK_FIFO_LINE_SIZE |
937 | ILK_FIFO_LINE_SIZE |
931 | }; |
938 | }; |
932 | 939 | ||
933 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
940 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
934 | SNB_DISPLAY_FIFO, |
941 | SNB_DISPLAY_FIFO, |
935 | SNB_DISPLAY_MAXWM, |
942 | SNB_DISPLAY_MAXWM, |
936 | SNB_DISPLAY_DFTWM, |
943 | SNB_DISPLAY_DFTWM, |
937 | 2, |
944 | 2, |
938 | SNB_FIFO_LINE_SIZE |
945 | SNB_FIFO_LINE_SIZE |
939 | }; |
946 | }; |
940 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
947 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
941 | SNB_CURSOR_FIFO, |
948 | SNB_CURSOR_FIFO, |
942 | SNB_CURSOR_MAXWM, |
949 | SNB_CURSOR_MAXWM, |
943 | SNB_CURSOR_DFTWM, |
950 | SNB_CURSOR_DFTWM, |
944 | 2, |
951 | 2, |
945 | SNB_FIFO_LINE_SIZE |
952 | SNB_FIFO_LINE_SIZE |
946 | }; |
953 | }; |
947 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
954 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
948 | SNB_DISPLAY_SR_FIFO, |
955 | SNB_DISPLAY_SR_FIFO, |
949 | SNB_DISPLAY_MAX_SRWM, |
956 | SNB_DISPLAY_MAX_SRWM, |
950 | SNB_DISPLAY_DFT_SRWM, |
957 | SNB_DISPLAY_DFT_SRWM, |
951 | 2, |
958 | 2, |
952 | SNB_FIFO_LINE_SIZE |
959 | SNB_FIFO_LINE_SIZE |
953 | }; |
960 | }; |
954 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
961 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
955 | SNB_CURSOR_SR_FIFO, |
962 | SNB_CURSOR_SR_FIFO, |
956 | SNB_CURSOR_MAX_SRWM, |
963 | SNB_CURSOR_MAX_SRWM, |
957 | SNB_CURSOR_DFT_SRWM, |
964 | SNB_CURSOR_DFT_SRWM, |
958 | 2, |
965 | 2, |
959 | SNB_FIFO_LINE_SIZE |
966 | SNB_FIFO_LINE_SIZE |
960 | }; |
967 | }; |
961 | 968 | ||
962 | 969 | ||
963 | /** |
970 | /** |
964 | * intel_calculate_wm - calculate watermark level |
971 | * intel_calculate_wm - calculate watermark level |
965 | * @clock_in_khz: pixel clock |
972 | * @clock_in_khz: pixel clock |
966 | * @wm: chip FIFO params |
973 | * @wm: chip FIFO params |
967 | * @pixel_size: display pixel size |
974 | * @pixel_size: display pixel size |
968 | * @latency_ns: memory latency for the platform |
975 | * @latency_ns: memory latency for the platform |
969 | * |
976 | * |
970 | * Calculate the watermark level (the level at which the display plane will |
977 | * Calculate the watermark level (the level at which the display plane will |
971 | * start fetching from memory again). Each chip has a different display |
978 | * start fetching from memory again). Each chip has a different display |
972 | * FIFO size and allocation, so the caller needs to figure that out and pass |
979 | * FIFO size and allocation, so the caller needs to figure that out and pass |
973 | * in the correct intel_watermark_params structure. |
980 | * in the correct intel_watermark_params structure. |
974 | * |
981 | * |
975 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
982 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
976 | * on the pixel size. When it reaches the watermark level, it'll start |
983 | * on the pixel size. When it reaches the watermark level, it'll start |
977 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
984 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
978 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
985 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
979 | * will occur, and a display engine hang could result. |
986 | * will occur, and a display engine hang could result. |
980 | */ |
987 | */ |
981 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
988 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
982 | const struct intel_watermark_params *wm, |
989 | const struct intel_watermark_params *wm, |
983 | int fifo_size, |
990 | int fifo_size, |
984 | int pixel_size, |
991 | int pixel_size, |
985 | unsigned long latency_ns) |
992 | unsigned long latency_ns) |
986 | { |
993 | { |
987 | long entries_required, wm_size; |
994 | long entries_required, wm_size; |
988 | 995 | ||
989 | /* |
996 | /* |
990 | * Note: we need to make sure we don't overflow for various clock & |
997 | * Note: we need to make sure we don't overflow for various clock & |
991 | * latency values. |
998 | * latency values. |
992 | * clocks go from a few thousand to several hundred thousand. |
999 | * clocks go from a few thousand to several hundred thousand. |
993 | * latency is usually a few thousand |
1000 | * latency is usually a few thousand |
994 | */ |
1001 | */ |
995 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
1002 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
996 | 1000; |
1003 | 1000; |
997 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
1004 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
998 | 1005 | ||
999 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
1006 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
1000 | 1007 | ||
1001 | wm_size = fifo_size - (entries_required + wm->guard_size); |
1008 | wm_size = fifo_size - (entries_required + wm->guard_size); |
1002 | 1009 | ||
1003 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
1010 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
1004 | 1011 | ||
1005 | /* Don't promote wm_size to unsigned... */ |
1012 | /* Don't promote wm_size to unsigned... */ |
1006 | if (wm_size > (long)wm->max_wm) |
1013 | if (wm_size > (long)wm->max_wm) |
1007 | wm_size = wm->max_wm; |
1014 | wm_size = wm->max_wm; |
1008 | if (wm_size <= 0) |
1015 | if (wm_size <= 0) |
1009 | wm_size = wm->default_wm; |
1016 | wm_size = wm->default_wm; |
1010 | return wm_size; |
1017 | return wm_size; |
1011 | } |
1018 | } |
1012 | 1019 | ||
1013 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
1020 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
1014 | { |
1021 | { |
1015 | struct drm_crtc *crtc, *enabled = NULL; |
1022 | struct drm_crtc *crtc, *enabled = NULL; |
1016 | 1023 | ||
1017 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1024 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1018 | if (crtc->enabled && crtc->fb) { |
1025 | if (intel_crtc_active(crtc)) { |
1019 | if (enabled) |
1026 | if (enabled) |
1020 | return NULL; |
1027 | return NULL; |
1021 | enabled = crtc; |
1028 | enabled = crtc; |
1022 | } |
1029 | } |
1023 | } |
1030 | } |
1024 | 1031 | ||
1025 | return enabled; |
1032 | return enabled; |
1026 | } |
1033 | } |
1027 | 1034 | ||
1028 | static void pineview_update_wm(struct drm_device *dev) |
1035 | static void pineview_update_wm(struct drm_device *dev) |
1029 | { |
1036 | { |
1030 | struct drm_i915_private *dev_priv = dev->dev_private; |
1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
1031 | struct drm_crtc *crtc; |
1038 | struct drm_crtc *crtc; |
1032 | const struct cxsr_latency *latency; |
1039 | const struct cxsr_latency *latency; |
1033 | u32 reg; |
1040 | u32 reg; |
1034 | unsigned long wm; |
1041 | unsigned long wm; |
1035 | 1042 | ||
1036 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
1043 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
1037 | dev_priv->fsb_freq, dev_priv->mem_freq); |
1044 | dev_priv->fsb_freq, dev_priv->mem_freq); |
1038 | if (!latency) { |
1045 | if (!latency) { |
1039 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
1046 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
1040 | pineview_disable_cxsr(dev); |
1047 | pineview_disable_cxsr(dev); |
1041 | return; |
1048 | return; |
1042 | } |
1049 | } |
1043 | 1050 | ||
1044 | crtc = single_enabled_crtc(dev); |
1051 | crtc = single_enabled_crtc(dev); |
1045 | if (crtc) { |
1052 | if (crtc) { |
1046 | int clock = crtc->mode.clock; |
1053 | int clock = crtc->mode.clock; |
1047 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1054 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1048 | 1055 | ||
1049 | /* Display SR */ |
1056 | /* Display SR */ |
1050 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
1057 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
1051 | pineview_display_wm.fifo_size, |
1058 | pineview_display_wm.fifo_size, |
1052 | pixel_size, latency->display_sr); |
1059 | pixel_size, latency->display_sr); |
1053 | reg = I915_READ(DSPFW1); |
1060 | reg = I915_READ(DSPFW1); |
1054 | reg &= ~DSPFW_SR_MASK; |
1061 | reg &= ~DSPFW_SR_MASK; |
1055 | reg |= wm << DSPFW_SR_SHIFT; |
1062 | reg |= wm << DSPFW_SR_SHIFT; |
1056 | I915_WRITE(DSPFW1, reg); |
1063 | I915_WRITE(DSPFW1, reg); |
1057 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
1064 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
1058 | 1065 | ||
1059 | /* cursor SR */ |
1066 | /* cursor SR */ |
1060 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
1067 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
1061 | pineview_display_wm.fifo_size, |
1068 | pineview_display_wm.fifo_size, |
1062 | pixel_size, latency->cursor_sr); |
1069 | pixel_size, latency->cursor_sr); |
1063 | reg = I915_READ(DSPFW3); |
1070 | reg = I915_READ(DSPFW3); |
1064 | reg &= ~DSPFW_CURSOR_SR_MASK; |
1071 | reg &= ~DSPFW_CURSOR_SR_MASK; |
1065 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
1072 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
1066 | I915_WRITE(DSPFW3, reg); |
1073 | I915_WRITE(DSPFW3, reg); |
1067 | 1074 | ||
1068 | /* Display HPLL off SR */ |
1075 | /* Display HPLL off SR */ |
1069 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
1076 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
1070 | pineview_display_hplloff_wm.fifo_size, |
1077 | pineview_display_hplloff_wm.fifo_size, |
1071 | pixel_size, latency->display_hpll_disable); |
1078 | pixel_size, latency->display_hpll_disable); |
1072 | reg = I915_READ(DSPFW3); |
1079 | reg = I915_READ(DSPFW3); |
1073 | reg &= ~DSPFW_HPLL_SR_MASK; |
1080 | reg &= ~DSPFW_HPLL_SR_MASK; |
1074 | reg |= wm & DSPFW_HPLL_SR_MASK; |
1081 | reg |= wm & DSPFW_HPLL_SR_MASK; |
1075 | I915_WRITE(DSPFW3, reg); |
1082 | I915_WRITE(DSPFW3, reg); |
1076 | 1083 | ||
1077 | /* cursor HPLL off SR */ |
1084 | /* cursor HPLL off SR */ |
1078 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
1085 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
1079 | pineview_display_hplloff_wm.fifo_size, |
1086 | pineview_display_hplloff_wm.fifo_size, |
1080 | pixel_size, latency->cursor_hpll_disable); |
1087 | pixel_size, latency->cursor_hpll_disable); |
1081 | reg = I915_READ(DSPFW3); |
1088 | reg = I915_READ(DSPFW3); |
1082 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
1089 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
1083 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
1090 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
1084 | I915_WRITE(DSPFW3, reg); |
1091 | I915_WRITE(DSPFW3, reg); |
1085 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
1092 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
1086 | 1093 | ||
1087 | /* activate cxsr */ |
1094 | /* activate cxsr */ |
1088 | I915_WRITE(DSPFW3, |
1095 | I915_WRITE(DSPFW3, |
1089 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
1096 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
1090 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
1097 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
1091 | } else { |
1098 | } else { |
1092 | pineview_disable_cxsr(dev); |
1099 | pineview_disable_cxsr(dev); |
1093 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
1100 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
1094 | } |
1101 | } |
1095 | } |
1102 | } |
1096 | 1103 | ||
1097 | static bool g4x_compute_wm0(struct drm_device *dev, |
1104 | static bool g4x_compute_wm0(struct drm_device *dev, |
1098 | int plane, |
1105 | int plane, |
1099 | const struct intel_watermark_params *display, |
1106 | const struct intel_watermark_params *display, |
1100 | int display_latency_ns, |
1107 | int display_latency_ns, |
1101 | const struct intel_watermark_params *cursor, |
1108 | const struct intel_watermark_params *cursor, |
1102 | int cursor_latency_ns, |
1109 | int cursor_latency_ns, |
1103 | int *plane_wm, |
1110 | int *plane_wm, |
1104 | int *cursor_wm) |
1111 | int *cursor_wm) |
1105 | { |
1112 | { |
1106 | struct drm_crtc *crtc; |
1113 | struct drm_crtc *crtc; |
1107 | int htotal, hdisplay, clock, pixel_size; |
1114 | int htotal, hdisplay, clock, pixel_size; |
1108 | int line_time_us, line_count; |
1115 | int line_time_us, line_count; |
1109 | int entries, tlb_miss; |
1116 | int entries, tlb_miss; |
1110 | 1117 | ||
1111 | crtc = intel_get_crtc_for_plane(dev, plane); |
1118 | crtc = intel_get_crtc_for_plane(dev, plane); |
1112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1119 | if (!intel_crtc_active(crtc)) { |
1113 | - | ||
1114 | if (crtc->fb == NULL || !crtc->enabled || !intel_crtc->active) { |
- | |
1115 | *cursor_wm = cursor->guard_size; |
1120 | *cursor_wm = cursor->guard_size; |
1116 | *plane_wm = display->guard_size; |
1121 | *plane_wm = display->guard_size; |
1117 | return false; |
1122 | return false; |
1118 | } |
1123 | } |
1119 | 1124 | ||
1120 | htotal = crtc->mode.htotal; |
1125 | htotal = crtc->mode.htotal; |
1121 | hdisplay = crtc->mode.hdisplay; |
1126 | hdisplay = crtc->mode.hdisplay; |
1122 | clock = crtc->mode.clock; |
1127 | clock = crtc->mode.clock; |
1123 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1128 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1124 | 1129 | ||
1125 | /* Use the small buffer method to calculate plane watermark */ |
1130 | /* Use the small buffer method to calculate plane watermark */ |
1126 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
1131 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
1127 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
1132 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
1128 | if (tlb_miss > 0) |
1133 | if (tlb_miss > 0) |
1129 | entries += tlb_miss; |
1134 | entries += tlb_miss; |
1130 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
1135 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
1131 | *plane_wm = entries + display->guard_size; |
1136 | *plane_wm = entries + display->guard_size; |
1132 | if (*plane_wm > (int)display->max_wm) |
1137 | if (*plane_wm > (int)display->max_wm) |
1133 | *plane_wm = display->max_wm; |
1138 | *plane_wm = display->max_wm; |
1134 | 1139 | ||
1135 | /* Use the large buffer method to calculate cursor watermark */ |
1140 | /* Use the large buffer method to calculate cursor watermark */ |
1136 | line_time_us = ((htotal * 1000) / clock); |
1141 | line_time_us = ((htotal * 1000) / clock); |
1137 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
1142 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
1138 | entries = line_count * 64 * pixel_size; |
1143 | entries = line_count * 64 * pixel_size; |
1139 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1144 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1140 | if (tlb_miss > 0) |
1145 | if (tlb_miss > 0) |
1141 | entries += tlb_miss; |
1146 | entries += tlb_miss; |
1142 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1147 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1143 | *cursor_wm = entries + cursor->guard_size; |
1148 | *cursor_wm = entries + cursor->guard_size; |
1144 | if (*cursor_wm > (int)cursor->max_wm) |
1149 | if (*cursor_wm > (int)cursor->max_wm) |
1145 | *cursor_wm = (int)cursor->max_wm; |
1150 | *cursor_wm = (int)cursor->max_wm; |
1146 | 1151 | ||
1147 | return true; |
1152 | return true; |
1148 | } |
1153 | } |
1149 | 1154 | ||
1150 | /* |
1155 | /* |
1151 | * Check the wm result. |
1156 | * Check the wm result. |
1152 | * |
1157 | * |
1153 | * If any calculated watermark values is larger than the maximum value that |
1158 | * If any calculated watermark values is larger than the maximum value that |
1154 | * can be programmed into the associated watermark register, that watermark |
1159 | * can be programmed into the associated watermark register, that watermark |
1155 | * must be disabled. |
1160 | * must be disabled. |
1156 | */ |
1161 | */ |
1157 | static bool g4x_check_srwm(struct drm_device *dev, |
1162 | static bool g4x_check_srwm(struct drm_device *dev, |
1158 | int display_wm, int cursor_wm, |
1163 | int display_wm, int cursor_wm, |
1159 | const struct intel_watermark_params *display, |
1164 | const struct intel_watermark_params *display, |
1160 | const struct intel_watermark_params *cursor) |
1165 | const struct intel_watermark_params *cursor) |
1161 | { |
1166 | { |
1162 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
1167 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
1163 | display_wm, cursor_wm); |
1168 | display_wm, cursor_wm); |
1164 | 1169 | ||
1165 | if (display_wm > display->max_wm) { |
1170 | if (display_wm > display->max_wm) { |
1166 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
1171 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
1167 | display_wm, display->max_wm); |
1172 | display_wm, display->max_wm); |
1168 | return false; |
1173 | return false; |
1169 | } |
1174 | } |
1170 | 1175 | ||
1171 | if (cursor_wm > cursor->max_wm) { |
1176 | if (cursor_wm > cursor->max_wm) { |
1172 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
1177 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
1173 | cursor_wm, cursor->max_wm); |
1178 | cursor_wm, cursor->max_wm); |
1174 | return false; |
1179 | return false; |
1175 | } |
1180 | } |
1176 | 1181 | ||
1177 | if (!(display_wm || cursor_wm)) { |
1182 | if (!(display_wm || cursor_wm)) { |
1178 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
1183 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
1179 | return false; |
1184 | return false; |
1180 | } |
1185 | } |
1181 | 1186 | ||
1182 | return true; |
1187 | return true; |
1183 | } |
1188 | } |
1184 | 1189 | ||
1185 | static bool g4x_compute_srwm(struct drm_device *dev, |
1190 | static bool g4x_compute_srwm(struct drm_device *dev, |
1186 | int plane, |
1191 | int plane, |
1187 | int latency_ns, |
1192 | int latency_ns, |
1188 | const struct intel_watermark_params *display, |
1193 | const struct intel_watermark_params *display, |
1189 | const struct intel_watermark_params *cursor, |
1194 | const struct intel_watermark_params *cursor, |
1190 | int *display_wm, int *cursor_wm) |
1195 | int *display_wm, int *cursor_wm) |
1191 | { |
1196 | { |
1192 | struct drm_crtc *crtc; |
1197 | struct drm_crtc *crtc; |
1193 | int hdisplay, htotal, pixel_size, clock; |
1198 | int hdisplay, htotal, pixel_size, clock; |
1194 | unsigned long line_time_us; |
1199 | unsigned long line_time_us; |
1195 | int line_count, line_size; |
1200 | int line_count, line_size; |
1196 | int small, large; |
1201 | int small, large; |
1197 | int entries; |
1202 | int entries; |
1198 | 1203 | ||
1199 | if (!latency_ns) { |
1204 | if (!latency_ns) { |
1200 | *display_wm = *cursor_wm = 0; |
1205 | *display_wm = *cursor_wm = 0; |
1201 | return false; |
1206 | return false; |
1202 | } |
1207 | } |
1203 | 1208 | ||
1204 | crtc = intel_get_crtc_for_plane(dev, plane); |
1209 | crtc = intel_get_crtc_for_plane(dev, plane); |
1205 | hdisplay = crtc->mode.hdisplay; |
1210 | hdisplay = crtc->mode.hdisplay; |
1206 | htotal = crtc->mode.htotal; |
1211 | htotal = crtc->mode.htotal; |
1207 | clock = crtc->mode.clock; |
1212 | clock = crtc->mode.clock; |
1208 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1213 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1209 | 1214 | ||
1210 | line_time_us = (htotal * 1000) / clock; |
1215 | line_time_us = (htotal * 1000) / clock; |
1211 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1216 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1212 | line_size = hdisplay * pixel_size; |
1217 | line_size = hdisplay * pixel_size; |
1213 | 1218 | ||
1214 | /* Use the minimum of the small and large buffer method for primary */ |
1219 | /* Use the minimum of the small and large buffer method for primary */ |
1215 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1220 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1216 | large = line_count * line_size; |
1221 | large = line_count * line_size; |
1217 | 1222 | ||
1218 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1223 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1219 | *display_wm = entries + display->guard_size; |
1224 | *display_wm = entries + display->guard_size; |
1220 | 1225 | ||
1221 | /* calculate the self-refresh watermark for display cursor */ |
1226 | /* calculate the self-refresh watermark for display cursor */ |
1222 | entries = line_count * pixel_size * 64; |
1227 | entries = line_count * pixel_size * 64; |
1223 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1228 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1224 | *cursor_wm = entries + cursor->guard_size; |
1229 | *cursor_wm = entries + cursor->guard_size; |
1225 | 1230 | ||
1226 | return g4x_check_srwm(dev, |
1231 | return g4x_check_srwm(dev, |
1227 | *display_wm, *cursor_wm, |
1232 | *display_wm, *cursor_wm, |
1228 | display, cursor); |
1233 | display, cursor); |
1229 | } |
1234 | } |
1230 | 1235 | ||
1231 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
1236 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
1232 | int plane, |
1237 | int plane, |
1233 | int *plane_prec_mult, |
1238 | int *plane_prec_mult, |
1234 | int *plane_dl, |
1239 | int *plane_dl, |
1235 | int *cursor_prec_mult, |
1240 | int *cursor_prec_mult, |
1236 | int *cursor_dl) |
1241 | int *cursor_dl) |
1237 | { |
1242 | { |
1238 | struct drm_crtc *crtc; |
1243 | struct drm_crtc *crtc; |
1239 | int clock, pixel_size; |
1244 | int clock, pixel_size; |
1240 | int entries; |
1245 | int entries; |
1241 | 1246 | ||
1242 | crtc = intel_get_crtc_for_plane(dev, plane); |
1247 | crtc = intel_get_crtc_for_plane(dev, plane); |
1243 | if (crtc->fb == NULL || !crtc->enabled) |
1248 | if (!intel_crtc_active(crtc)) |
1244 | return false; |
1249 | return false; |
1245 | 1250 | ||
1246 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
1251 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
1247 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
1252 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
1248 | 1253 | ||
1249 | entries = (clock / 1000) * pixel_size; |
1254 | entries = (clock / 1000) * pixel_size; |
1250 | *plane_prec_mult = (entries > 256) ? |
1255 | *plane_prec_mult = (entries > 256) ? |
1251 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1256 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1252 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
1257 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
1253 | pixel_size); |
1258 | pixel_size); |
1254 | 1259 | ||
1255 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
1260 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
1256 | *cursor_prec_mult = (entries > 256) ? |
1261 | *cursor_prec_mult = (entries > 256) ? |
1257 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1262 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
1258 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
1263 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
1259 | 1264 | ||
1260 | return true; |
1265 | return true; |
1261 | } |
1266 | } |
1262 | 1267 | ||
1263 | /* |
1268 | /* |
1264 | * Update drain latency registers of memory arbiter |
1269 | * Update drain latency registers of memory arbiter |
1265 | * |
1270 | * |
1266 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
1271 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
1267 | * to be programmed. Each plane has a drain latency multiplier and a drain |
1272 | * to be programmed. Each plane has a drain latency multiplier and a drain |
1268 | * latency value. |
1273 | * latency value. |
1269 | */ |
1274 | */ |
1270 | 1275 | ||
1271 | static void vlv_update_drain_latency(struct drm_device *dev) |
1276 | static void vlv_update_drain_latency(struct drm_device *dev) |
1272 | { |
1277 | { |
1273 | struct drm_i915_private *dev_priv = dev->dev_private; |
1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
1274 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
1279 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
1275 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
1280 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
1276 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
1281 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
1277 | either 16 or 32 */ |
1282 | either 16 or 32 */ |
1278 | 1283 | ||
1279 | /* For plane A, Cursor A */ |
1284 | /* For plane A, Cursor A */ |
1280 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
1285 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
1281 | &cursor_prec_mult, &cursora_dl)) { |
1286 | &cursor_prec_mult, &cursora_dl)) { |
1282 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1287 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1283 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
1288 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
1284 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1289 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1285 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
1290 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
1286 | 1291 | ||
1287 | I915_WRITE(VLV_DDL1, cursora_prec | |
1292 | I915_WRITE(VLV_DDL1, cursora_prec | |
1288 | (cursora_dl << DDL_CURSORA_SHIFT) | |
1293 | (cursora_dl << DDL_CURSORA_SHIFT) | |
1289 | planea_prec | planea_dl); |
1294 | planea_prec | planea_dl); |
1290 | } |
1295 | } |
1291 | 1296 | ||
1292 | /* For plane B, Cursor B */ |
1297 | /* For plane B, Cursor B */ |
1293 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
1298 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
1294 | &cursor_prec_mult, &cursorb_dl)) { |
1299 | &cursor_prec_mult, &cursorb_dl)) { |
1295 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1300 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1296 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
1301 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
1297 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1302 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
1298 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
1303 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
1299 | 1304 | ||
1300 | I915_WRITE(VLV_DDL2, cursorb_prec | |
1305 | I915_WRITE(VLV_DDL2, cursorb_prec | |
1301 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
1306 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
1302 | planeb_prec | planeb_dl); |
1307 | planeb_prec | planeb_dl); |
1303 | } |
1308 | } |
1304 | } |
1309 | } |
1305 | 1310 | ||
1306 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1311 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1307 | 1312 | ||
1308 | static void valleyview_update_wm(struct drm_device *dev) |
1313 | static void valleyview_update_wm(struct drm_device *dev) |
1309 | { |
1314 | { |
1310 | static const int sr_latency_ns = 12000; |
1315 | static const int sr_latency_ns = 12000; |
1311 | struct drm_i915_private *dev_priv = dev->dev_private; |
1316 | struct drm_i915_private *dev_priv = dev->dev_private; |
1312 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1317 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1313 | int plane_sr, cursor_sr; |
1318 | int plane_sr, cursor_sr; |
- | 1319 | int ignore_plane_sr, ignore_cursor_sr; |
|
1314 | unsigned int enabled = 0; |
1320 | unsigned int enabled = 0; |
1315 | 1321 | ||
1316 | vlv_update_drain_latency(dev); |
1322 | vlv_update_drain_latency(dev); |
1317 | 1323 | ||
1318 | if (g4x_compute_wm0(dev, 0, |
1324 | if (g4x_compute_wm0(dev, 0, |
1319 | &valleyview_wm_info, latency_ns, |
1325 | &valleyview_wm_info, latency_ns, |
1320 | &valleyview_cursor_wm_info, latency_ns, |
1326 | &valleyview_cursor_wm_info, latency_ns, |
1321 | &planea_wm, &cursora_wm)) |
1327 | &planea_wm, &cursora_wm)) |
1322 | enabled |= 1; |
1328 | enabled |= 1; |
1323 | 1329 | ||
1324 | if (g4x_compute_wm0(dev, 1, |
1330 | if (g4x_compute_wm0(dev, 1, |
1325 | &valleyview_wm_info, latency_ns, |
1331 | &valleyview_wm_info, latency_ns, |
1326 | &valleyview_cursor_wm_info, latency_ns, |
1332 | &valleyview_cursor_wm_info, latency_ns, |
1327 | &planeb_wm, &cursorb_wm)) |
1333 | &planeb_wm, &cursorb_wm)) |
1328 | enabled |= 2; |
1334 | enabled |= 2; |
1329 | - | ||
1330 | plane_sr = cursor_sr = 0; |
1335 | |
1331 | if (single_plane_enabled(enabled) && |
1336 | if (single_plane_enabled(enabled) && |
1332 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1337 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1333 | sr_latency_ns, |
1338 | sr_latency_ns, |
1334 | &valleyview_wm_info, |
1339 | &valleyview_wm_info, |
1335 | &valleyview_cursor_wm_info, |
1340 | &valleyview_cursor_wm_info, |
- | 1341 | &plane_sr, &ignore_cursor_sr) && |
|
- | 1342 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
|
- | 1343 | 2*sr_latency_ns, |
|
- | 1344 | &valleyview_wm_info, |
|
- | 1345 | &valleyview_cursor_wm_info, |
|
1336 | &plane_sr, &cursor_sr)) |
1346 | &ignore_plane_sr, &cursor_sr)) { |
1337 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
1347 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
1338 | else |
1348 | } else { |
1339 | I915_WRITE(FW_BLC_SELF_VLV, |
1349 | I915_WRITE(FW_BLC_SELF_VLV, |
1340 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
1350 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
- | 1351 | plane_sr = cursor_sr = 0; |
|
- | 1352 | } |
|
1341 | 1353 | ||
1342 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1354 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1343 | planea_wm, cursora_wm, |
1355 | planea_wm, cursora_wm, |
1344 | planeb_wm, cursorb_wm, |
1356 | planeb_wm, cursorb_wm, |
1345 | plane_sr, cursor_sr); |
1357 | plane_sr, cursor_sr); |
1346 | 1358 | ||
1347 | I915_WRITE(DSPFW1, |
1359 | I915_WRITE(DSPFW1, |
1348 | (plane_sr << DSPFW_SR_SHIFT) | |
1360 | (plane_sr << DSPFW_SR_SHIFT) | |
1349 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1361 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1350 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1362 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1351 | planea_wm); |
1363 | planea_wm); |
1352 | I915_WRITE(DSPFW2, |
1364 | I915_WRITE(DSPFW2, |
1353 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
1365 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1354 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1366 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1355 | I915_WRITE(DSPFW3, |
1367 | I915_WRITE(DSPFW3, |
1356 | (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT))); |
1368 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
- | 1369 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
|
1357 | } |
1370 | } |
1358 | 1371 | ||
1359 | static void g4x_update_wm(struct drm_device *dev) |
1372 | static void g4x_update_wm(struct drm_device *dev) |
1360 | { |
1373 | { |
1361 | static const int sr_latency_ns = 12000; |
1374 | static const int sr_latency_ns = 12000; |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
1363 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1376 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1364 | int plane_sr, cursor_sr; |
1377 | int plane_sr, cursor_sr; |
1365 | unsigned int enabled = 0; |
1378 | unsigned int enabled = 0; |
1366 | 1379 | ||
1367 | if (g4x_compute_wm0(dev, 0, |
1380 | if (g4x_compute_wm0(dev, 0, |
1368 | &g4x_wm_info, latency_ns, |
1381 | &g4x_wm_info, latency_ns, |
1369 | &g4x_cursor_wm_info, latency_ns, |
1382 | &g4x_cursor_wm_info, latency_ns, |
1370 | &planea_wm, &cursora_wm)) |
1383 | &planea_wm, &cursora_wm)) |
1371 | enabled |= 1; |
1384 | enabled |= 1; |
1372 | 1385 | ||
1373 | if (g4x_compute_wm0(dev, 1, |
1386 | if (g4x_compute_wm0(dev, 1, |
1374 | &g4x_wm_info, latency_ns, |
1387 | &g4x_wm_info, latency_ns, |
1375 | &g4x_cursor_wm_info, latency_ns, |
1388 | &g4x_cursor_wm_info, latency_ns, |
1376 | &planeb_wm, &cursorb_wm)) |
1389 | &planeb_wm, &cursorb_wm)) |
1377 | enabled |= 2; |
1390 | enabled |= 2; |
1378 | - | ||
1379 | plane_sr = cursor_sr = 0; |
1391 | |
1380 | if (single_plane_enabled(enabled) && |
1392 | if (single_plane_enabled(enabled) && |
1381 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1393 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
1382 | sr_latency_ns, |
1394 | sr_latency_ns, |
1383 | &g4x_wm_info, |
1395 | &g4x_wm_info, |
1384 | &g4x_cursor_wm_info, |
1396 | &g4x_cursor_wm_info, |
1385 | &plane_sr, &cursor_sr)) |
1397 | &plane_sr, &cursor_sr)) { |
1386 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1398 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1387 | else |
1399 | } else { |
1388 | I915_WRITE(FW_BLC_SELF, |
1400 | I915_WRITE(FW_BLC_SELF, |
1389 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
1401 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
- | 1402 | plane_sr = cursor_sr = 0; |
|
- | 1403 | } |
|
1390 | 1404 | ||
1391 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1405 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
1392 | planea_wm, cursora_wm, |
1406 | planea_wm, cursora_wm, |
1393 | planeb_wm, cursorb_wm, |
1407 | planeb_wm, cursorb_wm, |
1394 | plane_sr, cursor_sr); |
1408 | plane_sr, cursor_sr); |
1395 | 1409 | ||
1396 | I915_WRITE(DSPFW1, |
1410 | I915_WRITE(DSPFW1, |
1397 | (plane_sr << DSPFW_SR_SHIFT) | |
1411 | (plane_sr << DSPFW_SR_SHIFT) | |
1398 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1412 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
1399 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1413 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
1400 | planea_wm); |
1414 | planea_wm); |
1401 | I915_WRITE(DSPFW2, |
1415 | I915_WRITE(DSPFW2, |
1402 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
1416 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
1403 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1417 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1404 | /* HPLL off in SR has some issues on G4x... disable it */ |
1418 | /* HPLL off in SR has some issues on G4x... disable it */ |
1405 | I915_WRITE(DSPFW3, |
1419 | I915_WRITE(DSPFW3, |
1406 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
1420 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
1407 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1421 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1408 | } |
1422 | } |
1409 | 1423 | ||
1410 | static void i965_update_wm(struct drm_device *dev) |
1424 | static void i965_update_wm(struct drm_device *dev) |
1411 | { |
1425 | { |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; |
1426 | struct drm_i915_private *dev_priv = dev->dev_private; |
1413 | struct drm_crtc *crtc; |
1427 | struct drm_crtc *crtc; |
1414 | int srwm = 1; |
1428 | int srwm = 1; |
1415 | int cursor_sr = 16; |
1429 | int cursor_sr = 16; |
1416 | 1430 | ||
1417 | /* Calc sr entries for one plane configs */ |
1431 | /* Calc sr entries for one plane configs */ |
1418 | crtc = single_enabled_crtc(dev); |
1432 | crtc = single_enabled_crtc(dev); |
1419 | if (crtc) { |
1433 | if (crtc) { |
1420 | /* self-refresh has much higher latency */ |
1434 | /* self-refresh has much higher latency */ |
1421 | static const int sr_latency_ns = 12000; |
1435 | static const int sr_latency_ns = 12000; |
1422 | int clock = crtc->mode.clock; |
1436 | int clock = crtc->mode.clock; |
1423 | int htotal = crtc->mode.htotal; |
1437 | int htotal = crtc->mode.htotal; |
1424 | int hdisplay = crtc->mode.hdisplay; |
1438 | int hdisplay = crtc->mode.hdisplay; |
1425 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1439 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1426 | unsigned long line_time_us; |
1440 | unsigned long line_time_us; |
1427 | int entries; |
1441 | int entries; |
1428 | 1442 | ||
1429 | line_time_us = ((htotal * 1000) / clock); |
1443 | line_time_us = ((htotal * 1000) / clock); |
1430 | 1444 | ||
1431 | /* Use ns/us then divide to preserve precision */ |
1445 | /* Use ns/us then divide to preserve precision */ |
1432 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1446 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1433 | pixel_size * hdisplay; |
1447 | pixel_size * hdisplay; |
1434 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1448 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1435 | srwm = I965_FIFO_SIZE - entries; |
1449 | srwm = I965_FIFO_SIZE - entries; |
1436 | if (srwm < 0) |
1450 | if (srwm < 0) |
1437 | srwm = 1; |
1451 | srwm = 1; |
1438 | srwm &= 0x1ff; |
1452 | srwm &= 0x1ff; |
1439 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1453 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1440 | entries, srwm); |
1454 | entries, srwm); |
1441 | 1455 | ||
1442 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1456 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1443 | pixel_size * 64; |
1457 | pixel_size * 64; |
1444 | entries = DIV_ROUND_UP(entries, |
1458 | entries = DIV_ROUND_UP(entries, |
1445 | i965_cursor_wm_info.cacheline_size); |
1459 | i965_cursor_wm_info.cacheline_size); |
1446 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1460 | cursor_sr = i965_cursor_wm_info.fifo_size - |
1447 | (entries + i965_cursor_wm_info.guard_size); |
1461 | (entries + i965_cursor_wm_info.guard_size); |
1448 | 1462 | ||
1449 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1463 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
1450 | cursor_sr = i965_cursor_wm_info.max_wm; |
1464 | cursor_sr = i965_cursor_wm_info.max_wm; |
1451 | 1465 | ||
1452 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1466 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
1453 | "cursor %d\n", srwm, cursor_sr); |
1467 | "cursor %d\n", srwm, cursor_sr); |
1454 | 1468 | ||
1455 | if (IS_CRESTLINE(dev)) |
1469 | if (IS_CRESTLINE(dev)) |
1456 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1470 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
1457 | } else { |
1471 | } else { |
1458 | /* Turn off self refresh if both pipes are enabled */ |
1472 | /* Turn off self refresh if both pipes are enabled */ |
1459 | if (IS_CRESTLINE(dev)) |
1473 | if (IS_CRESTLINE(dev)) |
1460 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
1474 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
1461 | & ~FW_BLC_SELF_EN); |
1475 | & ~FW_BLC_SELF_EN); |
1462 | } |
1476 | } |
1463 | 1477 | ||
1464 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1478 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
1465 | srwm); |
1479 | srwm); |
1466 | 1480 | ||
1467 | /* 965 has limitations... */ |
1481 | /* 965 has limitations... */ |
1468 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
1482 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
1469 | (8 << 16) | (8 << 8) | (8 << 0)); |
1483 | (8 << 16) | (8 << 8) | (8 << 0)); |
1470 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
1484 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
1471 | /* update cursor SR watermark */ |
1485 | /* update cursor SR watermark */ |
1472 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1486 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1473 | } |
1487 | } |
1474 | 1488 | ||
1475 | static void i9xx_update_wm(struct drm_device *dev) |
1489 | static void i9xx_update_wm(struct drm_device *dev) |
1476 | { |
1490 | { |
1477 | struct drm_i915_private *dev_priv = dev->dev_private; |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; |
1478 | const struct intel_watermark_params *wm_info; |
1492 | const struct intel_watermark_params *wm_info; |
1479 | uint32_t fwater_lo; |
1493 | uint32_t fwater_lo; |
1480 | uint32_t fwater_hi; |
1494 | uint32_t fwater_hi; |
1481 | int cwm, srwm = 1; |
1495 | int cwm, srwm = 1; |
1482 | int fifo_size; |
1496 | int fifo_size; |
1483 | int planea_wm, planeb_wm; |
1497 | int planea_wm, planeb_wm; |
1484 | struct drm_crtc *crtc, *enabled = NULL; |
1498 | struct drm_crtc *crtc, *enabled = NULL; |
1485 | 1499 | ||
1486 | if (IS_I945GM(dev)) |
1500 | if (IS_I945GM(dev)) |
1487 | wm_info = &i945_wm_info; |
1501 | wm_info = &i945_wm_info; |
1488 | else if (!IS_GEN2(dev)) |
1502 | else if (!IS_GEN2(dev)) |
1489 | wm_info = &i915_wm_info; |
1503 | wm_info = &i915_wm_info; |
1490 | else |
1504 | else |
1491 | wm_info = &i855_wm_info; |
1505 | wm_info = &i855_wm_info; |
1492 | 1506 | ||
1493 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1507 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1494 | crtc = intel_get_crtc_for_plane(dev, 0); |
1508 | crtc = intel_get_crtc_for_plane(dev, 0); |
1495 | if (crtc->enabled && crtc->fb) { |
1509 | if (intel_crtc_active(crtc)) { |
- | 1510 | int cpp = crtc->fb->bits_per_pixel / 8; |
|
- | 1511 | if (IS_GEN2(dev)) |
|
- | 1512 | cpp = 4; |
|
- | 1513 | ||
1496 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
1514 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
1497 | wm_info, fifo_size, |
1515 | wm_info, fifo_size, cpp, |
1498 | crtc->fb->bits_per_pixel / 8, |
- | |
1499 | latency_ns); |
1516 | latency_ns); |
1500 | enabled = crtc; |
1517 | enabled = crtc; |
1501 | } else |
1518 | } else |
1502 | planea_wm = fifo_size - wm_info->guard_size; |
1519 | planea_wm = fifo_size - wm_info->guard_size; |
1503 | 1520 | ||
1504 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1521 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1505 | crtc = intel_get_crtc_for_plane(dev, 1); |
1522 | crtc = intel_get_crtc_for_plane(dev, 1); |
1506 | if (crtc->enabled && crtc->fb) { |
1523 | if (intel_crtc_active(crtc)) { |
- | 1524 | int cpp = crtc->fb->bits_per_pixel / 8; |
|
- | 1525 | if (IS_GEN2(dev)) |
|
- | 1526 | cpp = 4; |
|
- | 1527 | ||
1507 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
1528 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
1508 | wm_info, fifo_size, |
1529 | wm_info, fifo_size, cpp, |
1509 | crtc->fb->bits_per_pixel / 8, |
- | |
1510 | latency_ns); |
1530 | latency_ns); |
1511 | if (enabled == NULL) |
1531 | if (enabled == NULL) |
1512 | enabled = crtc; |
1532 | enabled = crtc; |
1513 | else |
1533 | else |
1514 | enabled = NULL; |
1534 | enabled = NULL; |
1515 | } else |
1535 | } else |
1516 | planeb_wm = fifo_size - wm_info->guard_size; |
1536 | planeb_wm = fifo_size - wm_info->guard_size; |
1517 | 1537 | ||
1518 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1538 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
1519 | 1539 | ||
1520 | /* |
1540 | /* |
1521 | * Overlay gets an aggressive default since video jitter is bad. |
1541 | * Overlay gets an aggressive default since video jitter is bad. |
1522 | */ |
1542 | */ |
1523 | cwm = 2; |
1543 | cwm = 2; |
1524 | 1544 | ||
1525 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1545 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
1526 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1546 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1527 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
1547 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
1528 | else if (IS_I915GM(dev)) |
1548 | else if (IS_I915GM(dev)) |
1529 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
1549 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
1530 | 1550 | ||
1531 | /* Calc sr entries for one plane configs */ |
1551 | /* Calc sr entries for one plane configs */ |
1532 | if (HAS_FW_BLC(dev) && enabled) { |
1552 | if (HAS_FW_BLC(dev) && enabled) { |
1533 | /* self-refresh has much higher latency */ |
1553 | /* self-refresh has much higher latency */ |
1534 | static const int sr_latency_ns = 6000; |
1554 | static const int sr_latency_ns = 6000; |
1535 | int clock = enabled->mode.clock; |
1555 | int clock = enabled->mode.clock; |
1536 | int htotal = enabled->mode.htotal; |
1556 | int htotal = enabled->mode.htotal; |
1537 | int hdisplay = enabled->mode.hdisplay; |
1557 | int hdisplay = enabled->mode.hdisplay; |
1538 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1558 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1539 | unsigned long line_time_us; |
1559 | unsigned long line_time_us; |
1540 | int entries; |
1560 | int entries; |
1541 | 1561 | ||
1542 | line_time_us = (htotal * 1000) / clock; |
1562 | line_time_us = (htotal * 1000) / clock; |
1543 | 1563 | ||
1544 | /* Use ns/us then divide to preserve precision */ |
1564 | /* Use ns/us then divide to preserve precision */ |
1545 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1565 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1546 | pixel_size * hdisplay; |
1566 | pixel_size * hdisplay; |
1547 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1567 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1548 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1568 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1549 | srwm = wm_info->fifo_size - entries; |
1569 | srwm = wm_info->fifo_size - entries; |
1550 | if (srwm < 0) |
1570 | if (srwm < 0) |
1551 | srwm = 1; |
1571 | srwm = 1; |
1552 | 1572 | ||
1553 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1573 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1554 | I915_WRITE(FW_BLC_SELF, |
1574 | I915_WRITE(FW_BLC_SELF, |
1555 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1575 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
1556 | else if (IS_I915GM(dev)) |
1576 | else if (IS_I915GM(dev)) |
1557 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1577 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1558 | } |
1578 | } |
1559 | 1579 | ||
1560 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1580 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
1561 | planea_wm, planeb_wm, cwm, srwm); |
1581 | planea_wm, planeb_wm, cwm, srwm); |
1562 | 1582 | ||
1563 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1583 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
1564 | fwater_hi = (cwm & 0x1f); |
1584 | fwater_hi = (cwm & 0x1f); |
1565 | 1585 | ||
1566 | /* Set request length to 8 cachelines per fetch */ |
1586 | /* Set request length to 8 cachelines per fetch */ |
1567 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1587 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
1568 | fwater_hi = fwater_hi | (1 << 8); |
1588 | fwater_hi = fwater_hi | (1 << 8); |
1569 | 1589 | ||
1570 | I915_WRITE(FW_BLC, fwater_lo); |
1590 | I915_WRITE(FW_BLC, fwater_lo); |
1571 | I915_WRITE(FW_BLC2, fwater_hi); |
1591 | I915_WRITE(FW_BLC2, fwater_hi); |
1572 | 1592 | ||
1573 | if (HAS_FW_BLC(dev)) { |
1593 | if (HAS_FW_BLC(dev)) { |
1574 | if (enabled) { |
1594 | if (enabled) { |
1575 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1595 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1576 | I915_WRITE(FW_BLC_SELF, |
1596 | I915_WRITE(FW_BLC_SELF, |
1577 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
1597 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
1578 | else if (IS_I915GM(dev)) |
1598 | else if (IS_I915GM(dev)) |
1579 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
1599 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
1580 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
1600 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
1581 | } else |
1601 | } else |
1582 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
1602 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
1583 | } |
1603 | } |
1584 | } |
1604 | } |
1585 | 1605 | ||
1586 | static void i830_update_wm(struct drm_device *dev) |
1606 | static void i830_update_wm(struct drm_device *dev) |
1587 | { |
1607 | { |
1588 | struct drm_i915_private *dev_priv = dev->dev_private; |
1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
1589 | struct drm_crtc *crtc; |
1609 | struct drm_crtc *crtc; |
1590 | uint32_t fwater_lo; |
1610 | uint32_t fwater_lo; |
1591 | int planea_wm; |
1611 | int planea_wm; |
1592 | 1612 | ||
1593 | crtc = single_enabled_crtc(dev); |
1613 | crtc = single_enabled_crtc(dev); |
1594 | if (crtc == NULL) |
1614 | if (crtc == NULL) |
1595 | return; |
1615 | return; |
1596 | 1616 | ||
1597 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
1617 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
1598 | dev_priv->display.get_fifo_size(dev, 0), |
1618 | dev_priv->display.get_fifo_size(dev, 0), |
1599 | crtc->fb->bits_per_pixel / 8, |
- | |
1600 | latency_ns); |
1619 | 4, latency_ns); |
1601 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1620 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1602 | fwater_lo |= (3<<8) | planea_wm; |
1621 | fwater_lo |= (3<<8) | planea_wm; |
1603 | 1622 | ||
1604 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1623 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
1605 | 1624 | ||
1606 | I915_WRITE(FW_BLC, fwater_lo); |
1625 | I915_WRITE(FW_BLC, fwater_lo); |
1607 | } |
1626 | } |
1608 | 1627 | ||
1609 | #define ILK_LP0_PLANE_LATENCY 700 |
1628 | #define ILK_LP0_PLANE_LATENCY 700 |
1610 | #define ILK_LP0_CURSOR_LATENCY 1300 |
1629 | #define ILK_LP0_CURSOR_LATENCY 1300 |
1611 | 1630 | ||
1612 | /* |
1631 | /* |
1613 | * Check the wm result. |
1632 | * Check the wm result. |
1614 | * |
1633 | * |
1615 | * If any calculated watermark values is larger than the maximum value that |
1634 | * If any calculated watermark values is larger than the maximum value that |
1616 | * can be programmed into the associated watermark register, that watermark |
1635 | * can be programmed into the associated watermark register, that watermark |
1617 | * must be disabled. |
1636 | * must be disabled. |
1618 | */ |
1637 | */ |
1619 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
1638 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
1620 | int fbc_wm, int display_wm, int cursor_wm, |
1639 | int fbc_wm, int display_wm, int cursor_wm, |
1621 | const struct intel_watermark_params *display, |
1640 | const struct intel_watermark_params *display, |
1622 | const struct intel_watermark_params *cursor) |
1641 | const struct intel_watermark_params *cursor) |
1623 | { |
1642 | { |
1624 | struct drm_i915_private *dev_priv = dev->dev_private; |
1643 | struct drm_i915_private *dev_priv = dev->dev_private; |
1625 | 1644 | ||
1626 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
1645 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
1627 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
1646 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
1628 | 1647 | ||
1629 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
1648 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
1630 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
1649 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
1631 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1650 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1632 | 1651 | ||
1633 | /* fbc has it's own way to disable FBC WM */ |
1652 | /* fbc has it's own way to disable FBC WM */ |
1634 | I915_WRITE(DISP_ARB_CTL, |
1653 | I915_WRITE(DISP_ARB_CTL, |
1635 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
1654 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
1636 | return false; |
1655 | return false; |
1637 | } |
1656 | } |
1638 | 1657 | ||
1639 | if (display_wm > display->max_wm) { |
1658 | if (display_wm > display->max_wm) { |
1640 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
1659 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
1641 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1660 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1642 | return false; |
1661 | return false; |
1643 | } |
1662 | } |
1644 | 1663 | ||
1645 | if (cursor_wm > cursor->max_wm) { |
1664 | if (cursor_wm > cursor->max_wm) { |
1646 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
1665 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
1647 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1666 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1648 | return false; |
1667 | return false; |
1649 | } |
1668 | } |
1650 | 1669 | ||
1651 | if (!(fbc_wm || display_wm || cursor_wm)) { |
1670 | if (!(fbc_wm || display_wm || cursor_wm)) { |
1652 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
1671 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
1653 | return false; |
1672 | return false; |
1654 | } |
1673 | } |
1655 | 1674 | ||
1656 | return true; |
1675 | return true; |
1657 | } |
1676 | } |
1658 | 1677 | ||
1659 | /* |
1678 | /* |
1660 | * Compute watermark values of WM[1-3], |
1679 | * Compute watermark values of WM[1-3], |
1661 | */ |
1680 | */ |
1662 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
1681 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
1663 | int latency_ns, |
1682 | int latency_ns, |
1664 | const struct intel_watermark_params *display, |
1683 | const struct intel_watermark_params *display, |
1665 | const struct intel_watermark_params *cursor, |
1684 | const struct intel_watermark_params *cursor, |
1666 | int *fbc_wm, int *display_wm, int *cursor_wm) |
1685 | int *fbc_wm, int *display_wm, int *cursor_wm) |
1667 | { |
1686 | { |
1668 | struct drm_crtc *crtc; |
1687 | struct drm_crtc *crtc; |
1669 | unsigned long line_time_us; |
1688 | unsigned long line_time_us; |
1670 | int hdisplay, htotal, pixel_size, clock; |
1689 | int hdisplay, htotal, pixel_size, clock; |
1671 | int line_count, line_size; |
1690 | int line_count, line_size; |
1672 | int small, large; |
1691 | int small, large; |
1673 | int entries; |
1692 | int entries; |
1674 | 1693 | ||
1675 | if (!latency_ns) { |
1694 | if (!latency_ns) { |
1676 | *fbc_wm = *display_wm = *cursor_wm = 0; |
1695 | *fbc_wm = *display_wm = *cursor_wm = 0; |
1677 | return false; |
1696 | return false; |
1678 | } |
1697 | } |
1679 | 1698 | ||
1680 | crtc = intel_get_crtc_for_plane(dev, plane); |
1699 | crtc = intel_get_crtc_for_plane(dev, plane); |
1681 | hdisplay = crtc->mode.hdisplay; |
1700 | hdisplay = crtc->mode.hdisplay; |
1682 | htotal = crtc->mode.htotal; |
1701 | htotal = crtc->mode.htotal; |
1683 | clock = crtc->mode.clock; |
1702 | clock = crtc->mode.clock; |
1684 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1703 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1685 | 1704 | ||
1686 | line_time_us = (htotal * 1000) / clock; |
1705 | line_time_us = (htotal * 1000) / clock; |
1687 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1706 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1688 | line_size = hdisplay * pixel_size; |
1707 | line_size = hdisplay * pixel_size; |
1689 | 1708 | ||
1690 | /* Use the minimum of the small and large buffer method for primary */ |
1709 | /* Use the minimum of the small and large buffer method for primary */ |
1691 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1710 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
1692 | large = line_count * line_size; |
1711 | large = line_count * line_size; |
1693 | 1712 | ||
1694 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1713 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
1695 | *display_wm = entries + display->guard_size; |
1714 | *display_wm = entries + display->guard_size; |
1696 | 1715 | ||
1697 | /* |
1716 | /* |
1698 | * Spec says: |
1717 | * Spec says: |
1699 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
1718 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
1700 | */ |
1719 | */ |
1701 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
1720 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
1702 | 1721 | ||
1703 | /* calculate the self-refresh watermark for display cursor */ |
1722 | /* calculate the self-refresh watermark for display cursor */ |
1704 | entries = line_count * pixel_size * 64; |
1723 | entries = line_count * pixel_size * 64; |
1705 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1724 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1706 | *cursor_wm = entries + cursor->guard_size; |
1725 | *cursor_wm = entries + cursor->guard_size; |
1707 | 1726 | ||
1708 | return ironlake_check_srwm(dev, level, |
1727 | return ironlake_check_srwm(dev, level, |
1709 | *fbc_wm, *display_wm, *cursor_wm, |
1728 | *fbc_wm, *display_wm, *cursor_wm, |
1710 | display, cursor); |
1729 | display, cursor); |
1711 | } |
1730 | } |
1712 | 1731 | ||
1713 | static void ironlake_update_wm(struct drm_device *dev) |
1732 | static void ironlake_update_wm(struct drm_device *dev) |
1714 | { |
1733 | { |
1715 | struct drm_i915_private *dev_priv = dev->dev_private; |
1734 | struct drm_i915_private *dev_priv = dev->dev_private; |
1716 | int fbc_wm, plane_wm, cursor_wm; |
1735 | int fbc_wm, plane_wm, cursor_wm; |
1717 | unsigned int enabled; |
1736 | unsigned int enabled; |
1718 | 1737 | ||
1719 | enabled = 0; |
1738 | enabled = 0; |
1720 | if (g4x_compute_wm0(dev, 0, |
1739 | if (g4x_compute_wm0(dev, 0, |
1721 | &ironlake_display_wm_info, |
1740 | &ironlake_display_wm_info, |
1722 | ILK_LP0_PLANE_LATENCY, |
1741 | ILK_LP0_PLANE_LATENCY, |
1723 | &ironlake_cursor_wm_info, |
1742 | &ironlake_cursor_wm_info, |
1724 | ILK_LP0_CURSOR_LATENCY, |
1743 | ILK_LP0_CURSOR_LATENCY, |
1725 | &plane_wm, &cursor_wm)) { |
1744 | &plane_wm, &cursor_wm)) { |
1726 | I915_WRITE(WM0_PIPEA_ILK, |
1745 | I915_WRITE(WM0_PIPEA_ILK, |
1727 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1746 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1728 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1747 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1729 | " plane %d, " "cursor: %d\n", |
1748 | " plane %d, " "cursor: %d\n", |
1730 | plane_wm, cursor_wm); |
1749 | plane_wm, cursor_wm); |
1731 | enabled |= 1; |
1750 | enabled |= 1; |
1732 | } |
1751 | } |
1733 | 1752 | ||
1734 | if (g4x_compute_wm0(dev, 1, |
1753 | if (g4x_compute_wm0(dev, 1, |
1735 | &ironlake_display_wm_info, |
1754 | &ironlake_display_wm_info, |
1736 | ILK_LP0_PLANE_LATENCY, |
1755 | ILK_LP0_PLANE_LATENCY, |
1737 | &ironlake_cursor_wm_info, |
1756 | &ironlake_cursor_wm_info, |
1738 | ILK_LP0_CURSOR_LATENCY, |
1757 | ILK_LP0_CURSOR_LATENCY, |
1739 | &plane_wm, &cursor_wm)) { |
1758 | &plane_wm, &cursor_wm)) { |
1740 | I915_WRITE(WM0_PIPEB_ILK, |
1759 | I915_WRITE(WM0_PIPEB_ILK, |
1741 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1760 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
1742 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1761 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1743 | " plane %d, cursor: %d\n", |
1762 | " plane %d, cursor: %d\n", |
1744 | plane_wm, cursor_wm); |
1763 | plane_wm, cursor_wm); |
1745 | enabled |= 2; |
1764 | enabled |= 2; |
1746 | } |
1765 | } |
1747 | 1766 | ||
1748 | /* |
1767 | /* |
1749 | * Calculate and update the self-refresh watermark only when one |
1768 | * Calculate and update the self-refresh watermark only when one |
1750 | * display plane is used. |
1769 | * display plane is used. |
1751 | */ |
1770 | */ |
1752 | I915_WRITE(WM3_LP_ILK, 0); |
1771 | I915_WRITE(WM3_LP_ILK, 0); |
1753 | I915_WRITE(WM2_LP_ILK, 0); |
1772 | I915_WRITE(WM2_LP_ILK, 0); |
1754 | I915_WRITE(WM1_LP_ILK, 0); |
1773 | I915_WRITE(WM1_LP_ILK, 0); |
1755 | 1774 | ||
1756 | if (!single_plane_enabled(enabled)) |
1775 | if (!single_plane_enabled(enabled)) |
1757 | return; |
1776 | return; |
1758 | enabled = ffs(enabled) - 1; |
1777 | enabled = ffs(enabled) - 1; |
1759 | 1778 | ||
1760 | /* WM1 */ |
1779 | /* WM1 */ |
1761 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1780 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1762 | ILK_READ_WM1_LATENCY() * 500, |
1781 | ILK_READ_WM1_LATENCY() * 500, |
1763 | &ironlake_display_srwm_info, |
1782 | &ironlake_display_srwm_info, |
1764 | &ironlake_cursor_srwm_info, |
1783 | &ironlake_cursor_srwm_info, |
1765 | &fbc_wm, &plane_wm, &cursor_wm)) |
1784 | &fbc_wm, &plane_wm, &cursor_wm)) |
1766 | return; |
1785 | return; |
1767 | 1786 | ||
1768 | I915_WRITE(WM1_LP_ILK, |
1787 | I915_WRITE(WM1_LP_ILK, |
1769 | WM1_LP_SR_EN | |
1788 | WM1_LP_SR_EN | |
1770 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1789 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1771 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1790 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1772 | (plane_wm << WM1_LP_SR_SHIFT) | |
1791 | (plane_wm << WM1_LP_SR_SHIFT) | |
1773 | cursor_wm); |
1792 | cursor_wm); |
1774 | 1793 | ||
1775 | /* WM2 */ |
1794 | /* WM2 */ |
1776 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1795 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1777 | ILK_READ_WM2_LATENCY() * 500, |
1796 | ILK_READ_WM2_LATENCY() * 500, |
1778 | &ironlake_display_srwm_info, |
1797 | &ironlake_display_srwm_info, |
1779 | &ironlake_cursor_srwm_info, |
1798 | &ironlake_cursor_srwm_info, |
1780 | &fbc_wm, &plane_wm, &cursor_wm)) |
1799 | &fbc_wm, &plane_wm, &cursor_wm)) |
1781 | return; |
1800 | return; |
1782 | 1801 | ||
1783 | I915_WRITE(WM2_LP_ILK, |
1802 | I915_WRITE(WM2_LP_ILK, |
1784 | WM2_LP_EN | |
1803 | WM2_LP_EN | |
1785 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1804 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1786 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1805 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1787 | (plane_wm << WM1_LP_SR_SHIFT) | |
1806 | (plane_wm << WM1_LP_SR_SHIFT) | |
1788 | cursor_wm); |
1807 | cursor_wm); |
1789 | 1808 | ||
1790 | /* |
1809 | /* |
1791 | * WM3 is unsupported on ILK, probably because we don't have latency |
1810 | * WM3 is unsupported on ILK, probably because we don't have latency |
1792 | * data for that power state |
1811 | * data for that power state |
1793 | */ |
1812 | */ |
1794 | } |
1813 | } |
1795 | 1814 | ||
1796 | static void sandybridge_update_wm(struct drm_device *dev) |
1815 | static void sandybridge_update_wm(struct drm_device *dev) |
1797 | { |
1816 | { |
1798 | struct drm_i915_private *dev_priv = dev->dev_private; |
1817 | struct drm_i915_private *dev_priv = dev->dev_private; |
1799 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1818 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1800 | u32 val; |
1819 | u32 val; |
1801 | int fbc_wm, plane_wm, cursor_wm; |
1820 | int fbc_wm, plane_wm, cursor_wm; |
1802 | unsigned int enabled; |
1821 | unsigned int enabled; |
1803 | 1822 | ||
1804 | enabled = 0; |
1823 | enabled = 0; |
1805 | if (g4x_compute_wm0(dev, 0, |
1824 | if (g4x_compute_wm0(dev, 0, |
1806 | &sandybridge_display_wm_info, latency, |
1825 | &sandybridge_display_wm_info, latency, |
1807 | &sandybridge_cursor_wm_info, latency, |
1826 | &sandybridge_cursor_wm_info, latency, |
1808 | &plane_wm, &cursor_wm)) { |
1827 | &plane_wm, &cursor_wm)) { |
1809 | val = I915_READ(WM0_PIPEA_ILK); |
1828 | val = I915_READ(WM0_PIPEA_ILK); |
1810 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1829 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1811 | I915_WRITE(WM0_PIPEA_ILK, val | |
1830 | I915_WRITE(WM0_PIPEA_ILK, val | |
1812 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1831 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1813 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1832 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
1814 | " plane %d, " "cursor: %d\n", |
1833 | " plane %d, " "cursor: %d\n", |
1815 | plane_wm, cursor_wm); |
1834 | plane_wm, cursor_wm); |
1816 | enabled |= 1; |
1835 | enabled |= 1; |
1817 | } |
1836 | } |
1818 | 1837 | ||
1819 | if (g4x_compute_wm0(dev, 1, |
1838 | if (g4x_compute_wm0(dev, 1, |
1820 | &sandybridge_display_wm_info, latency, |
1839 | &sandybridge_display_wm_info, latency, |
1821 | &sandybridge_cursor_wm_info, latency, |
1840 | &sandybridge_cursor_wm_info, latency, |
1822 | &plane_wm, &cursor_wm)) { |
1841 | &plane_wm, &cursor_wm)) { |
1823 | val = I915_READ(WM0_PIPEB_ILK); |
1842 | val = I915_READ(WM0_PIPEB_ILK); |
1824 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1843 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1825 | I915_WRITE(WM0_PIPEB_ILK, val | |
1844 | I915_WRITE(WM0_PIPEB_ILK, val | |
1826 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1845 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1827 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1846 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
1828 | " plane %d, cursor: %d\n", |
1847 | " plane %d, cursor: %d\n", |
1829 | plane_wm, cursor_wm); |
1848 | plane_wm, cursor_wm); |
1830 | enabled |= 2; |
1849 | enabled |= 2; |
1831 | } |
1850 | } |
- | 1851 | ||
- | 1852 | /* |
|
- | 1853 | * Calculate and update the self-refresh watermark only when one |
|
- | 1854 | * display plane is used. |
|
- | 1855 | * |
|
- | 1856 | * SNB support 3 levels of watermark. |
|
- | 1857 | * |
|
- | 1858 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
|
- | 1859 | * and disabled in the descending order |
|
- | 1860 | * |
|
- | 1861 | */ |
|
- | 1862 | I915_WRITE(WM3_LP_ILK, 0); |
|
- | 1863 | I915_WRITE(WM2_LP_ILK, 0); |
|
- | 1864 | I915_WRITE(WM1_LP_ILK, 0); |
|
- | 1865 | ||
1832 | 1866 | if (!single_plane_enabled(enabled) || |
|
- | 1867 | dev_priv->sprite_scaling_enabled) |
|
- | 1868 | return; |
|
- | 1869 | enabled = ffs(enabled) - 1; |
|
- | 1870 | ||
- | 1871 | /* WM1 */ |
|
- | 1872 | if (!ironlake_compute_srwm(dev, 1, enabled, |
|
- | 1873 | SNB_READ_WM1_LATENCY() * 500, |
|
- | 1874 | &sandybridge_display_srwm_info, |
|
- | 1875 | &sandybridge_cursor_srwm_info, |
|
- | 1876 | &fbc_wm, &plane_wm, &cursor_wm)) |
|
- | 1877 | return; |
|
- | 1878 | ||
- | 1879 | I915_WRITE(WM1_LP_ILK, |
|
- | 1880 | WM1_LP_SR_EN | |
|
- | 1881 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
|
- | 1882 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
|
- | 1883 | (plane_wm << WM1_LP_SR_SHIFT) | |
|
- | 1884 | cursor_wm); |
|
- | 1885 | ||
- | 1886 | /* WM2 */ |
|
- | 1887 | if (!ironlake_compute_srwm(dev, 2, enabled, |
|
- | 1888 | SNB_READ_WM2_LATENCY() * 500, |
|
- | 1889 | &sandybridge_display_srwm_info, |
|
- | 1890 | &sandybridge_cursor_srwm_info, |
|
- | 1891 | &fbc_wm, &plane_wm, &cursor_wm)) |
|
- | 1892 | return; |
|
- | 1893 | ||
- | 1894 | I915_WRITE(WM2_LP_ILK, |
|
- | 1895 | WM2_LP_EN | |
|
- | 1896 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
|
- | 1897 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
|
- | 1898 | (plane_wm << WM1_LP_SR_SHIFT) | |
|
- | 1899 | cursor_wm); |
|
- | 1900 | ||
- | 1901 | /* WM3 */ |
|
- | 1902 | if (!ironlake_compute_srwm(dev, 3, enabled, |
|
- | 1903 | SNB_READ_WM3_LATENCY() * 500, |
|
- | 1904 | &sandybridge_display_srwm_info, |
|
- | 1905 | &sandybridge_cursor_srwm_info, |
|
- | 1906 | &fbc_wm, &plane_wm, &cursor_wm)) |
|
- | 1907 | return; |
|
- | 1908 | ||
- | 1909 | I915_WRITE(WM3_LP_ILK, |
|
- | 1910 | WM3_LP_EN | |
|
- | 1911 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
|
- | 1912 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
|
- | 1913 | (plane_wm << WM1_LP_SR_SHIFT) | |
|
- | 1914 | cursor_wm); |
|
- | 1915 | } |
|
- | 1916 | ||
- | 1917 | static void ivybridge_update_wm(struct drm_device *dev) |
|
- | 1918 | { |
|
- | 1919 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1920 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
|
- | 1921 | u32 val; |
|
- | 1922 | int fbc_wm, plane_wm, cursor_wm; |
|
- | 1923 | int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; |
|
- | 1924 | unsigned int enabled; |
|
- | 1925 | ||
- | 1926 | enabled = 0; |
|
- | 1927 | if (g4x_compute_wm0(dev, 0, |
|
- | 1928 | &sandybridge_display_wm_info, latency, |
|
- | 1929 | &sandybridge_cursor_wm_info, latency, |
|
- | 1930 | &plane_wm, &cursor_wm)) { |
|
- | 1931 | val = I915_READ(WM0_PIPEA_ILK); |
|
- | 1932 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
|
- | 1933 | I915_WRITE(WM0_PIPEA_ILK, val | |
|
- | 1934 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
|
- | 1935 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
|
- | 1936 | " plane %d, " "cursor: %d\n", |
|
- | 1937 | plane_wm, cursor_wm); |
|
- | 1938 | enabled |= 1; |
|
- | 1939 | } |
|
- | 1940 | ||
- | 1941 | if (g4x_compute_wm0(dev, 1, |
|
- | 1942 | &sandybridge_display_wm_info, latency, |
|
- | 1943 | &sandybridge_cursor_wm_info, latency, |
|
- | 1944 | &plane_wm, &cursor_wm)) { |
|
- | 1945 | val = I915_READ(WM0_PIPEB_ILK); |
|
- | 1946 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
|
- | 1947 | I915_WRITE(WM0_PIPEB_ILK, val | |
|
- | 1948 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
|
- | 1949 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
|
- | 1950 | " plane %d, cursor: %d\n", |
|
- | 1951 | plane_wm, cursor_wm); |
|
- | 1952 | enabled |= 2; |
|
- | 1953 | } |
|
1833 | if ((dev_priv->num_pipe == 3) && |
1954 | |
1834 | g4x_compute_wm0(dev, 2, |
1955 | if (g4x_compute_wm0(dev, 2, |
1835 | &sandybridge_display_wm_info, latency, |
1956 | &sandybridge_display_wm_info, latency, |
1836 | &sandybridge_cursor_wm_info, latency, |
1957 | &sandybridge_cursor_wm_info, latency, |
1837 | &plane_wm, &cursor_wm)) { |
1958 | &plane_wm, &cursor_wm)) { |
1838 | val = I915_READ(WM0_PIPEC_IVB); |
1959 | val = I915_READ(WM0_PIPEC_IVB); |
1839 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1960 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
1840 | I915_WRITE(WM0_PIPEC_IVB, val | |
1961 | I915_WRITE(WM0_PIPEC_IVB, val | |
1841 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1962 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
1842 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
1963 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
1843 | " plane %d, cursor: %d\n", |
1964 | " plane %d, cursor: %d\n", |
1844 | plane_wm, cursor_wm); |
1965 | plane_wm, cursor_wm); |
1845 | enabled |= 3; |
1966 | enabled |= 3; |
1846 | } |
1967 | } |
1847 | 1968 | ||
1848 | /* |
1969 | /* |
1849 | * Calculate and update the self-refresh watermark only when one |
1970 | * Calculate and update the self-refresh watermark only when one |
1850 | * display plane is used. |
1971 | * display plane is used. |
1851 | * |
1972 | * |
1852 | * SNB support 3 levels of watermark. |
1973 | * SNB support 3 levels of watermark. |
1853 | * |
1974 | * |
1854 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1975 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
1855 | * and disabled in the descending order |
1976 | * and disabled in the descending order |
1856 | * |
1977 | * |
1857 | */ |
1978 | */ |
1858 | I915_WRITE(WM3_LP_ILK, 0); |
1979 | I915_WRITE(WM3_LP_ILK, 0); |
1859 | I915_WRITE(WM2_LP_ILK, 0); |
1980 | I915_WRITE(WM2_LP_ILK, 0); |
1860 | I915_WRITE(WM1_LP_ILK, 0); |
1981 | I915_WRITE(WM1_LP_ILK, 0); |
1861 | 1982 | ||
1862 | if (!single_plane_enabled(enabled) || |
1983 | if (!single_plane_enabled(enabled) || |
1863 | dev_priv->sprite_scaling_enabled) |
1984 | dev_priv->sprite_scaling_enabled) |
1864 | return; |
1985 | return; |
1865 | enabled = ffs(enabled) - 1; |
1986 | enabled = ffs(enabled) - 1; |
1866 | 1987 | ||
1867 | /* WM1 */ |
1988 | /* WM1 */ |
1868 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1989 | if (!ironlake_compute_srwm(dev, 1, enabled, |
1869 | SNB_READ_WM1_LATENCY() * 500, |
1990 | SNB_READ_WM1_LATENCY() * 500, |
1870 | &sandybridge_display_srwm_info, |
1991 | &sandybridge_display_srwm_info, |
1871 | &sandybridge_cursor_srwm_info, |
1992 | &sandybridge_cursor_srwm_info, |
1872 | &fbc_wm, &plane_wm, &cursor_wm)) |
1993 | &fbc_wm, &plane_wm, &cursor_wm)) |
1873 | return; |
1994 | return; |
1874 | 1995 | ||
1875 | I915_WRITE(WM1_LP_ILK, |
1996 | I915_WRITE(WM1_LP_ILK, |
1876 | WM1_LP_SR_EN | |
1997 | WM1_LP_SR_EN | |
1877 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1998 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1878 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1999 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1879 | (plane_wm << WM1_LP_SR_SHIFT) | |
2000 | (plane_wm << WM1_LP_SR_SHIFT) | |
1880 | cursor_wm); |
2001 | cursor_wm); |
1881 | 2002 | ||
1882 | /* WM2 */ |
2003 | /* WM2 */ |
1883 | if (!ironlake_compute_srwm(dev, 2, enabled, |
2004 | if (!ironlake_compute_srwm(dev, 2, enabled, |
1884 | SNB_READ_WM2_LATENCY() * 500, |
2005 | SNB_READ_WM2_LATENCY() * 500, |
1885 | &sandybridge_display_srwm_info, |
2006 | &sandybridge_display_srwm_info, |
1886 | &sandybridge_cursor_srwm_info, |
2007 | &sandybridge_cursor_srwm_info, |
1887 | &fbc_wm, &plane_wm, &cursor_wm)) |
2008 | &fbc_wm, &plane_wm, &cursor_wm)) |
1888 | return; |
2009 | return; |
1889 | 2010 | ||
1890 | I915_WRITE(WM2_LP_ILK, |
2011 | I915_WRITE(WM2_LP_ILK, |
1891 | WM2_LP_EN | |
2012 | WM2_LP_EN | |
1892 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2013 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1893 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2014 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1894 | (plane_wm << WM1_LP_SR_SHIFT) | |
2015 | (plane_wm << WM1_LP_SR_SHIFT) | |
1895 | cursor_wm); |
2016 | cursor_wm); |
1896 | 2017 | ||
1897 | /* WM3 */ |
2018 | /* WM3, note we have to correct the cursor latency */ |
1898 | if (!ironlake_compute_srwm(dev, 3, enabled, |
2019 | if (!ironlake_compute_srwm(dev, 3, enabled, |
1899 | SNB_READ_WM3_LATENCY() * 500, |
2020 | SNB_READ_WM3_LATENCY() * 500, |
1900 | &sandybridge_display_srwm_info, |
2021 | &sandybridge_display_srwm_info, |
1901 | &sandybridge_cursor_srwm_info, |
2022 | &sandybridge_cursor_srwm_info, |
1902 | &fbc_wm, &plane_wm, &cursor_wm)) |
2023 | &fbc_wm, &plane_wm, &ignore_cursor_wm) || |
- | 2024 | !ironlake_compute_srwm(dev, 3, enabled, |
|
- | 2025 | 2 * SNB_READ_WM3_LATENCY() * 500, |
|
- | 2026 | &sandybridge_display_srwm_info, |
|
- | 2027 | &sandybridge_cursor_srwm_info, |
|
- | 2028 | &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) |
|
1903 | return; |
2029 | return; |
1904 | 2030 | ||
1905 | I915_WRITE(WM3_LP_ILK, |
2031 | I915_WRITE(WM3_LP_ILK, |
1906 | WM3_LP_EN | |
2032 | WM3_LP_EN | |
1907 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
2033 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
1908 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
2034 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
1909 | (plane_wm << WM1_LP_SR_SHIFT) | |
2035 | (plane_wm << WM1_LP_SR_SHIFT) | |
1910 | cursor_wm); |
2036 | cursor_wm); |
1911 | } |
2037 | } |
1912 | 2038 | ||
1913 | static void |
2039 | static void |
1914 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, |
2040 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, |
1915 | struct drm_display_mode *mode) |
2041 | struct drm_display_mode *mode) |
1916 | { |
2042 | { |
1917 | struct drm_i915_private *dev_priv = dev->dev_private; |
2043 | struct drm_i915_private *dev_priv = dev->dev_private; |
1918 | u32 temp; |
2044 | u32 temp; |
1919 | 2045 | ||
1920 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); |
2046 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); |
1921 | temp &= ~PIPE_WM_LINETIME_MASK; |
2047 | temp &= ~PIPE_WM_LINETIME_MASK; |
1922 | 2048 | ||
1923 | /* The WM are computed with base on how long it takes to fill a single |
2049 | /* The WM are computed with base on how long it takes to fill a single |
1924 | * row at the given clock rate, multiplied by 8. |
2050 | * row at the given clock rate, multiplied by 8. |
1925 | * */ |
2051 | * */ |
1926 | temp |= PIPE_WM_LINETIME_TIME( |
2052 | temp |= PIPE_WM_LINETIME_TIME( |
1927 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); |
2053 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); |
1928 | 2054 | ||
1929 | /* IPS watermarks are only used by pipe A, and are ignored by |
2055 | /* IPS watermarks are only used by pipe A, and are ignored by |
1930 | * pipes B and C. They are calculated similarly to the common |
2056 | * pipes B and C. They are calculated similarly to the common |
1931 | * linetime values, except that we are using CD clock frequency |
2057 | * linetime values, except that we are using CD clock frequency |
1932 | * in MHz instead of pixel rate for the division. |
2058 | * in MHz instead of pixel rate for the division. |
1933 | * |
2059 | * |
1934 | * This is a placeholder for the IPS watermark calculation code. |
2060 | * This is a placeholder for the IPS watermark calculation code. |
1935 | */ |
2061 | */ |
1936 | 2062 | ||
1937 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); |
2063 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); |
1938 | } |
2064 | } |
1939 | 2065 | ||
1940 | static bool |
2066 | static bool |
1941 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
2067 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
1942 | uint32_t sprite_width, int pixel_size, |
2068 | uint32_t sprite_width, int pixel_size, |
1943 | const struct intel_watermark_params *display, |
2069 | const struct intel_watermark_params *display, |
1944 | int display_latency_ns, int *sprite_wm) |
2070 | int display_latency_ns, int *sprite_wm) |
1945 | { |
2071 | { |
1946 | struct drm_crtc *crtc; |
2072 | struct drm_crtc *crtc; |
1947 | int clock; |
2073 | int clock; |
1948 | int entries, tlb_miss; |
2074 | int entries, tlb_miss; |
1949 | 2075 | ||
1950 | crtc = intel_get_crtc_for_plane(dev, plane); |
2076 | crtc = intel_get_crtc_for_plane(dev, plane); |
1951 | if (crtc->fb == NULL || !crtc->enabled) { |
2077 | if (!intel_crtc_active(crtc)) { |
1952 | *sprite_wm = display->guard_size; |
2078 | *sprite_wm = display->guard_size; |
1953 | return false; |
2079 | return false; |
1954 | } |
2080 | } |
1955 | 2081 | ||
1956 | clock = crtc->mode.clock; |
2082 | clock = crtc->mode.clock; |
1957 | 2083 | ||
1958 | /* Use the small buffer method to calculate the sprite watermark */ |
2084 | /* Use the small buffer method to calculate the sprite watermark */ |
1959 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
2085 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
1960 | tlb_miss = display->fifo_size*display->cacheline_size - |
2086 | tlb_miss = display->fifo_size*display->cacheline_size - |
1961 | sprite_width * 8; |
2087 | sprite_width * 8; |
1962 | if (tlb_miss > 0) |
2088 | if (tlb_miss > 0) |
1963 | entries += tlb_miss; |
2089 | entries += tlb_miss; |
1964 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
2090 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
1965 | *sprite_wm = entries + display->guard_size; |
2091 | *sprite_wm = entries + display->guard_size; |
1966 | if (*sprite_wm > (int)display->max_wm) |
2092 | if (*sprite_wm > (int)display->max_wm) |
1967 | *sprite_wm = display->max_wm; |
2093 | *sprite_wm = display->max_wm; |
1968 | 2094 | ||
1969 | return true; |
2095 | return true; |
1970 | } |
2096 | } |
1971 | 2097 | ||
1972 | static bool |
2098 | static bool |
1973 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
2099 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
1974 | uint32_t sprite_width, int pixel_size, |
2100 | uint32_t sprite_width, int pixel_size, |
1975 | const struct intel_watermark_params *display, |
2101 | const struct intel_watermark_params *display, |
1976 | int latency_ns, int *sprite_wm) |
2102 | int latency_ns, int *sprite_wm) |
1977 | { |
2103 | { |
1978 | struct drm_crtc *crtc; |
2104 | struct drm_crtc *crtc; |
1979 | unsigned long line_time_us; |
2105 | unsigned long line_time_us; |
1980 | int clock; |
2106 | int clock; |
1981 | int line_count, line_size; |
2107 | int line_count, line_size; |
1982 | int small, large; |
2108 | int small, large; |
1983 | int entries; |
2109 | int entries; |
1984 | 2110 | ||
1985 | if (!latency_ns) { |
2111 | if (!latency_ns) { |
1986 | *sprite_wm = 0; |
2112 | *sprite_wm = 0; |
1987 | return false; |
2113 | return false; |
1988 | } |
2114 | } |
1989 | 2115 | ||
1990 | crtc = intel_get_crtc_for_plane(dev, plane); |
2116 | crtc = intel_get_crtc_for_plane(dev, plane); |
1991 | clock = crtc->mode.clock; |
2117 | clock = crtc->mode.clock; |
1992 | if (!clock) { |
2118 | if (!clock) { |
1993 | *sprite_wm = 0; |
2119 | *sprite_wm = 0; |
1994 | return false; |
2120 | return false; |
1995 | } |
2121 | } |
1996 | 2122 | ||
1997 | line_time_us = (sprite_width * 1000) / clock; |
2123 | line_time_us = (sprite_width * 1000) / clock; |
1998 | if (!line_time_us) { |
2124 | if (!line_time_us) { |
1999 | *sprite_wm = 0; |
2125 | *sprite_wm = 0; |
2000 | return false; |
2126 | return false; |
2001 | } |
2127 | } |
2002 | 2128 | ||
2003 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
2129 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
2004 | line_size = sprite_width * pixel_size; |
2130 | line_size = sprite_width * pixel_size; |
2005 | 2131 | ||
2006 | /* Use the minimum of the small and large buffer method for primary */ |
2132 | /* Use the minimum of the small and large buffer method for primary */ |
2007 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
2133 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
2008 | large = line_count * line_size; |
2134 | large = line_count * line_size; |
2009 | 2135 | ||
2010 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
2136 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
2011 | *sprite_wm = entries + display->guard_size; |
2137 | *sprite_wm = entries + display->guard_size; |
2012 | 2138 | ||
2013 | return *sprite_wm > 0x3ff ? false : true; |
2139 | return *sprite_wm > 0x3ff ? false : true; |
2014 | } |
2140 | } |
2015 | 2141 | ||
2016 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
2142 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
2017 | uint32_t sprite_width, int pixel_size) |
2143 | uint32_t sprite_width, int pixel_size) |
2018 | { |
2144 | { |
2019 | struct drm_i915_private *dev_priv = dev->dev_private; |
2145 | struct drm_i915_private *dev_priv = dev->dev_private; |
2020 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
2146 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
2021 | u32 val; |
2147 | u32 val; |
2022 | int sprite_wm, reg; |
2148 | int sprite_wm, reg; |
2023 | int ret; |
2149 | int ret; |
2024 | 2150 | ||
2025 | switch (pipe) { |
2151 | switch (pipe) { |
2026 | case 0: |
2152 | case 0: |
2027 | reg = WM0_PIPEA_ILK; |
2153 | reg = WM0_PIPEA_ILK; |
2028 | break; |
2154 | break; |
2029 | case 1: |
2155 | case 1: |
2030 | reg = WM0_PIPEB_ILK; |
2156 | reg = WM0_PIPEB_ILK; |
2031 | break; |
2157 | break; |
2032 | case 2: |
2158 | case 2: |
2033 | reg = WM0_PIPEC_IVB; |
2159 | reg = WM0_PIPEC_IVB; |
2034 | break; |
2160 | break; |
2035 | default: |
2161 | default: |
2036 | return; /* bad pipe */ |
2162 | return; /* bad pipe */ |
2037 | } |
2163 | } |
2038 | 2164 | ||
2039 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
2165 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
2040 | &sandybridge_display_wm_info, |
2166 | &sandybridge_display_wm_info, |
2041 | latency, &sprite_wm); |
2167 | latency, &sprite_wm); |
2042 | if (!ret) { |
2168 | if (!ret) { |
2043 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
2169 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
2044 | pipe); |
2170 | pipe); |
2045 | return; |
2171 | return; |
2046 | } |
2172 | } |
2047 | 2173 | ||
2048 | val = I915_READ(reg); |
2174 | val = I915_READ(reg); |
2049 | val &= ~WM0_PIPE_SPRITE_MASK; |
2175 | val &= ~WM0_PIPE_SPRITE_MASK; |
2050 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
2176 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
2051 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
2177 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
2052 | 2178 | ||
2053 | 2179 | ||
2054 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2180 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2055 | pixel_size, |
2181 | pixel_size, |
2056 | &sandybridge_display_srwm_info, |
2182 | &sandybridge_display_srwm_info, |
2057 | SNB_READ_WM1_LATENCY() * 500, |
2183 | SNB_READ_WM1_LATENCY() * 500, |
2058 | &sprite_wm); |
2184 | &sprite_wm); |
2059 | if (!ret) { |
2185 | if (!ret) { |
2060 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
2186 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
2061 | pipe); |
2187 | pipe); |
2062 | return; |
2188 | return; |
2063 | } |
2189 | } |
2064 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
2190 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
2065 | 2191 | ||
2066 | /* Only IVB has two more LP watermarks for sprite */ |
2192 | /* Only IVB has two more LP watermarks for sprite */ |
2067 | if (!IS_IVYBRIDGE(dev)) |
2193 | if (!IS_IVYBRIDGE(dev)) |
2068 | return; |
2194 | return; |
2069 | 2195 | ||
2070 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2196 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2071 | pixel_size, |
2197 | pixel_size, |
2072 | &sandybridge_display_srwm_info, |
2198 | &sandybridge_display_srwm_info, |
2073 | SNB_READ_WM2_LATENCY() * 500, |
2199 | SNB_READ_WM2_LATENCY() * 500, |
2074 | &sprite_wm); |
2200 | &sprite_wm); |
2075 | if (!ret) { |
2201 | if (!ret) { |
2076 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
2202 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
2077 | pipe); |
2203 | pipe); |
2078 | return; |
2204 | return; |
2079 | } |
2205 | } |
2080 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
2206 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
2081 | 2207 | ||
2082 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2208 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
2083 | pixel_size, |
2209 | pixel_size, |
2084 | &sandybridge_display_srwm_info, |
2210 | &sandybridge_display_srwm_info, |
2085 | SNB_READ_WM3_LATENCY() * 500, |
2211 | SNB_READ_WM3_LATENCY() * 500, |
2086 | &sprite_wm); |
2212 | &sprite_wm); |
2087 | if (!ret) { |
2213 | if (!ret) { |
2088 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
2214 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
2089 | pipe); |
2215 | pipe); |
2090 | return; |
2216 | return; |
2091 | } |
2217 | } |
2092 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
2218 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
2093 | } |
2219 | } |
2094 | 2220 | ||
2095 | /** |
2221 | /** |
2096 | * intel_update_watermarks - update FIFO watermark values based on current modes |
2222 | * intel_update_watermarks - update FIFO watermark values based on current modes |
2097 | * |
2223 | * |
2098 | * Calculate watermark values for the various WM regs based on current mode |
2224 | * Calculate watermark values for the various WM regs based on current mode |
2099 | * and plane configuration. |
2225 | * and plane configuration. |
2100 | * |
2226 | * |
2101 | * There are several cases to deal with here: |
2227 | * There are several cases to deal with here: |
2102 | * - normal (i.e. non-self-refresh) |
2228 | * - normal (i.e. non-self-refresh) |
2103 | * - self-refresh (SR) mode |
2229 | * - self-refresh (SR) mode |
2104 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
2230 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
2105 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
2231 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
2106 | * lines), so need to account for TLB latency |
2232 | * lines), so need to account for TLB latency |
2107 | * |
2233 | * |
2108 | * The normal calculation is: |
2234 | * The normal calculation is: |
2109 | * watermark = dotclock * bytes per pixel * latency |
2235 | * watermark = dotclock * bytes per pixel * latency |
2110 | * where latency is platform & configuration dependent (we assume pessimal |
2236 | * where latency is platform & configuration dependent (we assume pessimal |
2111 | * values here). |
2237 | * values here). |
2112 | * |
2238 | * |
2113 | * The SR calculation is: |
2239 | * The SR calculation is: |
2114 | * watermark = (trunc(latency/line time)+1) * surface width * |
2240 | * watermark = (trunc(latency/line time)+1) * surface width * |
2115 | * bytes per pixel |
2241 | * bytes per pixel |
2116 | * where |
2242 | * where |
2117 | * line time = htotal / dotclock |
2243 | * line time = htotal / dotclock |
2118 | * surface width = hdisplay for normal plane and 64 for cursor |
2244 | * surface width = hdisplay for normal plane and 64 for cursor |
2119 | * and latency is assumed to be high, as above. |
2245 | * and latency is assumed to be high, as above. |
2120 | * |
2246 | * |
2121 | * The final value programmed to the register should always be rounded up, |
2247 | * The final value programmed to the register should always be rounded up, |
2122 | * and include an extra 2 entries to account for clock crossings. |
2248 | * and include an extra 2 entries to account for clock crossings. |
2123 | * |
2249 | * |
2124 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
2250 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
2125 | * to set the non-SR watermarks to 8. |
2251 | * to set the non-SR watermarks to 8. |
2126 | */ |
2252 | */ |
2127 | void intel_update_watermarks(struct drm_device *dev) |
2253 | void intel_update_watermarks(struct drm_device *dev) |
2128 | { |
2254 | { |
2129 | struct drm_i915_private *dev_priv = dev->dev_private; |
2255 | struct drm_i915_private *dev_priv = dev->dev_private; |
2130 | 2256 | ||
2131 | if (dev_priv->display.update_wm) |
2257 | if (dev_priv->display.update_wm) |
2132 | dev_priv->display.update_wm(dev); |
2258 | dev_priv->display.update_wm(dev); |
2133 | } |
2259 | } |
2134 | 2260 | ||
2135 | void intel_update_linetime_watermarks(struct drm_device *dev, |
2261 | void intel_update_linetime_watermarks(struct drm_device *dev, |
2136 | int pipe, struct drm_display_mode *mode) |
2262 | int pipe, struct drm_display_mode *mode) |
2137 | { |
2263 | { |
2138 | struct drm_i915_private *dev_priv = dev->dev_private; |
2264 | struct drm_i915_private *dev_priv = dev->dev_private; |
2139 | 2265 | ||
2140 | if (dev_priv->display.update_linetime_wm) |
2266 | if (dev_priv->display.update_linetime_wm) |
2141 | dev_priv->display.update_linetime_wm(dev, pipe, mode); |
2267 | dev_priv->display.update_linetime_wm(dev, pipe, mode); |
2142 | } |
2268 | } |
2143 | 2269 | ||
2144 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
2270 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
2145 | uint32_t sprite_width, int pixel_size) |
2271 | uint32_t sprite_width, int pixel_size) |
2146 | { |
2272 | { |
2147 | struct drm_i915_private *dev_priv = dev->dev_private; |
2273 | struct drm_i915_private *dev_priv = dev->dev_private; |
2148 | 2274 | ||
2149 | if (dev_priv->display.update_sprite_wm) |
2275 | if (dev_priv->display.update_sprite_wm) |
2150 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
2276 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
2151 | pixel_size); |
2277 | pixel_size); |
2152 | } |
2278 | } |
2153 | 2279 | ||
2154 | static struct drm_i915_gem_object * |
2280 | static struct drm_i915_gem_object * |
2155 | intel_alloc_context_page(struct drm_device *dev) |
2281 | intel_alloc_context_page(struct drm_device *dev) |
2156 | { |
2282 | { |
2157 | struct drm_i915_gem_object *ctx; |
2283 | struct drm_i915_gem_object *ctx; |
2158 | int ret; |
2284 | int ret; |
2159 | 2285 | ||
2160 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2286 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2161 | 2287 | ||
2162 | ctx = i915_gem_alloc_object(dev, 4096); |
2288 | ctx = i915_gem_alloc_object(dev, 4096); |
2163 | if (!ctx) { |
2289 | if (!ctx) { |
2164 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
2290 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
2165 | return NULL; |
2291 | return NULL; |
2166 | } |
2292 | } |
2167 | 2293 | ||
2168 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
2294 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
2169 | if (ret) { |
2295 | if (ret) { |
2170 | DRM_ERROR("failed to pin power context: %d\n", ret); |
2296 | DRM_ERROR("failed to pin power context: %d\n", ret); |
2171 | goto err_unref; |
2297 | goto err_unref; |
2172 | } |
2298 | } |
2173 | 2299 | ||
2174 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
2300 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
2175 | if (ret) { |
2301 | if (ret) { |
2176 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
2302 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
2177 | goto err_unpin; |
2303 | goto err_unpin; |
2178 | } |
2304 | } |
2179 | 2305 | ||
2180 | return ctx; |
2306 | return ctx; |
2181 | 2307 | ||
2182 | err_unpin: |
2308 | err_unpin: |
2183 | i915_gem_object_unpin(ctx); |
2309 | i915_gem_object_unpin(ctx); |
2184 | err_unref: |
2310 | err_unref: |
2185 | drm_gem_object_unreference(&ctx->base); |
2311 | drm_gem_object_unreference(&ctx->base); |
2186 | mutex_unlock(&dev->struct_mutex); |
2312 | mutex_unlock(&dev->struct_mutex); |
2187 | return NULL; |
2313 | return NULL; |
2188 | } |
2314 | } |
2189 | 2315 | ||
2190 | /** |
2316 | /** |
2191 | * Lock protecting IPS related data structures |
2317 | * Lock protecting IPS related data structures |
2192 | */ |
2318 | */ |
2193 | DEFINE_SPINLOCK(mchdev_lock); |
2319 | DEFINE_SPINLOCK(mchdev_lock); |
2194 | 2320 | ||
2195 | /* Global for IPS driver to get at the current i915 device. Protected by |
2321 | /* Global for IPS driver to get at the current i915 device. Protected by |
2196 | * mchdev_lock. */ |
2322 | * mchdev_lock. */ |
2197 | static struct drm_i915_private *i915_mch_dev; |
2323 | static struct drm_i915_private *i915_mch_dev; |
2198 | 2324 | ||
2199 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2325 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2200 | { |
2326 | { |
2201 | struct drm_i915_private *dev_priv = dev->dev_private; |
2327 | struct drm_i915_private *dev_priv = dev->dev_private; |
2202 | u16 rgvswctl; |
2328 | u16 rgvswctl; |
2203 | 2329 | ||
2204 | assert_spin_locked(&mchdev_lock); |
2330 | assert_spin_locked(&mchdev_lock); |
2205 | 2331 | ||
2206 | rgvswctl = I915_READ16(MEMSWCTL); |
2332 | rgvswctl = I915_READ16(MEMSWCTL); |
2207 | if (rgvswctl & MEMCTL_CMD_STS) { |
2333 | if (rgvswctl & MEMCTL_CMD_STS) { |
2208 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
2334 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
2209 | return false; /* still busy with another command */ |
2335 | return false; /* still busy with another command */ |
2210 | } |
2336 | } |
2211 | 2337 | ||
2212 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
2338 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
2213 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
2339 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
2214 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2340 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2215 | POSTING_READ16(MEMSWCTL); |
2341 | POSTING_READ16(MEMSWCTL); |
2216 | 2342 | ||
2217 | rgvswctl |= MEMCTL_CMD_STS; |
2343 | rgvswctl |= MEMCTL_CMD_STS; |
2218 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2344 | I915_WRITE16(MEMSWCTL, rgvswctl); |
2219 | 2345 | ||
2220 | return true; |
2346 | return true; |
2221 | } |
2347 | } |
2222 | 2348 | ||
2223 | static void ironlake_enable_drps(struct drm_device *dev) |
2349 | static void ironlake_enable_drps(struct drm_device *dev) |
2224 | { |
2350 | { |
2225 | struct drm_i915_private *dev_priv = dev->dev_private; |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; |
2226 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
2352 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
2227 | u8 fmax, fmin, fstart, vstart; |
2353 | u8 fmax, fmin, fstart, vstart; |
2228 | 2354 | ||
2229 | spin_lock_irq(&mchdev_lock); |
2355 | spin_lock_irq(&mchdev_lock); |
2230 | 2356 | ||
2231 | /* Enable temp reporting */ |
2357 | /* Enable temp reporting */ |
2232 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
2358 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
2233 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
2359 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
2234 | 2360 | ||
2235 | /* 100ms RC evaluation intervals */ |
2361 | /* 100ms RC evaluation intervals */ |
2236 | I915_WRITE(RCUPEI, 100000); |
2362 | I915_WRITE(RCUPEI, 100000); |
2237 | I915_WRITE(RCDNEI, 100000); |
2363 | I915_WRITE(RCDNEI, 100000); |
2238 | 2364 | ||
2239 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
2365 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
2240 | I915_WRITE(RCBMAXAVG, 90000); |
2366 | I915_WRITE(RCBMAXAVG, 90000); |
2241 | I915_WRITE(RCBMINAVG, 80000); |
2367 | I915_WRITE(RCBMINAVG, 80000); |
2242 | 2368 | ||
2243 | I915_WRITE(MEMIHYST, 1); |
2369 | I915_WRITE(MEMIHYST, 1); |
2244 | 2370 | ||
2245 | /* Set up min, max, and cur for interrupt handling */ |
2371 | /* Set up min, max, and cur for interrupt handling */ |
2246 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
2372 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
2247 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
2373 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
2248 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
2374 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
2249 | MEMMODE_FSTART_SHIFT; |
2375 | MEMMODE_FSTART_SHIFT; |
2250 | 2376 | ||
2251 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
2377 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
2252 | PXVFREQ_PX_SHIFT; |
2378 | PXVFREQ_PX_SHIFT; |
2253 | 2379 | ||
2254 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2380 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2255 | dev_priv->ips.fstart = fstart; |
2381 | dev_priv->ips.fstart = fstart; |
2256 | 2382 | ||
2257 | dev_priv->ips.max_delay = fstart; |
2383 | dev_priv->ips.max_delay = fstart; |
2258 | dev_priv->ips.min_delay = fmin; |
2384 | dev_priv->ips.min_delay = fmin; |
2259 | dev_priv->ips.cur_delay = fstart; |
2385 | dev_priv->ips.cur_delay = fstart; |
2260 | 2386 | ||
2261 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
2387 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
2262 | fmax, fmin, fstart); |
2388 | fmax, fmin, fstart); |
2263 | 2389 | ||
2264 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
2390 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
2265 | 2391 | ||
2266 | /* |
2392 | /* |
2267 | * Interrupts will be enabled in ironlake_irq_postinstall |
2393 | * Interrupts will be enabled in ironlake_irq_postinstall |
2268 | */ |
2394 | */ |
2269 | 2395 | ||
2270 | I915_WRITE(VIDSTART, vstart); |
2396 | I915_WRITE(VIDSTART, vstart); |
2271 | POSTING_READ(VIDSTART); |
2397 | POSTING_READ(VIDSTART); |
2272 | 2398 | ||
2273 | rgvmodectl |= MEMMODE_SWMODE_EN; |
2399 | rgvmodectl |= MEMMODE_SWMODE_EN; |
2274 | I915_WRITE(MEMMODECTL, rgvmodectl); |
2400 | I915_WRITE(MEMMODECTL, rgvmodectl); |
2275 | 2401 | ||
2276 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2402 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2277 | DRM_ERROR("stuck trying to change perf mode\n"); |
2403 | DRM_ERROR("stuck trying to change perf mode\n"); |
2278 | mdelay(1); |
2404 | mdelay(1); |
2279 | 2405 | ||
2280 | ironlake_set_drps(dev, fstart); |
2406 | ironlake_set_drps(dev, fstart); |
2281 | 2407 | ||
2282 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2408 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2283 | I915_READ(0x112e0); |
2409 | I915_READ(0x112e0); |
2284 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2410 | dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks()); |
2285 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
2411 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
2286 | // getrawmonotonic(&dev_priv->ips.last_time2); |
2412 | // getrawmonotonic(&dev_priv->ips.last_time2); |
2287 | 2413 | ||
2288 | spin_unlock_irq(&mchdev_lock); |
2414 | spin_unlock_irq(&mchdev_lock); |
2289 | } |
2415 | } |
2290 | 2416 | ||
2291 | static void ironlake_disable_drps(struct drm_device *dev) |
2417 | static void ironlake_disable_drps(struct drm_device *dev) |
2292 | { |
2418 | { |
2293 | struct drm_i915_private *dev_priv = dev->dev_private; |
2419 | struct drm_i915_private *dev_priv = dev->dev_private; |
2294 | u16 rgvswctl; |
2420 | u16 rgvswctl; |
2295 | 2421 | ||
2296 | spin_lock_irq(&mchdev_lock); |
2422 | spin_lock_irq(&mchdev_lock); |
2297 | 2423 | ||
2298 | rgvswctl = I915_READ16(MEMSWCTL); |
2424 | rgvswctl = I915_READ16(MEMSWCTL); |
2299 | 2425 | ||
2300 | /* Ack interrupts, disable EFC interrupt */ |
2426 | /* Ack interrupts, disable EFC interrupt */ |
2301 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
2427 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
2302 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
2428 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
2303 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
2429 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
2304 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
2430 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
2305 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
2431 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
2306 | 2432 | ||
2307 | /* Go back to the starting frequency */ |
2433 | /* Go back to the starting frequency */ |
2308 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
2434 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
2309 | mdelay(1); |
2435 | mdelay(1); |
2310 | rgvswctl |= MEMCTL_CMD_STS; |
2436 | rgvswctl |= MEMCTL_CMD_STS; |
2311 | I915_WRITE(MEMSWCTL, rgvswctl); |
2437 | I915_WRITE(MEMSWCTL, rgvswctl); |
2312 | mdelay(1); |
2438 | mdelay(1); |
2313 | 2439 | ||
2314 | spin_unlock_irq(&mchdev_lock); |
2440 | spin_unlock_irq(&mchdev_lock); |
2315 | } |
2441 | } |
2316 | 2442 | ||
2317 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2443 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2318 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
2444 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
2319 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
2445 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
2320 | * all limits and the gpu stuck at whatever frequency it is at atm). |
2446 | * all limits and the gpu stuck at whatever frequency it is at atm). |
2321 | */ |
2447 | */ |
2322 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
2448 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
2323 | { |
2449 | { |
2324 | u32 limits; |
2450 | u32 limits; |
2325 | 2451 | ||
2326 | limits = 0; |
2452 | limits = 0; |
2327 | 2453 | ||
2328 | if (*val >= dev_priv->rps.max_delay) |
2454 | if (*val >= dev_priv->rps.max_delay) |
2329 | *val = dev_priv->rps.max_delay; |
2455 | *val = dev_priv->rps.max_delay; |
2330 | limits |= dev_priv->rps.max_delay << 24; |
2456 | limits |= dev_priv->rps.max_delay << 24; |
2331 | 2457 | ||
2332 | /* Only set the down limit when we've reached the lowest level to avoid |
2458 | /* Only set the down limit when we've reached the lowest level to avoid |
2333 | * getting more interrupts, otherwise leave this clear. This prevents a |
2459 | * getting more interrupts, otherwise leave this clear. This prevents a |
2334 | * race in the hw when coming out of rc6: There's a tiny window where |
2460 | * race in the hw when coming out of rc6: There's a tiny window where |
2335 | * the hw runs at the minimal clock before selecting the desired |
2461 | * the hw runs at the minimal clock before selecting the desired |
2336 | * frequency, if the down threshold expires in that window we will not |
2462 | * frequency, if the down threshold expires in that window we will not |
2337 | * receive a down interrupt. */ |
2463 | * receive a down interrupt. */ |
2338 | if (*val <= dev_priv->rps.min_delay) { |
2464 | if (*val <= dev_priv->rps.min_delay) { |
2339 | *val = dev_priv->rps.min_delay; |
2465 | *val = dev_priv->rps.min_delay; |
2340 | limits |= dev_priv->rps.min_delay << 16; |
2466 | limits |= dev_priv->rps.min_delay << 16; |
2341 | } |
2467 | } |
2342 | 2468 | ||
2343 | return limits; |
2469 | return limits; |
2344 | } |
2470 | } |
2345 | 2471 | ||
2346 | void gen6_set_rps(struct drm_device *dev, u8 val) |
2472 | void gen6_set_rps(struct drm_device *dev, u8 val) |
2347 | { |
2473 | { |
2348 | struct drm_i915_private *dev_priv = dev->dev_private; |
2474 | struct drm_i915_private *dev_priv = dev->dev_private; |
2349 | u32 limits = gen6_rps_limits(dev_priv, &val); |
2475 | u32 limits = gen6_rps_limits(dev_priv, &val); |
2350 | 2476 | ||
2351 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2477 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2352 | WARN_ON(val > dev_priv->rps.max_delay); |
2478 | WARN_ON(val > dev_priv->rps.max_delay); |
2353 | WARN_ON(val < dev_priv->rps.min_delay); |
2479 | WARN_ON(val < dev_priv->rps.min_delay); |
2354 | 2480 | ||
2355 | if (val == dev_priv->rps.cur_delay) |
2481 | if (val == dev_priv->rps.cur_delay) |
2356 | return; |
2482 | return; |
2357 | 2483 | ||
2358 | I915_WRITE(GEN6_RPNSWREQ, |
2484 | I915_WRITE(GEN6_RPNSWREQ, |
2359 | GEN6_FREQUENCY(val) | |
2485 | GEN6_FREQUENCY(val) | |
2360 | GEN6_OFFSET(0) | |
2486 | GEN6_OFFSET(0) | |
2361 | GEN6_AGGRESSIVE_TURBO); |
2487 | GEN6_AGGRESSIVE_TURBO); |
2362 | 2488 | ||
2363 | /* Make sure we continue to get interrupts |
2489 | /* Make sure we continue to get interrupts |
2364 | * until we hit the minimum or maximum frequencies. |
2490 | * until we hit the minimum or maximum frequencies. |
2365 | */ |
2491 | */ |
2366 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
2492 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
2367 | 2493 | ||
2368 | POSTING_READ(GEN6_RPNSWREQ); |
2494 | POSTING_READ(GEN6_RPNSWREQ); |
2369 | 2495 | ||
2370 | dev_priv->rps.cur_delay = val; |
2496 | dev_priv->rps.cur_delay = val; |
2371 | 2497 | ||
2372 | trace_intel_gpu_freq_change(val * 50); |
2498 | trace_intel_gpu_freq_change(val * 50); |
2373 | } |
2499 | } |
2374 | 2500 | ||
2375 | static void gen6_disable_rps(struct drm_device *dev) |
2501 | static void gen6_disable_rps(struct drm_device *dev) |
2376 | { |
2502 | { |
2377 | struct drm_i915_private *dev_priv = dev->dev_private; |
2503 | struct drm_i915_private *dev_priv = dev->dev_private; |
2378 | 2504 | ||
2379 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2505 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2380 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2506 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2381 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
2507 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
2382 | I915_WRITE(GEN6_PMIER, 0); |
2508 | I915_WRITE(GEN6_PMIER, 0); |
2383 | /* Complete PM interrupt masking here doesn't race with the rps work |
2509 | /* Complete PM interrupt masking here doesn't race with the rps work |
2384 | * item again unmasking PM interrupts because that is using a different |
2510 | * item again unmasking PM interrupts because that is using a different |
2385 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
2511 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
2386 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
2512 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
2387 | 2513 | ||
2388 | spin_lock_irq(&dev_priv->rps.lock); |
2514 | spin_lock_irq(&dev_priv->rps.lock); |
2389 | dev_priv->rps.pm_iir = 0; |
2515 | dev_priv->rps.pm_iir = 0; |
2390 | spin_unlock_irq(&dev_priv->rps.lock); |
2516 | spin_unlock_irq(&dev_priv->rps.lock); |
2391 | 2517 | ||
2392 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
2518 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
2393 | } |
2519 | } |
2394 | 2520 | ||
2395 | int intel_enable_rc6(const struct drm_device *dev) |
2521 | int intel_enable_rc6(const struct drm_device *dev) |
2396 | { |
2522 | { |
2397 | /* Respect the kernel parameter if it is set */ |
2523 | /* Respect the kernel parameter if it is set */ |
2398 | if (i915_enable_rc6 >= 0) |
2524 | if (i915_enable_rc6 >= 0) |
2399 | return i915_enable_rc6; |
2525 | return i915_enable_rc6; |
2400 | 2526 | ||
2401 | /* Disable RC6 on Ironlake */ |
2527 | /* Disable RC6 on Ironlake */ |
2402 | if (INTEL_INFO(dev)->gen == 5) |
2528 | if (INTEL_INFO(dev)->gen == 5) |
2403 | return 0; |
2529 | return 0; |
2404 | 2530 | ||
2405 | if (IS_HASWELL(dev)) { |
2531 | if (IS_HASWELL(dev)) { |
2406 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
2532 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
2407 | return INTEL_RC6_ENABLE; |
2533 | return INTEL_RC6_ENABLE; |
2408 | } |
2534 | } |
2409 | 2535 | ||
2410 | /* snb/ivb have more than one rc6 state. */ |
2536 | /* snb/ivb have more than one rc6 state. */ |
2411 | if (INTEL_INFO(dev)->gen == 6) { |
2537 | if (INTEL_INFO(dev)->gen == 6) { |
2412 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
2538 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
2413 | return INTEL_RC6_ENABLE; |
2539 | return INTEL_RC6_ENABLE; |
2414 | } |
2540 | } |
2415 | 2541 | ||
2416 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
2542 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
2417 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
2543 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
2418 | } |
2544 | } |
2419 | 2545 | ||
2420 | static void gen6_enable_rps(struct drm_device *dev) |
2546 | static void gen6_enable_rps(struct drm_device *dev) |
2421 | { |
2547 | { |
2422 | struct drm_i915_private *dev_priv = dev->dev_private; |
2548 | struct drm_i915_private *dev_priv = dev->dev_private; |
2423 | struct intel_ring_buffer *ring; |
2549 | struct intel_ring_buffer *ring; |
2424 | u32 rp_state_cap; |
2550 | u32 rp_state_cap; |
2425 | u32 gt_perf_status; |
2551 | u32 gt_perf_status; |
2426 | u32 pcu_mbox, rc6_mask = 0; |
2552 | u32 rc6vids, pcu_mbox, rc6_mask = 0; |
2427 | u32 gtfifodbg; |
2553 | u32 gtfifodbg; |
2428 | int rc6_mode; |
2554 | int rc6_mode; |
2429 | int i; |
2555 | int i, ret; |
2430 | 2556 | ||
2431 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2557 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2432 | 2558 | ||
2433 | /* Here begins a magic sequence of register writes to enable |
2559 | /* Here begins a magic sequence of register writes to enable |
2434 | * auto-downclocking. |
2560 | * auto-downclocking. |
2435 | * |
2561 | * |
2436 | * Perhaps there might be some value in exposing these to |
2562 | * Perhaps there might be some value in exposing these to |
2437 | * userspace... |
2563 | * userspace... |
2438 | */ |
2564 | */ |
2439 | I915_WRITE(GEN6_RC_STATE, 0); |
2565 | I915_WRITE(GEN6_RC_STATE, 0); |
2440 | 2566 | ||
2441 | /* Clear the DBG now so we don't confuse earlier errors */ |
2567 | /* Clear the DBG now so we don't confuse earlier errors */ |
2442 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
2568 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
2443 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
2569 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
2444 | I915_WRITE(GTFIFODBG, gtfifodbg); |
2570 | I915_WRITE(GTFIFODBG, gtfifodbg); |
2445 | } |
2571 | } |
2446 | 2572 | ||
2447 | gen6_gt_force_wake_get(dev_priv); |
2573 | gen6_gt_force_wake_get(dev_priv); |
2448 | 2574 | ||
2449 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
2575 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
2450 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
2576 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
2451 | 2577 | ||
2452 | /* In units of 100MHz */ |
2578 | /* In units of 100MHz */ |
2453 | dev_priv->rps.max_delay = rp_state_cap & 0xff; |
2579 | dev_priv->rps.max_delay = rp_state_cap & 0xff; |
2454 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
2580 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
2455 | dev_priv->rps.cur_delay = 0; |
2581 | dev_priv->rps.cur_delay = 0; |
2456 | 2582 | ||
2457 | /* disable the counters and set deterministic thresholds */ |
2583 | /* disable the counters and set deterministic thresholds */ |
2458 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2584 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2459 | 2585 | ||
2460 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
2586 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
2461 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
2587 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
2462 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
2588 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
2463 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
2589 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
2464 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
2590 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
2465 | 2591 | ||
2466 | for_each_ring(ring, dev_priv, i) |
2592 | for_each_ring(ring, dev_priv, i) |
2467 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
2593 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
2468 | 2594 | ||
2469 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2595 | I915_WRITE(GEN6_RC_SLEEP, 0); |
2470 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2596 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
2471 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2597 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
2472 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
2598 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
2473 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2599 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2474 | 2600 | ||
2475 | /* Check if we are enabling RC6 */ |
2601 | /* Check if we are enabling RC6 */ |
2476 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
2602 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
2477 | if (rc6_mode & INTEL_RC6_ENABLE) |
2603 | if (rc6_mode & INTEL_RC6_ENABLE) |
2478 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
2604 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
2479 | 2605 | ||
2480 | /* We don't use those on Haswell */ |
2606 | /* We don't use those on Haswell */ |
2481 | if (!IS_HASWELL(dev)) { |
2607 | if (!IS_HASWELL(dev)) { |
2482 | if (rc6_mode & INTEL_RC6p_ENABLE) |
2608 | if (rc6_mode & INTEL_RC6p_ENABLE) |
2483 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
2609 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
2484 | 2610 | ||
2485 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
2611 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
2486 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
2612 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
2487 | } |
2613 | } |
2488 | 2614 | ||
2489 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
2615 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
2490 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
2616 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
2491 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
2617 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
2492 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
2618 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
2493 | 2619 | ||
2494 | I915_WRITE(GEN6_RC_CONTROL, |
2620 | I915_WRITE(GEN6_RC_CONTROL, |
2495 | rc6_mask | |
2621 | rc6_mask | |
2496 | GEN6_RC_CTL_EI_MODE(1) | |
2622 | GEN6_RC_CTL_EI_MODE(1) | |
2497 | GEN6_RC_CTL_HW_ENABLE); |
2623 | GEN6_RC_CTL_HW_ENABLE); |
2498 | 2624 | ||
2499 | I915_WRITE(GEN6_RPNSWREQ, |
2625 | I915_WRITE(GEN6_RPNSWREQ, |
2500 | GEN6_FREQUENCY(10) | |
2626 | GEN6_FREQUENCY(10) | |
2501 | GEN6_OFFSET(0) | |
2627 | GEN6_OFFSET(0) | |
2502 | GEN6_AGGRESSIVE_TURBO); |
2628 | GEN6_AGGRESSIVE_TURBO); |
2503 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
2629 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
2504 | GEN6_FREQUENCY(12)); |
2630 | GEN6_FREQUENCY(12)); |
2505 | 2631 | ||
2506 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2632 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2507 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
2633 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
2508 | dev_priv->rps.max_delay << 24 | |
2634 | dev_priv->rps.max_delay << 24 | |
2509 | dev_priv->rps.min_delay << 16); |
2635 | dev_priv->rps.min_delay << 16); |
2510 | 2636 | ||
2511 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
2637 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
2512 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
2638 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
2513 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
2639 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
2514 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
2640 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
2515 | 2641 | ||
2516 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2642 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2517 | I915_WRITE(GEN6_RP_CONTROL, |
2643 | I915_WRITE(GEN6_RP_CONTROL, |
2518 | GEN6_RP_MEDIA_TURBO | |
2644 | GEN6_RP_MEDIA_TURBO | |
2519 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
2645 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
2520 | GEN6_RP_MEDIA_IS_GFX | |
2646 | GEN6_RP_MEDIA_IS_GFX | |
2521 | GEN6_RP_ENABLE | |
2647 | GEN6_RP_ENABLE | |
2522 | GEN6_RP_UP_BUSY_AVG | |
2648 | GEN6_RP_UP_BUSY_AVG | |
2523 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
2649 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
2524 | - | ||
2525 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
- | |
2526 | 500)) |
- | |
2527 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
- | |
2528 | - | ||
2529 | I915_WRITE(GEN6_PCODE_DATA, 0); |
- | |
2530 | I915_WRITE(GEN6_PCODE_MAILBOX, |
- | |
2531 | GEN6_PCODE_READY | |
2650 | |
2532 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
- | |
2533 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
2651 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
2534 | 500)) |
- | |
2535 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
- | |
2536 | - | ||
2537 | /* Check for overclock support */ |
- | |
2538 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
2652 | if (!ret) { |
2539 | 500)) |
- | |
2540 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
2653 | pcu_mbox = 0; |
2541 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); |
- | |
2542 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); |
- | |
2543 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
- | |
2544 | 500)) |
- | |
2545 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
2654 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
2546 | if (pcu_mbox & (1<<31)) { /* OC supported */ |
2655 | if (ret && pcu_mbox & (1<<31)) { /* OC supported */ |
2547 | dev_priv->rps.max_delay = pcu_mbox & 0xff; |
2656 | dev_priv->rps.max_delay = pcu_mbox & 0xff; |
2548 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
2657 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
2549 | } |
2658 | } |
- | 2659 | } else { |
|
- | 2660 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
|
- | 2661 | } |
|
2550 | 2662 | ||
2551 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
2663 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
2552 | 2664 | ||
2553 | /* requires MSI enabled */ |
2665 | /* requires MSI enabled */ |
2554 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
2666 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
2555 | spin_lock_irq(&dev_priv->rps.lock); |
2667 | spin_lock_irq(&dev_priv->rps.lock); |
2556 | WARN_ON(dev_priv->rps.pm_iir != 0); |
2668 | WARN_ON(dev_priv->rps.pm_iir != 0); |
2557 | I915_WRITE(GEN6_PMIMR, 0); |
2669 | I915_WRITE(GEN6_PMIMR, 0); |
2558 | spin_unlock_irq(&dev_priv->rps.lock); |
2670 | spin_unlock_irq(&dev_priv->rps.lock); |
2559 | /* enable all PM interrupts */ |
2671 | /* enable all PM interrupts */ |
2560 | I915_WRITE(GEN6_PMINTRMSK, 0); |
2672 | I915_WRITE(GEN6_PMINTRMSK, 0); |
- | 2673 | ||
- | 2674 | rc6vids = 0; |
|
- | 2675 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
|
- | 2676 | if (IS_GEN6(dev) && ret) { |
|
- | 2677 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
|
- | 2678 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
|
- | 2679 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
|
- | 2680 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
|
- | 2681 | rc6vids &= 0xffff00; |
|
- | 2682 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
|
- | 2683 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
|
- | 2684 | if (ret) |
|
- | 2685 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
|
- | 2686 | } |
|
2561 | 2687 | ||
2562 | gen6_gt_force_wake_put(dev_priv); |
2688 | gen6_gt_force_wake_put(dev_priv); |
2563 | } |
2689 | } |
2564 | 2690 | ||
2565 | #if 0 |
2691 | #if 0 |
2566 | static void gen6_update_ring_freq(struct drm_device *dev) |
2692 | static void gen6_update_ring_freq(struct drm_device *dev) |
2567 | { |
2693 | { |
2568 | struct drm_i915_private *dev_priv = dev->dev_private; |
2694 | struct drm_i915_private *dev_priv = dev->dev_private; |
2569 | int min_freq = 15; |
2695 | int min_freq = 15; |
- | 2696 | int gpu_freq; |
|
2570 | int gpu_freq, ia_freq, max_ia_freq; |
2697 | unsigned int ia_freq, max_ia_freq; |
2571 | int scaling_factor = 180; |
2698 | int scaling_factor = 180; |
2572 | 2699 | ||
2573 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2700 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
2574 | 2701 | ||
2575 | max_ia_freq = cpufreq_quick_get_max(0); |
2702 | max_ia_freq = cpufreq_quick_get_max(0); |
2576 | /* |
2703 | /* |
2577 | * Default to measured freq if none found, PCU will ensure we don't go |
2704 | * Default to measured freq if none found, PCU will ensure we don't go |
2578 | * over |
2705 | * over |
2579 | */ |
2706 | */ |
2580 | if (!max_ia_freq) |
2707 | if (!max_ia_freq) |
2581 | max_ia_freq = tsc_khz; |
2708 | max_ia_freq = tsc_khz; |
2582 | 2709 | ||
2583 | /* Convert from kHz to MHz */ |
2710 | /* Convert from kHz to MHz */ |
2584 | max_ia_freq /= 1000; |
2711 | max_ia_freq /= 1000; |
2585 | 2712 | ||
2586 | /* |
2713 | /* |
2587 | * For each potential GPU frequency, load a ring frequency we'd like |
2714 | * For each potential GPU frequency, load a ring frequency we'd like |
2588 | * to use for memory access. We do this by specifying the IA frequency |
2715 | * to use for memory access. We do this by specifying the IA frequency |
2589 | * the PCU should use as a reference to determine the ring frequency. |
2716 | * the PCU should use as a reference to determine the ring frequency. |
2590 | */ |
2717 | */ |
2591 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
2718 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
2592 | gpu_freq--) { |
2719 | gpu_freq--) { |
2593 | int diff = dev_priv->rps.max_delay - gpu_freq; |
2720 | int diff = dev_priv->rps.max_delay - gpu_freq; |
2594 | 2721 | ||
2595 | /* |
2722 | /* |
2596 | * For GPU frequencies less than 750MHz, just use the lowest |
2723 | * For GPU frequencies less than 750MHz, just use the lowest |
2597 | * ring freq. |
2724 | * ring freq. |
2598 | */ |
2725 | */ |
2599 | if (gpu_freq < min_freq) |
2726 | if (gpu_freq < min_freq) |
2600 | ia_freq = 800; |
2727 | ia_freq = 800; |
2601 | else |
2728 | else |
2602 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
2729 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
2603 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
2730 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
- | 2731 | ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; |
|
2604 | 2732 | ||
2605 | I915_WRITE(GEN6_PCODE_DATA, |
- | |
2606 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | |
- | |
2607 | gpu_freq); |
- | |
2608 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | |
2733 | sandybridge_pcode_write(dev_priv, |
2609 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
- | |
2610 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & |
- | |
2611 | GEN6_PCODE_READY) == 0, 10)) { |
- | |
2612 | DRM_ERROR("pcode write of freq table timed out\n"); |
2734 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
2613 | continue; |
- | |
2614 | } |
2735 | ia_freq | gpu_freq); |
2615 | } |
2736 | } |
2616 | } |
2737 | } |
2617 | #endif |
2738 | #endif |
2618 | 2739 | ||
2619 | void ironlake_teardown_rc6(struct drm_device *dev) |
2740 | void ironlake_teardown_rc6(struct drm_device *dev) |
2620 | { |
2741 | { |
2621 | struct drm_i915_private *dev_priv = dev->dev_private; |
2742 | struct drm_i915_private *dev_priv = dev->dev_private; |
2622 | 2743 | ||
2623 | if (dev_priv->renderctx) { |
2744 | if (dev_priv->ips.renderctx) { |
2624 | i915_gem_object_unpin(dev_priv->renderctx); |
2745 | i915_gem_object_unpin(dev_priv->ips.renderctx); |
2625 | drm_gem_object_unreference(&dev_priv->renderctx->base); |
2746 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
2626 | dev_priv->renderctx = NULL; |
2747 | dev_priv->ips.renderctx = NULL; |
2627 | } |
2748 | } |
2628 | 2749 | ||
2629 | if (dev_priv->pwrctx) { |
2750 | if (dev_priv->ips.pwrctx) { |
2630 | i915_gem_object_unpin(dev_priv->pwrctx); |
2751 | i915_gem_object_unpin(dev_priv->ips.pwrctx); |
2631 | drm_gem_object_unreference(&dev_priv->pwrctx->base); |
2752 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
2632 | dev_priv->pwrctx = NULL; |
2753 | dev_priv->ips.pwrctx = NULL; |
2633 | } |
2754 | } |
2634 | } |
2755 | } |
2635 | 2756 | ||
2636 | static void ironlake_disable_rc6(struct drm_device *dev) |
2757 | static void ironlake_disable_rc6(struct drm_device *dev) |
2637 | { |
2758 | { |
2638 | struct drm_i915_private *dev_priv = dev->dev_private; |
2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
2639 | 2760 | ||
2640 | if (I915_READ(PWRCTXA)) { |
2761 | if (I915_READ(PWRCTXA)) { |
2641 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
2762 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
2642 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
2763 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
2643 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
2764 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
2644 | 50); |
2765 | 50); |
2645 | 2766 | ||
2646 | I915_WRITE(PWRCTXA, 0); |
2767 | I915_WRITE(PWRCTXA, 0); |
2647 | POSTING_READ(PWRCTXA); |
2768 | POSTING_READ(PWRCTXA); |
2648 | 2769 | ||
2649 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2770 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2650 | POSTING_READ(RSTDBYCTL); |
2771 | POSTING_READ(RSTDBYCTL); |
2651 | } |
2772 | } |
2652 | } |
2773 | } |
2653 | 2774 | ||
2654 | static int ironlake_setup_rc6(struct drm_device *dev) |
2775 | static int ironlake_setup_rc6(struct drm_device *dev) |
2655 | { |
2776 | { |
2656 | struct drm_i915_private *dev_priv = dev->dev_private; |
2777 | struct drm_i915_private *dev_priv = dev->dev_private; |
2657 | 2778 | ||
2658 | if (dev_priv->renderctx == NULL) |
2779 | if (dev_priv->ips.renderctx == NULL) |
2659 | dev_priv->renderctx = intel_alloc_context_page(dev); |
2780 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
2660 | if (!dev_priv->renderctx) |
2781 | if (!dev_priv->ips.renderctx) |
2661 | return -ENOMEM; |
2782 | return -ENOMEM; |
2662 | 2783 | ||
2663 | if (dev_priv->pwrctx == NULL) |
2784 | if (dev_priv->ips.pwrctx == NULL) |
2664 | dev_priv->pwrctx = intel_alloc_context_page(dev); |
2785 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
2665 | if (!dev_priv->pwrctx) { |
2786 | if (!dev_priv->ips.pwrctx) { |
2666 | ironlake_teardown_rc6(dev); |
2787 | ironlake_teardown_rc6(dev); |
2667 | return -ENOMEM; |
2788 | return -ENOMEM; |
2668 | } |
2789 | } |
2669 | 2790 | ||
2670 | return 0; |
2791 | return 0; |
2671 | } |
2792 | } |
2672 | 2793 | ||
2673 | static void ironlake_enable_rc6(struct drm_device *dev) |
2794 | static void ironlake_enable_rc6(struct drm_device *dev) |
2674 | { |
2795 | { |
2675 | struct drm_i915_private *dev_priv = dev->dev_private; |
2796 | struct drm_i915_private *dev_priv = dev->dev_private; |
2676 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
2797 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | 2798 | bool was_interruptible; |
|
2677 | int ret; |
2799 | int ret; |
2678 | 2800 | ||
2679 | /* rc6 disabled by default due to repeated reports of hanging during |
2801 | /* rc6 disabled by default due to repeated reports of hanging during |
2680 | * boot and resume. |
2802 | * boot and resume. |
2681 | */ |
2803 | */ |
2682 | if (!intel_enable_rc6(dev)) |
2804 | if (!intel_enable_rc6(dev)) |
2683 | return; |
2805 | return; |
2684 | 2806 | ||
2685 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2807 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2686 | 2808 | ||
2687 | ret = ironlake_setup_rc6(dev); |
2809 | ret = ironlake_setup_rc6(dev); |
2688 | if (ret) |
2810 | if (ret) |
2689 | return; |
2811 | return; |
- | 2812 | ||
- | 2813 | was_interruptible = dev_priv->mm.interruptible; |
|
- | 2814 | dev_priv->mm.interruptible = false; |
|
2690 | 2815 | ||
2691 | /* |
2816 | /* |
2692 | * GPU can automatically power down the render unit if given a page |
2817 | * GPU can automatically power down the render unit if given a page |
2693 | * to save state. |
2818 | * to save state. |
2694 | */ |
2819 | */ |
2695 | ret = intel_ring_begin(ring, 6); |
2820 | ret = intel_ring_begin(ring, 6); |
2696 | if (ret) { |
2821 | if (ret) { |
2697 | ironlake_teardown_rc6(dev); |
2822 | ironlake_teardown_rc6(dev); |
- | 2823 | dev_priv->mm.interruptible = was_interruptible; |
|
2698 | return; |
2824 | return; |
2699 | } |
2825 | } |
2700 | 2826 | ||
2701 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
2827 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
2702 | intel_ring_emit(ring, MI_SET_CONTEXT); |
2828 | intel_ring_emit(ring, MI_SET_CONTEXT); |
2703 | intel_ring_emit(ring, dev_priv->renderctx->gtt_offset | |
2829 | intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | |
2704 | MI_MM_SPACE_GTT | |
2830 | MI_MM_SPACE_GTT | |
2705 | MI_SAVE_EXT_STATE_EN | |
2831 | MI_SAVE_EXT_STATE_EN | |
2706 | MI_RESTORE_EXT_STATE_EN | |
2832 | MI_RESTORE_EXT_STATE_EN | |
2707 | MI_RESTORE_INHIBIT); |
2833 | MI_RESTORE_INHIBIT); |
2708 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
2834 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
2709 | intel_ring_emit(ring, MI_NOOP); |
2835 | intel_ring_emit(ring, MI_NOOP); |
2710 | intel_ring_emit(ring, MI_FLUSH); |
2836 | intel_ring_emit(ring, MI_FLUSH); |
2711 | intel_ring_advance(ring); |
2837 | intel_ring_advance(ring); |
2712 | 2838 | ||
2713 | /* |
2839 | /* |
2714 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
2840 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
2715 | * does an implicit flush, combined with MI_FLUSH above, it should be |
2841 | * does an implicit flush, combined with MI_FLUSH above, it should be |
2716 | * safe to assume that renderctx is valid |
2842 | * safe to assume that renderctx is valid |
2717 | */ |
2843 | */ |
2718 | ret = intel_wait_ring_idle(ring); |
2844 | ret = intel_ring_idle(ring); |
- | 2845 | dev_priv->mm.interruptible = was_interruptible; |
|
2719 | if (ret) { |
2846 | if (ret) { |
2720 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
2847 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
2721 | ironlake_teardown_rc6(dev); |
2848 | ironlake_teardown_rc6(dev); |
2722 | return; |
2849 | return; |
2723 | } |
2850 | } |
2724 | 2851 | ||
2725 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
2852 | I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); |
2726 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2853 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2727 | } |
2854 | } |
2728 | 2855 | ||
2729 | static unsigned long intel_pxfreq(u32 vidfreq) |
2856 | static unsigned long intel_pxfreq(u32 vidfreq) |
2730 | { |
2857 | { |
2731 | unsigned long freq; |
2858 | unsigned long freq; |
2732 | int div = (vidfreq & 0x3f0000) >> 16; |
2859 | int div = (vidfreq & 0x3f0000) >> 16; |
2733 | int post = (vidfreq & 0x3000) >> 12; |
2860 | int post = (vidfreq & 0x3000) >> 12; |
2734 | int pre = (vidfreq & 0x7); |
2861 | int pre = (vidfreq & 0x7); |
2735 | 2862 | ||
2736 | if (!pre) |
2863 | if (!pre) |
2737 | return 0; |
2864 | return 0; |
2738 | 2865 | ||
2739 | freq = ((div * 133333) / ((1< |
2866 | freq = ((div * 133333) / ((1< |
2740 | 2867 | ||
2741 | return freq; |
2868 | return freq; |
2742 | } |
2869 | } |
2743 | 2870 | ||
2744 | static const struct cparams { |
2871 | static const struct cparams { |
2745 | u16 i; |
2872 | u16 i; |
2746 | u16 t; |
2873 | u16 t; |
2747 | u16 m; |
2874 | u16 m; |
2748 | u16 c; |
2875 | u16 c; |
2749 | } cparams[] = { |
2876 | } cparams[] = { |
2750 | { 1, 1333, 301, 28664 }, |
2877 | { 1, 1333, 301, 28664 }, |
2751 | { 1, 1066, 294, 24460 }, |
2878 | { 1, 1066, 294, 24460 }, |
2752 | { 1, 800, 294, 25192 }, |
2879 | { 1, 800, 294, 25192 }, |
2753 | { 0, 1333, 276, 27605 }, |
2880 | { 0, 1333, 276, 27605 }, |
2754 | { 0, 1066, 276, 27605 }, |
2881 | { 0, 1066, 276, 27605 }, |
2755 | { 0, 800, 231, 23784 }, |
2882 | { 0, 800, 231, 23784 }, |
2756 | }; |
2883 | }; |
2757 | 2884 | ||
2758 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
2885 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
2759 | { |
2886 | { |
2760 | u64 total_count, diff, ret; |
2887 | u64 total_count, diff, ret; |
2761 | u32 count1, count2, count3, m = 0, c = 0; |
2888 | u32 count1, count2, count3, m = 0, c = 0; |
2762 | unsigned long now = jiffies_to_msecs(GetTimerTicks()), diff1; |
2889 | unsigned long now = jiffies_to_msecs(GetTimerTicks()), diff1; |
2763 | int i; |
2890 | int i; |
2764 | 2891 | ||
2765 | assert_spin_locked(&mchdev_lock); |
2892 | assert_spin_locked(&mchdev_lock); |
2766 | 2893 | ||
2767 | diff1 = now - dev_priv->ips.last_time1; |
2894 | diff1 = now - dev_priv->ips.last_time1; |
2768 | 2895 | ||
2769 | /* Prevent division-by-zero if we are asking too fast. |
2896 | /* Prevent division-by-zero if we are asking too fast. |
2770 | * Also, we don't get interesting results if we are polling |
2897 | * Also, we don't get interesting results if we are polling |
2771 | * faster than once in 10ms, so just return the saved value |
2898 | * faster than once in 10ms, so just return the saved value |
2772 | * in such cases. |
2899 | * in such cases. |
2773 | */ |
2900 | */ |
2774 | if (diff1 <= 10) |
2901 | if (diff1 <= 10) |
2775 | return dev_priv->ips.chipset_power; |
2902 | return dev_priv->ips.chipset_power; |
2776 | 2903 | ||
2777 | count1 = I915_READ(DMIEC); |
2904 | count1 = I915_READ(DMIEC); |
2778 | count2 = I915_READ(DDREC); |
2905 | count2 = I915_READ(DDREC); |
2779 | count3 = I915_READ(CSIEC); |
2906 | count3 = I915_READ(CSIEC); |
2780 | 2907 | ||
2781 | total_count = count1 + count2 + count3; |
2908 | total_count = count1 + count2 + count3; |
2782 | 2909 | ||
2783 | /* FIXME: handle per-counter overflow */ |
2910 | /* FIXME: handle per-counter overflow */ |
2784 | if (total_count < dev_priv->ips.last_count1) { |
2911 | if (total_count < dev_priv->ips.last_count1) { |
2785 | diff = ~0UL - dev_priv->ips.last_count1; |
2912 | diff = ~0UL - dev_priv->ips.last_count1; |
2786 | diff += total_count; |
2913 | diff += total_count; |
2787 | } else { |
2914 | } else { |
2788 | diff = total_count - dev_priv->ips.last_count1; |
2915 | diff = total_count - dev_priv->ips.last_count1; |
2789 | } |
2916 | } |
2790 | 2917 | ||
2791 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
2918 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
2792 | if (cparams[i].i == dev_priv->ips.c_m && |
2919 | if (cparams[i].i == dev_priv->ips.c_m && |
2793 | cparams[i].t == dev_priv->ips.r_t) { |
2920 | cparams[i].t == dev_priv->ips.r_t) { |
2794 | m = cparams[i].m; |
2921 | m = cparams[i].m; |
2795 | c = cparams[i].c; |
2922 | c = cparams[i].c; |
2796 | break; |
2923 | break; |
2797 | } |
2924 | } |
2798 | } |
2925 | } |
2799 | 2926 | ||
2800 | diff = div_u64(diff, diff1); |
2927 | diff = div_u64(diff, diff1); |
2801 | ret = ((m * diff) + c); |
2928 | ret = ((m * diff) + c); |
2802 | ret = div_u64(ret, 10); |
2929 | ret = div_u64(ret, 10); |
2803 | 2930 | ||
2804 | dev_priv->ips.last_count1 = total_count; |
2931 | dev_priv->ips.last_count1 = total_count; |
2805 | dev_priv->ips.last_time1 = now; |
2932 | dev_priv->ips.last_time1 = now; |
2806 | 2933 | ||
2807 | dev_priv->ips.chipset_power = ret; |
2934 | dev_priv->ips.chipset_power = ret; |
2808 | 2935 | ||
2809 | return ret; |
2936 | return ret; |
2810 | } |
2937 | } |
2811 | 2938 | ||
2812 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
2939 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
2813 | { |
2940 | { |
2814 | unsigned long val; |
2941 | unsigned long val; |
2815 | 2942 | ||
2816 | if (dev_priv->info->gen != 5) |
2943 | if (dev_priv->info->gen != 5) |
2817 | return 0; |
2944 | return 0; |
2818 | 2945 | ||
2819 | spin_lock_irq(&mchdev_lock); |
2946 | spin_lock_irq(&mchdev_lock); |
2820 | 2947 | ||
2821 | val = __i915_chipset_val(dev_priv); |
2948 | val = __i915_chipset_val(dev_priv); |
2822 | 2949 | ||
2823 | spin_unlock_irq(&mchdev_lock); |
2950 | spin_unlock_irq(&mchdev_lock); |
2824 | 2951 | ||
2825 | return val; |
2952 | return val; |
2826 | } |
2953 | } |
2827 | 2954 | ||
2828 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
2955 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
2829 | { |
2956 | { |
2830 | unsigned long m, x, b; |
2957 | unsigned long m, x, b; |
2831 | u32 tsfs; |
2958 | u32 tsfs; |
2832 | 2959 | ||
2833 | tsfs = I915_READ(TSFS); |
2960 | tsfs = I915_READ(TSFS); |
2834 | 2961 | ||
2835 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
2962 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
2836 | x = I915_READ8(TR1); |
2963 | x = I915_READ8(TR1); |
2837 | 2964 | ||
2838 | b = tsfs & TSFS_INTR_MASK; |
2965 | b = tsfs & TSFS_INTR_MASK; |
2839 | 2966 | ||
2840 | return ((m * x) / 127) - b; |
2967 | return ((m * x) / 127) - b; |
2841 | } |
2968 | } |
2842 | 2969 | ||
2843 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
2970 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
2844 | { |
2971 | { |
2845 | static const struct v_table { |
2972 | static const struct v_table { |
2846 | u16 vd; /* in .1 mil */ |
2973 | u16 vd; /* in .1 mil */ |
2847 | u16 vm; /* in .1 mil */ |
2974 | u16 vm; /* in .1 mil */ |
2848 | } v_table[] = { |
2975 | } v_table[] = { |
2849 | { 0, 0, }, |
2976 | { 0, 0, }, |
2850 | { 375, 0, }, |
2977 | { 375, 0, }, |
2851 | { 500, 0, }, |
2978 | { 500, 0, }, |
2852 | { 625, 0, }, |
2979 | { 625, 0, }, |
2853 | { 750, 0, }, |
2980 | { 750, 0, }, |
2854 | { 875, 0, }, |
2981 | { 875, 0, }, |
2855 | { 1000, 0, }, |
2982 | { 1000, 0, }, |
2856 | { 1125, 0, }, |
2983 | { 1125, 0, }, |
2857 | { 4125, 3000, }, |
2984 | { 4125, 3000, }, |
2858 | { 4125, 3000, }, |
2985 | { 4125, 3000, }, |
2859 | { 4125, 3000, }, |
2986 | { 4125, 3000, }, |
2860 | { 4125, 3000, }, |
2987 | { 4125, 3000, }, |
2861 | { 4125, 3000, }, |
2988 | { 4125, 3000, }, |
2862 | { 4125, 3000, }, |
2989 | { 4125, 3000, }, |
2863 | { 4125, 3000, }, |
2990 | { 4125, 3000, }, |
2864 | { 4125, 3000, }, |
2991 | { 4125, 3000, }, |
2865 | { 4125, 3000, }, |
2992 | { 4125, 3000, }, |
2866 | { 4125, 3000, }, |
2993 | { 4125, 3000, }, |
2867 | { 4125, 3000, }, |
2994 | { 4125, 3000, }, |
2868 | { 4125, 3000, }, |
2995 | { 4125, 3000, }, |
2869 | { 4125, 3000, }, |
2996 | { 4125, 3000, }, |
2870 | { 4125, 3000, }, |
2997 | { 4125, 3000, }, |
2871 | { 4125, 3000, }, |
2998 | { 4125, 3000, }, |
2872 | { 4125, 3000, }, |
2999 | { 4125, 3000, }, |
2873 | { 4125, 3000, }, |
3000 | { 4125, 3000, }, |
2874 | { 4125, 3000, }, |
3001 | { 4125, 3000, }, |
2875 | { 4125, 3000, }, |
3002 | { 4125, 3000, }, |
2876 | { 4125, 3000, }, |
3003 | { 4125, 3000, }, |
2877 | { 4125, 3000, }, |
3004 | { 4125, 3000, }, |
2878 | { 4125, 3000, }, |
3005 | { 4125, 3000, }, |
2879 | { 4125, 3000, }, |
3006 | { 4125, 3000, }, |
2880 | { 4125, 3000, }, |
3007 | { 4125, 3000, }, |
2881 | { 4250, 3125, }, |
3008 | { 4250, 3125, }, |
2882 | { 4375, 3250, }, |
3009 | { 4375, 3250, }, |
2883 | { 4500, 3375, }, |
3010 | { 4500, 3375, }, |
2884 | { 4625, 3500, }, |
3011 | { 4625, 3500, }, |
2885 | { 4750, 3625, }, |
3012 | { 4750, 3625, }, |
2886 | { 4875, 3750, }, |
3013 | { 4875, 3750, }, |
2887 | { 5000, 3875, }, |
3014 | { 5000, 3875, }, |
2888 | { 5125, 4000, }, |
3015 | { 5125, 4000, }, |
2889 | { 5250, 4125, }, |
3016 | { 5250, 4125, }, |
2890 | { 5375, 4250, }, |
3017 | { 5375, 4250, }, |
2891 | { 5500, 4375, }, |
3018 | { 5500, 4375, }, |
2892 | { 5625, 4500, }, |
3019 | { 5625, 4500, }, |
2893 | { 5750, 4625, }, |
3020 | { 5750, 4625, }, |
2894 | { 5875, 4750, }, |
3021 | { 5875, 4750, }, |
2895 | { 6000, 4875, }, |
3022 | { 6000, 4875, }, |
2896 | { 6125, 5000, }, |
3023 | { 6125, 5000, }, |
2897 | { 6250, 5125, }, |
3024 | { 6250, 5125, }, |
2898 | { 6375, 5250, }, |
3025 | { 6375, 5250, }, |
2899 | { 6500, 5375, }, |
3026 | { 6500, 5375, }, |
2900 | { 6625, 5500, }, |
3027 | { 6625, 5500, }, |
2901 | { 6750, 5625, }, |
3028 | { 6750, 5625, }, |
2902 | { 6875, 5750, }, |
3029 | { 6875, 5750, }, |
2903 | { 7000, 5875, }, |
3030 | { 7000, 5875, }, |
2904 | { 7125, 6000, }, |
3031 | { 7125, 6000, }, |
2905 | { 7250, 6125, }, |
3032 | { 7250, 6125, }, |
2906 | { 7375, 6250, }, |
3033 | { 7375, 6250, }, |
2907 | { 7500, 6375, }, |
3034 | { 7500, 6375, }, |
2908 | { 7625, 6500, }, |
3035 | { 7625, 6500, }, |
2909 | { 7750, 6625, }, |
3036 | { 7750, 6625, }, |
2910 | { 7875, 6750, }, |
3037 | { 7875, 6750, }, |
2911 | { 8000, 6875, }, |
3038 | { 8000, 6875, }, |
2912 | { 8125, 7000, }, |
3039 | { 8125, 7000, }, |
2913 | { 8250, 7125, }, |
3040 | { 8250, 7125, }, |
2914 | { 8375, 7250, }, |
3041 | { 8375, 7250, }, |
2915 | { 8500, 7375, }, |
3042 | { 8500, 7375, }, |
2916 | { 8625, 7500, }, |
3043 | { 8625, 7500, }, |
2917 | { 8750, 7625, }, |
3044 | { 8750, 7625, }, |
2918 | { 8875, 7750, }, |
3045 | { 8875, 7750, }, |
2919 | { 9000, 7875, }, |
3046 | { 9000, 7875, }, |
2920 | { 9125, 8000, }, |
3047 | { 9125, 8000, }, |
2921 | { 9250, 8125, }, |
3048 | { 9250, 8125, }, |
2922 | { 9375, 8250, }, |
3049 | { 9375, 8250, }, |
2923 | { 9500, 8375, }, |
3050 | { 9500, 8375, }, |
2924 | { 9625, 8500, }, |
3051 | { 9625, 8500, }, |
2925 | { 9750, 8625, }, |
3052 | { 9750, 8625, }, |
2926 | { 9875, 8750, }, |
3053 | { 9875, 8750, }, |
2927 | { 10000, 8875, }, |
3054 | { 10000, 8875, }, |
2928 | { 10125, 9000, }, |
3055 | { 10125, 9000, }, |
2929 | { 10250, 9125, }, |
3056 | { 10250, 9125, }, |
2930 | { 10375, 9250, }, |
3057 | { 10375, 9250, }, |
2931 | { 10500, 9375, }, |
3058 | { 10500, 9375, }, |
2932 | { 10625, 9500, }, |
3059 | { 10625, 9500, }, |
2933 | { 10750, 9625, }, |
3060 | { 10750, 9625, }, |
2934 | { 10875, 9750, }, |
3061 | { 10875, 9750, }, |
2935 | { 11000, 9875, }, |
3062 | { 11000, 9875, }, |
2936 | { 11125, 10000, }, |
3063 | { 11125, 10000, }, |
2937 | { 11250, 10125, }, |
3064 | { 11250, 10125, }, |
2938 | { 11375, 10250, }, |
3065 | { 11375, 10250, }, |
2939 | { 11500, 10375, }, |
3066 | { 11500, 10375, }, |
2940 | { 11625, 10500, }, |
3067 | { 11625, 10500, }, |
2941 | { 11750, 10625, }, |
3068 | { 11750, 10625, }, |
2942 | { 11875, 10750, }, |
3069 | { 11875, 10750, }, |
2943 | { 12000, 10875, }, |
3070 | { 12000, 10875, }, |
2944 | { 12125, 11000, }, |
3071 | { 12125, 11000, }, |
2945 | { 12250, 11125, }, |
3072 | { 12250, 11125, }, |
2946 | { 12375, 11250, }, |
3073 | { 12375, 11250, }, |
2947 | { 12500, 11375, }, |
3074 | { 12500, 11375, }, |
2948 | { 12625, 11500, }, |
3075 | { 12625, 11500, }, |
2949 | { 12750, 11625, }, |
3076 | { 12750, 11625, }, |
2950 | { 12875, 11750, }, |
3077 | { 12875, 11750, }, |
2951 | { 13000, 11875, }, |
3078 | { 13000, 11875, }, |
2952 | { 13125, 12000, }, |
3079 | { 13125, 12000, }, |
2953 | { 13250, 12125, }, |
3080 | { 13250, 12125, }, |
2954 | { 13375, 12250, }, |
3081 | { 13375, 12250, }, |
2955 | { 13500, 12375, }, |
3082 | { 13500, 12375, }, |
2956 | { 13625, 12500, }, |
3083 | { 13625, 12500, }, |
2957 | { 13750, 12625, }, |
3084 | { 13750, 12625, }, |
2958 | { 13875, 12750, }, |
3085 | { 13875, 12750, }, |
2959 | { 14000, 12875, }, |
3086 | { 14000, 12875, }, |
2960 | { 14125, 13000, }, |
3087 | { 14125, 13000, }, |
2961 | { 14250, 13125, }, |
3088 | { 14250, 13125, }, |
2962 | { 14375, 13250, }, |
3089 | { 14375, 13250, }, |
2963 | { 14500, 13375, }, |
3090 | { 14500, 13375, }, |
2964 | { 14625, 13500, }, |
3091 | { 14625, 13500, }, |
2965 | { 14750, 13625, }, |
3092 | { 14750, 13625, }, |
2966 | { 14875, 13750, }, |
3093 | { 14875, 13750, }, |
2967 | { 15000, 13875, }, |
3094 | { 15000, 13875, }, |
2968 | { 15125, 14000, }, |
3095 | { 15125, 14000, }, |
2969 | { 15250, 14125, }, |
3096 | { 15250, 14125, }, |
2970 | { 15375, 14250, }, |
3097 | { 15375, 14250, }, |
2971 | { 15500, 14375, }, |
3098 | { 15500, 14375, }, |
2972 | { 15625, 14500, }, |
3099 | { 15625, 14500, }, |
2973 | { 15750, 14625, }, |
3100 | { 15750, 14625, }, |
2974 | { 15875, 14750, }, |
3101 | { 15875, 14750, }, |
2975 | { 16000, 14875, }, |
3102 | { 16000, 14875, }, |
2976 | { 16125, 15000, }, |
3103 | { 16125, 15000, }, |
2977 | }; |
3104 | }; |
2978 | if (dev_priv->info->is_mobile) |
3105 | if (dev_priv->info->is_mobile) |
2979 | return v_table[pxvid].vm; |
3106 | return v_table[pxvid].vm; |
2980 | else |
3107 | else |
2981 | return v_table[pxvid].vd; |
3108 | return v_table[pxvid].vd; |
2982 | } |
3109 | } |
2983 | 3110 | ||
2984 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3111 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
2985 | { |
3112 | { |
2986 | struct timespec now, diff1; |
3113 | struct timespec now, diff1; |
2987 | u64 diff; |
3114 | u64 diff; |
2988 | unsigned long diffms; |
3115 | unsigned long diffms; |
2989 | u32 count; |
3116 | u32 count; |
2990 | 3117 | ||
2991 | assert_spin_locked(&mchdev_lock); |
3118 | assert_spin_locked(&mchdev_lock); |
2992 | 3119 | ||
2993 | getrawmonotonic(&now); |
3120 | getrawmonotonic(&now); |
2994 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
3121 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
2995 | 3122 | ||
2996 | /* Don't divide by 0 */ |
3123 | /* Don't divide by 0 */ |
2997 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
3124 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
2998 | if (!diffms) |
3125 | if (!diffms) |
2999 | return; |
3126 | return; |
3000 | 3127 | ||
3001 | count = I915_READ(GFXEC); |
3128 | count = I915_READ(GFXEC); |
3002 | 3129 | ||
3003 | if (count < dev_priv->ips.last_count2) { |
3130 | if (count < dev_priv->ips.last_count2) { |
3004 | diff = ~0UL - dev_priv->ips.last_count2; |
3131 | diff = ~0UL - dev_priv->ips.last_count2; |
3005 | diff += count; |
3132 | diff += count; |
3006 | } else { |
3133 | } else { |
3007 | diff = count - dev_priv->ips.last_count2; |
3134 | diff = count - dev_priv->ips.last_count2; |
3008 | } |
3135 | } |
3009 | 3136 | ||
3010 | dev_priv->ips.last_count2 = count; |
3137 | dev_priv->ips.last_count2 = count; |
3011 | dev_priv->ips.last_time2 = now; |
3138 | dev_priv->ips.last_time2 = now; |
3012 | 3139 | ||
3013 | /* More magic constants... */ |
3140 | /* More magic constants... */ |
3014 | diff = diff * 1181; |
3141 | diff = diff * 1181; |
3015 | diff = div_u64(diff, diffms * 10); |
3142 | diff = div_u64(diff, diffms * 10); |
3016 | dev_priv->ips.gfx_power = diff; |
3143 | dev_priv->ips.gfx_power = diff; |
3017 | } |
3144 | } |
3018 | 3145 | ||
3019 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3146 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3020 | { |
3147 | { |
3021 | if (dev_priv->info->gen != 5) |
3148 | if (dev_priv->info->gen != 5) |
3022 | return; |
3149 | return; |
3023 | 3150 | ||
3024 | spin_lock_irq(&mchdev_lock); |
3151 | spin_lock_irq(&mchdev_lock); |
3025 | 3152 | ||
3026 | __i915_update_gfx_val(dev_priv); |
3153 | __i915_update_gfx_val(dev_priv); |
3027 | 3154 | ||
3028 | spin_unlock_irq(&mchdev_lock); |
3155 | spin_unlock_irq(&mchdev_lock); |
3029 | } |
3156 | } |
3030 | 3157 | ||
3031 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
3158 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
3032 | { |
3159 | { |
3033 | unsigned long t, corr, state1, corr2, state2; |
3160 | unsigned long t, corr, state1, corr2, state2; |
3034 | u32 pxvid, ext_v; |
3161 | u32 pxvid, ext_v; |
3035 | 3162 | ||
3036 | assert_spin_locked(&mchdev_lock); |
3163 | assert_spin_locked(&mchdev_lock); |
3037 | 3164 | ||
3038 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
3165 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
3039 | pxvid = (pxvid >> 24) & 0x7f; |
3166 | pxvid = (pxvid >> 24) & 0x7f; |
3040 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
3167 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
3041 | 3168 | ||
3042 | state1 = ext_v; |
3169 | state1 = ext_v; |
3043 | 3170 | ||
3044 | t = i915_mch_val(dev_priv); |
3171 | t = i915_mch_val(dev_priv); |
3045 | 3172 | ||
3046 | /* Revel in the empirically derived constants */ |
3173 | /* Revel in the empirically derived constants */ |
3047 | 3174 | ||
3048 | /* Correction factor in 1/100000 units */ |
3175 | /* Correction factor in 1/100000 units */ |
3049 | if (t > 80) |
3176 | if (t > 80) |
3050 | corr = ((t * 2349) + 135940); |
3177 | corr = ((t * 2349) + 135940); |
3051 | else if (t >= 50) |
3178 | else if (t >= 50) |
3052 | corr = ((t * 964) + 29317); |
3179 | corr = ((t * 964) + 29317); |
3053 | else /* < 50 */ |
3180 | else /* < 50 */ |
3054 | corr = ((t * 301) + 1004); |
3181 | corr = ((t * 301) + 1004); |
3055 | 3182 | ||
3056 | corr = corr * ((150142 * state1) / 10000 - 78642); |
3183 | corr = corr * ((150142 * state1) / 10000 - 78642); |
3057 | corr /= 100000; |
3184 | corr /= 100000; |
3058 | corr2 = (corr * dev_priv->ips.corr); |
3185 | corr2 = (corr * dev_priv->ips.corr); |
3059 | 3186 | ||
3060 | state2 = (corr2 * state1) / 10000; |
3187 | state2 = (corr2 * state1) / 10000; |
3061 | state2 /= 100; /* convert to mW */ |
3188 | state2 /= 100; /* convert to mW */ |
3062 | 3189 | ||
3063 | __i915_update_gfx_val(dev_priv); |
3190 | __i915_update_gfx_val(dev_priv); |
3064 | 3191 | ||
3065 | return dev_priv->ips.gfx_power + state2; |
3192 | return dev_priv->ips.gfx_power + state2; |
3066 | } |
3193 | } |
3067 | 3194 | ||
3068 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
3195 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
3069 | { |
3196 | { |
3070 | unsigned long val; |
3197 | unsigned long val; |
3071 | 3198 | ||
3072 | if (dev_priv->info->gen != 5) |
3199 | if (dev_priv->info->gen != 5) |
3073 | return 0; |
3200 | return 0; |
3074 | 3201 | ||
3075 | spin_lock_irq(&mchdev_lock); |
3202 | spin_lock_irq(&mchdev_lock); |
3076 | 3203 | ||
3077 | val = __i915_gfx_val(dev_priv); |
3204 | val = __i915_gfx_val(dev_priv); |
3078 | 3205 | ||
3079 | spin_unlock_irq(&mchdev_lock); |
3206 | spin_unlock_irq(&mchdev_lock); |
3080 | 3207 | ||
3081 | return val; |
3208 | return val; |
3082 | } |
3209 | } |
3083 | 3210 | ||
3084 | /** |
3211 | /** |
3085 | * i915_read_mch_val - return value for IPS use |
3212 | * i915_read_mch_val - return value for IPS use |
3086 | * |
3213 | * |
3087 | * Calculate and return a value for the IPS driver to use when deciding whether |
3214 | * Calculate and return a value for the IPS driver to use when deciding whether |
3088 | * we have thermal and power headroom to increase CPU or GPU power budget. |
3215 | * we have thermal and power headroom to increase CPU or GPU power budget. |
3089 | */ |
3216 | */ |
3090 | unsigned long i915_read_mch_val(void) |
3217 | unsigned long i915_read_mch_val(void) |
3091 | { |
3218 | { |
3092 | struct drm_i915_private *dev_priv; |
3219 | struct drm_i915_private *dev_priv; |
3093 | unsigned long chipset_val, graphics_val, ret = 0; |
3220 | unsigned long chipset_val, graphics_val, ret = 0; |
3094 | 3221 | ||
3095 | spin_lock_irq(&mchdev_lock); |
3222 | spin_lock_irq(&mchdev_lock); |
3096 | if (!i915_mch_dev) |
3223 | if (!i915_mch_dev) |
3097 | goto out_unlock; |
3224 | goto out_unlock; |
3098 | dev_priv = i915_mch_dev; |
3225 | dev_priv = i915_mch_dev; |
3099 | 3226 | ||
3100 | chipset_val = __i915_chipset_val(dev_priv); |
3227 | chipset_val = __i915_chipset_val(dev_priv); |
3101 | graphics_val = __i915_gfx_val(dev_priv); |
3228 | graphics_val = __i915_gfx_val(dev_priv); |
3102 | 3229 | ||
3103 | ret = chipset_val + graphics_val; |
3230 | ret = chipset_val + graphics_val; |
3104 | 3231 | ||
3105 | out_unlock: |
3232 | out_unlock: |
3106 | spin_unlock_irq(&mchdev_lock); |
3233 | spin_unlock_irq(&mchdev_lock); |
3107 | 3234 | ||
3108 | return ret; |
3235 | return ret; |
3109 | } |
3236 | } |
3110 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
3237 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
3111 | 3238 | ||
3112 | /** |
3239 | /** |
3113 | * i915_gpu_raise - raise GPU frequency limit |
3240 | * i915_gpu_raise - raise GPU frequency limit |
3114 | * |
3241 | * |
3115 | * Raise the limit; IPS indicates we have thermal headroom. |
3242 | * Raise the limit; IPS indicates we have thermal headroom. |
3116 | */ |
3243 | */ |
3117 | bool i915_gpu_raise(void) |
3244 | bool i915_gpu_raise(void) |
3118 | { |
3245 | { |
3119 | struct drm_i915_private *dev_priv; |
3246 | struct drm_i915_private *dev_priv; |
3120 | bool ret = true; |
3247 | bool ret = true; |
3121 | 3248 | ||
3122 | spin_lock_irq(&mchdev_lock); |
3249 | spin_lock_irq(&mchdev_lock); |
3123 | if (!i915_mch_dev) { |
3250 | if (!i915_mch_dev) { |
3124 | ret = false; |
3251 | ret = false; |
3125 | goto out_unlock; |
3252 | goto out_unlock; |
3126 | } |
3253 | } |
3127 | dev_priv = i915_mch_dev; |
3254 | dev_priv = i915_mch_dev; |
3128 | 3255 | ||
3129 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
3256 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
3130 | dev_priv->ips.max_delay--; |
3257 | dev_priv->ips.max_delay--; |
3131 | 3258 | ||
3132 | out_unlock: |
3259 | out_unlock: |
3133 | spin_unlock_irq(&mchdev_lock); |
3260 | spin_unlock_irq(&mchdev_lock); |
3134 | 3261 | ||
3135 | return ret; |
3262 | return ret; |
3136 | } |
3263 | } |
3137 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
3264 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
3138 | 3265 | ||
3139 | /** |
3266 | /** |
3140 | * i915_gpu_lower - lower GPU frequency limit |
3267 | * i915_gpu_lower - lower GPU frequency limit |
3141 | * |
3268 | * |
3142 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
3269 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
3143 | * frequency maximum. |
3270 | * frequency maximum. |
3144 | */ |
3271 | */ |
3145 | bool i915_gpu_lower(void) |
3272 | bool i915_gpu_lower(void) |
3146 | { |
3273 | { |
3147 | struct drm_i915_private *dev_priv; |
3274 | struct drm_i915_private *dev_priv; |
3148 | bool ret = true; |
3275 | bool ret = true; |
3149 | 3276 | ||
3150 | spin_lock_irq(&mchdev_lock); |
3277 | spin_lock_irq(&mchdev_lock); |
3151 | if (!i915_mch_dev) { |
3278 | if (!i915_mch_dev) { |
3152 | ret = false; |
3279 | ret = false; |
3153 | goto out_unlock; |
3280 | goto out_unlock; |
3154 | } |
3281 | } |
3155 | dev_priv = i915_mch_dev; |
3282 | dev_priv = i915_mch_dev; |
3156 | 3283 | ||
3157 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
3284 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
3158 | dev_priv->ips.max_delay++; |
3285 | dev_priv->ips.max_delay++; |
3159 | 3286 | ||
3160 | out_unlock: |
3287 | out_unlock: |
3161 | spin_unlock_irq(&mchdev_lock); |
3288 | spin_unlock_irq(&mchdev_lock); |
3162 | 3289 | ||
3163 | return ret; |
3290 | return ret; |
3164 | } |
3291 | } |
3165 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
3292 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
3166 | 3293 | ||
3167 | /** |
3294 | /** |
3168 | * i915_gpu_busy - indicate GPU business to IPS |
3295 | * i915_gpu_busy - indicate GPU business to IPS |
3169 | * |
3296 | * |
3170 | * Tell the IPS driver whether or not the GPU is busy. |
3297 | * Tell the IPS driver whether or not the GPU is busy. |
3171 | */ |
3298 | */ |
3172 | bool i915_gpu_busy(void) |
3299 | bool i915_gpu_busy(void) |
3173 | { |
3300 | { |
3174 | struct drm_i915_private *dev_priv; |
3301 | struct drm_i915_private *dev_priv; |
3175 | struct intel_ring_buffer *ring; |
3302 | struct intel_ring_buffer *ring; |
3176 | bool ret = false; |
3303 | bool ret = false; |
3177 | int i; |
3304 | int i; |
3178 | 3305 | ||
3179 | spin_lock_irq(&mchdev_lock); |
3306 | spin_lock_irq(&mchdev_lock); |
3180 | if (!i915_mch_dev) |
3307 | if (!i915_mch_dev) |
3181 | goto out_unlock; |
3308 | goto out_unlock; |
3182 | dev_priv = i915_mch_dev; |
3309 | dev_priv = i915_mch_dev; |
3183 | 3310 | ||
3184 | for_each_ring(ring, dev_priv, i) |
3311 | for_each_ring(ring, dev_priv, i) |
3185 | ret |= !list_empty(&ring->request_list); |
3312 | ret |= !list_empty(&ring->request_list); |
3186 | 3313 | ||
3187 | out_unlock: |
3314 | out_unlock: |
3188 | spin_unlock_irq(&mchdev_lock); |
3315 | spin_unlock_irq(&mchdev_lock); |
3189 | 3316 | ||
3190 | return ret; |
3317 | return ret; |
3191 | } |
3318 | } |
3192 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
3319 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
3193 | 3320 | ||
3194 | /** |
3321 | /** |
3195 | * i915_gpu_turbo_disable - disable graphics turbo |
3322 | * i915_gpu_turbo_disable - disable graphics turbo |
3196 | * |
3323 | * |
3197 | * Disable graphics turbo by resetting the max frequency and setting the |
3324 | * Disable graphics turbo by resetting the max frequency and setting the |
3198 | * current frequency to the default. |
3325 | * current frequency to the default. |
3199 | */ |
3326 | */ |
3200 | bool i915_gpu_turbo_disable(void) |
3327 | bool i915_gpu_turbo_disable(void) |
3201 | { |
3328 | { |
3202 | struct drm_i915_private *dev_priv; |
3329 | struct drm_i915_private *dev_priv; |
3203 | bool ret = true; |
3330 | bool ret = true; |
3204 | 3331 | ||
3205 | spin_lock_irq(&mchdev_lock); |
3332 | spin_lock_irq(&mchdev_lock); |
3206 | if (!i915_mch_dev) { |
3333 | if (!i915_mch_dev) { |
3207 | ret = false; |
3334 | ret = false; |
3208 | goto out_unlock; |
3335 | goto out_unlock; |
3209 | } |
3336 | } |
3210 | dev_priv = i915_mch_dev; |
3337 | dev_priv = i915_mch_dev; |
3211 | 3338 | ||
3212 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
3339 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
3213 | 3340 | ||
3214 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
3341 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
3215 | ret = false; |
3342 | ret = false; |
3216 | 3343 | ||
3217 | out_unlock: |
3344 | out_unlock: |
3218 | spin_unlock_irq(&mchdev_lock); |
3345 | spin_unlock_irq(&mchdev_lock); |
3219 | 3346 | ||
3220 | return ret; |
3347 | return ret; |
3221 | } |
3348 | } |
3222 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
3349 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
3223 | 3350 | ||
3224 | /** |
3351 | /** |
3225 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
3352 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
3226 | * IPS got loaded first. |
3353 | * IPS got loaded first. |
3227 | * |
3354 | * |
3228 | * This awkward dance is so that neither module has to depend on the |
3355 | * This awkward dance is so that neither module has to depend on the |
3229 | * other in order for IPS to do the appropriate communication of |
3356 | * other in order for IPS to do the appropriate communication of |
3230 | * GPU turbo limits to i915. |
3357 | * GPU turbo limits to i915. |
3231 | */ |
3358 | */ |
3232 | static void |
3359 | static void |
3233 | ips_ping_for_i915_load(void) |
3360 | ips_ping_for_i915_load(void) |
3234 | { |
3361 | { |
3235 | void (*link)(void); |
3362 | void (*link)(void); |
3236 | 3363 | ||
3237 | // link = symbol_get(ips_link_to_i915_driver); |
3364 | // link = symbol_get(ips_link_to_i915_driver); |
3238 | // if (link) { |
3365 | // if (link) { |
3239 | // link(); |
3366 | // link(); |
3240 | // symbol_put(ips_link_to_i915_driver); |
3367 | // symbol_put(ips_link_to_i915_driver); |
3241 | // } |
3368 | // } |
3242 | } |
3369 | } |
3243 | 3370 | ||
3244 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
3371 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
3245 | { |
3372 | { |
3246 | /* We only register the i915 ips part with intel-ips once everything is |
3373 | /* We only register the i915 ips part with intel-ips once everything is |
3247 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
3374 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
3248 | spin_lock_irq(&mchdev_lock); |
3375 | spin_lock_irq(&mchdev_lock); |
3249 | i915_mch_dev = dev_priv; |
3376 | i915_mch_dev = dev_priv; |
3250 | spin_unlock_irq(&mchdev_lock); |
3377 | spin_unlock_irq(&mchdev_lock); |
3251 | 3378 | ||
3252 | ips_ping_for_i915_load(); |
3379 | ips_ping_for_i915_load(); |
3253 | } |
3380 | } |
3254 | 3381 | ||
3255 | void intel_gpu_ips_teardown(void) |
3382 | void intel_gpu_ips_teardown(void) |
3256 | { |
3383 | { |
3257 | spin_lock_irq(&mchdev_lock); |
3384 | spin_lock_irq(&mchdev_lock); |
3258 | i915_mch_dev = NULL; |
3385 | i915_mch_dev = NULL; |
3259 | spin_unlock_irq(&mchdev_lock); |
3386 | spin_unlock_irq(&mchdev_lock); |
3260 | } |
3387 | } |
3261 | static void intel_init_emon(struct drm_device *dev) |
3388 | static void intel_init_emon(struct drm_device *dev) |
3262 | { |
3389 | { |
3263 | struct drm_i915_private *dev_priv = dev->dev_private; |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
3264 | u32 lcfuse; |
3391 | u32 lcfuse; |
3265 | u8 pxw[16]; |
3392 | u8 pxw[16]; |
3266 | int i; |
3393 | int i; |
3267 | 3394 | ||
3268 | /* Disable to program */ |
3395 | /* Disable to program */ |
3269 | I915_WRITE(ECR, 0); |
3396 | I915_WRITE(ECR, 0); |
3270 | POSTING_READ(ECR); |
3397 | POSTING_READ(ECR); |
3271 | 3398 | ||
3272 | /* Program energy weights for various events */ |
3399 | /* Program energy weights for various events */ |
3273 | I915_WRITE(SDEW, 0x15040d00); |
3400 | I915_WRITE(SDEW, 0x15040d00); |
3274 | I915_WRITE(CSIEW0, 0x007f0000); |
3401 | I915_WRITE(CSIEW0, 0x007f0000); |
3275 | I915_WRITE(CSIEW1, 0x1e220004); |
3402 | I915_WRITE(CSIEW1, 0x1e220004); |
3276 | I915_WRITE(CSIEW2, 0x04000004); |
3403 | I915_WRITE(CSIEW2, 0x04000004); |
3277 | 3404 | ||
3278 | for (i = 0; i < 5; i++) |
3405 | for (i = 0; i < 5; i++) |
3279 | I915_WRITE(PEW + (i * 4), 0); |
3406 | I915_WRITE(PEW + (i * 4), 0); |
3280 | for (i = 0; i < 3; i++) |
3407 | for (i = 0; i < 3; i++) |
3281 | I915_WRITE(DEW + (i * 4), 0); |
3408 | I915_WRITE(DEW + (i * 4), 0); |
3282 | 3409 | ||
3283 | /* Program P-state weights to account for frequency power adjustment */ |
3410 | /* Program P-state weights to account for frequency power adjustment */ |
3284 | for (i = 0; i < 16; i++) { |
3411 | for (i = 0; i < 16; i++) { |
3285 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
3412 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
3286 | unsigned long freq = intel_pxfreq(pxvidfreq); |
3413 | unsigned long freq = intel_pxfreq(pxvidfreq); |
3287 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
3414 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
3288 | PXVFREQ_PX_SHIFT; |
3415 | PXVFREQ_PX_SHIFT; |
3289 | unsigned long val; |
3416 | unsigned long val; |
3290 | 3417 | ||
3291 | val = vid * vid; |
3418 | val = vid * vid; |
3292 | val *= (freq / 1000); |
3419 | val *= (freq / 1000); |
3293 | val *= 255; |
3420 | val *= 255; |
3294 | val /= (127*127*900); |
3421 | val /= (127*127*900); |
3295 | if (val > 0xff) |
3422 | if (val > 0xff) |
3296 | DRM_ERROR("bad pxval: %ld\n", val); |
3423 | DRM_ERROR("bad pxval: %ld\n", val); |
3297 | pxw[i] = val; |
3424 | pxw[i] = val; |
3298 | } |
3425 | } |
3299 | /* Render standby states get 0 weight */ |
3426 | /* Render standby states get 0 weight */ |
3300 | pxw[14] = 0; |
3427 | pxw[14] = 0; |
3301 | pxw[15] = 0; |
3428 | pxw[15] = 0; |
3302 | 3429 | ||
3303 | for (i = 0; i < 4; i++) { |
3430 | for (i = 0; i < 4; i++) { |
3304 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
3431 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
3305 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
3432 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
3306 | I915_WRITE(PXW + (i * 4), val); |
3433 | I915_WRITE(PXW + (i * 4), val); |
3307 | } |
3434 | } |
3308 | 3435 | ||
3309 | /* Adjust magic regs to magic values (more experimental results) */ |
3436 | /* Adjust magic regs to magic values (more experimental results) */ |
3310 | I915_WRITE(OGW0, 0); |
3437 | I915_WRITE(OGW0, 0); |
3311 | I915_WRITE(OGW1, 0); |
3438 | I915_WRITE(OGW1, 0); |
3312 | I915_WRITE(EG0, 0x00007f00); |
3439 | I915_WRITE(EG0, 0x00007f00); |
3313 | I915_WRITE(EG1, 0x0000000e); |
3440 | I915_WRITE(EG1, 0x0000000e); |
3314 | I915_WRITE(EG2, 0x000e0000); |
3441 | I915_WRITE(EG2, 0x000e0000); |
3315 | I915_WRITE(EG3, 0x68000300); |
3442 | I915_WRITE(EG3, 0x68000300); |
3316 | I915_WRITE(EG4, 0x42000000); |
3443 | I915_WRITE(EG4, 0x42000000); |
3317 | I915_WRITE(EG5, 0x00140031); |
3444 | I915_WRITE(EG5, 0x00140031); |
3318 | I915_WRITE(EG6, 0); |
3445 | I915_WRITE(EG6, 0); |
3319 | I915_WRITE(EG7, 0); |
3446 | I915_WRITE(EG7, 0); |
3320 | 3447 | ||
3321 | for (i = 0; i < 8; i++) |
3448 | for (i = 0; i < 8; i++) |
3322 | I915_WRITE(PXWL + (i * 4), 0); |
3449 | I915_WRITE(PXWL + (i * 4), 0); |
3323 | 3450 | ||
3324 | /* Enable PMON + select events */ |
3451 | /* Enable PMON + select events */ |
3325 | I915_WRITE(ECR, 0x80000019); |
3452 | I915_WRITE(ECR, 0x80000019); |
3326 | 3453 | ||
3327 | lcfuse = I915_READ(LCFUSE02); |
3454 | lcfuse = I915_READ(LCFUSE02); |
3328 | 3455 | ||
3329 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
3456 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
3330 | } |
3457 | } |
3331 | 3458 | ||
3332 | void intel_disable_gt_powersave(struct drm_device *dev) |
3459 | void intel_disable_gt_powersave(struct drm_device *dev) |
3333 | { |
3460 | { |
- | 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3462 | ||
3334 | if (IS_IRONLAKE_M(dev)) { |
3463 | if (IS_IRONLAKE_M(dev)) { |
3335 | ironlake_disable_drps(dev); |
3464 | ironlake_disable_drps(dev); |
3336 | ironlake_disable_rc6(dev); |
3465 | ironlake_disable_rc6(dev); |
3337 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3466 | } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { |
3338 | gen6_disable_rps(dev); |
3467 | gen6_disable_rps(dev); |
3339 | } |
3468 | } |
3340 | } |
3469 | } |
3341 | 3470 | ||
3342 | void intel_enable_gt_powersave(struct drm_device *dev) |
3471 | void intel_enable_gt_powersave(struct drm_device *dev) |
3343 | { |
3472 | { |
- | 3473 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3474 | ||
3344 | if (IS_IRONLAKE_M(dev)) { |
3475 | if (IS_IRONLAKE_M(dev)) { |
3345 | ironlake_enable_drps(dev); |
3476 | ironlake_enable_drps(dev); |
3346 | ironlake_enable_rc6(dev); |
3477 | ironlake_enable_rc6(dev); |
3347 | intel_init_emon(dev); |
3478 | intel_init_emon(dev); |
3348 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3479 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
- | 3480 | /* |
|
- | 3481 | * PCU communication is slow and this doesn't need to be |
|
- | 3482 | * done at any specific time, so do this out of our fast path |
|
3349 | // gen6_enable_rps(dev); |
3483 | * to make resume and init faster. |
- | 3484 | */ |
|
- | 3485 | // schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
|
3350 | // gen6_update_ring_freq(dev); |
3486 | // round_jiffies_up_relative(HZ)); |
3351 | } |
3487 | } |
3352 | } |
3488 | } |
- | 3489 | ||
- | 3490 | static void ibx_init_clock_gating(struct drm_device *dev) |
|
- | 3491 | { |
|
- | 3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3493 | ||
- | 3494 | /* |
|
- | 3495 | * On Ibex Peak and Cougar Point, we need to disable clock |
|
- | 3496 | * gating for the panel power sequencer or it will fail to |
|
- | 3497 | * start up when no ports are active. |
|
- | 3498 | */ |
|
- | 3499 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
|
- | 3500 | } |
|
3353 | 3501 | ||
3354 | static void ironlake_init_clock_gating(struct drm_device *dev) |
3502 | static void ironlake_init_clock_gating(struct drm_device *dev) |
3355 | { |
3503 | { |
3356 | struct drm_i915_private *dev_priv = dev->dev_private; |
3504 | struct drm_i915_private *dev_priv = dev->dev_private; |
3357 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
3505 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3358 | 3506 | ||
3359 | /* Required for FBC */ |
3507 | /* Required for FBC */ |
3360 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
3508 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3361 | DPFCRUNIT_CLOCK_GATE_DISABLE | |
3509 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
3362 | DPFDUNIT_CLOCK_GATE_DISABLE; |
- | |
3363 | /* Required for CxSR */ |
- | |
3364 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
3510 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
3365 | 3511 | ||
3366 | I915_WRITE(PCH_3DCGDIS0, |
3512 | I915_WRITE(PCH_3DCGDIS0, |
3367 | MARIUNIT_CLOCK_GATE_DISABLE | |
3513 | MARIUNIT_CLOCK_GATE_DISABLE | |
3368 | SVSMUNIT_CLOCK_GATE_DISABLE); |
3514 | SVSMUNIT_CLOCK_GATE_DISABLE); |
3369 | I915_WRITE(PCH_3DCGDIS1, |
3515 | I915_WRITE(PCH_3DCGDIS1, |
3370 | VFMUNIT_CLOCK_GATE_DISABLE); |
3516 | VFMUNIT_CLOCK_GATE_DISABLE); |
3371 | - | ||
3372 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
- | |
3373 | 3517 | ||
3374 | /* |
3518 | /* |
3375 | * According to the spec the following bits should be set in |
3519 | * According to the spec the following bits should be set in |
3376 | * order to enable memory self-refresh |
3520 | * order to enable memory self-refresh |
3377 | * The bit 22/21 of 0x42004 |
3521 | * The bit 22/21 of 0x42004 |
3378 | * The bit 5 of 0x42020 |
3522 | * The bit 5 of 0x42020 |
3379 | * The bit 15 of 0x45000 |
3523 | * The bit 15 of 0x45000 |
3380 | */ |
3524 | */ |
3381 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3525 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3382 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
3526 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
3383 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
3527 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
3384 | I915_WRITE(ILK_DSPCLK_GATE, |
- | |
3385 | (I915_READ(ILK_DSPCLK_GATE) | |
- | |
3386 | ILK_DPARB_CLK_GATE)); |
3528 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
3387 | I915_WRITE(DISP_ARB_CTL, |
3529 | I915_WRITE(DISP_ARB_CTL, |
3388 | (I915_READ(DISP_ARB_CTL) | |
3530 | (I915_READ(DISP_ARB_CTL) | |
3389 | DISP_FBC_WM_DIS)); |
3531 | DISP_FBC_WM_DIS)); |
3390 | I915_WRITE(WM3_LP_ILK, 0); |
3532 | I915_WRITE(WM3_LP_ILK, 0); |
3391 | I915_WRITE(WM2_LP_ILK, 0); |
3533 | I915_WRITE(WM2_LP_ILK, 0); |
3392 | I915_WRITE(WM1_LP_ILK, 0); |
3534 | I915_WRITE(WM1_LP_ILK, 0); |
3393 | 3535 | ||
3394 | /* |
3536 | /* |
3395 | * Based on the document from hardware guys the following bits |
3537 | * Based on the document from hardware guys the following bits |
3396 | * should be set unconditionally in order to enable FBC. |
3538 | * should be set unconditionally in order to enable FBC. |
3397 | * The bit 22 of 0x42000 |
3539 | * The bit 22 of 0x42000 |
3398 | * The bit 22 of 0x42004 |
3540 | * The bit 22 of 0x42004 |
3399 | * The bit 7,8,9 of 0x42020. |
3541 | * The bit 7,8,9 of 0x42020. |
3400 | */ |
3542 | */ |
3401 | if (IS_IRONLAKE_M(dev)) { |
3543 | if (IS_IRONLAKE_M(dev)) { |
3402 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3544 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3403 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3545 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3404 | ILK_FBCQ_DIS); |
3546 | ILK_FBCQ_DIS); |
3405 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3547 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3406 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3548 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3407 | ILK_DPARB_GATE); |
3549 | ILK_DPARB_GATE); |
3408 | I915_WRITE(ILK_DSPCLK_GATE, |
- | |
3409 | I915_READ(ILK_DSPCLK_GATE) | |
- | |
3410 | ILK_DPFC_DIS1 | |
- | |
3411 | ILK_DPFC_DIS2 | |
- | |
3412 | ILK_CLK_FBC); |
- | |
3413 | } |
3550 | } |
- | 3551 | ||
- | 3552 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
|
3414 | 3553 | ||
3415 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3554 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3416 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3555 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3417 | ILK_ELPIN_409_SELECT); |
3556 | ILK_ELPIN_409_SELECT); |
3418 | I915_WRITE(_3D_CHICKEN2, |
3557 | I915_WRITE(_3D_CHICKEN2, |
3419 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
3558 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
3420 | _3D_CHICKEN2_WM_READ_PIPELINED); |
3559 | _3D_CHICKEN2_WM_READ_PIPELINED); |
- | 3560 | ||
- | 3561 | /* WaDisableRenderCachePipelinedFlush */ |
|
- | 3562 | I915_WRITE(CACHE_MODE_0, |
|
- | 3563 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
|
- | 3564 | ||
- | 3565 | ibx_init_clock_gating(dev); |
|
- | 3566 | } |
|
- | 3567 | ||
- | 3568 | static void cpt_init_clock_gating(struct drm_device *dev) |
|
- | 3569 | { |
|
- | 3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3571 | int pipe; |
|
- | 3572 | ||
- | 3573 | /* |
|
- | 3574 | * On Ibex Peak and Cougar Point, we need to disable clock |
|
- | 3575 | * gating for the panel power sequencer or it will fail to |
|
- | 3576 | * start up when no ports are active. |
|
- | 3577 | */ |
|
- | 3578 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
|
- | 3579 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
|
- | 3580 | DPLS_EDP_PPS_FIX_DIS); |
|
- | 3581 | /* The below fixes the weird display corruption, a few pixels shifted |
|
- | 3582 | * downward, on (only) LVDS of some HP laptops with IVY. |
|
- | 3583 | */ |
|
- | 3584 | for_each_pipe(pipe) |
|
- | 3585 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); |
|
- | 3586 | /* WADP0ClockGatingDisable */ |
|
- | 3587 | for_each_pipe(pipe) { |
|
- | 3588 | I915_WRITE(TRANS_CHICKEN1(pipe), |
|
- | 3589 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
|
- | 3590 | } |
|
3421 | } |
3591 | } |
3422 | 3592 | ||
3423 | static void gen6_init_clock_gating(struct drm_device *dev) |
3593 | static void gen6_init_clock_gating(struct drm_device *dev) |
3424 | { |
3594 | { |
3425 | struct drm_i915_private *dev_priv = dev->dev_private; |
3595 | struct drm_i915_private *dev_priv = dev->dev_private; |
3426 | int pipe; |
3596 | int pipe; |
3427 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
3597 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3428 | 3598 | ||
3429 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
3599 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3430 | 3600 | ||
3431 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3601 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3432 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3602 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3433 | ILK_ELPIN_409_SELECT); |
3603 | ILK_ELPIN_409_SELECT); |
- | 3604 | ||
- | 3605 | /* WaDisableHiZPlanesWhenMSAAEnabled */ |
|
- | 3606 | I915_WRITE(_3D_CHICKEN, |
|
- | 3607 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
|
- | 3608 | ||
- | 3609 | /* WaSetupGtModeTdRowDispatch */ |
|
- | 3610 | if (IS_SNB_GT1(dev)) |
|
- | 3611 | I915_WRITE(GEN6_GT_MODE, |
|
- | 3612 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
|
3434 | 3613 | ||
3435 | I915_WRITE(WM3_LP_ILK, 0); |
3614 | I915_WRITE(WM3_LP_ILK, 0); |
3436 | I915_WRITE(WM2_LP_ILK, 0); |
3615 | I915_WRITE(WM2_LP_ILK, 0); |
3437 | I915_WRITE(WM1_LP_ILK, 0); |
3616 | I915_WRITE(WM1_LP_ILK, 0); |
3438 | 3617 | ||
3439 | I915_WRITE(CACHE_MODE_0, |
3618 | I915_WRITE(CACHE_MODE_0, |
3440 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
3619 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
3441 | 3620 | ||
3442 | I915_WRITE(GEN6_UCGCTL1, |
3621 | I915_WRITE(GEN6_UCGCTL1, |
3443 | I915_READ(GEN6_UCGCTL1) | |
3622 | I915_READ(GEN6_UCGCTL1) | |
3444 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
3623 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
3445 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
3624 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
3446 | 3625 | ||
3447 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3626 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3448 | * gating disable must be set. Failure to set it results in |
3627 | * gating disable must be set. Failure to set it results in |
3449 | * flickering pixels due to Z write ordering failures after |
3628 | * flickering pixels due to Z write ordering failures after |
3450 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3629 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3451 | * Sanctuary and Tropics, and apparently anything else with |
3630 | * Sanctuary and Tropics, and apparently anything else with |
3452 | * alpha test or pixel discard. |
3631 | * alpha test or pixel discard. |
3453 | * |
3632 | * |
3454 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3633 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3455 | * but we didn't debug actual testcases to find it out. |
3634 | * but we didn't debug actual testcases to find it out. |
3456 | * |
3635 | * |
3457 | * Also apply WaDisableVDSUnitClockGating and |
3636 | * Also apply WaDisableVDSUnitClockGating and |
3458 | * WaDisableRCPBUnitClockGating. |
3637 | * WaDisableRCPBUnitClockGating. |
3459 | */ |
3638 | */ |
3460 | I915_WRITE(GEN6_UCGCTL2, |
3639 | I915_WRITE(GEN6_UCGCTL2, |
3461 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3640 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3462 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3641 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3463 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3642 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3464 | 3643 | ||
3465 | /* Bspec says we need to always set all mask bits. */ |
3644 | /* Bspec says we need to always set all mask bits. */ |
3466 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3645 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3467 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
3646 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
3468 | 3647 | ||
3469 | /* |
3648 | /* |
3470 | * According to the spec the following bits should be |
3649 | * According to the spec the following bits should be |
3471 | * set in order to enable memory self-refresh and fbc: |
3650 | * set in order to enable memory self-refresh and fbc: |
3472 | * The bit21 and bit22 of 0x42000 |
3651 | * The bit21 and bit22 of 0x42000 |
3473 | * The bit21 and bit22 of 0x42004 |
3652 | * The bit21 and bit22 of 0x42004 |
3474 | * The bit5 and bit7 of 0x42020 |
3653 | * The bit5 and bit7 of 0x42020 |
3475 | * The bit14 of 0x70180 |
3654 | * The bit14 of 0x70180 |
3476 | * The bit14 of 0x71180 |
3655 | * The bit14 of 0x71180 |
3477 | */ |
3656 | */ |
3478 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3657 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
3479 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3658 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
3480 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
3659 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
3481 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3660 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3482 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3661 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3483 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
3662 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
3484 | I915_WRITE(ILK_DSPCLK_GATE, |
3663 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3485 | I915_READ(ILK_DSPCLK_GATE) | |
3664 | I915_READ(ILK_DSPCLK_GATE_D) | |
3486 | ILK_DPARB_CLK_GATE | |
3665 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
3487 | ILK_DPFD_CLK_GATE); |
3666 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
- | 3667 | ||
3488 | 3668 | /* WaMbcDriverBootEnable */ |
|
3489 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3669 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3490 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3670 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3491 | 3671 | ||
3492 | for_each_pipe(pipe) { |
3672 | for_each_pipe(pipe) { |
3493 | I915_WRITE(DSPCNTR(pipe), |
3673 | I915_WRITE(DSPCNTR(pipe), |
3494 | I915_READ(DSPCNTR(pipe)) | |
3674 | I915_READ(DSPCNTR(pipe)) | |
3495 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3675 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3496 | intel_flush_display_plane(dev_priv, pipe); |
3676 | intel_flush_display_plane(dev_priv, pipe); |
3497 | } |
3677 | } |
3498 | 3678 | ||
3499 | /* The default value should be 0x200 according to docs, but the two |
3679 | /* The default value should be 0x200 according to docs, but the two |
3500 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3680 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
3501 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3681 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
3502 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
3682 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
- | 3683 | ||
- | 3684 | cpt_init_clock_gating(dev); |
|
3503 | } |
3685 | } |
3504 | 3686 | ||
3505 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
3687 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
3506 | { |
3688 | { |
3507 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
3689 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
3508 | 3690 | ||
3509 | reg &= ~GEN7_FF_SCHED_MASK; |
3691 | reg &= ~GEN7_FF_SCHED_MASK; |
3510 | reg |= GEN7_FF_TS_SCHED_HW; |
3692 | reg |= GEN7_FF_TS_SCHED_HW; |
3511 | reg |= GEN7_FF_VS_SCHED_HW; |
3693 | reg |= GEN7_FF_VS_SCHED_HW; |
3512 | reg |= GEN7_FF_DS_SCHED_HW; |
3694 | reg |= GEN7_FF_DS_SCHED_HW; |
3513 | 3695 | ||
3514 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3696 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3515 | } |
3697 | } |
- | 3698 | ||
- | 3699 | static void lpt_init_clock_gating(struct drm_device *dev) |
|
- | 3700 | { |
|
- | 3701 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3702 | ||
- | 3703 | /* |
|
- | 3704 | * TODO: this bit should only be enabled when really needed, then |
|
- | 3705 | * disabled when not needed anymore in order to save power. |
|
- | 3706 | */ |
|
- | 3707 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
|
- | 3708 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
|
- | 3709 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
|
- | 3710 | PCH_LP_PARTITION_LEVEL_DISABLE); |
|
- | 3711 | } |
|
3516 | 3712 | ||
3517 | static void haswell_init_clock_gating(struct drm_device *dev) |
3713 | static void haswell_init_clock_gating(struct drm_device *dev) |
3518 | { |
3714 | { |
3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
3715 | struct drm_i915_private *dev_priv = dev->dev_private; |
3520 | int pipe; |
3716 | int pipe; |
3521 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
- | |
3522 | - | ||
3523 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
- | |
3524 | 3717 | ||
3525 | I915_WRITE(WM3_LP_ILK, 0); |
3718 | I915_WRITE(WM3_LP_ILK, 0); |
3526 | I915_WRITE(WM2_LP_ILK, 0); |
3719 | I915_WRITE(WM2_LP_ILK, 0); |
3527 | I915_WRITE(WM1_LP_ILK, 0); |
3720 | I915_WRITE(WM1_LP_ILK, 0); |
3528 | 3721 | ||
3529 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3722 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3530 | * This implements the WaDisableRCZUnitClockGating workaround. |
3723 | * This implements the WaDisableRCZUnitClockGating workaround. |
3531 | */ |
3724 | */ |
3532 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
3725 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
3533 | - | ||
3534 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
- | |
3535 | - | ||
3536 | I915_WRITE(IVB_CHICKEN3, |
- | |
3537 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
- | |
3538 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
- | |
3539 | 3726 | ||
3540 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3727 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3541 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3728 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3542 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3729 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3543 | 3730 | ||
3544 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3731 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3545 | I915_WRITE(GEN7_L3CNTLREG1, |
3732 | I915_WRITE(GEN7_L3CNTLREG1, |
3546 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3733 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3547 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3734 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3548 | GEN7_WA_L3_CHICKEN_MODE); |
3735 | GEN7_WA_L3_CHICKEN_MODE); |
3549 | 3736 | ||
3550 | /* This is required by WaCatErrorRejectionIssue */ |
3737 | /* This is required by WaCatErrorRejectionIssue */ |
3551 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3738 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3552 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3739 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3553 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3740 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3554 | 3741 | ||
3555 | for_each_pipe(pipe) { |
3742 | for_each_pipe(pipe) { |
3556 | I915_WRITE(DSPCNTR(pipe), |
3743 | I915_WRITE(DSPCNTR(pipe), |
3557 | I915_READ(DSPCNTR(pipe)) | |
3744 | I915_READ(DSPCNTR(pipe)) | |
3558 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3745 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3559 | intel_flush_display_plane(dev_priv, pipe); |
3746 | intel_flush_display_plane(dev_priv, pipe); |
3560 | } |
3747 | } |
3561 | 3748 | ||
3562 | gen7_setup_fixed_func_scheduler(dev_priv); |
3749 | gen7_setup_fixed_func_scheduler(dev_priv); |
3563 | 3750 | ||
3564 | /* WaDisable4x2SubspanOptimization */ |
3751 | /* WaDisable4x2SubspanOptimization */ |
3565 | I915_WRITE(CACHE_MODE_1, |
3752 | I915_WRITE(CACHE_MODE_1, |
3566 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3753 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
- | 3754 | ||
- | 3755 | /* WaMbcDriverBootEnable */ |
|
- | 3756 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
|
- | 3757 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
|
3567 | 3758 | ||
3568 | /* XXX: This is a workaround for early silicon revisions and should be |
3759 | /* XXX: This is a workaround for early silicon revisions and should be |
3569 | * removed later. |
3760 | * removed later. |
3570 | */ |
3761 | */ |
3571 | I915_WRITE(WM_DBG, |
3762 | I915_WRITE(WM_DBG, |
3572 | I915_READ(WM_DBG) | |
3763 | I915_READ(WM_DBG) | |
3573 | WM_DBG_DISALLOW_MULTIPLE_LP | |
3764 | WM_DBG_DISALLOW_MULTIPLE_LP | |
3574 | WM_DBG_DISALLOW_SPRITE | |
3765 | WM_DBG_DISALLOW_SPRITE | |
3575 | WM_DBG_DISALLOW_MAXFIFO); |
3766 | WM_DBG_DISALLOW_MAXFIFO); |
- | 3767 | ||
3576 | 3768 | lpt_init_clock_gating(dev); |
|
3577 | } |
3769 | } |
3578 | 3770 | ||
3579 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
3771 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
3580 | { |
3772 | { |
3581 | struct drm_i915_private *dev_priv = dev->dev_private; |
3773 | struct drm_i915_private *dev_priv = dev->dev_private; |
3582 | int pipe; |
3774 | int pipe; |
3583 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
- | |
3584 | uint32_t snpcr; |
3775 | uint32_t snpcr; |
3585 | - | ||
3586 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
- | |
3587 | 3776 | ||
3588 | I915_WRITE(WM3_LP_ILK, 0); |
3777 | I915_WRITE(WM3_LP_ILK, 0); |
3589 | I915_WRITE(WM2_LP_ILK, 0); |
3778 | I915_WRITE(WM2_LP_ILK, 0); |
3590 | I915_WRITE(WM1_LP_ILK, 0); |
3779 | I915_WRITE(WM1_LP_ILK, 0); |
3591 | 3780 | ||
- | 3781 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
|
- | 3782 | ||
- | 3783 | /* WaDisableEarlyCull */ |
|
- | 3784 | I915_WRITE(_3D_CHICKEN3, |
|
- | 3785 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
|
3592 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
3786 | |
3593 | 3787 | /* WaDisableBackToBackFlipFix */ |
|
3594 | I915_WRITE(IVB_CHICKEN3, |
3788 | I915_WRITE(IVB_CHICKEN3, |
3595 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3789 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3596 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3790 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
- | 3791 | ||
- | 3792 | /* WaDisablePSDDualDispatchEnable */ |
|
- | 3793 | if (IS_IVB_GT1(dev)) |
|
- | 3794 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
|
- | 3795 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
|
- | 3796 | else |
|
- | 3797 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, |
|
- | 3798 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
|
3597 | 3799 | ||
3598 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3800 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3599 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3801 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3600 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3802 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3601 | 3803 | ||
3602 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3804 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3603 | I915_WRITE(GEN7_L3CNTLREG1, |
3805 | I915_WRITE(GEN7_L3CNTLREG1, |
3604 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3806 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
3605 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3807 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
3606 | GEN7_WA_L3_CHICKEN_MODE); |
3808 | GEN7_WA_L3_CHICKEN_MODE); |
- | 3809 | if (IS_IVB_GT1(dev)) |
|
- | 3810 | I915_WRITE(GEN7_ROW_CHICKEN2, |
|
- | 3811 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
|
- | 3812 | else |
|
- | 3813 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
|
- | 3814 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
|
- | 3815 | ||
- | 3816 | ||
- | 3817 | /* WaForceL3Serialization */ |
|
- | 3818 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
|
- | 3819 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
|
3607 | 3820 | ||
3608 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3821 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3609 | * gating disable must be set. Failure to set it results in |
3822 | * gating disable must be set. Failure to set it results in |
3610 | * flickering pixels due to Z write ordering failures after |
3823 | * flickering pixels due to Z write ordering failures after |
3611 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3824 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3612 | * Sanctuary and Tropics, and apparently anything else with |
3825 | * Sanctuary and Tropics, and apparently anything else with |
3613 | * alpha test or pixel discard. |
3826 | * alpha test or pixel discard. |
3614 | * |
3827 | * |
3615 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3828 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3616 | * but we didn't debug actual testcases to find it out. |
3829 | * but we didn't debug actual testcases to find it out. |
3617 | * |
3830 | * |
3618 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3831 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3619 | * This implements the WaDisableRCZUnitClockGating workaround. |
3832 | * This implements the WaDisableRCZUnitClockGating workaround. |
3620 | */ |
3833 | */ |
3621 | I915_WRITE(GEN6_UCGCTL2, |
3834 | I915_WRITE(GEN6_UCGCTL2, |
3622 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3835 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3623 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3836 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3624 | 3837 | ||
3625 | /* This is required by WaCatErrorRejectionIssue */ |
3838 | /* This is required by WaCatErrorRejectionIssue */ |
3626 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3839 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3627 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3840 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3628 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3841 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3629 | 3842 | ||
3630 | for_each_pipe(pipe) { |
3843 | for_each_pipe(pipe) { |
3631 | I915_WRITE(DSPCNTR(pipe), |
3844 | I915_WRITE(DSPCNTR(pipe), |
3632 | I915_READ(DSPCNTR(pipe)) | |
3845 | I915_READ(DSPCNTR(pipe)) | |
3633 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3846 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3634 | intel_flush_display_plane(dev_priv, pipe); |
3847 | intel_flush_display_plane(dev_priv, pipe); |
3635 | } |
3848 | } |
- | 3849 | ||
3636 | 3850 | /* WaMbcDriverBootEnable */ |
|
3637 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3851 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3638 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3852 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3639 | 3853 | ||
3640 | gen7_setup_fixed_func_scheduler(dev_priv); |
3854 | gen7_setup_fixed_func_scheduler(dev_priv); |
3641 | 3855 | ||
3642 | /* WaDisable4x2SubspanOptimization */ |
3856 | /* WaDisable4x2SubspanOptimization */ |
3643 | I915_WRITE(CACHE_MODE_1, |
3857 | I915_WRITE(CACHE_MODE_1, |
3644 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3858 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3645 | 3859 | ||
3646 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
3860 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
3647 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3861 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
3648 | snpcr |= GEN6_MBC_SNPCR_MED; |
3862 | snpcr |= GEN6_MBC_SNPCR_MED; |
3649 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
3863 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
- | 3864 | ||
- | 3865 | cpt_init_clock_gating(dev); |
|
3650 | } |
3866 | } |
3651 | 3867 | ||
3652 | static void valleyview_init_clock_gating(struct drm_device *dev) |
3868 | static void valleyview_init_clock_gating(struct drm_device *dev) |
3653 | { |
3869 | { |
3654 | struct drm_i915_private *dev_priv = dev->dev_private; |
3870 | struct drm_i915_private *dev_priv = dev->dev_private; |
3655 | int pipe; |
3871 | int pipe; |
3656 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
- | |
3657 | - | ||
3658 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
- | |
3659 | 3872 | ||
3660 | I915_WRITE(WM3_LP_ILK, 0); |
3873 | I915_WRITE(WM3_LP_ILK, 0); |
3661 | I915_WRITE(WM2_LP_ILK, 0); |
3874 | I915_WRITE(WM2_LP_ILK, 0); |
3662 | I915_WRITE(WM1_LP_ILK, 0); |
3875 | I915_WRITE(WM1_LP_ILK, 0); |
3663 | 3876 | ||
- | 3877 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
|
- | 3878 | ||
- | 3879 | /* WaDisableEarlyCull */ |
|
- | 3880 | I915_WRITE(_3D_CHICKEN3, |
|
- | 3881 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
|
3664 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
3882 | |
3665 | 3883 | /* WaDisableBackToBackFlipFix */ |
|
3666 | I915_WRITE(IVB_CHICKEN3, |
3884 | I915_WRITE(IVB_CHICKEN3, |
3667 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3885 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
3668 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
3886 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
- | 3887 | ||
- | 3888 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
|
- | 3889 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
|
3669 | 3890 | ||
3670 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3891 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
3671 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3892 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
3672 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3893 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
3673 | 3894 | ||
3674 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3895 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
3675 | I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); |
3896 | I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); |
3676 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
3897 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
- | 3898 | ||
- | 3899 | /* WaForceL3Serialization */ |
|
- | 3900 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
|
- | 3901 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
|
- | 3902 | ||
- | 3903 | /* WaDisableDopClockGating */ |
|
- | 3904 | I915_WRITE(GEN7_ROW_CHICKEN2, |
|
- | 3905 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
|
- | 3906 | ||
- | 3907 | /* WaForceL3Serialization */ |
|
- | 3908 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
|
- | 3909 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
|
3677 | 3910 | ||
3678 | /* This is required by WaCatErrorRejectionIssue */ |
3911 | /* This is required by WaCatErrorRejectionIssue */ |
3679 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3912 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
3680 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3913 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
3681 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
3914 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
- | 3915 | ||
3682 | 3916 | /* WaMbcDriverBootEnable */ |
|
3683 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3917 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3684 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3918 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
3685 | 3919 | ||
3686 | 3920 | ||
3687 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3921 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
3688 | * gating disable must be set. Failure to set it results in |
3922 | * gating disable must be set. Failure to set it results in |
3689 | * flickering pixels due to Z write ordering failures after |
3923 | * flickering pixels due to Z write ordering failures after |
3690 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3924 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
3691 | * Sanctuary and Tropics, and apparently anything else with |
3925 | * Sanctuary and Tropics, and apparently anything else with |
3692 | * alpha test or pixel discard. |
3926 | * alpha test or pixel discard. |
3693 | * |
3927 | * |
3694 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3928 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
3695 | * but we didn't debug actual testcases to find it out. |
3929 | * but we didn't debug actual testcases to find it out. |
3696 | * |
3930 | * |
3697 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3931 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
3698 | * This implements the WaDisableRCZUnitClockGating workaround. |
3932 | * This implements the WaDisableRCZUnitClockGating workaround. |
3699 | * |
3933 | * |
3700 | * Also apply WaDisableVDSUnitClockGating and |
3934 | * Also apply WaDisableVDSUnitClockGating and |
3701 | * WaDisableRCPBUnitClockGating. |
3935 | * WaDisableRCPBUnitClockGating. |
3702 | */ |
3936 | */ |
3703 | I915_WRITE(GEN6_UCGCTL2, |
3937 | I915_WRITE(GEN6_UCGCTL2, |
3704 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3938 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
3705 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
3939 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
3706 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3940 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
3707 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3941 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3708 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3942 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3709 | 3943 | ||
3710 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
3944 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
3711 | 3945 | ||
3712 | for_each_pipe(pipe) { |
3946 | for_each_pipe(pipe) { |
3713 | I915_WRITE(DSPCNTR(pipe), |
3947 | I915_WRITE(DSPCNTR(pipe), |
3714 | I915_READ(DSPCNTR(pipe)) | |
3948 | I915_READ(DSPCNTR(pipe)) | |
3715 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3949 | DISPPLANE_TRICKLE_FEED_DISABLE); |
3716 | intel_flush_display_plane(dev_priv, pipe); |
3950 | intel_flush_display_plane(dev_priv, pipe); |
3717 | } |
3951 | } |
3718 | 3952 | ||
3719 | I915_WRITE(CACHE_MODE_1, |
3953 | I915_WRITE(CACHE_MODE_1, |
3720 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3954 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
3721 | 3955 | ||
3722 | /* |
3956 | /* |
3723 | * On ValleyView, the GUnit needs to signal the GT |
3957 | * On ValleyView, the GUnit needs to signal the GT |
3724 | * when flip and other events complete. So enable |
3958 | * when flip and other events complete. So enable |
3725 | * all the GUnit->GT interrupts here |
3959 | * all the GUnit->GT interrupts here |
3726 | */ |
3960 | */ |
3727 | I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | |
3961 | I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | |
3728 | PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | |
3962 | PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | |
3729 | SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | |
3963 | SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | |
3730 | PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | |
3964 | PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | |
3731 | PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | |
3965 | PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | |
3732 | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | |
3966 | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | |
3733 | PLANEA_FLIPDONE_INT_EN); |
3967 | PLANEA_FLIPDONE_INT_EN); |
- | 3968 | ||
- | 3969 | /* |
|
- | 3970 | * WaDisableVLVClockGating_VBIIssue |
|
- | 3971 | * Disable clock gating on th GCFG unit to prevent a delay |
|
- | 3972 | * in the reporting of vblank events. |
|
- | 3973 | */ |
|
- | 3974 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
|
3734 | } |
3975 | } |
3735 | 3976 | ||
3736 | static void g4x_init_clock_gating(struct drm_device *dev) |
3977 | static void g4x_init_clock_gating(struct drm_device *dev) |
3737 | { |
3978 | { |
3738 | struct drm_i915_private *dev_priv = dev->dev_private; |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; |
3739 | uint32_t dspclk_gate; |
3980 | uint32_t dspclk_gate; |
3740 | 3981 | ||
3741 | I915_WRITE(RENCLK_GATE_D1, 0); |
3982 | I915_WRITE(RENCLK_GATE_D1, 0); |
3742 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
3983 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
3743 | GS_UNIT_CLOCK_GATE_DISABLE | |
3984 | GS_UNIT_CLOCK_GATE_DISABLE | |
3744 | CL_UNIT_CLOCK_GATE_DISABLE); |
3985 | CL_UNIT_CLOCK_GATE_DISABLE); |
3745 | I915_WRITE(RAMCLK_GATE_D, 0); |
3986 | I915_WRITE(RAMCLK_GATE_D, 0); |
3746 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
3987 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
3747 | OVRUNIT_CLOCK_GATE_DISABLE | |
3988 | OVRUNIT_CLOCK_GATE_DISABLE | |
3748 | OVCUNIT_CLOCK_GATE_DISABLE; |
3989 | OVCUNIT_CLOCK_GATE_DISABLE; |
3749 | if (IS_GM45(dev)) |
3990 | if (IS_GM45(dev)) |
3750 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
3991 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
3751 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
3992 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
- | 3993 | ||
- | 3994 | /* WaDisableRenderCachePipelinedFlush */ |
|
- | 3995 | I915_WRITE(CACHE_MODE_0, |
|
- | 3996 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
|
3752 | } |
3997 | } |
3753 | 3998 | ||
3754 | static void crestline_init_clock_gating(struct drm_device *dev) |
3999 | static void crestline_init_clock_gating(struct drm_device *dev) |
3755 | { |
4000 | { |
3756 | struct drm_i915_private *dev_priv = dev->dev_private; |
4001 | struct drm_i915_private *dev_priv = dev->dev_private; |
3757 | 4002 | ||
3758 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
4003 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
3759 | I915_WRITE(RENCLK_GATE_D2, 0); |
4004 | I915_WRITE(RENCLK_GATE_D2, 0); |
3760 | I915_WRITE(DSPCLK_GATE_D, 0); |
4005 | I915_WRITE(DSPCLK_GATE_D, 0); |
3761 | I915_WRITE(RAMCLK_GATE_D, 0); |
4006 | I915_WRITE(RAMCLK_GATE_D, 0); |
3762 | I915_WRITE16(DEUC, 0); |
4007 | I915_WRITE16(DEUC, 0); |
3763 | } |
4008 | } |
3764 | 4009 | ||
3765 | static void broadwater_init_clock_gating(struct drm_device *dev) |
4010 | static void broadwater_init_clock_gating(struct drm_device *dev) |
3766 | { |
4011 | { |
3767 | struct drm_i915_private *dev_priv = dev->dev_private; |
4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
3768 | 4013 | ||
3769 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
4014 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
3770 | I965_RCC_CLOCK_GATE_DISABLE | |
4015 | I965_RCC_CLOCK_GATE_DISABLE | |
3771 | I965_RCPB_CLOCK_GATE_DISABLE | |
4016 | I965_RCPB_CLOCK_GATE_DISABLE | |
3772 | I965_ISC_CLOCK_GATE_DISABLE | |
4017 | I965_ISC_CLOCK_GATE_DISABLE | |
3773 | I965_FBC_CLOCK_GATE_DISABLE); |
4018 | I965_FBC_CLOCK_GATE_DISABLE); |
3774 | I915_WRITE(RENCLK_GATE_D2, 0); |
4019 | I915_WRITE(RENCLK_GATE_D2, 0); |
3775 | } |
4020 | } |
3776 | 4021 | ||
3777 | static void gen3_init_clock_gating(struct drm_device *dev) |
4022 | static void gen3_init_clock_gating(struct drm_device *dev) |
3778 | { |
4023 | { |
3779 | struct drm_i915_private *dev_priv = dev->dev_private; |
4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
3780 | u32 dstate = I915_READ(D_STATE); |
4025 | u32 dstate = I915_READ(D_STATE); |
3781 | 4026 | ||
3782 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
4027 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
3783 | DSTATE_DOT_CLOCK_GATING; |
4028 | DSTATE_DOT_CLOCK_GATING; |
3784 | I915_WRITE(D_STATE, dstate); |
4029 | I915_WRITE(D_STATE, dstate); |
3785 | 4030 | ||
3786 | if (IS_PINEVIEW(dev)) |
4031 | if (IS_PINEVIEW(dev)) |
3787 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
4032 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
3788 | 4033 | ||
3789 | /* IIR "flip pending" means done if this bit is set */ |
4034 | /* IIR "flip pending" means done if this bit is set */ |
3790 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
4035 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
3791 | } |
4036 | } |
3792 | 4037 | ||
3793 | static void i85x_init_clock_gating(struct drm_device *dev) |
4038 | static void i85x_init_clock_gating(struct drm_device *dev) |
3794 | { |
4039 | { |
3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
4040 | struct drm_i915_private *dev_priv = dev->dev_private; |
3796 | 4041 | ||
3797 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
4042 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
3798 | } |
4043 | } |
3799 | 4044 | ||
3800 | static void i830_init_clock_gating(struct drm_device *dev) |
4045 | static void i830_init_clock_gating(struct drm_device *dev) |
3801 | { |
4046 | { |
3802 | struct drm_i915_private *dev_priv = dev->dev_private; |
4047 | struct drm_i915_private *dev_priv = dev->dev_private; |
3803 | 4048 | ||
3804 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
4049 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
3805 | } |
4050 | } |
3806 | - | ||
3807 | static void ibx_init_clock_gating(struct drm_device *dev) |
- | |
3808 | { |
- | |
3809 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3810 | - | ||
3811 | /* |
- | |
3812 | * On Ibex Peak and Cougar Point, we need to disable clock |
- | |
3813 | * gating for the panel power sequencer or it will fail to |
- | |
3814 | * start up when no ports are active. |
- | |
3815 | */ |
- | |
3816 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
- | |
3817 | } |
- | |
3818 | - | ||
3819 | static void cpt_init_clock_gating(struct drm_device *dev) |
- | |
3820 | { |
- | |
3821 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3822 | int pipe; |
- | |
3823 | - | ||
3824 | /* |
- | |
3825 | * On Ibex Peak and Cougar Point, we need to disable clock |
- | |
3826 | * gating for the panel power sequencer or it will fail to |
- | |
3827 | * start up when no ports are active. |
- | |
3828 | */ |
- | |
3829 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
- | |
3830 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
- | |
3831 | DPLS_EDP_PPS_FIX_DIS); |
- | |
3832 | /* Without this, mode sets may fail silently on FDI */ |
- | |
3833 | for_each_pipe(pipe) |
- | |
3834 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); |
- | |
3835 | } |
- | |
3836 | 4051 | ||
3837 | void intel_init_clock_gating(struct drm_device *dev) |
4052 | void intel_init_clock_gating(struct drm_device *dev) |
3838 | { |
4053 | { |
3839 | struct drm_i915_private *dev_priv = dev->dev_private; |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
3840 | 4055 | ||
3841 | dev_priv->display.init_clock_gating(dev); |
4056 | dev_priv->display.init_clock_gating(dev); |
3842 | - | ||
3843 | if (dev_priv->display.init_pch_clock_gating) |
- | |
3844 | dev_priv->display.init_pch_clock_gating(dev); |
- | |
3845 | } |
4057 | } |
3846 | 4058 | ||
3847 | /* Starting with Haswell, we have different power wells for |
4059 | /* Starting with Haswell, we have different power wells for |
3848 | * different parts of the GPU. This attempts to enable them all. |
4060 | * different parts of the GPU. This attempts to enable them all. |
3849 | */ |
4061 | */ |
3850 | void intel_init_power_wells(struct drm_device *dev) |
4062 | void intel_init_power_wells(struct drm_device *dev) |
3851 | { |
4063 | { |
3852 | struct drm_i915_private *dev_priv = dev->dev_private; |
4064 | struct drm_i915_private *dev_priv = dev->dev_private; |
3853 | unsigned long power_wells[] = { |
4065 | unsigned long power_wells[] = { |
3854 | HSW_PWR_WELL_CTL1, |
4066 | HSW_PWR_WELL_CTL1, |
3855 | HSW_PWR_WELL_CTL2, |
4067 | HSW_PWR_WELL_CTL2, |
3856 | HSW_PWR_WELL_CTL4 |
4068 | HSW_PWR_WELL_CTL4 |
3857 | }; |
4069 | }; |
3858 | int i; |
4070 | int i; |
3859 | 4071 | ||
3860 | if (!IS_HASWELL(dev)) |
4072 | if (!IS_HASWELL(dev)) |
3861 | return; |
4073 | return; |
3862 | 4074 | ||
3863 | mutex_lock(&dev->struct_mutex); |
4075 | mutex_lock(&dev->struct_mutex); |
3864 | 4076 | ||
3865 | for (i = 0; i < ARRAY_SIZE(power_wells); i++) { |
4077 | for (i = 0; i < ARRAY_SIZE(power_wells); i++) { |
3866 | int well = I915_READ(power_wells[i]); |
4078 | int well = I915_READ(power_wells[i]); |
3867 | 4079 | ||
3868 | if ((well & HSW_PWR_WELL_STATE) == 0) { |
4080 | if ((well & HSW_PWR_WELL_STATE) == 0) { |
3869 | I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); |
4081 | I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); |
3870 | if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) |
4082 | if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) |
3871 | DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); |
4083 | DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); |
3872 | } |
4084 | } |
3873 | } |
4085 | } |
3874 | 4086 | ||
3875 | mutex_unlock(&dev->struct_mutex); |
4087 | mutex_unlock(&dev->struct_mutex); |
3876 | } |
4088 | } |
3877 | 4089 | ||
3878 | /* Set up chip specific power management-related functions */ |
4090 | /* Set up chip specific power management-related functions */ |
3879 | void intel_init_pm(struct drm_device *dev) |
4091 | void intel_init_pm(struct drm_device *dev) |
3880 | { |
4092 | { |
3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
4093 | struct drm_i915_private *dev_priv = dev->dev_private; |
3882 | 4094 | ||
3883 | if (I915_HAS_FBC(dev)) { |
4095 | if (I915_HAS_FBC(dev)) { |
3884 | if (HAS_PCH_SPLIT(dev)) { |
4096 | if (HAS_PCH_SPLIT(dev)) { |
3885 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
4097 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
3886 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
4098 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
3887 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
4099 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
3888 | } else if (IS_GM45(dev)) { |
4100 | } else if (IS_GM45(dev)) { |
3889 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
4101 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
3890 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
4102 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
3891 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
4103 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
3892 | } else if (IS_CRESTLINE(dev)) { |
4104 | } else if (IS_CRESTLINE(dev)) { |
3893 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
4105 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
3894 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
4106 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
3895 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
4107 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
3896 | } |
4108 | } |
3897 | /* 855GM needs testing */ |
4109 | /* 855GM needs testing */ |
3898 | } |
4110 | } |
3899 | 4111 | ||
3900 | /* For cxsr */ |
4112 | /* For cxsr */ |
3901 | if (IS_PINEVIEW(dev)) |
4113 | if (IS_PINEVIEW(dev)) |
3902 | i915_pineview_get_mem_freq(dev); |
4114 | i915_pineview_get_mem_freq(dev); |
3903 | else if (IS_GEN5(dev)) |
4115 | else if (IS_GEN5(dev)) |
3904 | i915_ironlake_get_mem_freq(dev); |
4116 | i915_ironlake_get_mem_freq(dev); |
3905 | 4117 | ||
3906 | /* For FIFO watermark updates */ |
4118 | /* For FIFO watermark updates */ |
3907 | if (HAS_PCH_SPLIT(dev)) { |
4119 | if (HAS_PCH_SPLIT(dev)) { |
3908 | if (HAS_PCH_IBX(dev)) |
- | |
3909 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; |
- | |
3910 | else if (HAS_PCH_CPT(dev)) |
- | |
3911 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; |
- | |
3912 | - | ||
3913 | if (IS_GEN5(dev)) { |
4120 | if (IS_GEN5(dev)) { |
3914 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
4121 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
3915 | dev_priv->display.update_wm = ironlake_update_wm; |
4122 | dev_priv->display.update_wm = ironlake_update_wm; |
3916 | else { |
4123 | else { |
3917 | DRM_DEBUG_KMS("Failed to get proper latency. " |
4124 | DRM_DEBUG_KMS("Failed to get proper latency. " |
3918 | "Disable CxSR\n"); |
4125 | "Disable CxSR\n"); |
3919 | dev_priv->display.update_wm = NULL; |
4126 | dev_priv->display.update_wm = NULL; |
3920 | } |
4127 | } |
3921 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
4128 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
3922 | } else if (IS_GEN6(dev)) { |
4129 | } else if (IS_GEN6(dev)) { |
3923 | if (SNB_READ_WM0_LATENCY()) { |
4130 | if (SNB_READ_WM0_LATENCY()) { |
3924 | dev_priv->display.update_wm = sandybridge_update_wm; |
4131 | dev_priv->display.update_wm = sandybridge_update_wm; |
3925 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4132 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
3926 | } else { |
4133 | } else { |
3927 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4134 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
3928 | "Disable CxSR\n"); |
4135 | "Disable CxSR\n"); |
3929 | dev_priv->display.update_wm = NULL; |
4136 | dev_priv->display.update_wm = NULL; |
3930 | } |
4137 | } |
3931 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
4138 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
3932 | } else if (IS_IVYBRIDGE(dev)) { |
4139 | } else if (IS_IVYBRIDGE(dev)) { |
3933 | /* FIXME: detect B0+ stepping and use auto training */ |
4140 | /* FIXME: detect B0+ stepping and use auto training */ |
3934 | if (SNB_READ_WM0_LATENCY()) { |
4141 | if (SNB_READ_WM0_LATENCY()) { |
3935 | dev_priv->display.update_wm = sandybridge_update_wm; |
4142 | dev_priv->display.update_wm = ivybridge_update_wm; |
3936 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4143 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
3937 | } else { |
4144 | } else { |
3938 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4145 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
3939 | "Disable CxSR\n"); |
4146 | "Disable CxSR\n"); |
3940 | dev_priv->display.update_wm = NULL; |
4147 | dev_priv->display.update_wm = NULL; |
3941 | } |
4148 | } |
3942 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
4149 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
3943 | } else if (IS_HASWELL(dev)) { |
4150 | } else if (IS_HASWELL(dev)) { |
3944 | if (SNB_READ_WM0_LATENCY()) { |
4151 | if (SNB_READ_WM0_LATENCY()) { |
3945 | dev_priv->display.update_wm = sandybridge_update_wm; |
4152 | dev_priv->display.update_wm = sandybridge_update_wm; |
3946 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4153 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
3947 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
4154 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
3948 | } else { |
4155 | } else { |
3949 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
4156 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
3950 | "Disable CxSR\n"); |
4157 | "Disable CxSR\n"); |
3951 | dev_priv->display.update_wm = NULL; |
4158 | dev_priv->display.update_wm = NULL; |
3952 | } |
4159 | } |
3953 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
4160 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
3954 | } else |
4161 | } else |
3955 | dev_priv->display.update_wm = NULL; |
4162 | dev_priv->display.update_wm = NULL; |
3956 | } else if (IS_VALLEYVIEW(dev)) { |
4163 | } else if (IS_VALLEYVIEW(dev)) { |
3957 | dev_priv->display.update_wm = valleyview_update_wm; |
4164 | dev_priv->display.update_wm = valleyview_update_wm; |
3958 | dev_priv->display.init_clock_gating = |
4165 | dev_priv->display.init_clock_gating = |
3959 | valleyview_init_clock_gating; |
4166 | valleyview_init_clock_gating; |
3960 | } else if (IS_PINEVIEW(dev)) { |
4167 | } else if (IS_PINEVIEW(dev)) { |
3961 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
4168 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
3962 | dev_priv->is_ddr3, |
4169 | dev_priv->is_ddr3, |
3963 | dev_priv->fsb_freq, |
4170 | dev_priv->fsb_freq, |
3964 | dev_priv->mem_freq)) { |
4171 | dev_priv->mem_freq)) { |
3965 | DRM_INFO("failed to find known CxSR latency " |
4172 | DRM_INFO("failed to find known CxSR latency " |
3966 | "(found ddr%s fsb freq %d, mem freq %d), " |
4173 | "(found ddr%s fsb freq %d, mem freq %d), " |
3967 | "disabling CxSR\n", |
4174 | "disabling CxSR\n", |
3968 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
4175 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
3969 | dev_priv->fsb_freq, dev_priv->mem_freq); |
4176 | dev_priv->fsb_freq, dev_priv->mem_freq); |
3970 | /* Disable CxSR and never update its watermark again */ |
4177 | /* Disable CxSR and never update its watermark again */ |
3971 | pineview_disable_cxsr(dev); |
4178 | pineview_disable_cxsr(dev); |
3972 | dev_priv->display.update_wm = NULL; |
4179 | dev_priv->display.update_wm = NULL; |
3973 | } else |
4180 | } else |
3974 | dev_priv->display.update_wm = pineview_update_wm; |
4181 | dev_priv->display.update_wm = pineview_update_wm; |
3975 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4182 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
3976 | } else if (IS_G4X(dev)) { |
4183 | } else if (IS_G4X(dev)) { |
3977 | dev_priv->display.update_wm = g4x_update_wm; |
4184 | dev_priv->display.update_wm = g4x_update_wm; |
3978 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
4185 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
3979 | } else if (IS_GEN4(dev)) { |
4186 | } else if (IS_GEN4(dev)) { |
3980 | dev_priv->display.update_wm = i965_update_wm; |
4187 | dev_priv->display.update_wm = i965_update_wm; |
3981 | if (IS_CRESTLINE(dev)) |
4188 | if (IS_CRESTLINE(dev)) |
3982 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
4189 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
3983 | else if (IS_BROADWATER(dev)) |
4190 | else if (IS_BROADWATER(dev)) |
3984 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
4191 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
3985 | } else if (IS_GEN3(dev)) { |
4192 | } else if (IS_GEN3(dev)) { |
3986 | dev_priv->display.update_wm = i9xx_update_wm; |
4193 | dev_priv->display.update_wm = i9xx_update_wm; |
3987 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
4194 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
3988 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
4195 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
3989 | } else if (IS_I865G(dev)) { |
4196 | } else if (IS_I865G(dev)) { |
3990 | dev_priv->display.update_wm = i830_update_wm; |
4197 | dev_priv->display.update_wm = i830_update_wm; |
3991 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4198 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
3992 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4199 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
3993 | } else if (IS_I85X(dev)) { |
4200 | } else if (IS_I85X(dev)) { |
3994 | dev_priv->display.update_wm = i9xx_update_wm; |
4201 | dev_priv->display.update_wm = i9xx_update_wm; |
3995 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
4202 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
3996 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
4203 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
3997 | } else { |
4204 | } else { |
3998 | dev_priv->display.update_wm = i830_update_wm; |
4205 | dev_priv->display.update_wm = i830_update_wm; |
3999 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
4206 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
4000 | if (IS_845G(dev)) |
4207 | if (IS_845G(dev)) |
4001 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
4208 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
4002 | else |
4209 | else |
4003 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4210 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
4004 | } |
4211 | } |
4005 | } |
4212 | } |
4006 | 4213 | ||
4007 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
4214 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
4008 | { |
4215 | { |
4009 | u32 gt_thread_status_mask; |
4216 | u32 gt_thread_status_mask; |
4010 | 4217 | ||
4011 | if (IS_HASWELL(dev_priv->dev)) |
4218 | if (IS_HASWELL(dev_priv->dev)) |
4012 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
4219 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
4013 | else |
4220 | else |
4014 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
4221 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
4015 | 4222 | ||
4016 | /* w/a for a sporadic read returning 0 by waiting for the GT |
4223 | /* w/a for a sporadic read returning 0 by waiting for the GT |
4017 | * thread to wake up. |
4224 | * thread to wake up. |
4018 | */ |
4225 | */ |
4019 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
4226 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
4020 | DRM_ERROR("GT thread status wait timed out\n"); |
4227 | DRM_ERROR("GT thread status wait timed out\n"); |
4021 | } |
4228 | } |
- | 4229 | ||
- | 4230 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
|
- | 4231 | { |
|
- | 4232 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
|
- | 4233 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
|
- | 4234 | } |
|
4022 | 4235 | ||
4023 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4236 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4024 | { |
4237 | { |
4025 | u32 forcewake_ack; |
4238 | u32 forcewake_ack; |
4026 | 4239 | ||
4027 | if (IS_HASWELL(dev_priv->dev)) |
4240 | if (IS_HASWELL(dev_priv->dev)) |
4028 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4241 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4029 | else |
4242 | else |
4030 | forcewake_ack = FORCEWAKE_ACK; |
4243 | forcewake_ack = FORCEWAKE_ACK; |
4031 | 4244 | ||
4032 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4245 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4033 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4246 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4034 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4247 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4035 | 4248 | ||
4036 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
4249 | I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); |
4037 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4250 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4038 | 4251 | ||
4039 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4252 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4040 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4253 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4041 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4254 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4042 | 4255 | ||
4043 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4256 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4044 | } |
4257 | } |
- | 4258 | ||
- | 4259 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
|
- | 4260 | { |
|
- | 4261 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
|
- | 4262 | /* something from same cacheline, but !FORCEWAKE_MT */ |
|
- | 4263 | POSTING_READ(ECOBUS); |
|
- | 4264 | } |
|
4045 | 4265 | ||
4046 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
4266 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
4047 | { |
4267 | { |
4048 | u32 forcewake_ack; |
4268 | u32 forcewake_ack; |
4049 | 4269 | ||
4050 | if (IS_HASWELL(dev_priv->dev)) |
4270 | if (IS_HASWELL(dev_priv->dev)) |
4051 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4271 | forcewake_ack = FORCEWAKE_ACK_HSW; |
4052 | else |
4272 | else |
4053 | forcewake_ack = FORCEWAKE_MT_ACK; |
4273 | forcewake_ack = FORCEWAKE_MT_ACK; |
4054 | 4274 | ||
4055 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4275 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, |
4056 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4276 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4057 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4277 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4058 | 4278 | ||
4059 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); |
4279 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
- | 4280 | /* something from same cacheline, but !FORCEWAKE_MT */ |
|
4060 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
4281 | POSTING_READ(ECOBUS); |
4061 | 4282 | ||
4062 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4283 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), |
4063 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4284 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4064 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4285 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4065 | 4286 | ||
4066 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4287 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4067 | } |
4288 | } |
4068 | 4289 | ||
4069 | /* |
4290 | /* |
4070 | * Generally this is called implicitly by the register read function. However, |
4291 | * Generally this is called implicitly by the register read function. However, |
4071 | * if some sequence requires the GT to not power down then this function should |
4292 | * if some sequence requires the GT to not power down then this function should |
4072 | * be called at the beginning of the sequence followed by a call to |
4293 | * be called at the beginning of the sequence followed by a call to |
4073 | * gen6_gt_force_wake_put() at the end of the sequence. |
4294 | * gen6_gt_force_wake_put() at the end of the sequence. |
4074 | */ |
4295 | */ |
4075 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4296 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4076 | { |
4297 | { |
4077 | unsigned long irqflags; |
4298 | unsigned long irqflags; |
4078 | 4299 | ||
4079 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4300 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4080 | if (dev_priv->forcewake_count++ == 0) |
4301 | if (dev_priv->forcewake_count++ == 0) |
4081 | dev_priv->gt.force_wake_get(dev_priv); |
4302 | dev_priv->gt.force_wake_get(dev_priv); |
4082 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4303 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4083 | } |
4304 | } |
4084 | 4305 | ||
4085 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
4306 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
4086 | { |
4307 | { |
4087 | u32 gtfifodbg; |
4308 | u32 gtfifodbg; |
4088 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
4309 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
4089 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
4310 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
4090 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
4311 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
4091 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
4312 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
4092 | } |
4313 | } |
4093 | 4314 | ||
4094 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4315 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4095 | { |
4316 | { |
4096 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4317 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
4097 | /* gen6_gt_check_fifodbg doubles as the POSTING_READ */ |
4318 | /* something from same cacheline, but !FORCEWAKE */ |
- | 4319 | POSTING_READ(ECOBUS); |
|
4098 | gen6_gt_check_fifodbg(dev_priv); |
4320 | gen6_gt_check_fifodbg(dev_priv); |
4099 | } |
4321 | } |
4100 | 4322 | ||
4101 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
4323 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
4102 | { |
4324 | { |
4103 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); |
4325 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4104 | /* gen6_gt_check_fifodbg doubles as the POSTING_READ */ |
4326 | /* something from same cacheline, but !FORCEWAKE_MT */ |
- | 4327 | POSTING_READ(ECOBUS); |
|
4105 | gen6_gt_check_fifodbg(dev_priv); |
4328 | gen6_gt_check_fifodbg(dev_priv); |
4106 | } |
4329 | } |
4107 | 4330 | ||
4108 | /* |
4331 | /* |
4109 | * see gen6_gt_force_wake_get() |
4332 | * see gen6_gt_force_wake_get() |
4110 | */ |
4333 | */ |
4111 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4334 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
4112 | { |
4335 | { |
4113 | unsigned long irqflags; |
4336 | unsigned long irqflags; |
4114 | 4337 | ||
4115 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4338 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
4116 | if (--dev_priv->forcewake_count == 0) |
4339 | if (--dev_priv->forcewake_count == 0) |
4117 | dev_priv->gt.force_wake_put(dev_priv); |
4340 | dev_priv->gt.force_wake_put(dev_priv); |
4118 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4341 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
4119 | } |
4342 | } |
4120 | 4343 | ||
4121 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
4344 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
4122 | { |
4345 | { |
4123 | int ret = 0; |
4346 | int ret = 0; |
4124 | 4347 | ||
4125 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
4348 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
4126 | int loop = 500; |
4349 | int loop = 500; |
4127 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4350 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4128 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
4351 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
4129 | udelay(10); |
4352 | udelay(10); |
4130 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4353 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
4131 | } |
4354 | } |
4132 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
4355 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
4133 | ++ret; |
4356 | ++ret; |
4134 | dev_priv->gt_fifo_count = fifo; |
4357 | dev_priv->gt_fifo_count = fifo; |
4135 | } |
4358 | } |
4136 | dev_priv->gt_fifo_count--; |
4359 | dev_priv->gt_fifo_count--; |
4137 | 4360 | ||
4138 | return ret; |
4361 | return ret; |
4139 | } |
4362 | } |
- | 4363 | ||
- | 4364 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
|
- | 4365 | { |
|
- | 4366 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); |
|
- | 4367 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
|
- | 4368 | POSTING_READ(FORCEWAKE_ACK_VLV); |
|
- | 4369 | } |
|
4140 | 4370 | ||
4141 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
4371 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
4142 | { |
4372 | { |
4143 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, |
4373 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, |
4144 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4374 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4145 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4375 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
4146 | 4376 | ||
4147 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(1)); |
4377 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
4148 | 4378 | ||
4149 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), |
4379 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), |
4150 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4380 | FORCEWAKE_ACK_TIMEOUT_MS)) |
4151 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4381 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
4152 | 4382 | ||
4153 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4383 | __gen6_gt_wait_for_thread_c0(dev_priv); |
4154 | } |
4384 | } |
4155 | 4385 | ||
4156 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
4386 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
4157 | { |
4387 | { |
4158 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(1)); |
4388 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
4159 | /* The below doubles as a POSTING_READ */ |
4389 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
- | 4390 | POSTING_READ(FORCEWAKE_ACK_VLV); |
|
4160 | gen6_gt_check_fifodbg(dev_priv); |
4391 | gen6_gt_check_fifodbg(dev_priv); |
4161 | } |
4392 | } |
- | 4393 | ||
- | 4394 | void intel_gt_reset(struct drm_device *dev) |
|
- | 4395 | { |
|
- | 4396 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4397 | ||
- | 4398 | if (IS_VALLEYVIEW(dev)) { |
|
- | 4399 | vlv_force_wake_reset(dev_priv); |
|
- | 4400 | } else if (INTEL_INFO(dev)->gen >= 6) { |
|
- | 4401 | __gen6_gt_force_wake_reset(dev_priv); |
|
- | 4402 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
|
- | 4403 | __gen6_gt_force_wake_mt_reset(dev_priv); |
|
- | 4404 | } |
|
- | 4405 | } |
|
4162 | 4406 | ||
4163 | void intel_gt_init(struct drm_device *dev) |
4407 | void intel_gt_init(struct drm_device *dev) |
4164 | { |
4408 | { |
4165 | struct drm_i915_private *dev_priv = dev->dev_private; |
4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
4166 | 4410 | ||
4167 | spin_lock_init(&dev_priv->gt_lock); |
4411 | spin_lock_init(&dev_priv->gt_lock); |
- | 4412 | ||
- | 4413 | intel_gt_reset(dev); |
|
4168 | 4414 | ||
4169 | if (IS_VALLEYVIEW(dev)) { |
4415 | if (IS_VALLEYVIEW(dev)) { |
4170 | dev_priv->gt.force_wake_get = vlv_force_wake_get; |
4416 | dev_priv->gt.force_wake_get = vlv_force_wake_get; |
4171 | dev_priv->gt.force_wake_put = vlv_force_wake_put; |
4417 | dev_priv->gt.force_wake_put = vlv_force_wake_put; |
- | 4418 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
|
- | 4419 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; |
|
- | 4420 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; |
|
4172 | } else if (INTEL_INFO(dev)->gen >= 6) { |
4421 | } else if (IS_GEN6(dev)) { |
4173 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4422 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4174 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
4423 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; |
- | 4424 | } |
|
- | 4425 | } |
|
4175 | 4426 | ||
4176 | /* IVB configs may use multi-threaded forcewake */ |
- | |
4177 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
- | |
4178 | u32 ecobus; |
4427 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4179 | - | ||
4180 | /* A small trick here - if the bios hasn't configured |
- | |
4181 | * MT forcewake, and if the device is in RC6, then |
- | |
4182 | * force_wake_mt_get will not wake the device and the |
- | |
4183 | * ECOBUS read will return zero. Which will be |
- | |
4184 | * (correctly) interpreted by the test below as MT |
- | |
4185 | * forcewake being disabled. |
- | |
4186 | */ |
- | |
4187 | mutex_lock(&dev->struct_mutex); |
- | |
4188 | __gen6_gt_force_wake_mt_get(dev_priv); |
- | |
4189 | ecobus = I915_READ_NOTRACE(ECOBUS); |
- | |
4190 | __gen6_gt_force_wake_mt_put(dev_priv); |
4428 | { |
4191 | mutex_unlock(&dev->struct_mutex); |
4429 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
4192 | 4430 | ||
4193 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
- | |
4194 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); |
- | |
4195 | dev_priv->gt.force_wake_get = |
- | |
4196 | __gen6_gt_force_wake_mt_get; |
4431 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
4197 | dev_priv->gt.force_wake_put = |
4432 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
- | 4433 | return -EAGAIN; |
|
- | 4434 | } |
|
- | 4435 | ||
- | 4436 | I915_WRITE(GEN6_PCODE_DATA, *val); |
|
- | 4437 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
|
- | 4438 | ||
- | 4439 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 4440 | 500)) { |
|
4198 | __gen6_gt_force_wake_mt_put; |
4441 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
- | 4442 | return -ETIMEDOUT; |
|
- | 4443 | } |
|
- | 4444 | ||
- | 4445 | *val = I915_READ(GEN6_PCODE_DATA); |
|
- | 4446 | I915_WRITE(GEN6_PCODE_DATA, 0); |
|
- | 4447 | ||
- | 4448 | return 0; |
|
- | 4449 | } |
|
- | 4450 | ||
- | 4451 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
|
- | 4452 | { |
|
- | 4453 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
|
- | 4454 | ||
- | 4455 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
|
4199 | } |
4456 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
- | 4457 | return -EAGAIN; |
|
- | 4458 | } |
|
- | 4459 | ||
- | 4460 | I915_WRITE(GEN6_PCODE_DATA, val); |
|
- | 4461 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
|
- | 4462 | ||
- | 4463 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 4464 | 500)) { |
|
4200 | } |
4465 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
- | 4466 | return -ETIMEDOUT; |
|
- | 4467 | } |
|
- | 4468 | ||
- | 4469 | I915_WRITE(GEN6_PCODE_DATA, 0); |
|
4201 | } |
4470 | |
4202 | }=>>=>>>><>><>>><>><>><>>>>>>>>>>=> |
4471 | return 0; |
4203 | >< |
4472 | }=>>=>>>><>><>>><>><>><>>>>>>>>>>=> |
4204 | > |
4473 | >< |
4205 | >< |
4474 | > |
4206 | >><>><>><>><>>> |
4475 | >< |
- | 4476 | >><>><>><>><>>> |