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#ifndef _INTEL_LRC_H_
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define GEN8_LR_CONTEXT_ALIGN 4096
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_LR_CONTEXT_ALIGN 4096
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#define GEN8_CSB_PTR_MASK 0x07
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/* Execlists regs */
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/* Execlists regs */
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#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
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#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
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#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
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#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
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#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
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#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
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#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
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#define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)
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#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
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#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
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#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
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#define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
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#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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/* Logical Rings */
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
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int intel_logical_rings_init(struct drm_device *dev);
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int intel_logical_rings_init(struct drm_device *dev);
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int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
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int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf);
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void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf);
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int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
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					   u32 data)
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					   u32 data)
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{
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{
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	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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	ringbuf->tail += 4;
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	ringbuf->tail += 4;
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}
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}
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int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords);
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/* Logical Ring Contexts */
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/* Logical Ring Contexts */
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/* One extra page is added before LRC for GuC as shared data */
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#define LRC_GUCSHR_PN	(0)
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int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
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#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + 1)
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#define LRC_STATE_PN	(LRC_PPHWSP_PN + 1)
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				       struct intel_context *ctx);
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void intel_lr_context_free(struct intel_context *ctx);
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void intel_lr_context_free(struct intel_context *ctx);
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int intel_lr_context_deferred_create(struct intel_context *ctx,
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int intel_lr_context_deferred_alloc(struct intel_context *ctx,
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				     struct intel_engine_cs *ring);
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				    struct intel_engine_cs *ring);
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void intel_lr_context_unpin(struct drm_i915_gem_request *req);
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void intel_lr_context_unpin(struct intel_engine_cs *ring,
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void intel_lr_context_reset(struct drm_device *dev,
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			struct intel_context *ctx);
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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
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		struct intel_context *ctx);
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				     struct intel_engine_cs *ring);
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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/* Execlists */
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int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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			       struct intel_engine_cs *ring,
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struct i915_execbuffer_params;
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			       struct intel_context *ctx,
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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			       struct drm_i915_gem_execbuffer2 *args,
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			       struct list_head *vmas,
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			       struct drm_i915_gem_object *batch_obj,
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			       struct drm_i915_gem_execbuffer2 *args,
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			       u64 exec_start, u32 flags);
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
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/**
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 * struct intel_ctx_submit_request - queued context submission request
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 * @ctx: Context to submit to the ELSP.
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 * @ring: Engine to submit it to.
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 * @tail: how far in the context's ringbuffer this request goes to.
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 * @execlist_link: link in the submission queue.
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 * @work: workqueue for processing this request in a bottom half.
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 * @elsp_submitted: no. of times this request has been sent to the ELSP.
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 *
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 * The ELSP only accepts two elements at a time, so we queue context/tail
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 * pairs on a given queue (ring->execlist_queue) until the hardware is
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 * available. The queue serves a double purpose: we also use it to keep track
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 * of the up to 2 contexts currently in the hardware (usually one in execution
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 * and the other queued up by the GPU): We only remove elements from the head
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 * of the queue when the hardware informs us that an element has been
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 * completed.
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 *
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 * All accesses to the queue are mediated by a spinlock (ring->execlist_lock).
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 */
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struct intel_ctx_submit_request {
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	struct intel_context *ctx;
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	struct intel_engine_cs *ring;
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	u32 tail;
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	struct list_head execlist_link;
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	int elsp_submitted;
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			       struct list_head *vmas);
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};
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
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