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	/* Important: The hw handles only the first bit, so set only one! Since

	/* Important: The hw handles only the first bit, so set only one! Since

	 * we also need to check for NAKs besides the hw ready/idle signal, we

	 * we also need to check for NAKs besides the hw ready/idle signal, we

	 * need to wake up periodically and check that ourselves. */

	 * need to wake up periodically and check that ourselves. */

	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);

	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);

	for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {

	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {

		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,

		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,

				TASK_UNINTERRUPTIBLE);

				TASK_UNINTERRUPTIBLE);

		return wait_for(C, 10);

		return wait_for(C, 10);

	/* Important: The hw handles only the first bit, so set only one! */

	/* Important: The hw handles only the first bit, so set only one! */

	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,

	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);

				 msecs_to_jiffies_timeout(10));

int intel_setup_gmbus(struct drm_device *dev)

int intel_setup_gmbus(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret, i;

	int ret, i;

	if (HAS_PCH_SPLIT(dev))

	else if (HAS_PCH_SPLIT(dev))

		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;

		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;

	else if (IS_VALLEYVIEW(dev))

	else if (IS_VALLEYVIEW(dev))

		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;

		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;

	else

	else