WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_i2c.c

 void
 intel_i2c_reset(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
+	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
+}
 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
+{
 	algo->udelay = I2C_RISEFALL_TIME;
 	algo->timeout = usecs_to_jiffies(2200);
 	algo->data = bus;
+}
+/*
+ * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
+ * mode. This results in spurious interrupt warnings if the legacy irq no. is
+ * shared with another device. The kernel then disables that interrupt source
+ * and so prevents the other device from working properly.
+ */
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
+static int
+gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
+		     u32 gmbus2_status,
+		     u32 gmbus4_irq_en)
+{
+	int i;
+	int reg_offset = dev_priv->gpio_mmio_base;
+	u32 gmbus2 = 0;
+	DEFINE_WAIT(wait);
+	if (!HAS_GMBUS_IRQ(dev_priv->dev))
+		gmbus4_irq_en = 0;
+	/* Important: The hw handles only the first bit, so set only one! Since
+	 * we also need to check for NAKs besides the hw ready/idle signal, we
+	 * need to wake up periodically and check that ourselves. */
+	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
+	for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
+		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
+				TASK_UNINTERRUPTIBLE);
+		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
+		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
+			break;
+		schedule_timeout(1);
+	}
+	finish_wait(&dev_priv->gmbus_wait_queue, &wait);
+	I915_WRITE(GMBUS4 + reg_offset, 0);
+	if (gmbus2 & GMBUS_SATOER)
+		return -ENXIO;
+	if (gmbus2 & gmbus2_status)
+		return 0;
+	return -ETIMEDOUT;
+}
+static int
+gmbus_wait_idle(struct drm_i915_private *dev_priv)
+{
+	int ret;
+	int reg_offset = dev_priv->gpio_mmio_base;
+#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
+	if (!HAS_GMBUS_IRQ(dev_priv->dev))
+		return wait_for(C, 10);
+	/* Important: The hw handles only the first bit, so set only one! */
+	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
+	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
+	I915_WRITE(GMBUS4 + reg_offset, 0);
+	if (ret)
+		return 0;
+	else
+		return -ETIMEDOUT;
+#undef C
+}
 static int
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 		u32 gmbus1_index)
+{
 		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 	while (len) {
 		int ret;
 		u32 val, loop = 0;
-		u32 gmbus2;
-		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
+		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
-			       (GMBUS_SATOER | GMBUS_HW_RDY),
-);
+					   GMBUS_HW_RDY_EN);
-		if (ret)
-			return -ETIMEDOUT;
-		if (gmbus2 & GMBUS_SATOER)
+		if (ret)
-			return -ENXIO;
+			return ret;
 		val = I915_READ(GMBUS3 + reg_offset);
 		do {
 		   (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
 		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 	while (len) {
 		int ret;
-		u32 gmbus2;
 		val = loop = 0;
 		do {
 			val |= *buf++ << (8 * loop);
 		} while (--len && ++loop < 4);
 		I915_WRITE(GMBUS3 + reg_offset, val);
 		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
-			       (GMBUS_SATOER | GMBUS_HW_RDY),
-);
-		if (ret)
+		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
-			return -ETIMEDOUT;
+					   GMBUS_HW_RDY_EN);
-		if (gmbus2 & GMBUS_SATOER)
+		if (ret)
-			return -ENXIO;
+			return ret;
+	}
 	reg_offset = dev_priv->gpio_mmio_base;
 	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
-	for (i = 0; i < num; i++) {
 		u32 gmbus2;
 	for (i = 0; i < num; i++) {
 		if (gmbus_is_index_read(msgs, i, num)) {
 			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 			i += 1;  /* set i to the index of the read xfer */
 		if (ret == -ETIMEDOUT)
 			goto timeout;
 		if (ret == -ENXIO)
 			goto clear_err;
-		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
+		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
+					   GMBUS_HW_WAIT_EN);
-			       (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
+		if (ret == -ENXIO)
-);
+			goto clear_err;
 		if (ret)
-			goto timeout;
-		if (gmbus2 & GMBUS_SATOER)
-			goto clear_err;
+			goto timeout;
+	}
 	/* Generate a STOP condition on the bus. Note that gmbus can't generata
 	/* Mark the GMBUS interface as disabled after waiting for idle.
 	 * We will re-enable it at the start of the next xfer,
 	 * till then let it sleep.
 	 */
-	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
-)) {
+	if (gmbus_wait_idle(dev_priv)) {
 		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 			 adapter->name);
 		ret = -ETIMEDOUT;
+	}
 	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
 	 * timing out seems to happen when there _is_ a ddc chip present, but
 	 * it's slow responding and only answers on the 2nd retry.
 	 */
 	ret = -ENXIO;
-	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
+	if (gmbus_wait_idle(dev_priv)) {
-)) {
 		DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 			      adapter->name);
 		ret = -ETIMEDOUT;
+	}
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret, i;
 	if (HAS_PCH_SPLIT(dev))
+		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
+	else if (IS_VALLEYVIEW(dev))
-		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
+		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else
 		dev_priv->gpio_mmio_base = 0;
 	mutex_init(&dev_priv->gmbus_mutex);
-	mutex_init(&dev_priv->gmbus_mutex);
+	init_waitqueue_head(&dev_priv->gmbus_wait_queue);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_i2c.c – Rev 3243 → 3480