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Rev 3243 | Rev 3480 | ||
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Line 61... | Line 61... | ||
61 | void |
61 | void |
62 | intel_i2c_reset(struct drm_device *dev) |
62 | intel_i2c_reset(struct drm_device *dev) |
63 | { |
63 | { |
64 | struct drm_i915_private *dev_priv = dev->dev_private; |
64 | struct drm_i915_private *dev_priv = dev->dev_private; |
65 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
65 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
- | 66 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); |
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66 | } |
67 | } |
Line 67... | Line 68... | ||
67 | 68 | ||
68 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
69 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
69 | { |
70 | { |
Line 200... | Line 201... | ||
200 | algo->udelay = I2C_RISEFALL_TIME; |
201 | algo->udelay = I2C_RISEFALL_TIME; |
201 | algo->timeout = usecs_to_jiffies(2200); |
202 | algo->timeout = usecs_to_jiffies(2200); |
202 | algo->data = bus; |
203 | algo->data = bus; |
203 | } |
204 | } |
Line -... | Line 205... | ||
- | 205 | ||
- | 206 | /* |
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- | 207 | * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI |
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- | 208 | * mode. This results in spurious interrupt warnings if the legacy irq no. is |
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- | 209 | * shared with another device. The kernel then disables that interrupt source |
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- | 210 | * and so prevents the other device from working properly. |
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- | 211 | */ |
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- | 212 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
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- | 213 | static int |
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- | 214 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
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- | 215 | u32 gmbus2_status, |
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- | 216 | u32 gmbus4_irq_en) |
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- | 217 | { |
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- | 218 | int i; |
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- | 219 | int reg_offset = dev_priv->gpio_mmio_base; |
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- | 220 | u32 gmbus2 = 0; |
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- | 221 | DEFINE_WAIT(wait); |
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- | 222 | ||
- | 223 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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- | 224 | gmbus4_irq_en = 0; |
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- | 225 | ||
- | 226 | /* Important: The hw handles only the first bit, so set only one! Since |
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- | 227 | * we also need to check for NAKs besides the hw ready/idle signal, we |
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- | 228 | * need to wake up periodically and check that ourselves. */ |
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- | 229 | I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); |
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- | 230 | ||
- | 231 | for (i = 0; i < msecs_to_jiffies(50) + 1; i++) { |
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- | 232 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
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- | 233 | TASK_UNINTERRUPTIBLE); |
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- | 234 | ||
- | 235 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
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- | 236 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
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- | 237 | break; |
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- | 238 | ||
- | 239 | schedule_timeout(1); |
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- | 240 | } |
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- | 241 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
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- | 242 | ||
- | 243 | I915_WRITE(GMBUS4 + reg_offset, 0); |
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- | 244 | ||
- | 245 | if (gmbus2 & GMBUS_SATOER) |
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- | 246 | return -ENXIO; |
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- | 247 | if (gmbus2 & gmbus2_status) |
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- | 248 | return 0; |
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- | 249 | return -ETIMEDOUT; |
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- | 250 | } |
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- | 251 | ||
- | 252 | static int |
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- | 253 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
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- | 254 | { |
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- | 255 | int ret; |
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- | 256 | int reg_offset = dev_priv->gpio_mmio_base; |
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- | 257 | ||
- | 258 | #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) |
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- | 259 | ||
- | 260 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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- | 261 | return wait_for(C, 10); |
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- | 262 | ||
- | 263 | /* Important: The hw handles only the first bit, so set only one! */ |
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- | 264 | I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); |
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- | 265 | ||
- | 266 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); |
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- | 267 | ||
- | 268 | I915_WRITE(GMBUS4 + reg_offset, 0); |
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- | 269 | ||
- | 270 | if (ret) |
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- | 271 | return 0; |
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- | 272 | else |
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- | 273 | return -ETIMEDOUT; |
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- | 274 | #undef C |
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- | 275 | } |
|
204 | 276 | ||
205 | static int |
277 | static int |
206 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
278 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
207 | u32 gmbus1_index) |
279 | u32 gmbus1_index) |
208 | { |
280 | { |
Line 217... | Line 289... | ||
217 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
289 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
218 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
290 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
219 | while (len) { |
291 | while (len) { |
220 | int ret; |
292 | int ret; |
221 | u32 val, loop = 0; |
293 | u32 val, loop = 0; |
222 | u32 gmbus2; |
- | |
Line 223... | Line 294... | ||
223 | 294 | ||
224 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
295 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
225 | (GMBUS_SATOER | GMBUS_HW_RDY), |
- | |
226 | 50); |
296 | GMBUS_HW_RDY_EN); |
227 | if (ret) |
- | |
228 | return -ETIMEDOUT; |
- | |
229 | if (gmbus2 & GMBUS_SATOER) |
297 | if (ret) |
Line 230... | Line 298... | ||
230 | return -ENXIO; |
298 | return ret; |
231 | 299 | ||
232 | val = I915_READ(GMBUS3 + reg_offset); |
300 | val = I915_READ(GMBUS3 + reg_offset); |
233 | do { |
301 | do { |
Line 259... | Line 327... | ||
259 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
327 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
260 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
328 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
261 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
329 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
262 | while (len) { |
330 | while (len) { |
263 | int ret; |
331 | int ret; |
264 | u32 gmbus2; |
- | |
Line 265... | Line 332... | ||
265 | 332 | ||
266 | val = loop = 0; |
333 | val = loop = 0; |
267 | do { |
334 | do { |
268 | val |= *buf++ << (8 * loop); |
335 | val |= *buf++ << (8 * loop); |
Line 269... | Line 336... | ||
269 | } while (--len && ++loop < 4); |
336 | } while (--len && ++loop < 4); |
Line 270... | Line 337... | ||
270 | 337 | ||
271 | I915_WRITE(GMBUS3 + reg_offset, val); |
338 | I915_WRITE(GMBUS3 + reg_offset, val); |
272 | - | ||
273 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
339 | |
274 | (GMBUS_SATOER | GMBUS_HW_RDY), |
- | |
275 | 50); |
- | |
276 | if (ret) |
340 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
277 | return -ETIMEDOUT; |
341 | GMBUS_HW_RDY_EN); |
278 | if (gmbus2 & GMBUS_SATOER) |
342 | if (ret) |
279 | return -ENXIO; |
343 | return ret; |
Line 280... | Line 344... | ||
280 | } |
344 | } |
Line 343... | Line 407... | ||
343 | reg_offset = dev_priv->gpio_mmio_base; |
407 | reg_offset = dev_priv->gpio_mmio_base; |
Line 344... | Line 408... | ||
344 | 408 | ||
Line 345... | Line 409... | ||
345 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
409 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
346 | - | ||
347 | for (i = 0; i < num; i++) { |
- | |
348 | u32 gmbus2; |
410 | |
349 | 411 | for (i = 0; i < num; i++) { |
|
350 | if (gmbus_is_index_read(msgs, i, num)) { |
412 | if (gmbus_is_index_read(msgs, i, num)) { |
351 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
413 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
352 | i += 1; /* set i to the index of the read xfer */ |
414 | i += 1; /* set i to the index of the read xfer */ |
Line 359... | Line 421... | ||
359 | if (ret == -ETIMEDOUT) |
421 | if (ret == -ETIMEDOUT) |
360 | goto timeout; |
422 | goto timeout; |
361 | if (ret == -ENXIO) |
423 | if (ret == -ENXIO) |
362 | goto clear_err; |
424 | goto clear_err; |
Line 363... | Line 425... | ||
363 | 425 | ||
364 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
426 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
- | 427 | GMBUS_HW_WAIT_EN); |
|
365 | (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), |
428 | if (ret == -ENXIO) |
366 | 50); |
429 | goto clear_err; |
367 | if (ret) |
430 | if (ret) |
368 | goto timeout; |
- | |
369 | if (gmbus2 & GMBUS_SATOER) |
- | |
370 | goto clear_err; |
431 | goto timeout; |
Line 371... | Line 432... | ||
371 | } |
432 | } |
372 | 433 | ||
373 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
434 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
Line 378... | Line 439... | ||
378 | 439 | ||
379 | /* Mark the GMBUS interface as disabled after waiting for idle. |
440 | /* Mark the GMBUS interface as disabled after waiting for idle. |
380 | * We will re-enable it at the start of the next xfer, |
441 | * We will re-enable it at the start of the next xfer, |
381 | * till then let it sleep. |
442 | * till then let it sleep. |
382 | */ |
443 | */ |
383 | if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, |
- | |
384 | 10)) { |
444 | if (gmbus_wait_idle(dev_priv)) { |
385 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
445 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
386 | adapter->name); |
446 | adapter->name); |
387 | ret = -ETIMEDOUT; |
447 | ret = -ETIMEDOUT; |
388 | } |
448 | } |
Line 403... | Line 463... | ||
403 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
463 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
404 | * timing out seems to happen when there _is_ a ddc chip present, but |
464 | * timing out seems to happen when there _is_ a ddc chip present, but |
405 | * it's slow responding and only answers on the 2nd retry. |
465 | * it's slow responding and only answers on the 2nd retry. |
406 | */ |
466 | */ |
407 | ret = -ENXIO; |
467 | ret = -ENXIO; |
408 | if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, |
468 | if (gmbus_wait_idle(dev_priv)) { |
409 | 10)) { |
- | |
410 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
469 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
411 | adapter->name); |
470 | adapter->name); |
412 | ret = -ETIMEDOUT; |
471 | ret = -ETIMEDOUT; |
413 | } |
472 | } |
Line 463... | Line 522... | ||
463 | struct drm_i915_private *dev_priv = dev->dev_private; |
522 | struct drm_i915_private *dev_priv = dev->dev_private; |
464 | int ret, i; |
523 | int ret, i; |
Line 465... | Line 524... | ||
465 | 524 | ||
466 | if (HAS_PCH_SPLIT(dev)) |
525 | if (HAS_PCH_SPLIT(dev)) |
- | 526 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
|
- | 527 | else if (IS_VALLEYVIEW(dev)) |
|
467 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
528 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
468 | else |
529 | else |
Line 469... | Line 530... | ||
469 | dev_priv->gpio_mmio_base = 0; |
530 | dev_priv->gpio_mmio_base = 0; |
- | 531 | ||
Line 470... | Line 532... | ||
470 | 532 | mutex_init(&dev_priv->gmbus_mutex); |
|
471 | mutex_init(&dev_priv->gmbus_mutex); |
533 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
472 | 534 |