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Rev 6935 | Rev 6937 | ||
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Line 76... | Line 76... | ||
76 | case HDMI_INFOFRAME_TYPE_SPD: |
76 | case HDMI_INFOFRAME_TYPE_SPD: |
77 | return VIDEO_DIP_SELECT_SPD; |
77 | return VIDEO_DIP_SELECT_SPD; |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; |
79 | return VIDEO_DIP_SELECT_VENDOR; |
80 | default: |
80 | default: |
81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
81 | MISSING_CASE(type); |
82 | return 0; |
82 | return 0; |
83 | } |
83 | } |
84 | } |
84 | } |
Line 85... | Line 85... | ||
85 | 85 | ||
Line 91... | Line 91... | ||
91 | case HDMI_INFOFRAME_TYPE_SPD: |
91 | case HDMI_INFOFRAME_TYPE_SPD: |
92 | return VIDEO_DIP_ENABLE_SPD; |
92 | return VIDEO_DIP_ENABLE_SPD; |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; |
94 | return VIDEO_DIP_ENABLE_VENDOR; |
95 | default: |
95 | default: |
96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
96 | MISSING_CASE(type); |
97 | return 0; |
97 | return 0; |
98 | } |
98 | } |
99 | } |
99 | } |
Line 100... | Line 100... | ||
100 | 100 | ||
Line 106... | Line 106... | ||
106 | case HDMI_INFOFRAME_TYPE_SPD: |
106 | case HDMI_INFOFRAME_TYPE_SPD: |
107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; |
109 | return VIDEO_DIP_ENABLE_VS_HSW; |
110 | default: |
110 | default: |
111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
111 | MISSING_CASE(type); |
112 | return 0; |
112 | return 0; |
113 | } |
113 | } |
114 | } |
114 | } |
Line -... | Line 115... | ||
- | 115 | ||
115 | 116 | static i915_reg_t |
|
116 | static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, |
117 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, |
117 | enum transcoder cpu_transcoder, |
118 | enum transcoder cpu_transcoder, |
118 | enum hdmi_infoframe_type type, |
119 | enum hdmi_infoframe_type type, |
119 | int i) |
120 | int i) |
120 | { |
121 | { |
Line 124... | Line 125... | ||
124 | case HDMI_INFOFRAME_TYPE_SPD: |
125 | case HDMI_INFOFRAME_TYPE_SPD: |
125 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
126 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
126 | case HDMI_INFOFRAME_TYPE_VENDOR: |
127 | case HDMI_INFOFRAME_TYPE_VENDOR: |
127 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
128 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
128 | default: |
129 | default: |
129 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
130 | MISSING_CASE(type); |
130 | return 0; |
131 | return INVALID_MMIO_REG; |
131 | } |
132 | } |
132 | } |
133 | } |
Line 133... | Line 134... | ||
133 | 134 | ||
134 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
135 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
Line 166... | Line 167... | ||
166 | 167 | ||
167 | I915_WRITE(VIDEO_DIP_CTL, val); |
168 | I915_WRITE(VIDEO_DIP_CTL, val); |
168 | POSTING_READ(VIDEO_DIP_CTL); |
169 | POSTING_READ(VIDEO_DIP_CTL); |
Line 169... | Line 170... | ||
169 | } |
170 | } |
- | 171 | ||
170 | 172 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
|
171 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
- | |
172 | { |
173 | const struct intel_crtc_state *pipe_config) |
173 | struct drm_device *dev = encoder->dev; |
174 | { |
174 | struct drm_i915_private *dev_priv = dev->dev_private; |
175 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
Line 175... | Line 176... | ||
175 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
176 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
176 | u32 val = I915_READ(VIDEO_DIP_CTL); |
177 | u32 val = I915_READ(VIDEO_DIP_CTL); |
Line 191... | Line 192... | ||
191 | { |
192 | { |
192 | const uint32_t *data = frame; |
193 | const uint32_t *data = frame; |
193 | struct drm_device *dev = encoder->dev; |
194 | struct drm_device *dev = encoder->dev; |
194 | struct drm_i915_private *dev_priv = dev->dev_private; |
195 | struct drm_i915_private *dev_priv = dev->dev_private; |
195 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
196 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
196 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
197 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
197 | u32 val = I915_READ(reg); |
198 | u32 val = I915_READ(reg); |
- | 199 | int i; |
|
Line 198... | Line 200... | ||
198 | 200 | ||
Line 199... | Line 201... | ||
199 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
201 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
200 | 202 | ||
Line 221... | Line 223... | ||
221 | 223 | ||
222 | I915_WRITE(reg, val); |
224 | I915_WRITE(reg, val); |
223 | POSTING_READ(reg); |
225 | POSTING_READ(reg); |
Line 224... | Line 226... | ||
224 | } |
226 | } |
- | 227 | ||
225 | 228 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
|
226 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
- | |
227 | { |
229 | const struct intel_crtc_state *pipe_config) |
228 | struct drm_device *dev = encoder->dev; |
- | |
229 | struct drm_i915_private *dev_priv = dev->dev_private; |
230 | { |
- | 231 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
|
230 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
232 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
231 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
233 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
Line 232... | Line 234... | ||
232 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
234 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); |
233 | u32 val = I915_READ(reg); |
235 | u32 val = I915_READ(reg); |
Line 249... | Line 251... | ||
249 | { |
251 | { |
250 | const uint32_t *data = frame; |
252 | const uint32_t *data = frame; |
251 | struct drm_device *dev = encoder->dev; |
253 | struct drm_device *dev = encoder->dev; |
252 | struct drm_i915_private *dev_priv = dev->dev_private; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
254 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
256 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
255 | u32 val = I915_READ(reg); |
257 | u32 val = I915_READ(reg); |
- | 258 | int i; |
|
Line 256... | Line 259... | ||
256 | 259 | ||
Line 257... | Line 260... | ||
257 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
258 | 261 | ||
Line 282... | Line 285... | ||
282 | 285 | ||
283 | I915_WRITE(reg, val); |
286 | I915_WRITE(reg, val); |
284 | POSTING_READ(reg); |
287 | POSTING_READ(reg); |
Line 285... | Line 288... | ||
285 | } |
288 | } |
- | 289 | ||
286 | 290 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
|
287 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
- | |
288 | { |
291 | const struct intel_crtc_state *pipe_config) |
289 | struct drm_device *dev = encoder->dev; |
292 | { |
290 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
291 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
293 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
Line 292... | Line 294... | ||
292 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
294 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
293 | u32 val = I915_READ(reg); |
295 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); |
Line 294... | Line 296... | ||
294 | 296 | ||
Line 306... | Line 308... | ||
306 | { |
308 | { |
307 | const uint32_t *data = frame; |
309 | const uint32_t *data = frame; |
308 | struct drm_device *dev = encoder->dev; |
310 | struct drm_device *dev = encoder->dev; |
309 | struct drm_i915_private *dev_priv = dev->dev_private; |
311 | struct drm_i915_private *dev_priv = dev->dev_private; |
310 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
312 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
311 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
313 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
312 | u32 val = I915_READ(reg); |
314 | u32 val = I915_READ(reg); |
- | 315 | int i; |
|
Line 313... | Line 316... | ||
313 | 316 | ||
Line 314... | Line 317... | ||
314 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
317 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
315 | 318 | ||
Line 336... | Line 339... | ||
336 | 339 | ||
337 | I915_WRITE(reg, val); |
340 | I915_WRITE(reg, val); |
338 | POSTING_READ(reg); |
341 | POSTING_READ(reg); |
Line 339... | Line 342... | ||
339 | } |
342 | } |
- | 343 | ||
340 | 344 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
|
341 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
- | |
342 | { |
345 | const struct intel_crtc_state *pipe_config) |
343 | struct drm_device *dev = encoder->dev; |
- | |
344 | struct drm_i915_private *dev_priv = dev->dev_private; |
346 | { |
345 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
347 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
346 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
348 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
Line 347... | Line 349... | ||
347 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
349 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
348 | u32 val = I915_READ(reg); |
350 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); |
Line 349... | Line 351... | ||
349 | 351 | ||
Line 365... | Line 367... | ||
365 | const uint32_t *data = frame; |
367 | const uint32_t *data = frame; |
366 | struct drm_device *dev = encoder->dev; |
368 | struct drm_device *dev = encoder->dev; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; |
369 | struct drm_i915_private *dev_priv = dev->dev_private; |
368 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
370 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
369 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
371 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
370 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
372 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
371 | u32 data_reg; |
373 | i915_reg_t data_reg; |
372 | int i; |
374 | int i; |
373 | u32 val = I915_READ(ctl_reg); |
375 | u32 val = I915_READ(ctl_reg); |
Line 374... | Line 376... | ||
374 | 376 | ||
375 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
- | |
376 | if (data_reg == 0) |
- | |
Line 377... | Line 377... | ||
377 | return; |
377 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
378 | 378 | ||
Line 379... | Line 379... | ||
379 | val &= ~hsw_infoframe_enable(type); |
379 | val &= ~hsw_infoframe_enable(type); |
Line 394... | Line 394... | ||
394 | val |= hsw_infoframe_enable(type); |
394 | val |= hsw_infoframe_enable(type); |
395 | I915_WRITE(ctl_reg, val); |
395 | I915_WRITE(ctl_reg, val); |
396 | POSTING_READ(ctl_reg); |
396 | POSTING_READ(ctl_reg); |
397 | } |
397 | } |
Line 398... | Line 398... | ||
398 | 398 | ||
- | 399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
|
399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
400 | const struct intel_crtc_state *pipe_config) |
400 | { |
- | |
401 | struct drm_device *dev = encoder->dev; |
401 | { |
402 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
403 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
402 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
404 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
- | |
Line 405... | Line 403... | ||
405 | u32 val = I915_READ(ctl_reg); |
403 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
406 | 404 | ||
407 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
405 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
408 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
406 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
Line 511... | Line 509... | ||
511 | const struct drm_display_mode *adjusted_mode) |
509 | const struct drm_display_mode *adjusted_mode) |
512 | { |
510 | { |
513 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
511 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
514 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
512 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
515 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
513 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
516 | u32 reg = VIDEO_DIP_CTL; |
514 | i915_reg_t reg = VIDEO_DIP_CTL; |
517 | u32 val = I915_READ(reg); |
515 | u32 val = I915_READ(reg); |
518 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
516 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
Line 519... | Line 517... | ||
519 | 517 | ||
Line 631... | Line 629... | ||
631 | 629 | ||
632 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
630 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
633 | { |
631 | { |
634 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
632 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
- | 633 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
|
635 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
634 | i915_reg_t reg; |
Line 636... | Line 635... | ||
636 | u32 reg, val = 0; |
635 | u32 val = 0; |
637 | 636 | ||
638 | if (HAS_DDI(dev_priv)) |
637 | if (HAS_DDI(dev_priv)) |
639 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); |
638 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); |
640 | else if (IS_VALLEYVIEW(dev_priv)) |
639 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
641 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
640 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
642 | else if (HAS_PCH_SPLIT(dev_priv->dev)) |
641 | else if (HAS_PCH_SPLIT(dev_priv->dev)) |
643 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
642 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
Line 664... | Line 663... | ||
664 | { |
663 | { |
665 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
664 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
666 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
665 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
667 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
666 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
668 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
667 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
669 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
668 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
670 | u32 val = I915_READ(reg); |
669 | u32 val = I915_READ(reg); |
671 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
670 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
Line 672... | Line 671... | ||
672 | 671 | ||
Line 715... | Line 714... | ||
715 | const struct drm_display_mode *adjusted_mode) |
714 | const struct drm_display_mode *adjusted_mode) |
716 | { |
715 | { |
717 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
716 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
718 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
717 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
719 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
718 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
720 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
719 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
721 | u32 val = I915_READ(reg); |
720 | u32 val = I915_READ(reg); |
Line 722... | Line 721... | ||
722 | 721 | ||
Line 723... | Line 722... | ||
723 | assert_hdmi_port_disabled(intel_hdmi); |
722 | assert_hdmi_port_disabled(intel_hdmi); |
Line 758... | Line 757... | ||
758 | { |
757 | { |
759 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
758 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
760 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
759 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
760 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
762 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
761 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
763 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
762 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
764 | u32 val = I915_READ(reg); |
763 | u32 val = I915_READ(reg); |
765 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
764 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
Line 766... | Line 765... | ||
766 | 765 | ||
Line 809... | Line 808... | ||
809 | const struct drm_display_mode *adjusted_mode) |
808 | const struct drm_display_mode *adjusted_mode) |
810 | { |
809 | { |
811 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
810 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
811 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
812 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
814 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
813 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
815 | u32 val = I915_READ(reg); |
814 | u32 val = I915_READ(reg); |
Line 816... | Line 815... | ||
816 | 815 | ||
Line 817... | Line 816... | ||
817 | assert_hdmi_port_disabled(intel_hdmi); |
816 | assert_hdmi_port_disabled(intel_hdmi); |
Line 879... | Line 878... | ||
879 | struct drm_device *dev = encoder->base.dev; |
878 | struct drm_device *dev = encoder->base.dev; |
880 | struct drm_i915_private *dev_priv = dev->dev_private; |
879 | struct drm_i915_private *dev_priv = dev->dev_private; |
881 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
880 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
882 | enum intel_display_power_domain power_domain; |
881 | enum intel_display_power_domain power_domain; |
883 | u32 tmp; |
882 | u32 tmp; |
- | 883 | bool ret; |
|
Line 884... | Line 884... | ||
884 | 884 | ||
885 | power_domain = intel_display_port_power_domain(encoder); |
885 | power_domain = intel_display_port_power_domain(encoder); |
886 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
886 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Line -... | Line 887... | ||
- | 887 | return false; |
|
- | 888 | ||
887 | return false; |
889 | ret = false; |
Line 888... | Line 890... | ||
888 | 890 | ||
889 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
891 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
Line 890... | Line 892... | ||
890 | 892 | ||
891 | if (!(tmp & SDVO_ENABLE)) |
893 | if (!(tmp & SDVO_ENABLE)) |
892 | return false; |
894 | goto out; |
893 | 895 | ||
894 | if (HAS_PCH_CPT(dev)) |
896 | if (HAS_PCH_CPT(dev)) |
895 | *pipe = PORT_TO_PIPE_CPT(tmp); |
897 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Line 896... | Line 898... | ||
896 | else if (IS_CHERRYVIEW(dev)) |
898 | else if (IS_CHERRYVIEW(dev)) |
- | 899 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
|
- | 900 | else |
|
- | 901 | *pipe = PORT_TO_PIPE(tmp); |
|
- | 902 | ||
- | 903 | ret = true; |
|
897 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
904 | |
Line 898... | Line 905... | ||
898 | else |
905 | out: |
899 | *pipe = PORT_TO_PIPE(tmp); |
906 | intel_display_power_put(dev_priv, power_domain); |
900 | 907 | ||
Line 923... | Line 930... | ||
923 | flags |= DRM_MODE_FLAG_NVSYNC; |
930 | flags |= DRM_MODE_FLAG_NVSYNC; |
Line 924... | Line 931... | ||
924 | 931 | ||
925 | if (tmp & HDMI_MODE_SELECT_HDMI) |
932 | if (tmp & HDMI_MODE_SELECT_HDMI) |
Line 926... | Line 933... | ||
926 | pipe_config->has_hdmi_sink = true; |
933 | pipe_config->has_hdmi_sink = true; |
927 | 934 | ||
Line 928... | Line 935... | ||
928 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
935 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
929 | pipe_config->has_infoframe = true; |
936 | pipe_config->has_infoframe = true; |
Line 1106... | Line 1113... | ||
1106 | * HW workaround for IBX, we need to move the port |
1113 | * HW workaround for IBX, we need to move the port |
1107 | * to transcoder A after disabling it to allow the |
1114 | * to transcoder A after disabling it to allow the |
1108 | * matching DP port to be enabled on transcoder A. |
1115 | * matching DP port to be enabled on transcoder A. |
1109 | */ |
1116 | */ |
1110 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { |
1117 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { |
- | 1118 | /* |
|
- | 1119 | * We get CPU/PCH FIFO underruns on the other pipe when |
|
- | 1120 | * doing the workaround. Sweep them under the rug. |
|
- | 1121 | */ |
|
- | 1122 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
|
- | 1123 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
|
- | 1124 | ||
1111 | temp &= ~SDVO_PIPE_B_SELECT; |
1125 | temp &= ~SDVO_PIPE_B_SELECT; |
1112 | temp |= SDVO_ENABLE; |
1126 | temp |= SDVO_ENABLE; |
1113 | /* |
1127 | /* |
1114 | * HW workaround, need to write this twice for issue |
1128 | * HW workaround, need to write this twice for issue |
1115 | * that may result in first write getting masked. |
1129 | * that may result in first write getting masked. |
Line 1120... | Line 1134... | ||
1120 | POSTING_READ(intel_hdmi->hdmi_reg); |
1134 | POSTING_READ(intel_hdmi->hdmi_reg); |
Line 1121... | Line 1135... | ||
1121 | 1135 | ||
1122 | temp &= ~SDVO_ENABLE; |
1136 | temp &= ~SDVO_ENABLE; |
1123 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1137 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
- | 1138 | POSTING_READ(intel_hdmi->hdmi_reg); |
|
- | 1139 | ||
- | 1140 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
|
- | 1141 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
|
1124 | POSTING_READ(intel_hdmi->hdmi_reg); |
1142 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Line 1125... | Line 1143... | ||
1125 | } |
1143 | } |
1126 | 1144 | ||
Line 1329... | Line 1347... | ||
1329 | kfree(to_intel_connector(connector)->detect_edid); |
1347 | kfree(to_intel_connector(connector)->detect_edid); |
1330 | to_intel_connector(connector)->detect_edid = NULL; |
1348 | to_intel_connector(connector)->detect_edid = NULL; |
1331 | } |
1349 | } |
Line 1332... | Line 1350... | ||
1332 | 1350 | ||
1333 | static bool |
1351 | static bool |
1334 | intel_hdmi_set_edid(struct drm_connector *connector) |
1352 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
1335 | { |
1353 | { |
1336 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1354 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1337 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1355 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1338 | struct edid *edid; |
1356 | struct edid *edid = NULL; |
Line -... | Line 1357... | ||
- | 1357 | bool connected = false; |
|
1339 | bool connected = false; |
1358 | |
Line 1340... | Line 1359... | ||
1340 | 1359 | if (force) { |
|
1341 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1360 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1342 | 1361 | ||
Line 1343... | Line 1362... | ||
1343 | edid = drm_get_edid(connector, |
1362 | edid = drm_get_edid(connector, |
- | 1363 | intel_gmbus_get_adapter(dev_priv, |
|
Line 1344... | Line 1364... | ||
1344 | intel_gmbus_get_adapter(dev_priv, |
1364 | intel_hdmi->ddc_bus)); |
1345 | intel_hdmi->ddc_bus)); |
1365 | |
1346 | 1366 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
|
1347 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1367 | } |
Line 1368... | Line 1388... | ||
1368 | 1388 | ||
1369 | static enum drm_connector_status |
1389 | static enum drm_connector_status |
1370 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
1390 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
1371 | { |
1391 | { |
- | 1392 | enum drm_connector_status status; |
|
1372 | enum drm_connector_status status; |
1393 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
- | 1394 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
|
- | 1395 | bool live_status = false; |
|
Line 1373... | Line 1396... | ||
1373 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1396 | unsigned int try; |
1374 | 1397 | ||
Line 1375... | Line 1398... | ||
1375 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1398 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Line -... | Line 1399... | ||
- | 1399 | connector->base.id, connector->name); |
|
- | 1400 | ||
- | 1401 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
|
- | 1402 | ||
- | 1403 | for (try = 0; !live_status && try < 9; try++) { |
|
- | 1404 | if (try) |
|
- | 1405 | msleep(10); |
|
- | 1406 | live_status = intel_digital_port_connected(dev_priv, |
|
- | 1407 | hdmi_to_dig_port(intel_hdmi)); |
|
- | 1408 | } |
|
- | 1409 | ||
- | 1410 | if (!live_status) { |
|
- | 1411 | DRM_DEBUG_KMS("HDMI live status down\n"); |
|
- | 1412 | /* |
|
- | 1413 | * Live status register is not reliable on all intel platforms. |
|
- | 1414 | * So consider live_status only for certain platforms, for |
|
- | 1415 | * others, read EDID to determine presence of sink. |
|
- | 1416 | */ |
|
1376 | connector->base.id, connector->name); |
1417 | if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) |
Line 1377... | Line 1418... | ||
1377 | 1418 | live_status = true; |
|
1378 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1419 | } |
Line 1379... | Line 1420... | ||
1379 | 1420 | ||
1380 | intel_hdmi_unset_edid(connector); |
1421 | intel_hdmi_unset_edid(connector); |
1381 | 1422 | ||
Line 1403... | Line 1444... | ||
1403 | intel_hdmi_unset_edid(connector); |
1444 | intel_hdmi_unset_edid(connector); |
Line 1404... | Line 1445... | ||
1404 | 1445 | ||
1405 | if (connector->status != connector_status_connected) |
1446 | if (connector->status != connector_status_connected) |
Line 1406... | Line 1447... | ||
1406 | return; |
1447 | return; |
1407 | 1448 | ||
1408 | intel_hdmi_set_edid(connector); |
1449 | intel_hdmi_set_edid(connector, true); |
Line 1409... | Line 1450... | ||
1409 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1450 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1410 | } |
1451 | } |
Line 1995... | Line 2036... | ||
1995 | intel_hdmi->color_range_auto = true; |
2036 | intel_hdmi->color_range_auto = true; |
1996 | intel_attach_aspect_ratio_property(connector); |
2037 | intel_attach_aspect_ratio_property(connector); |
1997 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
2038 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
1998 | } |
2039 | } |
Line 1999... | Line -... | ||
1999 | - | ||
2000 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, |
- | |
2001 | enum port port) |
- | |
2002 | { |
- | |
2003 | const struct ddi_vbt_port_info *info = |
- | |
2004 | &dev_priv->vbt.ddi_port_info[port]; |
- | |
2005 | u8 ddc_pin; |
- | |
2006 | - | ||
2007 | if (info->alternate_ddc_pin) { |
- | |
2008 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", |
- | |
2009 | info->alternate_ddc_pin, port_name(port)); |
- | |
2010 | return info->alternate_ddc_pin; |
- | |
2011 | } |
- | |
2012 | - | ||
2013 | switch (port) { |
- | |
2014 | case PORT_B: |
- | |
2015 | if (IS_BROXTON(dev_priv)) |
- | |
2016 | ddc_pin = GMBUS_PIN_1_BXT; |
- | |
2017 | else |
- | |
2018 | ddc_pin = GMBUS_PIN_DPB; |
- | |
2019 | break; |
- | |
2020 | case PORT_C: |
- | |
2021 | if (IS_BROXTON(dev_priv)) |
- | |
2022 | ddc_pin = GMBUS_PIN_2_BXT; |
- | |
2023 | else |
- | |
2024 | ddc_pin = GMBUS_PIN_DPC; |
- | |
2025 | break; |
- | |
2026 | case PORT_D: |
- | |
2027 | if (IS_CHERRYVIEW(dev_priv)) |
- | |
2028 | ddc_pin = GMBUS_PIN_DPD_CHV; |
- | |
2029 | else |
- | |
2030 | ddc_pin = GMBUS_PIN_DPD; |
- | |
2031 | break; |
- | |
2032 | default: |
- | |
2033 | MISSING_CASE(port); |
- | |
2034 | ddc_pin = GMBUS_PIN_DPB; |
- | |
2035 | break; |
- | |
2036 | } |
- | |
2037 | - | ||
2038 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", |
- | |
2039 | ddc_pin, port_name(port)); |
- | |
2040 | - | ||
2041 | return ddc_pin; |
- | |
2042 | } |
- | |
2043 | 2040 | ||
2044 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2041 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2045 | struct intel_connector *intel_connector) |
2042 | struct intel_connector *intel_connector) |
2046 | { |
2043 | { |
2047 | struct drm_connector *connector = &intel_connector->base; |
2044 | struct drm_connector *connector = &intel_connector->base; |
2048 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
2045 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
2049 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2046 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2050 | struct drm_device *dev = intel_encoder->base.dev; |
2047 | struct drm_device *dev = intel_encoder->base.dev; |
2051 | struct drm_i915_private *dev_priv = dev->dev_private; |
2048 | struct drm_i915_private *dev_priv = dev->dev_private; |
2052 | enum port port = intel_dig_port->port; |
- | |
2053 | - | ||
2054 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2049 | enum port port = intel_dig_port->port; |
Line 2055... | Line 2050... | ||
2055 | port_name(port)); |
2050 | uint8_t alternate_ddc_pin; |
2056 | 2051 | ||
2057 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
2052 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
Line 2058... | Line 2053... | ||
2058 | DRM_MODE_CONNECTOR_HDMIA); |
2053 | DRM_MODE_CONNECTOR_HDMIA); |
2059 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2054 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2060 | 2055 | ||
Line 2061... | Line -... | ||
2061 | connector->interlace_allowed = 1; |
- | |
2062 | connector->doublescan_allowed = 0; |
- | |
2063 | connector->stereo_allowed = 1; |
2056 | connector->interlace_allowed = 1; |
2064 | 2057 | connector->doublescan_allowed = 0; |
|
- | 2058 | connector->stereo_allowed = 1; |
|
- | 2059 | ||
- | 2060 | switch (port) { |
|
- | 2061 | case PORT_B: |
|
2065 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
2062 | if (IS_BROXTON(dev_priv)) |
2066 | 2063 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; |
|
2067 | switch (port) { |
2064 | else |
2068 | case PORT_B: |
2065 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
2069 | /* |
2066 | /* |
2070 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
2067 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
2071 | * interrupts to check the external panel connection. |
2068 | * interrupts to check the external panel connection. |
2072 | */ |
2069 | */ |
2073 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
2070 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
2074 | intel_encoder->hpd_pin = HPD_PORT_A; |
2071 | intel_encoder->hpd_pin = HPD_PORT_A; |
- | 2072 | else |
|
- | 2073 | intel_encoder->hpd_pin = HPD_PORT_B; |
|
- | 2074 | break; |
|
- | 2075 | case PORT_C: |
|
2075 | else |
2076 | if (IS_BROXTON(dev_priv)) |
2076 | intel_encoder->hpd_pin = HPD_PORT_B; |
2077 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; |
2077 | break; |
2078 | else |
- | 2079 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
|
- | 2080 | intel_encoder->hpd_pin = HPD_PORT_C; |
|
- | 2081 | break; |
|
- | 2082 | case PORT_D: |
|
- | 2083 | if (WARN_ON(IS_BROXTON(dev_priv))) |
|
- | 2084 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; |
|
2078 | case PORT_C: |
2085 | else if (IS_CHERRYVIEW(dev_priv)) |
2079 | intel_encoder->hpd_pin = HPD_PORT_C; |
2086 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
2080 | break; |
2087 | else |
- | 2088 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
|
- | 2089 | intel_encoder->hpd_pin = HPD_PORT_D; |
|
- | 2090 | break; |
|
- | 2091 | case PORT_E: |
|
- | 2092 | /* On SKL PORT E doesn't have seperate GMBUS pin |
|
- | 2093 | * We rely on VBT to set a proper alternate GMBUS pin. */ |
|
- | 2094 | alternate_ddc_pin = |
|
- | 2095 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; |
|
- | 2096 | switch (alternate_ddc_pin) { |
|
- | 2097 | case DDC_PIN_B: |
|
- | 2098 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
|
- | 2099 | break; |
|
- | 2100 | case DDC_PIN_C: |
|
- | 2101 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
|
- | 2102 | break; |
|
- | 2103 | case DDC_PIN_D: |
|
- | 2104 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
|
2081 | case PORT_D: |
2105 | break; |
2082 | intel_encoder->hpd_pin = HPD_PORT_D; |
2106 | default: |
- | 2107 | MISSING_CASE(alternate_ddc_pin); |
|
- | 2108 | } |
|
- | 2109 | intel_encoder->hpd_pin = HPD_PORT_E; |
|
2083 | break; |
2110 | break; |
2084 | case PORT_E: |
- | |
2085 | intel_encoder->hpd_pin = HPD_PORT_E; |
2111 | case PORT_A: |
2086 | break; |
2112 | intel_encoder->hpd_pin = HPD_PORT_A; |
Line 2087... | Line 2113... | ||
2087 | default: |
2113 | /* Internal port only for eDP. */ |
2088 | MISSING_CASE(port); |
2114 | default: |
2089 | return; |
2115 | BUG(); |
2090 | } |
2116 | } |
2091 | 2117 | ||
2092 | if (IS_VALLEYVIEW(dev)) { |
2118 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Line 2131... | Line 2157... | ||
2131 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2157 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2132 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2158 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2133 | } |
2159 | } |
2134 | } |
2160 | } |
Line 2135... | Line 2161... | ||
2135 | 2161 | ||
- | 2162 | void intel_hdmi_init(struct drm_device *dev, |
|
2136 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
2163 | i915_reg_t hdmi_reg, enum port port) |
2137 | { |
2164 | { |
2138 | struct intel_digital_port *intel_dig_port; |
2165 | struct intel_digital_port *intel_dig_port; |
2139 | struct intel_encoder *intel_encoder; |
2166 | struct intel_encoder *intel_encoder; |
Line 2150... | Line 2177... | ||
2150 | } |
2177 | } |
Line 2151... | Line 2178... | ||
2151 | 2178 | ||
Line 2152... | Line 2179... | ||
2152 | intel_encoder = &intel_dig_port->base; |
2179 | intel_encoder = &intel_dig_port->base; |
2153 | 2180 | ||
Line 2154... | Line 2181... | ||
2154 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
2181 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
2155 | DRM_MODE_ENCODER_TMDS); |
2182 | DRM_MODE_ENCODER_TMDS, NULL); |
2156 | 2183 | ||
2157 | intel_encoder->compute_config = intel_hdmi_compute_config; |
2184 | intel_encoder->compute_config = intel_hdmi_compute_config; |
Line 2202... | Line 2229... | ||
2202 | if (IS_G4X(dev)) |
2229 | if (IS_G4X(dev)) |
2203 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
2230 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
Line 2204... | Line 2231... | ||
2204 | 2231 | ||
2205 | intel_dig_port->port = port; |
2232 | intel_dig_port->port = port; |
2206 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
2233 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
Line 2207... | Line 2234... | ||
2207 | intel_dig_port->dp.output_reg = 0; |
2234 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
2208 | 2235 |