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Rev 5139 | Rev 5354 | ||
---|---|---|---|
Line 164... | Line 164... | ||
164 | 164 | ||
165 | I915_WRITE(VIDEO_DIP_CTL, val); |
165 | I915_WRITE(VIDEO_DIP_CTL, val); |
166 | POSTING_READ(VIDEO_DIP_CTL); |
166 | POSTING_READ(VIDEO_DIP_CTL); |
Line -... | Line 167... | ||
- | 167 | } |
|
- | 168 | ||
- | 169 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
|
- | 170 | { |
|
- | 171 | struct drm_device *dev = encoder->dev; |
|
- | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 173 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
|
- | 174 | u32 val = I915_READ(VIDEO_DIP_CTL); |
|
- | 175 | ||
- | 176 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
|
- | 177 | return val & VIDEO_DIP_ENABLE; |
|
- | 178 | ||
- | 179 | return false; |
|
167 | } |
180 | } |
168 | 181 | ||
169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
182 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
170 | enum hdmi_infoframe_type type, |
183 | enum hdmi_infoframe_type type, |
171 | const void *frame, ssize_t len) |
184 | const void *frame, ssize_t len) |
Line 202... | Line 215... | ||
202 | 215 | ||
203 | I915_WRITE(reg, val); |
216 | I915_WRITE(reg, val); |
204 | POSTING_READ(reg); |
217 | POSTING_READ(reg); |
Line -... | Line 218... | ||
- | 218 | } |
|
- | 219 | ||
- | 220 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
|
- | 221 | { |
|
- | 222 | struct drm_device *dev = encoder->dev; |
|
- | 223 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 224 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
|
- | 225 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
|
- | 226 | u32 val = I915_READ(reg); |
|
- | 227 | ||
- | 228 | return val & VIDEO_DIP_ENABLE; |
|
205 | } |
229 | } |
206 | 230 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
231 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
208 | enum hdmi_infoframe_type type, |
232 | enum hdmi_infoframe_type type, |
209 | const void *frame, ssize_t len) |
233 | const void *frame, ssize_t len) |
Line 243... | Line 267... | ||
243 | 267 | ||
244 | I915_WRITE(reg, val); |
268 | I915_WRITE(reg, val); |
245 | POSTING_READ(reg); |
269 | POSTING_READ(reg); |
Line -... | Line 270... | ||
- | 270 | } |
|
- | 271 | ||
- | 272 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
|
- | 273 | { |
|
- | 274 | struct drm_device *dev = encoder->dev; |
|
- | 275 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 276 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
|
- | 277 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
|
- | 278 | u32 val = I915_READ(reg); |
|
- | 279 | ||
- | 280 | return val & VIDEO_DIP_ENABLE; |
|
246 | } |
281 | } |
247 | 282 | ||
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
283 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
249 | enum hdmi_infoframe_type type, |
284 | enum hdmi_infoframe_type type, |
250 | const void *frame, ssize_t len) |
285 | const void *frame, ssize_t len) |
Line 281... | Line 316... | ||
281 | 316 | ||
282 | I915_WRITE(reg, val); |
317 | I915_WRITE(reg, val); |
283 | POSTING_READ(reg); |
318 | POSTING_READ(reg); |
Line -... | Line 319... | ||
- | 319 | } |
|
- | 320 | ||
- | 321 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
|
- | 322 | { |
|
- | 323 | struct drm_device *dev = encoder->dev; |
|
- | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 325 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
|
- | 326 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
|
- | 327 | u32 val = I915_READ(reg); |
|
- | 328 | ||
- | 329 | return val & VIDEO_DIP_ENABLE; |
|
284 | } |
330 | } |
285 | 331 | ||
286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
332 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
287 | enum hdmi_infoframe_type type, |
333 | enum hdmi_infoframe_type type, |
288 | const void *frame, ssize_t len) |
334 | const void *frame, ssize_t len) |
Line 318... | Line 364... | ||
318 | val |= hsw_infoframe_enable(type); |
364 | val |= hsw_infoframe_enable(type); |
319 | I915_WRITE(ctl_reg, val); |
365 | I915_WRITE(ctl_reg, val); |
320 | POSTING_READ(ctl_reg); |
366 | POSTING_READ(ctl_reg); |
321 | } |
367 | } |
Line -... | Line 368... | ||
- | 368 | ||
- | 369 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
|
- | 370 | { |
|
- | 371 | struct drm_device *dev = encoder->dev; |
|
- | 372 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 373 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
|
- | 374 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
|
- | 375 | u32 val = I915_READ(ctl_reg); |
|
- | 376 | ||
- | 377 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | |
|
- | 378 | VIDEO_DIP_ENABLE_VS_HSW); |
|
- | 379 | } |
|
322 | 380 | ||
323 | /* |
381 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
382 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
383 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
384 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
Line 659... | Line 717... | ||
659 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
717 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
Line 660... | Line 718... | ||
660 | 718 | ||
661 | if (crtc->config.has_hdmi_sink) |
719 | if (crtc->config.has_hdmi_sink) |
Line 662... | Line -... | ||
662 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
- | |
663 | - | ||
664 | if (crtc->config.has_audio) { |
- | |
665 | WARN_ON(!crtc->config.has_hdmi_sink); |
- | |
666 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
- | |
667 | pipe_name(crtc->pipe)); |
- | |
668 | hdmi_val |= SDVO_AUDIO_ENABLE; |
- | |
669 | intel_write_eld(&encoder->base, adjusted_mode); |
- | |
670 | } |
720 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
671 | 721 | ||
672 | if (HAS_PCH_CPT(dev)) |
722 | if (HAS_PCH_CPT(dev)) |
673 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
723 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
674 | else if (IS_CHERRYVIEW(dev)) |
724 | else if (IS_CHERRYVIEW(dev)) |
Line 688... | Line 738... | ||
688 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
738 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
689 | enum intel_display_power_domain power_domain; |
739 | enum intel_display_power_domain power_domain; |
690 | u32 tmp; |
740 | u32 tmp; |
Line 691... | Line 741... | ||
691 | 741 | ||
692 | power_domain = intel_display_port_power_domain(encoder); |
742 | power_domain = intel_display_port_power_domain(encoder); |
693 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
743 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
Line 694... | Line 744... | ||
694 | return false; |
744 | return false; |
Line 695... | Line 745... | ||
695 | 745 | ||
Line 730... | Line 780... | ||
730 | flags |= DRM_MODE_FLAG_NVSYNC; |
780 | flags |= DRM_MODE_FLAG_NVSYNC; |
Line 731... | Line 781... | ||
731 | 781 | ||
732 | if (tmp & HDMI_MODE_SELECT_HDMI) |
782 | if (tmp & HDMI_MODE_SELECT_HDMI) |
Line -... | Line 783... | ||
- | 783 | pipe_config->has_hdmi_sink = true; |
|
- | 784 | ||
- | 785 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
|
733 | pipe_config->has_hdmi_sink = true; |
786 | pipe_config->has_infoframe = true; |
734 | 787 | ||
Line 735... | Line 788... | ||
735 | if (tmp & HDMI_MODE_SELECT_HDMI) |
788 | if (tmp & SDVO_AUDIO_ENABLE) |
736 | pipe_config->has_audio = true; |
789 | pipe_config->has_audio = true; |
737 | 790 | ||
Line 789... | Line 842... | ||
789 | */ |
842 | */ |
790 | if (HAS_PCH_SPLIT(dev)) { |
843 | if (HAS_PCH_SPLIT(dev)) { |
791 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
844 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
792 | POSTING_READ(intel_hdmi->hdmi_reg); |
845 | POSTING_READ(intel_hdmi->hdmi_reg); |
793 | } |
846 | } |
- | 847 | ||
- | 848 | if (intel_crtc->config.has_audio) { |
|
- | 849 | WARN_ON(!intel_crtc->config.has_hdmi_sink); |
|
- | 850 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
|
- | 851 | pipe_name(intel_crtc->pipe)); |
|
- | 852 | intel_audio_codec_enable(encoder); |
|
- | 853 | } |
|
794 | } |
854 | } |
Line 795... | Line 855... | ||
795 | 855 | ||
796 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
856 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
797 | { |
857 | { |
Line 800... | Line 860... | ||
800 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
860 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
801 | { |
861 | { |
802 | struct drm_device *dev = encoder->base.dev; |
862 | struct drm_device *dev = encoder->base.dev; |
803 | struct drm_i915_private *dev_priv = dev->dev_private; |
863 | struct drm_i915_private *dev_priv = dev->dev_private; |
804 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
864 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
- | 865 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
|
805 | u32 temp; |
866 | u32 temp; |
806 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
867 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
Line -... | Line 868... | ||
- | 868 | ||
- | 869 | if (crtc->config.has_audio) |
|
- | 870 | intel_audio_codec_disable(encoder); |
|
807 | 871 | ||
Line 808... | Line 872... | ||
808 | temp = I915_READ(intel_hdmi->hdmi_reg); |
872 | temp = I915_READ(intel_hdmi->hdmi_reg); |
809 | 873 | ||
810 | /* HW workaround for IBX, we need to move the port to transcoder A |
874 | /* HW workaround for IBX, we need to move the port to transcoder A |
Line 867... | Line 931... | ||
867 | 931 | ||
868 | static enum drm_mode_status |
932 | static enum drm_mode_status |
869 | intel_hdmi_mode_valid(struct drm_connector *connector, |
933 | intel_hdmi_mode_valid(struct drm_connector *connector, |
870 | struct drm_display_mode *mode) |
934 | struct drm_display_mode *mode) |
- | 935 | { |
|
- | 936 | int clock = mode->clock; |
|
- | 937 | ||
- | 938 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
|
- | 939 | clock *= 2; |
|
871 | { |
940 | |
872 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
941 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
873 | true)) |
942 | true)) |
874 | return MODE_CLOCK_HIGH; |
943 | return MODE_CLOCK_HIGH; |
875 | if (mode->clock < 20000) |
944 | if (clock < 20000) |
Line 876... | Line 945... | ||
876 | return MODE_CLOCK_LOW; |
945 | return MODE_CLOCK_LOW; |
877 | 946 | ||
Line 888... | Line 957... | ||
888 | int count = 0, count_hdmi = 0; |
957 | int count = 0, count_hdmi = 0; |
Line 889... | Line 958... | ||
889 | 958 | ||
890 | if (HAS_GMCH_DISPLAY(dev)) |
959 | if (HAS_GMCH_DISPLAY(dev)) |
Line 891... | Line 960... | ||
891 | return false; |
960 | return false; |
892 | 961 | ||
893 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
962 | for_each_intel_encoder(dev, encoder) { |
Line 894... | Line 963... | ||
894 | if (encoder->new_crtc != crtc) |
963 | if (encoder->new_crtc != crtc) |
895 | continue; |
964 | continue; |
Line 915... | Line 984... | ||
915 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
984 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
916 | int desired_bpp; |
985 | int desired_bpp; |
Line 917... | Line 986... | ||
917 | 986 | ||
Line -... | Line 987... | ||
- | 987 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
|
- | 988 | ||
- | 989 | if (pipe_config->has_hdmi_sink) |
|
918 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
990 | pipe_config->has_infoframe = true; |
919 | 991 | ||
920 | if (intel_hdmi->color_range_auto) { |
992 | if (intel_hdmi->color_range_auto) { |
921 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
993 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
922 | if (pipe_config->has_hdmi_sink && |
994 | if (pipe_config->has_hdmi_sink && |
923 | drm_match_cea_mode(adjusted_mode) > 1) |
995 | drm_match_cea_mode(adjusted_mode) > 1) |
924 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
996 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
925 | else |
997 | else |
Line -... | Line 998... | ||
- | 998 | intel_hdmi->color_range = 0; |
|
- | 999 | } |
|
- | 1000 | ||
- | 1001 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
|
926 | intel_hdmi->color_range = 0; |
1002 | pipe_config->pixel_multiplier = 2; |
927 | } |
1003 | } |
Line 928... | Line 1004... | ||
928 | 1004 | ||
929 | if (intel_hdmi->color_range) |
1005 | if (intel_hdmi->color_range) |
Line 965... | Line 1041... | ||
965 | } |
1041 | } |
Line 966... | Line 1042... | ||
966 | 1042 | ||
967 | return true; |
1043 | return true; |
Line 968... | Line 1044... | ||
968 | } |
1044 | } |
969 | 1045 | ||
970 | static enum drm_connector_status |
1046 | static void |
971 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
- | |
972 | { |
1047 | intel_hdmi_unset_edid(struct drm_connector *connector) |
973 | struct drm_device *dev = connector->dev; |
- | |
974 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
- | |
975 | struct intel_digital_port *intel_dig_port = |
- | |
976 | hdmi_to_dig_port(intel_hdmi); |
- | |
977 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
- | |
978 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
979 | struct edid *edid; |
- | |
Line 980... | Line 1048... | ||
980 | enum intel_display_power_domain power_domain; |
1048 | { |
- | 1049 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
|
- | 1050 | ||
- | 1051 | intel_hdmi->has_hdmi_sink = false; |
|
981 | enum drm_connector_status status = connector_status_disconnected; |
1052 | intel_hdmi->has_audio = false; |
- | 1053 | intel_hdmi->rgb_quant_range_selectable = false; |
|
- | 1054 | ||
- | 1055 | kfree(to_intel_connector(connector)->detect_edid); |
|
- | 1056 | to_intel_connector(connector)->detect_edid = NULL; |
|
- | 1057 | } |
|
- | 1058 | ||
- | 1059 | static bool |
|
- | 1060 | intel_hdmi_set_edid(struct drm_connector *connector) |
|
- | 1061 | { |
|
- | 1062 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
|
- | 1063 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
|
- | 1064 | struct intel_encoder *intel_encoder = |
|
- | 1065 | &hdmi_to_dig_port(intel_hdmi)->base; |
|
Line 982... | Line 1066... | ||
982 | 1066 | enum intel_display_power_domain power_domain; |
|
983 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1067 | struct edid *edid; |
Line 984... | Line -... | ||
984 | connector->base.id, connector->name); |
- | |
985 | - | ||
986 | power_domain = intel_display_port_power_domain(intel_encoder); |
- | |
987 | intel_display_power_get(dev_priv, power_domain); |
1068 | bool connected = false; |
988 | 1069 | ||
989 | intel_hdmi->has_hdmi_sink = false; |
1070 | power_domain = intel_display_port_power_domain(intel_encoder); |
Line 990... | Line -... | ||
990 | intel_hdmi->has_audio = false; |
- | |
991 | intel_hdmi->rgb_quant_range_selectable = false; |
1071 | intel_display_power_get(dev_priv, power_domain); |
- | 1072 | ||
992 | edid = drm_get_edid(connector, |
1073 | edid = drm_get_edid(connector, |
993 | intel_gmbus_get_adapter(dev_priv, |
1074 | intel_gmbus_get_adapter(dev_priv, |
994 | intel_hdmi->ddc_bus)); |
- | |
995 | - | ||
996 | if (edid) { |
- | |
997 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1075 | intel_hdmi->ddc_bus)); |
998 | status = connector_status_connected; |
1076 | |
999 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
- | |
1000 | intel_hdmi->has_hdmi_sink = |
- | |
1001 | drm_detect_hdmi_monitor(edid); |
- | |
Line 1002... | Line 1077... | ||
1002 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
1077 | intel_display_power_put(dev_priv, power_domain); |
1003 | intel_hdmi->rgb_quant_range_selectable = |
1078 | |
1004 | drm_rgb_quant_range_selectable(edid); |
1079 | to_intel_connector(connector)->detect_edid = edid; |
1005 | } |
1080 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { |
- | 1081 | intel_hdmi->rgb_quant_range_selectable = |
|
1006 | kfree(edid); |
1082 | drm_rgb_quant_range_selectable(edid); |
- | 1083 | ||
- | 1084 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
|
- | 1085 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
|
- | 1086 | intel_hdmi->has_audio = |
|
1007 | } |
1087 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
Line -... | Line 1088... | ||
- | 1088 | ||
- | 1089 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
|
- | 1090 | intel_hdmi->has_hdmi_sink = |
|
- | 1091 | drm_detect_hdmi_monitor(edid); |
|
- | 1092 | ||
- | 1093 | connected = true; |
|
- | 1094 | } |
|
- | 1095 | ||
- | 1096 | return connected; |
|
- | 1097 | } |
|
- | 1098 | ||
1008 | 1099 | static enum drm_connector_status |
|
- | 1100 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
|
- | 1101 | { |
|
- | 1102 | enum drm_connector_status status; |
|
- | 1103 | ||
- | 1104 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 1105 | connector->base.id, connector->name); |
|
- | 1106 | ||
- | 1107 | intel_hdmi_unset_edid(connector); |
|
Line 1009... | Line 1108... | ||
1009 | if (status == connector_status_connected) { |
1108 | |
1010 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1109 | if (intel_hdmi_set_edid(connector)) { |
Line -... | Line 1110... | ||
- | 1110 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
|
1011 | intel_hdmi->has_audio = |
1111 | |
1012 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
1112 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1013 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1113 | status = connector_status_connected; |
1014 | } |
- | |
1015 | - | ||
1016 | intel_display_power_put(dev_priv, power_domain); |
- | |
1017 | - | ||
Line 1018... | Line 1114... | ||
1018 | return status; |
1114 | } else |
1019 | } |
1115 | status = connector_status_disconnected; |
1020 | - | ||
Line 1021... | Line -... | ||
1021 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
- | |
1022 | { |
1116 | |
Line 1023... | Line 1117... | ||
1023 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1117 | return status; |
1024 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
- | |
1025 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1118 | } |
Line 1026... | Line 1119... | ||
1026 | enum intel_display_power_domain power_domain; |
1119 | |
- | 1120 | static void |
|
- | 1121 | intel_hdmi_force(struct drm_connector *connector) |
|
Line -... | Line 1122... | ||
- | 1122 | { |
|
- | 1123 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
|
- | 1124 | ||
- | 1125 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 1126 | connector->base.id, connector->name); |
|
- | 1127 | ||
1027 | int ret; |
1128 | intel_hdmi_unset_edid(connector); |
- | 1129 | ||
- | 1130 | if (connector->status != connector_status_connected) |
|
1028 | 1131 | return; |
|
Line 1029... | Line 1132... | ||
1029 | /* We should parse the EDID data and find out if it's an HDMI sink so |
1132 | |
1030 | * we can send audio to it. |
1133 | intel_hdmi_set_edid(connector); |
1031 | */ |
1134 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1032 | - | ||
1033 | power_domain = intel_display_port_power_domain(intel_encoder); |
- | |
1034 | intel_display_power_get(dev_priv, power_domain); |
- | |
1035 | - | ||
1036 | ret = intel_ddc_get_modes(connector, |
- | |
1037 | intel_gmbus_get_adapter(dev_priv, |
1135 | } |
- | 1136 | ||
Line 1038... | Line -... | ||
1038 | intel_hdmi->ddc_bus)); |
- | |
1039 | - | ||
1040 | intel_display_power_put(dev_priv, power_domain); |
- | |
1041 | 1137 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
|
1042 | return ret; |
- | |
1043 | } |
- | |
1044 | - | ||
1045 | static bool |
1138 | { |
1046 | intel_hdmi_detect_audio(struct drm_connector *connector) |
1139 | struct edid *edid; |
1047 | { |
- | |
1048 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
- | |
1049 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
- | |
1050 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
- | |
Line 1051... | Line 1140... | ||
1051 | enum intel_display_power_domain power_domain; |
1140 | |
1052 | struct edid *edid; |
1141 | edid = to_intel_connector(connector)->detect_edid; |
Line 1053... | Line 1142... | ||
1053 | bool has_audio = false; |
1142 | if (edid == NULL) |
Line 1263... | Line 1352... | ||
1263 | to_intel_crtc(encoder->base.crtc); |
1352 | to_intel_crtc(encoder->base.crtc); |
1264 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1353 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1265 | enum pipe pipe = intel_crtc->pipe; |
1354 | enum pipe pipe = intel_crtc->pipe; |
1266 | u32 val; |
1355 | u32 val; |
Line -... | Line 1356... | ||
- | 1356 | ||
- | 1357 | intel_hdmi_prepare(encoder); |
|
1267 | 1358 | ||
Line 1268... | Line 1359... | ||
1268 | mutex_lock(&dev_priv->dpio_lock); |
1359 | mutex_lock(&dev_priv->dpio_lock); |
1269 | 1360 | ||
1270 | /* program left/right clock distribution */ |
1361 | /* program left/right clock distribution */ |
Line 1368... | Line 1459... | ||
1368 | } |
1459 | } |
Line 1369... | Line 1460... | ||
1369 | 1460 | ||
1370 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1461 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1371 | { |
1462 | { |
- | 1463 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
|
1372 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1464 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
1373 | struct drm_device *dev = encoder->base.dev; |
1465 | struct drm_device *dev = encoder->base.dev; |
1374 | struct drm_i915_private *dev_priv = dev->dev_private; |
1466 | struct drm_i915_private *dev_priv = dev->dev_private; |
1375 | struct intel_crtc *intel_crtc = |
1467 | struct intel_crtc *intel_crtc = |
- | 1468 | to_intel_crtc(encoder->base.crtc); |
|
- | 1469 | struct drm_display_mode *adjusted_mode = |
|
1376 | to_intel_crtc(encoder->base.crtc); |
1470 | &intel_crtc->config.adjusted_mode; |
1377 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1471 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1378 | int pipe = intel_crtc->pipe; |
1472 | int pipe = intel_crtc->pipe; |
1379 | int data, i; |
1473 | int data, i; |
Line 1380... | Line 1474... | ||
1380 | u32 val; |
1474 | u32 val; |
Line -... | Line 1475... | ||
- | 1475 | ||
- | 1476 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1477 | ||
- | 1478 | /* allow hardware to manage TX FIFO reset source */ |
|
- | 1479 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
|
- | 1480 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
|
- | 1481 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
|
- | 1482 | ||
- | 1483 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
|
1381 | 1484 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
|
1382 | mutex_lock(&dev_priv->dpio_lock); |
1485 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
1383 | 1486 | ||
1384 | /* Deassert soft data lane reset*/ |
1487 | /* Deassert soft data lane reset*/ |
Line 1415... | Line 1518... | ||
1415 | /* FIXME: Fix up value only after power analysis */ |
1518 | /* FIXME: Fix up value only after power analysis */ |
Line 1416... | Line 1519... | ||
1416 | 1519 | ||
1417 | /* Clear calc init */ |
1520 | /* Clear calc init */ |
1418 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1521 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
- | 1522 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 1523 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
|
1419 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1524 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
Line 1420... | Line 1525... | ||
1420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1525 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1421 | 1526 | ||
- | 1527 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 1528 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
1422 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
1529 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
Line -... | Line 1530... | ||
- | 1530 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
|
- | 1531 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 1532 | ||
- | 1533 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
|
- | 1534 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
|
- | 1535 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
|
- | 1536 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
|
- | 1537 | ||
- | 1538 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
|
- | 1539 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
|
1423 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1540 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
1424 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1541 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
1425 | 1542 | ||
1426 | /* FIXME: Program the support xxx V-dB */ |
1543 | /* FIXME: Program the support xxx V-dB */ |
1427 | /* Use 800mV-0dB */ |
1544 | /* Use 800mV-0dB */ |
Line 1432... | Line 1549... | ||
1432 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
1549 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
1433 | } |
1550 | } |
Line 1434... | Line 1551... | ||
1434 | 1551 | ||
1435 | for (i = 0; i < 4; i++) { |
1552 | for (i = 0; i < 4; i++) { |
1436 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
1553 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
1437 | val &= ~DPIO_SWING_MARGIN_MASK; |
1554 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1438 | val |= 102 << DPIO_SWING_MARGIN_SHIFT; |
1555 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; |
1439 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1556 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
Line 1440... | Line 1557... | ||
1440 | } |
1557 | } |
1441 | 1558 | ||
Line 1473... | Line 1590... | ||
1473 | val |= DPIO_LRC_BYPASS; |
1590 | val |= DPIO_LRC_BYPASS; |
1474 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
1591 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
Line 1475... | Line 1592... | ||
1475 | 1592 | ||
Line -... | Line 1593... | ||
- | 1593 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 1594 | ||
- | 1595 | intel_hdmi->set_infoframes(&encoder->base, |
|
- | 1596 | intel_crtc->config.has_hdmi_sink, |
|
1476 | mutex_unlock(&dev_priv->dpio_lock); |
1597 | adjusted_mode); |
Line 1477... | Line 1598... | ||
1477 | 1598 | ||
1478 | intel_enable_hdmi(encoder); |
1599 | intel_enable_hdmi(encoder); |
Line 1479... | Line 1600... | ||
1479 | 1600 | ||
1480 | vlv_wait_port_ready(dev_priv, dport); |
1601 | vlv_wait_port_ready(dev_priv, dport); |
- | 1602 | } |
|
1481 | } |
1603 | |
1482 | 1604 | static void intel_hdmi_destroy(struct drm_connector *connector) |
|
1483 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1605 | { |
Line 1484... | Line 1606... | ||
1484 | { |
1606 | kfree(to_intel_connector(connector)->detect_edid); |
1485 | drm_connector_cleanup(connector); |
1607 | drm_connector_cleanup(connector); |
1486 | kfree(connector); |
1608 | kfree(connector); |
- | 1609 | } |
|
1487 | } |
1610 | |
1488 | 1611 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
|
1489 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
1612 | .dpms = intel_connector_dpms, |
1490 | .dpms = intel_connector_dpms, |
1613 | .detect = intel_hdmi_detect, |
Line 1565... | Line 1688... | ||
1565 | } |
1688 | } |
Line 1566... | Line 1689... | ||
1566 | 1689 | ||
1567 | if (IS_VALLEYVIEW(dev)) { |
1690 | if (IS_VALLEYVIEW(dev)) { |
1568 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
1691 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
- | 1692 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
|
1569 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
1693 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
1570 | } else if (IS_G4X(dev)) { |
1694 | } else if (IS_G4X(dev)) { |
1571 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1695 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
- | 1696 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
|
1572 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
1697 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
1573 | } else if (HAS_DDI(dev)) { |
1698 | } else if (HAS_DDI(dev)) { |
1574 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
1699 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
- | 1700 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
|
1575 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
1701 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
1576 | } else if (HAS_PCH_IBX(dev)) { |
1702 | } else if (HAS_PCH_IBX(dev)) { |
1577 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
1703 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
- | 1704 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
|
1578 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
1705 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
1579 | } else { |
1706 | } else { |
1580 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
1707 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
- | 1708 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
|
1581 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
1709 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
Line 1582... | Line 1710... | ||
1582 | } |
1710 | } |
1583 | 1711 | ||
1584 | if (HAS_DDI(dev)) |
1712 | if (HAS_DDI(dev)) |