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| Rev 2330 | Rev 2342 | ||
|---|---|---|---|
| Line 67... | Line 67... | ||
| 67 | unsigned i; |
67 | unsigned i; |
| Line 68... | Line 68... | ||
| 68 | 68 | ||
| 69 | frame->checksum = 0; |
69 | frame->checksum = 0; |
| Line 70... | Line -... | ||
| 70 | frame->ecc = 0; |
- | |
| 71 | 70 | frame->ecc = 0; |
|
| 72 | /* Header isn't part of the checksum */ |
71 | |
| Line 73... | Line 72... | ||
| 73 | for (i = 5; i < frame->len; i++) |
72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
| 74 | sum += data[i]; |
73 | sum += data[i]; |
| Line 102... | Line 101... | ||
| 102 | switch (frame->type) { |
101 | switch (frame->type) { |
| 103 | case DIP_TYPE_AVI: |
102 | case DIP_TYPE_AVI: |
| 104 | flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; |
103 | flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 105 | break; |
104 | break; |
| 106 | case DIP_TYPE_SPD: |
105 | case DIP_TYPE_SPD: |
| 107 | flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC; |
106 | flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; |
| 108 | break; |
107 | break; |
| 109 | default: |
108 | default: |
| 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 111 | break; |
110 | break; |
| 112 | } |
111 | } |
| Line 163... | Line 162... | ||
| 163 | 162 | ||
| Line 164... | Line 163... | ||
| 164 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
163 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| Line 165... | Line 164... | ||
| 165 | 164 | ||
| Line 166... | Line 165... | ||
| 166 | flags = intel_infoframe_index(frame); |
165 | flags = intel_infoframe_index(frame); |
| Line 167... | Line 166... | ||
| 167 | 166 | ||
| 168 | val &= ~VIDEO_DIP_SELECT_MASK; |
167 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| 169 | 168 | ||
| 170 | I915_WRITE(reg, val | flags); |
169 | I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); |
| Line 243... | Line 242... | ||
| 243 | /* Required on CPT */ |
242 | /* Required on CPT */ |
| 244 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
243 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
| 245 | sdvox |= HDMI_MODE_SELECT; |
244 | sdvox |= HDMI_MODE_SELECT; |
| Line 246... | Line 245... | ||
| 246 | 245 | ||
| - | 246 | if (intel_hdmi->has_audio) { |
|
| - | 247 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
|
| 247 | if (intel_hdmi->has_audio) { |
248 | pipe_name(intel_crtc->pipe)); |
| 248 | sdvox |= SDVO_AUDIO_ENABLE; |
249 | sdvox |= SDVO_AUDIO_ENABLE; |
| - | 250 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
|
| 249 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
251 | intel_write_eld(encoder, adjusted_mode); |
| Line 250... | Line -... | ||
| 250 | } |
- | |
| 251 | 252 | } |
|
| 252 | if (intel_crtc->pipe == 1) { |
253 | |
| 253 | if (HAS_PCH_CPT(dev)) |
254 | if (HAS_PCH_CPT(dev)) |
| 254 | sdvox |= PORT_TRANS_B_SEL_CPT; |
255 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 255 | else |
- | |
| Line 256... | Line 256... | ||
| 256 | sdvox |= SDVO_PIPE_B_SELECT; |
256 | else if (intel_crtc->pipe == 1) |
| 257 | } |
257 | sdvox |= SDVO_PIPE_B_SELECT; |
| Line 258... | Line 258... | ||
| 258 | 258 | ||
| Line 267... | Line 267... | ||
| 267 | { |
267 | { |
| 268 | struct drm_device *dev = encoder->dev; |
268 | struct drm_device *dev = encoder->dev; |
| 269 | struct drm_i915_private *dev_priv = dev->dev_private; |
269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 270 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
270 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 271 | u32 temp; |
271 | u32 temp; |
| - | 272 | u32 enable_bits = SDVO_ENABLE; |
|
| - | 273 | ||
| - | 274 | if (intel_hdmi->has_audio) |
|
| - | 275 | enable_bits |= SDVO_AUDIO_ENABLE; |
|
| Line 272... | Line 276... | ||
| 272 | 276 | ||
| Line 273... | Line 277... | ||
| 273 | temp = I915_READ(intel_hdmi->sdvox_reg); |
277 | temp = I915_READ(intel_hdmi->sdvox_reg); |
| 274 | 278 | ||
| Line 279... | Line 283... | ||
| 279 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
283 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
| 280 | POSTING_READ(intel_hdmi->sdvox_reg); |
284 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 281 | } |
285 | } |
| Line 282... | Line 286... | ||
| 282 | 286 | ||
| 283 | if (mode != DRM_MODE_DPMS_ON) { |
287 | if (mode != DRM_MODE_DPMS_ON) { |
| 284 | temp &= ~SDVO_ENABLE; |
288 | temp &= ~enable_bits; |
| 285 | } else { |
289 | } else { |
| 286 | temp |= SDVO_ENABLE; |
290 | temp |= enable_bits; |
| Line 287... | Line 291... | ||
| 287 | } |
291 | } |
| 288 | 292 | ||
| Line 484... | Line 488... | ||
| 484 | struct drm_i915_private *dev_priv = dev->dev_private; |
488 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 485 | struct drm_connector *connector; |
489 | struct drm_connector *connector; |
| 486 | struct intel_encoder *intel_encoder; |
490 | struct intel_encoder *intel_encoder; |
| 487 | struct intel_connector *intel_connector; |
491 | struct intel_connector *intel_connector; |
| 488 | struct intel_hdmi *intel_hdmi; |
492 | struct intel_hdmi *intel_hdmi; |
| - | 493 | int i; |
|
| Line 489... | Line 494... | ||
| 489 | 494 | ||
| 490 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
495 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
| 491 | if (!intel_hdmi) |
496 | if (!intel_hdmi) |
| Line 509... | Line 514... | ||
| 509 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
514 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
| Line 510... | Line 515... | ||
| 510 | 515 | ||
| 511 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
516 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 512 | connector->interlace_allowed = 0; |
517 | connector->interlace_allowed = 0; |
| 513 | connector->doublescan_allowed = 0; |
518 | connector->doublescan_allowed = 0; |
| Line 514... | Line 519... | ||
| 514 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
519 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 515 | 520 | ||
| 516 | /* Set up the DDC bus. */ |
521 | /* Set up the DDC bus. */ |
| 517 | if (sdvox_reg == SDVOB) { |
522 | if (sdvox_reg == SDVOB) { |
| Line 536... | Line 541... | ||
| 536 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
541 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
| 537 | } |
542 | } |
| Line 538... | Line 543... | ||
| 538 | 543 | ||
| Line 539... | Line 544... | ||
| 539 | intel_hdmi->sdvox_reg = sdvox_reg; |
544 | intel_hdmi->sdvox_reg = sdvox_reg; |
| 540 | 545 | ||
| - | 546 | if (!HAS_PCH_SPLIT(dev)) { |
|
| 541 | if (!HAS_PCH_SPLIT(dev)) |
547 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
| 542 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
548 | I915_WRITE(VIDEO_DIP_CTL, 0); |
| - | 549 | } else { |
|
| - | 550 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
|
| - | 551 | for_each_pipe(i) |
|
| Line 543... | Line 552... | ||
| 543 | else |
552 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| Line 544... | Line 553... | ||
| 544 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
553 | } |