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1
/*
1
/*
2
 * Copyright © 2014 Intel Corporation
2
 * Copyright © 2014 Intel Corporation
3
 *
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
5
 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
10
 *
11
 * The above copyright notice and this permission notice (including the next
11
 * The above copyright notice and this permission notice (including the next
12
 * paragraph) shall be included in all copies or substantial portions of the
12
 * paragraph) shall be included in all copies or substantial portions of the
13
 * Software.
13
 * Software.
14
 *
14
 *
15
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
 * IN THE SOFTWARE.
21
 * IN THE SOFTWARE.
22
 */
22
 */
23
#ifndef _INTEL_GUC_FWIF_H
23
#ifndef _INTEL_GUC_FWIF_H
24
#define _INTEL_GUC_FWIF_H
24
#define _INTEL_GUC_FWIF_H
25
 
25
 
26
/*
26
/*
27
 * This file is partially autogenerated, although currently with some manual
27
 * This file is partially autogenerated, although currently with some manual
28
 * fixups afterwards. In future, it should be entirely autogenerated, in order
28
 * fixups afterwards. In future, it should be entirely autogenerated, in order
29
 * to ensure that the definitions herein remain in sync with those used by the
29
 * to ensure that the definitions herein remain in sync with those used by the
30
 * GuC's own firmware.
30
 * GuC's own firmware.
31
 *
31
 *
32
 * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
32
 * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
33
 */
33
 */
34
 
34
 
35
#define GFXCORE_FAMILY_GEN9		12
35
#define GFXCORE_FAMILY_GEN9		12
36
#define GFXCORE_FAMILY_UNKNOWN		0x7fffffff
36
#define GFXCORE_FAMILY_UNKNOWN		0x7fffffff
37
 
37
 
38
#define GUC_CTX_PRIORITY_KMD_HIGH	0
38
#define GUC_CTX_PRIORITY_KMD_HIGH	0
39
#define GUC_CTX_PRIORITY_HIGH		1
39
#define GUC_CTX_PRIORITY_HIGH		1
40
#define GUC_CTX_PRIORITY_KMD_NORMAL	2
40
#define GUC_CTX_PRIORITY_KMD_NORMAL	2
41
#define GUC_CTX_PRIORITY_NORMAL		3
41
#define GUC_CTX_PRIORITY_NORMAL		3
42
 
42
 
43
#define GUC_MAX_GPU_CONTEXTS		1024
43
#define GUC_MAX_GPU_CONTEXTS		1024
44
#define	GUC_INVALID_CTX_ID		GUC_MAX_GPU_CONTEXTS
44
#define	GUC_INVALID_CTX_ID		GUC_MAX_GPU_CONTEXTS
45
 
45
 
46
/* Work queue item header definitions */
46
/* Work queue item header definitions */
47
#define WQ_STATUS_ACTIVE		1
47
#define WQ_STATUS_ACTIVE		1
48
#define WQ_STATUS_SUSPENDED		2
48
#define WQ_STATUS_SUSPENDED		2
49
#define WQ_STATUS_CMD_ERROR		3
49
#define WQ_STATUS_CMD_ERROR		3
50
#define WQ_STATUS_ENGINE_ID_NOT_USED	4
50
#define WQ_STATUS_ENGINE_ID_NOT_USED	4
51
#define WQ_STATUS_SUSPENDED_FROM_RESET	5
51
#define WQ_STATUS_SUSPENDED_FROM_RESET	5
52
#define WQ_TYPE_SHIFT			0
52
#define WQ_TYPE_SHIFT			0
53
#define   WQ_TYPE_BATCH_BUF		(0x1 << WQ_TYPE_SHIFT)
53
#define   WQ_TYPE_BATCH_BUF		(0x1 << WQ_TYPE_SHIFT)
54
#define   WQ_TYPE_PSEUDO		(0x2 << WQ_TYPE_SHIFT)
54
#define   WQ_TYPE_PSEUDO		(0x2 << WQ_TYPE_SHIFT)
55
#define   WQ_TYPE_INORDER		(0x3 << WQ_TYPE_SHIFT)
55
#define   WQ_TYPE_INORDER		(0x3 << WQ_TYPE_SHIFT)
56
#define WQ_TARGET_SHIFT			10
56
#define WQ_TARGET_SHIFT			10
57
#define WQ_LEN_SHIFT			16
57
#define WQ_LEN_SHIFT			16
58
#define WQ_NO_WCFLUSH_WAIT		(1 << 27)
58
#define WQ_NO_WCFLUSH_WAIT		(1 << 27)
59
#define WQ_PRESENT_WORKLOAD		(1 << 28)
59
#define WQ_PRESENT_WORKLOAD		(1 << 28)
60
#define WQ_WORKLOAD_SHIFT		29
60
#define WQ_WORKLOAD_SHIFT		29
61
#define   WQ_WORKLOAD_GENERAL		(0 << WQ_WORKLOAD_SHIFT)
61
#define   WQ_WORKLOAD_GENERAL		(0 << WQ_WORKLOAD_SHIFT)
62
#define   WQ_WORKLOAD_GPGPU		(1 << WQ_WORKLOAD_SHIFT)
62
#define   WQ_WORKLOAD_GPGPU		(1 << WQ_WORKLOAD_SHIFT)
63
#define   WQ_WORKLOAD_TOUCH		(2 << WQ_WORKLOAD_SHIFT)
63
#define   WQ_WORKLOAD_TOUCH		(2 << WQ_WORKLOAD_SHIFT)
64
 
64
 
65
#define WQ_RING_TAIL_SHIFT		20
65
#define WQ_RING_TAIL_SHIFT		20
66
#define WQ_RING_TAIL_MASK		(0x7FF << WQ_RING_TAIL_SHIFT)
66
#define WQ_RING_TAIL_MASK		(0x7FF << WQ_RING_TAIL_SHIFT)
67
 
67
 
68
#define GUC_DOORBELL_ENABLED		1
68
#define GUC_DOORBELL_ENABLED		1
69
#define GUC_DOORBELL_DISABLED		0
69
#define GUC_DOORBELL_DISABLED		0
70
 
70
 
71
#define GUC_CTX_DESC_ATTR_ACTIVE	(1 << 0)
71
#define GUC_CTX_DESC_ATTR_ACTIVE	(1 << 0)
72
#define GUC_CTX_DESC_ATTR_PENDING_DB	(1 << 1)
72
#define GUC_CTX_DESC_ATTR_PENDING_DB	(1 << 1)
73
#define GUC_CTX_DESC_ATTR_KERNEL	(1 << 2)
73
#define GUC_CTX_DESC_ATTR_KERNEL	(1 << 2)
74
#define GUC_CTX_DESC_ATTR_PREEMPT	(1 << 3)
74
#define GUC_CTX_DESC_ATTR_PREEMPT	(1 << 3)
75
#define GUC_CTX_DESC_ATTR_RESET		(1 << 4)
75
#define GUC_CTX_DESC_ATTR_RESET		(1 << 4)
76
#define GUC_CTX_DESC_ATTR_WQLOCKED	(1 << 5)
76
#define GUC_CTX_DESC_ATTR_WQLOCKED	(1 << 5)
77
#define GUC_CTX_DESC_ATTR_PCH		(1 << 6)
77
#define GUC_CTX_DESC_ATTR_PCH		(1 << 6)
78
#define GUC_CTX_DESC_ATTR_TERMINATED	(1 << 7)
78
#define GUC_CTX_DESC_ATTR_TERMINATED	(1 << 7)
79
 
79
 
80
/* The guc control data is 10 DWORDs */
80
/* The guc control data is 10 DWORDs */
81
#define GUC_CTL_CTXINFO			0
81
#define GUC_CTL_CTXINFO			0
82
#define   GUC_CTL_CTXNUM_IN16_SHIFT	0
82
#define   GUC_CTL_CTXNUM_IN16_SHIFT	0
83
#define   GUC_CTL_BASE_ADDR_SHIFT	12
83
#define   GUC_CTL_BASE_ADDR_SHIFT	12
84
#define GUC_CTL_ARAT_HIGH		1
84
#define GUC_CTL_ARAT_HIGH		1
85
#define GUC_CTL_ARAT_LOW		2
85
#define GUC_CTL_ARAT_LOW		2
86
#define GUC_CTL_DEVICE_INFO		3
86
#define GUC_CTL_DEVICE_INFO		3
87
#define   GUC_CTL_GTTYPE_SHIFT		0
87
#define   GUC_CTL_GTTYPE_SHIFT		0
88
#define   GUC_CTL_COREFAMILY_SHIFT	7
88
#define   GUC_CTL_COREFAMILY_SHIFT	7
89
#define GUC_CTL_LOG_PARAMS		4
89
#define GUC_CTL_LOG_PARAMS		4
90
#define   GUC_LOG_VALID			(1 << 0)
90
#define   GUC_LOG_VALID			(1 << 0)
91
#define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
91
#define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
92
#define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
92
#define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
93
#define   GUC_LOG_CRASH_PAGES		1
93
#define   GUC_LOG_CRASH_PAGES		1
94
#define   GUC_LOG_CRASH_SHIFT		4
94
#define   GUC_LOG_CRASH_SHIFT		4
95
#define   GUC_LOG_DPC_PAGES		3
95
#define   GUC_LOG_DPC_PAGES		3
96
#define   GUC_LOG_DPC_SHIFT		6
96
#define   GUC_LOG_DPC_SHIFT		6
97
#define   GUC_LOG_ISR_PAGES		3
97
#define   GUC_LOG_ISR_PAGES		3
98
#define   GUC_LOG_ISR_SHIFT		9
98
#define   GUC_LOG_ISR_SHIFT		9
99
#define   GUC_LOG_BUF_ADDR_SHIFT	12
99
#define   GUC_LOG_BUF_ADDR_SHIFT	12
100
#define GUC_CTL_PAGE_FAULT_CONTROL	5
100
#define GUC_CTL_PAGE_FAULT_CONTROL	5
101
#define GUC_CTL_WA			6
101
#define GUC_CTL_WA			6
102
#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
102
#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
103
#define GUC_CTL_FEATURE			7
103
#define GUC_CTL_FEATURE			7
104
#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
104
#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
105
#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
105
#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
106
#define   GUC_CTL_FEATURE2		(1 << 2)
106
#define   GUC_CTL_FEATURE2		(1 << 2)
107
#define   GUC_CTL_POWER_GATING		(1 << 3)
107
#define   GUC_CTL_POWER_GATING		(1 << 3)
108
#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
108
#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
109
#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
109
#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
110
#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
110
#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
111
#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
111
#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
112
#define GUC_CTL_DEBUG			8
112
#define GUC_CTL_DEBUG			8
113
#define   GUC_LOG_VERBOSITY_SHIFT	0
113
#define   GUC_LOG_VERBOSITY_SHIFT	0
114
#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
114
#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
115
#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
115
#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
116
#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
116
#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
117
#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
117
#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
118
/* Verbosity range-check limits, without the shift */
118
/* Verbosity range-check limits, without the shift */
119
#define	  GUC_LOG_VERBOSITY_MIN		0
119
#define	  GUC_LOG_VERBOSITY_MIN		0
120
#define	  GUC_LOG_VERBOSITY_MAX		3
120
#define	  GUC_LOG_VERBOSITY_MAX		3
121
#define GUC_CTL_RSRVD			9
121
#define GUC_CTL_RSRVD			9
122
 
122
 
123
#define GUC_CTL_MAX_DWORDS		(GUC_CTL_RSRVD + 1)
123
#define GUC_CTL_MAX_DWORDS		(GUC_CTL_RSRVD + 1)
-
 
124
 
-
 
125
/**
-
 
126
 * DOC: GuC Firmware Layout
-
 
127
 *
-
 
128
 * The GuC firmware layout looks like this:
-
 
129
 *
-
 
130
 *     +-------------------------------+
-
 
131
 *     |        guc_css_header         |
-
 
132
 *     | contains major/minor version  |
-
 
133
 *     +-------------------------------+
-
 
134
 *     |             uCode             |
-
 
135
 *     +-------------------------------+
-
 
136
 *     |         RSA signature         |
-
 
137
 *     +-------------------------------+
-
 
138
 *     |          modulus key          |
-
 
139
 *     +-------------------------------+
-
 
140
 *     |          exponent val         |
-
 
141
 *     +-------------------------------+
-
 
142
 *
-
 
143
 * The firmware may or may not have modulus key and exponent data. The header,
-
 
144
 * uCode and RSA signature are must-have components that will be used by driver.
-
 
145
 * Length of each components, which is all in dwords, can be found in header.
-
 
146
 * In the case that modulus and exponent are not present in fw, a.k.a truncated
-
 
147
 * image, the length value still appears in header.
-
 
148
 *
-
 
149
 * Driver will do some basic fw size validation based on the following rules:
-
 
150
 *
-
 
151
 * 1. Header, uCode and RSA are must-have components.
-
 
152
 * 2. All firmware components, if they present, are in the sequence illustrated
-
 
153
 * in the layout table above.
-
 
154
 * 3. Length info of each component can be found in header, in dwords.
-
 
155
 * 4. Modulus and exponent key are not required by driver. They may not appear
-
 
156
 * in fw. So driver will load a truncated firmware in this case.
-
 
157
 */
-
 
158
 
-
 
159
struct guc_css_header {
-
 
160
	uint32_t module_type;
-
 
161
	/* header_size includes all non-uCode bits, including css_header, rsa
-
 
162
	 * key, modulus key and exponent data. */
-
 
163
	uint32_t header_size_dw;
-
 
164
	uint32_t header_version;
-
 
165
	uint32_t module_id;
-
 
166
	uint32_t module_vendor;
-
 
167
	union {
-
 
168
		struct {
-
 
169
			uint8_t day;
-
 
170
			uint8_t month;
-
 
171
			uint16_t year;
-
 
172
		};
-
 
173
		uint32_t date;
-
 
174
	};
-
 
175
	uint32_t size_dw; /* uCode plus header_size_dw */
-
 
176
	uint32_t key_size_dw;
-
 
177
	uint32_t modulus_size_dw;
-
 
178
	uint32_t exponent_size_dw;
-
 
179
	union {
-
 
180
		struct {
-
 
181
			uint8_t hour;
-
 
182
			uint8_t min;
-
 
183
			uint16_t sec;
-
 
184
		};
-
 
185
		uint32_t time;
-
 
186
	};
-
 
187
 
-
 
188
	char username[8];
-
 
189
	char buildnumber[12];
-
 
190
	uint32_t device_id;
-
 
191
	uint32_t guc_sw_version;
-
 
192
	uint32_t prod_preprod_fw;
-
 
193
	uint32_t reserved[12];
-
 
194
	uint32_t header_info;
-
 
195
} __packed;
124
 
196
 
125
struct guc_doorbell_info {
197
struct guc_doorbell_info {
126
	u32 db_status;
198
	u32 db_status;
127
	u32 cookie;
199
	u32 cookie;
128
	u32 reserved[14];
200
	u32 reserved[14];
129
} __packed;
201
} __packed;
130
 
202
 
131
union guc_doorbell_qw {
203
union guc_doorbell_qw {
132
	struct {
204
	struct {
133
		u32 db_status;
205
		u32 db_status;
134
		u32 cookie;
206
		u32 cookie;
135
	};
207
	};
136
	u64 value_qw;
208
	u64 value_qw;
137
} __packed;
209
} __packed;
138
 
210
 
139
#define GUC_MAX_DOORBELLS		256
211
#define GUC_MAX_DOORBELLS		256
140
#define GUC_INVALID_DOORBELL_ID		(GUC_MAX_DOORBELLS)
212
#define GUC_INVALID_DOORBELL_ID		(GUC_MAX_DOORBELLS)
141
 
213
 
142
#define GUC_DB_SIZE			(PAGE_SIZE)
214
#define GUC_DB_SIZE			(PAGE_SIZE)
143
#define GUC_WQ_SIZE			(PAGE_SIZE * 2)
215
#define GUC_WQ_SIZE			(PAGE_SIZE * 2)
144
 
216
 
145
/* Work item for submitting workloads into work queue of GuC. */
217
/* Work item for submitting workloads into work queue of GuC. */
146
struct guc_wq_item {
218
struct guc_wq_item {
147
	u32 header;
219
	u32 header;
148
	u32 context_desc;
220
	u32 context_desc;
149
	u32 ring_tail;
221
	u32 ring_tail;
150
	u32 fence_id;
222
	u32 fence_id;
151
} __packed;
223
} __packed;
152
 
224
 
153
struct guc_process_desc {
225
struct guc_process_desc {
154
	u32 context_id;
226
	u32 context_id;
155
	u64 db_base_addr;
227
	u64 db_base_addr;
156
	u32 head;
228
	u32 head;
157
	u32 tail;
229
	u32 tail;
158
	u32 error_offset;
230
	u32 error_offset;
159
	u64 wq_base_addr;
231
	u64 wq_base_addr;
160
	u32 wq_size_bytes;
232
	u32 wq_size_bytes;
161
	u32 wq_status;
233
	u32 wq_status;
162
	u32 engine_presence;
234
	u32 engine_presence;
163
	u32 priority;
235
	u32 priority;
164
	u32 reserved[30];
236
	u32 reserved[30];
165
} __packed;
237
} __packed;
166
 
238
 
167
/* engine id and context id is packed into guc_execlist_context.context_id*/
239
/* engine id and context id is packed into guc_execlist_context.context_id*/
168
#define GUC_ELC_CTXID_OFFSET		0
240
#define GUC_ELC_CTXID_OFFSET		0
169
#define GUC_ELC_ENGINE_OFFSET		29
241
#define GUC_ELC_ENGINE_OFFSET		29
170
 
242
 
171
/* The execlist context including software and HW information */
243
/* The execlist context including software and HW information */
172
struct guc_execlist_context {
244
struct guc_execlist_context {
173
	u32 context_desc;
245
	u32 context_desc;
174
	u32 context_id;
246
	u32 context_id;
175
	u32 ring_status;
247
	u32 ring_status;
176
	u32 ring_lcra;
248
	u32 ring_lcra;
177
	u32 ring_begin;
249
	u32 ring_begin;
178
	u32 ring_end;
250
	u32 ring_end;
179
	u32 ring_next_free_location;
251
	u32 ring_next_free_location;
180
	u32 ring_current_tail_pointer_value;
252
	u32 ring_current_tail_pointer_value;
181
	u8 engine_state_submit_value;
253
	u8 engine_state_submit_value;
182
	u8 engine_state_wait_value;
254
	u8 engine_state_wait_value;
183
	u16 pagefault_count;
255
	u16 pagefault_count;
184
	u16 engine_submit_queue_count;
256
	u16 engine_submit_queue_count;
185
} __packed;
257
} __packed;
186
 
258
 
187
/*Context descriptor for communicating between uKernel and Driver*/
259
/*Context descriptor for communicating between uKernel and Driver*/
188
struct guc_context_desc {
260
struct guc_context_desc {
189
	u32 sched_common_area;
261
	u32 sched_common_area;
190
	u32 context_id;
262
	u32 context_id;
191
	u32 pas_id;
263
	u32 pas_id;
192
	u8 engines_used;
264
	u8 engines_used;
193
	u64 db_trigger_cpu;
265
	u64 db_trigger_cpu;
194
	u32 db_trigger_uk;
266
	u32 db_trigger_uk;
195
	u64 db_trigger_phy;
267
	u64 db_trigger_phy;
196
	u16 db_id;
268
	u16 db_id;
197
 
269
 
198
	struct guc_execlist_context lrc[I915_NUM_RINGS];
270
	struct guc_execlist_context lrc[I915_NUM_RINGS];
199
 
271
 
200
	u8 attribute;
272
	u8 attribute;
201
 
273
 
202
	u32 priority;
274
	u32 priority;
203
 
275
 
204
	u32 wq_sampled_tail_offset;
276
	u32 wq_sampled_tail_offset;
205
	u32 wq_total_submit_enqueues;
277
	u32 wq_total_submit_enqueues;
206
 
278
 
207
	u32 process_desc;
279
	u32 process_desc;
208
	u32 wq_addr;
280
	u32 wq_addr;
209
	u32 wq_size;
281
	u32 wq_size;
210
 
282
 
211
	u32 engine_presence;
283
	u32 engine_presence;
212
 
284
 
213
	u8 engine_suspended;
285
	u8 engine_suspended;
214
 
286
 
215
	u8 reserved0[3];
287
	u8 reserved0[3];
216
	u64 reserved1[1];
288
	u64 reserved1[1];
217
 
289
 
218
	u64 desc_private;
290
	u64 desc_private;
219
} __packed;
291
} __packed;
220
 
292
 
221
#define GUC_FORCEWAKE_RENDER	(1 << 0)
293
#define GUC_FORCEWAKE_RENDER	(1 << 0)
222
#define GUC_FORCEWAKE_MEDIA	(1 << 1)
294
#define GUC_FORCEWAKE_MEDIA	(1 << 1)
223
 
295
 
224
#define GUC_POWER_UNSPECIFIED	0
296
#define GUC_POWER_UNSPECIFIED	0
225
#define GUC_POWER_D0		1
297
#define GUC_POWER_D0		1
226
#define GUC_POWER_D1		2
298
#define GUC_POWER_D1		2
227
#define GUC_POWER_D2		3
299
#define GUC_POWER_D2		3
228
#define GUC_POWER_D3		4
300
#define GUC_POWER_D3		4
229
 
301
 
230
/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
302
/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
231
enum host2guc_action {
303
enum host2guc_action {
232
	HOST2GUC_ACTION_DEFAULT = 0x0,
304
	HOST2GUC_ACTION_DEFAULT = 0x0,
233
	HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
305
	HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
234
	HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
306
	HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
235
	HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
307
	HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
236
	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
308
	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
237
	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
309
	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
238
	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
310
	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
239
	HOST2GUC_ACTION_LIMIT
311
	HOST2GUC_ACTION_LIMIT
240
};
312
};
241
 
313
 
242
/*
314
/*
243
 * The GuC sends its response to a command by overwriting the
315
 * The GuC sends its response to a command by overwriting the
244
 * command in SS0. The response is distinguishable from a command
316
 * command in SS0. The response is distinguishable from a command
245
 * by the fact that all the MASK bits are set. The remaining bits
317
 * by the fact that all the MASK bits are set. The remaining bits
246
 * give more detail.
318
 * give more detail.
247
 */
319
 */
248
#define	GUC2HOST_RESPONSE_MASK		((u32)0xF0000000)
320
#define	GUC2HOST_RESPONSE_MASK		((u32)0xF0000000)
249
#define	GUC2HOST_IS_RESPONSE(x) 	((u32)(x) >= GUC2HOST_RESPONSE_MASK)
321
#define	GUC2HOST_IS_RESPONSE(x) 	((u32)(x) >= GUC2HOST_RESPONSE_MASK)
250
#define	GUC2HOST_STATUS(x)		(GUC2HOST_RESPONSE_MASK | (x))
322
#define	GUC2HOST_STATUS(x)		(GUC2HOST_RESPONSE_MASK | (x))
251
 
323
 
252
/* GUC will return status back to SOFT_SCRATCH_O_REG */
324
/* GUC will return status back to SOFT_SCRATCH_O_REG */
253
enum guc2host_status {
325
enum guc2host_status {
254
	GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
326
	GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
255
	GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
327
	GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
256
	GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
328
	GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
257
	GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
329
	GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
258
};
330
};
259
 
331
 
260
#endif
332
#endif