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Rev 6937 | Rev 7144 | ||
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Line 28... | Line 28... | ||
28 | #include |
28 | #include |
29 | #include "intel_drv.h" |
29 | #include "intel_drv.h" |
30 | #include "i915_drv.h" |
30 | #include "i915_drv.h" |
31 | #include "intel_dsi.h" |
31 | #include "intel_dsi.h" |
Line 32... | Line -... | ||
32 | - | ||
33 | #define DSI_HSS_PACKET_SIZE 4 |
- | |
34 | #define DSI_HSE_PACKET_SIZE 4 |
- | |
35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 |
- | |
36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 |
- | |
37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 |
- | |
38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 |
- | |
39 | #define DSI_EOTP_PACKET_SIZE 4 |
- | |
40 | 32 | ||
41 | static int dsi_pixel_format_bpp(int pixel_format) |
33 | int dsi_pixel_format_bpp(int pixel_format) |
42 | { |
34 | { |
Line 43... | Line 35... | ||
43 | int bpp; |
35 | int bpp; |
44 | 36 | ||
Line 69... | Line 61... | ||
69 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
61 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
70 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
62 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
71 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ |
63 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ |
72 | }; |
64 | }; |
Line 73... | Line -... | ||
73 | - | ||
74 | #ifdef DSI_CLK_FROM_RR |
- | |
75 | - | ||
76 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
- | |
77 | int pixel_format, int video_mode_format, |
- | |
78 | int lane_count, bool eotp) |
- | |
79 | { |
- | |
80 | u32 bpp; |
- | |
81 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; |
- | |
82 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; |
- | |
83 | u32 bytes_per_line, bytes_per_frame; |
- | |
84 | u32 num_frames; |
- | |
85 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; |
- | |
86 | u32 dsi_bit_clock_hz; |
- | |
87 | u32 dsi_clk; |
- | |
88 | - | ||
89 | bpp = dsi_pixel_format_bpp(pixel_format); |
- | |
90 | - | ||
91 | hactive = mode->hdisplay; |
- | |
92 | vactive = mode->vdisplay; |
- | |
93 | hfp = mode->hsync_start - mode->hdisplay; |
- | |
94 | hsync = mode->hsync_end - mode->hsync_start; |
- | |
95 | hbp = mode->htotal - mode->hsync_end; |
- | |
96 | - | ||
97 | vfp = mode->vsync_start - mode->vdisplay; |
- | |
98 | vsync = mode->vsync_end - mode->vsync_start; |
- | |
99 | vbp = mode->vtotal - mode->vsync_end; |
- | |
100 | - | ||
101 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); |
- | |
102 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); |
- | |
103 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); |
- | |
104 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); |
- | |
105 | - | ||
106 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + |
- | |
107 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + |
- | |
108 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + |
- | |
109 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + |
- | |
110 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; |
- | |
111 | - | ||
112 | /* |
- | |
113 | * XXX: Need to accurately calculate LP to HS transition timeout and add |
- | |
114 | * it to bytes_per_line/bytes_per_frame. |
- | |
115 | */ |
- | |
116 | - | ||
117 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
- | |
118 | bytes_per_line += DSI_EOTP_PACKET_SIZE; |
- | |
119 | - | ||
120 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + |
- | |
121 | vactive * bytes_per_line + vfp * bytes_per_line; |
- | |
122 | - | ||
123 | if (eotp && |
- | |
124 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || |
- | |
125 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) |
- | |
126 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; |
- | |
127 | - | ||
128 | num_frames = drm_mode_vrefresh(mode); |
- | |
129 | bytes_per_x_frames = num_frames * bytes_per_frame; |
- | |
130 | - | ||
131 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; |
- | |
132 | - | ||
133 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ |
- | |
134 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; |
- | |
135 | dsi_clk = dsi_bit_clock_hz / 1000; |
- | |
136 | - | ||
137 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
- | |
138 | dsi_clk *= 2; |
- | |
139 | - | ||
140 | return dsi_clk; |
- | |
141 | } |
- | |
142 | - | ||
143 | #else |
- | |
144 | 65 | ||
145 | /* Get DSI clock from pixel clock */ |
66 | /* Get DSI clock from pixel clock */ |
146 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
67 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
147 | { |
68 | { |
148 | u32 dsi_clk_khz; |
69 | u32 dsi_clk_khz; |
Line 153... | Line 74... | ||
153 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
74 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
Line 154... | Line 75... | ||
154 | 75 | ||
155 | return dsi_clk_khz; |
76 | return dsi_clk_khz; |
Line 156... | Line -... | ||
156 | } |
- | |
157 | - | ||
158 | #endif |
77 | } |
159 | 78 | ||
160 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
79 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
161 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) |
80 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) |
162 | { |
81 | { |
Line 320... | Line 239... | ||
320 | WARN(bpp != pipe_bpp, |
239 | WARN(bpp != pipe_bpp, |
321 | "bpp match assertion failure (expected %d, current %d)\n", |
240 | "bpp match assertion failure (expected %d, current %d)\n", |
322 | bpp, pipe_bpp); |
241 | bpp, pipe_bpp); |
323 | } |
242 | } |
Line 324... | Line 243... | ||
324 | 243 | ||
325 | u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
244 | static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
326 | { |
245 | { |
327 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
246 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
328 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
247 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
329 | u32 dsi_clock, pclk; |
248 | u32 dsi_clock, pclk; |
Line 382... | Line 301... | ||
382 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); |
301 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); |
Line 383... | Line 302... | ||
383 | 302 | ||
384 | return pclk; |
303 | return pclk; |
Line 385... | Line 304... | ||
385 | } |
304 | } |
386 | 305 | ||
387 | u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
306 | static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
388 | { |
307 | { |
389 | u32 pclk; |
308 | u32 pclk; |
390 | u32 dsi_clk; |
309 | u32 dsi_clk; |
Line 417... | Line 336... | ||
417 | 336 | ||
418 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); |
337 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); |
419 | return pclk; |
338 | return pclk; |
Line -... | Line 339... | ||
- | 339 | } |
|
- | 340 | ||
- | 341 | u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
|
- | 342 | { |
|
- | 343 | if (IS_BROXTON(encoder->base.dev)) |
|
- | 344 | return bxt_dsi_get_pclk(encoder, pipe_bpp); |
|
- | 345 | else |
|
- | 346 | return vlv_dsi_get_pclk(encoder, pipe_bpp); |
|
420 | } |
347 | } |
421 | 348 | ||
422 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
349 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
423 | { |
350 | { |
424 | u32 temp; |
351 | u32 temp; |