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static int dsi_pixel_format_bpp(int pixel_format)

{

	int bpp;

	switch (pixel_format) {

	default:

	case VID_MODE_FORMAT_RGB888:

	case VID_MODE_FORMAT_RGB666_LOOSE:

		bpp = 24;

		break;

	case VID_MODE_FORMAT_RGB666:

		bpp = 18;

		break;

	case VID_MODE_FORMAT_RGB565:

		bpp = 16;

		break;

	}

	return bpp;

}

}

	/* target_dsi_clk is expected in kHz */

	if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {

		DRM_ERROR("DSI CLK Out of Range\n");

		return -ECHRNG;

	}

		m_max = 96;

	} else {

		ref_clk = 25000;

		n = 1;

		m_min = 62;

		m_max = 92;

	}

			int d = abs(target_dsi_clk - calc_dsi_clk);

			if (d < delta) {

		return;

	if (intel_dsi->ports & (1 << PORT_A))

		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

	mutex_lock(&dev_priv->sb_lock);

	usleep_range(1, 10);

}

static void bxt_disable_dsi_pll(struct intel_encoder *encoder)

{

	/* mask out other bits and extract the P1 divisor */

	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;

	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);

	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);

	return pclk;

}

u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)

{

	u32 pclk;

	u32 dsi_clk;

	u32 dsi_ratio;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	/* Divide by zero */

	if (!pipe_bpp) {

		DRM_ERROR("Invalid BPP(0)\n");

		return 0;

	}

	dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &

				BXT_DSI_PLL_RATIO_MASK;

	/* Invalid DSI ratio ? */

	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||

			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {

		DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);

		return 0;

	}

	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;

	/* pixel_format and pipe_bpp should agree */

	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);

	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);

	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);

	return pclk;

}

static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	u32 temp;

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	temp = I915_READ(MIPI_CTRL(port));

	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;

	I915_WRITE(MIPI_CTRL(port), temp |

			intel_dsi->escape_clk_div <<

			ESCAPE_CLOCK_DIVIDER_SHIFT);

}

/* Program BXT Mipi clocks and dividers */

static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)

{

	u32 tmp;

	u32 divider;

	u32 dsi_rate;

	u32 pll_ratio;

	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Clear old configurations */

	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);

	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));

	tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));

	tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));

	tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));

	/* Get the current DSI rate(actual) */

	pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &

				BXT_DSI_PLL_RATIO_MASK;

	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;

	/* Max possible output of clock is 39.5 MHz, program value -1 */

	divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;

	tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);

	/*

	 * Tx escape clock must be as close to 20MHz possible, but should

	 * not exceed it. Hence select divide by 2

	 */

	tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);

	tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);

	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);

}

static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	u8 dsi_ratio;

	u32 dsi_clk;

	u32 val;

	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,

			intel_dsi->lane_count);

	/*

	 * From clock diagram, to get PLL ratio divider, divide double of DSI

	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to

	 * round 'up' the result

	 */

	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);

	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||

			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {

		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");

		return false;

	}

	/*

	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x

	 * Spec says both have to be programmed, even if one is not getting

	 * used. Configure MIPI_CLOCK_CTL dividers in modeset

	 */

	val = I915_READ(BXT_DSI_PLL_CTL);

	val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;

	val &= ~BXT_DSI_FREQ_SEL_MASK;

	val &= ~BXT_DSI_PLL_RATIO_MASK;

	val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);

	/* As per recommendation from hardware team,

	 * Prog PVD ratio =1 if dsi ratio <= 50

	 */

	if (dsi_ratio <= 50) {

		val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;

		val |= BXT_DSI_PLL_PVD_RATIO_1;

	}

	I915_WRITE(BXT_DSI_PLL_CTL, val);

	POSTING_READ(BXT_DSI_PLL_CTL);

	return true;

}

static void bxt_enable_dsi_pll(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	enum port port;

	u32 val;

	DRM_DEBUG_KMS("\n");

	val = I915_READ(BXT_DSI_PLL_ENABLE);

	if (val & BXT_DSI_PLL_DO_ENABLE) {

		WARN(1, "DSI PLL already enabled. Disabling it.\n");

		val &= ~BXT_DSI_PLL_DO_ENABLE;

		I915_WRITE(BXT_DSI_PLL_ENABLE, val);

	}

	/* Configure PLL vales */

	if (!bxt_configure_dsi_pll(encoder)) {

		DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");

		return;

	}

	/* Program TX, RX, Dphy clocks */

	for_each_dsi_port(port, intel_dsi->ports)

		bxt_dsi_program_clocks(encoder->base.dev, port);

	/* Enable DSI PLL */

	val = I915_READ(BXT_DSI_PLL_ENABLE);

	val |= BXT_DSI_PLL_DO_ENABLE;

	I915_WRITE(BXT_DSI_PLL_ENABLE, val);

	/* Timeout and fail if PLL not locked */

	if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {

		DRM_ERROR("Timed out waiting for DSI PLL to lock\n");

		return;

	}

	DRM_DEBUG_KMS("DSI PLL locked\n");

}

void intel_enable_dsi_pll(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	if (IS_VALLEYVIEW(dev))

		vlv_enable_dsi_pll(encoder);

	else if (IS_BROXTON(dev))

		bxt_enable_dsi_pll(encoder);

}

void intel_disable_dsi_pll(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	if (IS_VALLEYVIEW(dev))

		vlv_disable_dsi_pll(encoder);

	else if (IS_BROXTON(dev))

		bxt_disable_dsi_pll(encoder);

}

static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	u32 tmp;

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Clear old configurations */

	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);

	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));

	tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));

	tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));

	tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));

	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);

	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);

}

void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	struct drm_device *dev = encoder->base.dev;