Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6937 | Rev 7144 | ||
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Line 476... | Line 476... | ||
476 | enum port port; |
476 | enum port port; |
477 | u32 tmp; |
477 | u32 tmp; |
Line 478... | Line 478... | ||
478 | 478 | ||
Line 479... | Line -... | ||
479 | DRM_DEBUG_KMS("\n"); |
- | |
480 | 479 | DRM_DEBUG_KMS("\n"); |
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- | 480 | ||
Line 481... | Line 481... | ||
481 | intel_dsi_prepare(encoder); |
481 | intel_enable_dsi_pll(encoder); |
482 | intel_enable_dsi_pll(encoder); |
482 | intel_dsi_prepare(encoder); |
483 | 483 | ||
Line 632... | Line 632... | ||
632 | 632 | ||
633 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
633 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
634 | { |
634 | { |
635 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
635 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
636 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
- | |
Line 637... | Line 636... | ||
637 | u32 val; |
636 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Line 638... | Line 637... | ||
638 | 637 | ||
Line 639... | Line 638... | ||
639 | DRM_DEBUG_KMS("\n"); |
638 | DRM_DEBUG_KMS("\n"); |
Line -... | Line 639... | ||
- | 639 | ||
- | 640 | intel_dsi_disable(encoder); |
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- | 641 | ||
640 | 642 | intel_dsi_clear_device_ready(encoder); |
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641 | intel_dsi_disable(encoder); |
643 | |
642 | 644 | if (!IS_BROXTON(dev_priv)) { |
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- | 645 | u32 val; |
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Line 643... | Line 646... | ||
643 | intel_dsi_clear_device_ready(encoder); |
646 | |
Line 644... | Line 647... | ||
644 | 647 | val = I915_READ(DSPCLK_GATE_D); |
|
645 | val = I915_READ(DSPCLK_GATE_D); |
648 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
Line 707... | Line 710... | ||
707 | } |
710 | } |
Line 708... | Line 711... | ||
708 | 711 | ||
709 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
712 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
710 | struct intel_crtc_state *pipe_config) |
713 | struct intel_crtc_state *pipe_config) |
711 | { |
714 | { |
712 | u32 pclk = 0; |
715 | u32 pclk; |
Line 713... | Line 716... | ||
713 | DRM_DEBUG_KMS("\n"); |
716 | DRM_DEBUG_KMS("\n"); |
Line 714... | Line 717... | ||
714 | 717 | ||
715 | pipe_config->has_dsi_encoder = true; |
718 | pipe_config->has_dsi_encoder = true; |
716 | 719 | ||
717 | /* |
720 | /* |
718 | * DPLL_MD is not used in case of DSI, reading will get some default value |
721 | * DPLL_MD is not used in case of DSI, reading will get some default value |
Line 719... | Line -... | ||
719 | * set dpll_md = 0 |
- | |
720 | */ |
722 | * set dpll_md = 0 |
721 | pipe_config->dpll_hw_state.dpll_md = 0; |
- | |
722 | - | ||
723 | if (IS_BROXTON(encoder->base.dev)) |
- | |
724 | pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
- | |
725 | else if (IS_VALLEYVIEW(encoder->base.dev) || |
723 | */ |
726 | IS_CHERRYVIEW(encoder->base.dev)) |
724 | pipe_config->dpll_hw_state.dpll_md = 0; |
Line 727... | Line 725... | ||
727 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
725 | |
728 | 726 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); |
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Line 785... | Line 783... | ||
785 | static void set_dsi_timings(struct drm_encoder *encoder, |
783 | static void set_dsi_timings(struct drm_encoder *encoder, |
786 | const struct drm_display_mode *adjusted_mode) |
784 | const struct drm_display_mode *adjusted_mode) |
787 | { |
785 | { |
788 | struct drm_device *dev = encoder->dev; |
786 | struct drm_device *dev = encoder->dev; |
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
790 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
- | |
791 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
788 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
792 | enum port port; |
789 | enum port port; |
793 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
790 | unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format); |
794 | unsigned int lane_count = intel_dsi->lane_count; |
791 | unsigned int lane_count = intel_dsi->lane_count; |
Line 795... | Line 792... | ||
795 | 792 | ||
Line 796... | Line 793... | ||
796 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
793 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
Line 859... | Line 856... | ||
859 | struct drm_i915_private *dev_priv = dev->dev_private; |
856 | struct drm_i915_private *dev_priv = dev->dev_private; |
860 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
857 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
861 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
858 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
862 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
859 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
863 | enum port port; |
860 | enum port port; |
864 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
861 | unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format); |
865 | u32 val, tmp; |
862 | u32 val, tmp; |
866 | u16 mode_hdisplay; |
863 | u16 mode_hdisplay; |
Line 867... | Line 864... | ||
867 | 864 |