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1 | /* |
1 | /* |
2 | * Copyright © 2013 Intel Corporation |
2 | * Copyright © 2013 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Author: Jani Nikula |
23 | * Author: Jani Nikula |
24 | */ |
24 | */ |
25 | 25 | ||
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "i915_drv.h" |
31 | #include "i915_drv.h" |
32 | #include "intel_drv.h" |
32 | #include "intel_drv.h" |
33 | #include "intel_dsi.h" |
33 | #include "intel_dsi.h" |
34 | #include "intel_dsi_cmd.h" |
34 | #include "intel_dsi_cmd.h" |
35 | 35 | ||
36 | /* the sub-encoders aka panel drivers */ |
36 | /* the sub-encoders aka panel drivers */ |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { |
38 | { |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
40 | .name = "vbt-generic-dsi-vid-mode-display", |
40 | .name = "vbt-generic-dsi-vid-mode-display", |
41 | .dev_ops = &vbt_generic_dsi_display_ops, |
41 | .dev_ops = &vbt_generic_dsi_display_ops, |
42 | }, |
42 | }, |
43 | }; |
43 | }; |
44 | 44 | ||
45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
46 | { |
46 | { |
47 | mutex_lock(&dev_priv->dpio_lock); |
47 | mutex_lock(&dev_priv->dpio_lock); |
48 | 48 | ||
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
52 | udelay(150); |
52 | udelay(150); |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
55 | 55 | ||
56 | mutex_unlock(&dev_priv->dpio_lock); |
56 | mutex_unlock(&dev_priv->dpio_lock); |
57 | } |
57 | } |
58 | 58 | ||
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
60 | { |
60 | { |
61 | return container_of(intel_attached_encoder(connector), |
61 | return container_of(intel_attached_encoder(connector), |
62 | struct intel_dsi, base); |
62 | struct intel_dsi, base); |
63 | } |
63 | } |
64 | 64 | ||
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
66 | { |
66 | { |
67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
68 | } |
68 | } |
69 | 69 | ||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
71 | { |
71 | { |
72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
73 | } |
73 | } |
74 | 74 | ||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
76 | { |
76 | { |
77 | DRM_DEBUG_KMS("\n"); |
77 | DRM_DEBUG_KMS("\n"); |
78 | } |
78 | } |
79 | 79 | ||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
81 | struct intel_crtc_config *config) |
81 | struct intel_crtc_config *config) |
82 | { |
82 | { |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
84 | base); |
84 | base); |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; |
88 | struct drm_display_mode *mode = &config->requested_mode; |
88 | struct drm_display_mode *mode = &config->requested_mode; |
89 | 89 | ||
90 | DRM_DEBUG_KMS("\n"); |
90 | DRM_DEBUG_KMS("\n"); |
91 | 91 | ||
92 | if (fixed_mode) |
92 | if (fixed_mode) |
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
94 | 94 | ||
95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
96 | adjusted_mode->flags = 0; |
96 | adjusted_mode->flags = 0; |
97 | 97 | ||
98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, |
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, |
100 | mode, adjusted_mode); |
100 | mode, adjusted_mode); |
101 | 101 | ||
102 | return true; |
102 | return true; |
103 | } |
103 | } |
104 | 104 | ||
105 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
105 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
106 | { |
106 | { |
107 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
107 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
108 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
108 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
109 | int pipe = intel_crtc->pipe; |
109 | int pipe = intel_crtc->pipe; |
110 | u32 val; |
110 | u32 val; |
111 | 111 | ||
112 | DRM_DEBUG_KMS("\n"); |
112 | DRM_DEBUG_KMS("\n"); |
113 | 113 | ||
114 | mutex_lock(&dev_priv->dpio_lock); |
114 | mutex_lock(&dev_priv->dpio_lock); |
115 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
115 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
116 | * needed everytime after power gate */ |
116 | * needed everytime after power gate */ |
117 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
117 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
118 | mutex_unlock(&dev_priv->dpio_lock); |
118 | mutex_unlock(&dev_priv->dpio_lock); |
119 | 119 | ||
120 | /* bandgap reset is needed after everytime we do power gate */ |
120 | /* bandgap reset is needed after everytime we do power gate */ |
121 | band_gap_reset(dev_priv); |
121 | band_gap_reset(dev_priv); |
122 | 122 | ||
123 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
123 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
124 | usleep_range(2500, 3000); |
124 | usleep_range(2500, 3000); |
125 | 125 | ||
126 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
126 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
127 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
127 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
128 | usleep_range(1000, 1500); |
128 | usleep_range(1000, 1500); |
129 | 129 | ||
130 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
130 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
131 | usleep_range(2500, 3000); |
131 | usleep_range(2500, 3000); |
132 | 132 | ||
133 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
133 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
134 | usleep_range(2500, 3000); |
134 | usleep_range(2500, 3000); |
135 | } |
135 | } |
136 | 136 | ||
137 | static void intel_dsi_enable(struct intel_encoder *encoder) |
137 | static void intel_dsi_enable(struct intel_encoder *encoder) |
138 | { |
138 | { |
139 | struct drm_device *dev = encoder->base.dev; |
139 | struct drm_device *dev = encoder->base.dev; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
141 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
141 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
142 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
142 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
143 | int pipe = intel_crtc->pipe; |
143 | int pipe = intel_crtc->pipe; |
144 | u32 temp; |
144 | u32 temp; |
145 | 145 | ||
146 | DRM_DEBUG_KMS("\n"); |
146 | DRM_DEBUG_KMS("\n"); |
147 | 147 | ||
148 | if (is_cmd_mode(intel_dsi)) |
148 | if (is_cmd_mode(intel_dsi)) |
149 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); |
149 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); |
150 | else { |
150 | else { |
151 | msleep(20); /* XXX */ |
151 | msleep(20); /* XXX */ |
152 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
152 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
153 | msleep(100); |
153 | msleep(100); |
154 | 154 | ||
155 | if (intel_dsi->dev.dev_ops->enable) |
155 | if (intel_dsi->dev.dev_ops->enable) |
156 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); |
156 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); |
157 | 157 | ||
158 | wait_for_dsi_fifo_empty(intel_dsi); |
158 | wait_for_dsi_fifo_empty(intel_dsi); |
159 | 159 | ||
160 | /* assert ip_tg_enable signal */ |
160 | /* assert ip_tg_enable signal */ |
161 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
161 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
162 | temp = temp | intel_dsi->port_bits; |
162 | temp = temp | intel_dsi->port_bits; |
163 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
163 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
164 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
164 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
165 | } |
165 | } |
166 | } |
166 | } |
167 | 167 | ||
168 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
168 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
169 | { |
169 | { |
170 | struct drm_device *dev = encoder->base.dev; |
170 | struct drm_device *dev = encoder->base.dev; |
171 | struct drm_i915_private *dev_priv = dev->dev_private; |
171 | struct drm_i915_private *dev_priv = dev->dev_private; |
172 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
172 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
173 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
173 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
174 | enum pipe pipe = intel_crtc->pipe; |
174 | enum pipe pipe = intel_crtc->pipe; |
175 | u32 tmp; |
175 | u32 tmp; |
176 | 176 | ||
177 | DRM_DEBUG_KMS("\n"); |
177 | DRM_DEBUG_KMS("\n"); |
178 | 178 | ||
179 | /* Disable DPOunit clock gating, can stall pipe |
179 | /* Disable DPOunit clock gating, can stall pipe |
180 | * and we need DPLL REFA always enabled */ |
180 | * and we need DPLL REFA always enabled */ |
181 | tmp = I915_READ(DPLL(pipe)); |
181 | tmp = I915_READ(DPLL(pipe)); |
182 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; |
182 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; |
183 | I915_WRITE(DPLL(pipe), tmp); |
183 | I915_WRITE(DPLL(pipe), tmp); |
184 | 184 | ||
185 | /* update the hw state for DPLL */ |
185 | /* update the hw state for DPLL */ |
186 | intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
186 | intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
187 | DPLL_REFA_CLK_ENABLE_VLV; |
187 | DPLL_REFA_CLK_ENABLE_VLV; |
188 | 188 | ||
189 | tmp = I915_READ(DSPCLK_GATE_D); |
189 | tmp = I915_READ(DSPCLK_GATE_D); |
190 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
190 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
191 | I915_WRITE(DSPCLK_GATE_D, tmp); |
191 | I915_WRITE(DSPCLK_GATE_D, tmp); |
192 | 192 | ||
193 | /* put device in ready state */ |
193 | /* put device in ready state */ |
194 | intel_dsi_device_ready(encoder); |
194 | intel_dsi_device_ready(encoder); |
195 | 195 | ||
196 | msleep(intel_dsi->panel_on_delay); |
196 | msleep(intel_dsi->panel_on_delay); |
197 | 197 | ||
198 | if (intel_dsi->dev.dev_ops->panel_reset) |
198 | if (intel_dsi->dev.dev_ops->panel_reset) |
199 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); |
199 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); |
200 | 200 | ||
201 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
201 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
202 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); |
202 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); |
203 | 203 | ||
204 | wait_for_dsi_fifo_empty(intel_dsi); |
204 | wait_for_dsi_fifo_empty(intel_dsi); |
205 | 205 | ||
206 | /* Enable port in pre-enable phase itself because as per hw team |
206 | /* Enable port in pre-enable phase itself because as per hw team |
207 | * recommendation, port should be enabled befor plane & pipe */ |
207 | * recommendation, port should be enabled befor plane & pipe */ |
208 | intel_dsi_enable(encoder); |
208 | intel_dsi_enable(encoder); |
209 | } |
209 | } |
210 | 210 | ||
211 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
211 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
212 | { |
212 | { |
213 | DRM_DEBUG_KMS("\n"); |
213 | DRM_DEBUG_KMS("\n"); |
214 | 214 | ||
215 | /* for DSI port enable has to be done before pipe |
215 | /* for DSI port enable has to be done before pipe |
216 | * and plane enable, so port enable is done in |
216 | * and plane enable, so port enable is done in |
217 | * pre_enable phase itself unlike other encoders |
217 | * pre_enable phase itself unlike other encoders |
218 | */ |
218 | */ |
219 | } |
219 | } |
220 | 220 | ||
221 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
221 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
222 | { |
222 | { |
223 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
223 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
224 | 224 | ||
225 | DRM_DEBUG_KMS("\n"); |
225 | DRM_DEBUG_KMS("\n"); |
226 | 226 | ||
227 | if (is_vid_mode(intel_dsi)) { |
227 | if (is_vid_mode(intel_dsi)) { |
228 | /* Send Shutdown command to the panel in LP mode */ |
228 | /* Send Shutdown command to the panel in LP mode */ |
229 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); |
229 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); |
230 | msleep(10); |
230 | msleep(10); |
231 | } |
231 | } |
232 | } |
232 | } |
233 | 233 | ||
234 | static void intel_dsi_disable(struct intel_encoder *encoder) |
234 | static void intel_dsi_disable(struct intel_encoder *encoder) |
235 | { |
235 | { |
236 | struct drm_device *dev = encoder->base.dev; |
236 | struct drm_device *dev = encoder->base.dev; |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
238 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
238 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
239 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
239 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
240 | int pipe = intel_crtc->pipe; |
240 | int pipe = intel_crtc->pipe; |
241 | u32 temp; |
241 | u32 temp; |
242 | 242 | ||
243 | DRM_DEBUG_KMS("\n"); |
243 | DRM_DEBUG_KMS("\n"); |
244 | 244 | ||
245 | if (is_vid_mode(intel_dsi)) { |
245 | if (is_vid_mode(intel_dsi)) { |
246 | wait_for_dsi_fifo_empty(intel_dsi); |
246 | wait_for_dsi_fifo_empty(intel_dsi); |
247 | 247 | ||
248 | /* de-assert ip_tg_enable signal */ |
248 | /* de-assert ip_tg_enable signal */ |
249 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); |
249 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); |
250 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); |
250 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); |
251 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
251 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
252 | 252 | ||
253 | msleep(2); |
253 | msleep(2); |
254 | } |
254 | } |
255 | 255 | ||
256 | /* Panel commands can be sent when clock is in LP11 */ |
256 | /* Panel commands can be sent when clock is in LP11 */ |
257 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); |
257 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); |
258 | 258 | ||
259 | temp = I915_READ(MIPI_CTRL(pipe)); |
259 | temp = I915_READ(MIPI_CTRL(pipe)); |
260 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
260 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
261 | I915_WRITE(MIPI_CTRL(pipe), temp | |
261 | I915_WRITE(MIPI_CTRL(pipe), temp | |
262 | intel_dsi->escape_clk_div << |
262 | intel_dsi->escape_clk_div << |
263 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
263 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
264 | 264 | ||
265 | I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); |
265 | I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); |
266 | 266 | ||
267 | temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); |
267 | temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); |
268 | temp &= ~VID_MODE_FORMAT_MASK; |
268 | temp &= ~VID_MODE_FORMAT_MASK; |
269 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); |
269 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); |
270 | 270 | ||
271 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); |
271 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); |
272 | 272 | ||
273 | /* if disable packets are sent before sending shutdown packet then in |
273 | /* if disable packets are sent before sending shutdown packet then in |
274 | * some next enable sequence send turn on packet error is observed */ |
274 | * some next enable sequence send turn on packet error is observed */ |
275 | if (intel_dsi->dev.dev_ops->disable) |
275 | if (intel_dsi->dev.dev_ops->disable) |
276 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); |
276 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); |
277 | 277 | ||
278 | wait_for_dsi_fifo_empty(intel_dsi); |
278 | wait_for_dsi_fifo_empty(intel_dsi); |
279 | } |
279 | } |
280 | 280 | ||
281 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
281 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
282 | { |
282 | { |
283 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
283 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
285 | int pipe = intel_crtc->pipe; |
285 | int pipe = intel_crtc->pipe; |
286 | u32 val; |
286 | u32 val; |
287 | 287 | ||
288 | DRM_DEBUG_KMS("\n"); |
288 | DRM_DEBUG_KMS("\n"); |
289 | 289 | ||
290 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
290 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
291 | usleep_range(2000, 2500); |
291 | usleep_range(2000, 2500); |
292 | 292 | ||
293 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
293 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
294 | usleep_range(2000, 2500); |
294 | usleep_range(2000, 2500); |
295 | 295 | ||
296 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
296 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
297 | usleep_range(2000, 2500); |
297 | usleep_range(2000, 2500); |
298 | 298 | ||
299 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
299 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
300 | == 0x00000), 30)) |
300 | == 0x00000), 30)) |
301 | DRM_ERROR("DSI LP not going Low\n"); |
301 | DRM_ERROR("DSI LP not going Low\n"); |
302 | 302 | ||
303 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
303 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
304 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); |
304 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); |
305 | usleep_range(1000, 1500); |
305 | usleep_range(1000, 1500); |
306 | 306 | ||
307 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
307 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
308 | usleep_range(2000, 2500); |
308 | usleep_range(2000, 2500); |
309 | 309 | ||
310 | vlv_disable_dsi_pll(encoder); |
310 | vlv_disable_dsi_pll(encoder); |
311 | } |
311 | } |
312 | 312 | ||
313 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
313 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
314 | { |
314 | { |
315 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
315 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
316 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
316 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
317 | u32 val; |
317 | u32 val; |
318 | 318 | ||
319 | DRM_DEBUG_KMS("\n"); |
319 | DRM_DEBUG_KMS("\n"); |
320 | 320 | ||
321 | intel_dsi_disable(encoder); |
321 | intel_dsi_disable(encoder); |
322 | 322 | ||
323 | intel_dsi_clear_device_ready(encoder); |
323 | intel_dsi_clear_device_ready(encoder); |
324 | 324 | ||
325 | val = I915_READ(DSPCLK_GATE_D); |
325 | val = I915_READ(DSPCLK_GATE_D); |
326 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
326 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
327 | I915_WRITE(DSPCLK_GATE_D, val); |
327 | I915_WRITE(DSPCLK_GATE_D, val); |
328 | 328 | ||
329 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
329 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
330 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); |
330 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); |
331 | 331 | ||
332 | msleep(intel_dsi->panel_off_delay); |
332 | msleep(intel_dsi->panel_off_delay); |
333 | msleep(intel_dsi->panel_pwr_cycle_delay); |
333 | msleep(intel_dsi->panel_pwr_cycle_delay); |
334 | } |
334 | } |
335 | 335 | ||
336 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
336 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
337 | enum pipe *pipe) |
337 | enum pipe *pipe) |
338 | { |
338 | { |
339 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
339 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
340 | enum intel_display_power_domain power_domain; |
340 | enum intel_display_power_domain power_domain; |
341 | u32 port, func; |
341 | u32 port, func; |
342 | enum pipe p; |
342 | enum pipe p; |
343 | 343 | ||
344 | DRM_DEBUG_KMS("\n"); |
344 | DRM_DEBUG_KMS("\n"); |
345 | 345 | ||
346 | power_domain = intel_display_port_power_domain(encoder); |
346 | power_domain = intel_display_port_power_domain(encoder); |
347 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
347 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
348 | return false; |
348 | return false; |
349 | 349 | ||
350 | /* XXX: this only works for one DSI output */ |
350 | /* XXX: this only works for one DSI output */ |
351 | for (p = PIPE_A; p <= PIPE_B; p++) { |
351 | for (p = PIPE_A; p <= PIPE_B; p++) { |
352 | port = I915_READ(MIPI_PORT_CTRL(p)); |
352 | port = I915_READ(MIPI_PORT_CTRL(p)); |
353 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); |
353 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); |
354 | 354 | ||
355 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
355 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
356 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { |
356 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { |
357 | *pipe = p; |
357 | *pipe = p; |
358 | return true; |
358 | return true; |
359 | } |
359 | } |
360 | } |
360 | } |
361 | } |
361 | } |
362 | 362 | ||
363 | return false; |
363 | return false; |
364 | } |
364 | } |
365 | 365 | ||
366 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
366 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
367 | struct intel_crtc_config *pipe_config) |
367 | struct intel_crtc_config *pipe_config) |
368 | { |
368 | { |
369 | u32 pclk; |
369 | u32 pclk; |
370 | DRM_DEBUG_KMS("\n"); |
370 | DRM_DEBUG_KMS("\n"); |
371 | 371 | ||
372 | /* |
372 | /* |
373 | * DPLL_MD is not used in case of DSI, reading will get some default value |
373 | * DPLL_MD is not used in case of DSI, reading will get some default value |
374 | * set dpll_md = 0 |
374 | * set dpll_md = 0 |
375 | */ |
375 | */ |
376 | pipe_config->dpll_hw_state.dpll_md = 0; |
376 | pipe_config->dpll_hw_state.dpll_md = 0; |
377 | 377 | ||
378 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
378 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
379 | if (!pclk) |
379 | if (!pclk) |
380 | return; |
380 | return; |
381 | 381 | ||
382 | pipe_config->adjusted_mode.crtc_clock = pclk; |
382 | pipe_config->adjusted_mode.crtc_clock = pclk; |
383 | pipe_config->port_clock = pclk; |
383 | pipe_config->port_clock = pclk; |
384 | } |
384 | } |
385 | 385 | ||
386 | static enum drm_mode_status |
386 | static enum drm_mode_status |
387 | intel_dsi_mode_valid(struct drm_connector *connector, |
387 | intel_dsi_mode_valid(struct drm_connector *connector, |
388 | struct drm_display_mode *mode) |
388 | struct drm_display_mode *mode) |
389 | { |
389 | { |
390 | struct intel_connector *intel_connector = to_intel_connector(connector); |
390 | struct intel_connector *intel_connector = to_intel_connector(connector); |
391 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
391 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
392 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
392 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
393 | 393 | ||
394 | DRM_DEBUG_KMS("\n"); |
394 | DRM_DEBUG_KMS("\n"); |
395 | 395 | ||
396 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
396 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
397 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
397 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
398 | return MODE_NO_DBLESCAN; |
398 | return MODE_NO_DBLESCAN; |
399 | } |
399 | } |
400 | 400 | ||
401 | if (fixed_mode) { |
401 | if (fixed_mode) { |
402 | if (mode->hdisplay > fixed_mode->hdisplay) |
402 | if (mode->hdisplay > fixed_mode->hdisplay) |
403 | return MODE_PANEL; |
403 | return MODE_PANEL; |
404 | if (mode->vdisplay > fixed_mode->vdisplay) |
404 | if (mode->vdisplay > fixed_mode->vdisplay) |
405 | return MODE_PANEL; |
405 | return MODE_PANEL; |
406 | } |
406 | } |
407 | 407 | ||
408 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); |
408 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); |
409 | } |
409 | } |
410 | 410 | ||
411 | /* return txclkesc cycles in terms of divider and duration in us */ |
411 | /* return txclkesc cycles in terms of divider and duration in us */ |
412 | static u16 txclkesc(u32 divider, unsigned int us) |
412 | static u16 txclkesc(u32 divider, unsigned int us) |
413 | { |
413 | { |
414 | switch (divider) { |
414 | switch (divider) { |
415 | case ESCAPE_CLOCK_DIVIDER_1: |
415 | case ESCAPE_CLOCK_DIVIDER_1: |
416 | default: |
416 | default: |
417 | return 20 * us; |
417 | return 20 * us; |
418 | case ESCAPE_CLOCK_DIVIDER_2: |
418 | case ESCAPE_CLOCK_DIVIDER_2: |
419 | return 10 * us; |
419 | return 10 * us; |
420 | case ESCAPE_CLOCK_DIVIDER_4: |
420 | case ESCAPE_CLOCK_DIVIDER_4: |
421 | return 5 * us; |
421 | return 5 * us; |
422 | } |
422 | } |
423 | } |
423 | } |
424 | 424 | ||
425 | /* return pixels in terms of txbyteclkhs */ |
425 | /* return pixels in terms of txbyteclkhs */ |
426 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) |
426 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
- | 427 | u16 burst_mode_ratio) |
|
427 | { |
428 | { |
428 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); |
429 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
- | 430 | 8 * 100), lane_count); |
|
429 | } |
431 | } |
430 | 432 | ||
431 | static void set_dsi_timings(struct drm_encoder *encoder, |
433 | static void set_dsi_timings(struct drm_encoder *encoder, |
432 | const struct drm_display_mode *mode) |
434 | const struct drm_display_mode *mode) |
433 | { |
435 | { |
434 | struct drm_device *dev = encoder->dev; |
436 | struct drm_device *dev = encoder->dev; |
435 | struct drm_i915_private *dev_priv = dev->dev_private; |
437 | struct drm_i915_private *dev_priv = dev->dev_private; |
436 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
438 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
437 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
439 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
438 | int pipe = intel_crtc->pipe; |
440 | int pipe = intel_crtc->pipe; |
439 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
441 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
440 | unsigned int lane_count = intel_dsi->lane_count; |
442 | unsigned int lane_count = intel_dsi->lane_count; |
441 | 443 | ||
442 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
444 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
443 | 445 | ||
444 | hactive = mode->hdisplay; |
446 | hactive = mode->hdisplay; |
445 | hfp = mode->hsync_start - mode->hdisplay; |
447 | hfp = mode->hsync_start - mode->hdisplay; |
446 | hsync = mode->hsync_end - mode->hsync_start; |
448 | hsync = mode->hsync_end - mode->hsync_start; |
447 | hbp = mode->htotal - mode->hsync_end; |
449 | hbp = mode->htotal - mode->hsync_end; |
448 | 450 | ||
449 | vfp = mode->vsync_start - mode->vdisplay; |
451 | vfp = mode->vsync_start - mode->vdisplay; |
450 | vsync = mode->vsync_end - mode->vsync_start; |
452 | vsync = mode->vsync_end - mode->vsync_start; |
451 | vbp = mode->vtotal - mode->vsync_end; |
453 | vbp = mode->vtotal - mode->vsync_end; |
452 | 454 | ||
453 | /* horizontal values are in terms of high speed byte clock */ |
455 | /* horizontal values are in terms of high speed byte clock */ |
454 | hactive = txbyteclkhs(hactive, bpp, lane_count); |
456 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
- | 457 | intel_dsi->burst_mode_ratio); |
|
455 | hfp = txbyteclkhs(hfp, bpp, lane_count); |
458 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
456 | hsync = txbyteclkhs(hsync, bpp, lane_count); |
459 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
- | 460 | intel_dsi->burst_mode_ratio); |
|
457 | hbp = txbyteclkhs(hbp, bpp, lane_count); |
461 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
458 | 462 | ||
459 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
463 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
460 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
464 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
461 | 465 | ||
462 | /* meaningful for video mode non-burst sync pulse mode only, can be zero |
466 | /* meaningful for video mode non-burst sync pulse mode only, can be zero |
463 | * for non-burst sync events and burst modes */ |
467 | * for non-burst sync events and burst modes */ |
464 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); |
468 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); |
465 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); |
469 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); |
466 | 470 | ||
467 | /* vertical values are in terms of lines */ |
471 | /* vertical values are in terms of lines */ |
468 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); |
472 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); |
469 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); |
473 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); |
470 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); |
474 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); |
471 | } |
475 | } |
472 | 476 | ||
473 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
477 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
474 | { |
478 | { |
475 | struct drm_encoder *encoder = &intel_encoder->base; |
479 | struct drm_encoder *encoder = &intel_encoder->base; |
476 | struct drm_device *dev = encoder->dev; |
480 | struct drm_device *dev = encoder->dev; |
477 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
478 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
479 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
483 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
480 | struct drm_display_mode *adjusted_mode = |
484 | struct drm_display_mode *adjusted_mode = |
481 | &intel_crtc->config.adjusted_mode; |
485 | &intel_crtc->config.adjusted_mode; |
482 | int pipe = intel_crtc->pipe; |
486 | int pipe = intel_crtc->pipe; |
483 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
487 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
484 | u32 val, tmp; |
488 | u32 val, tmp; |
485 | 489 | ||
486 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
490 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
487 | 491 | ||
488 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
492 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
489 | * off when doing this! txclkesc? */ |
493 | * off when doing this! txclkesc? */ |
490 | tmp = I915_READ(MIPI_CTRL(0)); |
494 | tmp = I915_READ(MIPI_CTRL(0)); |
491 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
495 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
492 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); |
496 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); |
493 | 497 | ||
494 | /* read request priority is per pipe */ |
498 | /* read request priority is per pipe */ |
495 | tmp = I915_READ(MIPI_CTRL(pipe)); |
499 | tmp = I915_READ(MIPI_CTRL(pipe)); |
496 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
500 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
497 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); |
501 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); |
498 | 502 | ||
499 | /* XXX: why here, why like this? handling in irq handler?! */ |
503 | /* XXX: why here, why like this? handling in irq handler?! */ |
500 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); |
504 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); |
501 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); |
505 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); |
502 | 506 | ||
503 | I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); |
507 | I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); |
504 | 508 | ||
505 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), |
509 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), |
506 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
510 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
507 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
511 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
508 | 512 | ||
509 | set_dsi_timings(encoder, adjusted_mode); |
513 | set_dsi_timings(encoder, adjusted_mode); |
510 | 514 | ||
511 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
515 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
512 | if (is_cmd_mode(intel_dsi)) { |
516 | if (is_cmd_mode(intel_dsi)) { |
513 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
517 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
514 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
518 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
515 | } else { |
519 | } else { |
516 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
520 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
517 | 521 | ||
518 | /* XXX: cross-check bpp vs. pixel format? */ |
522 | /* XXX: cross-check bpp vs. pixel format? */ |
519 | val |= intel_dsi->pixel_format; |
523 | val |= intel_dsi->pixel_format; |
520 | } |
524 | } |
521 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); |
525 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); |
522 | 526 | ||
523 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and |
527 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and |
524 | * stop state. */ |
528 | * stop state. */ |
525 | 529 | ||
526 | /* |
530 | /* |
527 | * In burst mode, value greater than one DPI line Time in byte clock |
531 | * In burst mode, value greater than one DPI line Time in byte clock |
528 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is |
532 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is |
529 | * recommended. |
533 | * recommended. |
530 | * |
534 | * |
531 | * In non-burst mode, Value greater than one DPI frame time in byte |
535 | * In non-burst mode, Value greater than one DPI frame time in byte |
532 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
536 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
533 | * is recommended. |
537 | * is recommended. |
534 | * |
538 | * |
535 | * In DBI only mode, value greater than one DBI frame time in byte |
539 | * In DBI only mode, value greater than one DBI frame time in byte |
536 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
540 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
537 | * is recommended. |
541 | * is recommended. |
538 | */ |
542 | */ |
539 | 543 | ||
540 | if (is_vid_mode(intel_dsi) && |
544 | if (is_vid_mode(intel_dsi) && |
541 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
545 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
542 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
546 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
543 | txbyteclkhs(adjusted_mode->htotal, bpp, |
547 | txbyteclkhs(adjusted_mode->htotal, bpp, |
544 | intel_dsi->lane_count) + 1); |
548 | intel_dsi->lane_count, |
- | 549 | intel_dsi->burst_mode_ratio) + 1); |
|
545 | } else { |
550 | } else { |
546 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
551 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
547 | txbyteclkhs(adjusted_mode->vtotal * |
552 | txbyteclkhs(adjusted_mode->vtotal * |
548 | adjusted_mode->htotal, |
553 | adjusted_mode->htotal, |
549 | bpp, intel_dsi->lane_count) + 1); |
554 | bpp, intel_dsi->lane_count, |
- | 555 | intel_dsi->burst_mode_ratio) + 1); |
|
550 | } |
556 | } |
551 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
557 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
552 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |
558 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |
553 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); |
559 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); |
554 | 560 | ||
555 | /* dphy stuff */ |
561 | /* dphy stuff */ |
556 | 562 | ||
557 | /* in terms of low power clock */ |
563 | /* in terms of low power clock */ |
558 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); |
564 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); |
559 | 565 | ||
560 | val = 0; |
566 | val = 0; |
561 | if (intel_dsi->eotp_pkt == 0) |
567 | if (intel_dsi->eotp_pkt == 0) |
562 | val |= EOT_DISABLE; |
568 | val |= EOT_DISABLE; |
563 | 569 | ||
564 | if (intel_dsi->clock_stop) |
570 | if (intel_dsi->clock_stop) |
565 | val |= CLOCKSTOP; |
571 | val |= CLOCKSTOP; |
566 | 572 | ||
567 | /* recovery disables */ |
573 | /* recovery disables */ |
568 | I915_WRITE(MIPI_EOT_DISABLE(pipe), val); |
574 | I915_WRITE(MIPI_EOT_DISABLE(pipe), val); |
569 | 575 | ||
570 | /* in terms of low power clock */ |
576 | /* in terms of low power clock */ |
571 | I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); |
577 | I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); |
572 | 578 | ||
573 | /* in terms of txbyteclkhs. actual high to low switch + |
579 | /* in terms of txbyteclkhs. actual high to low switch + |
574 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
580 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
575 | * |
581 | * |
576 | * XXX: write MIPI_STOP_STATE_STALL? |
582 | * XXX: write MIPI_STOP_STATE_STALL? |
577 | */ |
583 | */ |
578 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
584 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
579 | intel_dsi->hs_to_lp_count); |
585 | intel_dsi->hs_to_lp_count); |
580 | 586 | ||
581 | /* XXX: low power clock equivalence in terms of byte clock. the number |
587 | /* XXX: low power clock equivalence in terms of byte clock. the number |
582 | * of byte clocks occupied in one low power clock. based on txbyteclkhs |
588 | * of byte clocks occupied in one low power clock. based on txbyteclkhs |
583 | * and txclkesc. txclkesc time / txbyteclk time * (105 + |
589 | * and txclkesc. txclkesc time / txbyteclk time * (105 + |
584 | * MIPI_STOP_STATE_STALL) / 105.??? |
590 | * MIPI_STOP_STATE_STALL) / 105.??? |
585 | */ |
591 | */ |
586 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
592 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
587 | 593 | ||
588 | /* the bw essential for transmitting 16 long packets containing 252 |
594 | /* the bw essential for transmitting 16 long packets containing 252 |
589 | * bytes meant for dcs write memory command is programmed in this |
595 | * bytes meant for dcs write memory command is programmed in this |
590 | * register in terms of byte clocks. based on dsi transfer rate and the |
596 | * register in terms of byte clocks. based on dsi transfer rate and the |
591 | * number of lanes configured the time taken to transmit 16 long packets |
597 | * number of lanes configured the time taken to transmit 16 long packets |
592 | * in a dsi stream varies. */ |
598 | * in a dsi stream varies. */ |
593 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
599 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
594 | 600 | ||
595 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), |
601 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), |
596 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
602 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
597 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
603 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
598 | 604 | ||
599 | if (is_vid_mode(intel_dsi)) |
605 | if (is_vid_mode(intel_dsi)) |
600 | /* Some panels might have resolution which is not a multiple of |
606 | /* Some panels might have resolution which is not a multiple of |
601 | * 64 like 1366 x 768. Enable RANDOM resolution support for such |
607 | * 64 like 1366 x 768. Enable RANDOM resolution support for such |
602 | * panels by default */ |
608 | * panels by default */ |
603 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
609 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
604 | intel_dsi->video_frmt_cfg_bits | |
610 | intel_dsi->video_frmt_cfg_bits | |
605 | intel_dsi->video_mode_format | |
611 | intel_dsi->video_mode_format | |
606 | IP_TG_CONFIG | |
612 | IP_TG_CONFIG | |
607 | RANDOM_DPI_DISPLAY_RESOLUTION); |
613 | RANDOM_DPI_DISPLAY_RESOLUTION); |
608 | } |
614 | } |
609 | 615 | ||
610 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
616 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
611 | { |
617 | { |
612 | DRM_DEBUG_KMS("\n"); |
618 | DRM_DEBUG_KMS("\n"); |
613 | 619 | ||
614 | intel_dsi_prepare(encoder); |
620 | intel_dsi_prepare(encoder); |
615 | 621 | ||
616 | vlv_enable_dsi_pll(encoder); |
622 | vlv_enable_dsi_pll(encoder); |
617 | } |
623 | } |
618 | 624 | ||
619 | static enum drm_connector_status |
625 | static enum drm_connector_status |
620 | intel_dsi_detect(struct drm_connector *connector, bool force) |
626 | intel_dsi_detect(struct drm_connector *connector, bool force) |
621 | { |
627 | { |
622 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
628 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
623 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
629 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
624 | enum intel_display_power_domain power_domain; |
630 | enum intel_display_power_domain power_domain; |
625 | enum drm_connector_status connector_status; |
631 | enum drm_connector_status connector_status; |
626 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; |
632 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; |
627 | 633 | ||
628 | DRM_DEBUG_KMS("\n"); |
634 | DRM_DEBUG_KMS("\n"); |
629 | power_domain = intel_display_port_power_domain(intel_encoder); |
635 | power_domain = intel_display_port_power_domain(intel_encoder); |
630 | 636 | ||
631 | intel_display_power_get(dev_priv, power_domain); |
637 | intel_display_power_get(dev_priv, power_domain); |
632 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); |
638 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); |
633 | intel_display_power_put(dev_priv, power_domain); |
639 | intel_display_power_put(dev_priv, power_domain); |
634 | 640 | ||
635 | return connector_status; |
641 | return connector_status; |
636 | } |
642 | } |
637 | 643 | ||
638 | static int intel_dsi_get_modes(struct drm_connector *connector) |
644 | static int intel_dsi_get_modes(struct drm_connector *connector) |
639 | { |
645 | { |
640 | struct intel_connector *intel_connector = to_intel_connector(connector); |
646 | struct intel_connector *intel_connector = to_intel_connector(connector); |
641 | struct drm_display_mode *mode; |
647 | struct drm_display_mode *mode; |
642 | 648 | ||
643 | DRM_DEBUG_KMS("\n"); |
649 | DRM_DEBUG_KMS("\n"); |
644 | 650 | ||
645 | if (!intel_connector->panel.fixed_mode) { |
651 | if (!intel_connector->panel.fixed_mode) { |
646 | DRM_DEBUG_KMS("no fixed mode\n"); |
652 | DRM_DEBUG_KMS("no fixed mode\n"); |
647 | return 0; |
653 | return 0; |
648 | } |
654 | } |
649 | 655 | ||
650 | mode = drm_mode_duplicate(connector->dev, |
656 | mode = drm_mode_duplicate(connector->dev, |
651 | intel_connector->panel.fixed_mode); |
657 | intel_connector->panel.fixed_mode); |
652 | if (!mode) { |
658 | if (!mode) { |
653 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
659 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
654 | return 0; |
660 | return 0; |
655 | } |
661 | } |
656 | 662 | ||
657 | drm_mode_probed_add(connector, mode); |
663 | drm_mode_probed_add(connector, mode); |
658 | return 1; |
664 | return 1; |
659 | } |
665 | } |
660 | 666 | ||
661 | static void intel_dsi_destroy(struct drm_connector *connector) |
667 | static void intel_dsi_destroy(struct drm_connector *connector) |
662 | { |
668 | { |
663 | struct intel_connector *intel_connector = to_intel_connector(connector); |
669 | struct intel_connector *intel_connector = to_intel_connector(connector); |
664 | 670 | ||
665 | DRM_DEBUG_KMS("\n"); |
671 | DRM_DEBUG_KMS("\n"); |
666 | intel_panel_fini(&intel_connector->panel); |
672 | intel_panel_fini(&intel_connector->panel); |
667 | drm_connector_cleanup(connector); |
673 | drm_connector_cleanup(connector); |
668 | kfree(connector); |
674 | kfree(connector); |
669 | } |
675 | } |
670 | 676 | ||
671 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
677 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
672 | .destroy = intel_encoder_destroy, |
678 | .destroy = intel_encoder_destroy, |
673 | }; |
679 | }; |
674 | 680 | ||
675 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
681 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
676 | .get_modes = intel_dsi_get_modes, |
682 | .get_modes = intel_dsi_get_modes, |
677 | .mode_valid = intel_dsi_mode_valid, |
683 | .mode_valid = intel_dsi_mode_valid, |
678 | .best_encoder = intel_best_encoder, |
684 | .best_encoder = intel_best_encoder, |
679 | }; |
685 | }; |
680 | 686 | ||
681 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
687 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
682 | .dpms = intel_connector_dpms, |
688 | .dpms = intel_connector_dpms, |
683 | .detect = intel_dsi_detect, |
689 | .detect = intel_dsi_detect, |
684 | .destroy = intel_dsi_destroy, |
690 | .destroy = intel_dsi_destroy, |
685 | .fill_modes = drm_helper_probe_single_connector_modes, |
691 | .fill_modes = drm_helper_probe_single_connector_modes, |
686 | }; |
692 | }; |
687 | 693 | ||
688 | void intel_dsi_init(struct drm_device *dev) |
694 | void intel_dsi_init(struct drm_device *dev) |
689 | { |
695 | { |
690 | struct intel_dsi *intel_dsi; |
696 | struct intel_dsi *intel_dsi; |
691 | struct intel_encoder *intel_encoder; |
697 | struct intel_encoder *intel_encoder; |
692 | struct drm_encoder *encoder; |
698 | struct drm_encoder *encoder; |
693 | struct intel_connector *intel_connector; |
699 | struct intel_connector *intel_connector; |
694 | struct drm_connector *connector; |
700 | struct drm_connector *connector; |
695 | struct drm_display_mode *fixed_mode = NULL; |
701 | struct drm_display_mode *fixed_mode = NULL; |
696 | struct drm_i915_private *dev_priv = dev->dev_private; |
702 | struct drm_i915_private *dev_priv = dev->dev_private; |
697 | const struct intel_dsi_device *dsi; |
703 | const struct intel_dsi_device *dsi; |
698 | unsigned int i; |
704 | unsigned int i; |
699 | 705 | ||
700 | DRM_DEBUG_KMS("\n"); |
706 | DRM_DEBUG_KMS("\n"); |
701 | 707 | ||
702 | /* There is no detection method for MIPI so rely on VBT */ |
708 | /* There is no detection method for MIPI so rely on VBT */ |
703 | if (!dev_priv->vbt.has_mipi) |
709 | if (!dev_priv->vbt.has_mipi) |
704 | return; |
710 | return; |
705 | 711 | ||
706 | if (IS_VALLEYVIEW(dev)) { |
712 | if (IS_VALLEYVIEW(dev)) { |
707 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
713 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
708 | } else { |
714 | } else { |
709 | DRM_ERROR("Unsupported Mipi device to reg base"); |
715 | DRM_ERROR("Unsupported Mipi device to reg base"); |
710 | return; |
716 | return; |
711 | } |
717 | } |
712 | 718 | ||
713 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
719 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
714 | if (!intel_dsi) |
720 | if (!intel_dsi) |
715 | return; |
721 | return; |
716 | 722 | ||
717 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
723 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
718 | if (!intel_connector) { |
724 | if (!intel_connector) { |
719 | kfree(intel_dsi); |
725 | kfree(intel_dsi); |
720 | return; |
726 | return; |
721 | } |
727 | } |
722 | 728 | ||
723 | intel_encoder = &intel_dsi->base; |
729 | intel_encoder = &intel_dsi->base; |
724 | encoder = &intel_encoder->base; |
730 | encoder = &intel_encoder->base; |
725 | intel_dsi->attached_connector = intel_connector; |
731 | intel_dsi->attached_connector = intel_connector; |
726 | 732 | ||
727 | connector = &intel_connector->base; |
733 | connector = &intel_connector->base; |
728 | 734 | ||
729 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
735 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
730 | 736 | ||
731 | /* XXX: very likely not all of these are needed */ |
737 | /* XXX: very likely not all of these are needed */ |
732 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
738 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
733 | intel_encoder->compute_config = intel_dsi_compute_config; |
739 | intel_encoder->compute_config = intel_dsi_compute_config; |
734 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
740 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
735 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
741 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
736 | intel_encoder->enable = intel_dsi_enable_nop; |
742 | intel_encoder->enable = intel_dsi_enable_nop; |
737 | intel_encoder->disable = intel_dsi_pre_disable; |
743 | intel_encoder->disable = intel_dsi_pre_disable; |
738 | intel_encoder->post_disable = intel_dsi_post_disable; |
744 | intel_encoder->post_disable = intel_dsi_post_disable; |
739 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
745 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
740 | intel_encoder->get_config = intel_dsi_get_config; |
746 | intel_encoder->get_config = intel_dsi_get_config; |
741 | 747 | ||
742 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
748 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
743 | intel_connector->unregister = intel_connector_unregister; |
749 | intel_connector->unregister = intel_connector_unregister; |
744 | 750 | ||
745 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
751 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
746 | dsi = &intel_dsi_devices[i]; |
752 | dsi = &intel_dsi_devices[i]; |
747 | intel_dsi->dev = *dsi; |
753 | intel_dsi->dev = *dsi; |
748 | 754 | ||
749 | if (dsi->dev_ops->init(&intel_dsi->dev)) |
755 | if (dsi->dev_ops->init(&intel_dsi->dev)) |
750 | break; |
756 | break; |
751 | } |
757 | } |
752 | 758 | ||
753 | if (i == ARRAY_SIZE(intel_dsi_devices)) { |
759 | if (i == ARRAY_SIZE(intel_dsi_devices)) { |
754 | DRM_DEBUG_KMS("no device found\n"); |
760 | DRM_DEBUG_KMS("no device found\n"); |
755 | goto err; |
761 | goto err; |
756 | } |
762 | } |
757 | 763 | ||
758 | intel_encoder->type = INTEL_OUTPUT_DSI; |
764 | intel_encoder->type = INTEL_OUTPUT_DSI; |
759 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ |
765 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ |
760 | 766 | ||
761 | intel_encoder->cloneable = 0; |
767 | intel_encoder->cloneable = 0; |
762 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
768 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
763 | DRM_MODE_CONNECTOR_DSI); |
769 | DRM_MODE_CONNECTOR_DSI); |
764 | 770 | ||
765 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
771 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
766 | 772 | ||
767 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
773 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
768 | connector->interlace_allowed = false; |
774 | connector->interlace_allowed = false; |
769 | connector->doublescan_allowed = false; |
775 | connector->doublescan_allowed = false; |
770 | 776 | ||
771 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
777 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
772 | 778 | ||
773 | drm_connector_register(connector); |
779 | drm_connector_register(connector); |
774 | 780 | ||
775 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); |
781 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); |
776 | if (!fixed_mode) { |
782 | if (!fixed_mode) { |
777 | DRM_DEBUG_KMS("no fixed mode\n"); |
783 | DRM_DEBUG_KMS("no fixed mode\n"); |
778 | goto err; |
784 | goto err; |
779 | } |
785 | } |
780 | 786 | ||
781 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
787 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
782 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
788 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
783 | 789 | ||
784 | return; |
790 | return; |
785 | 791 | ||
786 | err: |
792 | err: |
787 | drm_encoder_cleanup(&intel_encoder->base); |
793 | drm_encoder_cleanup(&intel_encoder->base); |
788 | kfree(intel_dsi); |
794 | kfree(intel_dsi); |
789 | kfree(intel_connector); |
795 | kfree(intel_connector); |
790 | }><>>><>><>><>><>><>><>><>=> |
796 | }><>>><>><>><>><>><>><>><>=> |
791 | >< |
797 | >< |
792 | > |
798 | > |