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Rev 5060 Rev 5354
Line 342... Line 342...
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	enum pipe p;
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	enum pipe p;
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	DRM_DEBUG_KMS("\n");
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	DRM_DEBUG_KMS("\n");
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	power_domain = intel_display_port_power_domain(encoder);
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	power_domain = intel_display_port_power_domain(encoder);
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	if (!intel_display_power_enabled(dev_priv, power_domain))
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	if (!intel_display_power_is_enabled(dev_priv, power_domain))
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		return false;
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		return false;
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		return 5 * us;
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		return 5 * us;
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	}
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	}
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}
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}
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/* return pixels in terms of txbyteclkhs */
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/* return pixels in terms of txbyteclkhs */
- 
 
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static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
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static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
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		       u16 burst_mode_ratio)
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{
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{
- 
 
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	return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
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	return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
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					 8 * 100), lane_count);
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}
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}
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static void set_dsi_timings(struct drm_encoder *encoder,
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static void set_dsi_timings(struct drm_encoder *encoder,
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	vfp = mode->vsync_start - mode->vdisplay;
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	vfp = mode->vsync_start - mode->vdisplay;
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	vsync = mode->vsync_end - mode->vsync_start;
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	vsync = mode->vsync_end - mode->vsync_start;
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	vbp = mode->vtotal - mode->vsync_end;
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	vbp = mode->vtotal - mode->vsync_end;
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	/* horizontal values are in terms of high speed byte clock */
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	/* horizontal values are in terms of high speed byte clock */
- 
 
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	hactive = txbyteclkhs(hactive, bpp, lane_count,
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	hactive = txbyteclkhs(hactive, bpp, lane_count);
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			      intel_dsi->burst_mode_ratio);
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	hfp = txbyteclkhs(hfp, bpp, lane_count);
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	hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
- 
 
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	hsync = txbyteclkhs(hsync, bpp, lane_count,
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	hsync = txbyteclkhs(hsync, bpp, lane_count);
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			    intel_dsi->burst_mode_ratio);
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	hbp = txbyteclkhs(hbp, bpp, lane_count);
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	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
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	I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
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	I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
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	if (is_vid_mode(intel_dsi) &&
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	if (is_vid_mode(intel_dsi) &&
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	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
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	    intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
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		I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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		I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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			   txbyteclkhs(adjusted_mode->htotal, bpp,
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			   txbyteclkhs(adjusted_mode->htotal, bpp,
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				       intel_dsi->lane_count,
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				       intel_dsi->lane_count) + 1);
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				       intel_dsi->burst_mode_ratio) + 1);
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	} else {
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	} else {
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		I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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		I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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			   txbyteclkhs(adjusted_mode->vtotal *
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			   txbyteclkhs(adjusted_mode->vtotal *
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				       adjusted_mode->htotal,
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				       adjusted_mode->htotal,
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				       bpp, intel_dsi->lane_count,
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				       bpp, intel_dsi->lane_count) + 1);
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				       intel_dsi->burst_mode_ratio) + 1);
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	}
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	}
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	I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
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	I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
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	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
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	I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);