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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Keith Packard |
24 | * Keith Packard |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
- | 31 | #include |
|
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include "intel_drv.h" |
37 | #include "intel_drv.h" |
37 | #include |
38 | #include |
38 | #include "i915_drv.h" |
39 | #include "i915_drv.h" |
39 | 40 | ||
40 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
41 | 42 | ||
42 | /* Compliance test status bits */ |
43 | /* Compliance test status bits */ |
43 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
44 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
44 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
45 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
45 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
47 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
47 | 48 | ||
48 | struct dp_link_dpll { |
49 | struct dp_link_dpll { |
49 | int clock; |
50 | int clock; |
50 | struct dpll dpll; |
51 | struct dpll dpll; |
51 | }; |
52 | }; |
52 | 53 | ||
53 | static const struct dp_link_dpll gen4_dpll[] = { |
54 | static const struct dp_link_dpll gen4_dpll[] = { |
54 | { 162000, |
55 | { 162000, |
55 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
56 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
56 | { 270000, |
57 | { 270000, |
57 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
58 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
58 | }; |
59 | }; |
59 | 60 | ||
60 | static const struct dp_link_dpll pch_dpll[] = { |
61 | static const struct dp_link_dpll pch_dpll[] = { |
61 | { 162000, |
62 | { 162000, |
62 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
63 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
63 | { 270000, |
64 | { 270000, |
64 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
65 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
65 | }; |
66 | }; |
66 | 67 | ||
67 | static const struct dp_link_dpll vlv_dpll[] = { |
68 | static const struct dp_link_dpll vlv_dpll[] = { |
68 | { 162000, |
69 | { 162000, |
69 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
70 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
70 | { 270000, |
71 | { 270000, |
71 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
72 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
72 | }; |
73 | }; |
73 | 74 | ||
74 | /* |
75 | /* |
75 | * CHV supports eDP 1.4 that have more link rates. |
76 | * CHV supports eDP 1.4 that have more link rates. |
76 | * Below only provides the fixed rate but exclude variable rate. |
77 | * Below only provides the fixed rate but exclude variable rate. |
77 | */ |
78 | */ |
78 | static const struct dp_link_dpll chv_dpll[] = { |
79 | static const struct dp_link_dpll chv_dpll[] = { |
79 | /* |
80 | /* |
80 | * CHV requires to program fractional division for m2. |
81 | * CHV requires to program fractional division for m2. |
81 | * m2 is stored in fixed point format using formula below |
82 | * m2 is stored in fixed point format using formula below |
82 | * (m2_int << 22) | m2_fraction |
83 | * (m2_int << 22) | m2_fraction |
83 | */ |
84 | */ |
84 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
85 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
85 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
86 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
86 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
87 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
87 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
88 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
88 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
89 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
89 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
90 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
90 | }; |
91 | }; |
91 | 92 | ||
92 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
93 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
93 | 324000, 432000, 540000 }; |
94 | 324000, 432000, 540000 }; |
94 | static const int skl_rates[] = { 162000, 216000, 270000, |
95 | static const int skl_rates[] = { 162000, 216000, 270000, |
95 | 324000, 432000, 540000 }; |
96 | 324000, 432000, 540000 }; |
96 | static const int default_rates[] = { 162000, 270000, 540000 }; |
97 | static const int default_rates[] = { 162000, 270000, 540000 }; |
97 | 98 | ||
98 | /** |
99 | /** |
99 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
100 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
100 | * @intel_dp: DP struct |
101 | * @intel_dp: DP struct |
101 | * |
102 | * |
102 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
103 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
103 | * will return true, and false otherwise. |
104 | * will return true, and false otherwise. |
104 | */ |
105 | */ |
105 | static bool is_edp(struct intel_dp *intel_dp) |
106 | static bool is_edp(struct intel_dp *intel_dp) |
106 | { |
107 | { |
107 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
108 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
108 | 109 | ||
109 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
110 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
110 | } |
111 | } |
111 | 112 | ||
112 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
113 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
113 | { |
114 | { |
114 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
115 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
115 | 116 | ||
116 | return intel_dig_port->base.base.dev; |
117 | return intel_dig_port->base.base.dev; |
117 | } |
118 | } |
118 | 119 | ||
119 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
120 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
120 | { |
121 | { |
121 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
122 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
122 | } |
123 | } |
123 | 124 | ||
124 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
125 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
125 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
126 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
126 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
127 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
127 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
128 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
128 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
129 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
129 | enum pipe pipe); |
130 | enum pipe pipe); |
130 | 131 | ||
131 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
132 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
132 | { |
133 | { |
133 | return ~((1 << lane_count) - 1) & 0xf; |
134 | return ~((1 << lane_count) - 1) & 0xf; |
134 | } |
135 | } |
135 | 136 | ||
136 | static int |
137 | static int |
137 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
138 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
138 | { |
139 | { |
139 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
140 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
140 | 141 | ||
141 | switch (max_link_bw) { |
142 | switch (max_link_bw) { |
142 | case DP_LINK_BW_1_62: |
143 | case DP_LINK_BW_1_62: |
143 | case DP_LINK_BW_2_7: |
144 | case DP_LINK_BW_2_7: |
144 | case DP_LINK_BW_5_4: |
145 | case DP_LINK_BW_5_4: |
145 | break; |
146 | break; |
146 | default: |
147 | default: |
147 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | max_link_bw); |
149 | max_link_bw); |
149 | max_link_bw = DP_LINK_BW_1_62; |
150 | max_link_bw = DP_LINK_BW_1_62; |
150 | break; |
151 | break; |
151 | } |
152 | } |
152 | return max_link_bw; |
153 | return max_link_bw; |
153 | } |
154 | } |
154 | 155 | ||
155 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | { |
157 | { |
157 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
158 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
158 | struct drm_device *dev = intel_dig_port->base.base.dev; |
159 | struct drm_device *dev = intel_dig_port->base.base.dev; |
159 | u8 source_max, sink_max; |
160 | u8 source_max, sink_max; |
160 | 161 | ||
161 | source_max = 4; |
162 | source_max = 4; |
162 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
163 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
163 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
164 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
164 | source_max = 2; |
165 | source_max = 2; |
165 | 166 | ||
166 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
167 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
167 | 168 | ||
168 | return min(source_max, sink_max); |
169 | return min(source_max, sink_max); |
169 | } |
170 | } |
170 | 171 | ||
171 | /* |
172 | /* |
172 | * The units on the numbers in the next two are... bizarre. Examples will |
173 | * The units on the numbers in the next two are... bizarre. Examples will |
173 | * make it clearer; this one parallels an example in the eDP spec. |
174 | * make it clearer; this one parallels an example in the eDP spec. |
174 | * |
175 | * |
175 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
176 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
176 | * |
177 | * |
177 | * 270000 * 1 * 8 / 10 == 216000 |
178 | * 270000 * 1 * 8 / 10 == 216000 |
178 | * |
179 | * |
179 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
180 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
180 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
181 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
181 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
182 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
182 | * 119000. At 18bpp that's 2142000 kilobits per second. |
183 | * 119000. At 18bpp that's 2142000 kilobits per second. |
183 | * |
184 | * |
184 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
185 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
185 | * get the result in decakilobits instead of kilobits. |
186 | * get the result in decakilobits instead of kilobits. |
186 | */ |
187 | */ |
187 | 188 | ||
188 | static int |
189 | static int |
189 | intel_dp_link_required(int pixel_clock, int bpp) |
190 | intel_dp_link_required(int pixel_clock, int bpp) |
190 | { |
191 | { |
191 | return (pixel_clock * bpp + 9) / 10; |
192 | return (pixel_clock * bpp + 9) / 10; |
192 | } |
193 | } |
193 | 194 | ||
194 | static int |
195 | static int |
195 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
196 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
196 | { |
197 | { |
197 | return (max_link_clock * max_lanes * 8) / 10; |
198 | return (max_link_clock * max_lanes * 8) / 10; |
198 | } |
199 | } |
199 | 200 | ||
200 | static enum drm_mode_status |
201 | static enum drm_mode_status |
201 | intel_dp_mode_valid(struct drm_connector *connector, |
202 | intel_dp_mode_valid(struct drm_connector *connector, |
202 | struct drm_display_mode *mode) |
203 | struct drm_display_mode *mode) |
203 | { |
204 | { |
204 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
205 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
205 | struct intel_connector *intel_connector = to_intel_connector(connector); |
206 | struct intel_connector *intel_connector = to_intel_connector(connector); |
206 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
207 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
207 | int target_clock = mode->clock; |
208 | int target_clock = mode->clock; |
208 | int max_rate, mode_rate, max_lanes, max_link_clock; |
209 | int max_rate, mode_rate, max_lanes, max_link_clock; |
209 | 210 | ||
210 | if (is_edp(intel_dp) && fixed_mode) { |
211 | if (is_edp(intel_dp) && fixed_mode) { |
211 | if (mode->hdisplay > fixed_mode->hdisplay) |
212 | if (mode->hdisplay > fixed_mode->hdisplay) |
212 | return MODE_PANEL; |
213 | return MODE_PANEL; |
213 | 214 | ||
214 | if (mode->vdisplay > fixed_mode->vdisplay) |
215 | if (mode->vdisplay > fixed_mode->vdisplay) |
215 | return MODE_PANEL; |
216 | return MODE_PANEL; |
216 | 217 | ||
217 | target_clock = fixed_mode->clock; |
218 | target_clock = fixed_mode->clock; |
218 | } |
219 | } |
219 | 220 | ||
220 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
221 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
221 | max_lanes = intel_dp_max_lane_count(intel_dp); |
222 | max_lanes = intel_dp_max_lane_count(intel_dp); |
222 | 223 | ||
223 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
224 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
224 | mode_rate = intel_dp_link_required(target_clock, 18); |
225 | mode_rate = intel_dp_link_required(target_clock, 18); |
225 | 226 | ||
226 | if (mode_rate > max_rate) |
227 | if (mode_rate > max_rate) |
227 | return MODE_CLOCK_HIGH; |
228 | return MODE_CLOCK_HIGH; |
228 | 229 | ||
229 | if (mode->clock < 10000) |
230 | if (mode->clock < 10000) |
230 | return MODE_CLOCK_LOW; |
231 | return MODE_CLOCK_LOW; |
231 | 232 | ||
232 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
233 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
233 | return MODE_H_ILLEGAL; |
234 | return MODE_H_ILLEGAL; |
234 | 235 | ||
235 | return MODE_OK; |
236 | return MODE_OK; |
236 | } |
237 | } |
237 | 238 | ||
238 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
239 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
239 | { |
240 | { |
240 | int i; |
241 | int i; |
241 | uint32_t v = 0; |
242 | uint32_t v = 0; |
242 | 243 | ||
243 | if (src_bytes > 4) |
244 | if (src_bytes > 4) |
244 | src_bytes = 4; |
245 | src_bytes = 4; |
245 | for (i = 0; i < src_bytes; i++) |
246 | for (i = 0; i < src_bytes; i++) |
246 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
247 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
247 | return v; |
248 | return v; |
248 | } |
249 | } |
249 | 250 | ||
250 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
251 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
251 | { |
252 | { |
252 | int i; |
253 | int i; |
253 | if (dst_bytes > 4) |
254 | if (dst_bytes > 4) |
254 | dst_bytes = 4; |
255 | dst_bytes = 4; |
255 | for (i = 0; i < dst_bytes; i++) |
256 | for (i = 0; i < dst_bytes; i++) |
256 | dst[i] = src >> ((3-i) * 8); |
257 | dst[i] = src >> ((3-i) * 8); |
257 | } |
258 | } |
258 | 259 | ||
259 | static void |
260 | static void |
260 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
261 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
261 | struct intel_dp *intel_dp); |
262 | struct intel_dp *intel_dp); |
262 | static void |
263 | static void |
263 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
264 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
264 | struct intel_dp *intel_dp); |
265 | struct intel_dp *intel_dp); |
265 | 266 | ||
266 | static void pps_lock(struct intel_dp *intel_dp) |
267 | static void pps_lock(struct intel_dp *intel_dp) |
267 | { |
268 | { |
268 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
269 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
269 | struct intel_encoder *encoder = &intel_dig_port->base; |
270 | struct intel_encoder *encoder = &intel_dig_port->base; |
270 | struct drm_device *dev = encoder->base.dev; |
271 | struct drm_device *dev = encoder->base.dev; |
271 | struct drm_i915_private *dev_priv = dev->dev_private; |
272 | struct drm_i915_private *dev_priv = dev->dev_private; |
272 | enum intel_display_power_domain power_domain; |
273 | enum intel_display_power_domain power_domain; |
273 | 274 | ||
274 | /* |
275 | /* |
275 | * See vlv_power_sequencer_reset() why we need |
276 | * See vlv_power_sequencer_reset() why we need |
276 | * a power domain reference here. |
277 | * a power domain reference here. |
277 | */ |
278 | */ |
278 | power_domain = intel_display_port_aux_power_domain(encoder); |
279 | power_domain = intel_display_port_aux_power_domain(encoder); |
279 | intel_display_power_get(dev_priv, power_domain); |
280 | intel_display_power_get(dev_priv, power_domain); |
280 | 281 | ||
281 | mutex_lock(&dev_priv->pps_mutex); |
282 | mutex_lock(&dev_priv->pps_mutex); |
282 | } |
283 | } |
283 | 284 | ||
284 | static void pps_unlock(struct intel_dp *intel_dp) |
285 | static void pps_unlock(struct intel_dp *intel_dp) |
285 | { |
286 | { |
286 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
287 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
287 | struct intel_encoder *encoder = &intel_dig_port->base; |
288 | struct intel_encoder *encoder = &intel_dig_port->base; |
288 | struct drm_device *dev = encoder->base.dev; |
289 | struct drm_device *dev = encoder->base.dev; |
289 | struct drm_i915_private *dev_priv = dev->dev_private; |
290 | struct drm_i915_private *dev_priv = dev->dev_private; |
290 | enum intel_display_power_domain power_domain; |
291 | enum intel_display_power_domain power_domain; |
291 | 292 | ||
292 | mutex_unlock(&dev_priv->pps_mutex); |
293 | mutex_unlock(&dev_priv->pps_mutex); |
293 | 294 | ||
294 | power_domain = intel_display_port_aux_power_domain(encoder); |
295 | power_domain = intel_display_port_aux_power_domain(encoder); |
295 | intel_display_power_put(dev_priv, power_domain); |
296 | intel_display_power_put(dev_priv, power_domain); |
296 | } |
297 | } |
297 | 298 | ||
298 | static void |
299 | static void |
299 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
300 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
300 | { |
301 | { |
301 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
302 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
302 | struct drm_device *dev = intel_dig_port->base.base.dev; |
303 | struct drm_device *dev = intel_dig_port->base.base.dev; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; |
304 | struct drm_i915_private *dev_priv = dev->dev_private; |
304 | enum pipe pipe = intel_dp->pps_pipe; |
305 | enum pipe pipe = intel_dp->pps_pipe; |
305 | bool pll_enabled, release_cl_override = false; |
306 | bool pll_enabled, release_cl_override = false; |
306 | enum dpio_phy phy = DPIO_PHY(pipe); |
307 | enum dpio_phy phy = DPIO_PHY(pipe); |
307 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
308 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
308 | uint32_t DP; |
309 | uint32_t DP; |
309 | 310 | ||
310 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
311 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
311 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
312 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
312 | pipe_name(pipe), port_name(intel_dig_port->port))) |
313 | pipe_name(pipe), port_name(intel_dig_port->port))) |
313 | return; |
314 | return; |
314 | 315 | ||
315 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
316 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
316 | pipe_name(pipe), port_name(intel_dig_port->port)); |
317 | pipe_name(pipe), port_name(intel_dig_port->port)); |
317 | 318 | ||
318 | /* Preserve the BIOS-computed detected bit. This is |
319 | /* Preserve the BIOS-computed detected bit. This is |
319 | * supposed to be read-only. |
320 | * supposed to be read-only. |
320 | */ |
321 | */ |
321 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
322 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
322 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
323 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
323 | DP |= DP_PORT_WIDTH(1); |
324 | DP |= DP_PORT_WIDTH(1); |
324 | DP |= DP_LINK_TRAIN_PAT_1; |
325 | DP |= DP_LINK_TRAIN_PAT_1; |
325 | 326 | ||
326 | if (IS_CHERRYVIEW(dev)) |
327 | if (IS_CHERRYVIEW(dev)) |
327 | DP |= DP_PIPE_SELECT_CHV(pipe); |
328 | DP |= DP_PIPE_SELECT_CHV(pipe); |
328 | else if (pipe == PIPE_B) |
329 | else if (pipe == PIPE_B) |
329 | DP |= DP_PIPEB_SELECT; |
330 | DP |= DP_PIPEB_SELECT; |
330 | 331 | ||
331 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
332 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
332 | 333 | ||
333 | /* |
334 | /* |
334 | * The DPLL for the pipe must be enabled for this to work. |
335 | * The DPLL for the pipe must be enabled for this to work. |
335 | * So enable temporarily it if it's not already enabled. |
336 | * So enable temporarily it if it's not already enabled. |
336 | */ |
337 | */ |
337 | if (!pll_enabled) { |
338 | if (!pll_enabled) { |
338 | release_cl_override = IS_CHERRYVIEW(dev) && |
339 | release_cl_override = IS_CHERRYVIEW(dev) && |
339 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
340 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
340 | 341 | ||
341 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
342 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
342 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
343 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
343 | } |
344 | } |
344 | 345 | ||
345 | /* |
346 | /* |
346 | * Similar magic as in intel_dp_enable_port(). |
347 | * Similar magic as in intel_dp_enable_port(). |
347 | * We _must_ do this port enable + disable trick |
348 | * We _must_ do this port enable + disable trick |
348 | * to make this power seqeuencer lock onto the port. |
349 | * to make this power seqeuencer lock onto the port. |
349 | * Otherwise even VDD force bit won't work. |
350 | * Otherwise even VDD force bit won't work. |
350 | */ |
351 | */ |
351 | I915_WRITE(intel_dp->output_reg, DP); |
352 | I915_WRITE(intel_dp->output_reg, DP); |
352 | POSTING_READ(intel_dp->output_reg); |
353 | POSTING_READ(intel_dp->output_reg); |
353 | 354 | ||
354 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
355 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
355 | POSTING_READ(intel_dp->output_reg); |
356 | POSTING_READ(intel_dp->output_reg); |
356 | 357 | ||
357 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
358 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
358 | POSTING_READ(intel_dp->output_reg); |
359 | POSTING_READ(intel_dp->output_reg); |
359 | 360 | ||
360 | if (!pll_enabled) { |
361 | if (!pll_enabled) { |
361 | vlv_force_pll_off(dev, pipe); |
362 | vlv_force_pll_off(dev, pipe); |
362 | 363 | ||
363 | if (release_cl_override) |
364 | if (release_cl_override) |
364 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
365 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
365 | } |
366 | } |
366 | } |
367 | } |
367 | 368 | ||
368 | static enum pipe |
369 | static enum pipe |
369 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
370 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
370 | { |
371 | { |
371 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
372 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
372 | struct drm_device *dev = intel_dig_port->base.base.dev; |
373 | struct drm_device *dev = intel_dig_port->base.base.dev; |
373 | struct drm_i915_private *dev_priv = dev->dev_private; |
374 | struct drm_i915_private *dev_priv = dev->dev_private; |
374 | struct intel_encoder *encoder; |
375 | struct intel_encoder *encoder; |
375 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
376 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
376 | enum pipe pipe; |
377 | enum pipe pipe; |
377 | 378 | ||
378 | lockdep_assert_held(&dev_priv->pps_mutex); |
379 | lockdep_assert_held(&dev_priv->pps_mutex); |
379 | 380 | ||
380 | /* We should never land here with regular DP ports */ |
381 | /* We should never land here with regular DP ports */ |
381 | WARN_ON(!is_edp(intel_dp)); |
382 | WARN_ON(!is_edp(intel_dp)); |
382 | 383 | ||
383 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | return intel_dp->pps_pipe; |
385 | return intel_dp->pps_pipe; |
385 | 386 | ||
386 | /* |
387 | /* |
387 | * We don't have power sequencer currently. |
388 | * We don't have power sequencer currently. |
388 | * Pick one that's not used by other ports. |
389 | * Pick one that's not used by other ports. |
389 | */ |
390 | */ |
390 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
391 | for_each_intel_encoder(dev, encoder) { |
391 | base.head) { |
- | |
392 | struct intel_dp *tmp; |
392 | struct intel_dp *tmp; |
393 | 393 | ||
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
395 | continue; |
395 | continue; |
396 | 396 | ||
397 | tmp = enc_to_intel_dp(&encoder->base); |
397 | tmp = enc_to_intel_dp(&encoder->base); |
398 | 398 | ||
399 | if (tmp->pps_pipe != INVALID_PIPE) |
399 | if (tmp->pps_pipe != INVALID_PIPE) |
400 | pipes &= ~(1 << tmp->pps_pipe); |
400 | pipes &= ~(1 << tmp->pps_pipe); |
401 | } |
401 | } |
402 | 402 | ||
403 | /* |
403 | /* |
404 | * Didn't find one. This should not happen since there |
404 | * Didn't find one. This should not happen since there |
405 | * are two power sequencers and up to two eDP ports. |
405 | * are two power sequencers and up to two eDP ports. |
406 | */ |
406 | */ |
407 | if (WARN_ON(pipes == 0)) |
407 | if (WARN_ON(pipes == 0)) |
408 | pipe = PIPE_A; |
408 | pipe = PIPE_A; |
409 | else |
409 | else |
410 | pipe = ffs(pipes) - 1; |
410 | pipe = ffs(pipes) - 1; |
411 | 411 | ||
412 | vlv_steal_power_sequencer(dev, pipe); |
412 | vlv_steal_power_sequencer(dev, pipe); |
413 | intel_dp->pps_pipe = pipe; |
413 | intel_dp->pps_pipe = pipe; |
414 | 414 | ||
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
416 | pipe_name(intel_dp->pps_pipe), |
416 | pipe_name(intel_dp->pps_pipe), |
417 | port_name(intel_dig_port->port)); |
417 | port_name(intel_dig_port->port)); |
418 | 418 | ||
419 | /* init power sequencer on this pipe and port */ |
419 | /* init power sequencer on this pipe and port */ |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
422 | 422 | ||
423 | /* |
423 | /* |
424 | * Even vdd force doesn't work until we've made |
424 | * Even vdd force doesn't work until we've made |
425 | * the power sequencer lock in on the port. |
425 | * the power sequencer lock in on the port. |
426 | */ |
426 | */ |
427 | vlv_power_sequencer_kick(intel_dp); |
427 | vlv_power_sequencer_kick(intel_dp); |
428 | 428 | ||
429 | return intel_dp->pps_pipe; |
429 | return intel_dp->pps_pipe; |
430 | } |
430 | } |
431 | 431 | ||
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
433 | enum pipe pipe); |
433 | enum pipe pipe); |
434 | 434 | ||
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
436 | enum pipe pipe) |
436 | enum pipe pipe) |
437 | { |
437 | { |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
439 | } |
439 | } |
440 | 440 | ||
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
442 | enum pipe pipe) |
442 | enum pipe pipe) |
443 | { |
443 | { |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
445 | } |
445 | } |
446 | 446 | ||
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
448 | enum pipe pipe) |
448 | enum pipe pipe) |
449 | { |
449 | { |
450 | return true; |
450 | return true; |
451 | } |
451 | } |
452 | 452 | ||
453 | static enum pipe |
453 | static enum pipe |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
455 | enum port port, |
455 | enum port port, |
456 | vlv_pipe_check pipe_check) |
456 | vlv_pipe_check pipe_check) |
457 | { |
457 | { |
458 | enum pipe pipe; |
458 | enum pipe pipe; |
459 | 459 | ||
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
462 | PANEL_PORT_SELECT_MASK; |
462 | PANEL_PORT_SELECT_MASK; |
463 | 463 | ||
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
465 | continue; |
465 | continue; |
466 | 466 | ||
467 | if (!pipe_check(dev_priv, pipe)) |
467 | if (!pipe_check(dev_priv, pipe)) |
468 | continue; |
468 | continue; |
469 | 469 | ||
470 | return pipe; |
470 | return pipe; |
471 | } |
471 | } |
472 | 472 | ||
473 | return INVALID_PIPE; |
473 | return INVALID_PIPE; |
474 | } |
474 | } |
475 | 475 | ||
476 | static void |
476 | static void |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
478 | { |
478 | { |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
482 | enum port port = intel_dig_port->port; |
482 | enum port port = intel_dig_port->port; |
483 | 483 | ||
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
485 | 485 | ||
486 | /* try to find a pipe with this port selected */ |
486 | /* try to find a pipe with this port selected */ |
487 | /* first pick one where the panel is on */ |
487 | /* first pick one where the panel is on */ |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
489 | vlv_pipe_has_pp_on); |
489 | vlv_pipe_has_pp_on); |
490 | /* didn't find one? pick one where vdd is on */ |
490 | /* didn't find one? pick one where vdd is on */ |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
493 | vlv_pipe_has_vdd_on); |
493 | vlv_pipe_has_vdd_on); |
494 | /* didn't find one? pick one with just the correct port */ |
494 | /* didn't find one? pick one with just the correct port */ |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
497 | vlv_pipe_any); |
497 | vlv_pipe_any); |
498 | 498 | ||
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
502 | port_name(port)); |
502 | port_name(port)); |
503 | return; |
503 | return; |
504 | } |
504 | } |
505 | 505 | ||
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
508 | 508 | ||
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
511 | } |
511 | } |
512 | 512 | ||
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
514 | { |
514 | { |
515 | struct drm_device *dev = dev_priv->dev; |
515 | struct drm_device *dev = dev_priv->dev; |
516 | struct intel_encoder *encoder; |
516 | struct intel_encoder *encoder; |
517 | 517 | ||
518 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
518 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
519 | return; |
519 | return; |
520 | 520 | ||
521 | /* |
521 | /* |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
524 | * That also means that in order to use pps_pipe the code needs to |
524 | * That also means that in order to use pps_pipe the code needs to |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
528 | * should use them always. |
528 | * should use them always. |
529 | */ |
529 | */ |
530 | 530 | ||
531 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
531 | for_each_intel_encoder(dev, encoder) { |
532 | struct intel_dp *intel_dp; |
532 | struct intel_dp *intel_dp; |
533 | 533 | ||
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
535 | continue; |
535 | continue; |
536 | 536 | ||
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
539 | } |
539 | } |
540 | } |
540 | } |
- | 541 | ||
541 | 542 | static i915_reg_t |
|
542 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
543 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
543 | { |
544 | { |
544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
545 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
545 | 546 | ||
546 | if (IS_BROXTON(dev)) |
547 | if (IS_BROXTON(dev)) |
547 | return BXT_PP_CONTROL(0); |
548 | return BXT_PP_CONTROL(0); |
548 | else if (HAS_PCH_SPLIT(dev)) |
549 | else if (HAS_PCH_SPLIT(dev)) |
549 | return PCH_PP_CONTROL; |
550 | return PCH_PP_CONTROL; |
550 | else |
551 | else |
551 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | } |
553 | } |
- | 554 | ||
553 | 555 | static i915_reg_t |
|
554 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
556 | _pp_stat_reg(struct intel_dp *intel_dp) |
555 | { |
557 | { |
556 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
557 | 559 | ||
558 | if (IS_BROXTON(dev)) |
560 | if (IS_BROXTON(dev)) |
559 | return BXT_PP_STATUS(0); |
561 | return BXT_PP_STATUS(0); |
560 | else if (HAS_PCH_SPLIT(dev)) |
562 | else if (HAS_PCH_SPLIT(dev)) |
561 | return PCH_PP_STATUS; |
563 | return PCH_PP_STATUS; |
562 | else |
564 | else |
563 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
565 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
564 | } |
566 | } |
565 | 567 | ||
566 | #if 0 |
568 | #if 0 |
567 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
569 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
568 | This function only applicable when panel PM state is not to be tracked */ |
570 | This function only applicable when panel PM state is not to be tracked */ |
569 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
571 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
570 | void *unused) |
572 | void *unused) |
571 | { |
573 | { |
572 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
574 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
573 | edp_notifier); |
575 | edp_notifier); |
574 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
576 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
575 | struct drm_i915_private *dev_priv = dev->dev_private; |
577 | struct drm_i915_private *dev_priv = dev->dev_private; |
576 | 578 | ||
577 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
579 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
578 | return 0; |
580 | return 0; |
579 | 581 | ||
580 | pps_lock(intel_dp); |
582 | pps_lock(intel_dp); |
581 | 583 | ||
582 | if (IS_VALLEYVIEW(dev)) { |
584 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
583 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
585 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
584 | u32 pp_ctrl_reg, pp_div_reg; |
586 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
585 | u32 pp_div; |
587 | u32 pp_div; |
586 | 588 | ||
587 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
589 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
588 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
590 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
589 | pp_div = I915_READ(pp_div_reg); |
591 | pp_div = I915_READ(pp_div_reg); |
590 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
592 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
591 | 593 | ||
592 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
594 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
593 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
595 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
594 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
596 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
595 | msleep(intel_dp->panel_power_cycle_delay); |
597 | msleep(intel_dp->panel_power_cycle_delay); |
596 | } |
598 | } |
597 | 599 | ||
598 | pps_unlock(intel_dp); |
600 | pps_unlock(intel_dp); |
599 | 601 | ||
600 | return 0; |
602 | return 0; |
601 | } |
603 | } |
602 | #endif |
604 | #endif |
603 | 605 | ||
604 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
606 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
605 | { |
607 | { |
606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
607 | struct drm_i915_private *dev_priv = dev->dev_private; |
609 | struct drm_i915_private *dev_priv = dev->dev_private; |
608 | 610 | ||
609 | lockdep_assert_held(&dev_priv->pps_mutex); |
611 | lockdep_assert_held(&dev_priv->pps_mutex); |
610 | 612 | ||
611 | if (IS_VALLEYVIEW(dev) && |
613 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
612 | intel_dp->pps_pipe == INVALID_PIPE) |
614 | intel_dp->pps_pipe == INVALID_PIPE) |
613 | return false; |
615 | return false; |
614 | 616 | ||
615 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
617 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
616 | } |
618 | } |
617 | 619 | ||
618 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
620 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
619 | { |
621 | { |
620 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
622 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
621 | struct drm_i915_private *dev_priv = dev->dev_private; |
623 | struct drm_i915_private *dev_priv = dev->dev_private; |
622 | 624 | ||
623 | lockdep_assert_held(&dev_priv->pps_mutex); |
625 | lockdep_assert_held(&dev_priv->pps_mutex); |
624 | 626 | ||
625 | if (IS_VALLEYVIEW(dev) && |
627 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
626 | intel_dp->pps_pipe == INVALID_PIPE) |
628 | intel_dp->pps_pipe == INVALID_PIPE) |
627 | return false; |
629 | return false; |
628 | 630 | ||
629 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
631 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
630 | } |
632 | } |
631 | 633 | ||
632 | static void |
634 | static void |
633 | intel_dp_check_edp(struct intel_dp *intel_dp) |
635 | intel_dp_check_edp(struct intel_dp *intel_dp) |
634 | { |
636 | { |
635 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
637 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
636 | struct drm_i915_private *dev_priv = dev->dev_private; |
638 | struct drm_i915_private *dev_priv = dev->dev_private; |
637 | 639 | ||
638 | if (!is_edp(intel_dp)) |
640 | if (!is_edp(intel_dp)) |
639 | return; |
641 | return; |
640 | 642 | ||
641 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
643 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
642 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
644 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
643 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
645 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
644 | I915_READ(_pp_stat_reg(intel_dp)), |
646 | I915_READ(_pp_stat_reg(intel_dp)), |
645 | I915_READ(_pp_ctrl_reg(intel_dp))); |
647 | I915_READ(_pp_ctrl_reg(intel_dp))); |
646 | } |
648 | } |
647 | } |
649 | } |
648 | 650 | ||
649 | static uint32_t |
651 | static uint32_t |
650 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
652 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
651 | { |
653 | { |
652 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
654 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
653 | struct drm_device *dev = intel_dig_port->base.base.dev; |
655 | struct drm_device *dev = intel_dig_port->base.base.dev; |
654 | struct drm_i915_private *dev_priv = dev->dev_private; |
656 | struct drm_i915_private *dev_priv = dev->dev_private; |
655 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
657 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
656 | uint32_t status; |
658 | uint32_t status; |
657 | bool done; |
659 | bool done; |
658 | 660 | ||
659 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
661 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
660 | if (has_aux_irq) |
662 | if (has_aux_irq) |
661 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
663 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
662 | msecs_to_jiffies_timeout(10)); |
664 | msecs_to_jiffies_timeout(10)); |
663 | else |
665 | else |
664 | done = wait_for_atomic(C, 10) == 0; |
666 | done = wait_for_atomic(C, 10) == 0; |
665 | if (!done) |
667 | if (!done) |
666 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
668 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
667 | has_aux_irq); |
669 | has_aux_irq); |
668 | #undef C |
670 | #undef C |
669 | 671 | ||
670 | return status; |
672 | return status; |
671 | } |
673 | } |
672 | 674 | ||
673 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
675 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
674 | { |
676 | { |
675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
677 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
676 | struct drm_device *dev = intel_dig_port->base.base.dev; |
678 | struct drm_device *dev = intel_dig_port->base.base.dev; |
677 | 679 | ||
678 | /* |
680 | /* |
679 | * The clock divider is based off the hrawclk, and would like to run at |
681 | * The clock divider is based off the hrawclk, and would like to run at |
680 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
682 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
681 | */ |
683 | */ |
682 | return index ? 0 : intel_hrawclk(dev) / 2; |
684 | return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); |
683 | } |
685 | } |
684 | 686 | ||
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
687 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
686 | { |
688 | { |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
689 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
688 | struct drm_device *dev = intel_dig_port->base.base.dev; |
690 | struct drm_device *dev = intel_dig_port->base.base.dev; |
689 | struct drm_i915_private *dev_priv = dev->dev_private; |
691 | struct drm_i915_private *dev_priv = dev->dev_private; |
690 | 692 | ||
691 | if (index) |
693 | if (index) |
692 | return 0; |
694 | return 0; |
693 | 695 | ||
694 | if (intel_dig_port->port == PORT_A) { |
696 | if (intel_dig_port->port == PORT_A) { |
695 | return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); |
697 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
696 | 698 | ||
697 | } else { |
699 | } else { |
698 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
700 | return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
699 | } |
701 | } |
700 | } |
702 | } |
701 | 703 | ||
702 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
704 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
703 | { |
705 | { |
704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
705 | struct drm_device *dev = intel_dig_port->base.base.dev; |
707 | struct drm_device *dev = intel_dig_port->base.base.dev; |
706 | struct drm_i915_private *dev_priv = dev->dev_private; |
708 | struct drm_i915_private *dev_priv = dev->dev_private; |
707 | 709 | ||
708 | if (intel_dig_port->port == PORT_A) { |
710 | if (intel_dig_port->port == PORT_A) { |
709 | if (index) |
711 | if (index) |
710 | return 0; |
712 | return 0; |
711 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
713 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
712 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
714 | } else if (HAS_PCH_LPT_H(dev_priv)) { |
713 | /* Workaround for non-ULT HSW */ |
715 | /* Workaround for non-ULT HSW */ |
714 | switch (index) { |
716 | switch (index) { |
715 | case 0: return 63; |
717 | case 0: return 63; |
716 | case 1: return 72; |
718 | case 1: return 72; |
717 | default: return 0; |
719 | default: return 0; |
718 | } |
720 | } |
719 | } else { |
721 | } else { |
720 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
722 | return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
721 | } |
723 | } |
722 | } |
724 | } |
723 | 725 | ||
724 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
726 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
725 | { |
727 | { |
726 | return index ? 0 : 100; |
728 | return index ? 0 : 100; |
727 | } |
729 | } |
728 | 730 | ||
729 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
731 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
730 | { |
732 | { |
731 | /* |
733 | /* |
732 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
734 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
733 | * derive the clock from CDCLK automatically). We still implement the |
735 | * derive the clock from CDCLK automatically). We still implement the |
734 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
736 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
735 | */ |
737 | */ |
736 | return index ? 0 : 1; |
738 | return index ? 0 : 1; |
737 | } |
739 | } |
738 | 740 | ||
739 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
741 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
740 | bool has_aux_irq, |
742 | bool has_aux_irq, |
741 | int send_bytes, |
743 | int send_bytes, |
742 | uint32_t aux_clock_divider) |
744 | uint32_t aux_clock_divider) |
743 | { |
745 | { |
744 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
746 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
745 | struct drm_device *dev = intel_dig_port->base.base.dev; |
747 | struct drm_device *dev = intel_dig_port->base.base.dev; |
746 | uint32_t precharge, timeout; |
748 | uint32_t precharge, timeout; |
747 | 749 | ||
748 | if (IS_GEN6(dev)) |
750 | if (IS_GEN6(dev)) |
749 | precharge = 3; |
751 | precharge = 3; |
750 | else |
752 | else |
751 | precharge = 5; |
753 | precharge = 5; |
752 | 754 | ||
753 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
755 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
754 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
755 | else |
757 | else |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
758 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
757 | 759 | ||
758 | return DP_AUX_CH_CTL_SEND_BUSY | |
760 | return DP_AUX_CH_CTL_SEND_BUSY | |
759 | DP_AUX_CH_CTL_DONE | |
761 | DP_AUX_CH_CTL_DONE | |
760 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
762 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
761 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
763 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
762 | timeout | |
764 | timeout | |
763 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
765 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
764 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
766 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
765 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
767 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
766 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
768 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
767 | } |
769 | } |
768 | 770 | ||
769 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
771 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
770 | bool has_aux_irq, |
772 | bool has_aux_irq, |
771 | int send_bytes, |
773 | int send_bytes, |
772 | uint32_t unused) |
774 | uint32_t unused) |
773 | { |
775 | { |
774 | return DP_AUX_CH_CTL_SEND_BUSY | |
776 | return DP_AUX_CH_CTL_SEND_BUSY | |
775 | DP_AUX_CH_CTL_DONE | |
777 | DP_AUX_CH_CTL_DONE | |
776 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
778 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
777 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
779 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
778 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
780 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
779 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
781 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
780 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
782 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
781 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
783 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
782 | } |
784 | } |
783 | 785 | ||
784 | static int |
786 | static int |
785 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
787 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
786 | const uint8_t *send, int send_bytes, |
788 | const uint8_t *send, int send_bytes, |
787 | uint8_t *recv, int recv_size) |
789 | uint8_t *recv, int recv_size) |
788 | { |
790 | { |
789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
790 | struct drm_device *dev = intel_dig_port->base.base.dev; |
792 | struct drm_device *dev = intel_dig_port->base.base.dev; |
791 | struct drm_i915_private *dev_priv = dev->dev_private; |
793 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
794 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
793 | uint32_t ch_data = ch_ctl + 4; |
- | |
794 | uint32_t aux_clock_divider; |
795 | uint32_t aux_clock_divider; |
795 | int i, ret, recv_bytes; |
796 | int i, ret, recv_bytes; |
796 | uint32_t status; |
797 | uint32_t status; |
797 | int try, clock = 0; |
798 | int try, clock = 0; |
798 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
799 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
799 | bool vdd; |
800 | bool vdd; |
800 | 801 | ||
801 | pps_lock(intel_dp); |
802 | pps_lock(intel_dp); |
802 | 803 | ||
803 | /* |
804 | /* |
804 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
805 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
805 | * In such cases we want to leave VDD enabled and it's up to upper layers |
806 | * In such cases we want to leave VDD enabled and it's up to upper layers |
806 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
807 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
807 | * ourselves. |
808 | * ourselves. |
808 | */ |
809 | */ |
809 | vdd = edp_panel_vdd_on(intel_dp); |
810 | vdd = edp_panel_vdd_on(intel_dp); |
810 | 811 | ||
811 | /* dp aux is extremely sensitive to irq latency, hence request the |
812 | /* dp aux is extremely sensitive to irq latency, hence request the |
812 | * lowest possible wakeup latency and so prevent the cpu from going into |
813 | * lowest possible wakeup latency and so prevent the cpu from going into |
813 | * deep sleep states. |
814 | * deep sleep states. |
814 | */ |
815 | */ |
815 | 816 | ||
816 | intel_dp_check_edp(intel_dp); |
817 | intel_dp_check_edp(intel_dp); |
817 | 818 | ||
818 | /* Try to wait for any previous AUX channel activity */ |
819 | /* Try to wait for any previous AUX channel activity */ |
819 | for (try = 0; try < 3; try++) { |
820 | for (try = 0; try < 3; try++) { |
820 | status = I915_READ_NOTRACE(ch_ctl); |
821 | status = I915_READ_NOTRACE(ch_ctl); |
821 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
822 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
822 | break; |
823 | break; |
823 | msleep(1); |
824 | msleep(1); |
824 | } |
825 | } |
825 | 826 | ||
826 | if (try == 3) { |
827 | if (try == 3) { |
827 | static u32 last_status = -1; |
828 | static u32 last_status = -1; |
828 | const u32 status = I915_READ(ch_ctl); |
829 | const u32 status = I915_READ(ch_ctl); |
829 | 830 | ||
830 | if (status != last_status) { |
831 | if (status != last_status) { |
831 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
832 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
832 | status); |
833 | status); |
833 | last_status = status; |
834 | last_status = status; |
834 | } |
835 | } |
835 | 836 | ||
836 | ret = -EBUSY; |
837 | ret = -EBUSY; |
837 | goto out; |
838 | goto out; |
838 | } |
839 | } |
839 | 840 | ||
840 | /* Only 5 data registers! */ |
841 | /* Only 5 data registers! */ |
841 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
842 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
842 | ret = -E2BIG; |
843 | ret = -E2BIG; |
843 | goto out; |
844 | goto out; |
844 | } |
845 | } |
845 | 846 | ||
846 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
847 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
847 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
848 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
848 | has_aux_irq, |
849 | has_aux_irq, |
849 | send_bytes, |
850 | send_bytes, |
850 | aux_clock_divider); |
851 | aux_clock_divider); |
851 | 852 | ||
852 | /* Must try at least 3 times according to DP spec */ |
853 | /* Must try at least 3 times according to DP spec */ |
853 | for (try = 0; try < 5; try++) { |
854 | for (try = 0; try < 5; try++) { |
854 | /* Load the send data into the aux channel data registers */ |
855 | /* Load the send data into the aux channel data registers */ |
855 | for (i = 0; i < send_bytes; i += 4) |
856 | for (i = 0; i < send_bytes; i += 4) |
856 | I915_WRITE(ch_data + i, |
857 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
857 | intel_dp_pack_aux(send + i, |
858 | intel_dp_pack_aux(send + i, |
858 | send_bytes - i)); |
859 | send_bytes - i)); |
859 | 860 | ||
860 | /* Send the command and wait for it to complete */ |
861 | /* Send the command and wait for it to complete */ |
861 | I915_WRITE(ch_ctl, send_ctl); |
862 | I915_WRITE(ch_ctl, send_ctl); |
862 | 863 | ||
863 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
864 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
864 | 865 | ||
865 | /* Clear done status and any errors */ |
866 | /* Clear done status and any errors */ |
866 | I915_WRITE(ch_ctl, |
867 | I915_WRITE(ch_ctl, |
867 | status | |
868 | status | |
868 | DP_AUX_CH_CTL_DONE | |
869 | DP_AUX_CH_CTL_DONE | |
869 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
870 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
870 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
871 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
871 | 872 | ||
872 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
873 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
873 | continue; |
874 | continue; |
874 | 875 | ||
875 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
876 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
876 | * 400us delay required for errors and timeouts |
877 | * 400us delay required for errors and timeouts |
877 | * Timeout errors from the HW already meet this |
878 | * Timeout errors from the HW already meet this |
878 | * requirement so skip to next iteration |
879 | * requirement so skip to next iteration |
879 | */ |
880 | */ |
880 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
881 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
881 | usleep_range(400, 500); |
882 | usleep_range(400, 500); |
882 | continue; |
883 | continue; |
883 | } |
884 | } |
884 | if (status & DP_AUX_CH_CTL_DONE) |
885 | if (status & DP_AUX_CH_CTL_DONE) |
885 | goto done; |
886 | goto done; |
886 | } |
887 | } |
887 | } |
888 | } |
888 | 889 | ||
889 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
890 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
890 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
891 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
891 | ret = -EBUSY; |
892 | ret = -EBUSY; |
892 | goto out; |
893 | goto out; |
893 | } |
894 | } |
894 | 895 | ||
895 | done: |
896 | done: |
896 | /* Check for timeout or receive error. |
897 | /* Check for timeout or receive error. |
897 | * Timeouts occur when the sink is not connected |
898 | * Timeouts occur when the sink is not connected |
898 | */ |
899 | */ |
899 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
900 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
900 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
901 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
901 | ret = -EIO; |
902 | ret = -EIO; |
902 | goto out; |
903 | goto out; |
903 | } |
904 | } |
904 | 905 | ||
905 | /* Timeouts occur when the device isn't connected, so they're |
906 | /* Timeouts occur when the device isn't connected, so they're |
906 | * "normal" -- don't fill the kernel log with these */ |
907 | * "normal" -- don't fill the kernel log with these */ |
907 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
908 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
908 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
909 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
909 | ret = -ETIMEDOUT; |
910 | ret = -ETIMEDOUT; |
910 | goto out; |
911 | goto out; |
911 | } |
912 | } |
912 | 913 | ||
913 | /* Unload any bytes sent back from the other side */ |
914 | /* Unload any bytes sent back from the other side */ |
914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
915 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
916 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
- | 917 | ||
- | 918 | /* |
|
- | 919 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
|
- | 920 | * We have no idea of what happened so we return -EBUSY so |
|
- | 921 | * drm layer takes care for the necessary retries. |
|
- | 922 | */ |
|
- | 923 | if (recv_bytes == 0 || recv_bytes > 20) { |
|
- | 924 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
|
- | 925 | recv_bytes); |
|
- | 926 | /* |
|
- | 927 | * FIXME: This patch was created on top of a series that |
|
- | 928 | * organize the retries at drm level. There EBUSY should |
|
- | 929 | * also take care for 1ms wait before retrying. |
|
- | 930 | * That aux retries re-org is still needed and after that is |
|
- | 931 | * merged we remove this sleep from here. |
|
- | 932 | */ |
|
- | 933 | usleep_range(1000, 1500); |
|
- | 934 | ret = -EBUSY; |
|
- | 935 | goto out; |
|
- | 936 | } |
|
- | 937 | ||
916 | if (recv_bytes > recv_size) |
938 | if (recv_bytes > recv_size) |
917 | recv_bytes = recv_size; |
939 | recv_bytes = recv_size; |
918 | 940 | ||
919 | for (i = 0; i < recv_bytes; i += 4) |
941 | for (i = 0; i < recv_bytes; i += 4) |
920 | intel_dp_unpack_aux(I915_READ(ch_data + i), |
942 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
921 | recv + i, recv_bytes - i); |
943 | recv + i, recv_bytes - i); |
922 | 944 | ||
923 | ret = recv_bytes; |
945 | ret = recv_bytes; |
924 | out: |
946 | out: |
925 | 947 | ||
926 | if (vdd) |
948 | if (vdd) |
927 | edp_panel_vdd_off(intel_dp, false); |
949 | edp_panel_vdd_off(intel_dp, false); |
928 | 950 | ||
929 | pps_unlock(intel_dp); |
951 | pps_unlock(intel_dp); |
930 | 952 | ||
931 | return ret; |
953 | return ret; |
932 | } |
954 | } |
933 | 955 | ||
934 | #define BARE_ADDRESS_SIZE 3 |
956 | #define BARE_ADDRESS_SIZE 3 |
935 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
957 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
936 | static ssize_t |
958 | static ssize_t |
937 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
959 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
938 | { |
960 | { |
939 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
961 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
940 | uint8_t txbuf[20], rxbuf[20]; |
962 | uint8_t txbuf[20], rxbuf[20]; |
941 | size_t txsize, rxsize; |
963 | size_t txsize, rxsize; |
942 | int ret; |
964 | int ret; |
943 | 965 | ||
944 | txbuf[0] = (msg->request << 4) | |
966 | txbuf[0] = (msg->request << 4) | |
945 | ((msg->address >> 16) & 0xf); |
967 | ((msg->address >> 16) & 0xf); |
946 | txbuf[1] = (msg->address >> 8) & 0xff; |
968 | txbuf[1] = (msg->address >> 8) & 0xff; |
947 | txbuf[2] = msg->address & 0xff; |
969 | txbuf[2] = msg->address & 0xff; |
948 | txbuf[3] = msg->size - 1; |
970 | txbuf[3] = msg->size - 1; |
949 | 971 | ||
950 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
972 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
951 | case DP_AUX_NATIVE_WRITE: |
973 | case DP_AUX_NATIVE_WRITE: |
952 | case DP_AUX_I2C_WRITE: |
974 | case DP_AUX_I2C_WRITE: |
953 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
975 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
954 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
976 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
955 | rxsize = 2; /* 0 or 1 data bytes */ |
977 | rxsize = 2; /* 0 or 1 data bytes */ |
956 | 978 | ||
957 | if (WARN_ON(txsize > 20)) |
979 | if (WARN_ON(txsize > 20)) |
958 | return -E2BIG; |
980 | return -E2BIG; |
959 | 981 | ||
960 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
982 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
961 | 983 | ||
962 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
963 | if (ret > 0) { |
985 | if (ret > 0) { |
964 | msg->reply = rxbuf[0] >> 4; |
986 | msg->reply = rxbuf[0] >> 4; |
965 | 987 | ||
966 | if (ret > 1) { |
988 | if (ret > 1) { |
967 | /* Number of bytes written in a short write. */ |
989 | /* Number of bytes written in a short write. */ |
968 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
990 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
969 | } else { |
991 | } else { |
970 | /* Return payload size. */ |
992 | /* Return payload size. */ |
971 | ret = msg->size; |
993 | ret = msg->size; |
972 | } |
994 | } |
973 | } |
995 | } |
974 | break; |
996 | break; |
975 | 997 | ||
976 | case DP_AUX_NATIVE_READ: |
998 | case DP_AUX_NATIVE_READ: |
977 | case DP_AUX_I2C_READ: |
999 | case DP_AUX_I2C_READ: |
978 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
1000 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
979 | rxsize = msg->size + 1; |
1001 | rxsize = msg->size + 1; |
980 | 1002 | ||
981 | if (WARN_ON(rxsize > 20)) |
1003 | if (WARN_ON(rxsize > 20)) |
982 | return -E2BIG; |
1004 | return -E2BIG; |
983 | 1005 | ||
984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1006 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
985 | if (ret > 0) { |
1007 | if (ret > 0) { |
986 | msg->reply = rxbuf[0] >> 4; |
1008 | msg->reply = rxbuf[0] >> 4; |
987 | /* |
1009 | /* |
988 | * Assume happy day, and copy the data. The caller is |
1010 | * Assume happy day, and copy the data. The caller is |
989 | * expected to check msg->reply before touching it. |
1011 | * expected to check msg->reply before touching it. |
990 | * |
1012 | * |
991 | * Return payload size. |
1013 | * Return payload size. |
992 | */ |
1014 | */ |
993 | ret--; |
1015 | ret--; |
994 | memcpy(msg->buffer, rxbuf + 1, ret); |
1016 | memcpy(msg->buffer, rxbuf + 1, ret); |
995 | } |
1017 | } |
996 | break; |
1018 | break; |
997 | 1019 | ||
998 | default: |
1020 | default: |
999 | ret = -EINVAL; |
1021 | ret = -EINVAL; |
1000 | break; |
1022 | break; |
1001 | } |
1023 | } |
1002 | 1024 | ||
1003 | return ret; |
1025 | return ret; |
1004 | } |
1026 | } |
1005 | - | ||
1006 | static void |
1027 | |
- | 1028 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
|
1007 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1029 | enum port port) |
- | 1030 | { |
|
- | 1031 | switch (port) { |
|
- | 1032 | case PORT_B: |
|
- | 1033 | case PORT_C: |
|
- | 1034 | case PORT_D: |
|
- | 1035 | return DP_AUX_CH_CTL(port); |
|
- | 1036 | default: |
|
1008 | { |
1037 | MISSING_CASE(port); |
- | 1038 | return DP_AUX_CH_CTL(PORT_B); |
|
- | 1039 | } |
|
- | 1040 | } |
|
1009 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1041 | |
- | 1042 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
|
- | 1043 | enum port port, int index) |
|
- | 1044 | { |
|
- | 1045 | switch (port) { |
|
- | 1046 | case PORT_B: |
|
- | 1047 | case PORT_C: |
|
- | 1048 | case PORT_D: |
|
- | 1049 | return DP_AUX_CH_DATA(port, index); |
|
- | 1050 | default: |
|
- | 1051 | MISSING_CASE(port); |
|
- | 1052 | return DP_AUX_CH_DATA(PORT_B, index); |
|
- | 1053 | } |
|
- | 1054 | } |
|
1010 | struct drm_i915_private *dev_priv = dev->dev_private; |
1055 | |
1011 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1056 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
- | 1057 | enum port port) |
|
- | 1058 | { |
|
- | 1059 | switch (port) { |
|
- | 1060 | case PORT_A: |
|
- | 1061 | return DP_AUX_CH_CTL(port); |
|
- | 1062 | case PORT_B: |
|
- | 1063 | case PORT_C: |
|
- | 1064 | case PORT_D: |
|
- | 1065 | return PCH_DP_AUX_CH_CTL(port); |
|
- | 1066 | default: |
|
- | 1067 | MISSING_CASE(port); |
|
- | 1068 | return DP_AUX_CH_CTL(PORT_A); |
|
- | 1069 | } |
|
- | 1070 | } |
|
1012 | enum port port = intel_dig_port->port; |
1071 | |
1013 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
1072 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
- | 1073 | enum port port, int index) |
|
- | 1074 | { |
|
- | 1075 | switch (port) { |
|
- | 1076 | case PORT_A: |
|
- | 1077 | return DP_AUX_CH_DATA(port, index); |
|
- | 1078 | case PORT_B: |
|
- | 1079 | case PORT_C: |
|
1014 | const char *name = NULL; |
1080 | case PORT_D: |
1015 | uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1081 | return PCH_DP_AUX_CH_DATA(port, index); |
- | 1082 | default: |
|
- | 1083 | MISSING_CASE(port); |
|
- | 1084 | return DP_AUX_CH_DATA(PORT_A, index); |
|
- | 1085 | } |
|
- | 1086 | } |
|
1016 | int ret; |
1087 | |
1017 | 1088 | /* |
|
1018 | /* On SKL we don't have Aux for port E so we rely on VBT to set |
1089 | * On SKL we don't have Aux for port E so we rely |
- | 1090 | * on VBT to set a proper alternate aux channel. |
|
- | 1091 | */ |
|
- | 1092 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
|
1019 | * a proper alternate aux channel. |
1093 | { |
- | 1094 | const struct ddi_vbt_port_info *info = |
|
1020 | */ |
1095 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
- | 1096 | ||
- | 1097 | switch (info->alternate_aux_channel) { |
|
1021 | if (IS_SKYLAKE(dev) && port == PORT_E) { |
1098 | case DP_AUX_A: |
1022 | switch (info->alternate_aux_channel) { |
- | |
1023 | case DP_AUX_B: |
1099 | return PORT_A; |
1024 | porte_aux_ctl_reg = DPB_AUX_CH_CTL; |
1100 | case DP_AUX_B: |
1025 | break; |
- | |
1026 | case DP_AUX_C: |
1101 | return PORT_B; |
1027 | porte_aux_ctl_reg = DPC_AUX_CH_CTL; |
1102 | case DP_AUX_C: |
1028 | break; |
- | |
1029 | case DP_AUX_D: |
- | |
1030 | porte_aux_ctl_reg = DPD_AUX_CH_CTL; |
1103 | return PORT_C; |
1031 | break; |
1104 | case DP_AUX_D: |
1032 | case DP_AUX_A: |
1105 | return PORT_D; |
- | 1106 | default: |
|
1033 | default: |
1107 | MISSING_CASE(info->alternate_aux_channel); |
1034 | porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1108 | return PORT_A; |
1035 | } |
1109 | } |
1036 | } |
1110 | } |
- | 1111 | ||
- | 1112 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
|
- | 1113 | enum port port) |
|
- | 1114 | { |
|
- | 1115 | if (port == PORT_E) |
|
- | 1116 | port = skl_porte_aux_port(dev_priv); |
|
1037 | 1117 | ||
1038 | switch (port) { |
1118 | switch (port) { |
1039 | case PORT_A: |
- | |
1040 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
- | |
1041 | name = "DPDDC-A"; |
- | |
1042 | break; |
1119 | case PORT_A: |
1043 | case PORT_B: |
- | |
1044 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
- | |
1045 | name = "DPDDC-B"; |
- | |
1046 | break; |
1120 | case PORT_B: |
1047 | case PORT_C: |
- | |
1048 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
- | |
1049 | name = "DPDDC-C"; |
- | |
1050 | break; |
1121 | case PORT_C: |
1051 | case PORT_D: |
1122 | case PORT_D: |
1052 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
- | |
1053 | name = "DPDDC-D"; |
- | |
1054 | break; |
- | |
1055 | case PORT_E: |
- | |
1056 | intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg; |
- | |
1057 | name = "DPDDC-E"; |
- | |
1058 | break; |
1123 | return DP_AUX_CH_CTL(port); |
- | 1124 | default: |
|
- | 1125 | MISSING_CASE(port); |
|
1059 | default: |
1126 | return DP_AUX_CH_CTL(PORT_A); |
1060 | BUG(); |
1127 | } |
- | 1128 | } |
|
- | 1129 | ||
- | 1130 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
|
- | 1131 | enum port port, int index) |
|
- | 1132 | { |
|
- | 1133 | if (port == PORT_E) |
|
- | 1134 | port = skl_porte_aux_port(dev_priv); |
|
- | 1135 | ||
- | 1136 | switch (port) { |
|
- | 1137 | case PORT_A: |
|
- | 1138 | case PORT_B: |
|
- | 1139 | case PORT_C: |
|
- | 1140 | case PORT_D: |
|
- | 1141 | return DP_AUX_CH_DATA(port, index); |
|
- | 1142 | default: |
|
1061 | } |
1143 | MISSING_CASE(port); |
- | 1144 | return DP_AUX_CH_DATA(PORT_A, index); |
|
- | 1145 | } |
|
- | 1146 | } |
|
- | 1147 | ||
- | 1148 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
|
- | 1149 | enum port port) |
|
- | 1150 | { |
|
- | 1151 | if (INTEL_INFO(dev_priv)->gen >= 9) |
|
1062 | 1152 | return skl_aux_ctl_reg(dev_priv, port); |
|
1063 | /* |
1153 | else if (HAS_PCH_SPLIT(dev_priv)) |
1064 | * The AUX_CTL register is usually DP_CTL + 0x10. |
1154 | return ilk_aux_ctl_reg(dev_priv, port); |
- | 1155 | else |
|
- | 1156 | return g4x_aux_ctl_reg(dev_priv, port); |
|
1065 | * |
1157 | } |
- | 1158 | ||
- | 1159 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
|
- | 1160 | enum port port, int index) |
|
- | 1161 | { |
|
- | 1162 | if (INTEL_INFO(dev_priv)->gen >= 9) |
|
1066 | * On Haswell and Broadwell though: |
1163 | return skl_aux_data_reg(dev_priv, port, index); |
1067 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU |
1164 | else if (HAS_PCH_SPLIT(dev_priv)) |
- | 1165 | return ilk_aux_data_reg(dev_priv, port, index); |
|
- | 1166 | else |
|
- | 1167 | return g4x_aux_data_reg(dev_priv, port, index); |
|
1068 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU |
1168 | } |
- | 1169 | ||
- | 1170 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
|
- | 1171 | { |
|
1069 | * |
1172 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
- | 1173 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 1174 | int i; |
|
1070 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. |
1175 | |
1071 | */ |
1176 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
- | 1177 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
|
- | 1178 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
|
- | 1179 | } |
|
- | 1180 | ||
- | 1181 | static void |
|
- | 1182 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
|
- | 1183 | { |
|
- | 1184 | drm_dp_aux_unregister(&intel_dp->aux); |
|
- | 1185 | kfree(intel_dp->aux.name); |
|
- | 1186 | } |
|
- | 1187 | ||
- | 1188 | static int |
|
- | 1189 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
|
- | 1190 | { |
|
- | 1191 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1192 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 1193 | enum port port = intel_dig_port->port; |
|
- | 1194 | int ret; |
|
- | 1195 | ||
- | 1196 | intel_aux_reg_init(intel_dp); |
|
- | 1197 | ||
- | 1198 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
|
1072 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E) |
- | |
1073 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
1199 | if (!intel_dp->aux.name) |
1074 | 1200 | return -ENOMEM; |
|
1075 | intel_dp->aux.name = name; |
1201 | |
1076 | intel_dp->aux.dev = dev->dev; |
1202 | intel_dp->aux.dev = dev->dev; |
1077 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1203 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1078 | 1204 | ||
1079 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
1205 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
- | 1206 | intel_dp->aux.name, |
|
1080 | ""); |
1207 | connector->base.kdev->kobj.name); |
1081 | 1208 | ||
1082 | ret = drm_dp_aux_register(&intel_dp->aux); |
1209 | ret = drm_dp_aux_register(&intel_dp->aux); |
1083 | if (ret < 0) { |
1210 | if (ret < 0) { |
1084 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1211 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1085 | name, ret); |
1212 | intel_dp->aux.name, ret); |
- | 1213 | kfree(intel_dp->aux.name); |
|
1086 | return; |
1214 | return ret; |
1087 | } |
1215 | } |
1088 | 1216 | ||
1089 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1217 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1090 | &intel_dp->aux.ddc.dev.kobj, |
1218 | &intel_dp->aux.ddc.dev.kobj, |
1091 | intel_dp->aux.ddc.dev.kobj.name); |
1219 | intel_dp->aux.ddc.dev.kobj.name); |
1092 | if (ret < 0) { |
1220 | if (ret < 0) { |
1093 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); |
1221 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", |
- | 1222 | intel_dp->aux.name, ret); |
|
1094 | drm_dp_aux_unregister(&intel_dp->aux); |
1223 | intel_dp_aux_fini(intel_dp); |
- | 1224 | return ret; |
|
1095 | } |
1225 | } |
- | 1226 | ||
- | 1227 | return 0; |
|
1096 | } |
1228 | } |
1097 | 1229 | ||
1098 | static void |
1230 | static void |
1099 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1231 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1100 | { |
1232 | { |
1101 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1233 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1102 | 1234 | ||
1103 | if (!intel_connector->mst_port) |
1235 | if (!intel_connector->mst_port) |
1104 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
1236 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
1105 | intel_dp->aux.ddc.dev.kobj.name); |
1237 | intel_dp->aux.ddc.dev.kobj.name); |
1106 | intel_connector_unregister(intel_connector); |
1238 | intel_connector_unregister(intel_connector); |
1107 | } |
1239 | } |
1108 | 1240 | ||
1109 | static void |
1241 | static void |
1110 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1242 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1111 | { |
1243 | { |
1112 | u32 ctrl1; |
1244 | u32 ctrl1; |
1113 | 1245 | ||
1114 | memset(&pipe_config->dpll_hw_state, 0, |
1246 | memset(&pipe_config->dpll_hw_state, 0, |
1115 | sizeof(pipe_config->dpll_hw_state)); |
1247 | sizeof(pipe_config->dpll_hw_state)); |
1116 | 1248 | ||
1117 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1249 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1118 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1250 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1119 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1251 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1120 | 1252 | ||
1121 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1253 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1122 | switch (pipe_config->port_clock / 2) { |
1254 | switch (pipe_config->port_clock / 2) { |
1123 | case 81000: |
1255 | case 81000: |
1124 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1256 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1125 | SKL_DPLL0); |
1257 | SKL_DPLL0); |
1126 | break; |
1258 | break; |
1127 | case 135000: |
1259 | case 135000: |
1128 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1260 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1129 | SKL_DPLL0); |
1261 | SKL_DPLL0); |
1130 | break; |
1262 | break; |
1131 | case 270000: |
1263 | case 270000: |
1132 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1264 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1133 | SKL_DPLL0); |
1265 | SKL_DPLL0); |
1134 | break; |
1266 | break; |
1135 | case 162000: |
1267 | case 162000: |
1136 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1268 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1137 | SKL_DPLL0); |
1269 | SKL_DPLL0); |
1138 | break; |
1270 | break; |
1139 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1271 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1140 | results in CDCLK change. Need to handle the change of CDCLK by |
1272 | results in CDCLK change. Need to handle the change of CDCLK by |
1141 | disabling pipes and re-enabling them */ |
1273 | disabling pipes and re-enabling them */ |
1142 | case 108000: |
1274 | case 108000: |
1143 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1275 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1144 | SKL_DPLL0); |
1276 | SKL_DPLL0); |
1145 | break; |
1277 | break; |
1146 | case 216000: |
1278 | case 216000: |
1147 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1279 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1148 | SKL_DPLL0); |
1280 | SKL_DPLL0); |
1149 | break; |
1281 | break; |
1150 | 1282 | ||
1151 | } |
1283 | } |
1152 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1284 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1153 | } |
1285 | } |
1154 | 1286 | ||
1155 | void |
1287 | void |
1156 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1288 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1157 | { |
1289 | { |
1158 | memset(&pipe_config->dpll_hw_state, 0, |
1290 | memset(&pipe_config->dpll_hw_state, 0, |
1159 | sizeof(pipe_config->dpll_hw_state)); |
1291 | sizeof(pipe_config->dpll_hw_state)); |
1160 | 1292 | ||
1161 | switch (pipe_config->port_clock / 2) { |
1293 | switch (pipe_config->port_clock / 2) { |
1162 | case 81000: |
1294 | case 81000: |
1163 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1295 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1164 | break; |
1296 | break; |
1165 | case 135000: |
1297 | case 135000: |
1166 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1298 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1167 | break; |
1299 | break; |
1168 | case 270000: |
1300 | case 270000: |
1169 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1301 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1170 | break; |
1302 | break; |
1171 | } |
1303 | } |
1172 | } |
1304 | } |
1173 | 1305 | ||
1174 | static int |
1306 | static int |
1175 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1307 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1176 | { |
1308 | { |
1177 | if (intel_dp->num_sink_rates) { |
1309 | if (intel_dp->num_sink_rates) { |
1178 | *sink_rates = intel_dp->sink_rates; |
1310 | *sink_rates = intel_dp->sink_rates; |
1179 | return intel_dp->num_sink_rates; |
1311 | return intel_dp->num_sink_rates; |
1180 | } |
1312 | } |
1181 | 1313 | ||
1182 | *sink_rates = default_rates; |
1314 | *sink_rates = default_rates; |
1183 | 1315 | ||
1184 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1316 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1185 | } |
1317 | } |
1186 | 1318 | ||
1187 | static bool intel_dp_source_supports_hbr2(struct drm_device *dev) |
1319 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
- | 1320 | { |
|
- | 1321 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
- | 1322 | struct drm_device *dev = dig_port->base.base.dev; |
|
1188 | { |
1323 | |
1189 | /* WaDisableHBR2:skl */ |
1324 | /* WaDisableHBR2:skl */ |
1190 | if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) |
1325 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
1191 | return false; |
1326 | return false; |
1192 | 1327 | ||
1193 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1328 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1194 | (INTEL_INFO(dev)->gen >= 9)) |
1329 | (INTEL_INFO(dev)->gen >= 9)) |
1195 | return true; |
1330 | return true; |
1196 | else |
1331 | else |
1197 | return false; |
1332 | return false; |
1198 | } |
1333 | } |
1199 | 1334 | ||
1200 | static int |
1335 | static int |
1201 | intel_dp_source_rates(struct drm_device *dev, const int **source_rates) |
1336 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
1202 | { |
1337 | { |
- | 1338 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
- | 1339 | struct drm_device *dev = dig_port->base.base.dev; |
|
1203 | int size; |
1340 | int size; |
1204 | 1341 | ||
1205 | if (IS_BROXTON(dev)) { |
1342 | if (IS_BROXTON(dev)) { |
1206 | *source_rates = bxt_rates; |
1343 | *source_rates = bxt_rates; |
1207 | size = ARRAY_SIZE(bxt_rates); |
1344 | size = ARRAY_SIZE(bxt_rates); |
1208 | } else if (IS_SKYLAKE(dev)) { |
1345 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
1209 | *source_rates = skl_rates; |
1346 | *source_rates = skl_rates; |
1210 | size = ARRAY_SIZE(skl_rates); |
1347 | size = ARRAY_SIZE(skl_rates); |
1211 | } else { |
1348 | } else { |
1212 | *source_rates = default_rates; |
1349 | *source_rates = default_rates; |
1213 | size = ARRAY_SIZE(default_rates); |
1350 | size = ARRAY_SIZE(default_rates); |
1214 | } |
1351 | } |
1215 | 1352 | ||
1216 | /* This depends on the fact that 5.4 is last value in the array */ |
1353 | /* This depends on the fact that 5.4 is last value in the array */ |
1217 | if (!intel_dp_source_supports_hbr2(dev)) |
1354 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
1218 | size--; |
1355 | size--; |
1219 | 1356 | ||
1220 | return size; |
1357 | return size; |
1221 | } |
1358 | } |
1222 | 1359 | ||
1223 | static void |
1360 | static void |
1224 | intel_dp_set_clock(struct intel_encoder *encoder, |
1361 | intel_dp_set_clock(struct intel_encoder *encoder, |
1225 | struct intel_crtc_state *pipe_config) |
1362 | struct intel_crtc_state *pipe_config) |
1226 | { |
1363 | { |
1227 | struct drm_device *dev = encoder->base.dev; |
1364 | struct drm_device *dev = encoder->base.dev; |
1228 | const struct dp_link_dpll *divisor = NULL; |
1365 | const struct dp_link_dpll *divisor = NULL; |
1229 | int i, count = 0; |
1366 | int i, count = 0; |
1230 | 1367 | ||
1231 | if (IS_G4X(dev)) { |
1368 | if (IS_G4X(dev)) { |
1232 | divisor = gen4_dpll; |
1369 | divisor = gen4_dpll; |
1233 | count = ARRAY_SIZE(gen4_dpll); |
1370 | count = ARRAY_SIZE(gen4_dpll); |
1234 | } else if (HAS_PCH_SPLIT(dev)) { |
1371 | } else if (HAS_PCH_SPLIT(dev)) { |
1235 | divisor = pch_dpll; |
1372 | divisor = pch_dpll; |
1236 | count = ARRAY_SIZE(pch_dpll); |
1373 | count = ARRAY_SIZE(pch_dpll); |
1237 | } else if (IS_CHERRYVIEW(dev)) { |
1374 | } else if (IS_CHERRYVIEW(dev)) { |
1238 | divisor = chv_dpll; |
1375 | divisor = chv_dpll; |
1239 | count = ARRAY_SIZE(chv_dpll); |
1376 | count = ARRAY_SIZE(chv_dpll); |
1240 | } else if (IS_VALLEYVIEW(dev)) { |
1377 | } else if (IS_VALLEYVIEW(dev)) { |
1241 | divisor = vlv_dpll; |
1378 | divisor = vlv_dpll; |
1242 | count = ARRAY_SIZE(vlv_dpll); |
1379 | count = ARRAY_SIZE(vlv_dpll); |
1243 | } |
1380 | } |
1244 | 1381 | ||
1245 | if (divisor && count) { |
1382 | if (divisor && count) { |
1246 | for (i = 0; i < count; i++) { |
1383 | for (i = 0; i < count; i++) { |
1247 | if (pipe_config->port_clock == divisor[i].clock) { |
1384 | if (pipe_config->port_clock == divisor[i].clock) { |
1248 | pipe_config->dpll = divisor[i].dpll; |
1385 | pipe_config->dpll = divisor[i].dpll; |
1249 | pipe_config->clock_set = true; |
1386 | pipe_config->clock_set = true; |
1250 | break; |
1387 | break; |
1251 | } |
1388 | } |
1252 | } |
1389 | } |
1253 | } |
1390 | } |
1254 | } |
1391 | } |
1255 | 1392 | ||
1256 | static int intersect_rates(const int *source_rates, int source_len, |
1393 | static int intersect_rates(const int *source_rates, int source_len, |
1257 | const int *sink_rates, int sink_len, |
1394 | const int *sink_rates, int sink_len, |
1258 | int *common_rates) |
1395 | int *common_rates) |
1259 | { |
1396 | { |
1260 | int i = 0, j = 0, k = 0; |
1397 | int i = 0, j = 0, k = 0; |
1261 | 1398 | ||
1262 | while (i < source_len && j < sink_len) { |
1399 | while (i < source_len && j < sink_len) { |
1263 | if (source_rates[i] == sink_rates[j]) { |
1400 | if (source_rates[i] == sink_rates[j]) { |
1264 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1401 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1265 | return k; |
1402 | return k; |
1266 | common_rates[k] = source_rates[i]; |
1403 | common_rates[k] = source_rates[i]; |
1267 | ++k; |
1404 | ++k; |
1268 | ++i; |
1405 | ++i; |
1269 | ++j; |
1406 | ++j; |
1270 | } else if (source_rates[i] < sink_rates[j]) { |
1407 | } else if (source_rates[i] < sink_rates[j]) { |
1271 | ++i; |
1408 | ++i; |
1272 | } else { |
1409 | } else { |
1273 | ++j; |
1410 | ++j; |
1274 | } |
1411 | } |
1275 | } |
1412 | } |
1276 | return k; |
1413 | return k; |
1277 | } |
1414 | } |
1278 | 1415 | ||
1279 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1416 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1280 | int *common_rates) |
1417 | int *common_rates) |
1281 | { |
1418 | { |
1282 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1283 | const int *source_rates, *sink_rates; |
1419 | const int *source_rates, *sink_rates; |
1284 | int source_len, sink_len; |
1420 | int source_len, sink_len; |
1285 | 1421 | ||
1286 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1422 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1287 | source_len = intel_dp_source_rates(dev, &source_rates); |
1423 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1288 | 1424 | ||
1289 | return intersect_rates(source_rates, source_len, |
1425 | return intersect_rates(source_rates, source_len, |
1290 | sink_rates, sink_len, |
1426 | sink_rates, sink_len, |
1291 | common_rates); |
1427 | common_rates); |
1292 | } |
1428 | } |
1293 | 1429 | ||
1294 | static void snprintf_int_array(char *str, size_t len, |
1430 | static void snprintf_int_array(char *str, size_t len, |
1295 | const int *array, int nelem) |
1431 | const int *array, int nelem) |
1296 | { |
1432 | { |
1297 | int i; |
1433 | int i; |
1298 | 1434 | ||
1299 | str[0] = '\0'; |
1435 | str[0] = '\0'; |
1300 | 1436 | ||
1301 | for (i = 0; i < nelem; i++) { |
1437 | for (i = 0; i < nelem; i++) { |
1302 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1438 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1303 | if (r >= len) |
1439 | if (r >= len) |
1304 | return; |
1440 | return; |
1305 | str += r; |
1441 | str += r; |
1306 | len -= r; |
1442 | len -= r; |
1307 | } |
1443 | } |
1308 | } |
1444 | } |
1309 | 1445 | ||
1310 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1446 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1311 | { |
1447 | { |
1312 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1313 | const int *source_rates, *sink_rates; |
1448 | const int *source_rates, *sink_rates; |
1314 | int source_len, sink_len, common_len; |
1449 | int source_len, sink_len, common_len; |
1315 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1450 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1316 | char str[128]; /* FIXME: too big for stack? */ |
1451 | char str[128]; /* FIXME: too big for stack? */ |
1317 | 1452 | ||
1318 | if ((drm_debug & DRM_UT_KMS) == 0) |
1453 | if ((drm_debug & DRM_UT_KMS) == 0) |
1319 | return; |
1454 | return; |
1320 | 1455 | ||
1321 | source_len = intel_dp_source_rates(dev, &source_rates); |
1456 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1322 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1457 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1323 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1458 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1324 | 1459 | ||
1325 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1460 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1326 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1461 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1327 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1462 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1328 | 1463 | ||
1329 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1464 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1330 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1465 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1331 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1466 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1332 | } |
1467 | } |
1333 | 1468 | ||
1334 | static int rate_to_index(int find, const int *rates) |
1469 | static int rate_to_index(int find, const int *rates) |
1335 | { |
1470 | { |
1336 | int i = 0; |
1471 | int i = 0; |
1337 | 1472 | ||
1338 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1473 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1339 | if (find == rates[i]) |
1474 | if (find == rates[i]) |
1340 | break; |
1475 | break; |
1341 | 1476 | ||
1342 | return i; |
1477 | return i; |
1343 | } |
1478 | } |
1344 | 1479 | ||
1345 | int |
1480 | int |
1346 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1481 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1347 | { |
1482 | { |
1348 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1483 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1349 | int len; |
1484 | int len; |
1350 | 1485 | ||
1351 | len = intel_dp_common_rates(intel_dp, rates); |
1486 | len = intel_dp_common_rates(intel_dp, rates); |
1352 | if (WARN_ON(len <= 0)) |
1487 | if (WARN_ON(len <= 0)) |
1353 | return 162000; |
1488 | return 162000; |
1354 | 1489 | ||
1355 | return rates[rate_to_index(0, rates) - 1]; |
1490 | return rates[rate_to_index(0, rates) - 1]; |
1356 | } |
1491 | } |
1357 | 1492 | ||
1358 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1493 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1359 | { |
1494 | { |
1360 | return rate_to_index(rate, intel_dp->sink_rates); |
1495 | return rate_to_index(rate, intel_dp->sink_rates); |
1361 | } |
1496 | } |
1362 | 1497 | ||
1363 | static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1498 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1364 | uint8_t *link_bw, uint8_t *rate_select) |
1499 | uint8_t *link_bw, uint8_t *rate_select) |
1365 | { |
1500 | { |
1366 | if (intel_dp->num_sink_rates) { |
1501 | if (intel_dp->num_sink_rates) { |
1367 | *link_bw = 0; |
1502 | *link_bw = 0; |
1368 | *rate_select = |
1503 | *rate_select = |
1369 | intel_dp_rate_select(intel_dp, port_clock); |
1504 | intel_dp_rate_select(intel_dp, port_clock); |
1370 | } else { |
1505 | } else { |
1371 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1506 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1372 | *rate_select = 0; |
1507 | *rate_select = 0; |
1373 | } |
1508 | } |
1374 | } |
1509 | } |
1375 | 1510 | ||
1376 | bool |
1511 | bool |
1377 | intel_dp_compute_config(struct intel_encoder *encoder, |
1512 | intel_dp_compute_config(struct intel_encoder *encoder, |
1378 | struct intel_crtc_state *pipe_config) |
1513 | struct intel_crtc_state *pipe_config) |
1379 | { |
1514 | { |
1380 | struct drm_device *dev = encoder->base.dev; |
1515 | struct drm_device *dev = encoder->base.dev; |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
1516 | struct drm_i915_private *dev_priv = dev->dev_private; |
1382 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1517 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1518 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1384 | enum port port = dp_to_dig_port(intel_dp)->port; |
1519 | enum port port = dp_to_dig_port(intel_dp)->port; |
1385 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1520 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1386 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1521 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1387 | int lane_count, clock; |
1522 | int lane_count, clock; |
1388 | int min_lane_count = 1; |
1523 | int min_lane_count = 1; |
1389 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1524 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1390 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1525 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1391 | int min_clock = 0; |
1526 | int min_clock = 0; |
1392 | int max_clock; |
1527 | int max_clock; |
1393 | int bpp, mode_rate; |
1528 | int bpp, mode_rate; |
1394 | int link_avail, link_clock; |
1529 | int link_avail, link_clock; |
1395 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1530 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1396 | int common_len; |
1531 | int common_len; |
1397 | uint8_t link_bw, rate_select; |
1532 | uint8_t link_bw, rate_select; |
1398 | 1533 | ||
1399 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1534 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1400 | 1535 | ||
1401 | /* No common link rates between source and sink */ |
1536 | /* No common link rates between source and sink */ |
1402 | WARN_ON(common_len <= 0); |
1537 | WARN_ON(common_len <= 0); |
1403 | 1538 | ||
1404 | max_clock = common_len - 1; |
1539 | max_clock = common_len - 1; |
1405 | 1540 | ||
1406 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1541 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1407 | pipe_config->has_pch_encoder = true; |
1542 | pipe_config->has_pch_encoder = true; |
1408 | 1543 | ||
1409 | pipe_config->has_dp_encoder = true; |
1544 | pipe_config->has_dp_encoder = true; |
1410 | pipe_config->has_drrs = false; |
1545 | pipe_config->has_drrs = false; |
1411 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1546 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1412 | 1547 | ||
1413 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1548 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1414 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1549 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1415 | adjusted_mode); |
1550 | adjusted_mode); |
1416 | 1551 | ||
1417 | if (INTEL_INFO(dev)->gen >= 9) { |
1552 | if (INTEL_INFO(dev)->gen >= 9) { |
1418 | int ret; |
1553 | int ret; |
1419 | ret = skl_update_scaler_crtc(pipe_config); |
1554 | ret = skl_update_scaler_crtc(pipe_config); |
1420 | if (ret) |
1555 | if (ret) |
1421 | return ret; |
1556 | return ret; |
1422 | } |
1557 | } |
1423 | 1558 | ||
1424 | if (!HAS_PCH_SPLIT(dev)) |
1559 | if (HAS_GMCH_DISPLAY(dev)) |
1425 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1560 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1426 | intel_connector->panel.fitting_mode); |
1561 | intel_connector->panel.fitting_mode); |
1427 | else |
1562 | else |
1428 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1563 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1429 | intel_connector->panel.fitting_mode); |
1564 | intel_connector->panel.fitting_mode); |
1430 | } |
1565 | } |
1431 | 1566 | ||
1432 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1567 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1433 | return false; |
1568 | return false; |
1434 | 1569 | ||
1435 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1570 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1436 | "max bw %d pixel clock %iKHz\n", |
1571 | "max bw %d pixel clock %iKHz\n", |
1437 | max_lane_count, common_rates[max_clock], |
1572 | max_lane_count, common_rates[max_clock], |
1438 | adjusted_mode->crtc_clock); |
1573 | adjusted_mode->crtc_clock); |
1439 | 1574 | ||
1440 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1575 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1441 | * bpc in between. */ |
1576 | * bpc in between. */ |
1442 | bpp = pipe_config->pipe_bpp; |
1577 | bpp = pipe_config->pipe_bpp; |
1443 | if (is_edp(intel_dp)) { |
1578 | if (is_edp(intel_dp)) { |
1444 | 1579 | ||
1445 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1580 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1446 | if (intel_connector->base.display_info.bpc == 0 && |
1581 | if (intel_connector->base.display_info.bpc == 0 && |
1447 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1582 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1448 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1583 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1449 | dev_priv->vbt.edp_bpp); |
1584 | dev_priv->vbt.edp_bpp); |
1450 | bpp = dev_priv->vbt.edp_bpp; |
1585 | bpp = dev_priv->vbt.edp_bpp; |
1451 | } |
1586 | } |
1452 | 1587 | ||
1453 | /* |
1588 | /* |
1454 | * Use the maximum clock and number of lanes the eDP panel |
1589 | * Use the maximum clock and number of lanes the eDP panel |
1455 | * advertizes being capable of. The panels are generally |
1590 | * advertizes being capable of. The panels are generally |
1456 | * designed to support only a single clock and lane |
1591 | * designed to support only a single clock and lane |
1457 | * configuration, and typically these values correspond to the |
1592 | * configuration, and typically these values correspond to the |
1458 | * native resolution of the panel. |
1593 | * native resolution of the panel. |
1459 | */ |
1594 | */ |
1460 | min_lane_count = max_lane_count; |
1595 | min_lane_count = max_lane_count; |
1461 | min_clock = max_clock; |
1596 | min_clock = max_clock; |
1462 | } |
1597 | } |
1463 | 1598 | ||
1464 | for (; bpp >= 6*3; bpp -= 2*3) { |
1599 | for (; bpp >= 6*3; bpp -= 2*3) { |
1465 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1600 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1466 | bpp); |
1601 | bpp); |
1467 | 1602 | ||
1468 | for (clock = min_clock; clock <= max_clock; clock++) { |
1603 | for (clock = min_clock; clock <= max_clock; clock++) { |
1469 | for (lane_count = min_lane_count; |
1604 | for (lane_count = min_lane_count; |
1470 | lane_count <= max_lane_count; |
1605 | lane_count <= max_lane_count; |
1471 | lane_count <<= 1) { |
1606 | lane_count <<= 1) { |
1472 | 1607 | ||
1473 | link_clock = common_rates[clock]; |
1608 | link_clock = common_rates[clock]; |
1474 | link_avail = intel_dp_max_data_rate(link_clock, |
1609 | link_avail = intel_dp_max_data_rate(link_clock, |
1475 | lane_count); |
1610 | lane_count); |
1476 | 1611 | ||
1477 | if (mode_rate <= link_avail) { |
1612 | if (mode_rate <= link_avail) { |
1478 | goto found; |
1613 | goto found; |
1479 | } |
1614 | } |
1480 | } |
1615 | } |
1481 | } |
1616 | } |
1482 | } |
1617 | } |
1483 | 1618 | ||
1484 | return false; |
1619 | return false; |
1485 | 1620 | ||
1486 | found: |
1621 | found: |
1487 | if (intel_dp->color_range_auto) { |
1622 | if (intel_dp->color_range_auto) { |
1488 | /* |
1623 | /* |
1489 | * See: |
1624 | * See: |
1490 | * CEA-861-E - 5.1 Default Encoding Parameters |
1625 | * CEA-861-E - 5.1 Default Encoding Parameters |
1491 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1626 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1492 | */ |
1627 | */ |
1493 | pipe_config->limited_color_range = |
1628 | pipe_config->limited_color_range = |
1494 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1629 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1495 | } else { |
1630 | } else { |
1496 | pipe_config->limited_color_range = |
1631 | pipe_config->limited_color_range = |
1497 | intel_dp->limited_color_range; |
1632 | intel_dp->limited_color_range; |
1498 | } |
1633 | } |
1499 | 1634 | ||
1500 | pipe_config->lane_count = lane_count; |
1635 | pipe_config->lane_count = lane_count; |
1501 | 1636 | ||
1502 | pipe_config->pipe_bpp = bpp; |
1637 | pipe_config->pipe_bpp = bpp; |
1503 | pipe_config->port_clock = common_rates[clock]; |
1638 | pipe_config->port_clock = common_rates[clock]; |
1504 | 1639 | ||
1505 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1640 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1506 | &link_bw, &rate_select); |
1641 | &link_bw, &rate_select); |
1507 | 1642 | ||
1508 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1643 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1509 | link_bw, rate_select, pipe_config->lane_count, |
1644 | link_bw, rate_select, pipe_config->lane_count, |
1510 | pipe_config->port_clock, bpp); |
1645 | pipe_config->port_clock, bpp); |
1511 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1646 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1512 | mode_rate, link_avail); |
1647 | mode_rate, link_avail); |
1513 | 1648 | ||
1514 | intel_link_compute_m_n(bpp, lane_count, |
1649 | intel_link_compute_m_n(bpp, lane_count, |
1515 | adjusted_mode->crtc_clock, |
1650 | adjusted_mode->crtc_clock, |
1516 | pipe_config->port_clock, |
1651 | pipe_config->port_clock, |
1517 | &pipe_config->dp_m_n); |
1652 | &pipe_config->dp_m_n); |
1518 | 1653 | ||
1519 | if (intel_connector->panel.downclock_mode != NULL && |
1654 | if (intel_connector->panel.downclock_mode != NULL && |
1520 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1655 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1521 | pipe_config->has_drrs = true; |
1656 | pipe_config->has_drrs = true; |
1522 | intel_link_compute_m_n(bpp, lane_count, |
1657 | intel_link_compute_m_n(bpp, lane_count, |
1523 | intel_connector->panel.downclock_mode->clock, |
1658 | intel_connector->panel.downclock_mode->clock, |
1524 | pipe_config->port_clock, |
1659 | pipe_config->port_clock, |
1525 | &pipe_config->dp_m2_n2); |
1660 | &pipe_config->dp_m2_n2); |
1526 | } |
1661 | } |
1527 | 1662 | ||
1528 | if (IS_SKYLAKE(dev) && is_edp(intel_dp)) |
1663 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) |
1529 | skl_edp_set_pll_config(pipe_config); |
1664 | skl_edp_set_pll_config(pipe_config); |
1530 | else if (IS_BROXTON(dev)) |
1665 | else if (IS_BROXTON(dev)) |
1531 | /* handled in ddi */; |
1666 | /* handled in ddi */; |
1532 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1667 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1533 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1668 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1534 | else |
1669 | else |
1535 | intel_dp_set_clock(encoder, pipe_config); |
1670 | intel_dp_set_clock(encoder, pipe_config); |
1536 | 1671 | ||
1537 | return true; |
1672 | return true; |
1538 | } |
1673 | } |
1539 | - | ||
1540 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
- | |
1541 | { |
- | |
1542 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
1543 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
- | |
1544 | struct drm_device *dev = crtc->base.dev; |
- | |
1545 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1546 | u32 dpa_ctl; |
- | |
1547 | - | ||
1548 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", |
- | |
1549 | crtc->config->port_clock); |
- | |
1550 | dpa_ctl = I915_READ(DP_A); |
- | |
1551 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
- | |
1552 | - | ||
1553 | if (crtc->config->port_clock == 162000) { |
- | |
1554 | /* For a long time we've carried around a ILK-DevA w/a for the |
- | |
1555 | * 160MHz clock. If we're really unlucky, it's still required. |
- | |
1556 | */ |
- | |
1557 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
- | |
1558 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
- | |
1559 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
- | |
1560 | } else { |
- | |
1561 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
- | |
1562 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
- | |
1563 | } |
- | |
1564 | - | ||
1565 | I915_WRITE(DP_A, dpa_ctl); |
- | |
1566 | - | ||
1567 | POSTING_READ(DP_A); |
- | |
1568 | udelay(500); |
- | |
1569 | } |
- | |
1570 | 1674 | ||
1571 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1675 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1572 | const struct intel_crtc_state *pipe_config) |
1676 | const struct intel_crtc_state *pipe_config) |
1573 | { |
1677 | { |
1574 | intel_dp->link_rate = pipe_config->port_clock; |
1678 | intel_dp->link_rate = pipe_config->port_clock; |
1575 | intel_dp->lane_count = pipe_config->lane_count; |
1679 | intel_dp->lane_count = pipe_config->lane_count; |
1576 | } |
1680 | } |
1577 | 1681 | ||
1578 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1682 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1579 | { |
1683 | { |
1580 | struct drm_device *dev = encoder->base.dev; |
1684 | struct drm_device *dev = encoder->base.dev; |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; |
1685 | struct drm_i915_private *dev_priv = dev->dev_private; |
1582 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1686 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1583 | enum port port = dp_to_dig_port(intel_dp)->port; |
1687 | enum port port = dp_to_dig_port(intel_dp)->port; |
1584 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1688 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1585 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1689 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1586 | 1690 | ||
1587 | intel_dp_set_link_params(intel_dp, crtc->config); |
1691 | intel_dp_set_link_params(intel_dp, crtc->config); |
1588 | 1692 | ||
1589 | /* |
1693 | /* |
1590 | * There are four kinds of DP registers: |
1694 | * There are four kinds of DP registers: |
1591 | * |
1695 | * |
1592 | * IBX PCH |
1696 | * IBX PCH |
1593 | * SNB CPU |
1697 | * SNB CPU |
1594 | * IVB CPU |
1698 | * IVB CPU |
1595 | * CPT PCH |
1699 | * CPT PCH |
1596 | * |
1700 | * |
1597 | * IBX PCH and CPU are the same for almost everything, |
1701 | * IBX PCH and CPU are the same for almost everything, |
1598 | * except that the CPU DP PLL is configured in this |
1702 | * except that the CPU DP PLL is configured in this |
1599 | * register |
1703 | * register |
1600 | * |
1704 | * |
1601 | * CPT PCH is quite different, having many bits moved |
1705 | * CPT PCH is quite different, having many bits moved |
1602 | * to the TRANS_DP_CTL register instead. That |
1706 | * to the TRANS_DP_CTL register instead. That |
1603 | * configuration happens (oddly) in ironlake_pch_enable |
1707 | * configuration happens (oddly) in ironlake_pch_enable |
1604 | */ |
1708 | */ |
1605 | 1709 | ||
1606 | /* Preserve the BIOS-computed detected bit. This is |
1710 | /* Preserve the BIOS-computed detected bit. This is |
1607 | * supposed to be read-only. |
1711 | * supposed to be read-only. |
1608 | */ |
1712 | */ |
1609 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1713 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1610 | 1714 | ||
1611 | /* Handle DP bits in common between all three register formats */ |
1715 | /* Handle DP bits in common between all three register formats */ |
1612 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1716 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1613 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1717 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1614 | - | ||
1615 | if (crtc->config->has_audio) |
- | |
1616 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
- | |
1617 | 1718 | ||
1618 | /* Split out the IBX/CPU vs CPT settings */ |
1719 | /* Split out the IBX/CPU vs CPT settings */ |
1619 | 1720 | ||
1620 | if (IS_GEN7(dev) && port == PORT_A) { |
1721 | if (IS_GEN7(dev) && port == PORT_A) { |
1621 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1722 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1622 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1723 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1623 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1724 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1624 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1725 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1625 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1726 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1626 | 1727 | ||
1627 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1728 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1628 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1729 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1629 | 1730 | ||
1630 | intel_dp->DP |= crtc->pipe << 29; |
1731 | intel_dp->DP |= crtc->pipe << 29; |
1631 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1732 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1632 | u32 trans_dp; |
1733 | u32 trans_dp; |
1633 | 1734 | ||
1634 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1735 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1635 | 1736 | ||
1636 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1737 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1637 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1738 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1638 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1739 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1639 | else |
1740 | else |
1640 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1741 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1641 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1742 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1642 | } else { |
1743 | } else { |
1643 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1744 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1644 | crtc->config->limited_color_range) |
1745 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
1645 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1746 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1646 | 1747 | ||
1647 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1748 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1648 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1749 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1649 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1750 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1650 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1751 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1651 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1752 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1652 | 1753 | ||
1653 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1754 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1654 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1755 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1655 | 1756 | ||
1656 | if (IS_CHERRYVIEW(dev)) |
1757 | if (IS_CHERRYVIEW(dev)) |
1657 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1758 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1658 | else if (crtc->pipe == PIPE_B) |
1759 | else if (crtc->pipe == PIPE_B) |
1659 | intel_dp->DP |= DP_PIPEB_SELECT; |
1760 | intel_dp->DP |= DP_PIPEB_SELECT; |
1660 | } |
1761 | } |
1661 | } |
1762 | } |
1662 | 1763 | ||
1663 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1764 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1664 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1765 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1665 | 1766 | ||
1666 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1767 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1667 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1768 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1668 | 1769 | ||
1669 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1770 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1670 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1771 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1671 | 1772 | ||
1672 | static void wait_panel_status(struct intel_dp *intel_dp, |
1773 | static void wait_panel_status(struct intel_dp *intel_dp, |
1673 | u32 mask, |
1774 | u32 mask, |
1674 | u32 value) |
1775 | u32 value) |
1675 | { |
1776 | { |
1676 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1777 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; |
1678 | u32 pp_stat_reg, pp_ctrl_reg; |
1779 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1679 | 1780 | ||
1680 | lockdep_assert_held(&dev_priv->pps_mutex); |
1781 | lockdep_assert_held(&dev_priv->pps_mutex); |
1681 | 1782 | ||
1682 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1783 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1683 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1784 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1684 | 1785 | ||
1685 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1786 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1686 | mask, value, |
1787 | mask, value, |
1687 | I915_READ(pp_stat_reg), |
1788 | I915_READ(pp_stat_reg), |
1688 | I915_READ(pp_ctrl_reg)); |
1789 | I915_READ(pp_ctrl_reg)); |
1689 | 1790 | ||
1690 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1791 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1691 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1792 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1692 | I915_READ(pp_stat_reg), |
1793 | I915_READ(pp_stat_reg), |
1693 | I915_READ(pp_ctrl_reg)); |
1794 | I915_READ(pp_ctrl_reg)); |
1694 | } |
1795 | } |
1695 | 1796 | ||
1696 | DRM_DEBUG_KMS("Wait complete\n"); |
1797 | DRM_DEBUG_KMS("Wait complete\n"); |
1697 | } |
1798 | } |
1698 | 1799 | ||
1699 | static void wait_panel_on(struct intel_dp *intel_dp) |
1800 | static void wait_panel_on(struct intel_dp *intel_dp) |
1700 | { |
1801 | { |
1701 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1802 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1702 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1803 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1703 | } |
1804 | } |
1704 | 1805 | ||
1705 | static void wait_panel_off(struct intel_dp *intel_dp) |
1806 | static void wait_panel_off(struct intel_dp *intel_dp) |
1706 | { |
1807 | { |
1707 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1808 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1708 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1809 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1709 | } |
1810 | } |
1710 | 1811 | ||
1711 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1812 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1712 | { |
1813 | { |
1713 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1814 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1714 | 1815 | ||
1715 | /* When we disable the VDD override bit last we have to do the manual |
1816 | /* When we disable the VDD override bit last we have to do the manual |
1716 | * wait. */ |
1817 | * wait. */ |
1717 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1818 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1718 | intel_dp->panel_power_cycle_delay); |
1819 | intel_dp->panel_power_cycle_delay); |
1719 | 1820 | ||
1720 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1821 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1721 | } |
1822 | } |
1722 | 1823 | ||
1723 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1824 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1724 | { |
1825 | { |
1725 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1826 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1726 | intel_dp->backlight_on_delay); |
1827 | intel_dp->backlight_on_delay); |
1727 | } |
1828 | } |
1728 | 1829 | ||
1729 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1830 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1730 | { |
1831 | { |
1731 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1832 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1732 | intel_dp->backlight_off_delay); |
1833 | intel_dp->backlight_off_delay); |
1733 | } |
1834 | } |
1734 | 1835 | ||
1735 | /* Read the current pp_control value, unlocking the register if it |
1836 | /* Read the current pp_control value, unlocking the register if it |
1736 | * is locked |
1837 | * is locked |
1737 | */ |
1838 | */ |
1738 | 1839 | ||
1739 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1840 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1740 | { |
1841 | { |
1741 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1842 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
1743 | u32 control; |
1844 | u32 control; |
1744 | 1845 | ||
1745 | lockdep_assert_held(&dev_priv->pps_mutex); |
1846 | lockdep_assert_held(&dev_priv->pps_mutex); |
1746 | 1847 | ||
1747 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1848 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1748 | if (!IS_BROXTON(dev)) { |
1849 | if (!IS_BROXTON(dev)) { |
1749 | control &= ~PANEL_UNLOCK_MASK; |
1850 | control &= ~PANEL_UNLOCK_MASK; |
1750 | control |= PANEL_UNLOCK_REGS; |
1851 | control |= PANEL_UNLOCK_REGS; |
1751 | } |
1852 | } |
1752 | return control; |
1853 | return control; |
1753 | } |
1854 | } |
1754 | 1855 | ||
1755 | /* |
1856 | /* |
1756 | * Must be paired with edp_panel_vdd_off(). |
1857 | * Must be paired with edp_panel_vdd_off(). |
1757 | * Must hold pps_mutex around the whole on/off sequence. |
1858 | * Must hold pps_mutex around the whole on/off sequence. |
1758 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1859 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1759 | */ |
1860 | */ |
1760 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1861 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1761 | { |
1862 | { |
1762 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1863 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1763 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1864 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1764 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1865 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; |
1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
1766 | enum intel_display_power_domain power_domain; |
1867 | enum intel_display_power_domain power_domain; |
1767 | u32 pp; |
1868 | u32 pp; |
1768 | u32 pp_stat_reg, pp_ctrl_reg; |
1869 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1769 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1870 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1770 | 1871 | ||
1771 | lockdep_assert_held(&dev_priv->pps_mutex); |
1872 | lockdep_assert_held(&dev_priv->pps_mutex); |
1772 | 1873 | ||
1773 | if (!is_edp(intel_dp)) |
1874 | if (!is_edp(intel_dp)) |
1774 | return false; |
1875 | return false; |
1775 | 1876 | ||
1776 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
1877 | // cancel_delayed_work(&intel_dp->panel_vdd_work); |
1777 | intel_dp->want_panel_vdd = true; |
1878 | intel_dp->want_panel_vdd = true; |
1778 | 1879 | ||
1779 | if (edp_have_panel_vdd(intel_dp)) |
1880 | if (edp_have_panel_vdd(intel_dp)) |
1780 | return need_to_disable; |
1881 | return need_to_disable; |
1781 | 1882 | ||
1782 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1883 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1783 | intel_display_power_get(dev_priv, power_domain); |
1884 | intel_display_power_get(dev_priv, power_domain); |
1784 | 1885 | ||
1785 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1886 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1786 | port_name(intel_dig_port->port)); |
1887 | port_name(intel_dig_port->port)); |
1787 | 1888 | ||
1788 | if (!edp_have_panel_power(intel_dp)) |
1889 | if (!edp_have_panel_power(intel_dp)) |
1789 | wait_panel_power_cycle(intel_dp); |
1890 | wait_panel_power_cycle(intel_dp); |
1790 | 1891 | ||
1791 | pp = ironlake_get_pp_control(intel_dp); |
1892 | pp = ironlake_get_pp_control(intel_dp); |
1792 | pp |= EDP_FORCE_VDD; |
1893 | pp |= EDP_FORCE_VDD; |
1793 | 1894 | ||
1794 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1895 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1795 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1896 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1796 | 1897 | ||
1797 | I915_WRITE(pp_ctrl_reg, pp); |
1898 | I915_WRITE(pp_ctrl_reg, pp); |
1798 | POSTING_READ(pp_ctrl_reg); |
1899 | POSTING_READ(pp_ctrl_reg); |
1799 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1900 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1800 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1901 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1801 | /* |
1902 | /* |
1802 | * If the panel wasn't on, delay before accessing aux channel |
1903 | * If the panel wasn't on, delay before accessing aux channel |
1803 | */ |
1904 | */ |
1804 | if (!edp_have_panel_power(intel_dp)) { |
1905 | if (!edp_have_panel_power(intel_dp)) { |
1805 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1906 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1806 | port_name(intel_dig_port->port)); |
1907 | port_name(intel_dig_port->port)); |
1807 | msleep(intel_dp->panel_power_up_delay); |
1908 | msleep(intel_dp->panel_power_up_delay); |
1808 | } |
1909 | } |
1809 | 1910 | ||
1810 | return need_to_disable; |
1911 | return need_to_disable; |
1811 | } |
1912 | } |
1812 | 1913 | ||
1813 | /* |
1914 | /* |
1814 | * Must be paired with intel_edp_panel_vdd_off() or |
1915 | * Must be paired with intel_edp_panel_vdd_off() or |
1815 | * intel_edp_panel_off(). |
1916 | * intel_edp_panel_off(). |
1816 | * Nested calls to these functions are not allowed since |
1917 | * Nested calls to these functions are not allowed since |
1817 | * we drop the lock. Caller must use some higher level |
1918 | * we drop the lock. Caller must use some higher level |
1818 | * locking to prevent nested calls from other threads. |
1919 | * locking to prevent nested calls from other threads. |
1819 | */ |
1920 | */ |
1820 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1921 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1821 | { |
1922 | { |
1822 | bool vdd; |
1923 | bool vdd; |
1823 | 1924 | ||
1824 | if (!is_edp(intel_dp)) |
1925 | if (!is_edp(intel_dp)) |
1825 | return; |
1926 | return; |
1826 | 1927 | ||
1827 | pps_lock(intel_dp); |
1928 | pps_lock(intel_dp); |
1828 | vdd = edp_panel_vdd_on(intel_dp); |
1929 | vdd = edp_panel_vdd_on(intel_dp); |
1829 | pps_unlock(intel_dp); |
1930 | pps_unlock(intel_dp); |
1830 | 1931 | ||
1831 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1932 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1832 | port_name(dp_to_dig_port(intel_dp)->port)); |
1933 | port_name(dp_to_dig_port(intel_dp)->port)); |
1833 | } |
1934 | } |
1834 | 1935 | ||
1835 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1936 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1836 | { |
1937 | { |
1837 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1938 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1838 | struct drm_i915_private *dev_priv = dev->dev_private; |
1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
1839 | struct intel_digital_port *intel_dig_port = |
1940 | struct intel_digital_port *intel_dig_port = |
1840 | dp_to_dig_port(intel_dp); |
1941 | dp_to_dig_port(intel_dp); |
1841 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1942 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1842 | enum intel_display_power_domain power_domain; |
1943 | enum intel_display_power_domain power_domain; |
1843 | u32 pp; |
1944 | u32 pp; |
1844 | u32 pp_stat_reg, pp_ctrl_reg; |
1945 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1845 | 1946 | ||
1846 | lockdep_assert_held(&dev_priv->pps_mutex); |
1947 | lockdep_assert_held(&dev_priv->pps_mutex); |
1847 | 1948 | ||
1848 | WARN_ON(intel_dp->want_panel_vdd); |
1949 | WARN_ON(intel_dp->want_panel_vdd); |
1849 | 1950 | ||
1850 | if (!edp_have_panel_vdd(intel_dp)) |
1951 | if (!edp_have_panel_vdd(intel_dp)) |
1851 | return; |
1952 | return; |
1852 | 1953 | ||
1853 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1954 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1854 | port_name(intel_dig_port->port)); |
1955 | port_name(intel_dig_port->port)); |
1855 | 1956 | ||
1856 | pp = ironlake_get_pp_control(intel_dp); |
1957 | pp = ironlake_get_pp_control(intel_dp); |
1857 | pp &= ~EDP_FORCE_VDD; |
1958 | pp &= ~EDP_FORCE_VDD; |
1858 | 1959 | ||
1859 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1960 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1860 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1961 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1861 | 1962 | ||
1862 | I915_WRITE(pp_ctrl_reg, pp); |
1963 | I915_WRITE(pp_ctrl_reg, pp); |
1863 | POSTING_READ(pp_ctrl_reg); |
1964 | POSTING_READ(pp_ctrl_reg); |
1864 | 1965 | ||
1865 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1966 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1866 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1967 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1867 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1968 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1868 | 1969 | ||
1869 | if ((pp & POWER_TARGET_ON) == 0) |
1970 | if ((pp & POWER_TARGET_ON) == 0) |
1870 | intel_dp->last_power_cycle = jiffies; |
1971 | intel_dp->last_power_cycle = jiffies; |
1871 | 1972 | ||
1872 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1973 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1873 | intel_display_power_put(dev_priv, power_domain); |
1974 | intel_display_power_put(dev_priv, power_domain); |
1874 | } |
1975 | } |
1875 | 1976 | ||
1876 | static void edp_panel_vdd_work(struct work_struct *__work) |
1977 | static void edp_panel_vdd_work(struct work_struct *__work) |
1877 | { |
1978 | { |
1878 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1979 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1879 | struct intel_dp, panel_vdd_work); |
1980 | struct intel_dp, panel_vdd_work); |
1880 | 1981 | ||
1881 | pps_lock(intel_dp); |
1982 | pps_lock(intel_dp); |
1882 | if (!intel_dp->want_panel_vdd) |
1983 | if (!intel_dp->want_panel_vdd) |
1883 | edp_panel_vdd_off_sync(intel_dp); |
1984 | edp_panel_vdd_off_sync(intel_dp); |
1884 | pps_unlock(intel_dp); |
1985 | pps_unlock(intel_dp); |
1885 | } |
1986 | } |
1886 | 1987 | ||
1887 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1988 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1888 | { |
1989 | { |
1889 | unsigned long delay; |
1990 | unsigned long delay; |
1890 | 1991 | ||
1891 | /* |
1992 | /* |
1892 | * Queue the timer to fire a long time from now (relative to the power |
1993 | * Queue the timer to fire a long time from now (relative to the power |
1893 | * down delay) to keep the panel power up across a sequence of |
1994 | * down delay) to keep the panel power up across a sequence of |
1894 | * operations. |
1995 | * operations. |
1895 | */ |
1996 | */ |
1896 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1997 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1897 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1998 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1898 | } |
1999 | } |
1899 | 2000 | ||
1900 | /* |
2001 | /* |
1901 | * Must be paired with edp_panel_vdd_on(). |
2002 | * Must be paired with edp_panel_vdd_on(). |
1902 | * Must hold pps_mutex around the whole on/off sequence. |
2003 | * Must hold pps_mutex around the whole on/off sequence. |
1903 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
2004 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1904 | */ |
2005 | */ |
1905 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
2006 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1906 | { |
2007 | { |
1907 | struct drm_i915_private *dev_priv = |
2008 | struct drm_i915_private *dev_priv = |
1908 | intel_dp_to_dev(intel_dp)->dev_private; |
2009 | intel_dp_to_dev(intel_dp)->dev_private; |
1909 | 2010 | ||
1910 | lockdep_assert_held(&dev_priv->pps_mutex); |
2011 | lockdep_assert_held(&dev_priv->pps_mutex); |
1911 | 2012 | ||
1912 | if (!is_edp(intel_dp)) |
2013 | if (!is_edp(intel_dp)) |
1913 | return; |
2014 | return; |
1914 | 2015 | ||
1915 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
2016 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
1916 | port_name(dp_to_dig_port(intel_dp)->port)); |
2017 | port_name(dp_to_dig_port(intel_dp)->port)); |
1917 | 2018 | ||
1918 | intel_dp->want_panel_vdd = false; |
2019 | intel_dp->want_panel_vdd = false; |
1919 | 2020 | ||
1920 | if (sync) |
2021 | if (sync) |
1921 | edp_panel_vdd_off_sync(intel_dp); |
2022 | edp_panel_vdd_off_sync(intel_dp); |
1922 | else |
2023 | else |
1923 | edp_panel_vdd_schedule_off(intel_dp); |
2024 | edp_panel_vdd_schedule_off(intel_dp); |
1924 | } |
2025 | } |
1925 | 2026 | ||
1926 | static void edp_panel_on(struct intel_dp *intel_dp) |
2027 | static void edp_panel_on(struct intel_dp *intel_dp) |
1927 | { |
2028 | { |
1928 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2029 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; |
1930 | u32 pp; |
2031 | u32 pp; |
1931 | u32 pp_ctrl_reg; |
2032 | i915_reg_t pp_ctrl_reg; |
1932 | 2033 | ||
1933 | lockdep_assert_held(&dev_priv->pps_mutex); |
2034 | lockdep_assert_held(&dev_priv->pps_mutex); |
1934 | 2035 | ||
1935 | if (!is_edp(intel_dp)) |
2036 | if (!is_edp(intel_dp)) |
1936 | return; |
2037 | return; |
1937 | 2038 | ||
1938 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2039 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1939 | port_name(dp_to_dig_port(intel_dp)->port)); |
2040 | port_name(dp_to_dig_port(intel_dp)->port)); |
1940 | 2041 | ||
1941 | if (WARN(edp_have_panel_power(intel_dp), |
2042 | if (WARN(edp_have_panel_power(intel_dp), |
1942 | "eDP port %c panel power already on\n", |
2043 | "eDP port %c panel power already on\n", |
1943 | port_name(dp_to_dig_port(intel_dp)->port))) |
2044 | port_name(dp_to_dig_port(intel_dp)->port))) |
1944 | return; |
2045 | return; |
1945 | 2046 | ||
1946 | wait_panel_power_cycle(intel_dp); |
2047 | wait_panel_power_cycle(intel_dp); |
1947 | 2048 | ||
1948 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2049 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1949 | pp = ironlake_get_pp_control(intel_dp); |
2050 | pp = ironlake_get_pp_control(intel_dp); |
1950 | if (IS_GEN5(dev)) { |
2051 | if (IS_GEN5(dev)) { |
1951 | /* ILK workaround: disable reset around power sequence */ |
2052 | /* ILK workaround: disable reset around power sequence */ |
1952 | pp &= ~PANEL_POWER_RESET; |
2053 | pp &= ~PANEL_POWER_RESET; |
1953 | I915_WRITE(pp_ctrl_reg, pp); |
2054 | I915_WRITE(pp_ctrl_reg, pp); |
1954 | POSTING_READ(pp_ctrl_reg); |
2055 | POSTING_READ(pp_ctrl_reg); |
1955 | } |
2056 | } |
1956 | 2057 | ||
1957 | pp |= POWER_TARGET_ON; |
2058 | pp |= POWER_TARGET_ON; |
1958 | if (!IS_GEN5(dev)) |
2059 | if (!IS_GEN5(dev)) |
1959 | pp |= PANEL_POWER_RESET; |
2060 | pp |= PANEL_POWER_RESET; |
1960 | 2061 | ||
1961 | I915_WRITE(pp_ctrl_reg, pp); |
2062 | I915_WRITE(pp_ctrl_reg, pp); |
1962 | POSTING_READ(pp_ctrl_reg); |
2063 | POSTING_READ(pp_ctrl_reg); |
1963 | 2064 | ||
1964 | wait_panel_on(intel_dp); |
2065 | wait_panel_on(intel_dp); |
1965 | intel_dp->last_power_on = jiffies; |
2066 | intel_dp->last_power_on = jiffies; |
1966 | 2067 | ||
1967 | if (IS_GEN5(dev)) { |
2068 | if (IS_GEN5(dev)) { |
1968 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
2069 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1969 | I915_WRITE(pp_ctrl_reg, pp); |
2070 | I915_WRITE(pp_ctrl_reg, pp); |
1970 | POSTING_READ(pp_ctrl_reg); |
2071 | POSTING_READ(pp_ctrl_reg); |
1971 | } |
2072 | } |
1972 | } |
2073 | } |
1973 | 2074 | ||
1974 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2075 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1975 | { |
2076 | { |
1976 | if (!is_edp(intel_dp)) |
2077 | if (!is_edp(intel_dp)) |
1977 | return; |
2078 | return; |
1978 | 2079 | ||
1979 | pps_lock(intel_dp); |
2080 | pps_lock(intel_dp); |
1980 | edp_panel_on(intel_dp); |
2081 | edp_panel_on(intel_dp); |
1981 | pps_unlock(intel_dp); |
2082 | pps_unlock(intel_dp); |
1982 | } |
2083 | } |
1983 | 2084 | ||
1984 | 2085 | ||
1985 | static void edp_panel_off(struct intel_dp *intel_dp) |
2086 | static void edp_panel_off(struct intel_dp *intel_dp) |
1986 | { |
2087 | { |
1987 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2088 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1988 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2089 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1989 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2090 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1990 | struct drm_i915_private *dev_priv = dev->dev_private; |
2091 | struct drm_i915_private *dev_priv = dev->dev_private; |
1991 | enum intel_display_power_domain power_domain; |
2092 | enum intel_display_power_domain power_domain; |
1992 | u32 pp; |
2093 | u32 pp; |
1993 | u32 pp_ctrl_reg; |
2094 | i915_reg_t pp_ctrl_reg; |
1994 | 2095 | ||
1995 | lockdep_assert_held(&dev_priv->pps_mutex); |
2096 | lockdep_assert_held(&dev_priv->pps_mutex); |
1996 | 2097 | ||
1997 | if (!is_edp(intel_dp)) |
2098 | if (!is_edp(intel_dp)) |
1998 | return; |
2099 | return; |
1999 | 2100 | ||
2000 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2101 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2001 | port_name(dp_to_dig_port(intel_dp)->port)); |
2102 | port_name(dp_to_dig_port(intel_dp)->port)); |
2002 | 2103 | ||
2003 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2104 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2004 | port_name(dp_to_dig_port(intel_dp)->port)); |
2105 | port_name(dp_to_dig_port(intel_dp)->port)); |
2005 | 2106 | ||
2006 | pp = ironlake_get_pp_control(intel_dp); |
2107 | pp = ironlake_get_pp_control(intel_dp); |
2007 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2108 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2008 | * panels get very unhappy and cease to work. */ |
2109 | * panels get very unhappy and cease to work. */ |
2009 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2110 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2010 | EDP_BLC_ENABLE); |
2111 | EDP_BLC_ENABLE); |
2011 | 2112 | ||
2012 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2113 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2013 | 2114 | ||
2014 | intel_dp->want_panel_vdd = false; |
2115 | intel_dp->want_panel_vdd = false; |
2015 | 2116 | ||
2016 | I915_WRITE(pp_ctrl_reg, pp); |
2117 | I915_WRITE(pp_ctrl_reg, pp); |
2017 | POSTING_READ(pp_ctrl_reg); |
2118 | POSTING_READ(pp_ctrl_reg); |
2018 | 2119 | ||
2019 | intel_dp->last_power_cycle = jiffies; |
2120 | intel_dp->last_power_cycle = jiffies; |
2020 | wait_panel_off(intel_dp); |
2121 | wait_panel_off(intel_dp); |
2021 | 2122 | ||
2022 | /* We got a reference when we enabled the VDD. */ |
2123 | /* We got a reference when we enabled the VDD. */ |
2023 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2124 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2024 | intel_display_power_put(dev_priv, power_domain); |
2125 | intel_display_power_put(dev_priv, power_domain); |
2025 | } |
2126 | } |
2026 | 2127 | ||
2027 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2128 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2028 | { |
2129 | { |
2029 | if (!is_edp(intel_dp)) |
2130 | if (!is_edp(intel_dp)) |
2030 | return; |
2131 | return; |
2031 | 2132 | ||
2032 | pps_lock(intel_dp); |
2133 | pps_lock(intel_dp); |
2033 | edp_panel_off(intel_dp); |
2134 | edp_panel_off(intel_dp); |
2034 | pps_unlock(intel_dp); |
2135 | pps_unlock(intel_dp); |
2035 | } |
2136 | } |
2036 | 2137 | ||
2037 | /* Enable backlight in the panel power control. */ |
2138 | /* Enable backlight in the panel power control. */ |
2038 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2139 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2039 | { |
2140 | { |
2040 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2141 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2041 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2142 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2042 | struct drm_i915_private *dev_priv = dev->dev_private; |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; |
2043 | u32 pp; |
2144 | u32 pp; |
2044 | u32 pp_ctrl_reg; |
2145 | i915_reg_t pp_ctrl_reg; |
2045 | 2146 | ||
2046 | /* |
2147 | /* |
2047 | * If we enable the backlight right away following a panel power |
2148 | * If we enable the backlight right away following a panel power |
2048 | * on, we may see slight flicker as the panel syncs with the eDP |
2149 | * on, we may see slight flicker as the panel syncs with the eDP |
2049 | * link. So delay a bit to make sure the image is solid before |
2150 | * link. So delay a bit to make sure the image is solid before |
2050 | * allowing it to appear. |
2151 | * allowing it to appear. |
2051 | */ |
2152 | */ |
2052 | wait_backlight_on(intel_dp); |
2153 | wait_backlight_on(intel_dp); |
2053 | 2154 | ||
2054 | pps_lock(intel_dp); |
2155 | pps_lock(intel_dp); |
2055 | 2156 | ||
2056 | pp = ironlake_get_pp_control(intel_dp); |
2157 | pp = ironlake_get_pp_control(intel_dp); |
2057 | pp |= EDP_BLC_ENABLE; |
2158 | pp |= EDP_BLC_ENABLE; |
2058 | 2159 | ||
2059 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2160 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2060 | 2161 | ||
2061 | I915_WRITE(pp_ctrl_reg, pp); |
2162 | I915_WRITE(pp_ctrl_reg, pp); |
2062 | POSTING_READ(pp_ctrl_reg); |
2163 | POSTING_READ(pp_ctrl_reg); |
2063 | 2164 | ||
2064 | pps_unlock(intel_dp); |
2165 | pps_unlock(intel_dp); |
2065 | } |
2166 | } |
2066 | 2167 | ||
2067 | /* Enable backlight PWM and backlight PP control. */ |
2168 | /* Enable backlight PWM and backlight PP control. */ |
2068 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2169 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2069 | { |
2170 | { |
2070 | if (!is_edp(intel_dp)) |
2171 | if (!is_edp(intel_dp)) |
2071 | return; |
2172 | return; |
2072 | 2173 | ||
2073 | DRM_DEBUG_KMS("\n"); |
2174 | DRM_DEBUG_KMS("\n"); |
2074 | 2175 | ||
2075 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2176 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2076 | _intel_edp_backlight_on(intel_dp); |
2177 | _intel_edp_backlight_on(intel_dp); |
2077 | } |
2178 | } |
2078 | 2179 | ||
2079 | /* Disable backlight in the panel power control. */ |
2180 | /* Disable backlight in the panel power control. */ |
2080 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2181 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2081 | { |
2182 | { |
2082 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2183 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; |
2184 | struct drm_i915_private *dev_priv = dev->dev_private; |
2084 | u32 pp; |
2185 | u32 pp; |
2085 | u32 pp_ctrl_reg; |
2186 | i915_reg_t pp_ctrl_reg; |
2086 | 2187 | ||
2087 | if (!is_edp(intel_dp)) |
2188 | if (!is_edp(intel_dp)) |
2088 | return; |
2189 | return; |
2089 | 2190 | ||
2090 | pps_lock(intel_dp); |
2191 | pps_lock(intel_dp); |
2091 | 2192 | ||
2092 | pp = ironlake_get_pp_control(intel_dp); |
2193 | pp = ironlake_get_pp_control(intel_dp); |
2093 | pp &= ~EDP_BLC_ENABLE; |
2194 | pp &= ~EDP_BLC_ENABLE; |
2094 | 2195 | ||
2095 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2196 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2096 | 2197 | ||
2097 | I915_WRITE(pp_ctrl_reg, pp); |
2198 | I915_WRITE(pp_ctrl_reg, pp); |
2098 | POSTING_READ(pp_ctrl_reg); |
2199 | POSTING_READ(pp_ctrl_reg); |
2099 | 2200 | ||
2100 | pps_unlock(intel_dp); |
2201 | pps_unlock(intel_dp); |
2101 | 2202 | ||
2102 | intel_dp->last_backlight_off = jiffies; |
2203 | intel_dp->last_backlight_off = jiffies; |
2103 | edp_wait_backlight_off(intel_dp); |
2204 | edp_wait_backlight_off(intel_dp); |
2104 | } |
2205 | } |
2105 | 2206 | ||
2106 | /* Disable backlight PP control and backlight PWM. */ |
2207 | /* Disable backlight PP control and backlight PWM. */ |
2107 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2208 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2108 | { |
2209 | { |
2109 | if (!is_edp(intel_dp)) |
2210 | if (!is_edp(intel_dp)) |
2110 | return; |
2211 | return; |
2111 | 2212 | ||
2112 | DRM_DEBUG_KMS("\n"); |
2213 | DRM_DEBUG_KMS("\n"); |
2113 | 2214 | ||
2114 | _intel_edp_backlight_off(intel_dp); |
2215 | _intel_edp_backlight_off(intel_dp); |
2115 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2216 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2116 | } |
2217 | } |
2117 | 2218 | ||
2118 | /* |
2219 | /* |
2119 | * Hook for controlling the panel power control backlight through the bl_power |
2220 | * Hook for controlling the panel power control backlight through the bl_power |
2120 | * sysfs attribute. Take care to handle multiple calls. |
2221 | * sysfs attribute. Take care to handle multiple calls. |
2121 | */ |
2222 | */ |
2122 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2223 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2123 | bool enable) |
2224 | bool enable) |
2124 | { |
2225 | { |
2125 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2226 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2126 | bool is_enabled; |
2227 | bool is_enabled; |
2127 | 2228 | ||
2128 | pps_lock(intel_dp); |
2229 | pps_lock(intel_dp); |
2129 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2230 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2130 | pps_unlock(intel_dp); |
2231 | pps_unlock(intel_dp); |
2131 | 2232 | ||
2132 | if (is_enabled == enable) |
2233 | if (is_enabled == enable) |
2133 | return; |
2234 | return; |
2134 | 2235 | ||
2135 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2236 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2136 | enable ? "enable" : "disable"); |
2237 | enable ? "enable" : "disable"); |
2137 | 2238 | ||
2138 | if (enable) |
2239 | if (enable) |
2139 | _intel_edp_backlight_on(intel_dp); |
2240 | _intel_edp_backlight_on(intel_dp); |
2140 | else |
2241 | else |
2141 | _intel_edp_backlight_off(intel_dp); |
2242 | _intel_edp_backlight_off(intel_dp); |
2142 | } |
2243 | } |
- | 2244 | ||
- | 2245 | static const char *state_string(bool enabled) |
|
- | 2246 | { |
|
- | 2247 | return enabled ? "on" : "off"; |
|
- | 2248 | } |
|
- | 2249 | ||
- | 2250 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
|
- | 2251 | { |
|
- | 2252 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
- | 2253 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
|
- | 2254 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
|
- | 2255 | ||
- | 2256 | I915_STATE_WARN(cur_state != state, |
|
- | 2257 | "DP port %c state assertion failure (expected %s, current %s)\n", |
|
- | 2258 | port_name(dig_port->port), |
|
- | 2259 | state_string(state), state_string(cur_state)); |
|
- | 2260 | } |
|
- | 2261 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
|
- | 2262 | ||
- | 2263 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
|
- | 2264 | { |
|
- | 2265 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
|
- | 2266 | ||
- | 2267 | I915_STATE_WARN(cur_state != state, |
|
- | 2268 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
|
- | 2269 | state_string(state), state_string(cur_state)); |
|
- | 2270 | } |
|
- | 2271 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
|
- | 2272 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
|
2143 | 2273 | ||
2144 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2274 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2145 | { |
2275 | { |
2146 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2276 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2147 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2277 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2148 | struct drm_device *dev = crtc->dev; |
- | |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
2278 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2150 | u32 dpa_ctl; |
- | |
- | 2279 | ||
- | 2280 | assert_pipe_disabled(dev_priv, crtc->pipe); |
|
2151 | 2281 | assert_dp_port_disabled(intel_dp); |
|
- | 2282 | assert_edp_pll_disabled(dev_priv); |
|
- | 2283 | ||
2152 | assert_pipe_disabled(dev_priv, |
2284 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
- | 2285 | crtc->config->port_clock); |
|
- | 2286 | ||
- | 2287 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
|
- | 2288 | ||
- | 2289 | if (crtc->config->port_clock == 162000) |
|
- | 2290 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
|
- | 2291 | else |
|
- | 2292 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
|
- | 2293 | ||
- | 2294 | I915_WRITE(DP_A, intel_dp->DP); |
|
- | 2295 | POSTING_READ(DP_A); |
|
2153 | to_intel_crtc(crtc)->pipe); |
- | |
2154 | - | ||
2155 | DRM_DEBUG_KMS("\n"); |
- | |
2156 | dpa_ctl = I915_READ(DP_A); |
- | |
2157 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
- | |
2158 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
- | |
2159 | - | ||
2160 | /* We don't adjust intel_dp->DP while tearing down the link, to |
- | |
2161 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
- | |
2162 | * enable bits here to ensure that we don't enable too much. */ |
2296 | udelay(500); |
- | 2297 | ||
2163 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
2298 | intel_dp->DP |= DP_PLL_ENABLE; |
2164 | intel_dp->DP |= DP_PLL_ENABLE; |
2299 | |
2165 | I915_WRITE(DP_A, intel_dp->DP); |
2300 | I915_WRITE(DP_A, intel_dp->DP); |
2166 | POSTING_READ(DP_A); |
2301 | POSTING_READ(DP_A); |
2167 | udelay(200); |
2302 | udelay(200); |
2168 | } |
2303 | } |
2169 | 2304 | ||
2170 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2305 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2171 | { |
2306 | { |
2172 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2307 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2173 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2308 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2174 | struct drm_device *dev = crtc->dev; |
2309 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
- | 2310 | ||
2175 | struct drm_i915_private *dev_priv = dev->dev_private; |
2311 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2176 | u32 dpa_ctl; |
2312 | assert_dp_port_disabled(intel_dp); |
- | 2313 | assert_edp_pll_enabled(dev_priv); |
|
2177 | 2314 | ||
2178 | assert_pipe_disabled(dev_priv, |
- | |
2179 | to_intel_crtc(crtc)->pipe); |
- | |
2180 | 2315 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
|
2181 | dpa_ctl = I915_READ(DP_A); |
- | |
2182 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
- | |
2183 | "dp pll off, should be on\n"); |
2316 | |
2184 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
- | |
2185 | - | ||
2186 | /* We can't rely on the value tracked for the DP register in |
- | |
2187 | * intel_dp->DP because link_down must not change that (otherwise link |
- | |
2188 | * re-training will fail. */ |
2317 | intel_dp->DP &= ~DP_PLL_ENABLE; |
2189 | dpa_ctl &= ~DP_PLL_ENABLE; |
2318 | |
2190 | I915_WRITE(DP_A, dpa_ctl); |
2319 | I915_WRITE(DP_A, intel_dp->DP); |
2191 | POSTING_READ(DP_A); |
2320 | POSTING_READ(DP_A); |
2192 | udelay(200); |
2321 | udelay(200); |
2193 | } |
2322 | } |
2194 | 2323 | ||
2195 | /* If the sink supports it, try to set the power state appropriately */ |
2324 | /* If the sink supports it, try to set the power state appropriately */ |
2196 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2325 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2197 | { |
2326 | { |
2198 | int ret, i; |
2327 | int ret, i; |
2199 | 2328 | ||
2200 | /* Should have a valid DPCD by this point */ |
2329 | /* Should have a valid DPCD by this point */ |
2201 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2330 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2202 | return; |
2331 | return; |
2203 | 2332 | ||
2204 | if (mode != DRM_MODE_DPMS_ON) { |
2333 | if (mode != DRM_MODE_DPMS_ON) { |
2205 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2334 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2206 | DP_SET_POWER_D3); |
2335 | DP_SET_POWER_D3); |
2207 | } else { |
2336 | } else { |
2208 | /* |
2337 | /* |
2209 | * When turning on, we need to retry for 1ms to give the sink |
2338 | * When turning on, we need to retry for 1ms to give the sink |
2210 | * time to wake up. |
2339 | * time to wake up. |
2211 | */ |
2340 | */ |
2212 | for (i = 0; i < 3; i++) { |
2341 | for (i = 0; i < 3; i++) { |
2213 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2342 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2214 | DP_SET_POWER_D0); |
2343 | DP_SET_POWER_D0); |
2215 | if (ret == 1) |
2344 | if (ret == 1) |
2216 | break; |
2345 | break; |
2217 | msleep(1); |
2346 | msleep(1); |
2218 | } |
2347 | } |
2219 | } |
2348 | } |
2220 | 2349 | ||
2221 | if (ret != 1) |
2350 | if (ret != 1) |
2222 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2351 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2223 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2352 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2224 | } |
2353 | } |
2225 | 2354 | ||
2226 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2355 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2227 | enum pipe *pipe) |
2356 | enum pipe *pipe) |
2228 | { |
2357 | { |
2229 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2358 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2230 | enum port port = dp_to_dig_port(intel_dp)->port; |
2359 | enum port port = dp_to_dig_port(intel_dp)->port; |
2231 | struct drm_device *dev = encoder->base.dev; |
2360 | struct drm_device *dev = encoder->base.dev; |
2232 | struct drm_i915_private *dev_priv = dev->dev_private; |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
2233 | enum intel_display_power_domain power_domain; |
2362 | enum intel_display_power_domain power_domain; |
2234 | u32 tmp; |
2363 | u32 tmp; |
- | 2364 | bool ret; |
|
2235 | 2365 | ||
2236 | power_domain = intel_display_port_power_domain(encoder); |
2366 | power_domain = intel_display_port_power_domain(encoder); |
2237 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
2367 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
- | 2368 | return false; |
|
- | 2369 | ||
2238 | return false; |
2370 | ret = false; |
2239 | 2371 | ||
2240 | tmp = I915_READ(intel_dp->output_reg); |
2372 | tmp = I915_READ(intel_dp->output_reg); |
2241 | 2373 | ||
2242 | if (!(tmp & DP_PORT_EN)) |
2374 | if (!(tmp & DP_PORT_EN)) |
2243 | return false; |
2375 | goto out; |
2244 | 2376 | ||
2245 | if (IS_GEN7(dev) && port == PORT_A) { |
2377 | if (IS_GEN7(dev) && port == PORT_A) { |
2246 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2378 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2247 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2379 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2248 | enum pipe p; |
2380 | enum pipe p; |
2249 | 2381 | ||
2250 | for_each_pipe(dev_priv, p) { |
2382 | for_each_pipe(dev_priv, p) { |
2251 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2383 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2252 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2384 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2253 | *pipe = p; |
2385 | *pipe = p; |
2254 | return true; |
2386 | ret = true; |
- | 2387 | ||
- | 2388 | goto out; |
|
2255 | } |
2389 | } |
2256 | } |
2390 | } |
2257 | 2391 | ||
2258 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2392 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2259 | intel_dp->output_reg); |
2393 | i915_mmio_reg_offset(intel_dp->output_reg)); |
2260 | } else if (IS_CHERRYVIEW(dev)) { |
2394 | } else if (IS_CHERRYVIEW(dev)) { |
2261 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2395 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2262 | } else { |
2396 | } else { |
2263 | *pipe = PORT_TO_PIPE(tmp); |
2397 | *pipe = PORT_TO_PIPE(tmp); |
2264 | } |
2398 | } |
2265 | 2399 | ||
- | 2400 | ret = true; |
|
- | 2401 | ||
- | 2402 | out: |
|
- | 2403 | intel_display_power_put(dev_priv, power_domain); |
|
- | 2404 | ||
2266 | return true; |
2405 | return ret; |
2267 | } |
2406 | } |
2268 | 2407 | ||
2269 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2408 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2270 | struct intel_crtc_state *pipe_config) |
2409 | struct intel_crtc_state *pipe_config) |
2271 | { |
2410 | { |
2272 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2411 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2273 | u32 tmp, flags = 0; |
2412 | u32 tmp, flags = 0; |
2274 | struct drm_device *dev = encoder->base.dev; |
2413 | struct drm_device *dev = encoder->base.dev; |
2275 | struct drm_i915_private *dev_priv = dev->dev_private; |
2414 | struct drm_i915_private *dev_priv = dev->dev_private; |
2276 | enum port port = dp_to_dig_port(intel_dp)->port; |
2415 | enum port port = dp_to_dig_port(intel_dp)->port; |
2277 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2416 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2278 | int dotclock; |
2417 | int dotclock; |
2279 | 2418 | ||
2280 | tmp = I915_READ(intel_dp->output_reg); |
2419 | tmp = I915_READ(intel_dp->output_reg); |
2281 | 2420 | ||
2282 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2421 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2283 | 2422 | ||
2284 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2423 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2285 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2424 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2286 | 2425 | ||
2287 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2426 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2288 | flags |= DRM_MODE_FLAG_PHSYNC; |
2427 | flags |= DRM_MODE_FLAG_PHSYNC; |
2289 | else |
2428 | else |
2290 | flags |= DRM_MODE_FLAG_NHSYNC; |
2429 | flags |= DRM_MODE_FLAG_NHSYNC; |
2291 | 2430 | ||
2292 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2431 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2293 | flags |= DRM_MODE_FLAG_PVSYNC; |
2432 | flags |= DRM_MODE_FLAG_PVSYNC; |
2294 | else |
2433 | else |
2295 | flags |= DRM_MODE_FLAG_NVSYNC; |
2434 | flags |= DRM_MODE_FLAG_NVSYNC; |
2296 | } else { |
2435 | } else { |
2297 | if (tmp & DP_SYNC_HS_HIGH) |
2436 | if (tmp & DP_SYNC_HS_HIGH) |
2298 | flags |= DRM_MODE_FLAG_PHSYNC; |
2437 | flags |= DRM_MODE_FLAG_PHSYNC; |
2299 | else |
2438 | else |
2300 | flags |= DRM_MODE_FLAG_NHSYNC; |
2439 | flags |= DRM_MODE_FLAG_NHSYNC; |
2301 | 2440 | ||
2302 | if (tmp & DP_SYNC_VS_HIGH) |
2441 | if (tmp & DP_SYNC_VS_HIGH) |
2303 | flags |= DRM_MODE_FLAG_PVSYNC; |
2442 | flags |= DRM_MODE_FLAG_PVSYNC; |
2304 | else |
2443 | else |
2305 | flags |= DRM_MODE_FLAG_NVSYNC; |
2444 | flags |= DRM_MODE_FLAG_NVSYNC; |
2306 | } |
2445 | } |
2307 | 2446 | ||
2308 | pipe_config->base.adjusted_mode.flags |= flags; |
2447 | pipe_config->base.adjusted_mode.flags |= flags; |
2309 | 2448 | ||
2310 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2449 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2311 | tmp & DP_COLOR_RANGE_16_235) |
2450 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
2312 | pipe_config->limited_color_range = true; |
2451 | pipe_config->limited_color_range = true; |
2313 | 2452 | ||
2314 | pipe_config->has_dp_encoder = true; |
2453 | pipe_config->has_dp_encoder = true; |
2315 | 2454 | ||
2316 | pipe_config->lane_count = |
2455 | pipe_config->lane_count = |
2317 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2456 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2318 | 2457 | ||
2319 | intel_dp_get_m_n(crtc, pipe_config); |
2458 | intel_dp_get_m_n(crtc, pipe_config); |
2320 | 2459 | ||
2321 | if (port == PORT_A) { |
2460 | if (port == PORT_A) { |
2322 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
2461 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
2323 | pipe_config->port_clock = 162000; |
2462 | pipe_config->port_clock = 162000; |
2324 | else |
2463 | else |
2325 | pipe_config->port_clock = 270000; |
2464 | pipe_config->port_clock = 270000; |
2326 | } |
2465 | } |
2327 | 2466 | ||
2328 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2467 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2329 | &pipe_config->dp_m_n); |
2468 | &pipe_config->dp_m_n); |
2330 | 2469 | ||
2331 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2470 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2332 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2471 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2333 | 2472 | ||
2334 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2473 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2335 | 2474 | ||
2336 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2475 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2337 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2476 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2338 | /* |
2477 | /* |
2339 | * This is a big fat ugly hack. |
2478 | * This is a big fat ugly hack. |
2340 | * |
2479 | * |
2341 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2480 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2342 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2481 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2343 | * unknown we fail to light up. Yet the same BIOS boots up with |
2482 | * unknown we fail to light up. Yet the same BIOS boots up with |
2344 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2483 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2345 | * max, not what it tells us to use. |
2484 | * max, not what it tells us to use. |
2346 | * |
2485 | * |
2347 | * Note: This will still be broken if the eDP panel is not lit |
2486 | * Note: This will still be broken if the eDP panel is not lit |
2348 | * up by the BIOS, and thus we can't get the mode at module |
2487 | * up by the BIOS, and thus we can't get the mode at module |
2349 | * load. |
2488 | * load. |
2350 | */ |
2489 | */ |
2351 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2490 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2352 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2491 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2353 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2492 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2354 | } |
2493 | } |
2355 | } |
2494 | } |
2356 | 2495 | ||
2357 | static void intel_disable_dp(struct intel_encoder *encoder) |
2496 | static void intel_disable_dp(struct intel_encoder *encoder) |
2358 | { |
2497 | { |
2359 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2498 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2360 | struct drm_device *dev = encoder->base.dev; |
2499 | struct drm_device *dev = encoder->base.dev; |
2361 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2500 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2362 | 2501 | ||
2363 | if (crtc->config->has_audio) |
2502 | if (crtc->config->has_audio) |
2364 | intel_audio_codec_disable(encoder); |
2503 | intel_audio_codec_disable(encoder); |
2365 | 2504 | ||
2366 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2505 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2367 | intel_psr_disable(intel_dp); |
2506 | intel_psr_disable(intel_dp); |
2368 | 2507 | ||
2369 | /* Make sure the panel is off before trying to change the mode. But also |
2508 | /* Make sure the panel is off before trying to change the mode. But also |
2370 | * ensure that we have vdd while we switch off the panel. */ |
2509 | * ensure that we have vdd while we switch off the panel. */ |
2371 | intel_edp_panel_vdd_on(intel_dp); |
2510 | intel_edp_panel_vdd_on(intel_dp); |
2372 | intel_edp_backlight_off(intel_dp); |
2511 | intel_edp_backlight_off(intel_dp); |
2373 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2512 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2374 | intel_edp_panel_off(intel_dp); |
2513 | intel_edp_panel_off(intel_dp); |
2375 | 2514 | ||
2376 | /* disable the port before the pipe on g4x */ |
2515 | /* disable the port before the pipe on g4x */ |
2377 | if (INTEL_INFO(dev)->gen < 5) |
2516 | if (INTEL_INFO(dev)->gen < 5) |
2378 | intel_dp_link_down(intel_dp); |
2517 | intel_dp_link_down(intel_dp); |
2379 | } |
2518 | } |
2380 | 2519 | ||
2381 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2520 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2382 | { |
2521 | { |
2383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2522 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2384 | enum port port = dp_to_dig_port(intel_dp)->port; |
2523 | enum port port = dp_to_dig_port(intel_dp)->port; |
2385 | 2524 | ||
2386 | intel_dp_link_down(intel_dp); |
2525 | intel_dp_link_down(intel_dp); |
- | 2526 | ||
- | 2527 | /* Only ilk+ has port A */ |
|
2387 | if (port == PORT_A) |
2528 | if (port == PORT_A) |
2388 | ironlake_edp_pll_off(intel_dp); |
2529 | ironlake_edp_pll_off(intel_dp); |
2389 | } |
2530 | } |
2390 | 2531 | ||
2391 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2532 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2392 | { |
2533 | { |
2393 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2534 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2394 | 2535 | ||
2395 | intel_dp_link_down(intel_dp); |
2536 | intel_dp_link_down(intel_dp); |
2396 | } |
2537 | } |
2397 | 2538 | ||
2398 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2539 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2399 | bool reset) |
2540 | bool reset) |
2400 | { |
2541 | { |
2401 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2542 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2402 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2543 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2403 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2544 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2404 | enum pipe pipe = crtc->pipe; |
2545 | enum pipe pipe = crtc->pipe; |
2405 | uint32_t val; |
2546 | uint32_t val; |
2406 | 2547 | ||
2407 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2548 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2408 | if (reset) |
2549 | if (reset) |
2409 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2550 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2410 | else |
2551 | else |
2411 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2552 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2412 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2553 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2413 | 2554 | ||
2414 | if (crtc->config->lane_count > 2) { |
2555 | if (crtc->config->lane_count > 2) { |
2415 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2556 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2416 | if (reset) |
2557 | if (reset) |
2417 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2558 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2418 | else |
2559 | else |
2419 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2560 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2561 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2421 | } |
2562 | } |
2422 | 2563 | ||
2423 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2564 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2424 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2565 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2425 | if (reset) |
2566 | if (reset) |
2426 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2567 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2427 | else |
2568 | else |
2428 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2569 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2429 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2570 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2430 | 2571 | ||
2431 | if (crtc->config->lane_count > 2) { |
2572 | if (crtc->config->lane_count > 2) { |
2432 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2573 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2433 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2574 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2434 | if (reset) |
2575 | if (reset) |
2435 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2576 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2436 | else |
2577 | else |
2437 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2578 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2438 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2579 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2439 | } |
2580 | } |
2440 | } |
2581 | } |
2441 | 2582 | ||
2442 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2583 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2443 | { |
2584 | { |
2444 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2585 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2445 | struct drm_device *dev = encoder->base.dev; |
2586 | struct drm_device *dev = encoder->base.dev; |
2446 | struct drm_i915_private *dev_priv = dev->dev_private; |
2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
2447 | 2588 | ||
2448 | intel_dp_link_down(intel_dp); |
2589 | intel_dp_link_down(intel_dp); |
2449 | 2590 | ||
2450 | mutex_lock(&dev_priv->sb_lock); |
2591 | mutex_lock(&dev_priv->sb_lock); |
2451 | 2592 | ||
2452 | /* Assert data lane reset */ |
2593 | /* Assert data lane reset */ |
2453 | chv_data_lane_soft_reset(encoder, true); |
2594 | chv_data_lane_soft_reset(encoder, true); |
2454 | 2595 | ||
2455 | mutex_unlock(&dev_priv->sb_lock); |
2596 | mutex_unlock(&dev_priv->sb_lock); |
2456 | } |
2597 | } |
2457 | 2598 | ||
2458 | static void |
2599 | static void |
2459 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2600 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2460 | uint32_t *DP, |
2601 | uint32_t *DP, |
2461 | uint8_t dp_train_pat) |
2602 | uint8_t dp_train_pat) |
2462 | { |
2603 | { |
2463 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2604 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2464 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2605 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2465 | struct drm_i915_private *dev_priv = dev->dev_private; |
2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
2466 | enum port port = intel_dig_port->port; |
2607 | enum port port = intel_dig_port->port; |
2467 | 2608 | ||
2468 | if (HAS_DDI(dev)) { |
2609 | if (HAS_DDI(dev)) { |
2469 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2610 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2470 | 2611 | ||
2471 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2612 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2472 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2613 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2473 | else |
2614 | else |
2474 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2615 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2475 | 2616 | ||
2476 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2617 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2477 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2618 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2478 | case DP_TRAINING_PATTERN_DISABLE: |
2619 | case DP_TRAINING_PATTERN_DISABLE: |
2479 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2620 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2480 | 2621 | ||
2481 | break; |
2622 | break; |
2482 | case DP_TRAINING_PATTERN_1: |
2623 | case DP_TRAINING_PATTERN_1: |
2483 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2624 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2484 | break; |
2625 | break; |
2485 | case DP_TRAINING_PATTERN_2: |
2626 | case DP_TRAINING_PATTERN_2: |
2486 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2627 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2487 | break; |
2628 | break; |
2488 | case DP_TRAINING_PATTERN_3: |
2629 | case DP_TRAINING_PATTERN_3: |
2489 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2630 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2490 | break; |
2631 | break; |
2491 | } |
2632 | } |
2492 | I915_WRITE(DP_TP_CTL(port), temp); |
2633 | I915_WRITE(DP_TP_CTL(port), temp); |
2493 | 2634 | ||
2494 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2635 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2495 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2636 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2496 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2637 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2497 | 2638 | ||
2498 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2639 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2499 | case DP_TRAINING_PATTERN_DISABLE: |
2640 | case DP_TRAINING_PATTERN_DISABLE: |
2500 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2641 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2501 | break; |
2642 | break; |
2502 | case DP_TRAINING_PATTERN_1: |
2643 | case DP_TRAINING_PATTERN_1: |
2503 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2644 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2504 | break; |
2645 | break; |
2505 | case DP_TRAINING_PATTERN_2: |
2646 | case DP_TRAINING_PATTERN_2: |
2506 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2647 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2507 | break; |
2648 | break; |
2508 | case DP_TRAINING_PATTERN_3: |
2649 | case DP_TRAINING_PATTERN_3: |
2509 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2650 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2510 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2651 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2511 | break; |
2652 | break; |
2512 | } |
2653 | } |
2513 | 2654 | ||
2514 | } else { |
2655 | } else { |
2515 | if (IS_CHERRYVIEW(dev)) |
2656 | if (IS_CHERRYVIEW(dev)) |
2516 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2657 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2517 | else |
2658 | else |
2518 | *DP &= ~DP_LINK_TRAIN_MASK; |
2659 | *DP &= ~DP_LINK_TRAIN_MASK; |
2519 | 2660 | ||
2520 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2661 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2521 | case DP_TRAINING_PATTERN_DISABLE: |
2662 | case DP_TRAINING_PATTERN_DISABLE: |
2522 | *DP |= DP_LINK_TRAIN_OFF; |
2663 | *DP |= DP_LINK_TRAIN_OFF; |
2523 | break; |
2664 | break; |
2524 | case DP_TRAINING_PATTERN_1: |
2665 | case DP_TRAINING_PATTERN_1: |
2525 | *DP |= DP_LINK_TRAIN_PAT_1; |
2666 | *DP |= DP_LINK_TRAIN_PAT_1; |
2526 | break; |
2667 | break; |
2527 | case DP_TRAINING_PATTERN_2: |
2668 | case DP_TRAINING_PATTERN_2: |
2528 | *DP |= DP_LINK_TRAIN_PAT_2; |
2669 | *DP |= DP_LINK_TRAIN_PAT_2; |
2529 | break; |
2670 | break; |
2530 | case DP_TRAINING_PATTERN_3: |
2671 | case DP_TRAINING_PATTERN_3: |
2531 | if (IS_CHERRYVIEW(dev)) { |
2672 | if (IS_CHERRYVIEW(dev)) { |
2532 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2673 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2533 | } else { |
2674 | } else { |
2534 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2675 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2535 | *DP |= DP_LINK_TRAIN_PAT_2; |
2676 | *DP |= DP_LINK_TRAIN_PAT_2; |
2536 | } |
2677 | } |
2537 | break; |
2678 | break; |
2538 | } |
2679 | } |
2539 | } |
2680 | } |
2540 | } |
2681 | } |
2541 | 2682 | ||
2542 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2683 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2543 | { |
2684 | { |
2544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2685 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
2686 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 2687 | struct intel_crtc *crtc = |
|
- | 2688 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
|
2546 | 2689 | ||
2547 | /* enable with pattern 1 (as per spec) */ |
2690 | /* enable with pattern 1 (as per spec) */ |
2548 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2691 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2549 | DP_TRAINING_PATTERN_1); |
2692 | DP_TRAINING_PATTERN_1); |
2550 | 2693 | ||
2551 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2694 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2552 | POSTING_READ(intel_dp->output_reg); |
2695 | POSTING_READ(intel_dp->output_reg); |
2553 | 2696 | ||
2554 | /* |
2697 | /* |
2555 | * Magic for VLV/CHV. We _must_ first set up the register |
2698 | * Magic for VLV/CHV. We _must_ first set up the register |
2556 | * without actually enabling the port, and then do another |
2699 | * without actually enabling the port, and then do another |
2557 | * write to enable the port. Otherwise link training will |
2700 | * write to enable the port. Otherwise link training will |
2558 | * fail when the power sequencer is freshly used for this port. |
2701 | * fail when the power sequencer is freshly used for this port. |
2559 | */ |
2702 | */ |
2560 | intel_dp->DP |= DP_PORT_EN; |
2703 | intel_dp->DP |= DP_PORT_EN; |
- | 2704 | if (crtc->config->has_audio) |
|
- | 2705 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
|
2561 | 2706 | ||
2562 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2707 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2563 | POSTING_READ(intel_dp->output_reg); |
2708 | POSTING_READ(intel_dp->output_reg); |
2564 | } |
2709 | } |
2565 | 2710 | ||
2566 | static void intel_enable_dp(struct intel_encoder *encoder) |
2711 | static void intel_enable_dp(struct intel_encoder *encoder) |
2567 | { |
2712 | { |
2568 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2713 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2569 | struct drm_device *dev = encoder->base.dev; |
2714 | struct drm_device *dev = encoder->base.dev; |
2570 | struct drm_i915_private *dev_priv = dev->dev_private; |
2715 | struct drm_i915_private *dev_priv = dev->dev_private; |
2571 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2716 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2572 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2717 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
- | 2718 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 2719 | enum pipe pipe = crtc->pipe; |
|
2573 | 2720 | ||
2574 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2721 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2575 | return; |
2722 | return; |
2576 | 2723 | ||
2577 | pps_lock(intel_dp); |
2724 | pps_lock(intel_dp); |
2578 | 2725 | ||
2579 | if (IS_VALLEYVIEW(dev)) |
2726 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
- | 2727 | vlv_init_panel_power_sequencer(intel_dp); |
|
- | 2728 | ||
- | 2729 | /* |
|
- | 2730 | * We get an occasional spurious underrun between the port |
|
- | 2731 | * enable and vdd enable, when enabling port A eDP. |
|
- | 2732 | * |
|
- | 2733 | * FIXME: Not sure if this applies to (PCH) port D eDP as well |
|
- | 2734 | */ |
|
- | 2735 | if (port == PORT_A) |
|
2580 | vlv_init_panel_power_sequencer(intel_dp); |
2736 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
- | 2737 | ||
- | 2738 | intel_dp_enable_port(intel_dp); |
|
- | 2739 | ||
- | 2740 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
|
- | 2741 | /* |
|
- | 2742 | * Underrun reporting for the other pipe was disabled in |
|
- | 2743 | * g4x_pre_enable_dp(). The eDP PLL and port have now been |
|
- | 2744 | * enabled, so it's now safe to re-enable underrun reporting. |
|
- | 2745 | */ |
|
- | 2746 | intel_wait_for_vblank_if_active(dev_priv->dev, !pipe); |
|
- | 2747 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true); |
|
2581 | 2748 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true); |
|
2582 | intel_dp_enable_port(intel_dp); |
2749 | } |
2583 | 2750 | ||
2584 | edp_panel_vdd_on(intel_dp); |
2751 | edp_panel_vdd_on(intel_dp); |
2585 | edp_panel_on(intel_dp); |
2752 | edp_panel_on(intel_dp); |
2586 | edp_panel_vdd_off(intel_dp, true); |
2753 | edp_panel_vdd_off(intel_dp, true); |
- | 2754 | ||
- | 2755 | if (port == PORT_A) |
|
- | 2756 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
|
2587 | 2757 | ||
2588 | pps_unlock(intel_dp); |
2758 | pps_unlock(intel_dp); |
2589 | 2759 | ||
2590 | if (IS_VALLEYVIEW(dev)) { |
2760 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2591 | unsigned int lane_mask = 0x0; |
2761 | unsigned int lane_mask = 0x0; |
2592 | 2762 | ||
2593 | if (IS_CHERRYVIEW(dev)) |
2763 | if (IS_CHERRYVIEW(dev)) |
2594 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2764 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2595 | 2765 | ||
2596 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2766 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2597 | lane_mask); |
2767 | lane_mask); |
2598 | } |
2768 | } |
2599 | 2769 | ||
2600 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2770 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2601 | intel_dp_start_link_train(intel_dp); |
2771 | intel_dp_start_link_train(intel_dp); |
2602 | intel_dp_stop_link_train(intel_dp); |
2772 | intel_dp_stop_link_train(intel_dp); |
2603 | 2773 | ||
2604 | if (crtc->config->has_audio) { |
2774 | if (crtc->config->has_audio) { |
2605 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2775 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2606 | pipe_name(crtc->pipe)); |
2776 | pipe_name(pipe)); |
2607 | intel_audio_codec_enable(encoder); |
2777 | intel_audio_codec_enable(encoder); |
2608 | } |
2778 | } |
2609 | } |
2779 | } |
2610 | 2780 | ||
2611 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2781 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2612 | { |
2782 | { |
2613 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2783 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2614 | 2784 | ||
2615 | intel_enable_dp(encoder); |
2785 | intel_enable_dp(encoder); |
2616 | intel_edp_backlight_on(intel_dp); |
2786 | intel_edp_backlight_on(intel_dp); |
2617 | } |
2787 | } |
2618 | 2788 | ||
2619 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2789 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2620 | { |
2790 | { |
2621 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2791 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2622 | 2792 | ||
2623 | intel_edp_backlight_on(intel_dp); |
2793 | intel_edp_backlight_on(intel_dp); |
2624 | intel_psr_enable(intel_dp); |
2794 | intel_psr_enable(intel_dp); |
2625 | } |
2795 | } |
2626 | 2796 | ||
2627 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2797 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2628 | { |
2798 | { |
- | 2799 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
|
2629 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2800 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2630 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2801 | enum port port = dp_to_dig_port(intel_dp)->port; |
- | 2802 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
|
2631 | 2803 | ||
2632 | intel_dp_prepare(encoder); |
2804 | intel_dp_prepare(encoder); |
- | 2805 | ||
- | 2806 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
|
- | 2807 | /* |
|
- | 2808 | * We get FIFO underruns on the other pipe when |
|
- | 2809 | * enabling the CPU eDP PLL, and when enabling CPU |
|
- | 2810 | * eDP port. We could potentially avoid the PLL |
|
- | 2811 | * underrun with a vblank wait just prior to enabling |
|
- | 2812 | * the PLL, but that doesn't appear to help the port |
|
- | 2813 | * enable case. Just sweep it all under the rug. |
|
- | 2814 | */ |
|
- | 2815 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false); |
|
- | 2816 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false); |
|
- | 2817 | } |
|
2633 | 2818 | ||
2634 | /* Only ilk+ has port A */ |
2819 | /* Only ilk+ has port A */ |
2635 | if (dport->port == PORT_A) { |
- | |
2636 | ironlake_set_pll_cpu_edp(intel_dp); |
2820 | if (port == PORT_A) |
2637 | ironlake_edp_pll_on(intel_dp); |
2821 | ironlake_edp_pll_on(intel_dp); |
2638 | } |
- | |
2639 | } |
2822 | } |
2640 | 2823 | ||
2641 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2824 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2642 | { |
2825 | { |
2643 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2826 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2644 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2827 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2645 | enum pipe pipe = intel_dp->pps_pipe; |
2828 | enum pipe pipe = intel_dp->pps_pipe; |
2646 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2829 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2647 | 2830 | ||
2648 | edp_panel_vdd_off_sync(intel_dp); |
2831 | edp_panel_vdd_off_sync(intel_dp); |
2649 | 2832 | ||
2650 | /* |
2833 | /* |
2651 | * VLV seems to get confused when multiple power seqeuencers |
2834 | * VLV seems to get confused when multiple power seqeuencers |
2652 | * have the same port selected (even if only one has power/vdd |
2835 | * have the same port selected (even if only one has power/vdd |
2653 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2836 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2654 | * CHV on the other hand doesn't seem to mind having the same port |
2837 | * CHV on the other hand doesn't seem to mind having the same port |
2655 | * selected in multiple power seqeuencers, but let's clear the |
2838 | * selected in multiple power seqeuencers, but let's clear the |
2656 | * port select always when logically disconnecting a power sequencer |
2839 | * port select always when logically disconnecting a power sequencer |
2657 | * from a port. |
2840 | * from a port. |
2658 | */ |
2841 | */ |
2659 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2842 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2660 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2843 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2661 | I915_WRITE(pp_on_reg, 0); |
2844 | I915_WRITE(pp_on_reg, 0); |
2662 | POSTING_READ(pp_on_reg); |
2845 | POSTING_READ(pp_on_reg); |
2663 | 2846 | ||
2664 | intel_dp->pps_pipe = INVALID_PIPE; |
2847 | intel_dp->pps_pipe = INVALID_PIPE; |
2665 | } |
2848 | } |
2666 | 2849 | ||
2667 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2850 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2668 | enum pipe pipe) |
2851 | enum pipe pipe) |
2669 | { |
2852 | { |
2670 | struct drm_i915_private *dev_priv = dev->dev_private; |
2853 | struct drm_i915_private *dev_priv = dev->dev_private; |
2671 | struct intel_encoder *encoder; |
2854 | struct intel_encoder *encoder; |
2672 | 2855 | ||
2673 | lockdep_assert_held(&dev_priv->pps_mutex); |
2856 | lockdep_assert_held(&dev_priv->pps_mutex); |
2674 | 2857 | ||
2675 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2858 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2676 | return; |
2859 | return; |
2677 | 2860 | ||
2678 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
- | |
2679 | base.head) { |
2861 | for_each_intel_encoder(dev, encoder) { |
2680 | struct intel_dp *intel_dp; |
2862 | struct intel_dp *intel_dp; |
2681 | enum port port; |
2863 | enum port port; |
2682 | 2864 | ||
2683 | if (encoder->type != INTEL_OUTPUT_EDP) |
2865 | if (encoder->type != INTEL_OUTPUT_EDP) |
2684 | continue; |
2866 | continue; |
2685 | 2867 | ||
2686 | intel_dp = enc_to_intel_dp(&encoder->base); |
2868 | intel_dp = enc_to_intel_dp(&encoder->base); |
2687 | port = dp_to_dig_port(intel_dp)->port; |
2869 | port = dp_to_dig_port(intel_dp)->port; |
2688 | 2870 | ||
2689 | if (intel_dp->pps_pipe != pipe) |
2871 | if (intel_dp->pps_pipe != pipe) |
2690 | continue; |
2872 | continue; |
2691 | 2873 | ||
2692 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2874 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2693 | pipe_name(pipe), port_name(port)); |
2875 | pipe_name(pipe), port_name(port)); |
2694 | 2876 | ||
2695 | WARN(encoder->base.crtc, |
2877 | WARN(encoder->base.crtc, |
2696 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2878 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2697 | pipe_name(pipe), port_name(port)); |
2879 | pipe_name(pipe), port_name(port)); |
2698 | 2880 | ||
2699 | /* make sure vdd is off before we steal it */ |
2881 | /* make sure vdd is off before we steal it */ |
2700 | vlv_detach_power_sequencer(intel_dp); |
2882 | vlv_detach_power_sequencer(intel_dp); |
2701 | } |
2883 | } |
2702 | } |
2884 | } |
2703 | 2885 | ||
2704 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2886 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2705 | { |
2887 | { |
2706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2888 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2707 | struct intel_encoder *encoder = &intel_dig_port->base; |
2889 | struct intel_encoder *encoder = &intel_dig_port->base; |
2708 | struct drm_device *dev = encoder->base.dev; |
2890 | struct drm_device *dev = encoder->base.dev; |
2709 | struct drm_i915_private *dev_priv = dev->dev_private; |
2891 | struct drm_i915_private *dev_priv = dev->dev_private; |
2710 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2892 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2711 | 2893 | ||
2712 | lockdep_assert_held(&dev_priv->pps_mutex); |
2894 | lockdep_assert_held(&dev_priv->pps_mutex); |
2713 | 2895 | ||
2714 | if (!is_edp(intel_dp)) |
2896 | if (!is_edp(intel_dp)) |
2715 | return; |
2897 | return; |
2716 | 2898 | ||
2717 | if (intel_dp->pps_pipe == crtc->pipe) |
2899 | if (intel_dp->pps_pipe == crtc->pipe) |
2718 | return; |
2900 | return; |
2719 | 2901 | ||
2720 | /* |
2902 | /* |
2721 | * If another power sequencer was being used on this |
2903 | * If another power sequencer was being used on this |
2722 | * port previously make sure to turn off vdd there while |
2904 | * port previously make sure to turn off vdd there while |
2723 | * we still have control of it. |
2905 | * we still have control of it. |
2724 | */ |
2906 | */ |
2725 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2907 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2726 | vlv_detach_power_sequencer(intel_dp); |
2908 | vlv_detach_power_sequencer(intel_dp); |
2727 | 2909 | ||
2728 | /* |
2910 | /* |
2729 | * We may be stealing the power |
2911 | * We may be stealing the power |
2730 | * sequencer from another port. |
2912 | * sequencer from another port. |
2731 | */ |
2913 | */ |
2732 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2914 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2733 | 2915 | ||
2734 | /* now it's all ours */ |
2916 | /* now it's all ours */ |
2735 | intel_dp->pps_pipe = crtc->pipe; |
2917 | intel_dp->pps_pipe = crtc->pipe; |
2736 | 2918 | ||
2737 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2919 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2738 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2920 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2739 | 2921 | ||
2740 | /* init power sequencer on this pipe and port */ |
2922 | /* init power sequencer on this pipe and port */ |
2741 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2923 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2742 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2924 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2743 | } |
2925 | } |
2744 | 2926 | ||
2745 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2927 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2746 | { |
2928 | { |
2747 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2929 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2748 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2930 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2749 | struct drm_device *dev = encoder->base.dev; |
2931 | struct drm_device *dev = encoder->base.dev; |
2750 | struct drm_i915_private *dev_priv = dev->dev_private; |
2932 | struct drm_i915_private *dev_priv = dev->dev_private; |
2751 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2933 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2752 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2934 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2753 | int pipe = intel_crtc->pipe; |
2935 | int pipe = intel_crtc->pipe; |
2754 | u32 val; |
2936 | u32 val; |
2755 | 2937 | ||
2756 | mutex_lock(&dev_priv->sb_lock); |
2938 | mutex_lock(&dev_priv->sb_lock); |
2757 | 2939 | ||
2758 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2940 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2759 | val = 0; |
2941 | val = 0; |
2760 | if (pipe) |
2942 | if (pipe) |
2761 | val |= (1<<21); |
2943 | val |= (1<<21); |
2762 | else |
2944 | else |
2763 | val &= ~(1<<21); |
2945 | val &= ~(1<<21); |
2764 | val |= 0x001000c4; |
2946 | val |= 0x001000c4; |
2765 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2947 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2766 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2948 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2767 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2768 | 2950 | ||
2769 | mutex_unlock(&dev_priv->sb_lock); |
2951 | mutex_unlock(&dev_priv->sb_lock); |
2770 | 2952 | ||
2771 | intel_enable_dp(encoder); |
2953 | intel_enable_dp(encoder); |
2772 | } |
2954 | } |
2773 | 2955 | ||
2774 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2956 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2775 | { |
2957 | { |
2776 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2958 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2777 | struct drm_device *dev = encoder->base.dev; |
2959 | struct drm_device *dev = encoder->base.dev; |
2778 | struct drm_i915_private *dev_priv = dev->dev_private; |
2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
2779 | struct intel_crtc *intel_crtc = |
2961 | struct intel_crtc *intel_crtc = |
2780 | to_intel_crtc(encoder->base.crtc); |
2962 | to_intel_crtc(encoder->base.crtc); |
2781 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2963 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2782 | int pipe = intel_crtc->pipe; |
2964 | int pipe = intel_crtc->pipe; |
2783 | 2965 | ||
2784 | intel_dp_prepare(encoder); |
2966 | intel_dp_prepare(encoder); |
2785 | 2967 | ||
2786 | /* Program Tx lane resets to default */ |
2968 | /* Program Tx lane resets to default */ |
2787 | mutex_lock(&dev_priv->sb_lock); |
2969 | mutex_lock(&dev_priv->sb_lock); |
2788 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2970 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2789 | DPIO_PCS_TX_LANE2_RESET | |
2971 | DPIO_PCS_TX_LANE2_RESET | |
2790 | DPIO_PCS_TX_LANE1_RESET); |
2972 | DPIO_PCS_TX_LANE1_RESET); |
2791 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2973 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2792 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2974 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2793 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2975 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2794 | (1< |
2976 | (1< |
2795 | DPIO_PCS_CLK_SOFT_RESET); |
2977 | DPIO_PCS_CLK_SOFT_RESET); |
2796 | 2978 | ||
2797 | /* Fix up inter-pair skew failure */ |
2979 | /* Fix up inter-pair skew failure */ |
2798 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2980 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2799 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2981 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2800 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2982 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2801 | mutex_unlock(&dev_priv->sb_lock); |
2983 | mutex_unlock(&dev_priv->sb_lock); |
2802 | } |
2984 | } |
2803 | 2985 | ||
2804 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2986 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2805 | { |
2987 | { |
2806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2988 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2807 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2989 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2808 | struct drm_device *dev = encoder->base.dev; |
2990 | struct drm_device *dev = encoder->base.dev; |
2809 | struct drm_i915_private *dev_priv = dev->dev_private; |
2991 | struct drm_i915_private *dev_priv = dev->dev_private; |
2810 | struct intel_crtc *intel_crtc = |
2992 | struct intel_crtc *intel_crtc = |
2811 | to_intel_crtc(encoder->base.crtc); |
2993 | to_intel_crtc(encoder->base.crtc); |
2812 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2994 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2813 | int pipe = intel_crtc->pipe; |
2995 | int pipe = intel_crtc->pipe; |
2814 | int data, i, stagger; |
2996 | int data, i, stagger; |
2815 | u32 val; |
2997 | u32 val; |
2816 | 2998 | ||
2817 | mutex_lock(&dev_priv->sb_lock); |
2999 | mutex_lock(&dev_priv->sb_lock); |
2818 | 3000 | ||
2819 | /* allow hardware to manage TX FIFO reset source */ |
3001 | /* allow hardware to manage TX FIFO reset source */ |
2820 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
3002 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2821 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
3003 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2822 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
3004 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2823 | 3005 | ||
2824 | if (intel_crtc->config->lane_count > 2) { |
3006 | if (intel_crtc->config->lane_count > 2) { |
2825 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
3007 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2826 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
3008 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2827 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
3009 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2828 | } |
3010 | } |
2829 | 3011 | ||
2830 | /* Program Tx lane latency optimal setting*/ |
3012 | /* Program Tx lane latency optimal setting*/ |
2831 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3013 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
2832 | /* Set the upar bit */ |
3014 | /* Set the upar bit */ |
2833 | if (intel_crtc->config->lane_count == 1) |
3015 | if (intel_crtc->config->lane_count == 1) |
2834 | data = 0x0; |
3016 | data = 0x0; |
2835 | else |
3017 | else |
2836 | data = (i == 1) ? 0x0 : 0x1; |
3018 | data = (i == 1) ? 0x0 : 0x1; |
2837 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
3019 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
2838 | data << DPIO_UPAR_SHIFT); |
3020 | data << DPIO_UPAR_SHIFT); |
2839 | } |
3021 | } |
2840 | 3022 | ||
2841 | /* Data lane stagger programming */ |
3023 | /* Data lane stagger programming */ |
2842 | if (intel_crtc->config->port_clock > 270000) |
3024 | if (intel_crtc->config->port_clock > 270000) |
2843 | stagger = 0x18; |
3025 | stagger = 0x18; |
2844 | else if (intel_crtc->config->port_clock > 135000) |
3026 | else if (intel_crtc->config->port_clock > 135000) |
2845 | stagger = 0xd; |
3027 | stagger = 0xd; |
2846 | else if (intel_crtc->config->port_clock > 67500) |
3028 | else if (intel_crtc->config->port_clock > 67500) |
2847 | stagger = 0x7; |
3029 | stagger = 0x7; |
2848 | else if (intel_crtc->config->port_clock > 33750) |
3030 | else if (intel_crtc->config->port_clock > 33750) |
2849 | stagger = 0x4; |
3031 | stagger = 0x4; |
2850 | else |
3032 | else |
2851 | stagger = 0x2; |
3033 | stagger = 0x2; |
2852 | 3034 | ||
2853 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
3035 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2854 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3036 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2855 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
3037 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2856 | 3038 | ||
2857 | if (intel_crtc->config->lane_count > 2) { |
3039 | if (intel_crtc->config->lane_count > 2) { |
2858 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
3040 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2859 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3041 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2860 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
3042 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2861 | } |
3043 | } |
2862 | 3044 | ||
2863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
3045 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
2864 | DPIO_LANESTAGGER_STRAP(stagger) | |
3046 | DPIO_LANESTAGGER_STRAP(stagger) | |
2865 | DPIO_LANESTAGGER_STRAP_OVRD | |
3047 | DPIO_LANESTAGGER_STRAP_OVRD | |
2866 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3048 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2867 | DPIO_TX1_STAGGER_MULT(6) | |
3049 | DPIO_TX1_STAGGER_MULT(6) | |
2868 | DPIO_TX2_STAGGER_MULT(0)); |
3050 | DPIO_TX2_STAGGER_MULT(0)); |
2869 | 3051 | ||
2870 | if (intel_crtc->config->lane_count > 2) { |
3052 | if (intel_crtc->config->lane_count > 2) { |
2871 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
3053 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
2872 | DPIO_LANESTAGGER_STRAP(stagger) | |
3054 | DPIO_LANESTAGGER_STRAP(stagger) | |
2873 | DPIO_LANESTAGGER_STRAP_OVRD | |
3055 | DPIO_LANESTAGGER_STRAP_OVRD | |
2874 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3056 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2875 | DPIO_TX1_STAGGER_MULT(7) | |
3057 | DPIO_TX1_STAGGER_MULT(7) | |
2876 | DPIO_TX2_STAGGER_MULT(5)); |
3058 | DPIO_TX2_STAGGER_MULT(5)); |
2877 | } |
3059 | } |
2878 | 3060 | ||
2879 | /* Deassert data lane reset */ |
3061 | /* Deassert data lane reset */ |
2880 | chv_data_lane_soft_reset(encoder, false); |
3062 | chv_data_lane_soft_reset(encoder, false); |
2881 | 3063 | ||
2882 | mutex_unlock(&dev_priv->sb_lock); |
3064 | mutex_unlock(&dev_priv->sb_lock); |
2883 | 3065 | ||
2884 | intel_enable_dp(encoder); |
3066 | intel_enable_dp(encoder); |
2885 | 3067 | ||
2886 | /* Second common lane will stay alive on its own now */ |
3068 | /* Second common lane will stay alive on its own now */ |
2887 | if (dport->release_cl2_override) { |
3069 | if (dport->release_cl2_override) { |
2888 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
3070 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
2889 | dport->release_cl2_override = false; |
3071 | dport->release_cl2_override = false; |
2890 | } |
3072 | } |
2891 | } |
3073 | } |
2892 | 3074 | ||
2893 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
3075 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2894 | { |
3076 | { |
2895 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
3077 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2896 | struct drm_device *dev = encoder->base.dev; |
3078 | struct drm_device *dev = encoder->base.dev; |
2897 | struct drm_i915_private *dev_priv = dev->dev_private; |
3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
2898 | struct intel_crtc *intel_crtc = |
3080 | struct intel_crtc *intel_crtc = |
2899 | to_intel_crtc(encoder->base.crtc); |
3081 | to_intel_crtc(encoder->base.crtc); |
2900 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3082 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2901 | enum pipe pipe = intel_crtc->pipe; |
3083 | enum pipe pipe = intel_crtc->pipe; |
2902 | unsigned int lane_mask = |
3084 | unsigned int lane_mask = |
2903 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
3085 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
2904 | u32 val; |
3086 | u32 val; |
2905 | 3087 | ||
2906 | intel_dp_prepare(encoder); |
3088 | intel_dp_prepare(encoder); |
2907 | 3089 | ||
2908 | /* |
3090 | /* |
2909 | * Must trick the second common lane into life. |
3091 | * Must trick the second common lane into life. |
2910 | * Otherwise we can't even access the PLL. |
3092 | * Otherwise we can't even access the PLL. |
2911 | */ |
3093 | */ |
2912 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
3094 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
2913 | dport->release_cl2_override = |
3095 | dport->release_cl2_override = |
2914 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
3096 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
2915 | 3097 | ||
2916 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
3098 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
2917 | 3099 | ||
2918 | mutex_lock(&dev_priv->sb_lock); |
3100 | mutex_lock(&dev_priv->sb_lock); |
2919 | 3101 | ||
2920 | /* Assert data lane reset */ |
3102 | /* Assert data lane reset */ |
2921 | chv_data_lane_soft_reset(encoder, true); |
3103 | chv_data_lane_soft_reset(encoder, true); |
2922 | 3104 | ||
2923 | /* program left/right clock distribution */ |
3105 | /* program left/right clock distribution */ |
2924 | if (pipe != PIPE_B) { |
3106 | if (pipe != PIPE_B) { |
2925 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3107 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2926 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3108 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2927 | if (ch == DPIO_CH0) |
3109 | if (ch == DPIO_CH0) |
2928 | val |= CHV_BUFLEFTENA1_FORCE; |
3110 | val |= CHV_BUFLEFTENA1_FORCE; |
2929 | if (ch == DPIO_CH1) |
3111 | if (ch == DPIO_CH1) |
2930 | val |= CHV_BUFRIGHTENA1_FORCE; |
3112 | val |= CHV_BUFRIGHTENA1_FORCE; |
2931 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3113 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2932 | } else { |
3114 | } else { |
2933 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3115 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2934 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3116 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2935 | if (ch == DPIO_CH0) |
3117 | if (ch == DPIO_CH0) |
2936 | val |= CHV_BUFLEFTENA2_FORCE; |
3118 | val |= CHV_BUFLEFTENA2_FORCE; |
2937 | if (ch == DPIO_CH1) |
3119 | if (ch == DPIO_CH1) |
2938 | val |= CHV_BUFRIGHTENA2_FORCE; |
3120 | val |= CHV_BUFRIGHTENA2_FORCE; |
2939 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3121 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2940 | } |
3122 | } |
2941 | 3123 | ||
2942 | /* program clock channel usage */ |
3124 | /* program clock channel usage */ |
2943 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
3125 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
2944 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3126 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2945 | if (pipe != PIPE_B) |
3127 | if (pipe != PIPE_B) |
2946 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3128 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2947 | else |
3129 | else |
2948 | val |= CHV_PCS_USEDCLKCHANNEL; |
3130 | val |= CHV_PCS_USEDCLKCHANNEL; |
2949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
3131 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
2950 | 3132 | ||
2951 | if (intel_crtc->config->lane_count > 2) { |
3133 | if (intel_crtc->config->lane_count > 2) { |
2952 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
3134 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
2953 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3135 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2954 | if (pipe != PIPE_B) |
3136 | if (pipe != PIPE_B) |
2955 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3137 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2956 | else |
3138 | else |
2957 | val |= CHV_PCS_USEDCLKCHANNEL; |
3139 | val |= CHV_PCS_USEDCLKCHANNEL; |
2958 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
3140 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
2959 | } |
3141 | } |
2960 | 3142 | ||
2961 | /* |
3143 | /* |
2962 | * This a a bit weird since generally CL |
3144 | * This a a bit weird since generally CL |
2963 | * matches the pipe, but here we need to |
3145 | * matches the pipe, but here we need to |
2964 | * pick the CL based on the port. |
3146 | * pick the CL based on the port. |
2965 | */ |
3147 | */ |
2966 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
3148 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
2967 | if (pipe != PIPE_B) |
3149 | if (pipe != PIPE_B) |
2968 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
3150 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
2969 | else |
3151 | else |
2970 | val |= CHV_CMN_USEDCLKCHANNEL; |
3152 | val |= CHV_CMN_USEDCLKCHANNEL; |
2971 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
3153 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
2972 | 3154 | ||
2973 | mutex_unlock(&dev_priv->sb_lock); |
3155 | mutex_unlock(&dev_priv->sb_lock); |
2974 | } |
3156 | } |
2975 | 3157 | ||
2976 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
3158 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2977 | { |
3159 | { |
2978 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3160 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2979 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
3161 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
2980 | u32 val; |
3162 | u32 val; |
2981 | 3163 | ||
2982 | mutex_lock(&dev_priv->sb_lock); |
3164 | mutex_lock(&dev_priv->sb_lock); |
2983 | 3165 | ||
2984 | /* disable left/right clock distribution */ |
3166 | /* disable left/right clock distribution */ |
2985 | if (pipe != PIPE_B) { |
3167 | if (pipe != PIPE_B) { |
2986 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3168 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2987 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3169 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2988 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3170 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2989 | } else { |
3171 | } else { |
2990 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3172 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2991 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3173 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2992 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3174 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2993 | } |
3175 | } |
2994 | 3176 | ||
2995 | mutex_unlock(&dev_priv->sb_lock); |
3177 | mutex_unlock(&dev_priv->sb_lock); |
2996 | 3178 | ||
2997 | /* |
3179 | /* |
2998 | * Leave the power down bit cleared for at least one |
3180 | * Leave the power down bit cleared for at least one |
2999 | * lane so that chv_powergate_phy_ch() will power |
3181 | * lane so that chv_powergate_phy_ch() will power |
3000 | * on something when the channel is otherwise unused. |
3182 | * on something when the channel is otherwise unused. |
3001 | * When the port is off and the override is removed |
3183 | * When the port is off and the override is removed |
3002 | * the lanes power down anyway, so otherwise it doesn't |
3184 | * the lanes power down anyway, so otherwise it doesn't |
3003 | * really matter what the state of power down bits is |
3185 | * really matter what the state of power down bits is |
3004 | * after this. |
3186 | * after this. |
3005 | */ |
3187 | */ |
3006 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3188 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3007 | } |
3189 | } |
3008 | 3190 | ||
3009 | /* |
3191 | /* |
3010 | * Native read with retry for link status and receiver capability reads for |
3192 | * Native read with retry for link status and receiver capability reads for |
3011 | * cases where the sink may still be asleep. |
3193 | * cases where the sink may still be asleep. |
3012 | * |
3194 | * |
3013 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3195 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3014 | * supposed to retry 3 times per the spec. |
3196 | * supposed to retry 3 times per the spec. |
3015 | */ |
3197 | */ |
3016 | static ssize_t |
3198 | static ssize_t |
3017 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3199 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3018 | void *buffer, size_t size) |
3200 | void *buffer, size_t size) |
3019 | { |
3201 | { |
3020 | ssize_t ret; |
3202 | ssize_t ret; |
3021 | int i; |
3203 | int i; |
3022 | 3204 | ||
3023 | /* |
3205 | /* |
3024 | * Sometime we just get the same incorrect byte repeated |
3206 | * Sometime we just get the same incorrect byte repeated |
3025 | * over the entire buffer. Doing just one throw away read |
3207 | * over the entire buffer. Doing just one throw away read |
3026 | * initially seems to "solve" it. |
3208 | * initially seems to "solve" it. |
3027 | */ |
3209 | */ |
3028 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3210 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3029 | 3211 | ||
3030 | for (i = 0; i < 3; i++) { |
3212 | for (i = 0; i < 3; i++) { |
3031 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3213 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3032 | if (ret == size) |
3214 | if (ret == size) |
3033 | return ret; |
3215 | return ret; |
3034 | msleep(1); |
3216 | msleep(1); |
3035 | } |
3217 | } |
3036 | 3218 | ||
3037 | return ret; |
3219 | return ret; |
3038 | } |
3220 | } |
3039 | 3221 | ||
3040 | /* |
3222 | /* |
3041 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3223 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3042 | * link status information |
3224 | * link status information |
3043 | */ |
3225 | */ |
3044 | static bool |
3226 | bool |
3045 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3227 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3046 | { |
3228 | { |
3047 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3229 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3048 | DP_LANE0_1_STATUS, |
3230 | DP_LANE0_1_STATUS, |
3049 | link_status, |
3231 | link_status, |
3050 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3232 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3051 | } |
3233 | } |
3052 | 3234 | ||
3053 | /* These are source-specific values. */ |
3235 | /* These are source-specific values. */ |
3054 | static uint8_t |
3236 | uint8_t |
3055 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3237 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3056 | { |
3238 | { |
3057 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3239 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3058 | struct drm_i915_private *dev_priv = dev->dev_private; |
3240 | struct drm_i915_private *dev_priv = dev->dev_private; |
3059 | enum port port = dp_to_dig_port(intel_dp)->port; |
3241 | enum port port = dp_to_dig_port(intel_dp)->port; |
3060 | 3242 | ||
3061 | if (IS_BROXTON(dev)) |
3243 | if (IS_BROXTON(dev)) |
3062 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3244 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3063 | else if (INTEL_INFO(dev)->gen >= 9) { |
3245 | else if (INTEL_INFO(dev)->gen >= 9) { |
3064 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3246 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3065 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3247 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3066 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3248 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3067 | } else if (IS_VALLEYVIEW(dev)) |
3249 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
3068 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3250 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3069 | else if (IS_GEN7(dev) && port == PORT_A) |
3251 | else if (IS_GEN7(dev) && port == PORT_A) |
3070 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3252 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3071 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3253 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3072 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3254 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3073 | else |
3255 | else |
3074 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3256 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3075 | } |
3257 | } |
3076 | 3258 | ||
3077 | static uint8_t |
3259 | uint8_t |
3078 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3260 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3079 | { |
3261 | { |
3080 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3262 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3081 | enum port port = dp_to_dig_port(intel_dp)->port; |
3263 | enum port port = dp_to_dig_port(intel_dp)->port; |
3082 | 3264 | ||
3083 | if (INTEL_INFO(dev)->gen >= 9) { |
3265 | if (INTEL_INFO(dev)->gen >= 9) { |
3084 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3266 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3085 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3267 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3086 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3268 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3087 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3269 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3088 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3270 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3090 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3272 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3091 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3092 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3274 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3093 | default: |
3275 | default: |
3094 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3276 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3095 | } |
3277 | } |
3096 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3278 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3097 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3279 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3280 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3099 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3281 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3101 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3283 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3102 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3103 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3285 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3105 | default: |
3287 | default: |
3106 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3288 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3107 | } |
3289 | } |
3108 | } else if (IS_VALLEYVIEW(dev)) { |
3290 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3109 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3291 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3110 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3111 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3293 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3294 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3113 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3295 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3296 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3115 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3297 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3116 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3298 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3117 | default: |
3299 | default: |
3118 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3300 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3119 | } |
3301 | } |
3120 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3302 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3121 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3303 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3304 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3123 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3305 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3306 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3125 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3126 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3308 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3127 | default: |
3309 | default: |
3128 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3310 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3129 | } |
3311 | } |
3130 | } else { |
3312 | } else { |
3131 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3313 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3132 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3314 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3133 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3315 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3134 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3316 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3135 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3317 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3318 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3137 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3319 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3138 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3320 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3139 | default: |
3321 | default: |
3140 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3322 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3141 | } |
3323 | } |
3142 | } |
3324 | } |
3143 | } |
3325 | } |
3144 | 3326 | ||
3145 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3327 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3146 | { |
3328 | { |
3147 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3329 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3148 | struct drm_i915_private *dev_priv = dev->dev_private; |
3330 | struct drm_i915_private *dev_priv = dev->dev_private; |
3149 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3331 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3150 | struct intel_crtc *intel_crtc = |
3332 | struct intel_crtc *intel_crtc = |
3151 | to_intel_crtc(dport->base.base.crtc); |
3333 | to_intel_crtc(dport->base.base.crtc); |
3152 | unsigned long demph_reg_value, preemph_reg_value, |
3334 | unsigned long demph_reg_value, preemph_reg_value, |
3153 | uniqtranscale_reg_value; |
3335 | uniqtranscale_reg_value; |
3154 | uint8_t train_set = intel_dp->train_set[0]; |
3336 | uint8_t train_set = intel_dp->train_set[0]; |
3155 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3337 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3156 | int pipe = intel_crtc->pipe; |
3338 | int pipe = intel_crtc->pipe; |
3157 | 3339 | ||
3158 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3340 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3159 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3341 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3160 | preemph_reg_value = 0x0004000; |
3342 | preemph_reg_value = 0x0004000; |
3161 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3343 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3162 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3344 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3163 | demph_reg_value = 0x2B405555; |
3345 | demph_reg_value = 0x2B405555; |
3164 | uniqtranscale_reg_value = 0x552AB83A; |
3346 | uniqtranscale_reg_value = 0x552AB83A; |
3165 | break; |
3347 | break; |
3166 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3348 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3167 | demph_reg_value = 0x2B404040; |
3349 | demph_reg_value = 0x2B404040; |
3168 | uniqtranscale_reg_value = 0x5548B83A; |
3350 | uniqtranscale_reg_value = 0x5548B83A; |
3169 | break; |
3351 | break; |
3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3352 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3171 | demph_reg_value = 0x2B245555; |
3353 | demph_reg_value = 0x2B245555; |
3172 | uniqtranscale_reg_value = 0x5560B83A; |
3354 | uniqtranscale_reg_value = 0x5560B83A; |
3173 | break; |
3355 | break; |
3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3356 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3175 | demph_reg_value = 0x2B405555; |
3357 | demph_reg_value = 0x2B405555; |
3176 | uniqtranscale_reg_value = 0x5598DA3A; |
3358 | uniqtranscale_reg_value = 0x5598DA3A; |
3177 | break; |
3359 | break; |
3178 | default: |
3360 | default: |
3179 | return 0; |
3361 | return 0; |
3180 | } |
3362 | } |
3181 | break; |
3363 | break; |
3182 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3364 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3183 | preemph_reg_value = 0x0002000; |
3365 | preemph_reg_value = 0x0002000; |
3184 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3366 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3186 | demph_reg_value = 0x2B404040; |
3368 | demph_reg_value = 0x2B404040; |
3187 | uniqtranscale_reg_value = 0x5552B83A; |
3369 | uniqtranscale_reg_value = 0x5552B83A; |
3188 | break; |
3370 | break; |
3189 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3371 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3190 | demph_reg_value = 0x2B404848; |
3372 | demph_reg_value = 0x2B404848; |
3191 | uniqtranscale_reg_value = 0x5580B83A; |
3373 | uniqtranscale_reg_value = 0x5580B83A; |
3192 | break; |
3374 | break; |
3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3375 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3194 | demph_reg_value = 0x2B404040; |
3376 | demph_reg_value = 0x2B404040; |
3195 | uniqtranscale_reg_value = 0x55ADDA3A; |
3377 | uniqtranscale_reg_value = 0x55ADDA3A; |
3196 | break; |
3378 | break; |
3197 | default: |
3379 | default: |
3198 | return 0; |
3380 | return 0; |
3199 | } |
3381 | } |
3200 | break; |
3382 | break; |
3201 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3383 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3202 | preemph_reg_value = 0x0000000; |
3384 | preemph_reg_value = 0x0000000; |
3203 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3385 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3386 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3205 | demph_reg_value = 0x2B305555; |
3387 | demph_reg_value = 0x2B305555; |
3206 | uniqtranscale_reg_value = 0x5570B83A; |
3388 | uniqtranscale_reg_value = 0x5570B83A; |
3207 | break; |
3389 | break; |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3390 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3209 | demph_reg_value = 0x2B2B4040; |
3391 | demph_reg_value = 0x2B2B4040; |
3210 | uniqtranscale_reg_value = 0x55ADDA3A; |
3392 | uniqtranscale_reg_value = 0x55ADDA3A; |
3211 | break; |
3393 | break; |
3212 | default: |
3394 | default: |
3213 | return 0; |
3395 | return 0; |
3214 | } |
3396 | } |
3215 | break; |
3397 | break; |
3216 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3398 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3217 | preemph_reg_value = 0x0006000; |
3399 | preemph_reg_value = 0x0006000; |
3218 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3400 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3401 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3220 | demph_reg_value = 0x1B405555; |
3402 | demph_reg_value = 0x1B405555; |
3221 | uniqtranscale_reg_value = 0x55ADDA3A; |
3403 | uniqtranscale_reg_value = 0x55ADDA3A; |
3222 | break; |
3404 | break; |
3223 | default: |
3405 | default: |
3224 | return 0; |
3406 | return 0; |
3225 | } |
3407 | } |
3226 | break; |
3408 | break; |
3227 | default: |
3409 | default: |
3228 | return 0; |
3410 | return 0; |
3229 | } |
3411 | } |
3230 | 3412 | ||
3231 | mutex_lock(&dev_priv->sb_lock); |
3413 | mutex_lock(&dev_priv->sb_lock); |
3232 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3414 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3233 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3415 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3234 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3416 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3235 | uniqtranscale_reg_value); |
3417 | uniqtranscale_reg_value); |
3236 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3418 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3237 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3419 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3238 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3239 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3421 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3240 | mutex_unlock(&dev_priv->sb_lock); |
3422 | mutex_unlock(&dev_priv->sb_lock); |
3241 | 3423 | ||
3242 | return 0; |
3424 | return 0; |
3243 | } |
3425 | } |
3244 | 3426 | ||
3245 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3427 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3246 | { |
3428 | { |
3247 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3429 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3248 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3430 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3249 | } |
3431 | } |
3250 | 3432 | ||
3251 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3433 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3252 | { |
3434 | { |
3253 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3435 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
3436 | struct drm_i915_private *dev_priv = dev->dev_private; |
3255 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3437 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3256 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3438 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3257 | u32 deemph_reg_value, margin_reg_value, val; |
3439 | u32 deemph_reg_value, margin_reg_value, val; |
3258 | uint8_t train_set = intel_dp->train_set[0]; |
3440 | uint8_t train_set = intel_dp->train_set[0]; |
3259 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3441 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3260 | enum pipe pipe = intel_crtc->pipe; |
3442 | enum pipe pipe = intel_crtc->pipe; |
3261 | int i; |
3443 | int i; |
3262 | 3444 | ||
3263 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3445 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3264 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3446 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3265 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3447 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3266 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3267 | deemph_reg_value = 128; |
3449 | deemph_reg_value = 128; |
3268 | margin_reg_value = 52; |
3450 | margin_reg_value = 52; |
3269 | break; |
3451 | break; |
3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3452 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3271 | deemph_reg_value = 128; |
3453 | deemph_reg_value = 128; |
3272 | margin_reg_value = 77; |
3454 | margin_reg_value = 77; |
3273 | break; |
3455 | break; |
3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3275 | deemph_reg_value = 128; |
3457 | deemph_reg_value = 128; |
3276 | margin_reg_value = 102; |
3458 | margin_reg_value = 102; |
3277 | break; |
3459 | break; |
3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3460 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3279 | deemph_reg_value = 128; |
3461 | deemph_reg_value = 128; |
3280 | margin_reg_value = 154; |
3462 | margin_reg_value = 154; |
3281 | /* FIXME extra to set for 1200 */ |
3463 | /* FIXME extra to set for 1200 */ |
3282 | break; |
3464 | break; |
3283 | default: |
3465 | default: |
3284 | return 0; |
3466 | return 0; |
3285 | } |
3467 | } |
3286 | break; |
3468 | break; |
3287 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3469 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3288 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3470 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3471 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3290 | deemph_reg_value = 85; |
3472 | deemph_reg_value = 85; |
3291 | margin_reg_value = 78; |
3473 | margin_reg_value = 78; |
3292 | break; |
3474 | break; |
3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3475 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3294 | deemph_reg_value = 85; |
3476 | deemph_reg_value = 85; |
3295 | margin_reg_value = 116; |
3477 | margin_reg_value = 116; |
3296 | break; |
3478 | break; |
3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3479 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3298 | deemph_reg_value = 85; |
3480 | deemph_reg_value = 85; |
3299 | margin_reg_value = 154; |
3481 | margin_reg_value = 154; |
3300 | break; |
3482 | break; |
3301 | default: |
3483 | default: |
3302 | return 0; |
3484 | return 0; |
3303 | } |
3485 | } |
3304 | break; |
3486 | break; |
3305 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3487 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3306 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3488 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3489 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3308 | deemph_reg_value = 64; |
3490 | deemph_reg_value = 64; |
3309 | margin_reg_value = 104; |
3491 | margin_reg_value = 104; |
3310 | break; |
3492 | break; |
3311 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3493 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3312 | deemph_reg_value = 64; |
3494 | deemph_reg_value = 64; |
3313 | margin_reg_value = 154; |
3495 | margin_reg_value = 154; |
3314 | break; |
3496 | break; |
3315 | default: |
3497 | default: |
3316 | return 0; |
3498 | return 0; |
3317 | } |
3499 | } |
3318 | break; |
3500 | break; |
3319 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3501 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3320 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3502 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3503 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3322 | deemph_reg_value = 43; |
3504 | deemph_reg_value = 43; |
3323 | margin_reg_value = 154; |
3505 | margin_reg_value = 154; |
3324 | break; |
3506 | break; |
3325 | default: |
3507 | default: |
3326 | return 0; |
3508 | return 0; |
3327 | } |
3509 | } |
3328 | break; |
3510 | break; |
3329 | default: |
3511 | default: |
3330 | return 0; |
3512 | return 0; |
3331 | } |
3513 | } |
3332 | 3514 | ||
3333 | mutex_lock(&dev_priv->sb_lock); |
3515 | mutex_lock(&dev_priv->sb_lock); |
3334 | 3516 | ||
3335 | /* Clear calc init */ |
3517 | /* Clear calc init */ |
3336 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3518 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3337 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3519 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3338 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3520 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3339 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3521 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3340 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3522 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3341 | 3523 | ||
3342 | if (intel_crtc->config->lane_count > 2) { |
3524 | if (intel_crtc->config->lane_count > 2) { |
3343 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3525 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3344 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3526 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3345 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3527 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3346 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3528 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3347 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3348 | } |
3530 | } |
3349 | 3531 | ||
3350 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3532 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3351 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3533 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3352 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3534 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3353 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3535 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3354 | 3536 | ||
3355 | if (intel_crtc->config->lane_count > 2) { |
3537 | if (intel_crtc->config->lane_count > 2) { |
3356 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3538 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3357 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3539 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3358 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3540 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3359 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3541 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3360 | } |
3542 | } |
3361 | 3543 | ||
3362 | /* Program swing deemph */ |
3544 | /* Program swing deemph */ |
3363 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3545 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3364 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3546 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3365 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3547 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3366 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3548 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3367 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3549 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3368 | } |
3550 | } |
3369 | 3551 | ||
3370 | /* Program swing margin */ |
3552 | /* Program swing margin */ |
3371 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3553 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3372 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3554 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3373 | 3555 | ||
3374 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3556 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3375 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3557 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3376 | 3558 | ||
3377 | /* |
3559 | /* |
3378 | * Supposedly this value shouldn't matter when unique transition |
3560 | * Supposedly this value shouldn't matter when unique transition |
3379 | * scale is disabled, but in fact it does matter. Let's just |
3561 | * scale is disabled, but in fact it does matter. Let's just |
3380 | * always program the same value and hope it's OK. |
3562 | * always program the same value and hope it's OK. |
3381 | */ |
3563 | */ |
3382 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3564 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3383 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3565 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3384 | 3566 | ||
3385 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3567 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3386 | } |
3568 | } |
3387 | 3569 | ||
3388 | /* |
3570 | /* |
3389 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3571 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3390 | * for ch1. Might be a typo in the doc. |
3572 | * for ch1. Might be a typo in the doc. |
3391 | * For now, for this unique transition scale selection, set bit |
3573 | * For now, for this unique transition scale selection, set bit |
3392 | * 27 for ch0 and ch1. |
3574 | * 27 for ch0 and ch1. |
3393 | */ |
3575 | */ |
3394 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3576 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3395 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3577 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3396 | if (chv_need_uniq_trans_scale(train_set)) |
3578 | if (chv_need_uniq_trans_scale(train_set)) |
3397 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3579 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3398 | else |
3580 | else |
3399 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3581 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3400 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3582 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3401 | } |
3583 | } |
3402 | 3584 | ||
3403 | /* Start swing calculation */ |
3585 | /* Start swing calculation */ |
3404 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3586 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3405 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3587 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3406 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3588 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3407 | 3589 | ||
3408 | if (intel_crtc->config->lane_count > 2) { |
3590 | if (intel_crtc->config->lane_count > 2) { |
3409 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3591 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3410 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3592 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3411 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3593 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3412 | } |
3594 | } |
3413 | 3595 | ||
3414 | mutex_unlock(&dev_priv->sb_lock); |
3596 | mutex_unlock(&dev_priv->sb_lock); |
3415 | 3597 | ||
3416 | return 0; |
3598 | return 0; |
3417 | } |
3599 | } |
3418 | - | ||
3419 | static void |
- | |
3420 | intel_get_adjust_train(struct intel_dp *intel_dp, |
- | |
3421 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
- | |
3422 | { |
- | |
3423 | uint8_t v = 0; |
- | |
3424 | uint8_t p = 0; |
- | |
3425 | int lane; |
- | |
3426 | uint8_t voltage_max; |
- | |
3427 | uint8_t preemph_max; |
- | |
3428 | - | ||
3429 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
- | |
3430 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
- | |
3431 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
- | |
3432 | - | ||
3433 | if (this_v > v) |
- | |
3434 | v = this_v; |
- | |
3435 | if (this_p > p) |
- | |
3436 | p = this_p; |
- | |
3437 | } |
- | |
3438 | - | ||
3439 | voltage_max = intel_dp_voltage_max(intel_dp); |
- | |
3440 | if (v >= voltage_max) |
- | |
3441 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
- | |
3442 | - | ||
3443 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
- | |
3444 | if (p >= preemph_max) |
- | |
3445 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
- | |
3446 | - | ||
3447 | for (lane = 0; lane < 4; lane++) |
- | |
3448 | intel_dp->train_set[lane] = v | p; |
- | |
3449 | } |
- | |
3450 | 3600 | ||
3451 | static uint32_t |
3601 | static uint32_t |
3452 | gen4_signal_levels(uint8_t train_set) |
3602 | gen4_signal_levels(uint8_t train_set) |
3453 | { |
3603 | { |
3454 | uint32_t signal_levels = 0; |
3604 | uint32_t signal_levels = 0; |
3455 | 3605 | ||
3456 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3606 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3607 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3458 | default: |
3608 | default: |
3459 | signal_levels |= DP_VOLTAGE_0_4; |
3609 | signal_levels |= DP_VOLTAGE_0_4; |
3460 | break; |
3610 | break; |
3461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3611 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3462 | signal_levels |= DP_VOLTAGE_0_6; |
3612 | signal_levels |= DP_VOLTAGE_0_6; |
3463 | break; |
3613 | break; |
3464 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3614 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3465 | signal_levels |= DP_VOLTAGE_0_8; |
3615 | signal_levels |= DP_VOLTAGE_0_8; |
3466 | break; |
3616 | break; |
3467 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3617 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3468 | signal_levels |= DP_VOLTAGE_1_2; |
3618 | signal_levels |= DP_VOLTAGE_1_2; |
3469 | break; |
3619 | break; |
3470 | } |
3620 | } |
3471 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3621 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3472 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3622 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3473 | default: |
3623 | default: |
3474 | signal_levels |= DP_PRE_EMPHASIS_0; |
3624 | signal_levels |= DP_PRE_EMPHASIS_0; |
3475 | break; |
3625 | break; |
3476 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3626 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3477 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3627 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3478 | break; |
3628 | break; |
3479 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3629 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3480 | signal_levels |= DP_PRE_EMPHASIS_6; |
3630 | signal_levels |= DP_PRE_EMPHASIS_6; |
3481 | break; |
3631 | break; |
3482 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3632 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3483 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3633 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3484 | break; |
3634 | break; |
3485 | } |
3635 | } |
3486 | return signal_levels; |
3636 | return signal_levels; |
3487 | } |
3637 | } |
3488 | 3638 | ||
3489 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3639 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3490 | static uint32_t |
3640 | static uint32_t |
3491 | gen6_edp_signal_levels(uint8_t train_set) |
3641 | gen6_edp_signal_levels(uint8_t train_set) |
3492 | { |
3642 | { |
3493 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3643 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3494 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3644 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3495 | switch (signal_levels) { |
3645 | switch (signal_levels) { |
3496 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3646 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3497 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3647 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3498 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3648 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3499 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3649 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3500 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3650 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3501 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3651 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3502 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3652 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3503 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3653 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3504 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3654 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3505 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3655 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3506 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3656 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3507 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3657 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3508 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3658 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3509 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3659 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3510 | default: |
3660 | default: |
3511 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3661 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3512 | "0x%x\n", signal_levels); |
3662 | "0x%x\n", signal_levels); |
3513 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3663 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3514 | } |
3664 | } |
3515 | } |
3665 | } |
3516 | 3666 | ||
3517 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3667 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3518 | static uint32_t |
3668 | static uint32_t |
3519 | gen7_edp_signal_levels(uint8_t train_set) |
3669 | gen7_edp_signal_levels(uint8_t train_set) |
3520 | { |
3670 | { |
3521 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3671 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3522 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3672 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3523 | switch (signal_levels) { |
3673 | switch (signal_levels) { |
3524 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3674 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3525 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3675 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3526 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3676 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3527 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3677 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3528 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3678 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3529 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3679 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3530 | 3680 | ||
3531 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3681 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3532 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3682 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3533 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3683 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3534 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3684 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3535 | 3685 | ||
3536 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3686 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3537 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3687 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3538 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3688 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3539 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3689 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3540 | 3690 | ||
3541 | default: |
3691 | default: |
3542 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3692 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3543 | "0x%x\n", signal_levels); |
3693 | "0x%x\n", signal_levels); |
3544 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3694 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3545 | } |
3695 | } |
3546 | } |
3696 | } |
3547 | - | ||
3548 | /* Properly updates "DP" with the correct signal levels. */ |
3697 | |
3549 | static void |
3698 | void |
3550 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
3699 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
3551 | { |
3700 | { |
3552 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3701 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3553 | enum port port = intel_dig_port->port; |
3702 | enum port port = intel_dig_port->port; |
3554 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3703 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | 3704 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
3555 | uint32_t signal_levels, mask = 0; |
3705 | uint32_t signal_levels, mask = 0; |
3556 | uint8_t train_set = intel_dp->train_set[0]; |
3706 | uint8_t train_set = intel_dp->train_set[0]; |
3557 | 3707 | ||
3558 | if (HAS_DDI(dev)) { |
3708 | if (HAS_DDI(dev)) { |
3559 | signal_levels = ddi_signal_levels(intel_dp); |
3709 | signal_levels = ddi_signal_levels(intel_dp); |
3560 | 3710 | ||
3561 | if (IS_BROXTON(dev)) |
3711 | if (IS_BROXTON(dev)) |
3562 | signal_levels = 0; |
3712 | signal_levels = 0; |
3563 | else |
3713 | else |
3564 | mask = DDI_BUF_EMP_MASK; |
3714 | mask = DDI_BUF_EMP_MASK; |
3565 | } else if (IS_CHERRYVIEW(dev)) { |
3715 | } else if (IS_CHERRYVIEW(dev)) { |
3566 | signal_levels = chv_signal_levels(intel_dp); |
3716 | signal_levels = chv_signal_levels(intel_dp); |
3567 | } else if (IS_VALLEYVIEW(dev)) { |
3717 | } else if (IS_VALLEYVIEW(dev)) { |
3568 | signal_levels = vlv_signal_levels(intel_dp); |
3718 | signal_levels = vlv_signal_levels(intel_dp); |
3569 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3719 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3570 | signal_levels = gen7_edp_signal_levels(train_set); |
3720 | signal_levels = gen7_edp_signal_levels(train_set); |
3571 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3721 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3572 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3722 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3573 | signal_levels = gen6_edp_signal_levels(train_set); |
3723 | signal_levels = gen6_edp_signal_levels(train_set); |
3574 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3724 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3575 | } else { |
3725 | } else { |
3576 | signal_levels = gen4_signal_levels(train_set); |
3726 | signal_levels = gen4_signal_levels(train_set); |
3577 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3727 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3578 | } |
3728 | } |
3579 | 3729 | ||
3580 | if (mask) |
3730 | if (mask) |
3581 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3731 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3582 | 3732 | ||
3583 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3733 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3584 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3734 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3585 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3735 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3586 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3736 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3587 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3737 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3588 | 3738 | ||
3589 | *DP = (*DP & ~mask) | signal_levels; |
- | |
3590 | } |
- | |
3591 | - | ||
3592 | static bool |
- | |
3593 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
- | |
3594 | uint32_t *DP, |
- | |
3595 | uint8_t dp_train_pat) |
- | |
3596 | { |
- | |
3597 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
3598 | struct drm_i915_private *dev_priv = |
- | |
3599 | to_i915(intel_dig_port->base.base.dev); |
- | |
3600 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
- | |
3601 | int ret, len; |
- | |
3602 | - | ||
3603 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
3739 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
3604 | 3740 | ||
3605 | I915_WRITE(intel_dp->output_reg, *DP); |
- | |
3606 | POSTING_READ(intel_dp->output_reg); |
- | |
3607 | - | ||
3608 | buf[0] = dp_train_pat; |
- | |
3609 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
- | |
3610 | DP_TRAINING_PATTERN_DISABLE) { |
- | |
3611 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
- | |
3612 | len = 1; |
- | |
3613 | } else { |
- | |
3614 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
- | |
3615 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
- | |
3616 | len = intel_dp->lane_count + 1; |
- | |
3617 | } |
- | |
3618 | - | ||
3619 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
- | |
3620 | buf, len); |
- | |
3621 | 3741 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
|
3622 | return ret == len; |
3742 | POSTING_READ(intel_dp->output_reg); |
3623 | } |
3743 | } |
3624 | 3744 | ||
3625 | static bool |
3745 | void |
3626 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
- | |
3627 | uint8_t dp_train_pat) |
- | |
3628 | { |
- | |
3629 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
- | |
3630 | intel_dp_set_signal_levels(intel_dp, DP); |
- | |
3631 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
- | |
3632 | } |
- | |
3633 | - | ||
3634 | static bool |
- | |
3635 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
3746 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3636 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3747 | uint8_t dp_train_pat) |
3637 | { |
3748 | { |
3638 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3749 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3639 | struct drm_i915_private *dev_priv = |
3750 | struct drm_i915_private *dev_priv = |
3640 | to_i915(intel_dig_port->base.base.dev); |
3751 | to_i915(intel_dig_port->base.base.dev); |
3641 | int ret; |
- | |
3642 | 3752 | ||
3643 | intel_get_adjust_train(intel_dp, link_status); |
- | |
3644 | intel_dp_set_signal_levels(intel_dp, DP); |
3753 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
3645 | 3754 | ||
3646 | I915_WRITE(intel_dp->output_reg, *DP); |
- | |
3647 | POSTING_READ(intel_dp->output_reg); |
- | |
3648 | - | ||
3649 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
- | |
3650 | intel_dp->train_set, intel_dp->lane_count); |
- | |
3651 | 3755 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
|
3652 | return ret == intel_dp->lane_count; |
3756 | POSTING_READ(intel_dp->output_reg); |
3653 | } |
3757 | } |
3654 | 3758 | ||
3655 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3759 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3656 | { |
3760 | { |
3657 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3761 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3658 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3762 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3659 | struct drm_i915_private *dev_priv = dev->dev_private; |
3763 | struct drm_i915_private *dev_priv = dev->dev_private; |
3660 | enum port port = intel_dig_port->port; |
3764 | enum port port = intel_dig_port->port; |
3661 | uint32_t val; |
3765 | uint32_t val; |
3662 | 3766 | ||
3663 | if (!HAS_DDI(dev)) |
3767 | if (!HAS_DDI(dev)) |
3664 | return; |
3768 | return; |
3665 | 3769 | ||
3666 | val = I915_READ(DP_TP_CTL(port)); |
3770 | val = I915_READ(DP_TP_CTL(port)); |
3667 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3771 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3668 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3772 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3669 | I915_WRITE(DP_TP_CTL(port), val); |
3773 | I915_WRITE(DP_TP_CTL(port), val); |
3670 | 3774 | ||
3671 | /* |
3775 | /* |
3672 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3776 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3673 | * we need to set idle transmission mode is to work around a HW issue |
3777 | * we need to set idle transmission mode is to work around a HW issue |
3674 | * where we enable the pipe while not in idle link-training mode. |
3778 | * where we enable the pipe while not in idle link-training mode. |
3675 | * In this case there is requirement to wait for a minimum number of |
3779 | * In this case there is requirement to wait for a minimum number of |
3676 | * idle patterns to be sent. |
3780 | * idle patterns to be sent. |
3677 | */ |
3781 | */ |
3678 | if (port == PORT_A) |
3782 | if (port == PORT_A) |
3679 | return; |
3783 | return; |
3680 | 3784 | ||
3681 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3785 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3682 | 1)) |
3786 | 1)) |
3683 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3787 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3684 | } |
3788 | } |
3685 | - | ||
3686 | /* Enable corresponding port and start training pattern 1 */ |
- | |
3687 | static void |
- | |
3688 | intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) |
- | |
3689 | { |
- | |
3690 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
- | |
3691 | struct drm_device *dev = encoder->dev; |
- | |
3692 | int i; |
- | |
3693 | uint8_t voltage; |
- | |
3694 | int voltage_tries, loop_tries; |
- | |
3695 | uint32_t DP = intel_dp->DP; |
- | |
3696 | uint8_t link_config[2]; |
- | |
3697 | uint8_t link_bw, rate_select; |
- | |
3698 | - | ||
3699 | if (HAS_DDI(dev)) |
- | |
3700 | intel_ddi_prepare_link_retrain(encoder); |
- | |
3701 | - | ||
3702 | intel_dp_compute_rate(intel_dp, intel_dp->link_rate, |
- | |
3703 | &link_bw, &rate_select); |
- | |
3704 | - | ||
3705 | /* Write the link configuration data */ |
- | |
3706 | link_config[0] = link_bw; |
- | |
3707 | link_config[1] = intel_dp->lane_count; |
- | |
3708 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
- | |
3709 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
- | |
3710 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
- | |
3711 | if (intel_dp->num_sink_rates) |
- | |
3712 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, |
- | |
3713 | &rate_select, 1); |
- | |
3714 | - | ||
3715 | link_config[0] = 0; |
- | |
3716 | link_config[1] = DP_SET_ANSI_8B10B; |
- | |
3717 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
- | |
3718 | - | ||
3719 | DP |= DP_PORT_EN; |
- | |
3720 | - | ||
3721 | /* clock recovery */ |
- | |
3722 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
- | |
3723 | DP_TRAINING_PATTERN_1 | |
- | |
3724 | DP_LINK_SCRAMBLING_DISABLE)) { |
- | |
3725 | DRM_ERROR("failed to enable link training\n"); |
- | |
3726 | return; |
- | |
3727 | } |
- | |
3728 | - | ||
3729 | voltage = 0xff; |
- | |
3730 | voltage_tries = 0; |
- | |
3731 | loop_tries = 0; |
- | |
3732 | for (;;) { |
- | |
3733 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
- | |
3734 | - | ||
3735 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
- | |
3736 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
- | |
3737 | DRM_ERROR("failed to get link status\n"); |
- | |
3738 | break; |
- | |
3739 | } |
- | |
3740 | - | ||
3741 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
- | |
3742 | DRM_DEBUG_KMS("clock recovery OK\n"); |
- | |
3743 | break; |
- | |
3744 | } |
- | |
3745 | - | ||
3746 | - | ||
3747 | /* Check to see if we've tried the max voltage */ |
- | |
3748 | for (i = 0; i < intel_dp->lane_count; i++) |
- | |
3749 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
- | |
3750 | break; |
- | |
3751 | if (i == intel_dp->lane_count) { |
- | |
3752 | ++loop_tries; |
- | |
3753 | if (loop_tries == 5) { |
- | |
3754 | DRM_ERROR("too many full retries, give up\n"); |
- | |
3755 | break; |
- | |
3756 | } |
- | |
3757 | intel_dp_reset_link_train(intel_dp, &DP, |
- | |
3758 | DP_TRAINING_PATTERN_1 | |
- | |
3759 | DP_LINK_SCRAMBLING_DISABLE); |
- | |
3760 | voltage_tries = 0; |
- | |
3761 | continue; |
- | |
3762 | } |
- | |
3763 | - | ||
3764 | /* Check to see if we've tried the same voltage 5 times */ |
- | |
3765 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
- | |
3766 | ++voltage_tries; |
- | |
3767 | if (voltage_tries == 5) { |
- | |
3768 | DRM_ERROR("too many voltage retries, give up\n"); |
- | |
3769 | break; |
- | |
3770 | } |
- | |
3771 | } else |
- | |
3772 | voltage_tries = 0; |
- | |
3773 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
- | |
3774 | - | ||
3775 | /* Update training set as requested by target */ |
- | |
3776 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
- | |
3777 | DRM_ERROR("failed to update link training\n"); |
- | |
3778 | break; |
- | |
3779 | } |
- | |
3780 | } |
- | |
3781 | - | ||
3782 | intel_dp->DP = DP; |
- | |
3783 | } |
- | |
3784 | - | ||
3785 | static void |
- | |
3786 | intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) |
- | |
3787 | { |
- | |
3788 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
3789 | struct drm_device *dev = dig_port->base.base.dev; |
- | |
3790 | bool channel_eq = false; |
- | |
3791 | int tries, cr_tries; |
- | |
3792 | uint32_t DP = intel_dp->DP; |
- | |
3793 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
- | |
3794 | - | ||
3795 | /* |
- | |
3796 | * Training Pattern 3 for HBR2 or 1.2 devices that support it. |
- | |
3797 | * |
- | |
3798 | * Intel platforms that support HBR2 also support TPS3. TPS3 support is |
- | |
3799 | * also mandatory for downstream devices that support HBR2. |
- | |
3800 | * |
- | |
3801 | * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is |
- | |
3802 | * supported but still not enabled. |
- | |
3803 | */ |
- | |
3804 | if (intel_dp_source_supports_hbr2(dev) && |
- | |
3805 | drm_dp_tps3_supported(intel_dp->dpcd)) |
- | |
3806 | training_pattern = DP_TRAINING_PATTERN_3; |
- | |
3807 | else if (intel_dp->link_rate == 540000) |
- | |
3808 | DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n"); |
- | |
3809 | - | ||
3810 | /* channel equalization */ |
- | |
3811 | if (!intel_dp_set_link_train(intel_dp, &DP, |
- | |
3812 | training_pattern | |
- | |
3813 | DP_LINK_SCRAMBLING_DISABLE)) { |
- | |
3814 | DRM_ERROR("failed to start channel equalization\n"); |
- | |
3815 | return; |
- | |
3816 | } |
- | |
3817 | - | ||
3818 | tries = 0; |
- | |
3819 | cr_tries = 0; |
- | |
3820 | channel_eq = false; |
- | |
3821 | for (;;) { |
- | |
3822 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
- | |
3823 | - | ||
3824 | if (cr_tries > 5) { |
- | |
3825 | DRM_ERROR("failed to train DP, aborting\n"); |
- | |
3826 | break; |
- | |
3827 | } |
- | |
3828 | - | ||
3829 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
- | |
3830 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
- | |
3831 | DRM_ERROR("failed to get link status\n"); |
- | |
3832 | break; |
- | |
3833 | } |
- | |
3834 | - | ||
3835 | /* Make sure clock is still ok */ |
- | |
3836 | if (!drm_dp_clock_recovery_ok(link_status, |
- | |
3837 | intel_dp->lane_count)) { |
- | |
3838 | intel_dp_link_training_clock_recovery(intel_dp); |
- | |
3839 | intel_dp_set_link_train(intel_dp, &DP, |
- | |
3840 | training_pattern | |
- | |
3841 | DP_LINK_SCRAMBLING_DISABLE); |
- | |
3842 | cr_tries++; |
- | |
3843 | continue; |
- | |
3844 | } |
- | |
3845 | - | ||
3846 | if (drm_dp_channel_eq_ok(link_status, |
- | |
3847 | intel_dp->lane_count)) { |
- | |
3848 | channel_eq = true; |
- | |
3849 | break; |
- | |
3850 | } |
- | |
3851 | - | ||
3852 | /* Try 5 times, then try clock recovery if that fails */ |
- | |
3853 | if (tries > 5) { |
- | |
3854 | intel_dp_link_training_clock_recovery(intel_dp); |
- | |
3855 | intel_dp_set_link_train(intel_dp, &DP, |
- | |
3856 | training_pattern | |
- | |
3857 | DP_LINK_SCRAMBLING_DISABLE); |
- | |
3858 | tries = 0; |
- | |
3859 | cr_tries++; |
- | |
3860 | continue; |
- | |
3861 | } |
- | |
3862 | - | ||
3863 | /* Update training set as requested by target */ |
- | |
3864 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
- | |
3865 | DRM_ERROR("failed to update link training\n"); |
- | |
3866 | break; |
- | |
3867 | } |
- | |
3868 | ++tries; |
- | |
3869 | } |
- | |
3870 | - | ||
3871 | intel_dp_set_idle_link_train(intel_dp); |
- | |
3872 | - | ||
3873 | intel_dp->DP = DP; |
- | |
3874 | - | ||
3875 | if (channel_eq) |
- | |
3876 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
- | |
3877 | } |
- | |
3878 | - | ||
3879 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
- | |
3880 | { |
- | |
3881 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
- | |
3882 | DP_TRAINING_PATTERN_DISABLE); |
- | |
3883 | } |
- | |
3884 | - | ||
3885 | void |
- | |
3886 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
- | |
3887 | { |
- | |
3888 | intel_dp_link_training_clock_recovery(intel_dp); |
- | |
3889 | intel_dp_link_training_channel_equalization(intel_dp); |
- | |
3890 | } |
- | |
3891 | 3789 | ||
3892 | static void |
3790 | static void |
3893 | intel_dp_link_down(struct intel_dp *intel_dp) |
3791 | intel_dp_link_down(struct intel_dp *intel_dp) |
3894 | { |
3792 | { |
3895 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3793 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3896 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3794 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3897 | enum port port = intel_dig_port->port; |
3795 | enum port port = intel_dig_port->port; |
3898 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3796 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3899 | struct drm_i915_private *dev_priv = dev->dev_private; |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
3900 | uint32_t DP = intel_dp->DP; |
3798 | uint32_t DP = intel_dp->DP; |
3901 | 3799 | ||
3902 | if (WARN_ON(HAS_DDI(dev))) |
3800 | if (WARN_ON(HAS_DDI(dev))) |
3903 | return; |
3801 | return; |
3904 | 3802 | ||
3905 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3803 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3906 | return; |
3804 | return; |
3907 | 3805 | ||
3908 | DRM_DEBUG_KMS("\n"); |
3806 | DRM_DEBUG_KMS("\n"); |
3909 | 3807 | ||
3910 | if ((IS_GEN7(dev) && port == PORT_A) || |
3808 | if ((IS_GEN7(dev) && port == PORT_A) || |
3911 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3809 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3912 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3810 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3913 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3811 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3914 | } else { |
3812 | } else { |
3915 | if (IS_CHERRYVIEW(dev)) |
3813 | if (IS_CHERRYVIEW(dev)) |
3916 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3814 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3917 | else |
3815 | else |
3918 | DP &= ~DP_LINK_TRAIN_MASK; |
3816 | DP &= ~DP_LINK_TRAIN_MASK; |
3919 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3817 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3920 | } |
3818 | } |
3921 | I915_WRITE(intel_dp->output_reg, DP); |
3819 | I915_WRITE(intel_dp->output_reg, DP); |
3922 | POSTING_READ(intel_dp->output_reg); |
3820 | POSTING_READ(intel_dp->output_reg); |
3923 | 3821 | ||
3924 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3822 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3925 | I915_WRITE(intel_dp->output_reg, DP); |
3823 | I915_WRITE(intel_dp->output_reg, DP); |
3926 | POSTING_READ(intel_dp->output_reg); |
3824 | POSTING_READ(intel_dp->output_reg); |
3927 | 3825 | ||
3928 | /* |
3826 | /* |
3929 | * HW workaround for IBX, we need to move the port |
3827 | * HW workaround for IBX, we need to move the port |
3930 | * to transcoder A after disabling it to allow the |
3828 | * to transcoder A after disabling it to allow the |
3931 | * matching HDMI port to be enabled on transcoder A. |
3829 | * matching HDMI port to be enabled on transcoder A. |
3932 | */ |
3830 | */ |
3933 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
3831 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
- | 3832 | /* |
|
- | 3833 | * We get CPU/PCH FIFO underruns on the other pipe when |
|
- | 3834 | * doing the workaround. Sweep them under the rug. |
|
- | 3835 | */ |
|
- | 3836 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
|
- | 3837 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
|
- | 3838 | ||
3934 | /* always enable with pattern 1 (as per spec) */ |
3839 | /* always enable with pattern 1 (as per spec) */ |
3935 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3840 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3936 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3841 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3937 | I915_WRITE(intel_dp->output_reg, DP); |
3842 | I915_WRITE(intel_dp->output_reg, DP); |
3938 | POSTING_READ(intel_dp->output_reg); |
3843 | POSTING_READ(intel_dp->output_reg); |
3939 | 3844 | ||
3940 | DP &= ~DP_PORT_EN; |
3845 | DP &= ~DP_PORT_EN; |
3941 | I915_WRITE(intel_dp->output_reg, DP); |
3846 | I915_WRITE(intel_dp->output_reg, DP); |
3942 | POSTING_READ(intel_dp->output_reg); |
3847 | POSTING_READ(intel_dp->output_reg); |
- | 3848 | ||
- | 3849 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
|
- | 3850 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
|
- | 3851 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
|
3943 | } |
3852 | } |
3944 | 3853 | ||
3945 | msleep(intel_dp->panel_power_down_delay); |
3854 | msleep(intel_dp->panel_power_down_delay); |
- | 3855 | ||
- | 3856 | intel_dp->DP = DP; |
|
3946 | } |
3857 | } |
3947 | 3858 | ||
3948 | static bool |
3859 | static bool |
3949 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3860 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3950 | { |
3861 | { |
3951 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3862 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3952 | struct drm_device *dev = dig_port->base.base.dev; |
3863 | struct drm_device *dev = dig_port->base.base.dev; |
3953 | struct drm_i915_private *dev_priv = dev->dev_private; |
3864 | struct drm_i915_private *dev_priv = dev->dev_private; |
3954 | uint8_t rev; |
3865 | uint8_t rev; |
3955 | 3866 | ||
3956 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3867 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3957 | sizeof(intel_dp->dpcd)) < 0) |
3868 | sizeof(intel_dp->dpcd)) < 0) |
3958 | return false; /* aux transfer failed */ |
3869 | return false; /* aux transfer failed */ |
3959 | 3870 | ||
3960 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3871 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3961 | 3872 | ||
3962 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3873 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3963 | return false; /* DPCD not present */ |
3874 | return false; /* DPCD not present */ |
3964 | 3875 | ||
3965 | /* Check if the panel supports PSR */ |
3876 | /* Check if the panel supports PSR */ |
3966 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3877 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3967 | if (is_edp(intel_dp)) { |
3878 | if (is_edp(intel_dp)) { |
3968 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3879 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3969 | intel_dp->psr_dpcd, |
3880 | intel_dp->psr_dpcd, |
3970 | sizeof(intel_dp->psr_dpcd)); |
3881 | sizeof(intel_dp->psr_dpcd)); |
3971 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3882 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3972 | dev_priv->psr.sink_support = true; |
3883 | dev_priv->psr.sink_support = true; |
3973 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3884 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3974 | } |
3885 | } |
3975 | 3886 | ||
3976 | if (INTEL_INFO(dev)->gen >= 9 && |
3887 | if (INTEL_INFO(dev)->gen >= 9 && |
3977 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3888 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3978 | uint8_t frame_sync_cap; |
3889 | uint8_t frame_sync_cap; |
3979 | 3890 | ||
3980 | dev_priv->psr.sink_support = true; |
3891 | dev_priv->psr.sink_support = true; |
3981 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3892 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3982 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
3893 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
3983 | &frame_sync_cap, 1); |
3894 | &frame_sync_cap, 1); |
3984 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3895 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3985 | /* PSR2 needs frame sync as well */ |
3896 | /* PSR2 needs frame sync as well */ |
3986 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
3897 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
3987 | DRM_DEBUG_KMS("PSR2 %s on sink", |
3898 | DRM_DEBUG_KMS("PSR2 %s on sink", |
3988 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
3899 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
3989 | } |
3900 | } |
3990 | } |
3901 | } |
3991 | 3902 | ||
3992 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
3903 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
3993 | yesno(intel_dp_source_supports_hbr2(dev)), |
3904 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
3994 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
3905 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
3995 | 3906 | ||
3996 | /* Intermediate frequency support */ |
3907 | /* Intermediate frequency support */ |
3997 | if (is_edp(intel_dp) && |
3908 | if (is_edp(intel_dp) && |
3998 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
3909 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
3999 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
3910 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
4000 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
3911 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
4001 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
3912 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
4002 | int i; |
3913 | int i; |
4003 | 3914 | ||
4004 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3915 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
4005 | DP_SUPPORTED_LINK_RATES, |
3916 | DP_SUPPORTED_LINK_RATES, |
4006 | sink_rates, |
3917 | sink_rates, |
4007 | sizeof(sink_rates)); |
3918 | sizeof(sink_rates)); |
4008 | 3919 | ||
4009 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3920 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4010 | int val = le16_to_cpu(sink_rates[i]); |
3921 | int val = le16_to_cpu(sink_rates[i]); |
4011 | 3922 | ||
4012 | if (val == 0) |
3923 | if (val == 0) |
4013 | break; |
3924 | break; |
4014 | 3925 | ||
4015 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3926 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
4016 | intel_dp->sink_rates[i] = (val * 200) / 10; |
3927 | intel_dp->sink_rates[i] = (val * 200) / 10; |
4017 | } |
3928 | } |
4018 | intel_dp->num_sink_rates = i; |
3929 | intel_dp->num_sink_rates = i; |
4019 | } |
3930 | } |
4020 | 3931 | ||
4021 | intel_dp_print_rates(intel_dp); |
3932 | intel_dp_print_rates(intel_dp); |
4022 | 3933 | ||
4023 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3934 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4024 | DP_DWN_STRM_PORT_PRESENT)) |
3935 | DP_DWN_STRM_PORT_PRESENT)) |
4025 | return true; /* native DP sink */ |
3936 | return true; /* native DP sink */ |
4026 | 3937 | ||
4027 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
3938 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
4028 | return true; /* no per-port downstream info */ |
3939 | return true; /* no per-port downstream info */ |
4029 | 3940 | ||
4030 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3941 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
4031 | intel_dp->downstream_ports, |
3942 | intel_dp->downstream_ports, |
4032 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
3943 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
4033 | return false; /* downstream port status fetch failed */ |
3944 | return false; /* downstream port status fetch failed */ |
4034 | 3945 | ||
4035 | return true; |
3946 | return true; |
4036 | } |
3947 | } |
4037 | 3948 | ||
4038 | static void |
3949 | static void |
4039 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
3950 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
4040 | { |
3951 | { |
4041 | u8 buf[3]; |
3952 | u8 buf[3]; |
4042 | 3953 | ||
4043 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3954 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
4044 | return; |
3955 | return; |
4045 | 3956 | ||
4046 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
3957 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
4047 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3958 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
4048 | buf[0], buf[1], buf[2]); |
3959 | buf[0], buf[1], buf[2]); |
4049 | 3960 | ||
4050 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
3961 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
4051 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3962 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
4052 | buf[0], buf[1], buf[2]); |
3963 | buf[0], buf[1], buf[2]); |
4053 | } |
3964 | } |
4054 | 3965 | ||
4055 | static bool |
3966 | static bool |
4056 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
3967 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
4057 | { |
3968 | { |
4058 | u8 buf[1]; |
3969 | u8 buf[1]; |
4059 | 3970 | ||
4060 | if (!intel_dp->can_mst) |
3971 | if (!intel_dp->can_mst) |
4061 | return false; |
3972 | return false; |
4062 | 3973 | ||
4063 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
3974 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
4064 | return false; |
3975 | return false; |
4065 | 3976 | ||
4066 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3977 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
4067 | if (buf[0] & DP_MST_CAP) { |
3978 | if (buf[0] & DP_MST_CAP) { |
4068 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
3979 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
4069 | intel_dp->is_mst = true; |
3980 | intel_dp->is_mst = true; |
4070 | } else { |
3981 | } else { |
4071 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
3982 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
4072 | intel_dp->is_mst = false; |
3983 | intel_dp->is_mst = false; |
4073 | } |
3984 | } |
4074 | } |
3985 | } |
4075 | 3986 | ||
4076 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
3987 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4077 | return intel_dp->is_mst; |
3988 | return intel_dp->is_mst; |
4078 | } |
3989 | } |
4079 | 3990 | ||
4080 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
3991 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
4081 | { |
3992 | { |
4082 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3993 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | 3994 | struct drm_device *dev = dig_port->base.base.dev; |
|
4083 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3995 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4084 | u8 buf; |
3996 | u8 buf; |
4085 | int ret = 0; |
3997 | int ret = 0; |
- | 3998 | int count = 0; |
|
- | 3999 | int attempts = 10; |
|
4086 | 4000 | ||
4087 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4001 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4088 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4002 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4089 | ret = -EIO; |
4003 | ret = -EIO; |
4090 | goto out; |
4004 | goto out; |
4091 | } |
4005 | } |
4092 | 4006 | ||
4093 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4007 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4094 | buf & ~DP_TEST_SINK_START) < 0) { |
4008 | buf & ~DP_TEST_SINK_START) < 0) { |
4095 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4009 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4096 | ret = -EIO; |
4010 | ret = -EIO; |
4097 | goto out; |
4011 | goto out; |
4098 | } |
4012 | } |
- | 4013 | ||
4099 | 4014 | do { |
|
- | 4015 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 4016 | ||
- | 4017 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
|
- | 4018 | DP_TEST_SINK_MISC, &buf) < 0) { |
|
- | 4019 | ret = -EIO; |
|
- | 4020 | goto out; |
|
- | 4021 | } |
|
- | 4022 | count = buf & DP_TEST_COUNT_MASK; |
|
- | 4023 | } while (--attempts && count); |
|
- | 4024 | ||
- | 4025 | if (attempts == 0) { |
|
- | 4026 | DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n"); |
|
- | 4027 | ret = -ETIMEDOUT; |
|
- | 4028 | } |
|
4100 | intel_dp->sink_crc.started = false; |
4029 | |
4101 | out: |
4030 | out: |
4102 | hsw_enable_ips(intel_crtc); |
4031 | hsw_enable_ips(intel_crtc); |
4103 | return ret; |
4032 | return ret; |
4104 | } |
4033 | } |
4105 | 4034 | ||
4106 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4035 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4107 | { |
4036 | { |
4108 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4037 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | 4038 | struct drm_device *dev = dig_port->base.base.dev; |
|
4109 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4039 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4110 | u8 buf; |
4040 | u8 buf; |
4111 | int ret; |
4041 | int ret; |
4112 | - | ||
4113 | if (intel_dp->sink_crc.started) { |
- | |
4114 | ret = intel_dp_sink_crc_stop(intel_dp); |
- | |
4115 | if (ret) |
- | |
4116 | return ret; |
- | |
4117 | } |
- | |
4118 | 4042 | ||
4119 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4043 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4120 | return -EIO; |
4044 | return -EIO; |
4121 | 4045 | ||
4122 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4046 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4123 | return -ENOTTY; |
4047 | return -ENOTTY; |
4124 | - | ||
4125 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
- | |
4126 | 4048 | ||
4127 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4049 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4128 | return -EIO; |
4050 | return -EIO; |
- | 4051 | ||
- | 4052 | if (buf & DP_TEST_SINK_START) { |
|
- | 4053 | ret = intel_dp_sink_crc_stop(intel_dp); |
|
- | 4054 | if (ret) |
|
- | 4055 | return ret; |
|
- | 4056 | } |
|
4129 | 4057 | ||
4130 | hsw_disable_ips(intel_crtc); |
4058 | hsw_disable_ips(intel_crtc); |
4131 | 4059 | ||
4132 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4060 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4133 | buf | DP_TEST_SINK_START) < 0) { |
4061 | buf | DP_TEST_SINK_START) < 0) { |
4134 | hsw_enable_ips(intel_crtc); |
4062 | hsw_enable_ips(intel_crtc); |
4135 | return -EIO; |
4063 | return -EIO; |
4136 | } |
4064 | } |
4137 | 4065 | ||
4138 | intel_dp->sink_crc.started = true; |
4066 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4139 | return 0; |
4067 | return 0; |
4140 | } |
4068 | } |
4141 | 4069 | ||
4142 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4070 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4143 | { |
4071 | { |
4144 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4072 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4145 | struct drm_device *dev = dig_port->base.base.dev; |
4073 | struct drm_device *dev = dig_port->base.base.dev; |
4146 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4074 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4147 | u8 buf; |
4075 | u8 buf; |
4148 | int count, ret; |
4076 | int count, ret; |
4149 | int attempts = 6; |
4077 | int attempts = 6; |
4150 | bool old_equal_new; |
- | |
4151 | 4078 | ||
4152 | ret = intel_dp_sink_crc_start(intel_dp); |
4079 | ret = intel_dp_sink_crc_start(intel_dp); |
4153 | if (ret) |
4080 | if (ret) |
4154 | return ret; |
4081 | return ret; |
4155 | 4082 | ||
4156 | do { |
4083 | do { |
4157 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4084 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4158 | 4085 | ||
4159 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4086 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4160 | DP_TEST_SINK_MISC, &buf) < 0) { |
4087 | DP_TEST_SINK_MISC, &buf) < 0) { |
4161 | ret = -EIO; |
4088 | ret = -EIO; |
4162 | goto stop; |
4089 | goto stop; |
4163 | } |
4090 | } |
4164 | count = buf & DP_TEST_COUNT_MASK; |
4091 | count = buf & DP_TEST_COUNT_MASK; |
4165 | - | ||
4166 | /* |
- | |
4167 | * Count might be reset during the loop. In this case |
- | |
4168 | * last known count needs to be reset as well. |
- | |
4169 | */ |
- | |
4170 | if (count == 0) |
- | |
4171 | intel_dp->sink_crc.last_count = 0; |
- | |
4172 | - | ||
4173 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
- | |
4174 | ret = -EIO; |
- | |
4175 | goto stop; |
- | |
4176 | } |
- | |
4177 | - | ||
4178 | old_equal_new = (count == intel_dp->sink_crc.last_count && |
- | |
4179 | !memcmp(intel_dp->sink_crc.last_crc, crc, |
- | |
4180 | 6 * sizeof(u8))); |
- | |
4181 | 4092 | ||
4182 | } while (--attempts && (count == 0 || old_equal_new)); |
- | |
4183 | - | ||
4184 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
- | |
4185 | memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8)); |
4093 | } while (--attempts && count == 0); |
4186 | - | ||
4187 | if (attempts == 0) { |
- | |
4188 | if (old_equal_new) { |
- | |
4189 | DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n"); |
4094 | |
4190 | } else { |
4095 | if (attempts == 0) { |
4191 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4096 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4192 | ret = -ETIMEDOUT; |
4097 | ret = -ETIMEDOUT; |
4193 | goto stop; |
4098 | goto stop; |
4194 | } |
4099 | } |
- | 4100 | ||
- | 4101 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
|
- | 4102 | ret = -EIO; |
|
- | 4103 | goto stop; |
|
4195 | } |
4104 | } |
4196 | 4105 | ||
4197 | stop: |
4106 | stop: |
4198 | intel_dp_sink_crc_stop(intel_dp); |
4107 | intel_dp_sink_crc_stop(intel_dp); |
4199 | return ret; |
4108 | return ret; |
4200 | } |
4109 | } |
4201 | 4110 | ||
4202 | static bool |
4111 | static bool |
4203 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4112 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4204 | { |
4113 | { |
4205 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4114 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4206 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4115 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4207 | sink_irq_vector, 1) == 1; |
4116 | sink_irq_vector, 1) == 1; |
4208 | } |
4117 | } |
4209 | 4118 | ||
4210 | static bool |
4119 | static bool |
4211 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4120 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4212 | { |
4121 | { |
4213 | int ret; |
4122 | int ret; |
4214 | 4123 | ||
4215 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4124 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4216 | DP_SINK_COUNT_ESI, |
4125 | DP_SINK_COUNT_ESI, |
4217 | sink_irq_vector, 14); |
4126 | sink_irq_vector, 14); |
4218 | if (ret != 14) |
4127 | if (ret != 14) |
4219 | return false; |
4128 | return false; |
4220 | 4129 | ||
4221 | return true; |
4130 | return true; |
4222 | } |
4131 | } |
4223 | 4132 | ||
4224 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4133 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4225 | { |
4134 | { |
4226 | uint8_t test_result = DP_TEST_ACK; |
4135 | uint8_t test_result = DP_TEST_ACK; |
4227 | return test_result; |
4136 | return test_result; |
4228 | } |
4137 | } |
4229 | 4138 | ||
4230 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4139 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4231 | { |
4140 | { |
4232 | uint8_t test_result = DP_TEST_NAK; |
4141 | uint8_t test_result = DP_TEST_NAK; |
4233 | return test_result; |
4142 | return test_result; |
4234 | } |
4143 | } |
4235 | 4144 | ||
4236 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4145 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4237 | { |
4146 | { |
4238 | uint8_t test_result = DP_TEST_NAK; |
4147 | uint8_t test_result = DP_TEST_NAK; |
4239 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4148 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4240 | struct drm_connector *connector = &intel_connector->base; |
4149 | struct drm_connector *connector = &intel_connector->base; |
4241 | 4150 | ||
4242 | if (intel_connector->detect_edid == NULL || |
4151 | if (intel_connector->detect_edid == NULL || |
4243 | connector->edid_corrupt || |
4152 | connector->edid_corrupt || |
4244 | intel_dp->aux.i2c_defer_count > 6) { |
4153 | intel_dp->aux.i2c_defer_count > 6) { |
4245 | /* Check EDID read for NACKs, DEFERs and corruption |
4154 | /* Check EDID read for NACKs, DEFERs and corruption |
4246 | * (DP CTS 1.2 Core r1.1) |
4155 | * (DP CTS 1.2 Core r1.1) |
4247 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4156 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4248 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4157 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4249 | * 4.2.2.6 : EDID corruption detected |
4158 | * 4.2.2.6 : EDID corruption detected |
4250 | * Use failsafe mode for all cases |
4159 | * Use failsafe mode for all cases |
4251 | */ |
4160 | */ |
4252 | if (intel_dp->aux.i2c_nack_count > 0 || |
4161 | if (intel_dp->aux.i2c_nack_count > 0 || |
4253 | intel_dp->aux.i2c_defer_count > 0) |
4162 | intel_dp->aux.i2c_defer_count > 0) |
4254 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4163 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4255 | intel_dp->aux.i2c_nack_count, |
4164 | intel_dp->aux.i2c_nack_count, |
4256 | intel_dp->aux.i2c_defer_count); |
4165 | intel_dp->aux.i2c_defer_count); |
4257 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4166 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4258 | } else { |
4167 | } else { |
4259 | struct edid *block = intel_connector->detect_edid; |
4168 | struct edid *block = intel_connector->detect_edid; |
4260 | 4169 | ||
4261 | /* We have to write the checksum |
4170 | /* We have to write the checksum |
4262 | * of the last block read |
4171 | * of the last block read |
4263 | */ |
4172 | */ |
4264 | block += intel_connector->detect_edid->extensions; |
4173 | block += intel_connector->detect_edid->extensions; |
4265 | 4174 | ||
4266 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4175 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4267 | DP_TEST_EDID_CHECKSUM, |
4176 | DP_TEST_EDID_CHECKSUM, |
4268 | &block->checksum, |
4177 | &block->checksum, |
4269 | 1)) |
4178 | 1)) |
4270 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4179 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4271 | 4180 | ||
4272 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4181 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4273 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4182 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4274 | } |
4183 | } |
4275 | 4184 | ||
4276 | /* Set test active flag here so userspace doesn't interrupt things */ |
4185 | /* Set test active flag here so userspace doesn't interrupt things */ |
4277 | intel_dp->compliance_test_active = 1; |
4186 | intel_dp->compliance_test_active = 1; |
4278 | 4187 | ||
4279 | return test_result; |
4188 | return test_result; |
4280 | } |
4189 | } |
4281 | 4190 | ||
4282 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4191 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4283 | { |
4192 | { |
4284 | uint8_t test_result = DP_TEST_NAK; |
4193 | uint8_t test_result = DP_TEST_NAK; |
4285 | return test_result; |
4194 | return test_result; |
4286 | } |
4195 | } |
4287 | 4196 | ||
4288 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4197 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4289 | { |
4198 | { |
4290 | uint8_t response = DP_TEST_NAK; |
4199 | uint8_t response = DP_TEST_NAK; |
4291 | uint8_t rxdata = 0; |
4200 | uint8_t rxdata = 0; |
4292 | int status = 0; |
4201 | int status = 0; |
4293 | - | ||
4294 | intel_dp->compliance_test_active = 0; |
- | |
4295 | intel_dp->compliance_test_type = 0; |
- | |
4296 | intel_dp->compliance_test_data = 0; |
- | |
4297 | - | ||
4298 | intel_dp->aux.i2c_nack_count = 0; |
- | |
4299 | intel_dp->aux.i2c_defer_count = 0; |
- | |
4300 | 4202 | ||
4301 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4203 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4302 | if (status <= 0) { |
4204 | if (status <= 0) { |
4303 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4205 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4304 | goto update_status; |
4206 | goto update_status; |
4305 | } |
4207 | } |
4306 | 4208 | ||
4307 | switch (rxdata) { |
4209 | switch (rxdata) { |
4308 | case DP_TEST_LINK_TRAINING: |
4210 | case DP_TEST_LINK_TRAINING: |
4309 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4211 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4310 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4212 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4311 | response = intel_dp_autotest_link_training(intel_dp); |
4213 | response = intel_dp_autotest_link_training(intel_dp); |
4312 | break; |
4214 | break; |
4313 | case DP_TEST_LINK_VIDEO_PATTERN: |
4215 | case DP_TEST_LINK_VIDEO_PATTERN: |
4314 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4216 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4315 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4217 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4316 | response = intel_dp_autotest_video_pattern(intel_dp); |
4218 | response = intel_dp_autotest_video_pattern(intel_dp); |
4317 | break; |
4219 | break; |
4318 | case DP_TEST_LINK_EDID_READ: |
4220 | case DP_TEST_LINK_EDID_READ: |
4319 | DRM_DEBUG_KMS("EDID test requested\n"); |
4221 | DRM_DEBUG_KMS("EDID test requested\n"); |
4320 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4222 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4321 | response = intel_dp_autotest_edid(intel_dp); |
4223 | response = intel_dp_autotest_edid(intel_dp); |
4322 | break; |
4224 | break; |
4323 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4225 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4324 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4226 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4325 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4227 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4326 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4228 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4327 | break; |
4229 | break; |
4328 | default: |
4230 | default: |
4329 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4231 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4330 | break; |
4232 | break; |
4331 | } |
4233 | } |
4332 | 4234 | ||
4333 | update_status: |
4235 | update_status: |
4334 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4236 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4335 | DP_TEST_RESPONSE, |
4237 | DP_TEST_RESPONSE, |
4336 | &response, 1); |
4238 | &response, 1); |
4337 | if (status <= 0) |
4239 | if (status <= 0) |
4338 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4240 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4339 | } |
4241 | } |
4340 | 4242 | ||
4341 | static int |
4243 | static int |
4342 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4244 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4343 | { |
4245 | { |
4344 | bool bret; |
4246 | bool bret; |
4345 | 4247 | ||
4346 | if (intel_dp->is_mst) { |
4248 | if (intel_dp->is_mst) { |
4347 | u8 esi[16] = { 0 }; |
4249 | u8 esi[16] = { 0 }; |
4348 | int ret = 0; |
4250 | int ret = 0; |
4349 | int retry; |
4251 | int retry; |
4350 | bool handled; |
4252 | bool handled; |
4351 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4253 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4352 | go_again: |
4254 | go_again: |
4353 | if (bret == true) { |
4255 | if (bret == true) { |
4354 | 4256 | ||
4355 | /* check link status - esi[10] = 0x200c */ |
4257 | /* check link status - esi[10] = 0x200c */ |
4356 | if (intel_dp->active_mst_links && |
4258 | if (intel_dp->active_mst_links && |
4357 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4259 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4358 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4260 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4359 | intel_dp_start_link_train(intel_dp); |
4261 | intel_dp_start_link_train(intel_dp); |
4360 | intel_dp_stop_link_train(intel_dp); |
4262 | intel_dp_stop_link_train(intel_dp); |
4361 | } |
4263 | } |
4362 | 4264 | ||
4363 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4265 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4364 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4266 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4365 | 4267 | ||
4366 | if (handled) { |
4268 | if (handled) { |
4367 | for (retry = 0; retry < 3; retry++) { |
4269 | for (retry = 0; retry < 3; retry++) { |
4368 | int wret; |
4270 | int wret; |
4369 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4271 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4370 | DP_SINK_COUNT_ESI+1, |
4272 | DP_SINK_COUNT_ESI+1, |
4371 | &esi[1], 3); |
4273 | &esi[1], 3); |
4372 | if (wret == 3) { |
4274 | if (wret == 3) { |
4373 | break; |
4275 | break; |
4374 | } |
4276 | } |
4375 | } |
4277 | } |
4376 | 4278 | ||
4377 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4279 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4378 | if (bret == true) { |
4280 | if (bret == true) { |
4379 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4281 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4380 | goto go_again; |
4282 | goto go_again; |
4381 | } |
4283 | } |
4382 | } else |
4284 | } else |
4383 | ret = 0; |
4285 | ret = 0; |
4384 | 4286 | ||
4385 | return ret; |
4287 | return ret; |
4386 | } else { |
4288 | } else { |
4387 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4388 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4290 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4389 | intel_dp->is_mst = false; |
4291 | intel_dp->is_mst = false; |
4390 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4292 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4391 | /* send a hotplug event */ |
4293 | /* send a hotplug event */ |
4392 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4294 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4393 | } |
4295 | } |
4394 | } |
4296 | } |
4395 | return -EINVAL; |
4297 | return -EINVAL; |
4396 | } |
4298 | } |
4397 | 4299 | ||
4398 | /* |
4300 | /* |
4399 | * According to DP spec |
4301 | * According to DP spec |
4400 | * 5.1.2: |
4302 | * 5.1.2: |
4401 | * 1. Read DPCD |
4303 | * 1. Read DPCD |
4402 | * 2. Configure link according to Receiver Capabilities |
4304 | * 2. Configure link according to Receiver Capabilities |
4403 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4305 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4404 | * 4. Check link status on receipt of hot-plug interrupt |
4306 | * 4. Check link status on receipt of hot-plug interrupt |
4405 | */ |
4307 | */ |
4406 | static void |
4308 | static void |
4407 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4309 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4408 | { |
4310 | { |
4409 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4311 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4410 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4312 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4411 | u8 sink_irq_vector; |
4313 | u8 sink_irq_vector; |
4412 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4314 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4413 | 4315 | ||
4414 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4316 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
- | 4317 | ||
- | 4318 | /* |
|
- | 4319 | * Clearing compliance test variables to allow capturing |
|
- | 4320 | * of values for next automated test request. |
|
- | 4321 | */ |
|
- | 4322 | intel_dp->compliance_test_active = 0; |
|
- | 4323 | intel_dp->compliance_test_type = 0; |
|
- | 4324 | intel_dp->compliance_test_data = 0; |
|
4415 | 4325 | ||
4416 | if (!intel_encoder->base.crtc) |
4326 | if (!intel_encoder->base.crtc) |
4417 | return; |
4327 | return; |
4418 | 4328 | ||
4419 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4329 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4420 | return; |
4330 | return; |
4421 | 4331 | ||
4422 | /* Try to read receiver status if the link appears to be up */ |
4332 | /* Try to read receiver status if the link appears to be up */ |
4423 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4333 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4424 | return; |
4334 | return; |
4425 | } |
4335 | } |
4426 | 4336 | ||
4427 | /* Now read the DPCD to see if it's actually running */ |
4337 | /* Now read the DPCD to see if it's actually running */ |
4428 | if (!intel_dp_get_dpcd(intel_dp)) { |
4338 | if (!intel_dp_get_dpcd(intel_dp)) { |
4429 | return; |
4339 | return; |
4430 | } |
4340 | } |
4431 | 4341 | ||
4432 | /* Try to read the source of the interrupt */ |
4342 | /* Try to read the source of the interrupt */ |
4433 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4343 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4434 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4344 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4435 | /* Clear interrupt source */ |
4345 | /* Clear interrupt source */ |
4436 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4346 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4437 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4347 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4438 | sink_irq_vector); |
4348 | sink_irq_vector); |
4439 | 4349 | ||
4440 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4350 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4441 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4351 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4442 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4352 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4443 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4353 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4444 | } |
4354 | } |
- | 4355 | ||
- | 4356 | /* if link training is requested we should perform it always */ |
|
4445 | 4357 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
|
4446 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
4358 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
4447 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4359 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4448 | intel_encoder->base.name); |
4360 | intel_encoder->base.name); |
4449 | intel_dp_start_link_train(intel_dp); |
4361 | intel_dp_start_link_train(intel_dp); |
4450 | intel_dp_stop_link_train(intel_dp); |
4362 | intel_dp_stop_link_train(intel_dp); |
4451 | } |
4363 | } |
4452 | } |
4364 | } |
4453 | 4365 | ||
4454 | /* XXX this is probably wrong for multiple downstream ports */ |
4366 | /* XXX this is probably wrong for multiple downstream ports */ |
4455 | static enum drm_connector_status |
4367 | static enum drm_connector_status |
4456 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4368 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4457 | { |
4369 | { |
4458 | uint8_t *dpcd = intel_dp->dpcd; |
4370 | uint8_t *dpcd = intel_dp->dpcd; |
4459 | uint8_t type; |
4371 | uint8_t type; |
4460 | 4372 | ||
4461 | if (!intel_dp_get_dpcd(intel_dp)) |
4373 | if (!intel_dp_get_dpcd(intel_dp)) |
4462 | return connector_status_disconnected; |
4374 | return connector_status_disconnected; |
4463 | 4375 | ||
4464 | /* if there's no downstream port, we're done */ |
4376 | /* if there's no downstream port, we're done */ |
4465 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4377 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4466 | return connector_status_connected; |
4378 | return connector_status_connected; |
4467 | 4379 | ||
4468 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4380 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4469 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4381 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4470 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4382 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4471 | uint8_t reg; |
4383 | uint8_t reg; |
4472 | 4384 | ||
4473 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4385 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4474 | ®, 1) < 0) |
4386 | ®, 1) < 0) |
4475 | return connector_status_unknown; |
4387 | return connector_status_unknown; |
4476 | 4388 | ||
4477 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4389 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4478 | : connector_status_disconnected; |
4390 | : connector_status_disconnected; |
4479 | } |
4391 | } |
4480 | 4392 | ||
4481 | /* If no HPD, poke DDC gently */ |
4393 | /* If no HPD, poke DDC gently */ |
4482 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4394 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4483 | return connector_status_connected; |
4395 | return connector_status_connected; |
4484 | 4396 | ||
4485 | /* Well we tried, say unknown for unreliable port types */ |
4397 | /* Well we tried, say unknown for unreliable port types */ |
4486 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4398 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4487 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4399 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4488 | if (type == DP_DS_PORT_TYPE_VGA || |
4400 | if (type == DP_DS_PORT_TYPE_VGA || |
4489 | type == DP_DS_PORT_TYPE_NON_EDID) |
4401 | type == DP_DS_PORT_TYPE_NON_EDID) |
4490 | return connector_status_unknown; |
4402 | return connector_status_unknown; |
4491 | } else { |
4403 | } else { |
4492 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4404 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4493 | DP_DWN_STRM_PORT_TYPE_MASK; |
4405 | DP_DWN_STRM_PORT_TYPE_MASK; |
4494 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4406 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4495 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4407 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4496 | return connector_status_unknown; |
4408 | return connector_status_unknown; |
4497 | } |
4409 | } |
4498 | 4410 | ||
4499 | /* Anything else is out of spec, warn and ignore */ |
4411 | /* Anything else is out of spec, warn and ignore */ |
4500 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4412 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4501 | return connector_status_disconnected; |
4413 | return connector_status_disconnected; |
4502 | } |
4414 | } |
4503 | 4415 | ||
4504 | static enum drm_connector_status |
4416 | static enum drm_connector_status |
4505 | edp_detect(struct intel_dp *intel_dp) |
4417 | edp_detect(struct intel_dp *intel_dp) |
4506 | { |
4418 | { |
4507 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4419 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4508 | enum drm_connector_status status; |
4420 | enum drm_connector_status status; |
4509 | 4421 | ||
4510 | status = intel_panel_detect(dev); |
4422 | status = intel_panel_detect(dev); |
4511 | if (status == connector_status_unknown) |
4423 | if (status == connector_status_unknown) |
4512 | status = connector_status_connected; |
4424 | status = connector_status_connected; |
4513 | 4425 | ||
4514 | return status; |
4426 | return status; |
4515 | } |
4427 | } |
4516 | 4428 | ||
4517 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4429 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4518 | struct intel_digital_port *port) |
4430 | struct intel_digital_port *port) |
4519 | { |
4431 | { |
4520 | u32 bit; |
4432 | u32 bit; |
4521 | 4433 | ||
4522 | switch (port->port) { |
4434 | switch (port->port) { |
4523 | case PORT_A: |
4435 | case PORT_A: |
4524 | return true; |
4436 | return true; |
4525 | case PORT_B: |
4437 | case PORT_B: |
4526 | bit = SDE_PORTB_HOTPLUG; |
4438 | bit = SDE_PORTB_HOTPLUG; |
4527 | break; |
4439 | break; |
4528 | case PORT_C: |
4440 | case PORT_C: |
4529 | bit = SDE_PORTC_HOTPLUG; |
4441 | bit = SDE_PORTC_HOTPLUG; |
4530 | break; |
4442 | break; |
4531 | case PORT_D: |
4443 | case PORT_D: |
4532 | bit = SDE_PORTD_HOTPLUG; |
4444 | bit = SDE_PORTD_HOTPLUG; |
4533 | break; |
4445 | break; |
4534 | default: |
4446 | default: |
4535 | MISSING_CASE(port->port); |
4447 | MISSING_CASE(port->port); |
4536 | return false; |
4448 | return false; |
4537 | } |
4449 | } |
4538 | 4450 | ||
4539 | return I915_READ(SDEISR) & bit; |
4451 | return I915_READ(SDEISR) & bit; |
4540 | } |
4452 | } |
4541 | 4453 | ||
4542 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4454 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4543 | struct intel_digital_port *port) |
4455 | struct intel_digital_port *port) |
4544 | { |
4456 | { |
4545 | u32 bit; |
4457 | u32 bit; |
4546 | 4458 | ||
4547 | switch (port->port) { |
4459 | switch (port->port) { |
4548 | case PORT_A: |
4460 | case PORT_A: |
4549 | return true; |
4461 | return true; |
4550 | case PORT_B: |
4462 | case PORT_B: |
4551 | bit = SDE_PORTB_HOTPLUG_CPT; |
4463 | bit = SDE_PORTB_HOTPLUG_CPT; |
4552 | break; |
4464 | break; |
4553 | case PORT_C: |
4465 | case PORT_C: |
4554 | bit = SDE_PORTC_HOTPLUG_CPT; |
4466 | bit = SDE_PORTC_HOTPLUG_CPT; |
4555 | break; |
4467 | break; |
4556 | case PORT_D: |
4468 | case PORT_D: |
4557 | bit = SDE_PORTD_HOTPLUG_CPT; |
4469 | bit = SDE_PORTD_HOTPLUG_CPT; |
4558 | break; |
4470 | break; |
4559 | case PORT_E: |
4471 | case PORT_E: |
4560 | bit = SDE_PORTE_HOTPLUG_SPT; |
4472 | bit = SDE_PORTE_HOTPLUG_SPT; |
4561 | break; |
4473 | break; |
4562 | default: |
4474 | default: |
4563 | MISSING_CASE(port->port); |
4475 | MISSING_CASE(port->port); |
4564 | return false; |
4476 | return false; |
4565 | } |
4477 | } |
4566 | 4478 | ||
4567 | return I915_READ(SDEISR) & bit; |
4479 | return I915_READ(SDEISR) & bit; |
4568 | } |
4480 | } |
4569 | 4481 | ||
4570 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4482 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4571 | struct intel_digital_port *port) |
4483 | struct intel_digital_port *port) |
4572 | { |
4484 | { |
4573 | u32 bit; |
4485 | u32 bit; |
4574 | 4486 | ||
4575 | switch (port->port) { |
4487 | switch (port->port) { |
4576 | case PORT_B: |
4488 | case PORT_B: |
4577 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4489 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4578 | break; |
4490 | break; |
4579 | case PORT_C: |
4491 | case PORT_C: |
4580 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4492 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4581 | break; |
4493 | break; |
4582 | case PORT_D: |
4494 | case PORT_D: |
4583 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4495 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4584 | break; |
4496 | break; |
4585 | default: |
4497 | default: |
4586 | MISSING_CASE(port->port); |
4498 | MISSING_CASE(port->port); |
4587 | return false; |
4499 | return false; |
4588 | } |
4500 | } |
4589 | 4501 | ||
4590 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4502 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4591 | } |
4503 | } |
4592 | 4504 | ||
4593 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4505 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4594 | struct intel_digital_port *port) |
4506 | struct intel_digital_port *port) |
4595 | { |
4507 | { |
4596 | u32 bit; |
4508 | u32 bit; |
4597 | 4509 | ||
4598 | switch (port->port) { |
4510 | switch (port->port) { |
4599 | case PORT_B: |
4511 | case PORT_B: |
4600 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
4512 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
4601 | break; |
4513 | break; |
4602 | case PORT_C: |
4514 | case PORT_C: |
4603 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
4515 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
4604 | break; |
4516 | break; |
4605 | case PORT_D: |
4517 | case PORT_D: |
4606 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
4518 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
4607 | break; |
4519 | break; |
4608 | default: |
4520 | default: |
4609 | MISSING_CASE(port->port); |
4521 | MISSING_CASE(port->port); |
4610 | return false; |
4522 | return false; |
4611 | } |
4523 | } |
4612 | 4524 | ||
4613 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4525 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4614 | } |
4526 | } |
4615 | 4527 | ||
4616 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4528 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4617 | struct intel_digital_port *intel_dig_port) |
4529 | struct intel_digital_port *intel_dig_port) |
4618 | { |
4530 | { |
4619 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4531 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4620 | enum port port; |
4532 | enum port port; |
4621 | u32 bit; |
4533 | u32 bit; |
4622 | 4534 | ||
4623 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4535 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4624 | switch (port) { |
4536 | switch (port) { |
4625 | case PORT_A: |
4537 | case PORT_A: |
4626 | bit = BXT_DE_PORT_HP_DDIA; |
4538 | bit = BXT_DE_PORT_HP_DDIA; |
4627 | break; |
4539 | break; |
4628 | case PORT_B: |
4540 | case PORT_B: |
4629 | bit = BXT_DE_PORT_HP_DDIB; |
4541 | bit = BXT_DE_PORT_HP_DDIB; |
4630 | break; |
4542 | break; |
4631 | case PORT_C: |
4543 | case PORT_C: |
4632 | bit = BXT_DE_PORT_HP_DDIC; |
4544 | bit = BXT_DE_PORT_HP_DDIC; |
4633 | break; |
4545 | break; |
4634 | default: |
4546 | default: |
4635 | MISSING_CASE(port); |
4547 | MISSING_CASE(port); |
4636 | return false; |
4548 | return false; |
4637 | } |
4549 | } |
4638 | 4550 | ||
4639 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4551 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4640 | } |
4552 | } |
4641 | 4553 | ||
4642 | /* |
4554 | /* |
4643 | * intel_digital_port_connected - is the specified port connected? |
4555 | * intel_digital_port_connected - is the specified port connected? |
4644 | * @dev_priv: i915 private structure |
4556 | * @dev_priv: i915 private structure |
4645 | * @port: the port to test |
4557 | * @port: the port to test |
4646 | * |
4558 | * |
4647 | * Return %true if @port is connected, %false otherwise. |
4559 | * Return %true if @port is connected, %false otherwise. |
4648 | */ |
4560 | */ |
4649 | static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4561 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4650 | struct intel_digital_port *port) |
4562 | struct intel_digital_port *port) |
4651 | { |
4563 | { |
4652 | if (HAS_PCH_IBX(dev_priv)) |
4564 | if (HAS_PCH_IBX(dev_priv)) |
4653 | return ibx_digital_port_connected(dev_priv, port); |
4565 | return ibx_digital_port_connected(dev_priv, port); |
4654 | if (HAS_PCH_SPLIT(dev_priv)) |
4566 | if (HAS_PCH_SPLIT(dev_priv)) |
4655 | return cpt_digital_port_connected(dev_priv, port); |
4567 | return cpt_digital_port_connected(dev_priv, port); |
4656 | else if (IS_BROXTON(dev_priv)) |
4568 | else if (IS_BROXTON(dev_priv)) |
4657 | return bxt_digital_port_connected(dev_priv, port); |
4569 | return bxt_digital_port_connected(dev_priv, port); |
4658 | else if (IS_GM45(dev_priv)) |
4570 | else if (IS_GM45(dev_priv)) |
4659 | return gm45_digital_port_connected(dev_priv, port); |
4571 | return gm45_digital_port_connected(dev_priv, port); |
4660 | else |
4572 | else |
4661 | return g4x_digital_port_connected(dev_priv, port); |
4573 | return g4x_digital_port_connected(dev_priv, port); |
4662 | } |
4574 | } |
4663 | - | ||
4664 | static enum drm_connector_status |
- | |
4665 | ironlake_dp_detect(struct intel_dp *intel_dp) |
- | |
4666 | { |
- | |
4667 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
4668 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4669 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
4670 | - | ||
4671 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
- | |
4672 | return connector_status_disconnected; |
- | |
4673 | - | ||
4674 | return intel_dp_detect_dpcd(intel_dp); |
- | |
4675 | } |
- | |
4676 | - | ||
4677 | static enum drm_connector_status |
- | |
4678 | g4x_dp_detect(struct intel_dp *intel_dp) |
- | |
4679 | { |
- | |
4680 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
4681 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
4682 | - | ||
4683 | /* Can't disconnect eDP, but you can close the lid... */ |
- | |
4684 | if (is_edp(intel_dp)) { |
- | |
4685 | enum drm_connector_status status; |
- | |
4686 | - | ||
4687 | status = intel_panel_detect(dev); |
- | |
4688 | if (status == connector_status_unknown) |
- | |
4689 | status = connector_status_connected; |
- | |
4690 | return status; |
- | |
4691 | } |
- | |
4692 | - | ||
4693 | if (!intel_digital_port_connected(dev->dev_private, intel_dig_port)) |
- | |
4694 | return connector_status_disconnected; |
- | |
4695 | - | ||
4696 | return intel_dp_detect_dpcd(intel_dp); |
- | |
4697 | } |
- | |
4698 | 4575 | ||
4699 | static struct edid * |
4576 | static struct edid * |
4700 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4577 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4701 | { |
4578 | { |
4702 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4579 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4703 | 4580 | ||
4704 | /* use cached edid if we have one */ |
4581 | /* use cached edid if we have one */ |
4705 | if (intel_connector->edid) { |
4582 | if (intel_connector->edid) { |
4706 | /* invalid edid */ |
4583 | /* invalid edid */ |
4707 | if (IS_ERR(intel_connector->edid)) |
4584 | if (IS_ERR(intel_connector->edid)) |
4708 | return NULL; |
4585 | return NULL; |
4709 | 4586 | ||
4710 | return drm_edid_duplicate(intel_connector->edid); |
4587 | return drm_edid_duplicate(intel_connector->edid); |
4711 | } else |
4588 | } else |
4712 | return drm_get_edid(&intel_connector->base, |
4589 | return drm_get_edid(&intel_connector->base, |
4713 | &intel_dp->aux.ddc); |
4590 | &intel_dp->aux.ddc); |
4714 | } |
4591 | } |
4715 | 4592 | ||
4716 | static void |
4593 | static void |
4717 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4594 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4718 | { |
4595 | { |
4719 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4596 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4720 | struct edid *edid; |
4597 | struct edid *edid; |
4721 | 4598 | ||
4722 | edid = intel_dp_get_edid(intel_dp); |
4599 | edid = intel_dp_get_edid(intel_dp); |
4723 | intel_connector->detect_edid = edid; |
4600 | intel_connector->detect_edid = edid; |
4724 | 4601 | ||
4725 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4602 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4726 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4603 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4727 | else |
4604 | else |
4728 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4605 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4729 | } |
4606 | } |
4730 | 4607 | ||
4731 | static void |
4608 | static void |
4732 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4609 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4733 | { |
4610 | { |
4734 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4611 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4735 | 4612 | ||
4736 | kfree(intel_connector->detect_edid); |
4613 | kfree(intel_connector->detect_edid); |
4737 | intel_connector->detect_edid = NULL; |
4614 | intel_connector->detect_edid = NULL; |
4738 | 4615 | ||
4739 | intel_dp->has_audio = false; |
4616 | intel_dp->has_audio = false; |
4740 | } |
4617 | } |
4741 | 4618 | ||
4742 | static enum drm_connector_status |
4619 | static enum drm_connector_status |
4743 | intel_dp_detect(struct drm_connector *connector, bool force) |
4620 | intel_dp_detect(struct drm_connector *connector, bool force) |
4744 | { |
4621 | { |
4745 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4622 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4746 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4623 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4747 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4624 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4748 | struct drm_device *dev = connector->dev; |
4625 | struct drm_device *dev = connector->dev; |
4749 | enum drm_connector_status status; |
4626 | enum drm_connector_status status; |
4750 | enum intel_display_power_domain power_domain; |
4627 | enum intel_display_power_domain power_domain; |
4751 | bool ret; |
4628 | bool ret; |
4752 | u8 sink_irq_vector; |
4629 | u8 sink_irq_vector; |
4753 | 4630 | ||
4754 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4631 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4755 | connector->base.id, connector->name); |
4632 | connector->base.id, connector->name); |
4756 | intel_dp_unset_edid(intel_dp); |
4633 | intel_dp_unset_edid(intel_dp); |
4757 | 4634 | ||
4758 | if (intel_dp->is_mst) { |
4635 | if (intel_dp->is_mst) { |
4759 | /* MST devices are disconnected from a monitor POV */ |
4636 | /* MST devices are disconnected from a monitor POV */ |
4760 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4637 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4761 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4638 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4762 | return connector_status_disconnected; |
4639 | return connector_status_disconnected; |
4763 | } |
4640 | } |
4764 | 4641 | ||
4765 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4642 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4766 | intel_display_power_get(to_i915(dev), power_domain); |
4643 | intel_display_power_get(to_i915(dev), power_domain); |
4767 | 4644 | ||
4768 | /* Can't disconnect eDP, but you can close the lid... */ |
4645 | /* Can't disconnect eDP, but you can close the lid... */ |
4769 | if (is_edp(intel_dp)) |
4646 | if (is_edp(intel_dp)) |
4770 | status = edp_detect(intel_dp); |
4647 | status = edp_detect(intel_dp); |
4771 | else if (HAS_PCH_SPLIT(dev)) |
4648 | else if (intel_digital_port_connected(to_i915(dev), |
- | 4649 | dp_to_dig_port(intel_dp))) |
|
4772 | status = ironlake_dp_detect(intel_dp); |
4650 | status = intel_dp_detect_dpcd(intel_dp); |
4773 | else |
4651 | else |
4774 | status = g4x_dp_detect(intel_dp); |
4652 | status = connector_status_disconnected; |
- | 4653 | ||
4775 | if (status != connector_status_connected) |
4654 | if (status != connector_status_connected) { |
- | 4655 | intel_dp->compliance_test_active = 0; |
|
- | 4656 | intel_dp->compliance_test_type = 0; |
|
- | 4657 | intel_dp->compliance_test_data = 0; |
|
- | 4658 | ||
4776 | goto out; |
4659 | goto out; |
- | 4660 | } |
|
4777 | 4661 | ||
4778 | intel_dp_probe_oui(intel_dp); |
4662 | intel_dp_probe_oui(intel_dp); |
4779 | 4663 | ||
4780 | ret = intel_dp_probe_mst(intel_dp); |
4664 | ret = intel_dp_probe_mst(intel_dp); |
4781 | if (ret) { |
4665 | if (ret) { |
4782 | /* if we are in MST mode then this connector |
4666 | /* if we are in MST mode then this connector |
4783 | won't appear connected or have anything with EDID on it */ |
4667 | won't appear connected or have anything with EDID on it */ |
4784 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4668 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4785 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4669 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4786 | status = connector_status_disconnected; |
4670 | status = connector_status_disconnected; |
4787 | goto out; |
4671 | goto out; |
4788 | } |
4672 | } |
- | 4673 | ||
- | 4674 | /* |
|
- | 4675 | * Clearing NACK and defer counts to get their exact values |
|
- | 4676 | * while reading EDID which are required by Compliance tests |
|
- | 4677 | * 4.2.2.4 and 4.2.2.5 |
|
- | 4678 | */ |
|
- | 4679 | intel_dp->aux.i2c_nack_count = 0; |
|
- | 4680 | intel_dp->aux.i2c_defer_count = 0; |
|
4789 | 4681 | ||
4790 | intel_dp_set_edid(intel_dp); |
4682 | intel_dp_set_edid(intel_dp); |
4791 | 4683 | ||
4792 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4684 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4793 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4685 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4794 | status = connector_status_connected; |
4686 | status = connector_status_connected; |
4795 | 4687 | ||
4796 | /* Try to read the source of the interrupt */ |
4688 | /* Try to read the source of the interrupt */ |
4797 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4689 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4798 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4690 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4799 | /* Clear interrupt source */ |
4691 | /* Clear interrupt source */ |
4800 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4692 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4801 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4693 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4802 | sink_irq_vector); |
4694 | sink_irq_vector); |
4803 | 4695 | ||
4804 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4696 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4805 | intel_dp_handle_test_request(intel_dp); |
4697 | intel_dp_handle_test_request(intel_dp); |
4806 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4698 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4807 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4699 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4808 | } |
4700 | } |
4809 | 4701 | ||
4810 | out: |
4702 | out: |
4811 | intel_display_power_put(to_i915(dev), power_domain); |
4703 | intel_display_power_put(to_i915(dev), power_domain); |
4812 | return status; |
4704 | return status; |
4813 | } |
4705 | } |
4814 | 4706 | ||
4815 | static void |
4707 | static void |
4816 | intel_dp_force(struct drm_connector *connector) |
4708 | intel_dp_force(struct drm_connector *connector) |
4817 | { |
4709 | { |
4818 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4710 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4819 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4711 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4820 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4712 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4821 | enum intel_display_power_domain power_domain; |
4713 | enum intel_display_power_domain power_domain; |
4822 | 4714 | ||
4823 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4715 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4824 | connector->base.id, connector->name); |
4716 | connector->base.id, connector->name); |
4825 | intel_dp_unset_edid(intel_dp); |
4717 | intel_dp_unset_edid(intel_dp); |
4826 | 4718 | ||
4827 | if (connector->status != connector_status_connected) |
4719 | if (connector->status != connector_status_connected) |
4828 | return; |
4720 | return; |
4829 | 4721 | ||
4830 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4722 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4831 | intel_display_power_get(dev_priv, power_domain); |
4723 | intel_display_power_get(dev_priv, power_domain); |
4832 | 4724 | ||
4833 | intel_dp_set_edid(intel_dp); |
4725 | intel_dp_set_edid(intel_dp); |
4834 | 4726 | ||
4835 | intel_display_power_put(dev_priv, power_domain); |
4727 | intel_display_power_put(dev_priv, power_domain); |
4836 | 4728 | ||
4837 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4729 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4838 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4730 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4839 | } |
4731 | } |
4840 | 4732 | ||
4841 | static int intel_dp_get_modes(struct drm_connector *connector) |
4733 | static int intel_dp_get_modes(struct drm_connector *connector) |
4842 | { |
4734 | { |
4843 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4735 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4844 | struct edid *edid; |
4736 | struct edid *edid; |
4845 | 4737 | ||
4846 | edid = intel_connector->detect_edid; |
4738 | edid = intel_connector->detect_edid; |
4847 | if (edid) { |
4739 | if (edid) { |
4848 | int ret = intel_connector_update_modes(connector, edid); |
4740 | int ret = intel_connector_update_modes(connector, edid); |
4849 | if (ret) |
4741 | if (ret) |
4850 | return ret; |
4742 | return ret; |
4851 | } |
4743 | } |
4852 | 4744 | ||
4853 | /* if eDP has no EDID, fall back to fixed mode */ |
4745 | /* if eDP has no EDID, fall back to fixed mode */ |
4854 | if (is_edp(intel_attached_dp(connector)) && |
4746 | if (is_edp(intel_attached_dp(connector)) && |
4855 | intel_connector->panel.fixed_mode) { |
4747 | intel_connector->panel.fixed_mode) { |
4856 | struct drm_display_mode *mode; |
4748 | struct drm_display_mode *mode; |
4857 | 4749 | ||
4858 | mode = drm_mode_duplicate(connector->dev, |
4750 | mode = drm_mode_duplicate(connector->dev, |
4859 | intel_connector->panel.fixed_mode); |
4751 | intel_connector->panel.fixed_mode); |
4860 | if (mode) { |
4752 | if (mode) { |
4861 | drm_mode_probed_add(connector, mode); |
4753 | drm_mode_probed_add(connector, mode); |
4862 | return 1; |
4754 | return 1; |
4863 | } |
4755 | } |
4864 | } |
4756 | } |
4865 | 4757 | ||
4866 | return 0; |
4758 | return 0; |
4867 | } |
4759 | } |
4868 | 4760 | ||
4869 | static bool |
4761 | static bool |
4870 | intel_dp_detect_audio(struct drm_connector *connector) |
4762 | intel_dp_detect_audio(struct drm_connector *connector) |
4871 | { |
4763 | { |
4872 | bool has_audio = false; |
4764 | bool has_audio = false; |
4873 | struct edid *edid; |
4765 | struct edid *edid; |
4874 | 4766 | ||
4875 | edid = to_intel_connector(connector)->detect_edid; |
4767 | edid = to_intel_connector(connector)->detect_edid; |
4876 | if (edid) |
4768 | if (edid) |
4877 | has_audio = drm_detect_monitor_audio(edid); |
4769 | has_audio = drm_detect_monitor_audio(edid); |
4878 | 4770 | ||
4879 | return has_audio; |
4771 | return has_audio; |
4880 | } |
4772 | } |
4881 | 4773 | ||
4882 | static int |
4774 | static int |
4883 | intel_dp_set_property(struct drm_connector *connector, |
4775 | intel_dp_set_property(struct drm_connector *connector, |
4884 | struct drm_property *property, |
4776 | struct drm_property *property, |
4885 | uint64_t val) |
4777 | uint64_t val) |
4886 | { |
4778 | { |
4887 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4779 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4888 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4780 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4889 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4781 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4890 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4782 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4891 | int ret; |
4783 | int ret; |
4892 | 4784 | ||
4893 | ret = drm_object_property_set_value(&connector->base, property, val); |
4785 | ret = drm_object_property_set_value(&connector->base, property, val); |
4894 | if (ret) |
4786 | if (ret) |
4895 | return ret; |
4787 | return ret; |
4896 | 4788 | ||
4897 | if (property == dev_priv->force_audio_property) { |
4789 | if (property == dev_priv->force_audio_property) { |
4898 | int i = val; |
4790 | int i = val; |
4899 | bool has_audio; |
4791 | bool has_audio; |
4900 | 4792 | ||
4901 | if (i == intel_dp->force_audio) |
4793 | if (i == intel_dp->force_audio) |
4902 | return 0; |
4794 | return 0; |
4903 | 4795 | ||
4904 | intel_dp->force_audio = i; |
4796 | intel_dp->force_audio = i; |
4905 | 4797 | ||
4906 | if (i == HDMI_AUDIO_AUTO) |
4798 | if (i == HDMI_AUDIO_AUTO) |
4907 | has_audio = intel_dp_detect_audio(connector); |
4799 | has_audio = intel_dp_detect_audio(connector); |
4908 | else |
4800 | else |
4909 | has_audio = (i == HDMI_AUDIO_ON); |
4801 | has_audio = (i == HDMI_AUDIO_ON); |
4910 | 4802 | ||
4911 | if (has_audio == intel_dp->has_audio) |
4803 | if (has_audio == intel_dp->has_audio) |
4912 | return 0; |
4804 | return 0; |
4913 | 4805 | ||
4914 | intel_dp->has_audio = has_audio; |
4806 | intel_dp->has_audio = has_audio; |
4915 | goto done; |
4807 | goto done; |
4916 | } |
4808 | } |
4917 | 4809 | ||
4918 | if (property == dev_priv->broadcast_rgb_property) { |
4810 | if (property == dev_priv->broadcast_rgb_property) { |
4919 | bool old_auto = intel_dp->color_range_auto; |
4811 | bool old_auto = intel_dp->color_range_auto; |
4920 | bool old_range = intel_dp->limited_color_range; |
4812 | bool old_range = intel_dp->limited_color_range; |
4921 | 4813 | ||
4922 | switch (val) { |
4814 | switch (val) { |
4923 | case INTEL_BROADCAST_RGB_AUTO: |
4815 | case INTEL_BROADCAST_RGB_AUTO: |
4924 | intel_dp->color_range_auto = true; |
4816 | intel_dp->color_range_auto = true; |
4925 | break; |
4817 | break; |
4926 | case INTEL_BROADCAST_RGB_FULL: |
4818 | case INTEL_BROADCAST_RGB_FULL: |
4927 | intel_dp->color_range_auto = false; |
4819 | intel_dp->color_range_auto = false; |
4928 | intel_dp->limited_color_range = false; |
4820 | intel_dp->limited_color_range = false; |
4929 | break; |
4821 | break; |
4930 | case INTEL_BROADCAST_RGB_LIMITED: |
4822 | case INTEL_BROADCAST_RGB_LIMITED: |
4931 | intel_dp->color_range_auto = false; |
4823 | intel_dp->color_range_auto = false; |
4932 | intel_dp->limited_color_range = true; |
4824 | intel_dp->limited_color_range = true; |
4933 | break; |
4825 | break; |
4934 | default: |
4826 | default: |
4935 | return -EINVAL; |
4827 | return -EINVAL; |
4936 | } |
4828 | } |
4937 | 4829 | ||
4938 | if (old_auto == intel_dp->color_range_auto && |
4830 | if (old_auto == intel_dp->color_range_auto && |
4939 | old_range == intel_dp->limited_color_range) |
4831 | old_range == intel_dp->limited_color_range) |
4940 | return 0; |
4832 | return 0; |
4941 | 4833 | ||
4942 | goto done; |
4834 | goto done; |
4943 | } |
4835 | } |
4944 | 4836 | ||
4945 | if (is_edp(intel_dp) && |
4837 | if (is_edp(intel_dp) && |
4946 | property == connector->dev->mode_config.scaling_mode_property) { |
4838 | property == connector->dev->mode_config.scaling_mode_property) { |
4947 | if (val == DRM_MODE_SCALE_NONE) { |
4839 | if (val == DRM_MODE_SCALE_NONE) { |
4948 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4840 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4949 | return -EINVAL; |
4841 | return -EINVAL; |
4950 | } |
4842 | } |
4951 | 4843 | ||
4952 | if (intel_connector->panel.fitting_mode == val) { |
4844 | if (intel_connector->panel.fitting_mode == val) { |
4953 | /* the eDP scaling property is not changed */ |
4845 | /* the eDP scaling property is not changed */ |
4954 | return 0; |
4846 | return 0; |
4955 | } |
4847 | } |
4956 | intel_connector->panel.fitting_mode = val; |
4848 | intel_connector->panel.fitting_mode = val; |
4957 | 4849 | ||
4958 | goto done; |
4850 | goto done; |
4959 | } |
4851 | } |
4960 | 4852 | ||
4961 | return -EINVAL; |
4853 | return -EINVAL; |
4962 | 4854 | ||
4963 | done: |
4855 | done: |
4964 | if (intel_encoder->base.crtc) |
4856 | if (intel_encoder->base.crtc) |
4965 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4857 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4966 | 4858 | ||
4967 | return 0; |
4859 | return 0; |
4968 | } |
4860 | } |
4969 | 4861 | ||
4970 | static void |
4862 | static void |
4971 | intel_dp_connector_destroy(struct drm_connector *connector) |
4863 | intel_dp_connector_destroy(struct drm_connector *connector) |
4972 | { |
4864 | { |
4973 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4865 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4974 | 4866 | ||
4975 | kfree(intel_connector->detect_edid); |
4867 | kfree(intel_connector->detect_edid); |
4976 | 4868 | ||
4977 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4869 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4978 | kfree(intel_connector->edid); |
4870 | kfree(intel_connector->edid); |
4979 | 4871 | ||
4980 | /* Can't call is_edp() since the encoder may have been destroyed |
4872 | /* Can't call is_edp() since the encoder may have been destroyed |
4981 | * already. */ |
4873 | * already. */ |
4982 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
4874 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
4983 | intel_panel_fini(&intel_connector->panel); |
4875 | intel_panel_fini(&intel_connector->panel); |
4984 | 4876 | ||
4985 | drm_connector_cleanup(connector); |
4877 | drm_connector_cleanup(connector); |
4986 | kfree(connector); |
4878 | kfree(connector); |
4987 | } |
4879 | } |
4988 | 4880 | ||
4989 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
4881 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
4990 | { |
4882 | { |
4991 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4883 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4992 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4884 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4993 | 4885 | ||
4994 | drm_dp_aux_unregister(&intel_dp->aux); |
4886 | intel_dp_aux_fini(intel_dp); |
4995 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
4887 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
4996 | if (is_edp(intel_dp)) { |
4888 | if (is_edp(intel_dp)) { |
4997 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4889 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4998 | /* |
4890 | /* |
4999 | * vdd might still be enabled do to the delayed vdd off. |
4891 | * vdd might still be enabled do to the delayed vdd off. |
5000 | * Make sure vdd is actually turned off here. |
4892 | * Make sure vdd is actually turned off here. |
5001 | */ |
4893 | */ |
5002 | pps_lock(intel_dp); |
4894 | pps_lock(intel_dp); |
5003 | edp_panel_vdd_off_sync(intel_dp); |
4895 | edp_panel_vdd_off_sync(intel_dp); |
5004 | pps_unlock(intel_dp); |
4896 | pps_unlock(intel_dp); |
- | 4897 | ||
- | 4898 | if (intel_dp->edp_notifier.notifier_call) { |
|
- | 4899 | intel_dp->edp_notifier.notifier_call = NULL; |
|
5005 | 4900 | } |
|
5006 | } |
4901 | } |
5007 | drm_encoder_cleanup(encoder); |
4902 | drm_encoder_cleanup(encoder); |
5008 | kfree(intel_dig_port); |
4903 | kfree(intel_dig_port); |
5009 | } |
4904 | } |
5010 | 4905 | ||
5011 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
4906 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
5012 | { |
4907 | { |
5013 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4908 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
5014 | 4909 | ||
5015 | if (!is_edp(intel_dp)) |
4910 | if (!is_edp(intel_dp)) |
5016 | return; |
4911 | return; |
5017 | 4912 | ||
5018 | /* |
4913 | /* |
5019 | * vdd might still be enabled do to the delayed vdd off. |
4914 | * vdd might still be enabled do to the delayed vdd off. |
5020 | * Make sure vdd is actually turned off here. |
4915 | * Make sure vdd is actually turned off here. |
5021 | */ |
4916 | */ |
5022 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4917 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5023 | pps_lock(intel_dp); |
4918 | pps_lock(intel_dp); |
5024 | edp_panel_vdd_off_sync(intel_dp); |
4919 | edp_panel_vdd_off_sync(intel_dp); |
5025 | pps_unlock(intel_dp); |
4920 | pps_unlock(intel_dp); |
5026 | } |
4921 | } |
5027 | 4922 | ||
5028 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4923 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
5029 | { |
4924 | { |
5030 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4925 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5031 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4926 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5032 | struct drm_i915_private *dev_priv = dev->dev_private; |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; |
5033 | enum intel_display_power_domain power_domain; |
4928 | enum intel_display_power_domain power_domain; |
5034 | 4929 | ||
5035 | lockdep_assert_held(&dev_priv->pps_mutex); |
4930 | lockdep_assert_held(&dev_priv->pps_mutex); |
5036 | 4931 | ||
5037 | if (!edp_have_panel_vdd(intel_dp)) |
4932 | if (!edp_have_panel_vdd(intel_dp)) |
5038 | return; |
4933 | return; |
5039 | 4934 | ||
5040 | /* |
4935 | /* |
5041 | * The VDD bit needs a power domain reference, so if the bit is |
4936 | * The VDD bit needs a power domain reference, so if the bit is |
5042 | * already enabled when we boot or resume, grab this reference and |
4937 | * already enabled when we boot or resume, grab this reference and |
5043 | * schedule a vdd off, so we don't hold on to the reference |
4938 | * schedule a vdd off, so we don't hold on to the reference |
5044 | * indefinitely. |
4939 | * indefinitely. |
5045 | */ |
4940 | */ |
5046 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
4941 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
5047 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
4942 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
5048 | intel_display_power_get(dev_priv, power_domain); |
4943 | intel_display_power_get(dev_priv, power_domain); |
5049 | 4944 | ||
5050 | edp_panel_vdd_schedule_off(intel_dp); |
4945 | edp_panel_vdd_schedule_off(intel_dp); |
5051 | } |
4946 | } |
5052 | 4947 | ||
5053 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4948 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
5054 | { |
4949 | { |
5055 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
- | |
5056 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4950 | struct intel_dp *intel_dp; |
5057 | - | ||
5058 | if (!HAS_DDI(dev_priv)) |
- | |
5059 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
- | |
5060 | 4951 | ||
5061 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
4952 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
5062 | return; |
4953 | return; |
- | 4954 | ||
- | 4955 | intel_dp = enc_to_intel_dp(encoder); |
|
5063 | 4956 | ||
5064 | pps_lock(intel_dp); |
4957 | pps_lock(intel_dp); |
5065 | 4958 | ||
5066 | /* |
4959 | /* |
5067 | * Read out the current power sequencer assignment, |
4960 | * Read out the current power sequencer assignment, |
5068 | * in case the BIOS did something with it. |
4961 | * in case the BIOS did something with it. |
5069 | */ |
4962 | */ |
5070 | if (IS_VALLEYVIEW(encoder->dev)) |
4963 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
5071 | vlv_initial_power_sequencer_setup(intel_dp); |
4964 | vlv_initial_power_sequencer_setup(intel_dp); |
5072 | 4965 | ||
5073 | intel_edp_panel_vdd_sanitize(intel_dp); |
4966 | intel_edp_panel_vdd_sanitize(intel_dp); |
5074 | 4967 | ||
5075 | pps_unlock(intel_dp); |
4968 | pps_unlock(intel_dp); |
5076 | } |
4969 | } |
5077 | 4970 | ||
5078 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4971 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
5079 | .dpms = drm_atomic_helper_connector_dpms, |
4972 | .dpms = drm_atomic_helper_connector_dpms, |
5080 | .detect = intel_dp_detect, |
4973 | .detect = intel_dp_detect, |
5081 | .force = intel_dp_force, |
4974 | .force = intel_dp_force, |
5082 | .fill_modes = drm_helper_probe_single_connector_modes, |
4975 | .fill_modes = drm_helper_probe_single_connector_modes, |
5083 | .set_property = intel_dp_set_property, |
4976 | .set_property = intel_dp_set_property, |
5084 | .atomic_get_property = intel_connector_atomic_get_property, |
4977 | .atomic_get_property = intel_connector_atomic_get_property, |
5085 | .destroy = intel_dp_connector_destroy, |
4978 | .destroy = intel_dp_connector_destroy, |
5086 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
4979 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
5087 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4980 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
5088 | }; |
4981 | }; |
5089 | 4982 | ||
5090 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
4983 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
5091 | .get_modes = intel_dp_get_modes, |
4984 | .get_modes = intel_dp_get_modes, |
5092 | .mode_valid = intel_dp_mode_valid, |
4985 | .mode_valid = intel_dp_mode_valid, |
5093 | .best_encoder = intel_best_encoder, |
4986 | .best_encoder = intel_best_encoder, |
5094 | }; |
4987 | }; |
5095 | 4988 | ||
5096 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
4989 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
5097 | .reset = intel_dp_encoder_reset, |
4990 | .reset = intel_dp_encoder_reset, |
5098 | .destroy = intel_dp_encoder_destroy, |
4991 | .destroy = intel_dp_encoder_destroy, |
5099 | }; |
4992 | }; |
5100 | 4993 | ||
5101 | enum irqreturn |
4994 | enum irqreturn |
5102 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4995 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5103 | { |
4996 | { |
5104 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4997 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5105 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4998 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5106 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4999 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5107 | struct drm_i915_private *dev_priv = dev->dev_private; |
5000 | struct drm_i915_private *dev_priv = dev->dev_private; |
5108 | enum intel_display_power_domain power_domain; |
5001 | enum intel_display_power_domain power_domain; |
5109 | enum irqreturn ret = IRQ_NONE; |
5002 | enum irqreturn ret = IRQ_NONE; |
5110 | 5003 | ||
5111 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5004 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5112 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
5005 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
5113 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
5006 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
5114 | 5007 | ||
5115 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5008 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5116 | /* |
5009 | /* |
5117 | * vdd off can generate a long pulse on eDP which |
5010 | * vdd off can generate a long pulse on eDP which |
5118 | * would require vdd on to handle it, and thus we |
5011 | * would require vdd on to handle it, and thus we |
5119 | * would end up in an endless cycle of |
5012 | * would end up in an endless cycle of |
5120 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5013 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5121 | */ |
5014 | */ |
5122 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5015 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5123 | port_name(intel_dig_port->port)); |
5016 | port_name(intel_dig_port->port)); |
5124 | return IRQ_HANDLED; |
5017 | return IRQ_HANDLED; |
5125 | } |
5018 | } |
5126 | 5019 | ||
5127 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5020 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5128 | port_name(intel_dig_port->port), |
5021 | port_name(intel_dig_port->port), |
5129 | long_hpd ? "long" : "short"); |
5022 | long_hpd ? "long" : "short"); |
5130 | 5023 | ||
5131 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5024 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5132 | intel_display_power_get(dev_priv, power_domain); |
5025 | intel_display_power_get(dev_priv, power_domain); |
5133 | 5026 | ||
5134 | if (long_hpd) { |
5027 | if (long_hpd) { |
- | 5028 | /* indicate that we need to restart link training */ |
|
- | 5029 | intel_dp->train_set_valid = false; |
|
- | 5030 | ||
5135 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5031 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5136 | goto mst_fail; |
5032 | goto mst_fail; |
5137 | 5033 | ||
5138 | if (!intel_dp_get_dpcd(intel_dp)) { |
5034 | if (!intel_dp_get_dpcd(intel_dp)) { |
5139 | goto mst_fail; |
5035 | goto mst_fail; |
5140 | } |
5036 | } |
5141 | 5037 | ||
5142 | intel_dp_probe_oui(intel_dp); |
5038 | intel_dp_probe_oui(intel_dp); |
5143 | 5039 | ||
5144 | if (!intel_dp_probe_mst(intel_dp)) { |
5040 | if (!intel_dp_probe_mst(intel_dp)) { |
5145 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5041 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5146 | intel_dp_check_link_status(intel_dp); |
5042 | intel_dp_check_link_status(intel_dp); |
5147 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5043 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5148 | goto mst_fail; |
5044 | goto mst_fail; |
5149 | } |
5045 | } |
5150 | } else { |
5046 | } else { |
5151 | if (intel_dp->is_mst) { |
5047 | if (intel_dp->is_mst) { |
5152 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5048 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5153 | goto mst_fail; |
5049 | goto mst_fail; |
5154 | } |
5050 | } |
5155 | 5051 | ||
5156 | if (!intel_dp->is_mst) { |
5052 | if (!intel_dp->is_mst) { |
5157 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5053 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5158 | intel_dp_check_link_status(intel_dp); |
5054 | intel_dp_check_link_status(intel_dp); |
5159 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5055 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5160 | } |
5056 | } |
5161 | } |
5057 | } |
5162 | 5058 | ||
5163 | ret = IRQ_HANDLED; |
5059 | ret = IRQ_HANDLED; |
5164 | 5060 | ||
5165 | goto put_power; |
5061 | goto put_power; |
5166 | mst_fail: |
5062 | mst_fail: |
5167 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5063 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5168 | if (intel_dp->is_mst) { |
5064 | if (intel_dp->is_mst) { |
5169 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5065 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5170 | intel_dp->is_mst = false; |
5066 | intel_dp->is_mst = false; |
5171 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5067 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5172 | } |
5068 | } |
5173 | put_power: |
5069 | put_power: |
5174 | intel_display_power_put(dev_priv, power_domain); |
5070 | intel_display_power_put(dev_priv, power_domain); |
5175 | 5071 | ||
5176 | return ret; |
5072 | return ret; |
5177 | } |
5073 | } |
5178 | - | ||
5179 | /* Return which DP Port should be selected for Transcoder DP control */ |
- | |
5180 | int |
- | |
5181 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
- | |
5182 | { |
- | |
5183 | struct drm_device *dev = crtc->dev; |
- | |
5184 | struct intel_encoder *intel_encoder; |
- | |
5185 | struct intel_dp *intel_dp; |
- | |
5186 | - | ||
5187 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
- | |
5188 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
- | |
5189 | - | ||
5190 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
- | |
5191 | intel_encoder->type == INTEL_OUTPUT_EDP) |
- | |
5192 | return intel_dp->output_reg; |
- | |
5193 | } |
- | |
5194 | - | ||
5195 | return -1; |
- | |
5196 | } |
- | |
5197 | 5074 | ||
5198 | /* check the VBT to see whether the eDP is on another port */ |
5075 | /* check the VBT to see whether the eDP is on another port */ |
5199 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5076 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5200 | { |
5077 | { |
5201 | struct drm_i915_private *dev_priv = dev->dev_private; |
5078 | struct drm_i915_private *dev_priv = dev->dev_private; |
5202 | union child_device_config *p_child; |
5079 | union child_device_config *p_child; |
5203 | int i; |
5080 | int i; |
5204 | static const short port_mapping[] = { |
5081 | static const short port_mapping[] = { |
5205 | [PORT_B] = DVO_PORT_DPB, |
5082 | [PORT_B] = DVO_PORT_DPB, |
5206 | [PORT_C] = DVO_PORT_DPC, |
5083 | [PORT_C] = DVO_PORT_DPC, |
5207 | [PORT_D] = DVO_PORT_DPD, |
5084 | [PORT_D] = DVO_PORT_DPD, |
5208 | [PORT_E] = DVO_PORT_DPE, |
5085 | [PORT_E] = DVO_PORT_DPE, |
5209 | }; |
5086 | }; |
5210 | 5087 | ||
5211 | /* |
5088 | /* |
5212 | * eDP not supported on g4x. so bail out early just |
5089 | * eDP not supported on g4x. so bail out early just |
5213 | * for a bit extra safety in case the VBT is bonkers. |
5090 | * for a bit extra safety in case the VBT is bonkers. |
5214 | */ |
5091 | */ |
5215 | if (INTEL_INFO(dev)->gen < 5) |
5092 | if (INTEL_INFO(dev)->gen < 5) |
5216 | return false; |
5093 | return false; |
5217 | 5094 | ||
5218 | if (port == PORT_A) |
5095 | if (port == PORT_A) |
5219 | return true; |
5096 | return true; |
5220 | 5097 | ||
5221 | if (!dev_priv->vbt.child_dev_num) |
5098 | if (!dev_priv->vbt.child_dev_num) |
5222 | return false; |
5099 | return false; |
5223 | 5100 | ||
5224 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5101 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5225 | p_child = dev_priv->vbt.child_dev + i; |
5102 | p_child = dev_priv->vbt.child_dev + i; |
5226 | 5103 | ||
5227 | if (p_child->common.dvo_port == port_mapping[port] && |
5104 | if (p_child->common.dvo_port == port_mapping[port] && |
5228 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5105 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5229 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5106 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5230 | return true; |
5107 | return true; |
5231 | } |
5108 | } |
5232 | return false; |
5109 | return false; |
5233 | } |
5110 | } |
5234 | 5111 | ||
5235 | void |
5112 | void |
5236 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5113 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5237 | { |
5114 | { |
5238 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5115 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5239 | 5116 | ||
5240 | intel_attach_force_audio_property(connector); |
5117 | intel_attach_force_audio_property(connector); |
5241 | intel_attach_broadcast_rgb_property(connector); |
5118 | intel_attach_broadcast_rgb_property(connector); |
5242 | intel_dp->color_range_auto = true; |
5119 | intel_dp->color_range_auto = true; |
5243 | 5120 | ||
5244 | if (is_edp(intel_dp)) { |
5121 | if (is_edp(intel_dp)) { |
5245 | drm_mode_create_scaling_mode_property(connector->dev); |
5122 | drm_mode_create_scaling_mode_property(connector->dev); |
5246 | drm_object_attach_property( |
5123 | drm_object_attach_property( |
5247 | &connector->base, |
5124 | &connector->base, |
5248 | connector->dev->mode_config.scaling_mode_property, |
5125 | connector->dev->mode_config.scaling_mode_property, |
5249 | DRM_MODE_SCALE_ASPECT); |
5126 | DRM_MODE_SCALE_ASPECT); |
5250 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5127 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5251 | } |
5128 | } |
5252 | } |
5129 | } |
5253 | 5130 | ||
5254 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5131 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5255 | { |
5132 | { |
5256 | intel_dp->last_power_cycle = jiffies; |
5133 | intel_dp->last_power_cycle = jiffies; |
5257 | intel_dp->last_power_on = jiffies; |
5134 | intel_dp->last_power_on = jiffies; |
5258 | intel_dp->last_backlight_off = jiffies; |
5135 | intel_dp->last_backlight_off = jiffies; |
5259 | } |
5136 | } |
5260 | 5137 | ||
5261 | static void |
5138 | static void |
5262 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5139 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5263 | struct intel_dp *intel_dp) |
5140 | struct intel_dp *intel_dp) |
5264 | { |
5141 | { |
5265 | struct drm_i915_private *dev_priv = dev->dev_private; |
5142 | struct drm_i915_private *dev_priv = dev->dev_private; |
5266 | struct edp_power_seq cur, vbt, spec, |
5143 | struct edp_power_seq cur, vbt, spec, |
5267 | *final = &intel_dp->pps_delays; |
5144 | *final = &intel_dp->pps_delays; |
5268 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5145 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5269 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0; |
5146 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
5270 | 5147 | ||
5271 | lockdep_assert_held(&dev_priv->pps_mutex); |
5148 | lockdep_assert_held(&dev_priv->pps_mutex); |
5272 | 5149 | ||
5273 | /* already initialized? */ |
5150 | /* already initialized? */ |
5274 | if (final->t11_t12 != 0) |
5151 | if (final->t11_t12 != 0) |
5275 | return; |
5152 | return; |
5276 | 5153 | ||
5277 | if (IS_BROXTON(dev)) { |
5154 | if (IS_BROXTON(dev)) { |
5278 | /* |
5155 | /* |
5279 | * TODO: BXT has 2 sets of PPS registers. |
5156 | * TODO: BXT has 2 sets of PPS registers. |
5280 | * Correct Register for Broxton need to be identified |
5157 | * Correct Register for Broxton need to be identified |
5281 | * using VBT. hardcoding for now |
5158 | * using VBT. hardcoding for now |
5282 | */ |
5159 | */ |
5283 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5160 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5284 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5161 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5285 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5162 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5286 | } else if (HAS_PCH_SPLIT(dev)) { |
5163 | } else if (HAS_PCH_SPLIT(dev)) { |
5287 | pp_ctrl_reg = PCH_PP_CONTROL; |
5164 | pp_ctrl_reg = PCH_PP_CONTROL; |
5288 | pp_on_reg = PCH_PP_ON_DELAYS; |
5165 | pp_on_reg = PCH_PP_ON_DELAYS; |
5289 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5166 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5290 | pp_div_reg = PCH_PP_DIVISOR; |
5167 | pp_div_reg = PCH_PP_DIVISOR; |
5291 | } else { |
5168 | } else { |
5292 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5169 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5293 | 5170 | ||
5294 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5171 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5295 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5172 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5296 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5173 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5297 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5174 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5298 | } |
5175 | } |
5299 | 5176 | ||
5300 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5177 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5301 | * the very first thing. */ |
5178 | * the very first thing. */ |
5302 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5179 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5303 | 5180 | ||
5304 | pp_on = I915_READ(pp_on_reg); |
5181 | pp_on = I915_READ(pp_on_reg); |
5305 | pp_off = I915_READ(pp_off_reg); |
5182 | pp_off = I915_READ(pp_off_reg); |
5306 | if (!IS_BROXTON(dev)) { |
5183 | if (!IS_BROXTON(dev)) { |
5307 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5184 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5308 | pp_div = I915_READ(pp_div_reg); |
5185 | pp_div = I915_READ(pp_div_reg); |
5309 | } |
5186 | } |
5310 | 5187 | ||
5311 | /* Pull timing values out of registers */ |
5188 | /* Pull timing values out of registers */ |
5312 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5189 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5313 | PANEL_POWER_UP_DELAY_SHIFT; |
5190 | PANEL_POWER_UP_DELAY_SHIFT; |
5314 | 5191 | ||
5315 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5192 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5316 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5193 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5317 | 5194 | ||
5318 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5195 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5319 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5196 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5320 | 5197 | ||
5321 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5198 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5322 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5199 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5323 | 5200 | ||
5324 | if (IS_BROXTON(dev)) { |
5201 | if (IS_BROXTON(dev)) { |
5325 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5202 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5326 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5203 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5327 | if (tmp > 0) |
5204 | if (tmp > 0) |
5328 | cur.t11_t12 = (tmp - 1) * 1000; |
5205 | cur.t11_t12 = (tmp - 1) * 1000; |
5329 | else |
5206 | else |
5330 | cur.t11_t12 = 0; |
5207 | cur.t11_t12 = 0; |
5331 | } else { |
5208 | } else { |
5332 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5209 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5333 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5210 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5334 | } |
5211 | } |
5335 | 5212 | ||
5336 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5213 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5337 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5214 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5338 | 5215 | ||
5339 | vbt = dev_priv->vbt.edp_pps; |
5216 | vbt = dev_priv->vbt.edp_pps; |
5340 | 5217 | ||
5341 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5218 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5342 | * our hw here, which are all in 100usec. */ |
5219 | * our hw here, which are all in 100usec. */ |
5343 | spec.t1_t3 = 210 * 10; |
5220 | spec.t1_t3 = 210 * 10; |
5344 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5221 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5345 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5222 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5346 | spec.t10 = 500 * 10; |
5223 | spec.t10 = 500 * 10; |
5347 | /* This one is special and actually in units of 100ms, but zero |
5224 | /* This one is special and actually in units of 100ms, but zero |
5348 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5225 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5349 | * table multiplies it with 1000 to make it in units of 100usec, |
5226 | * table multiplies it with 1000 to make it in units of 100usec, |
5350 | * too. */ |
5227 | * too. */ |
5351 | spec.t11_t12 = (510 + 100) * 10; |
5228 | spec.t11_t12 = (510 + 100) * 10; |
5352 | 5229 | ||
5353 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5230 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5354 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5231 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5355 | 5232 | ||
5356 | /* Use the max of the register settings and vbt. If both are |
5233 | /* Use the max of the register settings and vbt. If both are |
5357 | * unset, fall back to the spec limits. */ |
5234 | * unset, fall back to the spec limits. */ |
5358 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5235 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5359 | spec.field : \ |
5236 | spec.field : \ |
5360 | max(cur.field, vbt.field)) |
5237 | max(cur.field, vbt.field)) |
5361 | assign_final(t1_t3); |
5238 | assign_final(t1_t3); |
5362 | assign_final(t8); |
5239 | assign_final(t8); |
5363 | assign_final(t9); |
5240 | assign_final(t9); |
5364 | assign_final(t10); |
5241 | assign_final(t10); |
5365 | assign_final(t11_t12); |
5242 | assign_final(t11_t12); |
5366 | #undef assign_final |
5243 | #undef assign_final |
5367 | 5244 | ||
5368 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5245 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5369 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5246 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5370 | intel_dp->backlight_on_delay = get_delay(t8); |
5247 | intel_dp->backlight_on_delay = get_delay(t8); |
5371 | intel_dp->backlight_off_delay = get_delay(t9); |
5248 | intel_dp->backlight_off_delay = get_delay(t9); |
5372 | intel_dp->panel_power_down_delay = get_delay(t10); |
5249 | intel_dp->panel_power_down_delay = get_delay(t10); |
5373 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5250 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5374 | #undef get_delay |
5251 | #undef get_delay |
5375 | 5252 | ||
5376 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5253 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5377 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5254 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5378 | intel_dp->panel_power_cycle_delay); |
5255 | intel_dp->panel_power_cycle_delay); |
5379 | 5256 | ||
5380 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5257 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5381 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5258 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5382 | } |
5259 | } |
5383 | 5260 | ||
5384 | static void |
5261 | static void |
5385 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5262 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5386 | struct intel_dp *intel_dp) |
5263 | struct intel_dp *intel_dp) |
5387 | { |
5264 | { |
5388 | struct drm_i915_private *dev_priv = dev->dev_private; |
5265 | struct drm_i915_private *dev_priv = dev->dev_private; |
5389 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5266 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5390 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5267 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5391 | int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg; |
5268 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
5392 | enum port port = dp_to_dig_port(intel_dp)->port; |
5269 | enum port port = dp_to_dig_port(intel_dp)->port; |
5393 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5270 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5394 | 5271 | ||
5395 | lockdep_assert_held(&dev_priv->pps_mutex); |
5272 | lockdep_assert_held(&dev_priv->pps_mutex); |
5396 | 5273 | ||
5397 | if (IS_BROXTON(dev)) { |
5274 | if (IS_BROXTON(dev)) { |
5398 | /* |
5275 | /* |
5399 | * TODO: BXT has 2 sets of PPS registers. |
5276 | * TODO: BXT has 2 sets of PPS registers. |
5400 | * Correct Register for Broxton need to be identified |
5277 | * Correct Register for Broxton need to be identified |
5401 | * using VBT. hardcoding for now |
5278 | * using VBT. hardcoding for now |
5402 | */ |
5279 | */ |
5403 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5280 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5404 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5281 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5405 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5282 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5406 | 5283 | ||
5407 | } else if (HAS_PCH_SPLIT(dev)) { |
5284 | } else if (HAS_PCH_SPLIT(dev)) { |
5408 | pp_on_reg = PCH_PP_ON_DELAYS; |
5285 | pp_on_reg = PCH_PP_ON_DELAYS; |
5409 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5286 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5410 | pp_div_reg = PCH_PP_DIVISOR; |
5287 | pp_div_reg = PCH_PP_DIVISOR; |
5411 | } else { |
5288 | } else { |
5412 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5289 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5413 | 5290 | ||
5414 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5291 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5415 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5292 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5416 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5293 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5417 | } |
5294 | } |
5418 | 5295 | ||
5419 | /* |
5296 | /* |
5420 | * And finally store the new values in the power sequencer. The |
5297 | * And finally store the new values in the power sequencer. The |
5421 | * backlight delays are set to 1 because we do manual waits on them. For |
5298 | * backlight delays are set to 1 because we do manual waits on them. For |
5422 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5299 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5423 | * we'll end up waiting for the backlight off delay twice: once when we |
5300 | * we'll end up waiting for the backlight off delay twice: once when we |
5424 | * do the manual sleep, and once when we disable the panel and wait for |
5301 | * do the manual sleep, and once when we disable the panel and wait for |
5425 | * the PP_STATUS bit to become zero. |
5302 | * the PP_STATUS bit to become zero. |
5426 | */ |
5303 | */ |
5427 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5304 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5428 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5305 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5429 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5306 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5430 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5307 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5431 | /* Compute the divisor for the pp clock, simply match the Bspec |
5308 | /* Compute the divisor for the pp clock, simply match the Bspec |
5432 | * formula. */ |
5309 | * formula. */ |
5433 | if (IS_BROXTON(dev)) { |
5310 | if (IS_BROXTON(dev)) { |
5434 | pp_div = I915_READ(pp_ctrl_reg); |
5311 | pp_div = I915_READ(pp_ctrl_reg); |
5435 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5312 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5436 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5313 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5437 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5314 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5438 | } else { |
5315 | } else { |
5439 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5316 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5440 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5317 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5441 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5318 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5442 | } |
5319 | } |
5443 | 5320 | ||
5444 | /* Haswell doesn't have any port selection bits for the panel |
5321 | /* Haswell doesn't have any port selection bits for the panel |
5445 | * power sequencer any more. */ |
5322 | * power sequencer any more. */ |
5446 | if (IS_VALLEYVIEW(dev)) { |
5323 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5447 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5324 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5448 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5325 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5449 | if (port == PORT_A) |
5326 | if (port == PORT_A) |
5450 | port_sel = PANEL_PORT_SELECT_DPA; |
5327 | port_sel = PANEL_PORT_SELECT_DPA; |
5451 | else |
5328 | else |
5452 | port_sel = PANEL_PORT_SELECT_DPD; |
5329 | port_sel = PANEL_PORT_SELECT_DPD; |
5453 | } |
5330 | } |
5454 | 5331 | ||
5455 | pp_on |= port_sel; |
5332 | pp_on |= port_sel; |
5456 | 5333 | ||
5457 | I915_WRITE(pp_on_reg, pp_on); |
5334 | I915_WRITE(pp_on_reg, pp_on); |
5458 | I915_WRITE(pp_off_reg, pp_off); |
5335 | I915_WRITE(pp_off_reg, pp_off); |
5459 | if (IS_BROXTON(dev)) |
5336 | if (IS_BROXTON(dev)) |
5460 | I915_WRITE(pp_ctrl_reg, pp_div); |
5337 | I915_WRITE(pp_ctrl_reg, pp_div); |
5461 | else |
5338 | else |
5462 | I915_WRITE(pp_div_reg, pp_div); |
5339 | I915_WRITE(pp_div_reg, pp_div); |
5463 | 5340 | ||
5464 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5341 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5465 | I915_READ(pp_on_reg), |
5342 | I915_READ(pp_on_reg), |
5466 | I915_READ(pp_off_reg), |
5343 | I915_READ(pp_off_reg), |
5467 | IS_BROXTON(dev) ? |
5344 | IS_BROXTON(dev) ? |
5468 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5345 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5469 | I915_READ(pp_div_reg)); |
5346 | I915_READ(pp_div_reg)); |
5470 | } |
5347 | } |
5471 | 5348 | ||
5472 | /** |
5349 | /** |
5473 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5350 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5474 | * @dev: DRM device |
5351 | * @dev: DRM device |
5475 | * @refresh_rate: RR to be programmed |
5352 | * @refresh_rate: RR to be programmed |
5476 | * |
5353 | * |
5477 | * This function gets called when refresh rate (RR) has to be changed from |
5354 | * This function gets called when refresh rate (RR) has to be changed from |
5478 | * one frequency to another. Switches can be between high and low RR |
5355 | * one frequency to another. Switches can be between high and low RR |
5479 | * supported by the panel or to any other RR based on media playback (in |
5356 | * supported by the panel or to any other RR based on media playback (in |
5480 | * this case, RR value needs to be passed from user space). |
5357 | * this case, RR value needs to be passed from user space). |
5481 | * |
5358 | * |
5482 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5359 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5483 | */ |
5360 | */ |
5484 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5361 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5485 | { |
5362 | { |
5486 | struct drm_i915_private *dev_priv = dev->dev_private; |
5363 | struct drm_i915_private *dev_priv = dev->dev_private; |
5487 | struct intel_encoder *encoder; |
5364 | struct intel_encoder *encoder; |
5488 | struct intel_digital_port *dig_port = NULL; |
5365 | struct intel_digital_port *dig_port = NULL; |
5489 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5366 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5490 | struct intel_crtc_state *config = NULL; |
5367 | struct intel_crtc_state *config = NULL; |
5491 | struct intel_crtc *intel_crtc = NULL; |
5368 | struct intel_crtc *intel_crtc = NULL; |
5492 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5369 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5493 | 5370 | ||
5494 | if (refresh_rate <= 0) { |
5371 | if (refresh_rate <= 0) { |
5495 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5372 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5496 | return; |
5373 | return; |
5497 | } |
5374 | } |
5498 | 5375 | ||
5499 | if (intel_dp == NULL) { |
5376 | if (intel_dp == NULL) { |
5500 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5377 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5501 | return; |
5378 | return; |
5502 | } |
5379 | } |
5503 | 5380 | ||
5504 | /* |
5381 | /* |
5505 | * FIXME: This needs proper synchronization with psr state for some |
5382 | * FIXME: This needs proper synchronization with psr state for some |
5506 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5383 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5507 | */ |
5384 | */ |
5508 | 5385 | ||
5509 | dig_port = dp_to_dig_port(intel_dp); |
5386 | dig_port = dp_to_dig_port(intel_dp); |
5510 | encoder = &dig_port->base; |
5387 | encoder = &dig_port->base; |
5511 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5388 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5512 | 5389 | ||
5513 | if (!intel_crtc) { |
5390 | if (!intel_crtc) { |
5514 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5391 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5515 | return; |
5392 | return; |
5516 | } |
5393 | } |
5517 | 5394 | ||
5518 | config = intel_crtc->config; |
5395 | config = intel_crtc->config; |
5519 | 5396 | ||
5520 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5397 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5521 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5398 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5522 | return; |
5399 | return; |
5523 | } |
5400 | } |
5524 | 5401 | ||
5525 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5402 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5526 | refresh_rate) |
5403 | refresh_rate) |
5527 | index = DRRS_LOW_RR; |
5404 | index = DRRS_LOW_RR; |
5528 | 5405 | ||
5529 | if (index == dev_priv->drrs.refresh_rate_type) { |
5406 | if (index == dev_priv->drrs.refresh_rate_type) { |
5530 | DRM_DEBUG_KMS( |
5407 | DRM_DEBUG_KMS( |
5531 | "DRRS requested for previously set RR...ignoring\n"); |
5408 | "DRRS requested for previously set RR...ignoring\n"); |
5532 | return; |
5409 | return; |
5533 | } |
5410 | } |
5534 | 5411 | ||
5535 | if (!intel_crtc->active) { |
5412 | if (!intel_crtc->active) { |
5536 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5413 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5537 | return; |
5414 | return; |
5538 | } |
5415 | } |
5539 | 5416 | ||
5540 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5417 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5541 | switch (index) { |
5418 | switch (index) { |
5542 | case DRRS_HIGH_RR: |
5419 | case DRRS_HIGH_RR: |
5543 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5420 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5544 | break; |
5421 | break; |
5545 | case DRRS_LOW_RR: |
5422 | case DRRS_LOW_RR: |
5546 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5423 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5547 | break; |
5424 | break; |
5548 | case DRRS_MAX_RR: |
5425 | case DRRS_MAX_RR: |
5549 | default: |
5426 | default: |
5550 | DRM_ERROR("Unsupported refreshrate type\n"); |
5427 | DRM_ERROR("Unsupported refreshrate type\n"); |
5551 | } |
5428 | } |
5552 | } else if (INTEL_INFO(dev)->gen > 6) { |
5429 | } else if (INTEL_INFO(dev)->gen > 6) { |
5553 | u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5430 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5554 | u32 val; |
5431 | u32 val; |
5555 | 5432 | ||
5556 | val = I915_READ(reg); |
5433 | val = I915_READ(reg); |
5557 | if (index > DRRS_HIGH_RR) { |
5434 | if (index > DRRS_HIGH_RR) { |
5558 | if (IS_VALLEYVIEW(dev)) |
5435 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5559 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5436 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5560 | else |
5437 | else |
5561 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5438 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5562 | } else { |
5439 | } else { |
5563 | if (IS_VALLEYVIEW(dev)) |
5440 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5564 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5441 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5565 | else |
5442 | else |
5566 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5443 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5567 | } |
5444 | } |
5568 | I915_WRITE(reg, val); |
5445 | I915_WRITE(reg, val); |
5569 | } |
5446 | } |
5570 | 5447 | ||
5571 | dev_priv->drrs.refresh_rate_type = index; |
5448 | dev_priv->drrs.refresh_rate_type = index; |
5572 | 5449 | ||
5573 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5450 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5574 | } |
5451 | } |
5575 | 5452 | ||
5576 | /** |
5453 | /** |
5577 | * intel_edp_drrs_enable - init drrs struct if supported |
5454 | * intel_edp_drrs_enable - init drrs struct if supported |
5578 | * @intel_dp: DP struct |
5455 | * @intel_dp: DP struct |
5579 | * |
5456 | * |
5580 | * Initializes frontbuffer_bits and drrs.dp |
5457 | * Initializes frontbuffer_bits and drrs.dp |
5581 | */ |
5458 | */ |
5582 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5459 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5583 | { |
5460 | { |
5584 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5461 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5585 | struct drm_i915_private *dev_priv = dev->dev_private; |
5462 | struct drm_i915_private *dev_priv = dev->dev_private; |
5586 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5463 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5587 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5464 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5589 | 5466 | ||
5590 | if (!intel_crtc->config->has_drrs) { |
5467 | if (!intel_crtc->config->has_drrs) { |
5591 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5468 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5592 | return; |
5469 | return; |
5593 | } |
5470 | } |
5594 | 5471 | ||
5595 | mutex_lock(&dev_priv->drrs.mutex); |
5472 | mutex_lock(&dev_priv->drrs.mutex); |
5596 | if (WARN_ON(dev_priv->drrs.dp)) { |
5473 | if (WARN_ON(dev_priv->drrs.dp)) { |
5597 | DRM_ERROR("DRRS already enabled\n"); |
5474 | DRM_ERROR("DRRS already enabled\n"); |
5598 | goto unlock; |
5475 | goto unlock; |
5599 | } |
5476 | } |
5600 | 5477 | ||
5601 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5478 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5602 | 5479 | ||
5603 | dev_priv->drrs.dp = intel_dp; |
5480 | dev_priv->drrs.dp = intel_dp; |
5604 | 5481 | ||
5605 | unlock: |
5482 | unlock: |
5606 | mutex_unlock(&dev_priv->drrs.mutex); |
5483 | mutex_unlock(&dev_priv->drrs.mutex); |
5607 | } |
5484 | } |
5608 | 5485 | ||
5609 | /** |
5486 | /** |
5610 | * intel_edp_drrs_disable - Disable DRRS |
5487 | * intel_edp_drrs_disable - Disable DRRS |
5611 | * @intel_dp: DP struct |
5488 | * @intel_dp: DP struct |
5612 | * |
5489 | * |
5613 | */ |
5490 | */ |
5614 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5491 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5615 | { |
5492 | { |
5616 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5493 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5617 | struct drm_i915_private *dev_priv = dev->dev_private; |
5494 | struct drm_i915_private *dev_priv = dev->dev_private; |
5618 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5495 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5619 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5496 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5621 | 5498 | ||
5622 | if (!intel_crtc->config->has_drrs) |
5499 | if (!intel_crtc->config->has_drrs) |
5623 | return; |
5500 | return; |
5624 | 5501 | ||
5625 | mutex_lock(&dev_priv->drrs.mutex); |
5502 | mutex_lock(&dev_priv->drrs.mutex); |
5626 | if (!dev_priv->drrs.dp) { |
5503 | if (!dev_priv->drrs.dp) { |
5627 | mutex_unlock(&dev_priv->drrs.mutex); |
5504 | mutex_unlock(&dev_priv->drrs.mutex); |
5628 | return; |
5505 | return; |
5629 | } |
5506 | } |
5630 | 5507 | ||
5631 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5508 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5632 | intel_dp_set_drrs_state(dev_priv->dev, |
5509 | intel_dp_set_drrs_state(dev_priv->dev, |
5633 | intel_dp->attached_connector->panel. |
5510 | intel_dp->attached_connector->panel. |
5634 | fixed_mode->vrefresh); |
5511 | fixed_mode->vrefresh); |
5635 | 5512 | ||
5636 | dev_priv->drrs.dp = NULL; |
5513 | dev_priv->drrs.dp = NULL; |
5637 | mutex_unlock(&dev_priv->drrs.mutex); |
5514 | mutex_unlock(&dev_priv->drrs.mutex); |
5638 | 5515 | ||
5639 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
5516 | // cancel_delayed_work_sync(&dev_priv->drrs.work); |
5640 | } |
5517 | } |
5641 | 5518 | ||
5642 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5519 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5643 | { |
5520 | { |
5644 | struct drm_i915_private *dev_priv = |
5521 | struct drm_i915_private *dev_priv = |
5645 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5522 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5646 | struct intel_dp *intel_dp; |
5523 | struct intel_dp *intel_dp; |
5647 | 5524 | ||
5648 | mutex_lock(&dev_priv->drrs.mutex); |
5525 | mutex_lock(&dev_priv->drrs.mutex); |
5649 | 5526 | ||
5650 | intel_dp = dev_priv->drrs.dp; |
5527 | intel_dp = dev_priv->drrs.dp; |
5651 | 5528 | ||
5652 | if (!intel_dp) |
5529 | if (!intel_dp) |
5653 | goto unlock; |
5530 | goto unlock; |
5654 | 5531 | ||
5655 | /* |
5532 | /* |
5656 | * The delayed work can race with an invalidate hence we need to |
5533 | * The delayed work can race with an invalidate hence we need to |
5657 | * recheck. |
5534 | * recheck. |
5658 | */ |
5535 | */ |
5659 | 5536 | ||
5660 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5537 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5661 | goto unlock; |
5538 | goto unlock; |
5662 | 5539 | ||
5663 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5540 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5664 | intel_dp_set_drrs_state(dev_priv->dev, |
5541 | intel_dp_set_drrs_state(dev_priv->dev, |
5665 | intel_dp->attached_connector->panel. |
5542 | intel_dp->attached_connector->panel. |
5666 | downclock_mode->vrefresh); |
5543 | downclock_mode->vrefresh); |
5667 | 5544 | ||
5668 | unlock: |
5545 | unlock: |
5669 | mutex_unlock(&dev_priv->drrs.mutex); |
5546 | mutex_unlock(&dev_priv->drrs.mutex); |
5670 | } |
5547 | } |
5671 | 5548 | ||
5672 | /** |
5549 | /** |
5673 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5550 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5674 | * @dev: DRM device |
5551 | * @dev: DRM device |
5675 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5552 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5676 | * |
5553 | * |
5677 | * This function gets called everytime rendering on the given planes start. |
5554 | * This function gets called everytime rendering on the given planes start. |
5678 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5555 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5679 | * |
5556 | * |
5680 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5557 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5681 | */ |
5558 | */ |
5682 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5559 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5683 | unsigned frontbuffer_bits) |
5560 | unsigned frontbuffer_bits) |
5684 | { |
5561 | { |
5685 | struct drm_i915_private *dev_priv = dev->dev_private; |
5562 | struct drm_i915_private *dev_priv = dev->dev_private; |
5686 | struct drm_crtc *crtc; |
5563 | struct drm_crtc *crtc; |
5687 | enum pipe pipe; |
5564 | enum pipe pipe; |
5688 | 5565 | ||
5689 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5566 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5690 | return; |
5567 | return; |
5691 | 5568 | ||
5692 | cancel_delayed_work(&dev_priv->drrs.work); |
5569 | // cancel_delayed_work(&dev_priv->drrs.work); |
5693 | 5570 | ||
5694 | mutex_lock(&dev_priv->drrs.mutex); |
5571 | mutex_lock(&dev_priv->drrs.mutex); |
5695 | if (!dev_priv->drrs.dp) { |
5572 | if (!dev_priv->drrs.dp) { |
5696 | mutex_unlock(&dev_priv->drrs.mutex); |
5573 | mutex_unlock(&dev_priv->drrs.mutex); |
5697 | return; |
5574 | return; |
5698 | } |
5575 | } |
5699 | 5576 | ||
5700 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5577 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5701 | pipe = to_intel_crtc(crtc)->pipe; |
5578 | pipe = to_intel_crtc(crtc)->pipe; |
5702 | 5579 | ||
5703 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5580 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5704 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5581 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5705 | 5582 | ||
5706 | /* invalidate means busy screen hence upclock */ |
5583 | /* invalidate means busy screen hence upclock */ |
5707 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5584 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5708 | intel_dp_set_drrs_state(dev_priv->dev, |
5585 | intel_dp_set_drrs_state(dev_priv->dev, |
5709 | dev_priv->drrs.dp->attached_connector->panel. |
5586 | dev_priv->drrs.dp->attached_connector->panel. |
5710 | fixed_mode->vrefresh); |
5587 | fixed_mode->vrefresh); |
5711 | 5588 | ||
5712 | mutex_unlock(&dev_priv->drrs.mutex); |
5589 | mutex_unlock(&dev_priv->drrs.mutex); |
5713 | } |
5590 | } |
5714 | 5591 | ||
5715 | /** |
5592 | /** |
5716 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5593 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5717 | * @dev: DRM device |
5594 | * @dev: DRM device |
5718 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5595 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5719 | * |
5596 | * |
5720 | * This function gets called every time rendering on the given planes has |
5597 | * This function gets called every time rendering on the given planes has |
5721 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5598 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5722 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5599 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5723 | * if no other planes are dirty. |
5600 | * if no other planes are dirty. |
5724 | * |
5601 | * |
5725 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5602 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5726 | */ |
5603 | */ |
5727 | void intel_edp_drrs_flush(struct drm_device *dev, |
5604 | void intel_edp_drrs_flush(struct drm_device *dev, |
5728 | unsigned frontbuffer_bits) |
5605 | unsigned frontbuffer_bits) |
5729 | { |
5606 | { |
5730 | struct drm_i915_private *dev_priv = dev->dev_private; |
5607 | struct drm_i915_private *dev_priv = dev->dev_private; |
5731 | struct drm_crtc *crtc; |
5608 | struct drm_crtc *crtc; |
5732 | enum pipe pipe; |
5609 | enum pipe pipe; |
5733 | 5610 | ||
5734 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5611 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5735 | return; |
5612 | return; |
5736 | 5613 | ||
5737 | cancel_delayed_work(&dev_priv->drrs.work); |
5614 | // cancel_delayed_work(&dev_priv->drrs.work); |
5738 | 5615 | ||
5739 | mutex_lock(&dev_priv->drrs.mutex); |
5616 | mutex_lock(&dev_priv->drrs.mutex); |
5740 | if (!dev_priv->drrs.dp) { |
5617 | if (!dev_priv->drrs.dp) { |
5741 | mutex_unlock(&dev_priv->drrs.mutex); |
5618 | mutex_unlock(&dev_priv->drrs.mutex); |
5742 | return; |
5619 | return; |
5743 | } |
5620 | } |
5744 | 5621 | ||
5745 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5622 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5746 | pipe = to_intel_crtc(crtc)->pipe; |
5623 | pipe = to_intel_crtc(crtc)->pipe; |
5747 | 5624 | ||
5748 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5625 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5749 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5626 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5750 | 5627 | ||
5751 | /* flush means busy screen hence upclock */ |
5628 | /* flush means busy screen hence upclock */ |
5752 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5629 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5753 | intel_dp_set_drrs_state(dev_priv->dev, |
5630 | intel_dp_set_drrs_state(dev_priv->dev, |
5754 | dev_priv->drrs.dp->attached_connector->panel. |
5631 | dev_priv->drrs.dp->attached_connector->panel. |
5755 | fixed_mode->vrefresh); |
5632 | fixed_mode->vrefresh); |
5756 | 5633 | ||
5757 | /* |
5634 | /* |
5758 | * flush also means no more activity hence schedule downclock, if all |
5635 | * flush also means no more activity hence schedule downclock, if all |
5759 | * other fbs are quiescent too |
5636 | * other fbs are quiescent too |
5760 | */ |
5637 | */ |
5761 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
5638 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
5762 | schedule_delayed_work(&dev_priv->drrs.work, |
5639 | schedule_delayed_work(&dev_priv->drrs.work, |
5763 | msecs_to_jiffies(1000)); |
5640 | msecs_to_jiffies(1000)); |
5764 | mutex_unlock(&dev_priv->drrs.mutex); |
5641 | mutex_unlock(&dev_priv->drrs.mutex); |
5765 | } |
5642 | } |
5766 | 5643 | ||
5767 | /** |
5644 | /** |
5768 | * DOC: Display Refresh Rate Switching (DRRS) |
5645 | * DOC: Display Refresh Rate Switching (DRRS) |
5769 | * |
5646 | * |
5770 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5647 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5771 | * which enables swtching between low and high refresh rates, |
5648 | * which enables swtching between low and high refresh rates, |
5772 | * dynamically, based on the usage scenario. This feature is applicable |
5649 | * dynamically, based on the usage scenario. This feature is applicable |
5773 | * for internal panels. |
5650 | * for internal panels. |
5774 | * |
5651 | * |
5775 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5652 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5776 | * would list multiple refresh rates for one resolution. |
5653 | * would list multiple refresh rates for one resolution. |
5777 | * |
5654 | * |
5778 | * DRRS is of 2 types - static and seamless. |
5655 | * DRRS is of 2 types - static and seamless. |
5779 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5656 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5780 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5657 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5781 | * Seamless DRRS involves changing RR without any visual effect to the user |
5658 | * Seamless DRRS involves changing RR without any visual effect to the user |
5782 | * and can be used during normal system usage. This is done by programming |
5659 | * and can be used during normal system usage. This is done by programming |
5783 | * certain registers. |
5660 | * certain registers. |
5784 | * |
5661 | * |
5785 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5662 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5786 | * inputs from the panel spec. |
5663 | * inputs from the panel spec. |
5787 | * |
5664 | * |
5788 | * DRRS saves power by switching to low RR based on usage scenarios. |
5665 | * DRRS saves power by switching to low RR based on usage scenarios. |
5789 | * |
5666 | * |
5790 | * eDP DRRS:- |
5667 | * eDP DRRS:- |
5791 | * The implementation is based on frontbuffer tracking implementation. |
5668 | * The implementation is based on frontbuffer tracking implementation. |
5792 | * When there is a disturbance on the screen triggered by user activity or a |
5669 | * When there is a disturbance on the screen triggered by user activity or a |
5793 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5670 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5794 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5671 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5795 | * to low RR is made. |
5672 | * to low RR is made. |
5796 | * For integration with frontbuffer tracking code, |
5673 | * For integration with frontbuffer tracking code, |
5797 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5674 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5798 | * |
5675 | * |
5799 | * DRRS can be further extended to support other internal panels and also |
5676 | * DRRS can be further extended to support other internal panels and also |
5800 | * the scenario of video playback wherein RR is set based on the rate |
5677 | * the scenario of video playback wherein RR is set based on the rate |
5801 | * requested by userspace. |
5678 | * requested by userspace. |
5802 | */ |
5679 | */ |
5803 | 5680 | ||
5804 | /** |
5681 | /** |
5805 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5682 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5806 | * @intel_connector: eDP connector |
5683 | * @intel_connector: eDP connector |
5807 | * @fixed_mode: preferred mode of panel |
5684 | * @fixed_mode: preferred mode of panel |
5808 | * |
5685 | * |
5809 | * This function is called only once at driver load to initialize basic |
5686 | * This function is called only once at driver load to initialize basic |
5810 | * DRRS stuff. |
5687 | * DRRS stuff. |
5811 | * |
5688 | * |
5812 | * Returns: |
5689 | * Returns: |
5813 | * Downclock mode if panel supports it, else return NULL. |
5690 | * Downclock mode if panel supports it, else return NULL. |
5814 | * DRRS support is determined by the presence of downclock mode (apart |
5691 | * DRRS support is determined by the presence of downclock mode (apart |
5815 | * from VBT setting). |
5692 | * from VBT setting). |
5816 | */ |
5693 | */ |
5817 | static struct drm_display_mode * |
5694 | static struct drm_display_mode * |
5818 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5695 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5819 | struct drm_display_mode *fixed_mode) |
5696 | struct drm_display_mode *fixed_mode) |
5820 | { |
5697 | { |
5821 | struct drm_connector *connector = &intel_connector->base; |
5698 | struct drm_connector *connector = &intel_connector->base; |
5822 | struct drm_device *dev = connector->dev; |
5699 | struct drm_device *dev = connector->dev; |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; |
5700 | struct drm_i915_private *dev_priv = dev->dev_private; |
5824 | struct drm_display_mode *downclock_mode = NULL; |
5701 | struct drm_display_mode *downclock_mode = NULL; |
5825 | 5702 | ||
5826 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5703 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5827 | mutex_init(&dev_priv->drrs.mutex); |
5704 | mutex_init(&dev_priv->drrs.mutex); |
5828 | 5705 | ||
5829 | if (INTEL_INFO(dev)->gen <= 6) { |
5706 | if (INTEL_INFO(dev)->gen <= 6) { |
5830 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5707 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5831 | return NULL; |
5708 | return NULL; |
5832 | } |
5709 | } |
5833 | 5710 | ||
5834 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5711 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5835 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5712 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5836 | return NULL; |
5713 | return NULL; |
5837 | } |
5714 | } |
5838 | 5715 | ||
5839 | downclock_mode = intel_find_panel_downclock |
5716 | downclock_mode = intel_find_panel_downclock |
5840 | (dev, fixed_mode, connector); |
5717 | (dev, fixed_mode, connector); |
5841 | 5718 | ||
5842 | if (!downclock_mode) { |
5719 | if (!downclock_mode) { |
5843 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5720 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5844 | return NULL; |
5721 | return NULL; |
5845 | } |
5722 | } |
5846 | 5723 | ||
5847 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5724 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5848 | 5725 | ||
5849 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5726 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5850 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5727 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5851 | return downclock_mode; |
5728 | return downclock_mode; |
5852 | } |
5729 | } |
5853 | 5730 | ||
5854 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5731 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5855 | struct intel_connector *intel_connector) |
5732 | struct intel_connector *intel_connector) |
5856 | { |
5733 | { |
5857 | struct drm_connector *connector = &intel_connector->base; |
5734 | struct drm_connector *connector = &intel_connector->base; |
5858 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5735 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5859 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5736 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5860 | struct drm_device *dev = intel_encoder->base.dev; |
5737 | struct drm_device *dev = intel_encoder->base.dev; |
5861 | struct drm_i915_private *dev_priv = dev->dev_private; |
5738 | struct drm_i915_private *dev_priv = dev->dev_private; |
5862 | struct drm_display_mode *fixed_mode = NULL; |
5739 | struct drm_display_mode *fixed_mode = NULL; |
5863 | struct drm_display_mode *downclock_mode = NULL; |
5740 | struct drm_display_mode *downclock_mode = NULL; |
5864 | bool has_dpcd; |
5741 | bool has_dpcd; |
5865 | struct drm_display_mode *scan; |
5742 | struct drm_display_mode *scan; |
5866 | struct edid *edid; |
5743 | struct edid *edid; |
5867 | enum pipe pipe = INVALID_PIPE; |
5744 | enum pipe pipe = INVALID_PIPE; |
5868 | 5745 | ||
5869 | if (!is_edp(intel_dp)) |
5746 | if (!is_edp(intel_dp)) |
5870 | return true; |
5747 | return true; |
5871 | 5748 | ||
5872 | pps_lock(intel_dp); |
5749 | pps_lock(intel_dp); |
5873 | intel_edp_panel_vdd_sanitize(intel_dp); |
5750 | intel_edp_panel_vdd_sanitize(intel_dp); |
5874 | pps_unlock(intel_dp); |
5751 | pps_unlock(intel_dp); |
5875 | 5752 | ||
5876 | /* Cache DPCD and EDID for edp. */ |
5753 | /* Cache DPCD and EDID for edp. */ |
5877 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5754 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5878 | 5755 | ||
5879 | if (has_dpcd) { |
5756 | if (has_dpcd) { |
5880 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5757 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5881 | dev_priv->no_aux_handshake = |
5758 | dev_priv->no_aux_handshake = |
5882 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5759 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5883 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5760 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5884 | } else { |
5761 | } else { |
5885 | /* if this fails, presume the device is a ghost */ |
5762 | /* if this fails, presume the device is a ghost */ |
5886 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5763 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5887 | return false; |
5764 | return false; |
5888 | } |
5765 | } |
5889 | 5766 | ||
5890 | /* We now know it's not a ghost, init power sequence regs. */ |
5767 | /* We now know it's not a ghost, init power sequence regs. */ |
5891 | pps_lock(intel_dp); |
5768 | pps_lock(intel_dp); |
5892 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5769 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5893 | pps_unlock(intel_dp); |
5770 | pps_unlock(intel_dp); |
5894 | 5771 | ||
5895 | mutex_lock(&dev->mode_config.mutex); |
5772 | mutex_lock(&dev->mode_config.mutex); |
5896 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5773 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5897 | if (edid) { |
5774 | if (edid) { |
5898 | if (drm_add_edid_modes(connector, edid)) { |
5775 | if (drm_add_edid_modes(connector, edid)) { |
5899 | drm_mode_connector_update_edid_property(connector, |
5776 | drm_mode_connector_update_edid_property(connector, |
5900 | edid); |
5777 | edid); |
5901 | drm_edid_to_eld(connector, edid); |
5778 | drm_edid_to_eld(connector, edid); |
5902 | } else { |
5779 | } else { |
5903 | kfree(edid); |
5780 | kfree(edid); |
5904 | edid = ERR_PTR(-EINVAL); |
5781 | edid = ERR_PTR(-EINVAL); |
5905 | } |
5782 | } |
5906 | } else { |
5783 | } else { |
5907 | edid = ERR_PTR(-ENOENT); |
5784 | edid = ERR_PTR(-ENOENT); |
5908 | } |
5785 | } |
5909 | intel_connector->edid = edid; |
5786 | intel_connector->edid = edid; |
5910 | 5787 | ||
5911 | /* prefer fixed mode from EDID if available */ |
5788 | /* prefer fixed mode from EDID if available */ |
5912 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5789 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5913 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5790 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5914 | fixed_mode = drm_mode_duplicate(dev, scan); |
5791 | fixed_mode = drm_mode_duplicate(dev, scan); |
5915 | downclock_mode = intel_dp_drrs_init( |
5792 | downclock_mode = intel_dp_drrs_init( |
5916 | intel_connector, fixed_mode); |
5793 | intel_connector, fixed_mode); |
5917 | break; |
5794 | break; |
5918 | } |
5795 | } |
5919 | } |
5796 | } |
5920 | 5797 | ||
5921 | /* fallback to VBT if available for eDP */ |
5798 | /* fallback to VBT if available for eDP */ |
5922 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5799 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5923 | fixed_mode = drm_mode_duplicate(dev, |
5800 | fixed_mode = drm_mode_duplicate(dev, |
5924 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5801 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5925 | if (fixed_mode) |
5802 | if (fixed_mode) |
5926 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5803 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5927 | } |
5804 | } |
5928 | mutex_unlock(&dev->mode_config.mutex); |
5805 | mutex_unlock(&dev->mode_config.mutex); |
5929 | 5806 | ||
- | 5807 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
|
- | 5808 | // intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
|
5930 | if (IS_VALLEYVIEW(dev)) { |
5809 | // register_reboot_notifier(&intel_dp->edp_notifier); |
5931 | 5810 | ||
5932 | /* |
5811 | /* |
5933 | * Figure out the current pipe for the initial backlight setup. |
5812 | * Figure out the current pipe for the initial backlight setup. |
5934 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5813 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5935 | * fails just assume pipe A. |
5814 | * fails just assume pipe A. |
5936 | */ |
5815 | */ |
5937 | if (IS_CHERRYVIEW(dev)) |
5816 | if (IS_CHERRYVIEW(dev)) |
5938 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5817 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5939 | else |
5818 | else |
5940 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5819 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5941 | 5820 | ||
5942 | if (pipe != PIPE_A && pipe != PIPE_B) |
5821 | if (pipe != PIPE_A && pipe != PIPE_B) |
5943 | pipe = intel_dp->pps_pipe; |
5822 | pipe = intel_dp->pps_pipe; |
5944 | 5823 | ||
5945 | if (pipe != PIPE_A && pipe != PIPE_B) |
5824 | if (pipe != PIPE_A && pipe != PIPE_B) |
5946 | pipe = PIPE_A; |
5825 | pipe = PIPE_A; |
5947 | 5826 | ||
5948 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5827 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5949 | pipe_name(pipe)); |
5828 | pipe_name(pipe)); |
5950 | } |
5829 | } |
5951 | 5830 | ||
5952 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5831 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5953 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5832 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5954 | intel_panel_setup_backlight(connector, pipe); |
5833 | intel_panel_setup_backlight(connector, pipe); |
5955 | 5834 | ||
5956 | return true; |
5835 | return true; |
5957 | } |
5836 | } |
5958 | 5837 | ||
5959 | bool |
5838 | bool |
5960 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5839 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5961 | struct intel_connector *intel_connector) |
5840 | struct intel_connector *intel_connector) |
5962 | { |
5841 | { |
5963 | struct drm_connector *connector = &intel_connector->base; |
5842 | struct drm_connector *connector = &intel_connector->base; |
5964 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5843 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5965 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5844 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5966 | struct drm_device *dev = intel_encoder->base.dev; |
5845 | struct drm_device *dev = intel_encoder->base.dev; |
5967 | struct drm_i915_private *dev_priv = dev->dev_private; |
5846 | struct drm_i915_private *dev_priv = dev->dev_private; |
5968 | enum port port = intel_dig_port->port; |
5847 | enum port port = intel_dig_port->port; |
5969 | int type; |
5848 | int type, ret; |
5970 | 5849 | ||
5971 | intel_dp->pps_pipe = INVALID_PIPE; |
5850 | intel_dp->pps_pipe = INVALID_PIPE; |
5972 | 5851 | ||
5973 | /* intel_dp vfuncs */ |
5852 | /* intel_dp vfuncs */ |
5974 | if (INTEL_INFO(dev)->gen >= 9) |
5853 | if (INTEL_INFO(dev)->gen >= 9) |
5975 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5854 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5976 | else if (IS_VALLEYVIEW(dev)) |
5855 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5977 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5856 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5978 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5857 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5979 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
5858 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
5980 | else if (HAS_PCH_SPLIT(dev)) |
5859 | else if (HAS_PCH_SPLIT(dev)) |
5981 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5860 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5982 | else |
5861 | else |
5983 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
5862 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
5984 | 5863 | ||
5985 | if (INTEL_INFO(dev)->gen >= 9) |
5864 | if (INTEL_INFO(dev)->gen >= 9) |
5986 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5865 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5987 | else |
5866 | else |
5988 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
5867 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
- | 5868 | ||
- | 5869 | if (HAS_DDI(dev)) |
|
- | 5870 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
|
5989 | 5871 | ||
5990 | /* Preserve the current hw state. */ |
5872 | /* Preserve the current hw state. */ |
5991 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
5873 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
5992 | intel_dp->attached_connector = intel_connector; |
5874 | intel_dp->attached_connector = intel_connector; |
5993 | 5875 | ||
5994 | if (intel_dp_is_edp(dev, port)) |
5876 | if (intel_dp_is_edp(dev, port)) |
5995 | type = DRM_MODE_CONNECTOR_eDP; |
5877 | type = DRM_MODE_CONNECTOR_eDP; |
5996 | else |
5878 | else |
5997 | type = DRM_MODE_CONNECTOR_DisplayPort; |
5879 | type = DRM_MODE_CONNECTOR_DisplayPort; |
5998 | 5880 | ||
5999 | /* |
5881 | /* |
6000 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
5882 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
6001 | * for DP the encoder type can be set by the caller to |
5883 | * for DP the encoder type can be set by the caller to |
6002 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
5884 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
6003 | */ |
5885 | */ |
6004 | if (type == DRM_MODE_CONNECTOR_eDP) |
5886 | if (type == DRM_MODE_CONNECTOR_eDP) |
6005 | intel_encoder->type = INTEL_OUTPUT_EDP; |
5887 | intel_encoder->type = INTEL_OUTPUT_EDP; |
6006 | 5888 | ||
6007 | /* eDP only on port B and/or C on vlv/chv */ |
5889 | /* eDP only on port B and/or C on vlv/chv */ |
6008 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && |
5890 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
6009 | port != PORT_B && port != PORT_C)) |
5891 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
6010 | return false; |
5892 | return false; |
6011 | 5893 | ||
6012 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5894 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6013 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
5895 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
6014 | port_name(port)); |
5896 | port_name(port)); |
6015 | 5897 | ||
6016 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
5898 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
6017 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5899 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6018 | 5900 | ||
6019 | connector->interlace_allowed = true; |
5901 | connector->interlace_allowed = true; |
6020 | connector->doublescan_allowed = 0; |
5902 | connector->doublescan_allowed = 0; |
6021 | 5903 | ||
6022 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
5904 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
6023 | edp_panel_vdd_work); |
5905 | edp_panel_vdd_work); |
6024 | 5906 | ||
6025 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
5907 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
6026 | drm_connector_register(connector); |
5908 | drm_connector_register(connector); |
6027 | 5909 | ||
6028 | if (HAS_DDI(dev)) |
5910 | if (HAS_DDI(dev)) |
6029 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5911 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6030 | else |
5912 | else |
6031 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5913 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
6032 | intel_connector->unregister = intel_dp_connector_unregister; |
5914 | intel_connector->unregister = intel_dp_connector_unregister; |
6033 | 5915 | ||
6034 | /* Set up the hotplug pin. */ |
5916 | /* Set up the hotplug pin. */ |
6035 | switch (port) { |
5917 | switch (port) { |
6036 | case PORT_A: |
5918 | case PORT_A: |
6037 | intel_encoder->hpd_pin = HPD_PORT_A; |
5919 | intel_encoder->hpd_pin = HPD_PORT_A; |
6038 | break; |
5920 | break; |
6039 | case PORT_B: |
5921 | case PORT_B: |
6040 | intel_encoder->hpd_pin = HPD_PORT_B; |
5922 | intel_encoder->hpd_pin = HPD_PORT_B; |
6041 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
5923 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
6042 | intel_encoder->hpd_pin = HPD_PORT_A; |
5924 | intel_encoder->hpd_pin = HPD_PORT_A; |
6043 | break; |
5925 | break; |
6044 | case PORT_C: |
5926 | case PORT_C: |
6045 | intel_encoder->hpd_pin = HPD_PORT_C; |
5927 | intel_encoder->hpd_pin = HPD_PORT_C; |
6046 | break; |
5928 | break; |
6047 | case PORT_D: |
5929 | case PORT_D: |
6048 | intel_encoder->hpd_pin = HPD_PORT_D; |
5930 | intel_encoder->hpd_pin = HPD_PORT_D; |
6049 | break; |
5931 | break; |
6050 | case PORT_E: |
5932 | case PORT_E: |
6051 | intel_encoder->hpd_pin = HPD_PORT_E; |
5933 | intel_encoder->hpd_pin = HPD_PORT_E; |
6052 | break; |
5934 | break; |
6053 | default: |
5935 | default: |
6054 | BUG(); |
5936 | BUG(); |
6055 | } |
5937 | } |
6056 | 5938 | ||
6057 | if (is_edp(intel_dp)) { |
5939 | if (is_edp(intel_dp)) { |
6058 | pps_lock(intel_dp); |
5940 | pps_lock(intel_dp); |
6059 | intel_dp_init_panel_power_timestamps(intel_dp); |
5941 | intel_dp_init_panel_power_timestamps(intel_dp); |
6060 | if (IS_VALLEYVIEW(dev)) |
5942 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6061 | vlv_initial_power_sequencer_setup(intel_dp); |
5943 | vlv_initial_power_sequencer_setup(intel_dp); |
6062 | else |
5944 | else |
6063 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5945 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
6064 | pps_unlock(intel_dp); |
5946 | pps_unlock(intel_dp); |
6065 | } |
5947 | } |
6066 | 5948 | ||
- | 5949 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
|
- | 5950 | if (ret) |
|
6067 | intel_dp_aux_init(intel_dp, intel_connector); |
5951 | goto fail; |
6068 | 5952 | ||
6069 | /* init MST on ports that can support it */ |
5953 | /* init MST on ports that can support it */ |
6070 | if (HAS_DP_MST(dev) && |
5954 | if (HAS_DP_MST(dev) && |
6071 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5955 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6072 | intel_dp_mst_encoder_init(intel_dig_port, |
5956 | intel_dp_mst_encoder_init(intel_dig_port, |
6073 | intel_connector->base.base.id); |
5957 | intel_connector->base.base.id); |
6074 | 5958 | ||
6075 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
5959 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
6076 | drm_dp_aux_unregister(&intel_dp->aux); |
- | |
6077 | if (is_edp(intel_dp)) { |
- | |
6078 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
- | |
6079 | /* |
- | |
6080 | * vdd might still be enabled do to the delayed vdd off. |
- | |
6081 | * Make sure vdd is actually turned off here. |
- | |
6082 | */ |
- | |
6083 | pps_lock(intel_dp); |
- | |
6084 | edp_panel_vdd_off_sync(intel_dp); |
5960 | intel_dp_aux_fini(intel_dp); |
6085 | pps_unlock(intel_dp); |
- | |
6086 | } |
- | |
6087 | drm_connector_unregister(connector); |
- | |
6088 | drm_connector_cleanup(connector); |
5961 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
6089 | return false; |
5962 | goto fail; |
6090 | } |
5963 | } |
6091 | 5964 | ||
6092 | intel_dp_add_properties(intel_dp, connector); |
5965 | intel_dp_add_properties(intel_dp, connector); |
6093 | 5966 | ||
6094 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5967 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6095 | * 0xd. Failure to do so will result in spurious interrupts being |
5968 | * 0xd. Failure to do so will result in spurious interrupts being |
6096 | * generated on the port when a cable is not attached. |
5969 | * generated on the port when a cable is not attached. |
6097 | */ |
5970 | */ |
6098 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
5971 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
6099 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
5972 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6100 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
5973 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
6101 | } |
5974 | } |
6102 | 5975 | ||
6103 | i915_debugfs_connector_add(connector); |
5976 | i915_debugfs_connector_add(connector); |
6104 | 5977 | ||
6105 | return true; |
5978 | return true; |
- | 5979 | ||
- | 5980 | fail: |
|
- | 5981 | if (is_edp(intel_dp)) { |
|
- | 5982 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
|
- | 5983 | /* |
|
- | 5984 | * vdd might still be enabled do to the delayed vdd off. |
|
- | 5985 | * Make sure vdd is actually turned off here. |
|
- | 5986 | */ |
|
- | 5987 | pps_lock(intel_dp); |
|
- | 5988 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 5989 | pps_unlock(intel_dp); |
|
- | 5990 | } |
|
- | 5991 | drm_connector_unregister(connector); |
|
- | 5992 | drm_connector_cleanup(connector); |
|
- | 5993 | ||
- | 5994 | return false; |
|
6106 | } |
5995 | } |
- | 5996 | ||
6107 | 5997 | void |
|
6108 | bool intel_dp_init(struct drm_device *dev, |
- | |
6109 | int output_reg, |
5998 | intel_dp_init(struct drm_device *dev, |
6110 | enum port port) |
5999 | i915_reg_t output_reg, enum port port) |
6111 | { |
6000 | { |
6112 | struct drm_i915_private *dev_priv = dev->dev_private; |
6001 | struct drm_i915_private *dev_priv = dev->dev_private; |
6113 | struct intel_digital_port *intel_dig_port; |
6002 | struct intel_digital_port *intel_dig_port; |
6114 | struct intel_encoder *intel_encoder; |
6003 | struct intel_encoder *intel_encoder; |
6115 | struct drm_encoder *encoder; |
6004 | struct drm_encoder *encoder; |
6116 | struct intel_connector *intel_connector; |
6005 | struct intel_connector *intel_connector; |
6117 | 6006 | ||
6118 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6007 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6119 | if (!intel_dig_port) |
6008 | if (!intel_dig_port) |
6120 | return false; |
6009 | return; |
6121 | 6010 | ||
6122 | intel_connector = intel_connector_alloc(); |
6011 | intel_connector = intel_connector_alloc(); |
6123 | if (!intel_connector) |
6012 | if (!intel_connector) |
6124 | goto err_connector_alloc; |
6013 | goto err_connector_alloc; |
6125 | 6014 | ||
6126 | intel_encoder = &intel_dig_port->base; |
6015 | intel_encoder = &intel_dig_port->base; |
6127 | encoder = &intel_encoder->base; |
6016 | encoder = &intel_encoder->base; |
6128 | 6017 | ||
6129 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
6018 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
- | 6019 | DRM_MODE_ENCODER_TMDS, NULL)) |
|
6130 | DRM_MODE_ENCODER_TMDS); |
6020 | goto err_encoder_init; |
6131 | 6021 | ||
6132 | intel_encoder->compute_config = intel_dp_compute_config; |
6022 | intel_encoder->compute_config = intel_dp_compute_config; |
6133 | intel_encoder->disable = intel_disable_dp; |
6023 | intel_encoder->disable = intel_disable_dp; |
6134 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6024 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6135 | intel_encoder->get_config = intel_dp_get_config; |
6025 | intel_encoder->get_config = intel_dp_get_config; |
6136 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6026 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6137 | if (IS_CHERRYVIEW(dev)) { |
6027 | if (IS_CHERRYVIEW(dev)) { |
6138 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6028 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6139 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6029 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6140 | intel_encoder->enable = vlv_enable_dp; |
6030 | intel_encoder->enable = vlv_enable_dp; |
6141 | intel_encoder->post_disable = chv_post_disable_dp; |
6031 | intel_encoder->post_disable = chv_post_disable_dp; |
6142 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6032 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6143 | } else if (IS_VALLEYVIEW(dev)) { |
6033 | } else if (IS_VALLEYVIEW(dev)) { |
6144 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6034 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6145 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6035 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6146 | intel_encoder->enable = vlv_enable_dp; |
6036 | intel_encoder->enable = vlv_enable_dp; |
6147 | intel_encoder->post_disable = vlv_post_disable_dp; |
6037 | intel_encoder->post_disable = vlv_post_disable_dp; |
6148 | } else { |
6038 | } else { |
6149 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6039 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6150 | intel_encoder->enable = g4x_enable_dp; |
6040 | intel_encoder->enable = g4x_enable_dp; |
6151 | if (INTEL_INFO(dev)->gen >= 5) |
6041 | if (INTEL_INFO(dev)->gen >= 5) |
6152 | intel_encoder->post_disable = ilk_post_disable_dp; |
6042 | intel_encoder->post_disable = ilk_post_disable_dp; |
6153 | } |
6043 | } |
6154 | 6044 | ||
6155 | intel_dig_port->port = port; |
6045 | intel_dig_port->port = port; |
6156 | intel_dig_port->dp.output_reg = output_reg; |
6046 | intel_dig_port->dp.output_reg = output_reg; |
6157 | 6047 | ||
6158 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6048 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6159 | if (IS_CHERRYVIEW(dev)) { |
6049 | if (IS_CHERRYVIEW(dev)) { |
6160 | if (port == PORT_D) |
6050 | if (port == PORT_D) |
6161 | intel_encoder->crtc_mask = 1 << 2; |
6051 | intel_encoder->crtc_mask = 1 << 2; |
6162 | else |
6052 | else |
6163 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6053 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6164 | } else { |
6054 | } else { |
6165 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6055 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6166 | } |
6056 | } |
6167 | intel_encoder->cloneable = 0; |
6057 | intel_encoder->cloneable = 0; |
6168 | 6058 | ||
6169 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6059 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6170 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6060 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6171 | 6061 | ||
6172 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6062 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6173 | goto err_init_connector; |
6063 | goto err_init_connector; |
6174 | 6064 | ||
6175 | return true; |
6065 | return; |
6176 | 6066 | ||
6177 | err_init_connector: |
6067 | err_init_connector: |
6178 | drm_encoder_cleanup(encoder); |
6068 | drm_encoder_cleanup(encoder); |
- | 6069 | err_encoder_init: |
|
6179 | kfree(intel_connector); |
6070 | kfree(intel_connector); |
6180 | err_connector_alloc: |
6071 | err_connector_alloc: |
6181 | kfree(intel_dig_port); |
6072 | kfree(intel_dig_port); |
- | 6073 | ||
6182 | return false; |
6074 | return; |
6183 | } |
6075 | } |
6184 | 6076 | ||
6185 | void intel_dp_mst_suspend(struct drm_device *dev) |
6077 | void intel_dp_mst_suspend(struct drm_device *dev) |
6186 | { |
6078 | { |
6187 | struct drm_i915_private *dev_priv = dev->dev_private; |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; |
6188 | int i; |
6080 | int i; |
6189 | 6081 | ||
6190 | /* disable MST */ |
6082 | /* disable MST */ |
6191 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6083 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6192 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6084 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6193 | if (!intel_dig_port) |
6085 | if (!intel_dig_port) |
6194 | continue; |
6086 | continue; |
6195 | 6087 | ||
6196 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6088 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6197 | if (!intel_dig_port->dp.can_mst) |
6089 | if (!intel_dig_port->dp.can_mst) |
6198 | continue; |
6090 | continue; |
6199 | if (intel_dig_port->dp.is_mst) |
6091 | if (intel_dig_port->dp.is_mst) |
6200 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6092 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6201 | } |
6093 | } |
6202 | } |
6094 | } |
6203 | } |
6095 | } |
6204 | 6096 | ||
6205 | void intel_dp_mst_resume(struct drm_device *dev) |
6097 | void intel_dp_mst_resume(struct drm_device *dev) |
6206 | { |
6098 | { |
6207 | struct drm_i915_private *dev_priv = dev->dev_private; |
6099 | struct drm_i915_private *dev_priv = dev->dev_private; |
6208 | int i; |
6100 | int i; |
6209 | 6101 | ||
6210 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6102 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6211 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6103 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6212 | if (!intel_dig_port) |
6104 | if (!intel_dig_port) |
6213 | continue; |
6105 | continue; |
6214 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6106 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6215 | int ret; |
6107 | int ret; |
6216 | 6108 | ||
6217 | if (!intel_dig_port->dp.can_mst) |
6109 | if (!intel_dig_port->dp.can_mst) |
6218 | continue; |
6110 | continue; |
6219 | 6111 | ||
6220 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6112 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6221 | if (ret != 0) { |
6113 | if (ret != 0) { |
6222 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6114 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6223 | } |
6115 | } |
6224 | } |
6116 | } |
6225 | } |
6117 | } |
6226 | }>>><>><>><>><>><>><>>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6118 | }>>><>><>><>><>><>><>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6227 | ><21); |
6119 | ><21); |
6228 | >21); |
6120 | >21); |
6229 | ><21); |
6121 | ><21); |
6230 | >>>>><>=>=><=>=>=>>=>=>>>>>>>=>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |
6122 | >>>>><>=>=><=>=>=>>=>=>>>>>>>>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |