Rev 4560 | Rev 5097 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4560 | Rev 5060 | ||
---|---|---|---|
Line 62... | Line 62... | ||
62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
63 | { DP_LINK_BW_2_7, |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
65 | }; |
65 | }; |
Line -... | Line 66... | ||
- | 66 | ||
- | 67 | /* |
|
- | 68 | * CHV supports eDP 1.4 that have more link rates. |
|
- | 69 | * Below only provides the fixed rate but exclude variable rate. |
|
- | 70 | */ |
|
- | 71 | static const struct dp_link_dpll chv_dpll[] = { |
|
- | 72 | /* |
|
- | 73 | * CHV requires to program fractional division for m2. |
|
- | 74 | * m2 is stored in fixed point format using formula below |
|
- | 75 | * (m2_int << 22) | m2_fraction |
|
- | 76 | */ |
|
- | 77 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ |
|
- | 78 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
|
- | 79 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ |
|
- | 80 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
|
- | 81 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ |
|
- | 82 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
|
- | 83 | }; |
|
66 | 84 | ||
67 | /** |
85 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
86 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
69 | * @intel_dp: DP struct |
87 | * @intel_dp: DP struct |
70 | * |
88 | * |
Line 89... | Line 107... | ||
89 | { |
107 | { |
90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
91 | } |
109 | } |
Line 92... | Line 110... | ||
92 | 110 | ||
- | 111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
|
- | 112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
|
Line 93... | Line 113... | ||
93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
94 | 114 | ||
95 | static int |
115 | int |
96 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
- | 117 | { |
|
Line 97... | Line 118... | ||
97 | { |
118 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
98 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
119 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
99 | 120 | ||
100 | switch (max_link_bw) { |
121 | switch (max_link_bw) { |
101 | case DP_LINK_BW_1_62: |
122 | case DP_LINK_BW_1_62: |
- | 123 | case DP_LINK_BW_2_7: |
|
- | 124 | break; |
|
- | 125 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
|
- | 126 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
|
- | 127 | INTEL_INFO(dev)->gen >= 8) && |
|
102 | case DP_LINK_BW_2_7: |
128 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
103 | break; |
129 | max_link_bw = DP_LINK_BW_5_4; |
104 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
130 | else |
105 | max_link_bw = DP_LINK_BW_2_7; |
131 | max_link_bw = DP_LINK_BW_2_7; |
106 | break; |
132 | break; |
Line 111... | Line 137... | ||
111 | break; |
137 | break; |
112 | } |
138 | } |
113 | return max_link_bw; |
139 | return max_link_bw; |
114 | } |
140 | } |
Line -... | Line 141... | ||
- | 141 | ||
- | 142 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
|
- | 143 | { |
|
- | 144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 145 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 146 | u8 source_max, sink_max; |
|
- | 147 | ||
- | 148 | source_max = 4; |
|
- | 149 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
|
- | 150 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
|
- | 151 | source_max = 2; |
|
- | 152 | ||
- | 153 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
|
- | 154 | ||
- | 155 | return min(source_max, sink_max); |
|
- | 156 | } |
|
115 | 157 | ||
116 | /* |
158 | /* |
117 | * The units on the numbers in the next two are... bizarre. Examples will |
159 | * The units on the numbers in the next two are... bizarre. Examples will |
118 | * make it clearer; this one parallels an example in the eDP spec. |
160 | * make it clearer; this one parallels an example in the eDP spec. |
119 | * |
161 | * |
Line 161... | Line 203... | ||
161 | 203 | ||
162 | target_clock = fixed_mode->clock; |
204 | target_clock = fixed_mode->clock; |
Line 163... | Line 205... | ||
163 | } |
205 | } |
164 | 206 | ||
Line 165... | Line 207... | ||
165 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
207 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
166 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
208 | max_lanes = intel_dp_max_lane_count(intel_dp); |
Line 167... | Line 209... | ||
167 | 209 | ||
Line 292... | Line 334... | ||
292 | return PCH_PP_STATUS; |
334 | return PCH_PP_STATUS; |
293 | else |
335 | else |
294 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
336 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
295 | } |
337 | } |
Line -... | Line 338... | ||
- | 338 | ||
296 | 339 | ||
297 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
340 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
298 | { |
341 | { |
299 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
342 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 300... | Line 343... | ||
300 | struct drm_i915_private *dev_priv = dev->dev_private; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
301 | 344 | ||
Line 302... | Line 345... | ||
302 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
345 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
303 | } |
346 | } |
304 | 347 | ||
305 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
348 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
- | 349 | { |
|
- | 350 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 351 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line -... | Line 352... | ||
- | 352 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 353 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
306 | { |
354 | enum intel_display_power_domain power_domain; |
307 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
355 | |
Line 308... | Line 356... | ||
308 | struct drm_i915_private *dev_priv = dev->dev_private; |
356 | power_domain = intel_display_port_power_domain(intel_encoder); |
309 | 357 | return intel_display_power_enabled(dev_priv, power_domain) && |
|
310 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
358 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
Line 317... | Line 365... | ||
317 | struct drm_i915_private *dev_priv = dev->dev_private; |
365 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 318... | Line 366... | ||
318 | 366 | ||
319 | if (!is_edp(intel_dp)) |
367 | if (!is_edp(intel_dp)) |
Line 320... | Line 368... | ||
320 | return; |
368 | return; |
321 | 369 | ||
322 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
370 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
323 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
371 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
324 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
372 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
325 | I915_READ(_pp_stat_reg(intel_dp)), |
373 | I915_READ(_pp_stat_reg(intel_dp)), |
Line 349... | Line 397... | ||
349 | #undef C |
397 | #undef C |
Line 350... | Line 398... | ||
350 | 398 | ||
351 | return status; |
399 | return status; |
Line 352... | Line 400... | ||
352 | } |
400 | } |
353 | - | ||
354 | static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, |
401 | |
355 | int index) |
402 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
356 | { |
403 | { |
357 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
Line 358... | Line -... | ||
358 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | |
359 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
360 | - | ||
361 | /* The clock divider is based off the hrawclk, |
404 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
362 | * and would like to run at 2MHz. So, take the |
405 | struct drm_device *dev = intel_dig_port->base.base.dev; |
363 | * hrawclk value and divide by 2 and use that |
406 | |
364 | * |
407 | /* |
365 | * Note that PCH attached eDP panels should use a 125MHz input |
408 | * The clock divider is based off the hrawclk, and would like to run at |
- | 409 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
|
- | 410 | */ |
|
- | 411 | return index ? 0 : intel_hrawclk(dev) / 2; |
|
- | 412 | } |
|
366 | * clock divider. |
413 | |
367 | */ |
414 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
- | 415 | { |
|
368 | if (IS_VALLEYVIEW(dev)) { |
416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
369 | return index ? 0 : 100; |
417 | struct drm_device *dev = intel_dig_port->base.base.dev; |
370 | } else if (intel_dig_port->port == PORT_A) { |
- | |
- | 418 | ||
371 | if (index) |
419 | if (index) |
372 | return 0; |
420 | return 0; |
373 | if (HAS_DDI(dev)) |
421 | |
374 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
422 | if (intel_dig_port->port == PORT_A) { |
375 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
423 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
- | 424 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
|
- | 425 | else |
|
- | 426 | return 225; /* eDP input clock at 450Mhz */ |
|
- | 427 | } else { |
|
- | 428 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
|
- | 429 | } |
|
- | 430 | } |
|
- | 431 | ||
- | 432 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
- | 433 | { |
|
- | 434 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 435 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 436 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 437 | ||
- | 438 | if (intel_dig_port->port == PORT_A) { |
|
376 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
439 | if (index) |
377 | else |
440 | return 0; |
378 | return 225; /* eDP input clock at 450Mhz */ |
441 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
379 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
442 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
380 | /* Workaround for non-ULT HSW */ |
443 | /* Workaround for non-ULT HSW */ |
381 | switch (index) { |
444 | switch (index) { |
382 | case 0: return 63; |
445 | case 0: return 63; |
383 | case 1: return 72; |
- | |
384 | default: return 0; |
- | |
385 | } |
446 | case 1: return 72; |
386 | } else if (HAS_PCH_SPLIT(dev)) { |
447 | default: return 0; |
387 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
448 | } |
388 | } else { |
449 | } else { |
Line -... | Line 450... | ||
- | 450 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
|
- | 451 | } |
|
- | 452 | } |
|
- | 453 | ||
- | 454 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
- | 455 | { |
|
- | 456 | return index ? 0 : 100; |
|
- | 457 | } |
|
- | 458 | ||
- | 459 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
|
- | 460 | bool has_aux_irq, |
|
- | 461 | int send_bytes, |
|
- | 462 | uint32_t aux_clock_divider) |
|
- | 463 | { |
|
- | 464 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 465 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 466 | uint32_t precharge, timeout; |
|
- | 467 | ||
- | 468 | if (IS_GEN6(dev)) |
|
- | 469 | precharge = 3; |
|
- | 470 | else |
|
- | 471 | precharge = 5; |
|
- | 472 | ||
- | 473 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
|
- | 474 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
|
- | 475 | else |
|
- | 476 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
|
- | 477 | ||
- | 478 | return DP_AUX_CH_CTL_SEND_BUSY | |
|
- | 479 | DP_AUX_CH_CTL_DONE | |
|
- | 480 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
|
- | 481 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
|
- | 482 | timeout | |
|
- | 483 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
|
- | 484 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
|
389 | return index ? 0 :intel_hrawclk(dev) / 2; |
485 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
390 | } |
486 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
391 | } |
487 | } |
392 | 488 | ||
393 | static int |
489 | static int |
Line 401... | Line 497... | ||
401 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
497 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
402 | uint32_t ch_data = ch_ctl + 4; |
498 | uint32_t ch_data = ch_ctl + 4; |
403 | uint32_t aux_clock_divider; |
499 | uint32_t aux_clock_divider; |
404 | int i, ret, recv_bytes; |
500 | int i, ret, recv_bytes; |
405 | uint32_t status; |
501 | uint32_t status; |
406 | int try, precharge, clock = 0; |
502 | int try, clock = 0; |
407 | bool has_aux_irq = true; |
503 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
408 | uint32_t timeout; |
504 | bool vdd; |
- | 505 | ||
- | 506 | vdd = _edp_panel_vdd_on(intel_dp); |
|
Line 409... | Line 507... | ||
409 | 507 | ||
410 | /* dp aux is extremely sensitive to irq latency, hence request the |
508 | /* dp aux is extremely sensitive to irq latency, hence request the |
411 | * lowest possible wakeup latency and so prevent the cpu from going into |
509 | * lowest possible wakeup latency and so prevent the cpu from going into |
412 | * deep sleep states. |
510 | * deep sleep states. |
413 | */ |
- | |
Line 414... | Line 511... | ||
414 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
511 | */ |
Line 415... | Line -... | ||
415 | - | ||
416 | intel_dp_check_edp(intel_dp); |
- | |
417 | - | ||
418 | if (IS_GEN6(dev)) |
- | |
419 | precharge = 3; |
- | |
420 | else |
- | |
421 | precharge = 5; |
- | |
422 | - | ||
423 | if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL) |
- | |
424 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
- | |
425 | else |
512 | |
Line 426... | Line 513... | ||
426 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
513 | intel_dp_check_edp(intel_dp); |
427 | 514 | ||
428 | intel_aux_display_runtime_get(dev_priv); |
515 | intel_aux_display_runtime_get(dev_priv); |
Line 446... | Line 533... | ||
446 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
533 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
447 | ret = -E2BIG; |
534 | ret = -E2BIG; |
448 | goto out; |
535 | goto out; |
449 | } |
536 | } |
Line 450... | Line 537... | ||
450 | 537 | ||
- | 538 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
|
- | 539 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
|
- | 540 | has_aux_irq, |
|
- | 541 | send_bytes, |
|
- | 542 | aux_clock_divider); |
|
451 | while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { |
543 | |
452 | /* Must try at least 3 times according to DP spec */ |
544 | /* Must try at least 3 times according to DP spec */ |
453 | for (try = 0; try < 5; try++) { |
545 | for (try = 0; try < 5; try++) { |
454 | /* Load the send data into the aux channel data registers */ |
546 | /* Load the send data into the aux channel data registers */ |
455 | for (i = 0; i < send_bytes; i += 4) |
547 | for (i = 0; i < send_bytes; i += 4) |
456 | I915_WRITE(ch_data + i, |
548 | I915_WRITE(ch_data + i, |
Line 457... | Line 549... | ||
457 | pack_aux(send + i, send_bytes - i)); |
549 | pack_aux(send + i, send_bytes - i)); |
458 | 550 | ||
459 | /* Send the command and wait for it to complete */ |
- | |
460 | I915_WRITE(ch_ctl, |
- | |
461 | DP_AUX_CH_CTL_SEND_BUSY | |
- | |
462 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
- | |
463 | timeout | |
- | |
464 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
- | |
465 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
- | |
466 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
- | |
467 | DP_AUX_CH_CTL_DONE | |
- | |
Line 468... | Line 551... | ||
468 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
551 | /* Send the command and wait for it to complete */ |
Line 469... | Line 552... | ||
469 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
552 | I915_WRITE(ch_ctl, send_ctl); |
470 | 553 | ||
Line 523... | Line 606... | ||
523 | ret = recv_bytes; |
606 | ret = recv_bytes; |
524 | out: |
607 | out: |
525 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
608 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
526 | intel_aux_display_runtime_put(dev_priv); |
609 | intel_aux_display_runtime_put(dev_priv); |
Line -... | Line 610... | ||
- | 610 | ||
- | 611 | if (vdd) |
|
- | 612 | edp_panel_vdd_off(intel_dp, false); |
|
527 | 613 | ||
528 | return ret; |
614 | return ret; |
Line -... | Line 615... | ||
- | 615 | } |
|
529 | } |
616 | |
530 | 617 | #define BARE_ADDRESS_SIZE 3 |
|
531 | /* Write data to the aux channel in native mode */ |
618 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
532 | static int |
- | |
533 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
619 | static ssize_t |
- | 620 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
|
- | 621 | { |
|
- | 622 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
|
534 | uint16_t address, uint8_t *send, int send_bytes) |
623 | uint8_t txbuf[20], rxbuf[20]; |
535 | { |
- | |
536 | int ret; |
- | |
537 | uint8_t msg[20]; |
- | |
Line -... | Line 624... | ||
- | 624 | size_t txsize, rxsize; |
|
- | 625 | int ret; |
|
- | 626 | ||
- | 627 | txbuf[0] = msg->request << 4; |
|
- | 628 | txbuf[1] = msg->address >> 8; |
|
- | 629 | txbuf[2] = msg->address & 0xff; |
|
- | 630 | txbuf[3] = msg->size - 1; |
|
- | 631 | ||
- | 632 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
|
- | 633 | case DP_AUX_NATIVE_WRITE: |
|
- | 634 | case DP_AUX_I2C_WRITE: |
|
538 | int msg_bytes; |
635 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
539 | uint8_t ack; |
636 | rxsize = 1; |
Line 540... | Line -... | ||
540 | - | ||
541 | if (WARN_ON(send_bytes > 16)) |
- | |
542 | return -E2BIG; |
- | |
543 | - | ||
544 | intel_dp_check_edp(intel_dp); |
- | |
545 | msg[0] = DP_AUX_NATIVE_WRITE << 4; |
- | |
546 | msg[1] = address >> 8; |
- | |
547 | msg[2] = address & 0xff; |
- | |
548 | msg[3] = send_bytes - 1; |
637 | |
549 | memcpy(&msg[4], send, send_bytes); |
- | |
550 | msg_bytes = send_bytes + 4; |
- | |
551 | for (;;) { |
- | |
552 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
- | |
553 | if (ret < 0) |
- | |
554 | return ret; |
- | |
555 | ack >>= 4; |
- | |
556 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) |
- | |
557 | break; |
- | |
558 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
- | |
559 | udelay(100); |
- | |
560 | else |
- | |
Line 561... | Line 638... | ||
561 | return -EIO; |
638 | if (WARN_ON(txsize > 20)) |
562 | } |
639 | return -E2BIG; |
563 | return send_bytes; |
- | |
564 | } |
640 | |
565 | 641 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
|
566 | /* Write a single byte to the aux channel in native mode */ |
642 | |
- | 643 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
|
567 | static int |
644 | if (ret > 0) { |
- | 645 | msg->reply = rxbuf[0] >> 4; |
|
Line 568... | Line 646... | ||
568 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
646 | |
569 | uint16_t address, uint8_t byte) |
647 | /* Return payload size. */ |
570 | { |
- | |
571 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
648 | ret = msg->size; |
572 | } |
- | |
573 | - | ||
574 | /* read bytes from a native aux channel */ |
649 | } |
575 | static int |
- | |
576 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
- | |
577 | uint16_t address, uint8_t *recv, int recv_bytes) |
- | |
578 | { |
- | |
Line 579... | Line 650... | ||
579 | uint8_t msg[4]; |
650 | break; |
580 | int msg_bytes; |
651 | |
Line 581... | Line 652... | ||
581 | uint8_t reply[20]; |
652 | case DP_AUX_NATIVE_READ: |
582 | int reply_bytes; |
653 | case DP_AUX_I2C_READ: |
583 | uint8_t ack; |
654 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
- | 655 | rxsize = msg->size + 1; |
|
- | 656 | ||
- | 657 | if (WARN_ON(rxsize > 20)) |
|
- | 658 | return -E2BIG; |
|
584 | int ret; |
659 | |
- | 660 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
|
- | 661 | if (ret > 0) { |
|
585 | 662 | msg->reply = rxbuf[0] >> 4; |
|
- | 663 | /* |
|
- | 664 | * Assume happy day, and copy the data. The caller is |
|
Line 586... | Line 665... | ||
586 | if (WARN_ON(recv_bytes > 19)) |
665 | * expected to check msg->reply before touching it. |
587 | return -E2BIG; |
666 | * |
- | 667 | * Return payload size. |
|
- | 668 | */ |
|
Line 588... | Line -... | ||
588 | - | ||
589 | intel_dp_check_edp(intel_dp); |
- | |
590 | msg[0] = DP_AUX_NATIVE_READ << 4; |
- | |
591 | msg[1] = address >> 8; |
- | |
592 | msg[2] = address & 0xff; |
- | |
593 | msg[3] = recv_bytes - 1; |
- | |
594 | 669 | ret--; |
|
595 | msg_bytes = 4; |
- | |
596 | reply_bytes = recv_bytes + 1; |
- | |
597 | - | ||
598 | for (;;) { |
- | |
599 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
- | |
600 | reply, reply_bytes); |
- | |
601 | if (ret == 0) |
- | |
602 | return -EPROTO; |
- | |
603 | if (ret < 0) |
- | |
604 | return ret; |
- | |
605 | ack = reply[0] >> 4; |
670 | memcpy(msg->buffer, rxbuf + 1, ret); |
Line 606... | Line 671... | ||
606 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { |
671 | } |
607 | memcpy(recv, reply + 1, ret - 1); |
672 | break; |
608 | return ret - 1; |
- | |
609 | } |
673 | |
610 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
674 | default: |
611 | udelay(100); |
675 | ret = -EINVAL; |
612 | else |
- | |
613 | return -EIO; |
- | |
614 | } |
676 | break; |
615 | } |
- | |
616 | 677 | } |
|
617 | static int |
- | |
618 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
- | |
619 | uint8_t write_byte, uint8_t *read_byte) |
- | |
620 | { |
678 | |
Line 621... | Line -... | ||
621 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
- | |
622 | struct intel_dp *intel_dp = container_of(adapter, |
- | |
623 | struct intel_dp, |
- | |
624 | adapter); |
- | |
625 | uint16_t address = algo_data->address; |
- | |
626 | uint8_t msg[5]; |
- | |
627 | uint8_t reply[2]; |
- | |
628 | unsigned retry; |
- | |
629 | int msg_bytes; |
- | |
630 | int reply_bytes; |
- | |
631 | int ret; |
- | |
632 | - | ||
633 | ironlake_edp_panel_vdd_on(intel_dp); |
- | |
634 | intel_dp_check_edp(intel_dp); |
- | |
635 | /* Set up the command byte */ |
679 | return ret; |
636 | if (mode & MODE_I2C_READ) |
680 | } |
637 | msg[0] = DP_AUX_I2C_READ << 4; |
- | |
638 | else |
681 | |
639 | msg[0] = DP_AUX_I2C_WRITE << 4; |
682 | static void |
640 | - | ||
641 | if (!(mode & MODE_I2C_STOP)) |
683 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
642 | msg[0] |= DP_AUX_I2C_MOT << 4; |
684 | { |
643 | - | ||
644 | msg[1] = address >> 8; |
685 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
645 | msg[2] = address; |
686 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
646 | 687 | enum port port = intel_dig_port->port; |
|
647 | switch (mode) { |
688 | const char *name = NULL; |
648 | case MODE_I2C_WRITE: |
689 | int ret; |
649 | msg[3] = 0; |
690 | |
650 | msg[4] = write_byte; |
691 | switch (port) { |
651 | msg_bytes = 5; |
- | |
652 | reply_bytes = 1; |
- | |
653 | break; |
- | |
654 | case MODE_I2C_READ: |
- | |
655 | msg[3] = 0; |
- | |
656 | msg_bytes = 4; |
- | |
657 | reply_bytes = 2; |
- | |
658 | break; |
- | |
659 | default: |
- | |
660 | msg_bytes = 3; |
- | |
661 | reply_bytes = 1; |
- | |
662 | break; |
692 | case PORT_A: |
663 | } |
693 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
664 | 694 | name = "DPDDC-A"; |
|
665 | /* |
- | |
666 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is |
- | |
667 | * required to retry at least seven times upon receiving AUX_DEFER |
- | |
668 | * before giving up the AUX transaction. |
- | |
669 | */ |
- | |
670 | for (retry = 0; retry < 7; retry++) { |
- | |
671 | ret = intel_dp_aux_ch(intel_dp, |
- | |
672 | msg, msg_bytes, |
695 | break; |
673 | reply, reply_bytes); |
- | |
674 | if (ret < 0) { |
- | |
675 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
- | |
676 | goto out; |
- | |
677 | } |
- | |
678 | - | ||
679 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
- | |
680 | case DP_AUX_NATIVE_REPLY_ACK: |
- | |
681 | /* I2C-over-AUX Reply field is only valid |
- | |
682 | * when paired with AUX ACK. |
- | |
683 | */ |
- | |
684 | break; |
- | |
685 | case DP_AUX_NATIVE_REPLY_NACK: |
- | |
686 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
- | |
687 | ret = -EREMOTEIO; |
696 | case PORT_B: |
688 | goto out; |
- | |
689 | case DP_AUX_NATIVE_REPLY_DEFER: |
- | |
690 | /* |
- | |
691 | * For now, just give more slack to branch devices. We |
697 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
692 | * could check the DPCD for I2C bit rate capabilities, |
698 | name = "DPDDC-B"; |
Line 693... | Line -... | ||
693 | * and if available, adjust the interval. We could also |
- | |
694 | * be more careful with DP-to-Legacy adapters where a |
- | |
695 | * long legacy cable may force very low I2C bit rates. |
- | |
696 | */ |
- | |
697 | udelay(400); |
- | |
698 | continue; |
- | |
699 | default: |
- | |
700 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
- | |
701 | reply[0]); |
- | |
702 | ret = -EREMOTEIO; |
- | |
703 | goto out; |
- | |
704 | } |
- | |
705 | - | ||
706 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { |
699 | break; |
707 | case DP_AUX_I2C_REPLY_ACK: |
- | |
708 | if (mode == MODE_I2C_READ) { |
- | |
709 | *read_byte = reply[1]; |
700 | case PORT_C: |
710 | } |
- | |
711 | ret = reply_bytes - 1; |
- | |
712 | goto out; |
- | |
713 | case DP_AUX_I2C_REPLY_NACK: |
- | |
Line 714... | Line 701... | ||
714 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
701 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
715 | ret = -EREMOTEIO; |
702 | name = "DPDDC-C"; |
- | 703 | break; |
|
Line 716... | Line 704... | ||
716 | goto out; |
704 | case PORT_D: |
717 | case DP_AUX_I2C_REPLY_DEFER: |
705 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
- | 706 | name = "DPDDC-D"; |
|
- | 707 | break; |
|
- | 708 | default: |
|
718 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
709 | BUG(); |
- | 710 | } |
|
719 | udelay(100); |
711 | |
Line 720... | Line 712... | ||
720 | break; |
712 | if (!HAS_DDI(dev)) |
721 | default: |
713 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
722 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
- | |
723 | ret = -EREMOTEIO; |
714 | |
724 | goto out; |
715 | intel_dp->aux.name = name; |
Line 725... | Line -... | ||
725 | } |
- | |
726 | } |
- | |
727 | - | ||
728 | DRM_ERROR("too many retries, giving up\n"); |
716 | intel_dp->aux.dev = dev->dev; |
729 | ret = -EREMOTEIO; |
717 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
730 | - | ||
731 | out: |
- | |
732 | ironlake_edp_panel_vdd_off(intel_dp, false); |
- | |
733 | return ret; |
- | |
734 | } |
- | |
735 | - | ||
736 | static int |
- | |
Line -... | Line 718... | ||
- | 718 | ||
- | 719 | ||
- | 720 | ret = drm_dp_aux_register(&intel_dp->aux); |
|
- | 721 | if (ret < 0) { |
|
- | 722 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
|
737 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
723 | name, ret); |
- | 724 | return; |
|
- | 725 | } |
|
- | 726 | } |
|
- | 727 | ||
- | 728 | static void |
|
- | 729 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
|
738 | struct intel_connector *intel_connector, const char *name) |
730 | { |
- | 731 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
|
739 | { |
732 | |
Line 740... | Line 733... | ||
740 | int ret; |
733 | intel_connector_unregister(intel_connector); |
741 | 734 | } |
|
742 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
735 | |
Line 765... | Line 758... | ||
765 | int i, count = 0; |
758 | int i, count = 0; |
Line 766... | Line 759... | ||
766 | 759 | ||
767 | if (IS_G4X(dev)) { |
760 | if (IS_G4X(dev)) { |
768 | divisor = gen4_dpll; |
761 | divisor = gen4_dpll; |
769 | count = ARRAY_SIZE(gen4_dpll); |
- | |
770 | } else if (IS_HASWELL(dev)) { |
- | |
771 | /* Haswell has special-purpose DP DDI clocks. */ |
762 | count = ARRAY_SIZE(gen4_dpll); |
772 | } else if (HAS_PCH_SPLIT(dev)) { |
763 | } else if (HAS_PCH_SPLIT(dev)) { |
773 | divisor = pch_dpll; |
764 | divisor = pch_dpll; |
- | 765 | count = ARRAY_SIZE(pch_dpll); |
|
- | 766 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 767 | divisor = chv_dpll; |
|
774 | count = ARRAY_SIZE(pch_dpll); |
768 | count = ARRAY_SIZE(chv_dpll); |
775 | } else if (IS_VALLEYVIEW(dev)) { |
769 | } else if (IS_VALLEYVIEW(dev)) { |
776 | divisor = vlv_dpll; |
770 | divisor = vlv_dpll; |
777 | count = ARRAY_SIZE(vlv_dpll); |
771 | count = ARRAY_SIZE(vlv_dpll); |
Line 786... | Line 780... | ||
786 | } |
780 | } |
787 | } |
781 | } |
788 | } |
782 | } |
789 | } |
783 | } |
Line -... | Line 784... | ||
- | 784 | ||
- | 785 | static void |
|
- | 786 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) |
|
- | 787 | { |
|
- | 788 | struct drm_device *dev = crtc->base.dev; |
|
- | 789 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 790 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
|
- | 791 | ||
- | 792 | I915_WRITE(PIPE_DATA_M2(transcoder), |
|
- | 793 | TU_SIZE(m_n->tu) | m_n->gmch_m); |
|
- | 794 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); |
|
- | 795 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); |
|
- | 796 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); |
|
- | 797 | } |
|
790 | 798 | ||
791 | bool |
799 | bool |
792 | intel_dp_compute_config(struct intel_encoder *encoder, |
800 | intel_dp_compute_config(struct intel_encoder *encoder, |
793 | struct intel_crtc_config *pipe_config) |
801 | struct intel_crtc_config *pipe_config) |
794 | { |
802 | { |
Line 798... | Line 806... | ||
798 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
799 | enum port port = dp_to_dig_port(intel_dp)->port; |
807 | enum port port = dp_to_dig_port(intel_dp)->port; |
800 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
808 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
801 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
809 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
802 | int lane_count, clock; |
810 | int lane_count, clock; |
- | 811 | int min_lane_count = 1; |
|
803 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
812 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
- | 813 | /* Conveniently, the link BW constants become indices with a shift...*/ |
|
- | 814 | int min_clock = 0; |
|
804 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
815 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
805 | int bpp, mode_rate; |
816 | int bpp, mode_rate; |
806 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
817 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
807 | int link_avail, link_clock; |
818 | int link_avail, link_clock; |
Line 808... | Line 819... | ||
808 | 819 | ||
809 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
820 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Line 810... | Line 821... | ||
810 | pipe_config->has_pch_encoder = true; |
821 | pipe_config->has_pch_encoder = true; |
- | 822 | ||
Line 811... | Line 823... | ||
811 | 823 | pipe_config->has_dp_encoder = true; |
|
812 | pipe_config->has_dp_encoder = true; |
824 | pipe_config->has_audio = intel_dp->has_audio; |
813 | 825 | ||
814 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
826 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Line 831... | Line 843... | ||
831 | adjusted_mode->crtc_clock); |
843 | adjusted_mode->crtc_clock); |
Line 832... | Line 844... | ||
832 | 844 | ||
833 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
845 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
834 | * bpc in between. */ |
846 | * bpc in between. */ |
835 | bpp = pipe_config->pipe_bpp; |
847 | bpp = pipe_config->pipe_bpp; |
836 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
848 | if (is_edp(intel_dp)) { |
837 | dev_priv->vbt.edp_bpp < bpp) { |
849 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { |
838 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
850 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
839 | dev_priv->vbt.edp_bpp); |
851 | dev_priv->vbt.edp_bpp); |
840 | bpp = dev_priv->vbt.edp_bpp; |
852 | bpp = dev_priv->vbt.edp_bpp; |
Line -... | Line 853... | ||
- | 853 | } |
|
- | 854 | ||
- | 855 | if (IS_BROADWELL(dev)) { |
|
- | 856 | /* Yes, it's an ugly hack. */ |
|
- | 857 | min_lane_count = max_lane_count; |
|
- | 858 | DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", |
|
- | 859 | min_lane_count); |
|
- | 860 | } else if (dev_priv->vbt.edp_lanes) { |
|
- | 861 | min_lane_count = min(dev_priv->vbt.edp_lanes, |
|
- | 862 | max_lane_count); |
|
- | 863 | DRM_DEBUG_KMS("using min %u lanes per VBT\n", |
|
- | 864 | min_lane_count); |
|
- | 865 | } |
|
- | 866 | ||
- | 867 | if (dev_priv->vbt.edp_rate) { |
|
- | 868 | min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); |
|
- | 869 | DRM_DEBUG_KMS("using min %02x link bw per VBT\n", |
|
- | 870 | bws[min_clock]); |
|
- | 871 | } |
|
841 | } |
872 | } |
842 | 873 | ||
843 | for (; bpp >= 6*3; bpp -= 2*3) { |
874 | for (; bpp >= 6*3; bpp -= 2*3) { |
Line 844... | Line 875... | ||
844 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
875 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
845 | bpp); |
876 | bpp); |
846 | 877 | ||
847 | for (clock = 0; clock <= max_clock; clock++) { |
878 | for (clock = min_clock; clock <= max_clock; clock++) { |
848 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
879 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { |
Line 849... | Line 880... | ||
849 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
880 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
Line 889... | Line 920... | ||
889 | intel_link_compute_m_n(bpp, lane_count, |
920 | intel_link_compute_m_n(bpp, lane_count, |
890 | adjusted_mode->crtc_clock, |
921 | adjusted_mode->crtc_clock, |
891 | pipe_config->port_clock, |
922 | pipe_config->port_clock, |
892 | &pipe_config->dp_m_n); |
923 | &pipe_config->dp_m_n); |
Line -... | Line 924... | ||
- | 924 | ||
- | 925 | if (intel_connector->panel.downclock_mode != NULL && |
|
- | 926 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
|
- | 927 | intel_link_compute_m_n(bpp, lane_count, |
|
- | 928 | intel_connector->panel.downclock_mode->clock, |
|
- | 929 | pipe_config->port_clock, |
|
- | 930 | &pipe_config->dp_m2_n2); |
|
- | 931 | } |
|
- | 932 | ||
- | 933 | if (HAS_DDI(dev)) |
|
- | 934 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
|
893 | 935 | else |
|
Line 894... | Line 936... | ||
894 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
936 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
895 | 937 | ||
Line 924... | Line 966... | ||
924 | 966 | ||
925 | POSTING_READ(DP_A); |
967 | POSTING_READ(DP_A); |
926 | udelay(500); |
968 | udelay(500); |
Line 927... | Line 969... | ||
927 | } |
969 | } |
928 | 970 | ||
929 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
971 | static void intel_dp_prepare(struct intel_encoder *encoder) |
930 | { |
972 | { |
931 | struct drm_device *dev = encoder->base.dev; |
973 | struct drm_device *dev = encoder->base.dev; |
932 | struct drm_i915_private *dev_priv = dev->dev_private; |
974 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 959... | Line 1001... | ||
959 | 1001 | ||
960 | /* Handle DP bits in common between all three register formats */ |
1002 | /* Handle DP bits in common between all three register formats */ |
961 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1003 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Line 962... | Line 1004... | ||
962 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
1004 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
963 | 1005 | ||
964 | if (intel_dp->has_audio) { |
1006 | if (crtc->config.has_audio) { |
965 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
1007 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
966 | pipe_name(crtc->pipe)); |
1008 | pipe_name(crtc->pipe)); |
967 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
1009 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Line 992... | Line 1034... | ||
992 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1034 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
Line 993... | Line 1035... | ||
993 | 1035 | ||
994 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1036 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Line -... | Line 1037... | ||
- | 1037 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
|
995 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1038 | |
996 | 1039 | if (!IS_CHERRYVIEW(dev)) { |
|
997 | if (crtc->pipe == 1) |
1040 | if (crtc->pipe == 1) |
- | 1041 | intel_dp->DP |= DP_PIPEB_SELECT; |
|
- | 1042 | } else { |
|
- | 1043 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
|
998 | intel_dp->DP |= DP_PIPEB_SELECT; |
1044 | } |
999 | } else { |
1045 | } else { |
1000 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
- | |
1001 | } |
- | |
1002 | - | ||
1003 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
1046 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Line 1004... | Line 1047... | ||
1004 | ironlake_set_pll_cpu_edp(intel_dp); |
1047 | } |
1005 | } |
1048 | } |
Line 1006... | Line 1049... | ||
1006 | 1049 | ||
1007 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1050 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
Line 1008... | Line 1051... | ||
1008 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1051 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1009 | 1052 | ||
Line 1010... | Line 1053... | ||
1010 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1053 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1011 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1054 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1012 | 1055 | ||
1013 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1056 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1014 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1057 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1015 | 1058 | ||
Line 1036... | Line 1079... | ||
1036 | } |
1079 | } |
Line 1037... | Line 1080... | ||
1037 | 1080 | ||
1038 | DRM_DEBUG_KMS("Wait complete\n"); |
1081 | DRM_DEBUG_KMS("Wait complete\n"); |
Line 1039... | Line 1082... | ||
1039 | } |
1082 | } |
1040 | 1083 | ||
1041 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
1084 | static void wait_panel_on(struct intel_dp *intel_dp) |
1042 | { |
1085 | { |
1043 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1086 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Line 1044... | Line 1087... | ||
1044 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1087 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1045 | } |
1088 | } |
1046 | 1089 | ||
1047 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
1090 | static void wait_panel_off(struct intel_dp *intel_dp) |
1048 | { |
1091 | { |
Line 1049... | Line 1092... | ||
1049 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1092 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1050 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1093 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1051 | } |
1094 | } |
- | 1095 | ||
- | 1096 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
|
- | 1097 | { |
|
- | 1098 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
|
- | 1099 | ||
- | 1100 | /* When we disable the VDD override bit last we have to do the manual |
|
1052 | 1101 | * wait. */ |
|
1053 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
1102 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
Line -... | Line 1103... | ||
- | 1103 | intel_dp->panel_power_cycle_delay); |
|
- | 1104 | ||
- | 1105 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
|
- | 1106 | } |
|
- | 1107 | ||
- | 1108 | static void wait_backlight_on(struct intel_dp *intel_dp) |
|
- | 1109 | { |
|
- | 1110 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
|
- | 1111 | intel_dp->backlight_on_delay); |
|
- | 1112 | } |
|
- | 1113 | ||
Line 1054... | Line 1114... | ||
1054 | { |
1114 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1055 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1115 | { |
1056 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1116 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
Line 1071... | Line 1131... | ||
1071 | control &= ~PANEL_UNLOCK_MASK; |
1131 | control &= ~PANEL_UNLOCK_MASK; |
1072 | control |= PANEL_UNLOCK_REGS; |
1132 | control |= PANEL_UNLOCK_REGS; |
1073 | return control; |
1133 | return control; |
1074 | } |
1134 | } |
Line 1075... | Line 1135... | ||
1075 | 1135 | ||
1076 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1136 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
1077 | { |
1137 | { |
- | 1138 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1139 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1078 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1140 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
- | 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
1142 | enum intel_display_power_domain power_domain; |
1080 | u32 pp; |
1143 | u32 pp; |
- | 1144 | u32 pp_stat_reg, pp_ctrl_reg; |
|
Line 1081... | Line 1145... | ||
1081 | u32 pp_stat_reg, pp_ctrl_reg; |
1145 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1082 | 1146 | ||
1083 | if (!is_edp(intel_dp)) |
- | |
1084 | return; |
- | |
1085 | - | ||
Line 1086... | Line 1147... | ||
1086 | WARN(intel_dp->want_panel_vdd, |
1147 | if (!is_edp(intel_dp)) |
Line 1087... | Line 1148... | ||
1087 | "eDP VDD already requested on\n"); |
1148 | return false; |
1088 | 1149 | ||
Line -... | Line 1150... | ||
- | 1150 | intel_dp->want_panel_vdd = true; |
|
1089 | intel_dp->want_panel_vdd = true; |
1151 | |
Line 1090... | Line 1152... | ||
1090 | 1152 | if (edp_have_panel_vdd(intel_dp)) |
|
Line 1091... | Line 1153... | ||
1091 | if (ironlake_edp_have_panel_vdd(intel_dp)) |
1153 | return need_to_disable; |
1092 | return; |
1154 | |
Line 1093... | Line 1155... | ||
1093 | 1155 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
1094 | intel_runtime_pm_get(dev_priv); |
1156 | intel_display_power_get(dev_priv, power_domain); |
Line 1095... | Line 1157... | ||
1095 | 1157 | ||
Line 1109... | Line 1171... | ||
1109 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1171 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1110 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1172 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1111 | /* |
1173 | /* |
1112 | * If the panel wasn't on, delay before accessing aux channel |
1174 | * If the panel wasn't on, delay before accessing aux channel |
1113 | */ |
1175 | */ |
1114 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
1176 | if (!edp_have_panel_power(intel_dp)) { |
1115 | DRM_DEBUG_KMS("eDP was not running\n"); |
1177 | DRM_DEBUG_KMS("eDP was not running\n"); |
1116 | msleep(intel_dp->panel_power_up_delay); |
1178 | msleep(intel_dp->panel_power_up_delay); |
1117 | } |
1179 | } |
- | 1180 | ||
- | 1181 | return need_to_disable; |
|
1118 | } |
1182 | } |
Line -... | Line 1183... | ||
- | 1183 | ||
- | 1184 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
|
- | 1185 | { |
|
- | 1186 | if (is_edp(intel_dp)) { |
|
- | 1187 | bool vdd = _edp_panel_vdd_on(intel_dp); |
|
- | 1188 | ||
- | 1189 | WARN(!vdd, "eDP VDD already requested on\n"); |
|
- | 1190 | } |
|
- | 1191 | } |
|
1119 | 1192 | ||
1120 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1193 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1121 | { |
1194 | { |
1122 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1195 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1123 | struct drm_i915_private *dev_priv = dev->dev_private; |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; |
1124 | u32 pp; |
1197 | u32 pp; |
Line 1125... | Line 1198... | ||
1125 | u32 pp_stat_reg, pp_ctrl_reg; |
1198 | u32 pp_stat_reg, pp_ctrl_reg; |
- | 1199 | ||
- | 1200 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
|
- | 1201 | ||
- | 1202 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
|
- | 1203 | struct intel_digital_port *intel_dig_port = |
|
- | 1204 | dp_to_dig_port(intel_dp); |
|
Line 1126... | Line -... | ||
1126 | - | ||
1127 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1205 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Line 1128... | Line 1206... | ||
1128 | 1206 | enum intel_display_power_domain power_domain; |
|
1129 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1207 | |
Line 1141... | Line 1219... | ||
1141 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1219 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1142 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1220 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1143 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1221 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Line 1144... | Line 1222... | ||
1144 | 1222 | ||
1145 | if ((pp & POWER_TARGET_ON) == 0) |
1223 | if ((pp & POWER_TARGET_ON) == 0) |
Line -... | Line 1224... | ||
- | 1224 | intel_dp->last_power_cycle = jiffies; |
|
1146 | msleep(intel_dp->panel_power_cycle_delay); |
1225 | |
1147 | 1226 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
1148 | intel_runtime_pm_put(dev_priv); |
1227 | intel_display_power_put(dev_priv, power_domain); |
Line 1149... | Line 1228... | ||
1149 | } |
1228 | } |
1150 | } |
1229 | } |
1151 | 1230 | ||
1152 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1231 | static void edp_panel_vdd_work(struct work_struct *__work) |
1153 | { |
1232 | { |
Line 1154... | Line 1233... | ||
1154 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1233 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1155 | struct intel_dp, panel_vdd_work); |
1234 | struct intel_dp, panel_vdd_work); |
1156 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1235 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | 1236 | ||
- | 1237 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
|
- | 1238 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 1239 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
|
- | 1240 | } |
|
- | 1241 | ||
- | 1242 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
|
- | 1243 | { |
|
- | 1244 | unsigned long delay; |
|
- | 1245 | ||
- | 1246 | /* |
|
- | 1247 | * Queue the timer to fire a long time from now (relative to the power |
|
- | 1248 | * down delay) to keep the panel power up across a sequence of |
|
1157 | 1249 | * operations. |
|
Line 1158... | Line 1250... | ||
1158 | mutex_lock(&dev->mode_config.mutex); |
1250 | */ |
1159 | ironlake_panel_vdd_off_sync(intel_dp); |
1251 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1160 | mutex_unlock(&dev->mode_config.mutex); |
1252 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1161 | } |
1253 | } |
Line 1162... | Line 1254... | ||
1162 | 1254 | ||
Line 1163... | Line 1255... | ||
1163 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1255 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Line 1164... | Line 1256... | ||
1164 | { |
1256 | { |
1165 | if (!is_edp(intel_dp)) |
1257 | if (!is_edp(intel_dp)) |
1166 | return; |
1258 | return; |
1167 | - | ||
1168 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
- | |
1169 | - | ||
1170 | intel_dp->want_panel_vdd = false; |
- | |
1171 | - | ||
1172 | if (sync) { |
1259 | |
1173 | ironlake_panel_vdd_off_sync(intel_dp); |
- | |
1174 | } else { |
- | |
1175 | /* |
1260 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
Line 1176... | Line 1261... | ||
1176 | * Queue the timer to fire a long |
1261 | |
1177 | * time from now (relative to the power down delay) |
1262 | intel_dp->want_panel_vdd = false; |
1178 | * to keep the panel power up across a sequence of operations |
1263 | |
1179 | */ |
1264 | if (sync) |
1180 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
1265 | edp_panel_vdd_off_sync(intel_dp); |
1181 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
1266 | else |
Line 1192... | Line 1277... | ||
1192 | if (!is_edp(intel_dp)) |
1277 | if (!is_edp(intel_dp)) |
1193 | return; |
1278 | return; |
Line 1194... | Line 1279... | ||
1194 | 1279 | ||
Line 1195... | Line 1280... | ||
1195 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
1280 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
1196 | 1281 | ||
1197 | if (ironlake_edp_have_panel_power(intel_dp)) { |
1282 | if (edp_have_panel_power(intel_dp)) { |
1198 | DRM_DEBUG_KMS("eDP power already on\n"); |
1283 | DRM_DEBUG_KMS("eDP power already on\n"); |
Line 1199... | Line 1284... | ||
1199 | return; |
1284 | return; |
Line 1200... | Line 1285... | ||
1200 | } |
1285 | } |
1201 | 1286 | ||
1202 | ironlake_wait_panel_power_cycle(intel_dp); |
1287 | wait_panel_power_cycle(intel_dp); |
1203 | 1288 | ||
Line 1215... | Line 1300... | ||
1215 | pp |= PANEL_POWER_RESET; |
1300 | pp |= PANEL_POWER_RESET; |
Line 1216... | Line 1301... | ||
1216 | 1301 | ||
1217 | I915_WRITE(pp_ctrl_reg, pp); |
1302 | I915_WRITE(pp_ctrl_reg, pp); |
Line 1218... | Line 1303... | ||
1218 | POSTING_READ(pp_ctrl_reg); |
1303 | POSTING_READ(pp_ctrl_reg); |
- | 1304 | ||
Line 1219... | Line 1305... | ||
1219 | 1305 | wait_panel_on(intel_dp); |
|
1220 | ironlake_wait_panel_on(intel_dp); |
1306 | intel_dp->last_power_on = jiffies; |
1221 | 1307 | ||
1222 | if (IS_GEN5(dev)) { |
1308 | if (IS_GEN5(dev)) { |
1223 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1309 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1224 | I915_WRITE(pp_ctrl_reg, pp); |
1310 | I915_WRITE(pp_ctrl_reg, pp); |
Line 1225... | Line 1311... | ||
1225 | POSTING_READ(pp_ctrl_reg); |
1311 | POSTING_READ(pp_ctrl_reg); |
1226 | } |
1312 | } |
- | 1313 | } |
|
- | 1314 | ||
1227 | } |
1315 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
1228 | 1316 | { |
|
- | 1317 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1229 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
1318 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1230 | { |
1319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 1231... | Line 1320... | ||
1231 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
1321 | enum intel_display_power_domain power_domain; |
Line 1233... | Line 1322... | ||
1233 | u32 pp; |
1322 | u32 pp; |
Line -... | Line 1323... | ||
- | 1323 | u32 pp_ctrl_reg; |
|
- | 1324 | ||
1234 | u32 pp_ctrl_reg; |
1325 | if (!is_edp(intel_dp)) |
1235 | 1326 | return; |
|
1236 | if (!is_edp(intel_dp)) |
1327 | |
1237 | return; |
1328 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
- | 1329 | ||
Line 1238... | Line 1330... | ||
1238 | 1330 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
|
Line -... | Line 1331... | ||
- | 1331 | ||
- | 1332 | pp = ironlake_get_pp_control(intel_dp); |
|
1239 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
1333 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1240 | 1334 | * panels get very unhappy and cease to work. */ |
|
Line -... | Line 1335... | ||
- | 1335 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
|
1241 | pp = ironlake_get_pp_control(intel_dp); |
1336 | EDP_BLC_ENABLE); |
- | 1337 | ||
- | 1338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
|
- | 1339 | ||
- | 1340 | intel_dp->want_panel_vdd = false; |
|
1242 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1341 | |
Line 1243... | Line 1342... | ||
1243 | * panels get very unhappy and cease to work. */ |
1342 | I915_WRITE(pp_ctrl_reg, pp); |
1244 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
1343 | POSTING_READ(pp_ctrl_reg); |
1245 | 1344 | ||
1246 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1345 | intel_dp->last_power_cycle = jiffies; |
1247 | 1346 | wait_panel_off(intel_dp); |
|
1248 | I915_WRITE(pp_ctrl_reg, pp); |
1347 | |
Line 1261... | Line 1360... | ||
1261 | 1360 | ||
1262 | if (!is_edp(intel_dp)) |
1361 | if (!is_edp(intel_dp)) |
Line 1263... | Line 1362... | ||
1263 | return; |
1362 | return; |
- | 1363 | ||
- | 1364 | DRM_DEBUG_KMS("\n"); |
|
- | 1365 | ||
1264 | 1366 | intel_panel_enable_backlight(intel_dp->attached_connector); |
|
1265 | DRM_DEBUG_KMS("\n"); |
1367 | |
1266 | /* |
1368 | /* |
1267 | * If we enable the backlight right away following a panel power |
1369 | * If we enable the backlight right away following a panel power |
1268 | * on, we may see slight flicker as the panel syncs with the eDP |
1370 | * on, we may see slight flicker as the panel syncs with the eDP |
1269 | * link. So delay a bit to make sure the image is solid before |
1371 | * link. So delay a bit to make sure the image is solid before |
1270 | * allowing it to appear. |
1372 | * allowing it to appear. |
1271 | */ |
1373 | */ |
1272 | msleep(intel_dp->backlight_on_delay); |
1374 | wait_backlight_on(intel_dp); |
Line 1273... | Line 1375... | ||
1273 | pp = ironlake_get_pp_control(intel_dp); |
1375 | pp = ironlake_get_pp_control(intel_dp); |
Line 1274... | Line 1376... | ||
1274 | pp |= EDP_BLC_ENABLE; |
1376 | pp |= EDP_BLC_ENABLE; |
1275 | 1377 | ||
1276 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
- | |
1277 | - | ||
1278 | I915_WRITE(pp_ctrl_reg, pp); |
1378 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Line 1279... | Line 1379... | ||
1279 | POSTING_READ(pp_ctrl_reg); |
1379 | |
1280 | 1380 | I915_WRITE(pp_ctrl_reg, pp); |
|
1281 | intel_panel_enable_backlight(intel_dp->attached_connector); |
1381 | POSTING_READ(pp_ctrl_reg); |
1282 | } |
1382 | } |
1283 | 1383 | ||
1284 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
1384 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
Line 1285... | Line 1385... | ||
1285 | { |
1385 | { |
1286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1386 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 1287... | Line -... | ||
1287 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1288 | u32 pp; |
- | |
1289 | u32 pp_ctrl_reg; |
1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
1290 | 1388 | u32 pp; |
|
1291 | if (!is_edp(intel_dp)) |
1389 | u32 pp_ctrl_reg; |
Line 1292... | Line 1390... | ||
1292 | return; |
1390 | |
Line 1293... | Line 1391... | ||
1293 | 1391 | if (!is_edp(intel_dp)) |
|
1294 | intel_panel_disable_backlight(intel_dp->attached_connector); |
1392 | return; |
1295 | 1393 | ||
- | 1394 | DRM_DEBUG_KMS("\n"); |
|
- | 1395 | pp = ironlake_get_pp_control(intel_dp); |
|
- | 1396 | pp &= ~EDP_BLC_ENABLE; |
|
- | 1397 | ||
1296 | DRM_DEBUG_KMS("\n"); |
1398 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Line 1297... | Line 1399... | ||
1297 | pp = ironlake_get_pp_control(intel_dp); |
1399 | |
1298 | pp &= ~EDP_BLC_ENABLE; |
1400 | I915_WRITE(pp_ctrl_reg, pp); |
1299 | 1401 | POSTING_READ(pp_ctrl_reg); |
|
Line 1363... | Line 1465... | ||
1363 | /* Should have a valid DPCD by this point */ |
1465 | /* Should have a valid DPCD by this point */ |
1364 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
1466 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
1365 | return; |
1467 | return; |
Line 1366... | Line 1468... | ||
1366 | 1468 | ||
1367 | if (mode != DRM_MODE_DPMS_ON) { |
1469 | if (mode != DRM_MODE_DPMS_ON) { |
1368 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
1470 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1369 | DP_SET_POWER_D3); |
1471 | DP_SET_POWER_D3); |
1370 | if (ret != 1) |
1472 | if (ret != 1) |
1371 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1473 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1372 | } else { |
1474 | } else { |
1373 | /* |
1475 | /* |
1374 | * When turning on, we need to retry for 1ms to give the sink |
1476 | * When turning on, we need to retry for 1ms to give the sink |
1375 | * time to wake up. |
1477 | * time to wake up. |
1376 | */ |
1478 | */ |
1377 | for (i = 0; i < 3; i++) { |
1479 | for (i = 0; i < 3; i++) { |
1378 | ret = intel_dp_aux_native_write_1(intel_dp, |
- | |
1379 | DP_SET_POWER, |
1480 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1380 | DP_SET_POWER_D0); |
1481 | DP_SET_POWER_D0); |
1381 | if (ret == 1) |
1482 | if (ret == 1) |
1382 | break; |
1483 | break; |
1383 | msleep(1); |
1484 | msleep(1); |
Line 1390... | Line 1491... | ||
1390 | { |
1491 | { |
1391 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1492 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1392 | enum port port = dp_to_dig_port(intel_dp)->port; |
1493 | enum port port = dp_to_dig_port(intel_dp)->port; |
1393 | struct drm_device *dev = encoder->base.dev; |
1494 | struct drm_device *dev = encoder->base.dev; |
1394 | struct drm_i915_private *dev_priv = dev->dev_private; |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1496 | enum intel_display_power_domain power_domain; |
|
- | 1497 | u32 tmp; |
|
- | 1498 | ||
- | 1499 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 1500 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
|
- | 1501 | return false; |
|
- | 1502 | ||
1395 | u32 tmp = I915_READ(intel_dp->output_reg); |
1503 | tmp = I915_READ(intel_dp->output_reg); |
Line 1396... | Line 1504... | ||
1396 | 1504 | ||
1397 | if (!(tmp & DP_PORT_EN)) |
1505 | if (!(tmp & DP_PORT_EN)) |
Line 1398... | Line 1506... | ||
1398 | return false; |
1506 | return false; |
1399 | 1507 | ||
- | 1508 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
|
- | 1509 | *pipe = PORT_TO_PIPE_CPT(tmp); |
|
1400 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1510 | } else if (IS_CHERRYVIEW(dev)) { |
1401 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1511 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
1402 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1512 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1403 | *pipe = PORT_TO_PIPE(tmp); |
1513 | *pipe = PORT_TO_PIPE(tmp); |
1404 | } else { |
1514 | } else { |
Line 1444... | Line 1554... | ||
1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
1445 | enum port port = dp_to_dig_port(intel_dp)->port; |
1555 | enum port port = dp_to_dig_port(intel_dp)->port; |
1446 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1556 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1447 | int dotclock; |
1557 | int dotclock; |
Line 1448... | Line -... | ||
1448 | - | ||
1449 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1558 | |
- | 1559 | tmp = I915_READ(intel_dp->output_reg); |
|
- | 1560 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) |
|
- | 1561 | pipe_config->has_audio = true; |
|
- | 1562 | ||
1450 | tmp = I915_READ(intel_dp->output_reg); |
1563 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1451 | if (tmp & DP_SYNC_HS_HIGH) |
1564 | if (tmp & DP_SYNC_HS_HIGH) |
1452 | flags |= DRM_MODE_FLAG_PHSYNC; |
1565 | flags |= DRM_MODE_FLAG_PHSYNC; |
1453 | else |
1566 | else |
Line 1510... | Line 1623... | ||
1510 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
1623 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
1511 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
1624 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
1512 | } |
1625 | } |
1513 | } |
1626 | } |
Line 1514... | Line 1627... | ||
1514 | 1627 | ||
1515 | static bool is_edp_psr(struct drm_device *dev) |
1628 | static bool is_edp_psr(struct intel_dp *intel_dp) |
1516 | { |
- | |
1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1518 | 1629 | { |
|
1519 | return dev_priv->psr.sink_support; |
1630 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
Line 1520... | Line 1631... | ||
1520 | } |
1631 | } |
1521 | 1632 | ||
1522 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1633 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
Line 1562... | Line 1673... | ||
1562 | { |
1673 | { |
1563 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1674 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1564 | struct drm_i915_private *dev_priv = dev->dev_private; |
1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
1565 | struct edp_vsc_psr psr_vsc; |
1676 | struct edp_vsc_psr psr_vsc; |
Line 1566... | Line -... | ||
1566 | - | ||
1567 | if (intel_dp->psr_setup_done) |
- | |
1568 | return; |
- | |
1569 | 1677 | ||
1570 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
1678 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
1571 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
1679 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
1572 | psr_vsc.sdp_header.HB0 = 0; |
1680 | psr_vsc.sdp_header.HB0 = 0; |
1573 | psr_vsc.sdp_header.HB1 = 0x7; |
1681 | psr_vsc.sdp_header.HB1 = 0x7; |
Line 1576... | Line 1684... | ||
1576 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
1684 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
Line 1577... | Line 1685... | ||
1577 | 1685 | ||
1578 | /* Avoid continuous PSR exit by masking memup and hpd */ |
1686 | /* Avoid continuous PSR exit by masking memup and hpd */ |
1579 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
1687 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
1580 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
- | |
1581 | - | ||
1582 | intel_dp->psr_setup_done = true; |
1688 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
Line 1583... | Line 1689... | ||
1583 | } |
1689 | } |
1584 | 1690 | ||
- | 1691 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
|
1585 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
1692 | { |
1586 | { |
1693 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1587 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1694 | struct drm_device *dev = dig_port->base.base.dev; |
1588 | struct drm_i915_private *dev_priv = dev->dev_private; |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; |
1589 | uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); |
1696 | uint32_t aux_clock_divider; |
- | 1697 | int precharge = 0x3; |
|
- | 1698 | int msg_size = 5; /* Header(4) + Message(1) */ |
|
- | 1699 | bool only_standby = false; |
|
- | 1700 | ||
- | 1701 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
|
- | 1702 | ||
Line 1590... | Line 1703... | ||
1590 | int precharge = 0x3; |
1703 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
1591 | int msg_size = 5; /* Header(4) + Message(1) */ |
1704 | only_standby = true; |
1592 | 1705 | ||
1593 | /* Enable PSR in sink */ |
- | |
1594 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
1706 | /* Enable PSR in sink */ |
1595 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
1707 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
1596 | DP_PSR_ENABLE & |
1708 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1597 | ~DP_PSR_MAIN_LINK_ACTIVE); |
- | |
1598 | else |
1709 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
Line 1599... | Line 1710... | ||
1599 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
1710 | else |
1600 | DP_PSR_ENABLE | |
1711 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1601 | DP_PSR_MAIN_LINK_ACTIVE); |
1712 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
1602 | 1713 | ||
Line 1610... | Line 1721... | ||
1610 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
1721 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
1611 | } |
1722 | } |
Line 1612... | Line 1723... | ||
1612 | 1723 | ||
1613 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
1724 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
- | 1725 | { |
|
1614 | { |
1726 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1615 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1727 | struct drm_device *dev = dig_port->base.base.dev; |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
1728 | struct drm_i915_private *dev_priv = dev->dev_private; |
1617 | uint32_t max_sleep_time = 0x1f; |
1729 | uint32_t max_sleep_time = 0x1f; |
1618 | uint32_t idle_frames = 1; |
1730 | uint32_t idle_frames = 1; |
1619 | uint32_t val = 0x0; |
1731 | uint32_t val = 0x0; |
- | 1732 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
|
- | 1733 | bool only_standby = false; |
|
- | 1734 | ||
- | 1735 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
|
Line 1620... | Line 1736... | ||
1620 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
1736 | only_standby = true; |
1621 | 1737 | ||
1622 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { |
1738 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
1623 | val |= EDP_PSR_LINK_STANDBY; |
1739 | val |= EDP_PSR_LINK_STANDBY; |
1624 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
1740 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
- | 1741 | val |= EDP_PSR_TP1_TIME_0us; |
|
1625 | val |= EDP_PSR_TP1_TIME_0us; |
1742 | val |= EDP_PSR_SKIP_AUX_EXIT; |
1626 | val |= EDP_PSR_SKIP_AUX_EXIT; |
1743 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
Line 1627... | Line 1744... | ||
1627 | } else |
1744 | } else |
1628 | val |= EDP_PSR_LINK_DISABLE; |
1745 | val |= EDP_PSR_LINK_DISABLE; |
1629 | 1746 | ||
1630 | I915_WRITE(EDP_PSR_CTL(dev), val | |
1747 | I915_WRITE(EDP_PSR_CTL(dev), val | |
1631 | IS_BROADWELL(dev) ? 0 : link_entry_time | |
1748 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
1632 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1749 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
Line 1639... | Line 1756... | ||
1639 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1756 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1640 | struct drm_device *dev = dig_port->base.base.dev; |
1757 | struct drm_device *dev = dig_port->base.base.dev; |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; |
1758 | struct drm_i915_private *dev_priv = dev->dev_private; |
1642 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
1759 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
1643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1644 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; |
- | |
1645 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
- | |
Line 1646... | Line 1761... | ||
1646 | 1761 | ||
- | 1762 | lockdep_assert_held(&dev_priv->psr.lock); |
|
- | 1763 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
|
Line 1647... | Line -... | ||
1647 | dev_priv->psr.source_ok = false; |
- | |
1648 | - | ||
1649 | if (!HAS_PSR(dev)) { |
1764 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
1650 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
- | |
Line 1651... | Line -... | ||
1651 | return false; |
- | |
1652 | } |
1765 | |
1653 | 1766 | dev_priv->psr.source_ok = false; |
|
1654 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || |
1767 | |
1655 | (dig_port->port != PORT_A)) { |
1768 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
Line 1656... | Line 1769... | ||
1656 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
1769 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
1657 | return false; |
1770 | return false; |
1658 | } |
1771 | } |
1659 | 1772 | ||
Line 1660... | Line -... | ||
1660 | if (!i915_enable_psr) { |
- | |
1661 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
- | |
1662 | return false; |
1773 | if (!i915.enable_psr) { |
1663 | } |
- | |
1664 | - | ||
1665 | crtc = dig_port->base.base.crtc; |
- | |
1666 | if (crtc == NULL) { |
- | |
1667 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
1774 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
1668 | return false; |
- | |
1669 | } |
- | |
1670 | - | ||
1671 | intel_crtc = to_intel_crtc(crtc); |
- | |
1672 | if (!intel_crtc_active(crtc)) { |
- | |
1673 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
- | |
1674 | return false; |
- | |
1675 | } |
- | |
1676 | - | ||
1677 | obj = to_intel_framebuffer(crtc->fb)->obj; |
- | |
1678 | if (obj->tiling_mode != I915_TILING_X || |
- | |
1679 | obj->fence_reg == I915_FENCE_REG_NONE) { |
- | |
1680 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); |
- | |
1681 | return false; |
1775 | return false; |
1682 | } |
- | |
Line 1683... | Line 1776... | ||
1683 | 1776 | } |
|
1684 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { |
1777 | |
1685 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); |
1778 | /* Below limitations aren't valid for Broadwell */ |
1686 | return false; |
1779 | if (IS_BROADWELL(dev)) |
Line 1695... | Line 1788... | ||
1695 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
1788 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
1696 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
1789 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
1697 | return false; |
1790 | return false; |
1698 | } |
1791 | } |
Line -... | Line 1792... | ||
- | 1792 | ||
1699 | 1793 | out: |
|
1700 | dev_priv->psr.source_ok = true; |
1794 | dev_priv->psr.source_ok = true; |
1701 | return true; |
1795 | return true; |
Line 1702... | Line 1796... | ||
1702 | } |
1796 | } |
1703 | 1797 | ||
1704 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
1798 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
1705 | { |
- | |
1706 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1799 | { |
1707 | 1800 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1708 | if (!intel_edp_psr_match_conditions(intel_dp) || |
- | |
Line -... | Line 1801... | ||
- | 1801 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
1709 | intel_edp_is_psr_enabled(dev)) |
1802 | struct drm_i915_private *dev_priv = dev->dev_private; |
1710 | return; |
1803 | |
Line 1711... | Line 1804... | ||
1711 | 1804 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
|
1712 | /* Setup PSR once */ |
1805 | WARN_ON(dev_priv->psr.active); |
Line 1713... | Line 1806... | ||
1713 | intel_edp_psr_setup(intel_dp); |
1806 | lockdep_assert_held(&dev_priv->psr.lock); |
1714 | 1807 | ||
- | 1808 | /* Enable PSR on the panel */ |
|
- | 1809 | intel_edp_psr_enable_sink(intel_dp); |
|
1715 | /* Enable PSR on the panel */ |
1810 | |
Line 1716... | Line 1811... | ||
1716 | intel_edp_psr_enable_sink(intel_dp); |
1811 | /* Enable PSR on the host */ |
1717 | 1812 | intel_edp_psr_enable_source(intel_dp); |
|
1718 | /* Enable PSR on the host */ |
1813 | |
- | 1814 | dev_priv->psr.active = true; |
|
Line -... | Line 1815... | ||
- | 1815 | } |
|
- | 1816 | ||
- | 1817 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
|
- | 1818 | { |
|
- | 1819 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
1719 | intel_edp_psr_enable_source(intel_dp); |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1821 | ||
- | 1822 | if (!HAS_PSR(dev)) { |
|
- | 1823 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
|
- | 1824 | return; |
|
- | 1825 | } |
|
1720 | } |
1826 | |
- | 1827 | if (!is_edp_psr(intel_dp)) { |
|
- | 1828 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
|
- | 1829 | return; |
|
- | 1830 | } |
|
- | 1831 | ||
- | 1832 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1833 | if (dev_priv->psr.enabled) { |
|
- | 1834 | DRM_DEBUG_KMS("PSR already in use\n"); |
|
1721 | 1835 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1836 | return; |
|
- | 1837 | } |
|
- | 1838 | ||
- | 1839 | dev_priv->psr.busy_frontbuffer_bits = 0; |
|
1722 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1840 | |
Line 1723... | Line 1841... | ||
1723 | { |
1841 | /* Setup PSR once */ |
1724 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1842 | intel_edp_psr_setup(intel_dp); |
1725 | 1843 | ||
1726 | if (intel_edp_psr_match_conditions(intel_dp) && |
1844 | if (intel_edp_psr_match_conditions(intel_dp)) |
Line -... | Line 1845... | ||
- | 1845 | dev_priv->psr.enabled = intel_dp; |
|
1727 | !intel_edp_is_psr_enabled(dev)) |
1846 | mutex_unlock(&dev_priv->psr.lock); |
- | 1847 | } |
|
1728 | intel_edp_psr_do_enable(intel_dp); |
1848 | |
- | 1849 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
|
Line -... | Line 1850... | ||
- | 1850 | { |
|
1729 | } |
1851 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1730 | 1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line 1731... | Line 1853... | ||
1731 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1853 | |
1732 | { |
1854 | mutex_lock(&dev_priv->psr.lock); |
1733 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1855 | if (!dev_priv->psr.enabled) { |
1734 | struct drm_i915_private *dev_priv = dev->dev_private; |
1856 | mutex_unlock(&dev_priv->psr.lock); |
- | 1857 | return; |
|
- | 1858 | } |
|
- | 1859 | ||
- | 1860 | if (dev_priv->psr.active) { |
|
1735 | 1861 | I915_WRITE(EDP_PSR_CTL(dev), |
|
Line -... | Line 1862... | ||
- | 1862 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
|
- | 1863 | ||
- | 1864 | /* Wait till PSR is idle */ |
|
- | 1865 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
|
- | 1866 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
|
- | 1867 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
|
1736 | if (!intel_edp_is_psr_enabled(dev)) |
1868 | |
1737 | return; |
1869 | dev_priv->psr.active = false; |
1738 | 1870 | } else { |
|
- | 1871 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
|
1739 | I915_WRITE(EDP_PSR_CTL(dev), |
1872 | } |
Line 1740... | Line -... | ||
1740 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
- | |
1741 | 1873 | ||
1742 | /* Wait till PSR is idle */ |
1874 | dev_priv->psr.enabled = NULL; |
Line 1743... | Line 1875... | ||
1743 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
1875 | mutex_unlock(&dev_priv->psr.lock); |
1744 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1876 | |
- | 1877 | cancel_delayed_work_sync(&dev_priv->psr.work); |
|
- | 1878 | } |
|
- | 1879 | ||
- | 1880 | static void intel_edp_psr_work(struct work_struct *work) |
|
- | 1881 | { |
|
- | 1882 | struct drm_i915_private *dev_priv = |
|
- | 1883 | container_of(work, typeof(*dev_priv), psr.work.work); |
|
- | 1884 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
|
Line 1745... | Line -... | ||
1745 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
- | |
1746 | } |
- | |
1747 | - | ||
1748 | void intel_edp_psr_update(struct drm_device *dev) |
- | |
1749 | { |
1885 | |
- | 1886 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1887 | intel_dp = dev_priv->psr.enabled; |
|
1750 | struct intel_encoder *encoder; |
1888 | |
- | 1889 | if (!intel_dp) |
|
- | 1890 | goto unlock; |
|
- | 1891 | ||
- | 1892 | /* |
|
- | 1893 | * The delayed work can race with an invalidate hence we need to |
|
- | 1894 | * recheck. Since psr_flush first clears this and then reschedules we |
|
- | 1895 | * won't ever miss a flush when bailing out here. |
|
- | 1896 | */ |
|
- | 1897 | if (dev_priv->psr.busy_frontbuffer_bits) |
|
- | 1898 | goto unlock; |
|
- | 1899 | ||
- | 1900 | intel_edp_psr_do_enable(intel_dp); |
|
- | 1901 | unlock: |
|
- | 1902 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1903 | } |
|
- | 1904 | ||
- | 1905 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
|
- | 1906 | { |
|
- | 1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1908 | ||
- | 1909 | if (dev_priv->psr.active) { |
|
- | 1910 | u32 val = I915_READ(EDP_PSR_CTL(dev)); |
|
- | 1911 | ||
- | 1912 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
|
- | 1913 | ||
- | 1914 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); |
|
- | 1915 | ||
- | 1916 | dev_priv->psr.active = false; |
|
- | 1917 | } |
|
- | 1918 | ||
- | 1919 | } |
|
- | 1920 | ||
- | 1921 | void intel_edp_psr_invalidate(struct drm_device *dev, |
|
- | 1922 | unsigned frontbuffer_bits) |
|
- | 1923 | { |
|
- | 1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1925 | struct drm_crtc *crtc; |
|
- | 1926 | enum pipe pipe; |
|
- | 1927 | ||
- | 1928 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1929 | if (!dev_priv->psr.enabled) { |
|
- | 1930 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1931 | return; |
|
- | 1932 | } |
|
- | 1933 | ||
- | 1934 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
|
- | 1935 | pipe = to_intel_crtc(crtc)->pipe; |
|
- | 1936 | ||
- | 1937 | intel_edp_psr_do_exit(dev); |
|
- | 1938 | ||
- | 1939 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
|
- | 1940 | ||
- | 1941 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
|
- | 1942 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1943 | } |
|
- | 1944 | ||
- | 1945 | void intel_edp_psr_flush(struct drm_device *dev, |
|
- | 1946 | unsigned frontbuffer_bits) |
|
- | 1947 | { |
|
- | 1948 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1949 | struct drm_crtc *crtc; |
|
- | 1950 | enum pipe pipe; |
|
- | 1951 | ||
- | 1952 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1953 | if (!dev_priv->psr.enabled) { |
|
- | 1954 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1955 | return; |
|
- | 1956 | } |
|
- | 1957 | ||
- | 1958 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
|
- | 1959 | pipe = to_intel_crtc(crtc)->pipe; |
|
- | 1960 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
|
- | 1961 | ||
- | 1962 | /* |
|
- | 1963 | * On Haswell sprite plane updates don't result in a psr invalidating |
|
- | 1964 | * signal in the hardware. Which means we need to manually fake this in |
|
- | 1965 | * software for all flushes, not just when we've seen a preceding |
|
- | 1966 | * invalidation through frontbuffer rendering. |
|
- | 1967 | */ |
|
- | 1968 | if (IS_HASWELL(dev) && |
|
1751 | struct intel_dp *intel_dp = NULL; |
1969 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) |
Line 1752... | Line 1970... | ||
1752 | 1970 | intel_edp_psr_do_exit(dev); |
|
1753 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) |
1971 | |
1754 | if (encoder->type == INTEL_OUTPUT_EDP) { |
1972 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
1755 | intel_dp = enc_to_intel_dp(&encoder->base); |
1973 | schedule_delayed_work(&dev_priv->psr.work, |
1756 | 1974 | msecs_to_jiffies(100)); |
|
Line 1757... | Line 1975... | ||
1757 | if (!is_edp_psr(dev)) |
1975 | mutex_unlock(&dev_priv->psr.lock); |
1758 | return; |
1976 | } |
- | 1977 | ||
1759 | 1978 | void intel_edp_psr_init(struct drm_device *dev) |
|
1760 | if (!intel_edp_psr_match_conditions(intel_dp)) |
1979 | { |
1761 | intel_edp_psr_disable(intel_dp); |
1980 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1762... | Line 1981... | ||
1762 | else |
1981 | |
1763 | if (!intel_edp_is_psr_enabled(dev)) |
1982 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
1764 | intel_edp_psr_do_enable(intel_dp); |
1983 | mutex_init(&dev_priv->psr.lock); |
1765 | } |
1984 | } |
Line 1766... | Line 1985... | ||
1766 | } |
1985 | |
1767 | 1986 | static void intel_disable_dp(struct intel_encoder *encoder) |
|
1768 | static void intel_disable_dp(struct intel_encoder *encoder) |
1987 | { |
1769 | { |
1988 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1770 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
- | |
Line 1771... | Line 1989... | ||
1771 | enum port port = dp_to_dig_port(intel_dp)->port; |
1989 | enum port port = dp_to_dig_port(intel_dp)->port; |
- | 1990 | struct drm_device *dev = encoder->base.dev; |
|
- | 1991 | ||
1772 | struct drm_device *dev = encoder->base.dev; |
1992 | /* Make sure the panel is off before trying to change the mode. But also |
1773 | - | ||
1774 | /* Make sure the panel is off before trying to change the mode. But also |
1993 | * ensure that we have vdd while we switch off the panel. */ |
1775 | * ensure that we have vdd while we switch off the panel. */ |
1994 | intel_edp_panel_vdd_on(intel_dp); |
- | 1995 | intel_edp_backlight_off(intel_dp); |
|
- | 1996 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
|
- | 1997 | intel_edp_panel_off(intel_dp); |
|
- | 1998 | ||
- | 1999 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
|
- | 2000 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
|
- | 2001 | intel_dp_link_down(intel_dp); |
|
- | 2002 | } |
|
- | 2003 | ||
- | 2004 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
|
- | 2005 | { |
|
- | 2006 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2007 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 2008 | ||
- | 2009 | if (port != PORT_A) |
|
- | 2010 | return; |
|
- | 2011 | ||
- | 2012 | intel_dp_link_down(intel_dp); |
|
- | 2013 | ironlake_edp_pll_off(intel_dp); |
|
- | 2014 | } |
|
- | 2015 | ||
- | 2016 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
|
- | 2017 | { |
|
- | 2018 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2019 | ||
- | 2020 | intel_dp_link_down(intel_dp); |
|
- | 2021 | } |
|
- | 2022 | ||
- | 2023 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
|
- | 2024 | { |
|
- | 2025 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2026 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2027 | struct drm_device *dev = encoder->base.dev; |
|
- | 2028 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2029 | struct intel_crtc *intel_crtc = |
|
- | 2030 | to_intel_crtc(encoder->base.crtc); |
|
- | 2031 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2032 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2033 | u32 val; |
|
- | 2034 | ||
- | 2035 | intel_dp_link_down(intel_dp); |
|
- | 2036 | ||
1776 | ironlake_edp_backlight_off(intel_dp); |
2037 | mutex_lock(&dev_priv->dpio_lock); |
Line 1777... | Line 2038... | ||
1777 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2038 | |
1778 | ironlake_edp_panel_off(intel_dp); |
2039 | /* Propagate soft reset to data lane reset */ |
1779 | 2040 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
|
Line 1803... | Line 2064... | ||
1803 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2064 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Line 1804... | Line 2065... | ||
1804 | 2065 | ||
1805 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2066 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
Line 1806... | Line 2067... | ||
1806 | return; |
2067 | return; |
1807 | 2068 | ||
1808 | ironlake_edp_panel_vdd_on(intel_dp); |
2069 | intel_edp_panel_vdd_on(intel_dp); |
1809 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2070 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1810 | intel_dp_start_link_train(intel_dp); |
2071 | intel_dp_start_link_train(intel_dp); |
1811 | ironlake_edp_panel_on(intel_dp); |
2072 | intel_edp_panel_on(intel_dp); |
1812 | ironlake_edp_panel_vdd_off(intel_dp, true); |
2073 | edp_panel_vdd_off(intel_dp, true); |
1813 | intel_dp_complete_link_train(intel_dp); |
2074 | intel_dp_complete_link_train(intel_dp); |
Line 1814... | Line 2075... | ||
1814 | intel_dp_stop_link_train(intel_dp); |
2075 | intel_dp_stop_link_train(intel_dp); |
1815 | } |
2076 | } |
1816 | 2077 | ||
Line 1817... | Line 2078... | ||
1817 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2078 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1818 | { |
2079 | { |
1819 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2080 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Line 1820... | Line 2081... | ||
1820 | 2081 | ||
1821 | intel_enable_dp(encoder); |
2082 | intel_enable_dp(encoder); |
1822 | ironlake_edp_backlight_on(intel_dp); |
2083 | intel_edp_backlight_on(intel_dp); |
Line 1823... | Line 2084... | ||
1823 | } |
2084 | } |
1824 | 2085 | ||
Line 1825... | Line 2086... | ||
1825 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2086 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1826 | { |
2087 | { |
1827 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2088 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1828 | 2089 | ||
Line -... | Line 2090... | ||
- | 2090 | intel_edp_backlight_on(intel_dp); |
|
- | 2091 | } |
|
- | 2092 | ||
1829 | ironlake_edp_backlight_on(intel_dp); |
2093 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
- | 2094 | { |
|
1830 | } |
2095 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1831 | 2096 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2097 | ||
Line 1832... | Line 2098... | ||
1832 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2098 | intel_dp_prepare(encoder); |
1833 | { |
2099 | |
1834 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2100 | /* Only ilk+ has port A */ |
1835 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2101 | if (dport->port == PORT_A) { |
Line 1863... | Line 2129... | ||
1863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2129 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1864 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2130 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Line 1865... | Line 2131... | ||
1865 | 2131 | ||
Line -... | Line 2132... | ||
- | 2132 | mutex_unlock(&dev_priv->dpio_lock); |
|
1866 | mutex_unlock(&dev_priv->dpio_lock); |
2133 | |
1867 | 2134 | if (is_edp(intel_dp)) { |
|
1868 | /* init power sequencer on this pipe and port */ |
2135 | /* init power sequencer on this pipe and port */ |
1869 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
2136 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
- | 2137 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
|
Line 1870... | Line 2138... | ||
1870 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
2138 | &power_seq); |
Line 1871... | Line 2139... | ||
1871 | &power_seq); |
2139 | } |
1872 | 2140 | ||
Line 1883... | Line 2151... | ||
1883 | struct intel_crtc *intel_crtc = |
2151 | struct intel_crtc *intel_crtc = |
1884 | to_intel_crtc(encoder->base.crtc); |
2152 | to_intel_crtc(encoder->base.crtc); |
1885 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2153 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1886 | int pipe = intel_crtc->pipe; |
2154 | int pipe = intel_crtc->pipe; |
Line -... | Line 2155... | ||
- | 2155 | ||
- | 2156 | intel_dp_prepare(encoder); |
|
1887 | 2157 | ||
1888 | /* Program Tx lane resets to default */ |
2158 | /* Program Tx lane resets to default */ |
1889 | mutex_lock(&dev_priv->dpio_lock); |
2159 | mutex_lock(&dev_priv->dpio_lock); |
1890 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2160 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
1891 | DPIO_PCS_TX_LANE2_RESET | |
2161 | DPIO_PCS_TX_LANE2_RESET | |
Line 1901... | Line 2171... | ||
1901 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2171 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
1902 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2172 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
1903 | mutex_unlock(&dev_priv->dpio_lock); |
2173 | mutex_unlock(&dev_priv->dpio_lock); |
1904 | } |
2174 | } |
Line -... | Line 2175... | ||
- | 2175 | ||
- | 2176 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
|
- | 2177 | { |
|
- | 2178 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2179 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2180 | struct drm_device *dev = encoder->base.dev; |
|
- | 2181 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2182 | struct edp_power_seq power_seq; |
|
- | 2183 | struct intel_crtc *intel_crtc = |
|
- | 2184 | to_intel_crtc(encoder->base.crtc); |
|
- | 2185 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2186 | int pipe = intel_crtc->pipe; |
|
- | 2187 | int data, i; |
|
- | 2188 | u32 val; |
|
- | 2189 | ||
- | 2190 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2191 | ||
- | 2192 | /* Deassert soft data lane reset*/ |
|
- | 2193 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
|
- | 2194 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2195 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
|
- | 2196 | ||
- | 2197 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
|
- | 2198 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2199 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
|
- | 2200 | ||
- | 2201 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
|
- | 2202 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2203 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
|
- | 2204 | ||
- | 2205 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
|
- | 2206 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2207 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
|
- | 2208 | ||
- | 2209 | /* Program Tx lane latency optimal setting*/ |
|
- | 2210 | for (i = 0; i < 4; i++) { |
|
- | 2211 | /* Set the latency optimal bit */ |
|
- | 2212 | data = (i == 1) ? 0x0 : 0x6; |
|
- | 2213 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), |
|
- | 2214 | data << DPIO_FRC_LATENCY_SHFIT); |
|
- | 2215 | ||
- | 2216 | /* Set the upar bit */ |
|
- | 2217 | data = (i == 1) ? 0x0 : 0x1; |
|
- | 2218 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
|
- | 2219 | data << DPIO_UPAR_SHIFT); |
|
- | 2220 | } |
|
- | 2221 | ||
- | 2222 | /* Data lane stagger programming */ |
|
- | 2223 | /* FIXME: Fix up value only after power analysis */ |
|
- | 2224 | ||
- | 2225 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2226 | ||
- | 2227 | if (is_edp(intel_dp)) { |
|
- | 2228 | /* init power sequencer on this pipe and port */ |
|
- | 2229 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
|
- | 2230 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
|
- | 2231 | &power_seq); |
|
- | 2232 | } |
|
- | 2233 | ||
- | 2234 | intel_enable_dp(encoder); |
|
- | 2235 | ||
- | 2236 | vlv_wait_port_ready(dev_priv, dport); |
|
- | 2237 | } |
|
- | 2238 | ||
- | 2239 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
|
- | 2240 | { |
|
- | 2241 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
|
- | 2242 | struct drm_device *dev = encoder->base.dev; |
|
- | 2243 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2244 | struct intel_crtc *intel_crtc = |
|
- | 2245 | to_intel_crtc(encoder->base.crtc); |
|
- | 2246 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2247 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2248 | u32 val; |
|
- | 2249 | ||
- | 2250 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2251 | ||
- | 2252 | /* program left/right clock distribution */ |
|
- | 2253 | if (pipe != PIPE_B) { |
|
- | 2254 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
|
- | 2255 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
|
- | 2256 | if (ch == DPIO_CH0) |
|
- | 2257 | val |= CHV_BUFLEFTENA1_FORCE; |
|
- | 2258 | if (ch == DPIO_CH1) |
|
- | 2259 | val |= CHV_BUFRIGHTENA1_FORCE; |
|
- | 2260 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
|
- | 2261 | } else { |
|
- | 2262 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
|
- | 2263 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
|
- | 2264 | if (ch == DPIO_CH0) |
|
- | 2265 | val |= CHV_BUFLEFTENA2_FORCE; |
|
- | 2266 | if (ch == DPIO_CH1) |
|
- | 2267 | val |= CHV_BUFRIGHTENA2_FORCE; |
|
- | 2268 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
|
- | 2269 | } |
|
- | 2270 | ||
- | 2271 | /* program clock channel usage */ |
|
- | 2272 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
|
- | 2273 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
|
- | 2274 | if (pipe != PIPE_B) |
|
- | 2275 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
|
- | 2276 | else |
|
- | 2277 | val |= CHV_PCS_USEDCLKCHANNEL; |
|
- | 2278 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
|
- | 2279 | ||
- | 2280 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
|
- | 2281 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
|
- | 2282 | if (pipe != PIPE_B) |
|
- | 2283 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
|
- | 2284 | else |
|
- | 2285 | val |= CHV_PCS_USEDCLKCHANNEL; |
|
- | 2286 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
|
- | 2287 | ||
- | 2288 | /* |
|
- | 2289 | * This a a bit weird since generally CL |
|
- | 2290 | * matches the pipe, but here we need to |
|
- | 2291 | * pick the CL based on the port. |
|
- | 2292 | */ |
|
- | 2293 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
|
- | 2294 | if (pipe != PIPE_B) |
|
- | 2295 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
|
- | 2296 | else |
|
- | 2297 | val |= CHV_CMN_USEDCLKCHANNEL; |
|
- | 2298 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
|
- | 2299 | ||
- | 2300 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2301 | } |
|
1905 | 2302 | ||
1906 | /* |
2303 | /* |
1907 | * Native read with retry for link status and receiver capability reads for |
2304 | * Native read with retry for link status and receiver capability reads for |
- | 2305 | * cases where the sink may still be asleep. |
|
- | 2306 | * |
|
- | 2307 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
|
1908 | * cases where the sink may still be asleep. |
2308 | * supposed to retry 3 times per the spec. |
1909 | */ |
2309 | */ |
1910 | static bool |
2310 | static ssize_t |
1911 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
2311 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
1912 | uint8_t *recv, int recv_bytes) |
2312 | void *buffer, size_t size) |
- | 2313 | { |
|
1913 | { |
2314 | ssize_t ret; |
Line 1914... | Line -... | ||
1914 | int ret, i; |
- | |
1915 | - | ||
1916 | /* |
- | |
1917 | * Sinks are *supposed* to come up within 1ms from an off state, |
- | |
1918 | * but we're also supposed to retry 3 times per the spec. |
2315 | int i; |
1919 | */ |
2316 | |
1920 | for (i = 0; i < 3; i++) { |
- | |
1921 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
2317 | for (i = 0; i < 3; i++) { |
1922 | recv_bytes); |
2318 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
1923 | if (ret == recv_bytes) |
2319 | if (ret == size) |
1924 | return true; |
2320 | return ret; |
Line 1925... | Line 2321... | ||
1925 | msleep(1); |
2321 | msleep(1); |
1926 | } |
2322 | } |
Line 1927... | Line 2323... | ||
1927 | 2323 | ||
1928 | return false; |
2324 | return ret; |
1929 | } |
2325 | } |
1930 | 2326 | ||
1931 | /* |
2327 | /* |
1932 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
2328 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
1933 | * link status information |
2329 | * link status information |
1934 | */ |
2330 | */ |
1935 | static bool |
2331 | static bool |
1936 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2332 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
1937 | { |
2333 | { |
1938 | return intel_dp_aux_native_read_retry(intel_dp, |
2334 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
Line 1939... | Line -... | ||
1939 | DP_LANE0_1_STATUS, |
- | |
1940 | link_status, |
2335 | DP_LANE0_1_STATUS, |
1941 | DP_LINK_STATUS_SIZE); |
- | |
1942 | } |
- | |
1943 | - | ||
1944 | /* |
2336 | link_status, |
1945 | * These are source-specific values; current Intel hardware supports |
2337 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
1946 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
2338 | } |
1947 | */ |
2339 | |
1948 | 2340 | /* These are source-specific values. */ |
|
Line 1949... | Line 2341... | ||
1949 | static uint8_t |
2341 | static uint8_t |
1950 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2342 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1951 | { |
2343 | { |
1952 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2344 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1953 | enum port port = dp_to_dig_port(intel_dp)->port; |
2345 | enum port port = dp_to_dig_port(intel_dp)->port; |
1954 | 2346 | ||
Line 1966... | Line 2358... | ||
1966 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2358 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
1967 | { |
2359 | { |
1968 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2360 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1969 | enum port port = dp_to_dig_port(intel_dp)->port; |
2361 | enum port port = dp_to_dig_port(intel_dp)->port; |
Line 1970... | Line 2362... | ||
1970 | 2362 | ||
1971 | if (IS_BROADWELL(dev)) { |
- | |
1972 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
- | |
1973 | case DP_TRAIN_VOLTAGE_SWING_400: |
- | |
1974 | case DP_TRAIN_VOLTAGE_SWING_600: |
- | |
1975 | return DP_TRAIN_PRE_EMPHASIS_6; |
- | |
1976 | case DP_TRAIN_VOLTAGE_SWING_800: |
- | |
1977 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
- | |
1978 | case DP_TRAIN_VOLTAGE_SWING_1200: |
- | |
1979 | default: |
- | |
1980 | return DP_TRAIN_PRE_EMPHASIS_0; |
- | |
1981 | } |
- | |
1982 | } else if (IS_HASWELL(dev)) { |
2363 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1983 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2364 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1984 | case DP_TRAIN_VOLTAGE_SWING_400: |
2365 | case DP_TRAIN_VOLTAGE_SWING_400: |
1985 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2366 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
1986 | case DP_TRAIN_VOLTAGE_SWING_600: |
2367 | case DP_TRAIN_VOLTAGE_SWING_600: |
Line 2126... | Line 2507... | ||
2126 | mutex_unlock(&dev_priv->dpio_lock); |
2507 | mutex_unlock(&dev_priv->dpio_lock); |
Line 2127... | Line 2508... | ||
2127 | 2508 | ||
2128 | return 0; |
2509 | return 0; |
Line -... | Line 2510... | ||
- | 2510 | } |
|
- | 2511 | ||
- | 2512 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
|
- | 2513 | { |
|
- | 2514 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 2515 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2516 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2517 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
|
- | 2518 | u32 deemph_reg_value, margin_reg_value, val; |
|
- | 2519 | uint8_t train_set = intel_dp->train_set[0]; |
|
- | 2520 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2521 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2522 | int i; |
|
- | 2523 | ||
- | 2524 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
|
- | 2525 | case DP_TRAIN_PRE_EMPHASIS_0: |
|
- | 2526 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2527 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2528 | deemph_reg_value = 128; |
|
- | 2529 | margin_reg_value = 52; |
|
- | 2530 | break; |
|
- | 2531 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2532 | deemph_reg_value = 128; |
|
- | 2533 | margin_reg_value = 77; |
|
- | 2534 | break; |
|
- | 2535 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 2536 | deemph_reg_value = 128; |
|
- | 2537 | margin_reg_value = 102; |
|
- | 2538 | break; |
|
- | 2539 | case DP_TRAIN_VOLTAGE_SWING_1200: |
|
- | 2540 | deemph_reg_value = 128; |
|
- | 2541 | margin_reg_value = 154; |
|
- | 2542 | /* FIXME extra to set for 1200 */ |
|
- | 2543 | break; |
|
- | 2544 | default: |
|
- | 2545 | return 0; |
|
- | 2546 | } |
|
- | 2547 | break; |
|
- | 2548 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
|
- | 2549 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2550 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2551 | deemph_reg_value = 85; |
|
- | 2552 | margin_reg_value = 78; |
|
- | 2553 | break; |
|
- | 2554 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2555 | deemph_reg_value = 85; |
|
- | 2556 | margin_reg_value = 116; |
|
- | 2557 | break; |
|
- | 2558 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 2559 | deemph_reg_value = 85; |
|
- | 2560 | margin_reg_value = 154; |
|
- | 2561 | break; |
|
- | 2562 | default: |
|
- | 2563 | return 0; |
|
- | 2564 | } |
|
- | 2565 | break; |
|
- | 2566 | case DP_TRAIN_PRE_EMPHASIS_6: |
|
- | 2567 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2568 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2569 | deemph_reg_value = 64; |
|
- | 2570 | margin_reg_value = 104; |
|
- | 2571 | break; |
|
- | 2572 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2573 | deemph_reg_value = 64; |
|
- | 2574 | margin_reg_value = 154; |
|
- | 2575 | break; |
|
- | 2576 | default: |
|
- | 2577 | return 0; |
|
- | 2578 | } |
|
- | 2579 | break; |
|
- | 2580 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
|
- | 2581 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2582 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2583 | deemph_reg_value = 43; |
|
- | 2584 | margin_reg_value = 154; |
|
- | 2585 | break; |
|
- | 2586 | default: |
|
- | 2587 | return 0; |
|
- | 2588 | } |
|
- | 2589 | break; |
|
- | 2590 | default: |
|
- | 2591 | return 0; |
|
- | 2592 | } |
|
- | 2593 | ||
- | 2594 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2595 | ||
- | 2596 | /* Clear calc init */ |
|
- | 2597 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
|
- | 2598 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 2599 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
|
- | 2600 | ||
- | 2601 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 2602 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 2603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 2604 | ||
- | 2605 | /* Program swing deemph */ |
|
- | 2606 | for (i = 0; i < 4; i++) { |
|
- | 2607 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
|
- | 2608 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
|
- | 2609 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
|
- | 2610 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
|
- | 2611 | } |
|
- | 2612 | ||
- | 2613 | /* Program swing margin */ |
|
- | 2614 | for (i = 0; i < 4; i++) { |
|
- | 2615 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
|
- | 2616 | val &= ~DPIO_SWING_MARGIN_MASK; |
|
- | 2617 | val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; |
|
- | 2618 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
|
- | 2619 | } |
|
- | 2620 | ||
- | 2621 | /* Disable unique transition scale */ |
|
- | 2622 | for (i = 0; i < 4; i++) { |
|
- | 2623 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
|
- | 2624 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
|
- | 2625 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
|
- | 2626 | } |
|
- | 2627 | ||
- | 2628 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
|
- | 2629 | == DP_TRAIN_PRE_EMPHASIS_0) && |
|
- | 2630 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
|
- | 2631 | == DP_TRAIN_VOLTAGE_SWING_1200)) { |
|
- | 2632 | ||
- | 2633 | /* |
|
- | 2634 | * The document said it needs to set bit 27 for ch0 and bit 26 |
|
- | 2635 | * for ch1. Might be a typo in the doc. |
|
- | 2636 | * For now, for this unique transition scale selection, set bit |
|
- | 2637 | * 27 for ch0 and ch1. |
|
- | 2638 | */ |
|
- | 2639 | for (i = 0; i < 4; i++) { |
|
- | 2640 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
|
- | 2641 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
|
- | 2642 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
|
- | 2643 | } |
|
- | 2644 | ||
- | 2645 | for (i = 0; i < 4; i++) { |
|
- | 2646 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
|
- | 2647 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
|
- | 2648 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
|
- | 2649 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
|
- | 2650 | } |
|
- | 2651 | } |
|
- | 2652 | ||
- | 2653 | /* Start swing calculation */ |
|
- | 2654 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
|
- | 2655 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
|
- | 2656 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
|
- | 2657 | ||
- | 2658 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 2659 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
|
- | 2660 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 2661 | ||
- | 2662 | /* LRC Bypass */ |
|
- | 2663 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
|
- | 2664 | val |= DPIO_LRC_BYPASS; |
|
- | 2665 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
|
- | 2666 | ||
- | 2667 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2668 | ||
- | 2669 | return 0; |
|
2129 | } |
2670 | } |
2130 | 2671 | ||
2131 | static void |
2672 | static void |
2132 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2673 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2133 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2674 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Line 2289... | Line 2830... | ||
2289 | "0x%x\n", signal_levels); |
2830 | "0x%x\n", signal_levels); |
2290 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2831 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2291 | } |
2832 | } |
2292 | } |
2833 | } |
Line 2293... | Line -... | ||
2293 | - | ||
2294 | static uint32_t |
- | |
2295 | intel_bdw_signal_levels(uint8_t train_set) |
- | |
2296 | { |
- | |
2297 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
- | |
2298 | DP_TRAIN_PRE_EMPHASIS_MASK); |
- | |
2299 | switch (signal_levels) { |
- | |
2300 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2301 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
- | |
2302 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2303 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ |
- | |
2304 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
- | |
2305 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ |
- | |
2306 | - | ||
2307 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2308 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ |
- | |
2309 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2310 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ |
- | |
2311 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
- | |
2312 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ |
- | |
2313 | - | ||
2314 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2315 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ |
- | |
2316 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2317 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ |
- | |
2318 | - | ||
2319 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2320 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ |
- | |
2321 | - | ||
2322 | default: |
- | |
2323 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
- | |
2324 | "0x%x\n", signal_levels); |
- | |
2325 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
- | |
2326 | } |
- | |
2327 | } |
- | |
2328 | 2834 | ||
2329 | /* Properly updates "DP" with the correct signal levels. */ |
2835 | /* Properly updates "DP" with the correct signal levels. */ |
2330 | static void |
2836 | static void |
2331 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
2837 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
2332 | { |
2838 | { |
2333 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2839 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2334 | enum port port = intel_dig_port->port; |
2840 | enum port port = intel_dig_port->port; |
2335 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2841 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2336 | uint32_t signal_levels, mask; |
2842 | uint32_t signal_levels, mask; |
Line 2337... | Line 2843... | ||
2337 | uint8_t train_set = intel_dp->train_set[0]; |
2843 | uint8_t train_set = intel_dp->train_set[0]; |
2338 | - | ||
2339 | if (IS_BROADWELL(dev)) { |
- | |
2340 | signal_levels = intel_bdw_signal_levels(train_set); |
- | |
2341 | mask = DDI_BUF_EMP_MASK; |
2844 | |
2342 | } else if (IS_HASWELL(dev)) { |
2845 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
- | 2846 | signal_levels = intel_hsw_signal_levels(train_set); |
|
- | 2847 | mask = DDI_BUF_EMP_MASK; |
|
- | 2848 | } else if (IS_CHERRYVIEW(dev)) { |
|
2343 | signal_levels = intel_hsw_signal_levels(train_set); |
2849 | signal_levels = intel_chv_signal_levels(intel_dp); |
2344 | mask = DDI_BUF_EMP_MASK; |
2850 | mask = 0; |
2345 | } else if (IS_VALLEYVIEW(dev)) { |
2851 | } else if (IS_VALLEYVIEW(dev)) { |
2346 | signal_levels = intel_vlv_signal_levels(intel_dp); |
2852 | signal_levels = intel_vlv_signal_levels(intel_dp); |
2347 | mask = 0; |
2853 | mask = 0; |
Line 2450... | Line 2956... | ||
2450 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
2956 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
2451 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
2957 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
2452 | len = intel_dp->lane_count + 1; |
2958 | len = intel_dp->lane_count + 1; |
2453 | } |
2959 | } |
Line 2454... | Line 2960... | ||
2454 | 2960 | ||
2455 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, |
2961 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
Line 2456... | Line 2962... | ||
2456 | buf, len); |
2962 | buf, len); |
2457 | 2963 | ||
Line 2480... | Line 2986... | ||
2480 | intel_dp_set_signal_levels(intel_dp, DP); |
2986 | intel_dp_set_signal_levels(intel_dp, DP); |
Line 2481... | Line 2987... | ||
2481 | 2987 | ||
2482 | I915_WRITE(intel_dp->output_reg, *DP); |
2988 | I915_WRITE(intel_dp->output_reg, *DP); |
Line 2483... | Line 2989... | ||
2483 | POSTING_READ(intel_dp->output_reg); |
2989 | POSTING_READ(intel_dp->output_reg); |
2484 | - | ||
2485 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, |
2990 | |
Line 2486... | Line 2991... | ||
2486 | intel_dp->train_set, |
2991 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2487 | intel_dp->lane_count); |
2992 | intel_dp->train_set, intel_dp->lane_count); |
Line 2488... | Line 2993... | ||
2488 | 2993 | ||
Line 2538... | Line 3043... | ||
2538 | /* Write the link configuration data */ |
3043 | /* Write the link configuration data */ |
2539 | link_config[0] = intel_dp->link_bw; |
3044 | link_config[0] = intel_dp->link_bw; |
2540 | link_config[1] = intel_dp->lane_count; |
3045 | link_config[1] = intel_dp->lane_count; |
2541 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3046 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2542 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
3047 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
2543 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); |
3048 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
Line 2544... | Line 3049... | ||
2544 | 3049 | ||
2545 | link_config[0] = 0; |
3050 | link_config[0] = 0; |
2546 | link_config[1] = DP_SET_ANSI_8B10B; |
3051 | link_config[1] = DP_SET_ANSI_8B10B; |
Line 2547... | Line 3052... | ||
2547 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); |
3052 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
Line 2548... | Line 3053... | ||
2548 | 3053 | ||
2549 | DP |= DP_PORT_EN; |
3054 | DP |= DP_PORT_EN; |
Line 2615... | Line 3120... | ||
2615 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
3120 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2616 | { |
3121 | { |
2617 | bool channel_eq = false; |
3122 | bool channel_eq = false; |
2618 | int tries, cr_tries; |
3123 | int tries, cr_tries; |
2619 | uint32_t DP = intel_dp->DP; |
3124 | uint32_t DP = intel_dp->DP; |
- | 3125 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
|
- | 3126 | ||
- | 3127 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
|
- | 3128 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
|
- | 3129 | training_pattern = DP_TRAINING_PATTERN_3; |
|
Line 2620... | Line 3130... | ||
2620 | 3130 | ||
2621 | /* channel equalization */ |
3131 | /* channel equalization */ |
2622 | if (!intel_dp_set_link_train(intel_dp, &DP, |
3132 | if (!intel_dp_set_link_train(intel_dp, &DP, |
2623 | DP_TRAINING_PATTERN_2 | |
3133 | training_pattern | |
2624 | DP_LINK_SCRAMBLING_DISABLE)) { |
3134 | DP_LINK_SCRAMBLING_DISABLE)) { |
2625 | DRM_ERROR("failed to start channel equalization\n"); |
3135 | DRM_ERROR("failed to start channel equalization\n"); |
2626 | return; |
3136 | return; |
Line 2645... | Line 3155... | ||
2645 | 3155 | ||
2646 | /* Make sure clock is still ok */ |
3156 | /* Make sure clock is still ok */ |
2647 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
3157 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2648 | intel_dp_start_link_train(intel_dp); |
3158 | intel_dp_start_link_train(intel_dp); |
2649 | intel_dp_set_link_train(intel_dp, &DP, |
3159 | intel_dp_set_link_train(intel_dp, &DP, |
2650 | DP_TRAINING_PATTERN_2 | |
3160 | training_pattern | |
2651 | DP_LINK_SCRAMBLING_DISABLE); |
3161 | DP_LINK_SCRAMBLING_DISABLE); |
2652 | cr_tries++; |
3162 | cr_tries++; |
2653 | continue; |
3163 | continue; |
Line 2661... | Line 3171... | ||
2661 | /* Try 5 times, then try clock recovery if that fails */ |
3171 | /* Try 5 times, then try clock recovery if that fails */ |
2662 | if (tries > 5) { |
3172 | if (tries > 5) { |
2663 | intel_dp_link_down(intel_dp); |
3173 | intel_dp_link_down(intel_dp); |
2664 | intel_dp_start_link_train(intel_dp); |
3174 | intel_dp_start_link_train(intel_dp); |
2665 | intel_dp_set_link_train(intel_dp, &DP, |
3175 | intel_dp_set_link_train(intel_dp, &DP, |
2666 | DP_TRAINING_PATTERN_2 | |
3176 | training_pattern | |
2667 | DP_LINK_SCRAMBLING_DISABLE); |
3177 | DP_LINK_SCRAMBLING_DISABLE); |
2668 | tries = 0; |
3178 | tries = 0; |
2669 | cr_tries++; |
3179 | cr_tries++; |
2670 | continue; |
3180 | continue; |
2671 | } |
3181 | } |
Line 2702... | Line 3212... | ||
2702 | struct drm_i915_private *dev_priv = dev->dev_private; |
3212 | struct drm_i915_private *dev_priv = dev->dev_private; |
2703 | struct intel_crtc *intel_crtc = |
3213 | struct intel_crtc *intel_crtc = |
2704 | to_intel_crtc(intel_dig_port->base.base.crtc); |
3214 | to_intel_crtc(intel_dig_port->base.base.crtc); |
2705 | uint32_t DP = intel_dp->DP; |
3215 | uint32_t DP = intel_dp->DP; |
Line 2706... | Line -... | ||
2706 | - | ||
2707 | /* |
- | |
2708 | * DDI code has a strict mode set sequence and we should try to respect |
- | |
2709 | * it, otherwise we might hang the machine in many different ways. So we |
- | |
2710 | * really should be disabling the port only on a complete crtc_disable |
- | |
2711 | * sequence. This function is just called under two conditions on DDI |
- | |
2712 | * code: |
- | |
2713 | * - Link train failed while doing crtc_enable, and on this case we |
- | |
2714 | * really should respect the mode set sequence and wait for a |
- | |
2715 | * crtc_disable. |
- | |
2716 | * - Someone turned the monitor off and intel_dp_check_link_status |
- | |
2717 | * called us. We don't need to disable the whole port on this case, so |
- | |
2718 | * when someone turns the monitor on again, |
- | |
2719 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
- | |
2720 | * train. |
- | |
2721 | */ |
3216 | |
2722 | if (HAS_DDI(dev)) |
3217 | if (WARN_ON(HAS_DDI(dev))) |
Line 2723... | Line 3218... | ||
2723 | return; |
3218 | return; |
2724 | 3219 | ||
Line 2734... | Line 3229... | ||
2734 | DP &= ~DP_LINK_TRAIN_MASK; |
3229 | DP &= ~DP_LINK_TRAIN_MASK; |
2735 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
3230 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
2736 | } |
3231 | } |
2737 | POSTING_READ(intel_dp->output_reg); |
3232 | POSTING_READ(intel_dp->output_reg); |
Line 2738... | Line -... | ||
2738 | - | ||
2739 | /* We don't really know why we're doing this */ |
- | |
2740 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
- | |
2741 | 3233 | ||
2742 | if (HAS_PCH_IBX(dev) && |
3234 | if (HAS_PCH_IBX(dev) && |
2743 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
3235 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Line 2744... | Line 3236... | ||
2744 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
3236 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
Line 2780... | Line 3272... | ||
2780 | struct drm_device *dev = dig_port->base.base.dev; |
3272 | struct drm_device *dev = dig_port->base.base.dev; |
2781 | struct drm_i915_private *dev_priv = dev->dev_private; |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2782... | Line 3274... | ||
2782 | 3274 | ||
Line 2783... | Line 3275... | ||
2783 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
3275 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2784 | 3276 | ||
2785 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
3277 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
Line 2786... | Line 3278... | ||
2786 | sizeof(intel_dp->dpcd)) == 0) |
3278 | sizeof(intel_dp->dpcd)) < 0) |
2787 | return false; /* aux transfer failed */ |
3279 | return false; /* aux transfer failed */ |
2788 | 3280 | ||
Line 2794... | Line 3286... | ||
2794 | return false; /* DPCD not present */ |
3286 | return false; /* DPCD not present */ |
Line 2795... | Line 3287... | ||
2795 | 3287 | ||
2796 | /* Check if the panel supports PSR */ |
3288 | /* Check if the panel supports PSR */ |
2797 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3289 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
2798 | if (is_edp(intel_dp)) { |
3290 | if (is_edp(intel_dp)) { |
2799 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, |
3291 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
2800 | intel_dp->psr_dpcd, |
3292 | intel_dp->psr_dpcd, |
2801 | sizeof(intel_dp->psr_dpcd)); |
3293 | sizeof(intel_dp->psr_dpcd)); |
2802 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3294 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2803 | dev_priv->psr.sink_support = true; |
3295 | dev_priv->psr.sink_support = true; |
2804 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3296 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
2805 | } |
3297 | } |
Line -... | Line 3298... | ||
- | 3298 | } |
|
- | 3299 | ||
- | 3300 | /* Training Pattern 3 support */ |
|
- | 3301 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
|
- | 3302 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
|
- | 3303 | intel_dp->use_tps3 = true; |
|
- | 3304 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
|
- | 3305 | } else |
|
2806 | } |
3306 | intel_dp->use_tps3 = false; |
2807 | 3307 | ||
2808 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3308 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
Line 2809... | Line 3309... | ||
2809 | DP_DWN_STRM_PORT_PRESENT)) |
3309 | DP_DWN_STRM_PORT_PRESENT)) |
2810 | return true; /* native DP sink */ |
3310 | return true; /* native DP sink */ |
Line 2811... | Line 3311... | ||
2811 | 3311 | ||
2812 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
3312 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
2813 | return true; /* no per-port downstream info */ |
3313 | return true; /* no per-port downstream info */ |
2814 | 3314 | ||
Line 2815... | Line 3315... | ||
2815 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
3315 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
2816 | intel_dp->downstream_ports, |
3316 | intel_dp->downstream_ports, |
Line 2826... | Line 3326... | ||
2826 | u8 buf[3]; |
3326 | u8 buf[3]; |
Line 2827... | Line 3327... | ||
2827 | 3327 | ||
2828 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3328 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
Line 2829... | Line 3329... | ||
2829 | return; |
3329 | return; |
Line 2830... | Line 3330... | ||
2830 | 3330 | ||
2831 | ironlake_edp_panel_vdd_on(intel_dp); |
3331 | intel_edp_panel_vdd_on(intel_dp); |
2832 | 3332 | ||
Line 2833... | Line 3333... | ||
2833 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
3333 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
2834 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3334 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
2835 | buf[0], buf[1], buf[2]); |
3335 | buf[0], buf[1], buf[2]); |
Line 2836... | Line 3336... | ||
2836 | 3336 | ||
- | 3337 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
|
- | 3338 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
|
- | 3339 | buf[0], buf[1], buf[2]); |
|
- | 3340 | ||
- | 3341 | edp_panel_vdd_off(intel_dp, false); |
|
- | 3342 | } |
|
- | 3343 | ||
- | 3344 | static bool |
|
- | 3345 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
|
- | 3346 | { |
|
- | 3347 | u8 buf[1]; |
|
- | 3348 | ||
- | 3349 | if (!intel_dp->can_mst) |
|
- | 3350 | return false; |
|
- | 3351 | ||
- | 3352 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
|
- | 3353 | return false; |
|
- | 3354 | ||
- | 3355 | _edp_panel_vdd_on(intel_dp); |
|
- | 3356 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
|
- | 3357 | if (buf[0] & DP_MST_CAP) { |
|
- | 3358 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
|
- | 3359 | intel_dp->is_mst = true; |
|
- | 3360 | } else { |
|
- | 3361 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
|
- | 3362 | intel_dp->is_mst = false; |
|
- | 3363 | } |
|
- | 3364 | } |
|
- | 3365 | edp_panel_vdd_off(intel_dp, false); |
|
- | 3366 | ||
- | 3367 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
- | 3368 | return intel_dp->is_mst; |
|
- | 3369 | } |
|
- | 3370 | ||
- | 3371 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
|
- | 3372 | { |
|
- | 3373 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3374 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 3375 | struct intel_crtc *intel_crtc = |
|
- | 3376 | to_intel_crtc(intel_dig_port->base.base.crtc); |
|
- | 3377 | u8 buf[1]; |
|
- | 3378 | ||
- | 3379 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
|
- | 3380 | return -EAGAIN; |
|
- | 3381 | ||
- | 3382 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
|
- | 3383 | return -ENOTTY; |
|
- | 3384 | ||
- | 3385 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
|
- | 3386 | DP_TEST_SINK_START) < 0) |
|
- | 3387 | return -EAGAIN; |
|
- | 3388 | ||
- | 3389 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
|
- | 3390 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 3391 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 3392 | ||
2837 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
3393 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
Line 2838... | Line 3394... | ||
2838 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3394 | return -EAGAIN; |
2839 | buf[0], buf[1], buf[2]); |
3395 | |
2840 | 3396 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
|
- | 3397 | return 0; |
|
- | 3398 | } |
|
- | 3399 | ||
- | 3400 | static bool |
|
- | 3401 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
|
- | 3402 | { |
|
- | 3403 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
|
- | 3404 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
|
2841 | ironlake_edp_panel_vdd_off(intel_dp, false); |
3405 | sink_irq_vector, 1) == 1; |
Line 2842... | Line 3406... | ||
2842 | } |
3406 | } |
2843 | 3407 | ||
2844 | static bool |
3408 | static bool |
2845 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
3409 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
2846 | { |
3410 | { |
Line 2847... | Line 3411... | ||
2847 | int ret; |
3411 | int ret; |
2848 | 3412 | ||
Line 2849... | Line 3413... | ||
2849 | ret = intel_dp_aux_native_read_retry(intel_dp, |
3413 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
2850 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3414 | DP_SINK_COUNT_ESI, |
2851 | sink_irq_vector, 1); |
3415 | sink_irq_vector, 14); |
2852 | if (!ret) |
3416 | if (ret != 14) |
2853 | return false; |
3417 | return false; |
- | 3418 | ||
- | 3419 | return true; |
|
- | 3420 | } |
|
- | 3421 | ||
- | 3422 | static void |
|
- | 3423 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
|
- | 3424 | { |
|
- | 3425 | /* NAK by default */ |
|
- | 3426 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
|
- | 3427 | } |
|
- | 3428 | ||
- | 3429 | static int |
|
- | 3430 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
|
- | 3431 | { |
|
- | 3432 | bool bret; |
|
- | 3433 | ||
- | 3434 | if (intel_dp->is_mst) { |
|
- | 3435 | u8 esi[16] = { 0 }; |
|
- | 3436 | int ret = 0; |
|
- | 3437 | int retry; |
|
- | 3438 | bool handled; |
|
- | 3439 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
|
- | 3440 | go_again: |
|
- | 3441 | if (bret == true) { |
|
- | 3442 | ||
- | 3443 | /* check link status - esi[10] = 0x200c */ |
|
- | 3444 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
|
- | 3445 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
|
- | 3446 | intel_dp_start_link_train(intel_dp); |
|
- | 3447 | intel_dp_complete_link_train(intel_dp); |
|
- | 3448 | intel_dp_stop_link_train(intel_dp); |
|
- | 3449 | } |
|
- | 3450 | ||
- | 3451 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
|
- | 3452 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
|
- | 3453 | ||
- | 3454 | if (handled) { |
|
- | 3455 | for (retry = 0; retry < 3; retry++) { |
|
- | 3456 | int wret; |
|
- | 3457 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
|
- | 3458 | DP_SINK_COUNT_ESI+1, |
|
- | 3459 | &esi[1], 3); |
|
- | 3460 | if (wret == 3) { |
|
- | 3461 | break; |
|
- | 3462 | } |
|
- | 3463 | } |
|
- | 3464 | ||
- | 3465 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
|
- | 3466 | if (bret == true) { |
|
- | 3467 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
|
- | 3468 | goto go_again; |
|
- | 3469 | } |
|
- | 3470 | } else |
|
- | 3471 | ret = 0; |
|
- | 3472 | ||
- | 3473 | return ret; |
|
- | 3474 | } else { |
|
2854 | 3475 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
Line 2855... | Line 3476... | ||
2855 | return true; |
3476 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
2856 | } |
3477 | intel_dp->is_mst = false; |
2857 | 3478 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
2858 | static void |
3479 | /* send a hotplug event */ |
2859 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
3480 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
2860 | { |
3481 | } |
2861 | /* NAK by default */ |
3482 | } |
2862 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
3483 | return -EINVAL; |
2863 | } |
- | |
2864 | 3484 | } |
|
2865 | /* |
3485 | |
2866 | * According to DP spec |
3486 | /* |
- | 3487 | * According to DP spec |
|
2867 | * 5.1.2: |
3488 | * 5.1.2: |
2868 | * 1. Read DPCD |
3489 | * 1. Read DPCD |
2869 | * 2. Configure link according to Receiver Capabilities |
3490 | * 2. Configure link according to Receiver Capabilities |
Line -... | Line 3491... | ||
- | 3491 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
|
- | 3492 | * 4. Check link status on receipt of hot-plug interrupt |
|
2870 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
3493 | */ |
2871 | * 4. Check link status on receipt of hot-plug interrupt |
3494 | void |
Line 2872... | Line 3495... | ||
2872 | */ |
3495 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
2873 | 3496 | { |
|
Line -... | Line 3497... | ||
- | 3497 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 3498 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
|
- | 3499 | u8 sink_irq_vector; |
|
2874 | void |
3500 | u8 link_status[DP_LINK_STATUS_SIZE]; |
2875 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
3501 | |
2876 | { |
3502 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
2877 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
3503 | |
Line 2896... | Line 3522... | ||
2896 | 3522 | ||
2897 | /* Try to read the source of the interrupt */ |
3523 | /* Try to read the source of the interrupt */ |
2898 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3524 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2899 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
3525 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
2900 | /* Clear interrupt source */ |
3526 | /* Clear interrupt source */ |
2901 | intel_dp_aux_native_write_1(intel_dp, |
3527 | drm_dp_dpcd_writeb(&intel_dp->aux, |
2902 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3528 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
Line 2903... | Line 3529... | ||
2903 | sink_irq_vector); |
3529 | sink_irq_vector); |
2904 | 3530 | ||
Line 2908... | Line 3534... | ||
2908 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
3534 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
2909 | } |
3535 | } |
Line 2910... | Line 3536... | ||
2910 | 3536 | ||
2911 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3537 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2912 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
3538 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
2913 | drm_get_encoder_name(&intel_encoder->base)); |
3539 | intel_encoder->base.name); |
2914 | intel_dp_start_link_train(intel_dp); |
3540 | intel_dp_start_link_train(intel_dp); |
2915 | intel_dp_complete_link_train(intel_dp); |
3541 | intel_dp_complete_link_train(intel_dp); |
2916 | intel_dp_stop_link_train(intel_dp); |
3542 | intel_dp_stop_link_train(intel_dp); |
2917 | } |
3543 | } |
Line 2933... | Line 3559... | ||
2933 | 3559 | ||
2934 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
3560 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
2935 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3561 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2936 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
3562 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
- | 3563 | uint8_t reg; |
|
2937 | uint8_t reg; |
3564 | |
2938 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
3565 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
2939 | ®, 1)) |
3566 | ®, 1) < 0) |
- | 3567 | return connector_status_unknown; |
|
2940 | return connector_status_unknown; |
3568 | |
2941 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3569 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
2942 | : connector_status_disconnected; |
3570 | : connector_status_disconnected; |
Line 2943... | Line 3571... | ||
2943 | } |
3571 | } |
2944 | 3572 | ||
2945 | /* If no HPD, poke DDC gently */ |
3573 | /* If no HPD, poke DDC gently */ |
Line 2946... | Line 3574... | ||
2946 | if (drm_probe_ddc(&intel_dp->adapter)) |
3574 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
2947 | return connector_status_connected; |
3575 | return connector_status_connected; |
2948 | 3576 | ||
Line 3083... | Line 3711... | ||
3083 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3711 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3084 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3712 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3085 | struct drm_device *dev = connector->dev; |
3713 | struct drm_device *dev = connector->dev; |
3086 | struct drm_i915_private *dev_priv = dev->dev_private; |
3714 | struct drm_i915_private *dev_priv = dev->dev_private; |
3087 | enum drm_connector_status status; |
3715 | enum drm_connector_status status; |
- | 3716 | enum intel_display_power_domain power_domain; |
|
3088 | struct edid *edid = NULL; |
3717 | struct edid *edid = NULL; |
- | 3718 | bool ret; |
|
Line -... | Line 3719... | ||
- | 3719 | ||
3089 | 3720 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
Line 3090... | Line 3721... | ||
3090 | intel_runtime_pm_get(dev_priv); |
3721 | intel_display_power_get(dev_priv, power_domain); |
3091 | 3722 | ||
- | 3723 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 3724 | connector->base.id, connector->name); |
|
- | 3725 | ||
- | 3726 | if (intel_dp->is_mst) { |
|
- | 3727 | /* MST devices are disconnected from a monitor POV */ |
|
- | 3728 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 3729 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 3730 | status = connector_status_disconnected; |
|
Line 3092... | Line 3731... | ||
3092 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3731 | goto out; |
Line 3093... | Line 3732... | ||
3093 | connector->base.id, drm_get_connector_name(connector)); |
3732 | } |
3094 | 3733 | ||
Line 3102... | Line 3741... | ||
3102 | if (status != connector_status_connected) |
3741 | if (status != connector_status_connected) |
3103 | goto out; |
3742 | goto out; |
Line 3104... | Line 3743... | ||
3104 | 3743 | ||
Line -... | Line 3744... | ||
- | 3744 | intel_dp_probe_oui(intel_dp); |
|
- | 3745 | ||
- | 3746 | ret = intel_dp_probe_mst(intel_dp); |
|
- | 3747 | if (ret) { |
|
- | 3748 | /* if we are in MST mode then this connector |
|
- | 3749 | won't appear connected or have anything with EDID on it */ |
|
- | 3750 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 3751 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 3752 | status = connector_status_disconnected; |
|
- | 3753 | goto out; |
|
3105 | intel_dp_probe_oui(intel_dp); |
3754 | } |
3106 | 3755 | ||
3107 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3756 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3108 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
3757 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
3109 | } else { |
3758 | } else { |
3110 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
3759 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3111 | if (edid) { |
3760 | if (edid) { |
3112 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
3761 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
3113 | kfree(edid); |
3762 | kfree(edid); |
Line 3117... | Line 3766... | ||
3117 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3766 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3118 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3767 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3119 | status = connector_status_connected; |
3768 | status = connector_status_connected; |
Line 3120... | Line 3769... | ||
3120 | 3769 | ||
3121 | out: |
3770 | out: |
3122 | intel_runtime_pm_put(dev_priv); |
3771 | intel_display_power_put(dev_priv, power_domain); |
3123 | return status; |
3772 | return status; |
Line 3124... | Line 3773... | ||
3124 | } |
3773 | } |
3125 | 3774 | ||
3126 | static int intel_dp_get_modes(struct drm_connector *connector) |
3775 | static int intel_dp_get_modes(struct drm_connector *connector) |
- | 3776 | { |
|
- | 3777 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
|
3127 | { |
3778 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3128 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3779 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
- | 3780 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
- | 3781 | struct drm_device *dev = connector->dev; |
|
3129 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3782 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 3130... | Line 3783... | ||
3130 | struct drm_device *dev = connector->dev; |
3783 | enum intel_display_power_domain power_domain; |
3131 | int ret; |
3784 | int ret; |
Line -... | Line 3785... | ||
- | 3785 | ||
- | 3786 | /* We should parse the EDID data and find out if it has an audio sink |
|
- | 3787 | */ |
|
3132 | 3788 | ||
- | 3789 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
3133 | /* We should parse the EDID data and find out if it has an audio sink |
3790 | intel_display_power_get(dev_priv, power_domain); |
3134 | */ |
3791 | |
Line 3135... | Line 3792... | ||
3135 | 3792 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
|
3136 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
3793 | intel_display_power_put(dev_priv, power_domain); |
Line 3152... | Line 3809... | ||
3152 | 3809 | ||
3153 | static bool |
3810 | static bool |
3154 | intel_dp_detect_audio(struct drm_connector *connector) |
3811 | intel_dp_detect_audio(struct drm_connector *connector) |
3155 | { |
3812 | { |
- | 3813 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
|
- | 3814 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3815 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 3816 | struct drm_device *dev = connector->dev; |
|
- | 3817 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
3156 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3818 | enum intel_display_power_domain power_domain; |
3157 | struct edid *edid; |
3819 | struct edid *edid; |
Line -... | Line 3820... | ||
- | 3820 | bool has_audio = false; |
|
- | 3821 | ||
- | 3822 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
3158 | bool has_audio = false; |
3823 | intel_display_power_get(dev_priv, power_domain); |
3159 | 3824 | ||
3160 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
3825 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3161 | if (edid) { |
3826 | if (edid) { |
3162 | has_audio = drm_detect_monitor_audio(edid); |
3827 | has_audio = drm_detect_monitor_audio(edid); |
Line -... | Line 3828... | ||
- | 3828 | kfree(edid); |
|
- | 3829 | } |
|
3163 | kfree(edid); |
3830 | |
3164 | } |
3831 | intel_display_power_put(dev_priv, power_domain); |
Line 3165... | Line 3832... | ||
3165 | 3832 | ||
3166 | return has_audio; |
3833 | return has_audio; |
Line 3275... | Line 3942... | ||
3275 | { |
3942 | { |
3276 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3943 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3277 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3944 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3278 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3945 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 3279... | Line 3946... | ||
3279 | 3946 | ||
- | 3947 | drm_dp_aux_unregister(&intel_dp->aux); |
|
3280 | i2c_del_adapter(&intel_dp->adapter); |
3948 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
3281 | drm_encoder_cleanup(encoder); |
3949 | drm_encoder_cleanup(encoder); |
3282 | if (is_edp(intel_dp)) { |
3950 | if (is_edp(intel_dp)) { |
3283 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3951 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3284 | mutex_lock(&dev->mode_config.mutex); |
3952 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3285 | ironlake_panel_vdd_off_sync(intel_dp); |
3953 | edp_panel_vdd_off_sync(intel_dp); |
3286 | mutex_unlock(&dev->mode_config.mutex); |
3954 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
3287 | } |
3955 | } |
3288 | kfree(intel_dig_port); |
3956 | kfree(intel_dig_port); |
Line -... | Line 3957... | ||
- | 3957 | } |
|
- | 3958 | ||
- | 3959 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
|
- | 3960 | { |
|
- | 3961 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
|
- | 3962 | ||
- | 3963 | if (!is_edp(intel_dp)) |
|
- | 3964 | return; |
|
- | 3965 | ||
- | 3966 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 3967 | } |
|
- | 3968 | ||
- | 3969 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
|
- | 3970 | { |
|
- | 3971 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
|
3289 | } |
3972 | } |
3290 | 3973 | ||
3291 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3974 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3292 | .dpms = intel_connector_dpms, |
3975 | .dpms = intel_connector_dpms, |
3293 | .detect = intel_dp_detect, |
3976 | .detect = intel_dp_detect, |
Line 3301... | Line 3984... | ||
3301 | .mode_valid = intel_dp_mode_valid, |
3984 | .mode_valid = intel_dp_mode_valid, |
3302 | .best_encoder = intel_best_encoder, |
3985 | .best_encoder = intel_best_encoder, |
3303 | }; |
3986 | }; |
Line 3304... | Line 3987... | ||
3304 | 3987 | ||
- | 3988 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
|
3305 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
3989 | .reset = intel_dp_encoder_reset, |
3306 | .destroy = intel_dp_encoder_destroy, |
3990 | .destroy = intel_dp_encoder_destroy, |
Line 3307... | Line 3991... | ||
3307 | }; |
3991 | }; |
3308 | 3992 | ||
3309 | static void |
3993 | void |
- | 3994 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
|
- | 3995 | { |
|
- | 3996 | return; |
|
- | 3997 | } |
|
- | 3998 | ||
- | 3999 | bool |
|
3310 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
4000 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
- | 4001 | { |
|
- | 4002 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
- | 4003 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 4004 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 4005 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line -... | Line 4006... | ||
- | 4006 | enum intel_display_power_domain power_domain; |
|
- | 4007 | bool ret = true; |
|
- | 4008 | ||
- | 4009 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
|
- | 4010 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 4011 | ||
- | 4012 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
|
- | 4013 | long_hpd ? "long" : "short"); |
|
- | 4014 | ||
- | 4015 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 4016 | intel_display_power_get(dev_priv, power_domain); |
|
- | 4017 | ||
- | 4018 | if (long_hpd) { |
|
- | 4019 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
|
- | 4020 | goto mst_fail; |
|
- | 4021 | ||
- | 4022 | if (!intel_dp_get_dpcd(intel_dp)) { |
|
- | 4023 | goto mst_fail; |
|
- | 4024 | } |
|
- | 4025 | ||
- | 4026 | intel_dp_probe_oui(intel_dp); |
|
- | 4027 | ||
- | 4028 | if (!intel_dp_probe_mst(intel_dp)) |
|
- | 4029 | goto mst_fail; |
|
- | 4030 | ||
- | 4031 | } else { |
|
- | 4032 | if (intel_dp->is_mst) { |
|
- | 4033 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
|
- | 4034 | goto mst_fail; |
|
- | 4035 | } |
|
- | 4036 | ||
- | 4037 | if (!intel_dp->is_mst) { |
|
- | 4038 | /* |
|
- | 4039 | * we'll check the link status via the normal hot plug path later - |
|
3311 | { |
4040 | * but for short hpds we should check it now |
- | 4041 | */ |
|
- | 4042 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
|
- | 4043 | intel_dp_check_link_status(intel_dp); |
|
- | 4044 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
|
- | 4045 | } |
|
- | 4046 | } |
|
- | 4047 | ret = false; |
|
- | 4048 | goto put_power; |
|
- | 4049 | mst_fail: |
|
- | 4050 | /* if we were in MST mode, and device is not there get out of MST mode */ |
|
- | 4051 | if (intel_dp->is_mst) { |
|
- | 4052 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
|
- | 4053 | intel_dp->is_mst = false; |
|
- | 4054 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
- | 4055 | } |
|
- | 4056 | put_power: |
|
3312 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4057 | intel_display_power_put(dev_priv, power_domain); |
Line 3313... | Line 4058... | ||
3313 | 4058 | ||
3314 | intel_dp_check_link_status(intel_dp); |
4059 | return ret; |
3315 | } |
4060 | } |
Line 3360... | Line 4105... | ||
3360 | return true; |
4105 | return true; |
3361 | } |
4106 | } |
3362 | return false; |
4107 | return false; |
3363 | } |
4108 | } |
Line 3364... | Line 4109... | ||
3364 | 4109 | ||
3365 | static void |
4110 | void |
3366 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4111 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
3367 | { |
4112 | { |
Line 3368... | Line 4113... | ||
3368 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4113 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Line 3379... | Line 4124... | ||
3379 | DRM_MODE_SCALE_ASPECT); |
4124 | DRM_MODE_SCALE_ASPECT); |
3380 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
4125 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
3381 | } |
4126 | } |
3382 | } |
4127 | } |
Line -... | Line 4128... | ||
- | 4128 | ||
- | 4129 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
|
- | 4130 | { |
|
- | 4131 | intel_dp->last_power_cycle = jiffies; |
|
- | 4132 | intel_dp->last_power_on = jiffies; |
|
- | 4133 | intel_dp->last_backlight_off = jiffies; |
|
- | 4134 | } |
|
3383 | 4135 | ||
3384 | static void |
4136 | static void |
3385 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
4137 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
3386 | struct intel_dp *intel_dp, |
4138 | struct intel_dp *intel_dp, |
3387 | struct edp_power_seq *out) |
4139 | struct edp_power_seq *out) |
Line 3501... | Line 4253... | ||
3501 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
4253 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
3502 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
4254 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
3503 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
4255 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
3504 | } |
4256 | } |
Line -... | Line 4257... | ||
- | 4257 | ||
3505 | 4258 | /* |
|
- | 4259 | * And finally store the new values in the power sequencer. The |
|
- | 4260 | * backlight delays are set to 1 because we do manual waits on them. For |
|
- | 4261 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
|
- | 4262 | * we'll end up waiting for the backlight off delay twice: once when we |
|
- | 4263 | * do the manual sleep, and once when we disable the panel and wait for |
|
- | 4264 | * the PP_STATUS bit to become zero. |
|
3506 | /* And finally store the new values in the power sequencer. */ |
4265 | */ |
3507 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
4266 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
3508 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4267 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3509 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
4268 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
3510 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
4269 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
3511 | /* Compute the divisor for the pp clock, simply match the Bspec |
4270 | /* Compute the divisor for the pp clock, simply match the Bspec |
3512 | * formula. */ |
4271 | * formula. */ |
3513 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
4272 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
Line 3538... | Line 4297... | ||
3538 | I915_READ(pp_on_reg), |
4297 | I915_READ(pp_on_reg), |
3539 | I915_READ(pp_off_reg), |
4298 | I915_READ(pp_off_reg), |
3540 | I915_READ(pp_div_reg)); |
4299 | I915_READ(pp_div_reg)); |
3541 | } |
4300 | } |
Line -... | Line 4301... | ||
- | 4301 | ||
- | 4302 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
|
- | 4303 | { |
|
- | 4304 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4305 | struct intel_encoder *encoder; |
|
- | 4306 | struct intel_dp *intel_dp = NULL; |
|
- | 4307 | struct intel_crtc_config *config = NULL; |
|
- | 4308 | struct intel_crtc *intel_crtc = NULL; |
|
- | 4309 | struct intel_connector *intel_connector = dev_priv->drrs.connector; |
|
- | 4310 | u32 reg, val; |
|
- | 4311 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; |
|
- | 4312 | ||
- | 4313 | if (refresh_rate <= 0) { |
|
- | 4314 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
|
- | 4315 | return; |
|
- | 4316 | } |
|
- | 4317 | ||
- | 4318 | if (intel_connector == NULL) { |
|
- | 4319 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); |
|
- | 4320 | return; |
|
- | 4321 | } |
|
- | 4322 | ||
- | 4323 | /* |
|
- | 4324 | * FIXME: This needs proper synchronization with psr state. But really |
|
- | 4325 | * hard to tell without seeing the user of this function of this code. |
|
- | 4326 | * Check locking and ordering once that lands. |
|
- | 4327 | */ |
|
- | 4328 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
|
- | 4329 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
|
- | 4330 | return; |
|
- | 4331 | } |
|
- | 4332 | ||
- | 4333 | encoder = intel_attached_encoder(&intel_connector->base); |
|
- | 4334 | intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 4335 | intel_crtc = encoder->new_crtc; |
|
- | 4336 | ||
- | 4337 | if (!intel_crtc) { |
|
- | 4338 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
|
- | 4339 | return; |
|
- | 4340 | } |
|
- | 4341 | ||
- | 4342 | config = &intel_crtc->config; |
|
- | 4343 | ||
- | 4344 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { |
|
- | 4345 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
|
- | 4346 | return; |
|
- | 4347 | } |
|
- | 4348 | ||
- | 4349 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) |
|
- | 4350 | index = DRRS_LOW_RR; |
|
- | 4351 | ||
- | 4352 | if (index == intel_dp->drrs_state.refresh_rate_type) { |
|
- | 4353 | DRM_DEBUG_KMS( |
|
- | 4354 | "DRRS requested for previously set RR...ignoring\n"); |
|
- | 4355 | return; |
|
- | 4356 | } |
|
- | 4357 | ||
- | 4358 | if (!intel_crtc->active) { |
|
- | 4359 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
|
- | 4360 | return; |
|
- | 4361 | } |
|
- | 4362 | ||
- | 4363 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
|
- | 4364 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
|
- | 4365 | val = I915_READ(reg); |
|
- | 4366 | if (index > DRRS_HIGH_RR) { |
|
- | 4367 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
|
- | 4368 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); |
|
- | 4369 | } else { |
|
- | 4370 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
|
- | 4371 | } |
|
- | 4372 | I915_WRITE(reg, val); |
|
- | 4373 | } |
|
- | 4374 | ||
- | 4375 | /* |
|
- | 4376 | * mutex taken to ensure that there is no race between differnt |
|
- | 4377 | * drrs calls trying to update refresh rate. This scenario may occur |
|
- | 4378 | * in future when idleness detection based DRRS in kernel and |
|
- | 4379 | * possible calls from user space to set differnt RR are made. |
|
- | 4380 | */ |
|
- | 4381 | ||
- | 4382 | mutex_lock(&intel_dp->drrs_state.mutex); |
|
- | 4383 | ||
- | 4384 | intel_dp->drrs_state.refresh_rate_type = index; |
|
- | 4385 | ||
- | 4386 | mutex_unlock(&intel_dp->drrs_state.mutex); |
|
- | 4387 | ||
- | 4388 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
|
- | 4389 | } |
|
- | 4390 | ||
- | 4391 | static struct drm_display_mode * |
|
- | 4392 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, |
|
- | 4393 | struct intel_connector *intel_connector, |
|
- | 4394 | struct drm_display_mode *fixed_mode) |
|
- | 4395 | { |
|
- | 4396 | struct drm_connector *connector = &intel_connector->base; |
|
- | 4397 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
- | 4398 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 4399 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4400 | struct drm_display_mode *downclock_mode = NULL; |
|
- | 4401 | ||
- | 4402 | if (INTEL_INFO(dev)->gen <= 6) { |
|
- | 4403 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
|
- | 4404 | return NULL; |
|
- | 4405 | } |
|
- | 4406 | ||
- | 4407 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
|
- | 4408 | DRM_INFO("VBT doesn't support DRRS\n"); |
|
- | 4409 | return NULL; |
|
- | 4410 | } |
|
- | 4411 | ||
- | 4412 | downclock_mode = intel_find_panel_downclock |
|
- | 4413 | (dev, fixed_mode, connector); |
|
- | 4414 | ||
- | 4415 | if (!downclock_mode) { |
|
- | 4416 | DRM_INFO("DRRS not supported\n"); |
|
- | 4417 | return NULL; |
|
- | 4418 | } |
|
- | 4419 | ||
- | 4420 | dev_priv->drrs.connector = intel_connector; |
|
- | 4421 | ||
- | 4422 | mutex_init(&intel_dp->drrs_state.mutex); |
|
- | 4423 | ||
- | 4424 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
|
- | 4425 | ||
- | 4426 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
|
- | 4427 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); |
|
- | 4428 | return downclock_mode; |
|
- | 4429 | } |
|
- | 4430 | ||
- | 4431 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) |
|
- | 4432 | { |
|
- | 4433 | struct drm_device *dev = intel_encoder->base.dev; |
|
- | 4434 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4435 | struct intel_dp *intel_dp; |
|
- | 4436 | enum intel_display_power_domain power_domain; |
|
- | 4437 | ||
- | 4438 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 4439 | return; |
|
- | 4440 | ||
- | 4441 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
|
- | 4442 | if (!edp_have_panel_vdd(intel_dp)) |
|
- | 4443 | return; |
|
- | 4444 | /* |
|
- | 4445 | * The VDD bit needs a power domain reference, so if the bit is |
|
- | 4446 | * already enabled when we boot or resume, grab this reference and |
|
- | 4447 | * schedule a vdd off, so we don't hold on to the reference |
|
- | 4448 | * indefinitely. |
|
- | 4449 | */ |
|
- | 4450 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
|
- | 4451 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 4452 | intel_display_power_get(dev_priv, power_domain); |
|
- | 4453 | ||
- | 4454 | edp_panel_vdd_schedule_off(intel_dp); |
|
- | 4455 | } |
|
3542 | 4456 | ||
3543 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
4457 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
- | 4458 | struct intel_connector *intel_connector, |
|
3544 | struct intel_connector *intel_connector) |
4459 | struct edp_power_seq *power_seq) |
3545 | { |
4460 | { |
3546 | struct drm_connector *connector = &intel_connector->base; |
4461 | struct drm_connector *connector = &intel_connector->base; |
- | 4462 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
3547 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4463 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3548 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4464 | struct drm_device *dev = intel_encoder->base.dev; |
3549 | struct drm_i915_private *dev_priv = dev->dev_private; |
4465 | struct drm_i915_private *dev_priv = dev->dev_private; |
3550 | struct drm_display_mode *fixed_mode = NULL; |
4466 | struct drm_display_mode *fixed_mode = NULL; |
3551 | struct edp_power_seq power_seq = { 0 }; |
4467 | struct drm_display_mode *downclock_mode = NULL; |
3552 | bool has_dpcd; |
4468 | bool has_dpcd; |
3553 | struct drm_display_mode *scan; |
4469 | struct drm_display_mode *scan; |
Line -... | Line 4470... | ||
- | 4470 | struct edid *edid; |
|
- | 4471 | ||
3554 | struct edid *edid; |
4472 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
3555 | 4473 | ||
Line 3556... | Line 4474... | ||
3556 | if (!is_edp(intel_dp)) |
4474 | if (!is_edp(intel_dp)) |
Line 3557... | Line 4475... | ||
3557 | return true; |
4475 | return true; |
3558 | 4476 | ||
3559 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
4477 | intel_edp_panel_vdd_sanitize(intel_encoder); |
3560 | 4478 | ||
Line 3561... | Line 4479... | ||
3561 | /* Cache DPCD and EDID for edp. */ |
4479 | /* Cache DPCD and EDID for edp. */ |
3562 | ironlake_edp_panel_vdd_on(intel_dp); |
4480 | intel_edp_panel_vdd_on(intel_dp); |
3563 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4481 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
3564 | ironlake_edp_panel_vdd_off(intel_dp, false); |
4482 | edp_panel_vdd_off(intel_dp, false); |
Line 3573... | Line 4491... | ||
3573 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
4491 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3574 | return false; |
4492 | return false; |
3575 | } |
4493 | } |
Line 3576... | Line 4494... | ||
3576 | 4494 | ||
3577 | /* We now know it's not a ghost, init power sequence regs. */ |
4495 | /* We now know it's not a ghost, init power sequence regs. */ |
3578 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
- | |
Line -... | Line 4496... | ||
- | 4496 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
|
3579 | &power_seq); |
4497 | |
3580 | 4498 | mutex_lock(&dev->mode_config.mutex); |
|
3581 | edid = drm_get_edid(connector, &intel_dp->adapter); |
4499 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
3582 | if (edid) { |
4500 | if (edid) { |
3583 | if (drm_add_edid_modes(connector, edid)) { |
4501 | if (drm_add_edid_modes(connector, edid)) { |
3584 | drm_mode_connector_update_edid_property(connector, |
4502 | drm_mode_connector_update_edid_property(connector, |
Line 3595... | Line 4513... | ||
3595 | 4513 | ||
3596 | /* prefer fixed mode from EDID if available */ |
4514 | /* prefer fixed mode from EDID if available */ |
3597 | list_for_each_entry(scan, &connector->probed_modes, head) { |
4515 | list_for_each_entry(scan, &connector->probed_modes, head) { |
3598 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
4516 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
- | 4517 | fixed_mode = drm_mode_duplicate(dev, scan); |
|
- | 4518 | downclock_mode = intel_dp_drrs_init( |
|
- | 4519 | intel_dig_port, |
|
3599 | fixed_mode = drm_mode_duplicate(dev, scan); |
4520 | intel_connector, fixed_mode); |
3600 | break; |
4521 | break; |
3601 | } |
4522 | } |
Line 3602... | Line 4523... | ||
3602 | } |
4523 | } |
Line 3606... | Line 4527... | ||
3606 | fixed_mode = drm_mode_duplicate(dev, |
4527 | fixed_mode = drm_mode_duplicate(dev, |
3607 | dev_priv->vbt.lfp_lvds_vbt_mode); |
4528 | dev_priv->vbt.lfp_lvds_vbt_mode); |
3608 | if (fixed_mode) |
4529 | if (fixed_mode) |
3609 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
4530 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
3610 | } |
4531 | } |
- | 4532 | mutex_unlock(&dev->mode_config.mutex); |
|
Line 3611... | Line 4533... | ||
3611 | 4533 | ||
3612 | intel_panel_init(&intel_connector->panel, fixed_mode); |
4534 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Line 3613... | Line 4535... | ||
3613 | intel_panel_setup_backlight(connector); |
4535 | intel_panel_setup_backlight(connector); |
3614 | 4536 | ||
Line 3623... | Line 4545... | ||
3623 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4545 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3624 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4546 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3625 | struct drm_device *dev = intel_encoder->base.dev; |
4547 | struct drm_device *dev = intel_encoder->base.dev; |
3626 | struct drm_i915_private *dev_priv = dev->dev_private; |
4548 | struct drm_i915_private *dev_priv = dev->dev_private; |
3627 | enum port port = intel_dig_port->port; |
4549 | enum port port = intel_dig_port->port; |
3628 | const char *name = NULL; |
4550 | struct edp_power_seq power_seq = { 0 }; |
3629 | int type, error; |
4551 | int type; |
- | 4552 | ||
- | 4553 | /* intel_dp vfuncs */ |
|
- | 4554 | if (IS_VALLEYVIEW(dev)) |
|
- | 4555 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
|
- | 4556 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
- | 4557 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
|
- | 4558 | else if (HAS_PCH_SPLIT(dev)) |
|
- | 4559 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
|
- | 4560 | else |
|
- | 4561 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
|
- | 4562 | ||
- | 4563 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
|
Line 3630... | Line 4564... | ||
3630 | 4564 | ||
3631 | /* Preserve the current hw state. */ |
4565 | /* Preserve the current hw state. */ |
3632 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
4566 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Line 3654... | Line 4588... | ||
3654 | 4588 | ||
3655 | connector->interlace_allowed = true; |
4589 | connector->interlace_allowed = true; |
Line 3656... | Line 4590... | ||
3656 | connector->doublescan_allowed = 0; |
4590 | connector->doublescan_allowed = 0; |
3657 | 4591 | ||
Line 3658... | Line 4592... | ||
3658 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4592 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
3659 | ironlake_panel_vdd_work); |
4593 | edp_panel_vdd_work); |
Line 3660... | Line 4594... | ||
3660 | 4594 | ||
3661 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
4595 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3662 | drm_sysfs_connector_add(connector); |
4596 | drm_connector_register(connector); |
3663 | 4597 | ||
- | 4598 | if (HAS_DDI(dev)) |
|
Line 3664... | Line -... | ||
3664 | if (HAS_DDI(dev)) |
- | |
3665 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
- | |
3666 | else |
- | |
3667 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
- | |
3668 | - | ||
3669 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
- | |
3670 | if (HAS_DDI(dev)) { |
- | |
3671 | switch (intel_dig_port->port) { |
- | |
3672 | case PORT_A: |
- | |
3673 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
- | |
3674 | break; |
- | |
3675 | case PORT_B: |
- | |
3676 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
- | |
3677 | break; |
- | |
3678 | case PORT_C: |
- | |
3679 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
- | |
3680 | break; |
- | |
3681 | case PORT_D: |
- | |
3682 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
- | |
3683 | break; |
- | |
3684 | default: |
4599 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3685 | BUG(); |
4600 | else |
3686 | } |
4601 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
3687 | } |
4602 | intel_connector->unregister = intel_dp_connector_unregister; |
3688 | - | ||
3689 | /* Set up the DDC bus. */ |
4603 | |
3690 | switch (port) { |
4604 | /* Set up the hotplug pin. */ |
3691 | case PORT_A: |
4605 | switch (port) { |
3692 | intel_encoder->hpd_pin = HPD_PORT_A; |
- | |
3693 | name = "DPDDC-A"; |
4606 | case PORT_A: |
3694 | break; |
4607 | intel_encoder->hpd_pin = HPD_PORT_A; |
3695 | case PORT_B: |
4608 | break; |
3696 | intel_encoder->hpd_pin = HPD_PORT_B; |
- | |
3697 | name = "DPDDC-B"; |
4609 | case PORT_B: |
3698 | break; |
4610 | intel_encoder->hpd_pin = HPD_PORT_B; |
3699 | case PORT_C: |
4611 | break; |
3700 | intel_encoder->hpd_pin = HPD_PORT_C; |
- | |
3701 | name = "DPDDC-C"; |
4612 | case PORT_C: |
3702 | break; |
4613 | intel_encoder->hpd_pin = HPD_PORT_C; |
3703 | case PORT_D: |
4614 | break; |
3704 | intel_encoder->hpd_pin = HPD_PORT_D; |
4615 | case PORT_D: |
Line 3705... | Line 4616... | ||
3705 | name = "DPDDC-D"; |
4616 | intel_encoder->hpd_pin = HPD_PORT_D; |
3706 | break; |
4617 | break; |
3707 | default: |
4618 | default: |
- | 4619 | BUG(); |
|
Line 3708... | Line 4620... | ||
3708 | BUG(); |
4620 | } |
Line -... | Line 4621... | ||
- | 4621 | ||
- | 4622 | if (is_edp(intel_dp)) { |
|
- | 4623 | intel_dp_init_panel_power_timestamps(intel_dp); |
|
- | 4624 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
|
- | 4625 | } |
|
- | 4626 | ||
- | 4627 | intel_dp_aux_init(intel_dp, intel_connector); |
|
3709 | } |
4628 | |
3710 | 4629 | /* init MST on ports that can support it */ |
|
3711 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
4630 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3712 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", |
4631 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
3713 | error, port_name(port)); |
4632 | intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); |
3714 | 4633 | } |
|
3715 | intel_dp->psr_setup_done = false; |
4634 | } |
3716 | 4635 | ||
3717 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
4636 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
3718 | i2c_del_adapter(&intel_dp->adapter); |
4637 | drm_dp_aux_unregister(&intel_dp->aux); |
3719 | if (is_edp(intel_dp)) { |
4638 | if (is_edp(intel_dp)) { |
3720 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4639 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Line 3721... | Line 4640... | ||
3721 | mutex_lock(&dev->mode_config.mutex); |
4640 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
Line 3742... | Line 4661... | ||
3742 | } |
4661 | } |
Line 3743... | Line 4662... | ||
3743 | 4662 | ||
3744 | void |
4663 | void |
3745 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
4664 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
- | 4665 | { |
|
3746 | { |
4666 | struct drm_i915_private *dev_priv = dev->dev_private; |
3747 | struct intel_digital_port *intel_dig_port; |
4667 | struct intel_digital_port *intel_dig_port; |
3748 | struct intel_encoder *intel_encoder; |
4668 | struct intel_encoder *intel_encoder; |
3749 | struct drm_encoder *encoder; |
4669 | struct drm_encoder *encoder; |
Line 3764... | Line 4684... | ||
3764 | 4684 | ||
3765 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
4685 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Line 3766... | Line 4686... | ||
3766 | DRM_MODE_ENCODER_TMDS); |
4686 | DRM_MODE_ENCODER_TMDS); |
3767 | - | ||
3768 | intel_encoder->compute_config = intel_dp_compute_config; |
4687 | |
3769 | intel_encoder->mode_set = intel_dp_mode_set; |
- | |
3770 | intel_encoder->disable = intel_disable_dp; |
4688 | intel_encoder->compute_config = intel_dp_compute_config; |
3771 | intel_encoder->post_disable = intel_post_disable_dp; |
4689 | intel_encoder->disable = intel_disable_dp; |
- | 4690 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
|
3772 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
4691 | intel_encoder->get_config = intel_dp_get_config; |
- | 4692 | intel_encoder->suspend = intel_dp_encoder_suspend; |
|
- | 4693 | if (IS_CHERRYVIEW(dev)) { |
|
- | 4694 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
|
- | 4695 | intel_encoder->pre_enable = chv_pre_enable_dp; |
|
- | 4696 | intel_encoder->enable = vlv_enable_dp; |
|
3773 | intel_encoder->get_config = intel_dp_get_config; |
4697 | intel_encoder->post_disable = chv_post_disable_dp; |
3774 | if (IS_VALLEYVIEW(dev)) { |
4698 | } else if (IS_VALLEYVIEW(dev)) { |
3775 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
4699 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
- | 4700 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
|
3776 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
4701 | intel_encoder->enable = vlv_enable_dp; |
3777 | intel_encoder->enable = vlv_enable_dp; |
4702 | intel_encoder->post_disable = vlv_post_disable_dp; |
3778 | } else { |
4703 | } else { |
- | 4704 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
|
3779 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
4705 | intel_encoder->enable = g4x_enable_dp; |
Line 3780... | Line 4706... | ||
3780 | intel_encoder->enable = g4x_enable_dp; |
4706 | intel_encoder->post_disable = g4x_post_disable_dp; |
3781 | } |
4707 | } |
Line 3782... | Line 4708... | ||
3782 | 4708 | ||
- | 4709 | intel_dig_port->port = port; |
|
- | 4710 | intel_dig_port->dp.output_reg = output_reg; |
|
- | 4711 | ||
- | 4712 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 4713 | if (IS_CHERRYVIEW(dev)) { |
|
- | 4714 | if (port == PORT_D) |
|
3783 | intel_dig_port->port = port; |
4715 | intel_encoder->crtc_mask = 1 << 2; |
- | 4716 | else |
|
3784 | intel_dig_port->dp.output_reg = output_reg; |
4717 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
3785 | 4718 | } else { |
|
Line -... | Line 4719... | ||
- | 4719 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
|
- | 4720 | } |
|
- | 4721 | intel_encoder->cloneable = 0; |
|
3786 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4722 | intel_encoder->hot_plug = intel_dp_hot_plug; |
3787 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
4723 | |
3788 | intel_encoder->cloneable = false; |
4724 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
3789 | intel_encoder->hot_plug = intel_dp_hot_plug; |
4725 | dev_priv->hpd_irq_port[port] = intel_dig_port; |
3790 | 4726 | ||
3791 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
4727 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
- | 4728 | drm_encoder_cleanup(encoder); |
|
- | 4729 | kfree(intel_dig_port); |
|
- | 4730 | kfree(intel_connector); |
|
- | 4731 | } |
|
- | 4732 | } |
|
- | 4733 | ||
- | 4734 | void intel_dp_mst_suspend(struct drm_device *dev) |
|
- | 4735 | { |
|
- | 4736 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4737 | int i; |
|
- | 4738 | ||
- | 4739 | /* disable MST */ |
|
- | 4740 | for (i = 0; i < I915_MAX_PORTS; i++) { |
|
- | 4741 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
|
- | 4742 | if (!intel_dig_port) |
|
- | 4743 | continue; |
|
- | 4744 | ||
- | 4745 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
|
- | 4746 | if (!intel_dig_port->dp.can_mst) |
|
- | 4747 | continue; |
|
- | 4748 | if (intel_dig_port->dp.is_mst) |
|
- | 4749 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
|
- | 4750 | } |
|
- | 4751 | } |
|
- | 4752 | } |
|
- | 4753 | ||
- | 4754 | void intel_dp_mst_resume(struct drm_device *dev) |
|
- | 4755 | { |
|
- | 4756 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4757 | int i; |
|
- | 4758 | ||
- | 4759 | for (i = 0; i < I915_MAX_PORTS; i++) { |
|
- | 4760 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
|
- | 4761 | if (!intel_dig_port) |
|
- | 4762 | continue; |
|
- | 4763 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
|
- | 4764 | int ret; |
|
- | 4765 | ||
- | 4766 | if (!intel_dig_port->dp.can_mst) |
|
- | 4767 | continue; |
|
- | 4768 | ||
- | 4769 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
|
- | 4770 | if (ret != 0) { |