Rev 4126 | Rev 4293 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4126 | Rev 4280 | ||
|---|---|---|---|
| Line 1388... | Line 1388... | ||
| 1388 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1388 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
| 1389 | pipe_config->port_clock = 162000; |
1389 | pipe_config->port_clock = 162000; |
| 1390 | else |
1390 | else |
| 1391 | pipe_config->port_clock = 270000; |
1391 | pipe_config->port_clock = 270000; |
| 1392 | } |
1392 | } |
| - | 1393 | ||
| - | 1394 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
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| - | 1395 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
|
| - | 1396 | /* |
|
| - | 1397 | * This is a big fat ugly hack. |
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| - | 1398 | * |
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| - | 1399 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
|
| - | 1400 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
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| - | 1401 | * unknown we fail to light up. Yet the same BIOS boots up with |
|
| - | 1402 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
|
| - | 1403 | * max, not what it tells us to use. |
|
| - | 1404 | * |
|
| - | 1405 | * Note: This will still be broken if the eDP panel is not lit |
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| - | 1406 | * up by the BIOS, and thus we can't get the mode at module |
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| - | 1407 | * load. |
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| - | 1408 | */ |
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| - | 1409 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
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| - | 1410 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
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| - | 1411 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
|
| - | 1412 | } |
|
| 1393 | } |
1413 | } |
| Line 1394... | Line 1414... | ||
| 1394 | 1414 | ||
| 1395 | static bool is_edp_psr(struct intel_dp *intel_dp) |
1415 | static bool is_edp_psr(struct intel_dp *intel_dp) |
| 1396 | { |
1416 | { |