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Line 25... Line 25...
25
 *
25
 *
26
 */
26
 */
Line 27... Line 27...
27
 
27
 
28
#include 
28
#include 
29
#include 
29
#include 
30
#include "drmP.h"
30
#include 
31
#include "drm.h"
31
#include 
32
#include "drm_crtc.h"
32
#include 
-
 
33
#include 
33
#include "drm_crtc_helper.h"
34
#include 
34
#include "intel_drv.h"
35
#include "intel_drv.h"
35
#include "i915_drm.h"
36
#include 
36
#include "i915_drv.h"
-
 
Line 37... Line 37...
37
#include "drm_dp_helper.h"
37
#include "i915_drv.h"
38
 
38
 
39
#define DP_RECEIVER_CAP_SIZE	0xf
39
#define DP_RECEIVER_CAP_SIZE	0xf
Line 40... Line -...
40
#define DP_LINK_STATUS_SIZE 6
-
 
41
#define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
-
 
42
 
-
 
43
#define DP_LINK_CONFIGURATION_SIZE  9
-
 
44
 
-
 
45
struct intel_dp {
-
 
46
    struct intel_encoder base;
-
 
47
    uint32_t output_reg;
-
 
48
    uint32_t DP;
-
 
49
    uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
-
 
50
    bool has_audio;
-
 
51
    int force_audio;
-
 
52
    uint32_t color_range;
-
 
53
    int dpms_mode;
-
 
54
    uint8_t link_bw;
-
 
55
    uint8_t lane_count;
-
 
56
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
-
 
57
    struct i2c_adapter adapter;
-
 
58
    struct i2c_algo_dp_aux_data algo;
-
 
59
    bool is_pch_edp;
-
 
60
    uint8_t train_set[4];
-
 
61
	int panel_power_up_delay;
-
 
62
	int panel_power_down_delay;
-
 
63
	int panel_power_cycle_delay;
-
 
64
	int backlight_on_delay;
-
 
65
	int backlight_off_delay;
-
 
66
	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
-
 
67
	bool want_panel_vdd;
40
#define DP_LINK_STATUS_SIZE 6
68
};
41
#define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
69
 
42
 
70
/**
43
/**
71
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
44
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
Line 148... Line 121...
148
		*link_bw = 162000;
121
		*link_bw = 162000;
149
	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
122
	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
150
		*link_bw = 270000;
123
		*link_bw = 270000;
151
}
124
}
Line -... Line 125...
-
 
125
 
-
 
126
int
-
 
127
intel_edp_target_clock(struct intel_encoder *intel_encoder,
-
 
128
		       struct drm_display_mode *mode)
-
 
129
{
-
 
130
	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
-
 
131
 
-
 
132
	if (intel_dp->panel_fixed_mode)
-
 
133
		return intel_dp->panel_fixed_mode->clock;
-
 
134
	else
-
 
135
		return mode->clock;
-
 
136
}
152
 
137
 
153
static int
138
static int
154
intel_dp_max_lane_count(struct intel_dp *intel_dp)
139
intel_dp_max_lane_count(struct intel_dp *intel_dp)
155
{
140
{
156
	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
141
	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
Line 215... Line 200...
215
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
200
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
216
{
201
{
217
	return (max_link_clock * max_lanes * 8) / 10;
202
	return (max_link_clock * max_lanes * 8) / 10;
218
}
203
}
Line -... Line 204...
-
 
204
 
-
 
205
static bool
-
 
206
intel_dp_adjust_dithering(struct intel_dp *intel_dp,
-
 
207
			  struct drm_display_mode *mode,
-
 
208
			  bool adjust_mode)
-
 
209
{
-
 
210
	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
-
 
211
	int max_lanes = intel_dp_max_lane_count(intel_dp);
-
 
212
	int max_rate, mode_rate;
-
 
213
 
-
 
214
	mode_rate = intel_dp_link_required(mode->clock, 24);
-
 
215
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
-
 
216
 
-
 
217
	if (mode_rate > max_rate) {
-
 
218
		mode_rate = intel_dp_link_required(mode->clock, 18);
-
 
219
		if (mode_rate > max_rate)
-
 
220
			return false;
-
 
221
 
-
 
222
		if (adjust_mode)
-
 
223
			mode->private_flags
-
 
224
				|= INTEL_MODE_DP_FORCE_6BPC;
-
 
225
 
-
 
226
		return true;
-
 
227
	}
-
 
228
 
-
 
229
	return true;
-
 
230
}
219
 
231
 
220
static int
232
static int
221
intel_dp_mode_valid(struct drm_connector *connector,
233
intel_dp_mode_valid(struct drm_connector *connector,
222
		    struct drm_display_mode *mode)
234
		    struct drm_display_mode *mode)
223
{
235
{
224
	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
 
225
	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
-
 
226
	int max_lanes = intel_dp_max_lane_count(intel_dp);
-
 
Line 227... Line 236...
227
	int max_rate, mode_rate;
236
	struct intel_dp *intel_dp = intel_attached_dp(connector);
228
 
237
 
229
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
238
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
Line 230... Line 239...
230
		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
239
		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
231
			return MODE_PANEL;
240
			return MODE_PANEL;
232
 
241
 
Line 233... Line -...
233
		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
-
 
234
			return MODE_PANEL;
242
		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
235
	}
-
 
236
 
-
 
237
	mode_rate = intel_dp_link_required(mode->clock, 24);
-
 
238
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
-
 
239
 
243
			return MODE_PANEL;
240
	if (mode_rate > max_rate) {
-
 
241
			mode_rate = intel_dp_link_required(mode->clock, 18);
-
 
242
			if (mode_rate > max_rate)
-
 
Line 243... Line 244...
243
		return MODE_CLOCK_HIGH;
244
	}
244
			else
245
 
Line -... Line 246...
-
 
246
	if (!intel_dp_adjust_dithering(intel_dp, mode, false))
-
 
247
		return MODE_CLOCK_HIGH;
-
 
248
 
245
				mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
249
	if (mode->clock < 10000)
246
	}
250
		return MODE_CLOCK_LOW;
Line 247... Line 251...
247
 
251
 
248
	if (mode->clock < 10000)
252
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
Line 364... Line 368...
364
		if (IS_GEN6(dev) || IS_GEN7(dev))
368
		if (IS_GEN6(dev) || IS_GEN7(dev))
365
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
369
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
366
		else
370
		else
367
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
371
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
368
	} else if (HAS_PCH_SPLIT(dev))
372
	} else if (HAS_PCH_SPLIT(dev))
369
		aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
373
		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
370
	else
374
	else
371
		aux_clock_divider = intel_hrawclk(dev) / 2;
375
		aux_clock_divider = intel_hrawclk(dev) / 2;
Line 372... Line 376...
372
 
376
 
373
	if (IS_GEN6(dev))
377
	if (IS_GEN6(dev))
Line 417... Line 421...
417
		I915_WRITE(ch_ctl,
421
		I915_WRITE(ch_ctl,
418
			   status |
422
			   status |
419
			   DP_AUX_CH_CTL_DONE |
423
			   DP_AUX_CH_CTL_DONE |
420
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
424
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
421
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
425
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
-
 
426
 
-
 
427
		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
-
 
428
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
-
 
429
			continue;
422
		if (status & DP_AUX_CH_CTL_DONE)
430
		if (status & DP_AUX_CH_CTL_DONE)
423
			break;
431
			break;
424
	}
432
	}
Line 425... Line 433...
425
 
433
 
Line 647... Line 655...
647
	intel_dp->algo.running = false;
655
	intel_dp->algo.running = false;
648
	intel_dp->algo.address = 0;
656
	intel_dp->algo.address = 0;
649
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
657
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
Line 650... Line 658...
650
 
658
 
651
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
659
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
652
//	intel_dp->adapter.owner = THIS_MODULE;
660
	intel_dp->adapter.owner = THIS_MODULE;
653
	intel_dp->adapter.class = I2C_CLASS_DDC;
661
	intel_dp->adapter.class = I2C_CLASS_DDC;
654
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
662
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
655
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
663
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
656
	intel_dp->adapter.algo_data = &intel_dp->algo;
664
	intel_dp->adapter.algo_data = &intel_dp->algo;
Line 661... Line 669...
661
	ironlake_edp_panel_vdd_off(intel_dp, false);
669
	ironlake_edp_panel_vdd_off(intel_dp, false);
662
	return ret;
670
	return ret;
663
}
671
}
Line 664... Line 672...
664
 
672
 
665
static bool
673
static bool
-
 
674
intel_dp_mode_fixup(struct drm_encoder *encoder,
666
intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
675
		    const struct drm_display_mode *mode,
667
		    struct drm_display_mode *adjusted_mode)
676
		    struct drm_display_mode *adjusted_mode)
668
{
677
{
669
	struct drm_device *dev = encoder->dev;
678
	struct drm_device *dev = encoder->dev;
670
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
679
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
671
	int lane_count, clock;
680
	int lane_count, clock;
672
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
681
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
673
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
682
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
674
	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
683
	int bpp, mode_rate;
Line 675... Line 684...
675
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
684
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
676
 
685
 
677
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
686
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
678
		intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
687
		intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
679
		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
-
 
680
					mode, adjusted_mode);
-
 
681
		/*
-
 
682
		 * the mode->clock is used to calculate the Data&Link M/N
-
 
683
		 * of the pipe. For the eDP the fixed clock should be used.
-
 
684
		 */
688
		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
Line -... Line 689...
-
 
689
					mode, adjusted_mode);
-
 
690
	}
-
 
691
 
685
		mode->clock = intel_dp->panel_fixed_mode->clock;
692
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
-
 
693
		return false;
-
 
694
 
-
 
695
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
-
 
696
		      "max bw %02x pixel clock %iKHz\n",
-
 
697
		      max_lane_count, bws[max_clock], adjusted_mode->clock);
-
 
698
 
-
 
699
	if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
-
 
700
		return false;
-
 
701
 
686
	}
702
	bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
-
 
703
	mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
687
 
704
 
Line 688... Line -...
688
	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
-
 
689
		for (clock = 0; clock <= max_clock; clock++) {
705
	for (clock = 0; clock <= max_clock; clock++) {
690
			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
706
	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
691
 
707
			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
692
			if (intel_dp_link_required(mode->clock, bpp)
708
 
693
					<= link_avail) {
709
			if (mode_rate <= link_avail) {
694
				intel_dp->link_bw = bws[clock];
710
				intel_dp->link_bw = bws[clock];
695
				intel_dp->lane_count = lane_count;
711
				intel_dp->lane_count = lane_count;
696
				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
712
				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
-
 
713
				DRM_DEBUG_KMS("DP link bw %02x lane "
-
 
714
						"count %d clock %d bpp %d\n",
697
				DRM_DEBUG_KMS("Display port link bw %02x lane "
715
				       intel_dp->link_bw, intel_dp->lane_count,
698
						"count %d clock %d\n",
716
				       adjusted_mode->clock, bpp);
699
				       intel_dp->link_bw, intel_dp->lane_count,
717
				DRM_DEBUG_KMS("DP link bw required %i available %i\n",
700
				       adjusted_mode->clock);
718
					      mode_rate, link_avail);
Line 742... Line 760...
742
void
760
void
743
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
761
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
744
         struct drm_display_mode *adjusted_mode)
762
         struct drm_display_mode *adjusted_mode)
745
{
763
{
746
    struct drm_device *dev = crtc->dev;
764
    struct drm_device *dev = crtc->dev;
747
    struct drm_mode_config *mode_config = &dev->mode_config;
-
 
748
    struct drm_encoder *encoder;
765
	struct intel_encoder *encoder;
749
    struct drm_i915_private *dev_priv = dev->dev_private;
766
    struct drm_i915_private *dev_priv = dev->dev_private;
750
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
767
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
751
    int lane_count = 4;
768
    int lane_count = 4;
752
    struct intel_dp_m_n m_n;
769
    struct intel_dp_m_n m_n;
753
    int pipe = intel_crtc->pipe;
770
    int pipe = intel_crtc->pipe;
Line 754... Line 771...
754
 
771
 
755
    /*
772
    /*
756
     * Find the lane count in the intel_encoder private
773
     * Find the lane count in the intel_encoder private
757
     */
774
     */
758
    list_for_each_entry(encoder, &mode_config->encoder_list, head) {
775
	for_each_encoder_on_crtc(dev, crtc, encoder) {
Line 759... Line -...
759
        struct intel_dp *intel_dp;
-
 
760
 
-
 
761
        if (encoder->crtc != crtc)
-
 
762
            continue;
-
 
763
 
776
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
764
        intel_dp = enc_to_intel_dp(encoder);
777
 
765
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
778
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
766
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
779
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
767
		{
780
		{
Line 793... Line 806...
793
        I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
806
        I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
794
        I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
807
        I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
795
    }
808
    }
796
}
809
}
Line 797... Line -...
797
 
-
 
798
static void ironlake_edp_pll_on(struct drm_encoder *encoder);
-
 
799
static void ironlake_edp_pll_off(struct drm_encoder *encoder);
-
 
800
 
810
 
801
static void
811
static void
802
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
803
		  struct drm_display_mode *adjusted_mode)
813
		  struct drm_display_mode *adjusted_mode)
804
{
814
{
805
	struct drm_device *dev = encoder->dev;
815
	struct drm_device *dev = encoder->dev;
806
	struct drm_i915_private *dev_priv = dev->dev_private;
816
	struct drm_i915_private *dev_priv = dev->dev_private;
807
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
817
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
808
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
818
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
Line 809... Line -...
809
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
810
 
-
 
811
	/* Turn on the eDP PLL if needed */
-
 
812
	if (is_edp(intel_dp)) {
-
 
813
		if (!is_pch_edp(intel_dp))
-
 
814
			ironlake_edp_pll_on(encoder);
-
 
815
		else
-
 
816
			ironlake_edp_pll_off(encoder);
-
 
817
	}
819
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
818
 
820
 
819
	/*
821
	/*
820
	 * There are four kinds of DP registers:
822
	 * There are four kinds of DP registers:
821
	 *
823
	 *
Line 835... Line 837...
835
 
837
 
836
	/* Preserve the BIOS-computed detected bit. This is
838
	/* Preserve the BIOS-computed detected bit. This is
837
	 * supposed to be read-only.
839
	 * supposed to be read-only.
838
	 */
840
	 */
839
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
-
 
Line 840... Line 841...
840
	intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
841
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
841
 
-
 
842
	/* Handle DP bits in common between all three register formats */
842
 
Line 843... Line 843...
843
 
843
	/* Handle DP bits in common between all three register formats */
844
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
845
 
845
 
Line 885... Line 885...
885
			intel_dp->DP |= DP_ENHANCED_FRAMING;
885
			intel_dp->DP |= DP_ENHANCED_FRAMING;
Line 886... Line 886...
886
 
886
 
Line 887... Line 887...
887
		intel_dp->DP |= intel_crtc->pipe << 29;
887
		intel_dp->DP |= intel_crtc->pipe << 29;
888
 
-
 
889
		/* don't miss out required setting for eDP */
888
 
890
		intel_dp->DP |= DP_PLL_ENABLE;
889
		/* don't miss out required setting for eDP */
891
		if (adjusted_mode->clock < 200000)
890
		if (adjusted_mode->clock < 200000)
892
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
891
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893
		else
892
		else
Line 907... Line 906...
907
		if (intel_crtc->pipe == 1)
906
		if (intel_crtc->pipe == 1)
908
		intel_dp->DP |= DP_PIPEB_SELECT;
907
		intel_dp->DP |= DP_PIPEB_SELECT;
Line 909... Line 908...
909
 
908
 
910
		if (is_cpu_edp(intel_dp)) {
909
		if (is_cpu_edp(intel_dp)) {
911
		/* don't miss out required setting for eDP */
-
 
912
		intel_dp->DP |= DP_PLL_ENABLE;
910
		/* don't miss out required setting for eDP */
913
		if (adjusted_mode->clock < 200000)
911
		if (adjusted_mode->clock < 200000)
914
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
912
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915
		else
913
		else
916
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
914
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
Line 1114... Line 1112...
1114
	if (!is_edp(intel_dp))
1112
	if (!is_edp(intel_dp))
1115
		return;
1113
		return;
Line 1116... Line 1114...
1116
 
1114
 
Line 1117... Line 1115...
1117
	DRM_DEBUG_KMS("Turn eDP power off\n");
1115
	DRM_DEBUG_KMS("Turn eDP power off\n");
Line 1118... Line 1116...
1118
 
1116
 
-
 
1117
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
-
 
1118
 
1119
	WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1119
	pp = ironlake_get_pp_control(dev_priv);
1120
 
1120
	/* We need to switch off panel power _and_ force vdd, for otherwise some
1121
	pp = ironlake_get_pp_control(dev_priv);
1121
	 * panels get very unhappy and cease to work. */
Line -... Line 1122...
-
 
1122
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
-
 
1123
	I915_WRITE(PCH_PP_CONTROL, pp);
1122
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1124
	POSTING_READ(PCH_PP_CONTROL);
1123
	I915_WRITE(PCH_PP_CONTROL, pp);
1125
 
Line 1124... Line 1126...
1124
	POSTING_READ(PCH_PP_CONTROL);
1126
	intel_dp->want_panel_vdd = false;
1125
 
1127
 
Line 1164... Line 1166...
1164
	I915_WRITE(PCH_PP_CONTROL, pp);
1166
	I915_WRITE(PCH_PP_CONTROL, pp);
1165
	POSTING_READ(PCH_PP_CONTROL);
1167
	POSTING_READ(PCH_PP_CONTROL);
1166
	msleep(intel_dp->backlight_off_delay);
1168
	msleep(intel_dp->backlight_off_delay);
1167
}
1169
}
Line 1168... Line 1170...
1168
 
1170
 
1169
static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1171
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1170
{
1172
{
-
 
1173
	struct drm_device *dev = intel_dp->base.base.dev;
1171
	struct drm_device *dev = encoder->dev;
1174
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
1172
	struct drm_i915_private *dev_priv = dev->dev_private;
1175
	struct drm_i915_private *dev_priv = dev->dev_private;
Line -... Line 1176...
-
 
1176
	u32 dpa_ctl;
-
 
1177
 
-
 
1178
	assert_pipe_disabled(dev_priv,
1173
	u32 dpa_ctl;
1179
			     to_intel_crtc(crtc)->pipe);
1174
 
1180
 
-
 
1181
	DRM_DEBUG_KMS("\n");
-
 
1182
	dpa_ctl = I915_READ(DP_A);
-
 
1183
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
-
 
1184
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
-
 
1185
 
-
 
1186
	/* We don't adjust intel_dp->DP while tearing down the link, to
-
 
1187
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
1175
	DRM_DEBUG_KMS("\n");
1188
	 * enable bits here to ensure that we don't enable too much. */
1176
	dpa_ctl = I915_READ(DP_A);
1189
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1177
	dpa_ctl |= DP_PLL_ENABLE;
1190
	intel_dp->DP |= DP_PLL_ENABLE;
1178
	I915_WRITE(DP_A, dpa_ctl);
1191
	I915_WRITE(DP_A, intel_dp->DP);
1179
	POSTING_READ(DP_A);
1192
	POSTING_READ(DP_A);
Line 1180... Line 1193...
1180
	udelay(200);
1193
	udelay(200);
1181
}
1194
}
1182
 
1195
 
-
 
1196
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1183
static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1197
{
1184
{
1198
	struct drm_device *dev = intel_dp->base.base.dev;
Line -... Line 1199...
-
 
1199
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
-
 
1200
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
1201
	u32 dpa_ctl;
1185
	struct drm_device *dev = encoder->dev;
1202
 
-
 
1203
	assert_pipe_disabled(dev_priv,
-
 
1204
			     to_intel_crtc(crtc)->pipe);
-
 
1205
 
-
 
1206
	dpa_ctl = I915_READ(DP_A);
-
 
1207
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
-
 
1208
	     "dp pll off, should be on\n");
-
 
1209
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1186
	struct drm_i915_private *dev_priv = dev->dev_private;
1210
 
1187
	u32 dpa_ctl;
1211
	/* We can't rely on the value tracked for the DP register in
1188
 
1212
	 * intel_dp->DP because link_down must not change that (otherwise link
1189
	dpa_ctl = I915_READ(DP_A);
1213
	 * re-training will fail. */
1190
	dpa_ctl &= ~DP_PLL_ENABLE;
1214
	dpa_ctl &= ~DP_PLL_ENABLE;
Line 1221... Line 1245...
1221
			msleep(1);
1245
			msleep(1);
1222
		}
1246
		}
1223
	}
1247
	}
1224
}
1248
}
Line 1225... Line 1249...
1225
 
1249
 
-
 
1250
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1226
static void intel_dp_prepare(struct drm_encoder *encoder)
1251
				  enum pipe *pipe)
1227
{
1252
{
-
 
1253
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-
 
1254
	struct drm_device *dev = encoder->base.dev;
-
 
1255
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 1228... Line 1256...
1228
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1256
	u32 tmp = I915_READ(intel_dp->output_reg);
1229
 
1257
 
Line 1230... Line 1258...
1230
	ironlake_edp_backlight_off(intel_dp);
1258
	if (!(tmp & DP_PORT_EN))
1231
	ironlake_edp_panel_off(intel_dp);
1259
		return false;
1232
 
1260
 
1233
	/* Wake up the sink first */
1261
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
-
 
1262
		*pipe = PORT_TO_PIPE_CPT(tmp);
1234
	ironlake_edp_panel_vdd_on(intel_dp);
1263
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
-
 
1264
		*pipe = PORT_TO_PIPE(tmp);
-
 
1265
	} else {
Line 1235... Line 1266...
1235
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1266
		u32 trans_sel;
1236
	intel_dp_link_down(intel_dp);
1267
		u32 trans_dp;
-
 
1268
		int i;
-
 
1269
 
-
 
1270
		switch (intel_dp->output_reg) {
-
 
1271
		case PCH_DP_B:
-
 
1272
			trans_sel = TRANS_DP_PORT_SEL_B;
-
 
1273
			break;
-
 
1274
		case PCH_DP_C:
-
 
1275
			trans_sel = TRANS_DP_PORT_SEL_C;
-
 
1276
			break;
-
 
1277
		case PCH_DP_D:
-
 
1278
			trans_sel = TRANS_DP_PORT_SEL_D;
-
 
1279
			break;
-
 
1280
		default:
-
 
1281
			return true;
-
 
1282
		}
-
 
1283
 
-
 
1284
		for_each_pipe(i) {
1237
	ironlake_edp_panel_vdd_off(intel_dp, false);
1285
			trans_dp = I915_READ(TRANS_DP_CTL(i));
-
 
1286
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
-
 
1287
				*pipe = i;
-
 
1288
				return true;
-
 
1289
			}
-
 
1290
		}
-
 
1291
	}
1238
 
1292
 
Line 1239... Line 1293...
1239
	/* Make sure the panel is off before trying to
1293
	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1240
	 * change the mode
1294
 
1241
	 */
1295
	return true;
1242
}
-
 
1243
 
-
 
Line -... Line 1296...
-
 
1296
}
-
 
1297
 
1244
static void intel_dp_commit(struct drm_encoder *encoder)
1298
static void intel_disable_dp(struct intel_encoder *encoder)
-
 
1299
{
1245
{
1300
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1246
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
 
1247
	struct drm_device *dev = encoder->dev;
1301
 
1248
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
-
 
1249
 
-
 
1250
		ironlake_edp_panel_vdd_on(intel_dp);
-
 
Line -... Line 1302...
-
 
1302
	/* Make sure the panel is off before trying to change the mode. But also
-
 
1303
	 * ensure that we have vdd while we switch off the panel. */
1251
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1304
		ironlake_edp_panel_vdd_on(intel_dp);
-
 
1305
	ironlake_edp_backlight_off(intel_dp);
-
 
1306
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-
 
1307
	ironlake_edp_panel_off(intel_dp);
-
 
1308
 
-
 
1309
	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
Line 1252... Line 1310...
1252
	intel_dp_start_link_train(intel_dp);
1310
	if (!is_cpu_edp(intel_dp))
1253
		ironlake_edp_panel_on(intel_dp);
1311
		intel_dp_link_down(intel_dp);
-
 
1312
}
-
 
1313
 
1254
	ironlake_edp_panel_vdd_off(intel_dp, true);
1314
static void intel_post_disable_dp(struct intel_encoder *encoder)
Line 1255... Line -...
1255
	intel_dp_complete_link_train(intel_dp);
-
 
1256
	ironlake_edp_backlight_on(intel_dp);
1315
{
1257
 
1316
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1258
	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1317
 
1259
 
1318
	if (is_cpu_edp(intel_dp)) {
1260
	if (HAS_PCH_CPT(dev))
1319
		intel_dp_link_down(intel_dp);
1261
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1320
		ironlake_edp_pll_off(intel_dp);
Line 1262... Line 1321...
1262
}
1321
	}
1263
 
-
 
1264
static void
-
 
1265
intel_dp_dpms(struct drm_encoder *encoder, int mode)
-
 
1266
{
-
 
1267
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
 
1268
	struct drm_device *dev = encoder->dev;
-
 
1269
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
1270
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
-
 
1271
 
-
 
1272
	if (mode != DRM_MODE_DPMS_ON) {
-
 
1273
		ironlake_edp_backlight_off(intel_dp);
1322
}
1274
		ironlake_edp_panel_off(intel_dp);
-
 
1275
 
-
 
Line 1276... Line 1323...
1276
		ironlake_edp_panel_vdd_on(intel_dp);
1323
 
1277
		intel_dp_sink_dpms(intel_dp, mode);
1324
static void intel_enable_dp(struct intel_encoder *encoder)
1278
		intel_dp_link_down(intel_dp);
-
 
1279
		ironlake_edp_panel_vdd_off(intel_dp, false);
1325
{
1280
 
1326
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1281
		if (is_cpu_edp(intel_dp))
1327
	struct drm_device *dev = encoder->base.dev;
1282
			ironlake_edp_pll_off(encoder);
1328
	struct drm_i915_private *dev_priv = dev->dev_private;
1283
	} else {
-
 
1284
		if (is_cpu_edp(intel_dp))
-
 
1285
			ironlake_edp_pll_on(encoder);
1329
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1286
 
1330
 
-
 
1331
	if (WARN_ON(dp_reg & DP_PORT_EN))
-
 
1332
		return;
-
 
1333
 
-
 
1334
		ironlake_edp_panel_vdd_on(intel_dp);
-
 
1335
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-
 
1336
			intel_dp_start_link_train(intel_dp);
1287
			ironlake_edp_panel_vdd_on(intel_dp);
1337
				ironlake_edp_panel_on(intel_dp);
1288
		intel_dp_sink_dpms(intel_dp, mode);
1338
			ironlake_edp_panel_vdd_off(intel_dp, true);
Line 1289... Line 1339...
1289
		if (!(dp_reg & DP_PORT_EN)) {
1339
			intel_dp_complete_link_train(intel_dp);
1290
			intel_dp_start_link_train(intel_dp);
1340
		ironlake_edp_backlight_on(intel_dp);
1291
				ironlake_edp_panel_on(intel_dp);
1341
}
Line 1612... Line 1662...
1612
{
1662
{
1613
	struct drm_device *dev = intel_dp->base.base.dev;
1663
	struct drm_device *dev = intel_dp->base.base.dev;
1614
	struct drm_i915_private *dev_priv = dev->dev_private;
1664
	struct drm_i915_private *dev_priv = dev->dev_private;
1615
	int ret;
1665
	int ret;
Line -... Line 1666...
-
 
1666
 
-
 
1667
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
-
 
1668
		dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
-
 
1669
 
-
 
1670
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
-
 
1671
		case DP_TRAINING_PATTERN_DISABLE:
-
 
1672
			dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
-
 
1673
			break;
-
 
1674
		case DP_TRAINING_PATTERN_1:
-
 
1675
			dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
-
 
1676
			break;
-
 
1677
		case DP_TRAINING_PATTERN_2:
-
 
1678
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
-
 
1679
			break;
-
 
1680
		case DP_TRAINING_PATTERN_3:
-
 
1681
			DRM_ERROR("DP training pattern 3 not supported\n");
-
 
1682
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
-
 
1683
			break;
-
 
1684
		}
-
 
1685
 
-
 
1686
	} else {
-
 
1687
		dp_reg_value &= ~DP_LINK_TRAIN_MASK;
-
 
1688
 
-
 
1689
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
-
 
1690
		case DP_TRAINING_PATTERN_DISABLE:
-
 
1691
			dp_reg_value |= DP_LINK_TRAIN_OFF;
-
 
1692
			break;
-
 
1693
		case DP_TRAINING_PATTERN_1:
-
 
1694
			dp_reg_value |= DP_LINK_TRAIN_PAT_1;
-
 
1695
			break;
-
 
1696
		case DP_TRAINING_PATTERN_2:
-
 
1697
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
-
 
1698
			break;
-
 
1699
		case DP_TRAINING_PATTERN_3:
-
 
1700
			DRM_ERROR("DP training pattern 3 not supported\n");
-
 
1701
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
-
 
1702
			break;
-
 
1703
		}
-
 
1704
	}
1616
 
1705
 
1617
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
1706
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
Line 1618... Line 1707...
1618
	POSTING_READ(intel_dp->output_reg);
1707
	POSTING_READ(intel_dp->output_reg);
1619
 
1708
 
1620
	intel_dp_aux_native_write_1(intel_dp,
1709
	intel_dp_aux_native_write_1(intel_dp,
Line -... Line 1710...
-
 
1710
				    DP_TRAINING_PATTERN_SET,
-
 
1711
				    dp_train_pat);
1621
				    DP_TRAINING_PATTERN_SET,
1712
 
1622
				    dp_train_pat);
1713
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1623
 
1714
	    DP_TRAINING_PATTERN_DISABLE) {
1624
	ret = intel_dp_aux_native_write(intel_dp,
1715
	ret = intel_dp_aux_native_write(intel_dp,
1625
					DP_TRAINING_LANE0_SET,
1716
					DP_TRAINING_LANE0_SET,
1626
					intel_dp->train_set,
1717
					intel_dp->train_set,
-
 
1718
					intel_dp->lane_count);
Line 1627... Line 1719...
1627
					intel_dp->lane_count);
1719
	if (ret != intel_dp->lane_count)
1628
	if (ret != intel_dp->lane_count)
1720
		return false;
Line 1629... Line 1721...
1629
		return false;
1721
	}
1630
 
1722
 
1631
	return true;
1723
	return true;
1632
}
1724
}
1633
 
1725
 
1634
/* Enable corresponding port and start training pattern 1 */
-
 
1635
static void
-
 
1636
intel_dp_start_link_train(struct intel_dp *intel_dp)
1726
/* Enable corresponding port and start training pattern 1 */
1637
{
1727
static void
1638
	struct drm_device *dev = intel_dp->base.base.dev;
1728
intel_dp_start_link_train(struct intel_dp *intel_dp)
1639
	struct drm_i915_private *dev_priv = dev->dev_private;
1729
{
1640
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
-
 
1641
	int i;
1730
	struct drm_device *dev = intel_dp->base.base.dev;
Line 1642... Line -...
1642
	uint8_t voltage;
-
 
1643
	bool clock_recovery = false;
-
 
1644
	int voltage_tries, loop_tries;
-
 
1645
	u32 reg;
-
 
1646
	uint32_t DP = intel_dp->DP;
-
 
1647
 
-
 
1648
	/*
-
 
1649
	 * On CPT we have to enable the port in training pattern 1, which
-
 
1650
	 * will happen below in intel_dp_set_link_train.  Otherwise, enable
-
 
1651
	 * the port and wait for it to become active.
-
 
1652
	 */
-
 
1653
	if (!HAS_PCH_CPT(dev)) {
1731
	int i;
1654
		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1732
	uint8_t voltage;
1655
		POSTING_READ(intel_dp->output_reg);
1733
	bool clock_recovery = false;
1656
		intel_wait_for_vblank(dev, intel_crtc->pipe);
1734
	int voltage_tries, loop_tries;
Line 1657... Line 1735...
1657
	}
1735
	uint32_t DP = intel_dp->DP;
Line 1658... Line -...
1658
 
-
 
1659
	/* Write the link configuration data */
-
 
1660
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
-
 
1661
				  intel_dp->link_configuration,
-
 
1662
				  DP_LINK_CONFIGURATION_SIZE);
1736
 
1663
 
1737
	/* Write the link configuration data */
1664
	DP |= DP_PORT_EN;
1738
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1665
 
1739
				  intel_dp->link_configuration,
1666
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1740
				  DP_LINK_CONFIGURATION_SIZE);
Line 1688... Line 1762...
1688
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1762
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1689
			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1763
			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1690
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1764
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1691
		}
1765
		}
Line 1692... Line -...
1692
 
-
 
1693
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
-
 
1694
			reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
-
 
1695
		else
-
 
1696
			reg = DP | DP_LINK_TRAIN_PAT_1;
-
 
1697
 
1766
 
1698
		if (!intel_dp_set_link_train(intel_dp, reg,
1767
		if (!intel_dp_set_link_train(intel_dp, DP,
1699
					     DP_TRAINING_PATTERN_1 |
1768
					     DP_TRAINING_PATTERN_1 |
1700
					     DP_LINK_SCRAMBLING_DISABLE))
1769
					     DP_LINK_SCRAMBLING_DISABLE))
1701
			break;
1770
			break;
Line 1715... Line 1784...
1715
 
1784
 
1716
		/* Check to see if we've tried the max voltage */
1785
		/* Check to see if we've tried the max voltage */
1717
		for (i = 0; i < intel_dp->lane_count; i++)
1786
		for (i = 0; i < intel_dp->lane_count; i++)
1718
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1787
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1719
				break;
1788
				break;
1720
		if (i == intel_dp->lane_count) {
1789
		if (i == intel_dp->lane_count && voltage_tries == 5) {
1721
			++loop_tries;
1790
			++loop_tries;
1722
			if (loop_tries == 5) {
1791
			if (loop_tries == 5) {
1723
				DRM_DEBUG_KMS("too many full retries, give up\n");
1792
				DRM_DEBUG_KMS("too many full retries, give up\n");
1724
			break;
1793
			break;
Line 1748... Line 1817...
1748
 
1817
 
1749
static void
1818
static void
1750
intel_dp_complete_link_train(struct intel_dp *intel_dp)
1819
intel_dp_complete_link_train(struct intel_dp *intel_dp)
1751
{
1820
{
1752
	struct drm_device *dev = intel_dp->base.base.dev;
-
 
1753
	struct drm_i915_private *dev_priv = dev->dev_private;
1821
	struct drm_device *dev = intel_dp->base.base.dev;
1754
	bool channel_eq = false;
1822
	bool channel_eq = false;
1755
	int tries, cr_tries;
-
 
1756
	u32 reg;
1823
	int tries, cr_tries;
Line 1757... Line 1824...
1757
	uint32_t DP = intel_dp->DP;
1824
	uint32_t DP = intel_dp->DP;
1758
 
1825
 
1759
	/* channel equalization */
1826
	/* channel equalization */
Line 1780... Line 1847...
1780
		} else {
1847
		} else {
1781
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1848
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1782
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1849
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1783
		}
1850
		}
Line 1784... Line -...
1784
 
-
 
1785
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
-
 
1786
			reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
-
 
1787
		else
-
 
1788
			reg = DP | DP_LINK_TRAIN_PAT_2;
-
 
1789
 
1851
 
1790
		/* channel eq pattern */
1852
		/* channel eq pattern */
1791
		if (!intel_dp_set_link_train(intel_dp, reg,
1853
		if (!intel_dp_set_link_train(intel_dp, DP,
1792
					     DP_TRAINING_PATTERN_2 |
1854
					     DP_TRAINING_PATTERN_2 |
1793
					     DP_LINK_SCRAMBLING_DISABLE))
1855
					     DP_LINK_SCRAMBLING_DISABLE))
Line 1794... Line 1856...
1794
			break;
1856
			break;
Line 1821... Line 1883...
1821
		/* Compute new intel_dp->train_set as requested by target */
1883
		/* Compute new intel_dp->train_set as requested by target */
1822
		intel_get_adjust_train(intel_dp, link_status);
1884
		intel_get_adjust_train(intel_dp, link_status);
1823
		++tries;
1885
		++tries;
1824
	}
1886
	}
Line 1825... Line -...
1825
 
-
 
1826
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
-
 
1827
		reg = DP | DP_LINK_TRAIN_OFF_CPT;
-
 
1828
	else
-
 
1829
		reg = DP | DP_LINK_TRAIN_OFF;
-
 
1830
 
-
 
1831
	I915_WRITE(intel_dp->output_reg, reg);
-
 
1832
	POSTING_READ(intel_dp->output_reg);
-
 
1833
	intel_dp_aux_native_write_1(intel_dp,
1887
 
1834
				    DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1888
	intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
Line 1835... Line 1889...
1835
}
1889
}
1836
 
1890
 
1837
static void
1891
static void
1838
intel_dp_link_down(struct intel_dp *intel_dp)
1892
intel_dp_link_down(struct intel_dp *intel_dp)
1839
{
1893
{
1840
	struct drm_device *dev = intel_dp->base.base.dev;
1894
	struct drm_device *dev = intel_dp->base.base.dev;
Line 1841... Line 1895...
1841
	struct drm_i915_private *dev_priv = dev->dev_private;
1895
	struct drm_i915_private *dev_priv = dev->dev_private;
1842
	uint32_t DP = intel_dp->DP;
1896
	uint32_t DP = intel_dp->DP;
Line 1843... Line 1897...
1843
 
1897
 
Line 1844... Line -...
1844
	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
-
 
1845
		return;
-
 
1846
 
-
 
1847
	DRM_DEBUG_KMS("\n");
-
 
1848
 
-
 
1849
	if (is_edp(intel_dp)) {
-
 
1850
		DP &= ~DP_PLL_ENABLE;
-
 
1851
		I915_WRITE(intel_dp->output_reg, DP);
1898
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1852
		POSTING_READ(intel_dp->output_reg);
1899
		return;
1853
		udelay(100);
1900
 
1854
	}
1901
	DRM_DEBUG_KMS("\n");
1855
 
1902
 
Line 1862... Line 1909...
1862
	}
1909
	}
1863
	POSTING_READ(intel_dp->output_reg);
1910
	POSTING_READ(intel_dp->output_reg);
Line 1864... Line 1911...
1864
 
1911
 
Line 1865... Line -...
1865
	msleep(17);
-
 
1866
 
-
 
1867
	if (is_edp(intel_dp)) {
-
 
1868
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
-
 
1869
			DP |= DP_LINK_TRAIN_OFF_CPT;
-
 
1870
		else
-
 
1871
		DP |= DP_LINK_TRAIN_OFF;
-
 
1872
	}
1912
	msleep(17);
1873
 
1913
 
1874
	if (!HAS_PCH_CPT(dev) &&
1914
	if (HAS_PCH_IBX(dev) &&
Line 1875... Line 1915...
1875
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1915
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1876
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
1916
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
Line 1912... Line 1952...
1912
 
1952
 
1913
static bool
1953
static bool
1914
intel_dp_get_dpcd(struct intel_dp *intel_dp)
1954
intel_dp_get_dpcd(struct intel_dp *intel_dp)
1915
{
1955
{
1916
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1956
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
-
 
1957
					   sizeof(intel_dp->dpcd)) == 0)
-
 
1958
		return false; /* aux transfer failed */
1917
					   sizeof(intel_dp->dpcd)) &&
1959
 
-
 
1960
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
-
 
1961
		return false; /* DPCD not present */
-
 
1962
 
-
 
1963
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
-
 
1964
	      DP_DWN_STRM_PORT_PRESENT))
-
 
1965
		return true; /* native DP sink */
-
 
1966
 
-
 
1967
	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
-
 
1968
		return true; /* no per-port downstream info */
-
 
1969
 
-
 
1970
	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
-
 
1971
					   intel_dp->downstream_ports,
-
 
1972
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
-
 
1973
		return false; /* downstream port status fetch failed */
1918
	    (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1974
 
1919
		return true;
1975
		return true;
Line -... Line 1976...
-
 
1976
}
-
 
1977
 
-
 
1978
static void
-
 
1979
intel_dp_probe_oui(struct intel_dp *intel_dp)
-
 
1980
{
-
 
1981
	u8 buf[3];
1920
	}
1982
 
-
 
1983
	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
-
 
1984
		return;
-
 
1985
 
-
 
1986
	ironlake_edp_panel_vdd_on(intel_dp);
-
 
1987
 
-
 
1988
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
-
 
1989
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
-
 
1990
			      buf[0], buf[1], buf[2]);
-
 
1991
 
-
 
1992
	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
-
 
1993
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
-
 
1994
			      buf[0], buf[1], buf[2]);
1921
 
1995
 
Line 1922... Line 1996...
1922
	return false;
1996
	ironlake_edp_panel_vdd_off(intel_dp, false);
1923
}
1997
}
1924
 
1998
 
Line 1956... Line 2030...
1956
intel_dp_check_link_status(struct intel_dp *intel_dp)
2030
intel_dp_check_link_status(struct intel_dp *intel_dp)
1957
{
2031
{
1958
	u8 sink_irq_vector;
2032
	u8 sink_irq_vector;
1959
	u8 link_status[DP_LINK_STATUS_SIZE];
2033
	u8 link_status[DP_LINK_STATUS_SIZE];
Line 1960... Line 2034...
1960
 
2034
 
1961
	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2035
	if (!intel_dp->base.connectors_active)
Line 1962... Line 2036...
1962
		return;
2036
		return;
1963
 
2037
 
Line 1964... Line 2038...
1964
	if (!intel_dp->base.base.crtc)
2038
	if (WARN_ON(!intel_dp->base.base.crtc))
1965
		return;
2039
		return;
1966
 
2040
 
Line 1996... Line 2070...
1996
		intel_dp_start_link_train(intel_dp);
2070
		intel_dp_start_link_train(intel_dp);
1997
		intel_dp_complete_link_train(intel_dp);
2071
		intel_dp_complete_link_train(intel_dp);
1998
	}
2072
	}
1999
}
2073
}
Line -... Line 2074...
-
 
2074
 
2000
 
2075
/* XXX this is probably wrong for multiple downstream ports */
2001
static enum drm_connector_status
2076
static enum drm_connector_status
2002
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2077
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
-
 
2078
{
-
 
2079
	uint8_t *dpcd = intel_dp->dpcd;
-
 
2080
	bool hpd;
-
 
2081
	uint8_t type;
2003
{
2082
 
-
 
2083
	if (!intel_dp_get_dpcd(intel_dp))
-
 
2084
		return connector_status_disconnected;
-
 
2085
 
-
 
2086
	/* if there's no downstream port, we're done */
-
 
2087
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
-
 
2088
		return connector_status_connected;
-
 
2089
 
-
 
2090
	/* If we're HPD-aware, SINK_COUNT changes dynamically */
-
 
2091
	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
-
 
2092
	if (hpd) {
-
 
2093
		uint8_t reg;
-
 
2094
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
-
 
2095
						    ®, 1))
-
 
2096
			return connector_status_unknown;
-
 
2097
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
-
 
2098
					      : connector_status_disconnected;
-
 
2099
	}
-
 
2100
 
-
 
2101
	/* If no HPD, poke DDC gently */
2004
	if (intel_dp_get_dpcd(intel_dp))
2102
	if (drm_probe_ddc(&intel_dp->adapter))
-
 
2103
		return connector_status_connected;
-
 
2104
 
-
 
2105
	/* Well we tried, say unknown for unreliable port types */
-
 
2106
	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
-
 
2107
	if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
-
 
2108
		return connector_status_unknown;
-
 
2109
 
-
 
2110
	/* Anything else is out of spec, warn and ignore */
2005
		return connector_status_connected;
2111
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2006
	return connector_status_disconnected;
2112
	return connector_status_disconnected;
Line 2007... Line 2113...
2007
}
2113
}
2008
 
2114
 
Line 2025... Line 2131...
2025
static enum drm_connector_status
2131
static enum drm_connector_status
2026
g4x_dp_detect(struct intel_dp *intel_dp)
2132
g4x_dp_detect(struct intel_dp *intel_dp)
2027
{
2133
{
2028
	struct drm_device *dev = intel_dp->base.base.dev;
2134
	struct drm_device *dev = intel_dp->base.base.dev;
2029
	struct drm_i915_private *dev_priv = dev->dev_private;
2135
	struct drm_i915_private *dev_priv = dev->dev_private;
2030
	uint32_t temp, bit;
2136
	uint32_t bit;
Line 2031... Line 2137...
2031
 
2137
 
2032
	switch (intel_dp->output_reg) {
2138
	switch (intel_dp->output_reg) {
2033
	case DP_B:
2139
	case DP_B:
2034
		bit = DPB_HOTPLUG_INT_STATUS;
2140
		bit = DPB_HOTPLUG_LIVE_STATUS;
2035
		break;
2141
		break;
2036
	case DP_C:
2142
	case DP_C:
2037
		bit = DPC_HOTPLUG_INT_STATUS;
2143
		bit = DPC_HOTPLUG_LIVE_STATUS;
2038
		break;
2144
		break;
2039
	case DP_D:
2145
	case DP_D:
2040
		bit = DPD_HOTPLUG_INT_STATUS;
2146
		bit = DPD_HOTPLUG_LIVE_STATUS;
2041
		break;
2147
		break;
2042
	default:
2148
	default:
2043
		return connector_status_unknown;
2149
		return connector_status_unknown;
Line 2044... Line 2150...
2044
	}
2150
	}
2045
 
-
 
2046
	temp = I915_READ(PORT_HOTPLUG_STAT);
-
 
2047
 
2151
 
Line 2048... Line 2152...
2048
	if ((temp & bit) == 0)
2152
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2049
		return connector_status_disconnected;
2153
		return connector_status_disconnected;
Line 2050... Line 2154...
2050
 
2154
 
2051
	return intel_dp_detect_dpcd(intel_dp);
2155
	return intel_dp_detect_dpcd(intel_dp);
2052
}
2156
}
2053
 
2157
 
2054
static struct edid *
2158
static struct edid *
-
 
2159
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
-
 
2160
{
-
 
2161
	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
 
2162
	struct edid	*edid;
-
 
2163
	int size;
-
 
2164
 
-
 
2165
	if (is_edp(intel_dp)) {
-
 
2166
		if (!intel_dp->edid)
-
 
2167
			return NULL;
-
 
2168
 
-
 
2169
		size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
-
 
2170
		edid = kmalloc(size, GFP_KERNEL);
-
 
2171
		if (!edid)
-
 
2172
			return NULL;
Line 2055... Line -...
2055
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
-
 
2056
{
2173
 
2057
	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
 
2058
	struct edid	*edid;
2174
		memcpy(edid, intel_dp->edid, size);
2059
 
2175
		return edid;
Line 2060... Line 2176...
2060
	ironlake_edp_panel_vdd_on(intel_dp);
2176
	}
2061
	edid = drm_get_edid(connector, adapter);
2177
 
2062
	ironlake_edp_panel_vdd_off(intel_dp, false);
2178
	edid = drm_get_edid(connector, adapter);
2063
	return edid;
2179
	return edid;
2064
}
2180
}
Line 2065... Line 2181...
2065
 
2181
 
-
 
2182
static int
-
 
2183
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
-
 
2184
{
-
 
2185
	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
 
2186
	int	ret;
-
 
2187
 
-
 
2188
	if (is_edp(intel_dp)) {
-
 
2189
		drm_mode_connector_update_edid_property(connector,
2066
static int
2190
							intel_dp->edid);
2067
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
-
 
2068
{
2191
		ret = drm_add_edid_modes(connector, intel_dp->edid);
2069
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2192
		drm_edid_to_eld(connector,
Line 2070... Line 2193...
2070
	int	ret;
2193
				intel_dp->edid);
Line 2102... Line 2225...
2102
		      intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2225
		      intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2103
		      intel_dp->dpcd[6], intel_dp->dpcd[7]);
2226
		      intel_dp->dpcd[6], intel_dp->dpcd[7]);
Line 2104... Line 2227...
2104
 
2227
 
2105
	if (status != connector_status_connected)
2228
	if (status != connector_status_connected)
-
 
2229
		return status;
-
 
2230
 
-
 
2231
	intel_dp_probe_oui(intel_dp);
2106
		return status;
2232
 
2107
/*
2233
/*
2108
	if (intel_dp->force_audio) {
2234
	if (intel_dp->force_audio) {
2109
		intel_dp->has_audio = intel_dp->force_audio > 0;
2235
		intel_dp->has_audio = intel_dp->force_audio > 0;
2110
	} else {
2236
	} else {
2111
		edid = drm_get_edid(connector, &intel_dp->adapter);
2237
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2112
		if (edid) {
2238
		if (edid) {
2113
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
-
 
2114
			connector->display_info.raw_edid = NULL;
2239
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
2115
			kfree(edid);
2240
			kfree(edid);
2116
		}
2241
		}
2117
	}
2242
	}
2118
*/
2243
*/
Line 2190... Line 2315...
2190
		if (i == intel_dp->force_audio)
2315
		if (i == intel_dp->force_audio)
2191
			return 0;
2316
			return 0;
Line 2192... Line 2317...
2192
 
2317
 
Line 2193... Line 2318...
2193
		intel_dp->force_audio = i;
2318
		intel_dp->force_audio = i;
2194
 
2319
 
2195
		if (i == 0)
2320
		if (i == HDMI_AUDIO_AUTO)
2196
			has_audio = intel_dp_detect_audio(connector);
2321
			has_audio = intel_dp_detect_audio(connector);
Line 2197... Line 2322...
2197
		else
2322
		else
2198
			has_audio = i > 0;
2323
			has_audio = (i == HDMI_AUDIO_ON);
Line 2199... Line 2324...
2199
 
2324
 
Line 2216... Line 2341...
2216
	return -EINVAL;
2341
	return -EINVAL;
Line 2217... Line 2342...
2217
 
2342
 
2218
done:
2343
done:
2219
	if (intel_dp->base.base.crtc) {
2344
	if (intel_dp->base.base.crtc) {
2220
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
2345
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
2221
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
2346
		intel_set_mode(crtc, &crtc->mode,
2222
					 crtc->x, crtc->y,
-
 
2223
					 crtc->fb);
2347
			       crtc->x, crtc->y, crtc->fb);
Line 2224... Line 2348...
2224
	}
2348
	}
2225
 
2349
 
Line 2226... Line 2350...
2226
	return 0;
2350
	return 0;
2227
}
2351
}
2228
 
2352
 
2229
static void
2353
static void
-
 
2354
intel_dp_destroy(struct drm_connector *connector)
Line 2230... Line 2355...
2230
intel_dp_destroy(struct drm_connector *connector)
2355
{
2231
{
2356
	struct drm_device *dev = connector->dev;
Line 2232... Line 2357...
2232
	struct drm_device *dev = connector->dev;
2357
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2233
 
2358
 
2234
	if (intel_dpd_is_edp(dev))
2359
	if (is_edp(intel_dp))
Line 2251... Line 2376...
2251
	}
2376
	}
2252
	kfree(intel_dp);
2377
	kfree(intel_dp);
2253
}
2378
}
Line 2254... Line 2379...
2254
 
2379
 
2255
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
-
 
2256
	.dpms = intel_dp_dpms,
2380
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2257
	.mode_fixup = intel_dp_mode_fixup,
-
 
2258
	.prepare = intel_dp_prepare,
2381
	.mode_fixup = intel_dp_mode_fixup,
2259
	.mode_set = intel_dp_mode_set,
2382
	.mode_set = intel_dp_mode_set,
2260
	.commit = intel_dp_commit,
2383
	.disable = intel_encoder_noop,
Line 2261... Line 2384...
2261
};
2384
};
2262
 
2385
 
2263
static const struct drm_connector_funcs intel_dp_connector_funcs = {
2386
static const struct drm_connector_funcs intel_dp_connector_funcs = {
2264
	.dpms = drm_helper_connector_dpms,
2387
	.dpms = intel_connector_dpms,
2265
	.detect = intel_dp_detect,
2388
	.detect = intel_dp_detect,
2266
	.fill_modes = drm_helper_probe_single_connector_modes,
2389
	.fill_modes = drm_helper_probe_single_connector_modes,
2267
	.set_property = intel_dp_set_property,
2390
	.set_property = intel_dp_set_property,
Line 2289... Line 2412...
2289
/* Return which DP Port should be selected for Transcoder DP control */
2412
/* Return which DP Port should be selected for Transcoder DP control */
2290
int
2413
int
2291
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2414
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2292
{
2415
{
2293
	struct drm_device *dev = crtc->dev;
2416
	struct drm_device *dev = crtc->dev;
2294
	struct drm_mode_config *mode_config = &dev->mode_config;
-
 
2295
	struct drm_encoder *encoder;
2417
	struct intel_encoder *encoder;
2296
 
-
 
2297
	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
-
 
2298
		struct intel_dp *intel_dp;
-
 
Line 2299... Line 2418...
2299
 
2418
 
2300
		if (encoder->crtc != crtc)
2419
	for_each_encoder_on_crtc(dev, crtc, encoder) {
Line 2301... Line -...
2301
			continue;
-
 
2302
 
2420
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2303
		intel_dp = enc_to_intel_dp(encoder);
2421
 
2304
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2422
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2305
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
2423
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
Line 2335... Line 2453...
2335
	intel_attach_force_audio_property(connector);
2453
	intel_attach_force_audio_property(connector);
2336
	intel_attach_broadcast_rgb_property(connector);
2454
	intel_attach_broadcast_rgb_property(connector);
2337
}
2455
}
Line 2338... Line 2456...
2338
 
2456
 
2339
void
2457
void
2340
intel_dp_init(struct drm_device *dev, int output_reg)
2458
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2341
{
2459
{
2342
	struct drm_i915_private *dev_priv = dev->dev_private;
2460
	struct drm_i915_private *dev_priv = dev->dev_private;
2343
	struct drm_connector *connector;
2461
	struct drm_connector *connector;
2344
	struct intel_dp *intel_dp;
2462
	struct intel_dp *intel_dp;
Line 2350... Line 2468...
2350
	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2468
	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2351
	if (!intel_dp)
2469
	if (!intel_dp)
2352
		return;
2470
		return;
Line 2353... Line 2471...
2353
 
2471
 
2354
	intel_dp->output_reg = output_reg;
2472
	intel_dp->output_reg = output_reg;
-
 
2473
	intel_dp->port = port;
-
 
2474
	/* Preserve the current hw state. */
Line 2355... Line 2475...
2355
	intel_dp->dpms_mode = -1;
2475
	intel_dp->DP = I915_READ(intel_dp->output_reg);
2356
 
2476
 
2357
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2477
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2358
	if (!intel_connector) {
2478
	if (!intel_connector) {
Line 2377... Line 2497...
2377
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2497
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2378
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2498
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
Line 2379... Line 2499...
2379
 
2499
 
Line 2380... Line -...
2380
	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
 
2381
 
-
 
2382
	if (output_reg == DP_B || output_reg == PCH_DP_B)
-
 
2383
		intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2500
	connector->polled = DRM_CONNECTOR_POLL_HPD;
2384
	else if (output_reg == DP_C || output_reg == PCH_DP_C)
-
 
2385
		intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
-
 
Line 2386... Line -...
2386
	else if (output_reg == DP_D || output_reg == PCH_DP_D)
-
 
2387
		intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
-
 
2388
 
2501
 
2389
	if (is_edp(intel_dp)) {
2502
	intel_encoder->cloneable = false;
2390
		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
-
 
Line 2391... Line 2503...
2391
//		INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2503
 
-
 
2504
//	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2392
//				  ironlake_panel_vdd_work);
2505
//			  ironlake_panel_vdd_work);
2393
	}
2506
 
Line 2394... Line 2507...
2394
 
2507
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2395
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2508
 
2396
	connector->interlace_allowed = true;
2509
	connector->interlace_allowed = true;
Line 2397... Line 2510...
2397
	connector->doublescan_allowed = 0;
2510
	connector->doublescan_allowed = 0;
2398
 
2511
 
Line -... Line 2512...
-
 
2512
	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
-
 
2513
			 DRM_MODE_ENCODER_TMDS);
-
 
2514
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
-
 
2515
 
-
 
2516
	intel_connector_attach_encoder(intel_connector, intel_encoder);
-
 
2517
	drm_sysfs_connector_add(connector);
-
 
2518
 
2399
	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2519
	intel_encoder->enable = intel_enable_dp;
2400
			 DRM_MODE_ENCODER_TMDS);
2520
	intel_encoder->pre_enable = intel_pre_enable_dp;
2401
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2521
	intel_encoder->disable = intel_disable_dp;
2402
 
2522
	intel_encoder->post_disable = intel_post_disable_dp;
2403
	intel_connector_attach_encoder(intel_connector, intel_encoder);
2523
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
2404
	drm_sysfs_connector_add(connector);
2524
	intel_connector->get_hw_state = intel_connector_get_hw_state;
2405
 
-
 
2406
	/* Set up the DDC bus. */
2525
 
2407
	switch (output_reg) {
-
 
2408
		case DP_A:
2526
	/* Set up the DDC bus. */
2409
			name = "DPDDC-A";
2527
	switch (port) {
2410
			break;
2528
	case PORT_A:
2411
		case DP_B:
-
 
2412
		case PCH_DP_B:
2529
			name = "DPDDC-A";
2413
			dev_priv->hotplug_supported_mask |=
-
 
2414
				HDMIB_HOTPLUG_INT_STATUS;
2530
			break;
2415
			name = "DPDDC-B";
2531
	case PORT_B:
2416
			break;
2532
		dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2417
		case DP_C:
-
 
2418
		case PCH_DP_C:
2533
			name = "DPDDC-B";
2419
			dev_priv->hotplug_supported_mask |=
-
 
2420
				HDMIC_HOTPLUG_INT_STATUS;
2534
			break;
2421
			name = "DPDDC-C";
2535
	case PORT_C:
-
 
2536
		dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
-
 
2537
			name = "DPDDC-C";
-
 
2538
			break;
2422
			break;
2539
	case PORT_D:
Line 2423... Line 2540...
2423
		case DP_D:
2540
		dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2424
		case PCH_DP_D:
2541
			name = "DPDDC-D";
2425
			dev_priv->hotplug_supported_mask |=
-
 
2426
				HDMID_HOTPLUG_INT_STATUS;
2542
			break;
2427
			name = "DPDDC-D";
2543
	default:
Line 2428... Line 2544...
2428
			break;
2544
		WARN(1, "Invalid port %c\n", port_name(port));
2429
	}
2545
		break;
2430
 
2546
	}
Line -... Line 2547...
-
 
2547
 
-
 
2548
	/* Cache some DPCD data in the eDP case */
-
 
2549
	if (is_edp(intel_dp)) {
-
 
2550
		struct edp_power_seq	cur, vbt;
-
 
2551
		u32 pp_on, pp_off, pp_div;
-
 
2552
 
-
 
2553
		pp_on = I915_READ(PCH_PP_ON_DELAYS);
2431
	/* Cache some DPCD data in the eDP case */
2554
		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2432
	if (is_edp(intel_dp)) {
2555
		pp_div = I915_READ(PCH_PP_DIVISOR);
2433
		bool ret;
2556
 
Line 2434... Line 2557...
2434
		struct edp_power_seq	cur, vbt;
2557
		if (!pp_on || !pp_off || !pp_div) {
Line 2474... Line 2597...
2474
			      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2597
			      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2475
			      intel_dp->panel_power_cycle_delay);
2598
			      intel_dp->panel_power_cycle_delay);
Line 2476... Line 2599...
2476
 
2599
 
2477
		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2600
		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
-
 
2601
			      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
-
 
2602
	}
-
 
2603
 
-
 
2604
	intel_dp_i2c_init(intel_dp, intel_connector, name);
-
 
2605
 
-
 
2606
	if (is_edp(intel_dp)) {
-
 
2607
		bool ret;
Line 2478... Line 2608...
2478
			      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2608
		struct edid *edid;
2479
 
2609
 
2480
		ironlake_edp_panel_vdd_on(intel_dp);
2610
		ironlake_edp_panel_vdd_on(intel_dp);
Line 2491... Line 2621...
2491
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2621
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2492
			intel_dp_encoder_destroy(&intel_dp->base.base);
2622
			intel_dp_encoder_destroy(&intel_dp->base.base);
2493
			intel_dp_destroy(&intel_connector->base);
2623
			intel_dp_destroy(&intel_connector->base);
2494
			return;
2624
			return;
2495
		}
2625
		}
2496
	}
-
 
Line -... Line 2626...
-
 
2626
 
-
 
2627
		ironlake_edp_panel_vdd_on(intel_dp);
-
 
2628
		edid = drm_get_edid(connector, &intel_dp->adapter);
-
 
2629
		if (edid) {
-
 
2630
			drm_mode_connector_update_edid_property(connector,
-
 
2631
								edid);
-
 
2632
			intel_dp->edid_mode_count =
2497
 
2633
				drm_add_edid_modes(connector, edid);
-
 
2634
			drm_edid_to_eld(connector, edid);
-
 
2635
			intel_dp->edid = edid;
-
 
2636
		}
-
 
2637
		ironlake_edp_panel_vdd_off(intel_dp, false);
Line 2498... Line 2638...
2498
	intel_dp_i2c_init(intel_dp, intel_connector, name);
2638
	}
Line 2499... Line 2639...
2499
 
2639
 
2500
	intel_encoder->hot_plug = intel_dp_hot_plug;
2640
	intel_encoder->hot_plug = intel_dp_hot_plug;