WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_dp.c

 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 #include "drm_dp_helper.h"
 #define DP_RECEIVER_CAP_SIZE	0xf
 #define DP_LINK_STATUS_SIZE 6
 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
     int force_audio;
     uint32_t color_range;
     int dpms_mode;
     uint8_t link_bw;
     uint8_t lane_count;
-    uint8_t dpcd[8];
+	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
     struct i2c_adapter adapter;
     struct i2c_algo_dp_aux_data algo;
     bool is_pch_edp;
     uint8_t train_set[4];
+	int panel_power_up_delay;
+	int panel_power_down_delay;
-    uint8_t link_status[DP_LINK_STATUS_SIZE];
+	int panel_power_cycle_delay;
+	int backlight_on_delay;
+	int backlight_off_delay;
+	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
+	bool want_panel_vdd;
 };
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 static bool is_pch_edp(struct intel_dp *intel_dp)
+{
 	return intel_dp->is_pch_edp;
+}
+/**
+ * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
+ * @intel_dp: DP struct
+ *
+ * Returns true if the given DP struct corresponds to a CPU eDP port.
+ */
+static bool is_cpu_edp(struct intel_dp *intel_dp)
+{
+	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
+}
 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
+{
 	return container_of(encoder, struct intel_dp, base.base);
+}
 static int
 intel_dp_max_lane_count(struct intel_dp *intel_dp)
-{
-	int max_lane_count = 4;
-	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+{
-		max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
+	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 		switch (max_lane_count) {
 		case 1: case 2: case 4:
 			break;
 		default:
 			max_lane_count = 4;
-		}
+		}
 	return max_lane_count;
+}
 		return 270000;
 	else
 		return 162000;
+}
+/*
+ * The units on the numbers in the next two are... bizarre.  Examples will
+ * make it clearer; this one parallels an example in the eDP spec.
+ *
+ * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
+ *
+ *     270000 * 1 * 8 / 10 == 216000
+ *
+ * The actual data capacity of that configuration is 2.16Gbit/s, so the
+ * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
+ * or equivalently, kilopixels per second - so for 1680x1050R it'd be
+ * 119000.  At 18bpp that's 2142000 kilobits per second.
+ *
+ * Thus the strange-looking division by 10 in intel_dp_link_required, to
+ * get the result in decakilobits instead of kilobits.
+ */
 /* I think this is a fiction */
 static int
-intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
+intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
+{
 	struct drm_crtc *crtc = intel_dp->base.base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int bpp = 24;
-	int bpp = 24;
+	if (check_bpp)
 		bpp = check_bpp;
-	if (intel_crtc)
+	else if (intel_crtc)
 		bpp = intel_crtc->bpp;
-	return (pixel_clock * bpp + 7) / 8;
+	return (pixel_clock * bpp + 9) / 10;
+}
 static int
 intel_dp_mode_valid(struct drm_connector *connector,
 		    struct drm_display_mode *mode)
+{
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	struct drm_device *dev = connector->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 	int max_lanes = intel_dp_max_lane_count(intel_dp);
+	int max_rate, mode_rate;
-	if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
+	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
-		if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
+		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 			return MODE_PANEL;
-		if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
+		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 			return MODE_PANEL;
 	}
+	mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
-	/* only refuse the mode on non eDP since we have seen some weird eDP panels
+	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
-	   which are outside spec tolerances but somehow work by magic */
+	if (mode_rate > max_rate) {
-	if (!is_edp(intel_dp) &&
+			mode_rate = intel_dp_link_required(intel_dp,
+							   mode->clock, 18);
+			if (mode_rate > max_rate)
+		return MODE_CLOCK_HIGH;
-	    (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
+			else
-	     > intel_dp_max_data_rate(max_link_clock, max_lanes)))
+				mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
 		return MODE_CLOCK_HIGH;
 	default:
 		return 133;
+	}
+}
+static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+}
+static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+}
+static void
+intel_dp_check_edp(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	if (!is_edp(intel_dp))
+		return;
+	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
+		WARN(1, "eDP powered off while attempting aux channel communication.\n");
+		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
+			      I915_READ(PCH_PP_STATUS),
+			      I915_READ(PCH_PP_CONTROL));
+	}
+}
 static int
 intel_dp_aux_ch(struct intel_dp *intel_dp,
 		uint8_t *send, int send_bytes,
 		uint8_t *recv, int recv_size)
 	int recv_bytes;
 	uint32_t status;
 	uint32_t aux_clock_divider;
 	int try, precharge;
 	intel_dp_check_edp(intel_dp);
 	/* The clock divider is based off the hrawclk,
 	 * and would like to run at 2MHz. So, take the
 	 * hrawclk value and divide by 2 and use that
+	 *
 	 * Note that PCH attached eDP panels should use a 125MHz input
 	 * clock divider.
 	 */
-	if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
+	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev))
+		if (IS_GEN6(dev) || IS_GEN7(dev))
-			aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
+			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 	} else if (HAS_PCH_SPLIT(dev))
 		aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 	int ret;
 	uint8_t	msg[20];
 	int msg_bytes;
 	uint8_t	ack;
 	intel_dp_check_edp(intel_dp);
 	if (send_bytes > 16)
 		return -1;
 	msg[0] = AUX_NATIVE_WRITE << 4;
 	msg[1] = address >> 8;
 	uint8_t reply[20];
 	int reply_bytes;
 	uint8_t ack;
 	int ret;
 	intel_dp_check_edp(intel_dp);
 	msg[0] = AUX_NATIVE_READ << 4;
 	msg[1] = address >> 8;
 	msg[2] = address & 0xff;
 	unsigned retry;
 	int msg_bytes;
 	int reply_bytes;
 	int ret;
 	intel_dp_check_edp(intel_dp);
 	/* Set up the command byte */
 	if (mode & MODE_I2C_READ)
 		msg[0] = AUX_I2C_READ << 4;
 	else
 	DRM_ERROR("too many retries, giving up\n");
 	return -EREMOTEIO;
+}
+static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 static int
 intel_dp_i2c_init(struct intel_dp *intel_dp,
+		  struct intel_connector *intel_connector, const char *name)
+{
-		  struct intel_connector *intel_connector, const char *name)
+	int	ret;
 	DRM_DEBUG_KMS("i2c_init %s\n", name);
 	intel_dp->algo.running = false;
-	strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
+	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 	intel_dp->adapter.algo_data = &intel_dp->algo;
 	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
+	ironlake_edp_panel_vdd_on(intel_dp);
+	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
+	ironlake_edp_panel_vdd_off(intel_dp, false);
-	return i2c_dp_aux_add_bus(&intel_dp->adapter);
+	return ret;
+}
 static bool
 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		    struct drm_display_mode *adjusted_mode)
-{
 	struct drm_device *dev = encoder->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_device *dev = encoder->dev;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	int lane_count, clock;
+	int max_lane_count = intel_dp_max_lane_count(intel_dp);
-	int max_lane_count = intel_dp_max_lane_count(intel_dp);
+	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
 	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
-	if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
+	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
-		intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
+		intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 					mode, adjusted_mode);
 		/*
 		 * the mode->clock is used to calculate the Data&Link M/N
 		 * of the pipe. For the eDP the fixed clock should be used.
 		 */
-		mode->clock = dev_priv->panel_fixed_mode->clock;
+		mode->clock = intel_dp->panel_fixed_mode->clock;
+	}
 	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 		for (clock = 0; clock <= max_clock; clock++) {
 			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
-			if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
+			if (intel_dp_link_required(intel_dp, mode->clock, bpp)
 				return true;
+			}
+		}
+	}
-	if (is_edp(intel_dp)) {
-		/* okay we failed just pick the highest */
-		intel_dp->lane_count = max_lane_count;
-		intel_dp->link_bw = bws[max_clock];
-		adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
-		DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
-			      "count %d clock %d\n",
-			      intel_dp->link_bw, intel_dp->lane_count,
-			      adjusted_mode->clock);
-		return true;
-	}
 	return false;
+}
         if (encoder->crtc != crtc)
             continue;
+        intel_dp = enc_to_intel_dp(encoder);
+		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
-        intel_dp = enc_to_intel_dp(encoder);
+		    intel_dp->base.type == INTEL_OUTPUT_EDP)
         if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
-            lane_count = intel_dp->lane_count;
-            break;
-        } else if (is_edp(intel_dp)) {
-            lane_count = dev_priv->edp.lanes;
+            lane_count = intel_dp->lane_count;
             break;
+        }
+    }
         I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
         I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
+    }
+}
+static void ironlake_edp_pll_on(struct drm_encoder *encoder);
+static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 static void
 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		  struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = encoder->dev;
-	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_crtc *crtc = intel_dp->base.base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	/* Turn on the eDP PLL if needed */
+	if (is_edp(intel_dp)) {
+		if (!is_pch_edp(intel_dp))
+			ironlake_edp_pll_on(encoder);
+		else
+			ironlake_edp_pll_off(encoder);
-	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+	}
+	/*
+	 * There are four kinds of DP registers:
+	 *
+	 * 	IBX PCH
+	 * 	SNB CPU
+	 *	IVB CPU
-	intel_dp->DP |= intel_dp->color_range;
+	 * 	CPT PCH
+	 *
+	 * IBX PCH and CPU are the same for almost everything,
+	 * except that the CPU DP PLL is configured in this
-	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+	 * register
+	 *
+	 * CPT PCH is quite different, having many bits moved
-		intel_dp->DP |= DP_SYNC_HS_HIGH;
+	 * to the TRANS_DP_CTL register instead. That
-	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+	 * configuration happens (oddly) in ironlake_pch_enable
-		intel_dp->DP |= DP_SYNC_VS_HIGH;
+	 */
+	/* Preserve the BIOS-computed detected bit. This is
+	 * supposed to be read-only.
+	 */
+	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+	intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
-		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+	/* Handle DP bits in common between all three register formats */
 	else
-		intel_dp->DP |= DP_LINK_TRAIN_OFF;
+	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 		break;
 	case 4:
 		intel_dp->DP |= DP_PORT_WIDTH_4;
 		break;
+	}
-	if (intel_dp->has_audio)
+	if (intel_dp->has_audio) {
+		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
+				 pipe_name(intel_crtc->pipe));
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
+		intel_write_eld(encoder, adjusted_mode);
+	}
 	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 	intel_dp->link_configuration[0] = intel_dp->link_bw;
 	intel_dp->link_configuration[1] = intel_dp->lane_count;
 	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 	/*
 	 * Check for DPCD version > 1.1 and enhanced framing support
 	 */
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
-		intel_dp->DP |= DP_ENHANCED_FRAMING;
+	}
+	/* Split out the IBX/CPU vs CPT settings */
+	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+			intel_dp->DP |= DP_SYNC_HS_HIGH;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+			intel_dp->DP |= DP_SYNC_VS_HIGH;
+		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+			intel_dp->DP |= DP_ENHANCED_FRAMING;
+		intel_dp->DP |= intel_crtc->pipe << 29;
+		/* don't miss out required setting for eDP */
+		intel_dp->DP |= DP_PLL_ENABLE;
+		if (adjusted_mode->clock < 200000)
+			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
+		else
+			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
+		intel_dp->DP |= intel_dp->color_range;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+			intel_dp->DP |= DP_SYNC_HS_HIGH;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+			intel_dp->DP |= DP_SYNC_VS_HIGH;
+		intel_dp->DP |= DP_LINK_TRAIN_OFF;
+		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+		intel_dp->DP |= DP_ENHANCED_FRAMING;
-	/* CPT DP's pipe select is decided in TRANS_DP_CTL */
-	if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
+		if (intel_crtc->pipe == 1)
 		intel_dp->DP |= DP_PIPEB_SELECT;
-	if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
+		if (is_cpu_edp(intel_dp)) {
 		/* don't miss out required setting for eDP */
 		intel_dp->DP |= DP_PLL_ENABLE;
 		if (adjusted_mode->clock < 200000)
 			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 		else
+			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+	}
+	} else {
+		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+	}
+}
+#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
+#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
+#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
+#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
+static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
+				       u32 mask,
+				       u32 value)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
+		      mask, value,
+		      I915_READ(PCH_PP_STATUS),
+		      I915_READ(PCH_PP_CONTROL));
+	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
+			  I915_READ(PCH_PP_STATUS),
+			  I915_READ(PCH_PP_CONTROL));
+	}
+}
+static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
+{
+	DRM_DEBUG_KMS("Wait for panel power on\n");
+	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
+}
+static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+{
+	DRM_DEBUG_KMS("Wait for panel power off time\n");
+	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
+}
+static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
+{
+	DRM_DEBUG_KMS("Wait for panel power cycle\n");
+	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
+}
+/* Read the current pp_control value, unlocking the register if it
+ * is locked
+ */
+static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+{
+	u32	control = I915_READ(PCH_PP_CONTROL);
+	control &= ~PANEL_UNLOCK_MASK;
-			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+	control |= PANEL_UNLOCK_REGS;
 	return control;
+}
 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp;
-	struct drm_device *dev = intel_dp->base.base.dev;
+	if (!is_edp(intel_dp))
-	struct drm_i915_private *dev_priv = dev->dev_private;
+		return;
+	DRM_DEBUG_KMS("Turn eDP VDD on\n");
-	u32 pp;
+	WARN(intel_dp->want_panel_vdd,
-	/*
+	     "eDP VDD already requested on\n");
-	 * If the panel wasn't on, make sure there's not a currently
+	intel_dp->want_panel_vdd = true;
+	if (ironlake_edp_have_panel_vdd(intel_dp)) {
+		DRM_DEBUG_KMS("eDP VDD already on\n");
+		return;
-	 * active PP sequence before enabling AUX VDD.
+	}
 	 */
-	if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
+	if (!ironlake_edp_have_panel_power(intel_dp))
-		msleep(dev_priv->panel_t3);
+		ironlake_wait_panel_power_cycle(intel_dp);
+	pp = ironlake_get_pp_control(dev_priv);
+	pp |= EDP_FORCE_VDD;
+	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
+	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
+		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+	/*
+	 * If the panel wasn't on, delay before accessing aux channel
 	 */
-	pp = I915_READ(PCH_PP_CONTROL);
+	if (!ironlake_edp_have_panel_power(intel_dp)) {
-	pp |= EDP_FORCE_VDD;
+		DRM_DEBUG_KMS("eDP was not running\n");
-	I915_WRITE(PCH_PP_CONTROL, pp);
+		msleep(intel_dp->panel_power_up_delay);
 	POSTING_READ(PCH_PP_CONTROL);
+}
+static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
-	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp;
+	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
+		pp = ironlake_get_pp_control(dev_priv);
-	u32 pp;
+	pp &= ~EDP_FORCE_VDD;
+	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
+	/* Make sure sequencer is idle before allowing subsequent activity */
+		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
+			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+		msleep(intel_dp->panel_power_down_delay);
+	}
+}
+static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+{
+	if (!is_edp(intel_dp))
+		return;
+	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
+	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
+	intel_dp->want_panel_vdd = false;
+	if (sync) {
+		ironlake_panel_vdd_off_sync(intel_dp);
+	} else {
 		/*
-	pp = I915_READ(PCH_PP_CONTROL);
-	pp &= ~EDP_FORCE_VDD;
+		 * Queue the timer to fire a long
-	I915_WRITE(PCH_PP_CONTROL, pp);
+		 * time from now (relative to the power down delay)
-	POSTING_READ(PCH_PP_CONTROL);
+		 * to keep the panel power up across a sequence of operations
 		 */
-	/* Make sure sequencer is idle before allowing subsequent activity */
+//       schedule_delayed_work(&intel_dp->panel_vdd_work,
-	msleep(dev_priv->panel_t12);
+//                     msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
-}
+	}
+}
+static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp;
+	if (!is_edp(intel_dp))
+		return;
 /* Returns true if the panel was already on when called */
-static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
+	DRM_DEBUG_KMS("Turn eDP power on\n");
-	struct drm_device *dev = intel_dp->base.base.dev;
+	if (ironlake_edp_have_panel_power(intel_dp)) {
+		DRM_DEBUG_KMS("eDP power already on\n");
+		return;
+	}
+	ironlake_wait_panel_power_cycle(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 	pp = ironlake_get_pp_control(dev_priv);
-	if (I915_READ(PCH_PP_STATUS) & PP_ON)
-		return true;
-	pp = I915_READ(PCH_PP_CONTROL);
+	if (IS_GEN5(dev)) {
+	/* ILK workaround: disable reset around power sequence */
 	pp &= ~PANEL_POWER_RESET;
-	/* ILK workaround: disable reset around power sequence */
+	I915_WRITE(PCH_PP_CONTROL, pp);
-	pp &= ~PANEL_POWER_RESET;
+	POSTING_READ(PCH_PP_CONTROL);
-	I915_WRITE(PCH_PP_CONTROL, pp);
+	}
-	POSTING_READ(PCH_PP_CONTROL);
-	pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+	pp |= POWER_TARGET_ON;
-	I915_WRITE(PCH_PP_CONTROL, pp);
+	if (!IS_GEN5(dev))
+		pp |= PANEL_POWER_RESET;
 	POSTING_READ(PCH_PP_CONTROL);
+	I915_WRITE(PCH_PP_CONTROL, pp);
-	if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
-))
+	POSTING_READ(PCH_PP_CONTROL);
-		DRM_ERROR("panel on wait timed out: 0x%08x\n",
-			  I915_READ(PCH_PP_STATUS));
+	ironlake_wait_panel_on(intel_dp);
-	pp |= PANEL_POWER_RESET; /* restore panel reset bit */
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
-	return false;
-}
-static void ironlake_edp_panel_off (struct drm_device *dev)
-{
+	if (IS_GEN5(dev)) {
+	pp |= PANEL_POWER_RESET; /* restore panel reset bit */
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	I915_WRITE(PCH_PP_CONTROL, pp);
-	u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
+	POSTING_READ(PCH_PP_CONTROL);
+	}
+}
 		PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
+static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 	pp = I915_READ(PCH_PP_CONTROL);
+	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	/* ILK workaround: disable reset around power sequence */
+	u32 pp;
+	if (!is_edp(intel_dp))
+		return;
 	pp &= ~PANEL_POWER_RESET;
-	I915_WRITE(PCH_PP_CONTROL, pp);
+	DRM_DEBUG_KMS("Turn eDP power off\n");
 	POSTING_READ(PCH_PP_CONTROL);
 	WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
 	pp &= ~POWER_TARGET_ON;
-	I915_WRITE(PCH_PP_CONTROL, pp);
+	pp = ironlake_get_pp_control(dev_priv);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+	I915_WRITE(PCH_PP_CONTROL, pp);
-	if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
+	POSTING_READ(PCH_PP_CONTROL);
 		DRM_ERROR("panel off wait timed out: 0x%08x\n",
-			  I915_READ(PCH_PP_STATUS));
+	ironlake_wait_panel_off(intel_dp);
+}
-	pp |= PANEL_POWER_RESET; /* restore panel reset bit */
+static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	I915_WRITE(PCH_PP_CONTROL, pp);
+	struct drm_device *dev = intel_dp->base.base.dev;
-	POSTING_READ(PCH_PP_CONTROL);
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	if (!is_edp(intel_dp))
+		return;
-static void ironlake_edp_backlight_on (struct drm_device *dev)
+	DRM_DEBUG_KMS("\n");
 	/*
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	 * If we enable the backlight right away following a panel power
+	 * on, we may see slight flicker as the panel syncs with the eDP
+	 * link.  So delay a bit to make sure the image is solid before
-	u32 pp;
+	 * allowing it to appear.
 	 */
-	DRM_DEBUG_KMS("\n");
+	msleep(intel_dp->backlight_on_delay);
-	/*
+	pp = ironlake_get_pp_control(dev_priv);
+}
 static void intel_dp_prepare(struct drm_encoder *encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	ironlake_edp_backlight_off(intel_dp);
-	struct drm_device *dev = encoder->dev;
+	ironlake_edp_panel_off(intel_dp);
 	/* Wake up the sink first */
-	/* Wake up the sink first */
-	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-	if (is_edp(intel_dp)) {
-		ironlake_edp_backlight_off(dev);
-		ironlake_edp_panel_off(dev);
-		if (!is_pch_edp(intel_dp))
-			ironlake_edp_pll_on(encoder);
-		else
-			ironlake_edp_pll_off(encoder);
+	ironlake_edp_panel_vdd_on(intel_dp);
+	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	intel_dp_link_down(intel_dp);
+	ironlake_edp_panel_vdd_off(intel_dp, false);
+	/* Make sure the panel is off before trying to
 	 * change the mode
-	intel_dp_link_down(intel_dp);
+	 */
+}
 static void intel_dp_commit(struct drm_encoder *encoder)
+{
-{
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	struct drm_device *dev = encoder->dev;
+	struct drm_device *dev = encoder->dev;
 	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
-	if (is_edp(intel_dp))
-		ironlake_edp_panel_vdd_on(intel_dp);
-	intel_dp_start_link_train(intel_dp);
+		ironlake_edp_panel_vdd_on(intel_dp);
-	if (is_edp(intel_dp)) {
-		ironlake_edp_panel_on(intel_dp);
+	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-		ironlake_edp_panel_vdd_off(intel_dp);
-	}
+	intel_dp_start_link_train(intel_dp);
-	intel_dp_complete_link_train(intel_dp);
+		ironlake_edp_panel_on(intel_dp);
+	ironlake_edp_panel_vdd_off(intel_dp, true);
+	intel_dp_complete_link_train(intel_dp);
+	ironlake_edp_backlight_on(intel_dp);
-	if (is_edp(intel_dp))
+	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
 		ironlake_edp_backlight_on(dev);
 	if (HAS_PCH_CPT(dev))
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
+	if (mode != DRM_MODE_DPMS_ON) {
-	if (mode != DRM_MODE_DPMS_ON) {
+		ironlake_edp_backlight_off(intel_dp);
+		ironlake_edp_panel_off(intel_dp);
-		if (is_edp(intel_dp))
-			ironlake_edp_backlight_off(dev);
+		ironlake_edp_panel_vdd_on(intel_dp);
 		intel_dp_sink_dpms(intel_dp, mode);
-		intel_dp_link_down(intel_dp);
-		if (is_edp(intel_dp))
+		intel_dp_link_down(intel_dp);
+		ironlake_edp_panel_vdd_off(intel_dp, false);
-			ironlake_edp_panel_off(dev);
-		if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
+		if (is_cpu_edp(intel_dp))
 			ironlake_edp_pll_off(encoder);
 	} else {
+		if (is_cpu_edp(intel_dp))
+			ironlake_edp_pll_on(encoder);
 		if (is_edp(intel_dp))
 			ironlake_edp_panel_vdd_on(intel_dp);
 		intel_dp_sink_dpms(intel_dp, mode);
 		if (!(dp_reg & DP_PORT_EN)) {
-			intel_dp_start_link_train(intel_dp);
-			if (is_edp(intel_dp)) {
+			intel_dp_start_link_train(intel_dp);
 				ironlake_edp_panel_on(intel_dp);
-				ironlake_edp_panel_vdd_off(intel_dp);
 			ironlake_edp_panel_vdd_off(intel_dp, true);
 			intel_dp_complete_link_train(intel_dp);
-		}
+		} else
-		if (is_edp(intel_dp))
+			ironlake_edp_panel_vdd_off(intel_dp, false);
-			ironlake_edp_backlight_on(dev);
+		ironlake_edp_backlight_on(intel_dp);
+	}
 	intel_dp->dpms_mode = mode;
+}
 /*
  * Fetch AUX CH registers 0x202 - 0x207 which contain
  * link status information
  */
 static bool
-intel_dp_get_link_status(struct intel_dp *intel_dp)
+intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
 	return intel_dp_aux_native_read_retry(intel_dp,
 					      DP_LANE0_1_STATUS,
-					      intel_dp->link_status,
+					      link_status,
 					      DP_LINK_STATUS_SIZE);
+}
 static uint8_t
+{
 	return link_status[r - DP_LANE0_1_STATUS];
+}
 static uint8_t
-intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+intel_get_adjust_request_voltage(uint8_t adjust_request[2],
 				 int lane)
-{
 	int	    i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 	int	    s = ((lane & 1) ?
 			 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 			 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
-	uint8_t l = intel_dp_link_status(link_status, i);
+	uint8_t l = adjust_request[lane>>1];
 	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 }
 static uint8_t
-intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
-				      int lane)
+intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
 				      int lane)
 	int	    i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 	int	    s = ((lane & 1) ?
 			 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 			 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 /*
  * These are source-specific values; current Intel hardware supports
  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
- */
-#define I830_DP_VOLTAGE_MAX	    DP_TRAIN_VOLTAGE_SWING_800
+ */
 static uint8_t
+intel_dp_voltage_max(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
+		return DP_TRAIN_VOLTAGE_SWING_800;
+	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
+		return DP_TRAIN_VOLTAGE_SWING_1200;
+	else
+		return DP_TRAIN_VOLTAGE_SWING_800;
+}
+static uint8_t
+intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
+{
+	struct drm_device *dev = intel_dp->base.base.dev;
+	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 	} else {
 	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 	case DP_TRAIN_VOLTAGE_SWING_400:
 		return DP_TRAIN_PRE_EMPHASIS_6;
 	case DP_TRAIN_VOLTAGE_SWING_1200:
 	default:
 		return DP_TRAIN_PRE_EMPHASIS_0;
+	}
+	}
+}
 static void
-intel_get_adjust_train(struct intel_dp *intel_dp)
+intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
 	uint8_t v = 0;
 	uint8_t p = 0;
+	int lane;
+	uint8_t	*adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
+	uint8_t voltage_max;
-	int lane;
+	uint8_t preemph_max;
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
+		uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
-		uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
+		uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
 		if (this_v > v)
 			v = this_v;
+		if (this_p > p)
-		if (this_p > p)
+			p = this_p;
-			p = this_p;
+	}
-	}
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
-	if (v >= I830_DP_VOLTAGE_MAX)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 		v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= intel_dp_pre_emphasis_max(v))
+	if (p >= preemph_max)
-		p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 	for (lane = 0; lane < 4; lane++)
 		intel_dp->train_set[lane] = v | p;
+}
 			      "0x%x\n", signal_levels);
 		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
+	}
+}
+/* Gen7's DP voltage swing and pre-emphasis control */
+static uint32_t
+intel_gen7_edp_signal_levels(uint8_t train_set)
+{
+	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	switch (signal_levels) {
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+		return EDP_LINK_TRAIN_400MV_0DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+		return EDP_LINK_TRAIN_400MV_6DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+		return EDP_LINK_TRAIN_600MV_0DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+		return EDP_LINK_TRAIN_800MV_0DB_IVB;
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
+	default:
+		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
+			      "0x%x\n", signal_levels);
+		return EDP_LINK_TRAIN_500MV_0DB_IVB;
+	}
+}
 static uint8_t
 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 		      int lane)
-{
 	int i = DP_LANE0_1_STATUS + (lane >> 1);
 	int s = (lane & 1) * 4;
-	uint8_t l = intel_dp_link_status(link_status, i);
+	uint8_t l = link_status[lane>>1];
 	return (l >> s) & 0xf;
 /* Check to see if channel eq is done on all channels */
 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 			 DP_LANE_CHANNEL_EQ_DONE|\
 			 DP_LANE_SYMBOL_LOCKED)
 static bool
-intel_channel_eq_ok(struct intel_dp *intel_dp)
+intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
 	uint8_t lane_align;
 	uint8_t lane_status;
 	int lane;
-	lane_align = intel_dp_link_status(intel_dp->link_status,
+	lane_align = intel_dp_link_status(link_status,
 					  DP_LANE_ALIGN_STATUS_UPDATED);
 	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 		return false;
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		lane_status = intel_get_lane_status(intel_dp->link_status, lane);
+		lane_status = intel_get_lane_status(link_status, lane);
 		if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 			return false;
+	}
 	return true;
 				    DP_TRAINING_PATTERN_SET,
 				    dp_train_pat);
 	ret = intel_dp_aux_native_write(intel_dp,
 					DP_TRAINING_LANE0_SET,
+					intel_dp->train_set,
-					intel_dp->train_set, 4);
+					intel_dp->lane_count);
-	if (ret != 4)
+	if (ret != intel_dp->lane_count)
 		return false;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
 	int i;
 	uint8_t voltage;
 	bool clock_recovery = false;
-	int tries;
+	int voltage_tries, loop_tries;
 	u32 reg;
 	uint32_t DP = intel_dp->DP;
 	/*
 	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
 				  intel_dp->link_configuration,
 				  DP_LINK_CONFIGURATION_SIZE);
+	DP |= DP_PORT_EN;
-	DP |= DP_PORT_EN;
-	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
+	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 	else
 		DP &= ~DP_LINK_TRAIN_MASK;
 	memset(intel_dp->train_set, 0, 4);
+	voltage = 0xff;
-	voltage = 0xff;
+	voltage_tries = 0;
-	tries = 0;
+	loop_tries = 0;
 	clock_recovery = false;
 	for (;;) {
+		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
-		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
+		uint32_t    signal_levels;
-		uint32_t    signal_levels;
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
+			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
-		if (IS_GEN6(dev) && is_edp(intel_dp)) {
+		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
 		} else {
+			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
-			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
+			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
 			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 		}
-		if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
+		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 			reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
 		else
 					     DP_LINK_SCRAMBLING_DISABLE))
 			break;
 		/* Set training pattern 1 */
 		udelay(100);
+		if (!intel_dp_get_link_status(intel_dp, link_status)) {
-		if (!intel_dp_get_link_status(intel_dp))
+			DRM_ERROR("failed to get link status\n");
+			break;
-			break;
+		}
 		if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
-		if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+			DRM_DEBUG_KMS("clock recovery OK\n");
 			clock_recovery = true;
 			break;
+		}
 		/* Check to see if we've tried the max voltage */
 		for (i = 0; i < intel_dp->lane_count; i++)
+			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+				break;
+		if (i == intel_dp->lane_count) {
-			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+			++loop_tries;
+			if (loop_tries == 5) {
+				DRM_DEBUG_KMS("too many full retries, give up\n");
+			break;
+			}
+			memset(intel_dp->train_set, 0, 4);
-				break;
+			voltage_tries = 0;
-		if (i == intel_dp->lane_count)
+			continue;
-			break;
+		}
+		/* Check to see if we've tried the same voltage 5 times */
-		/* Check to see if we've tried the same voltage 5 times */
+		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+			++voltage_tries;
-		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+			if (voltage_tries == 5) {
-			++tries;
+				DRM_DEBUG_KMS("too many voltage retries, give up\n");
-			if (tries == 5)
+				break;
 				break;
 		} else
-			tries = 0;
+			voltage_tries = 0;
 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 	cr_tries = 0;
 	channel_eq = false;
 	for (;;) {
 		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
 		uint32_t    signal_levels;
+		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
 		if (cr_tries > 5) {
 			DRM_ERROR("failed to train DP, aborting\n");
 			intel_dp_link_down(intel_dp);
 			break;
 		}
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
-		if (IS_GEN6(dev) && is_edp(intel_dp)) {
+		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
 		} else {
-			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
+			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
+		}
-		if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
+		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 			reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
 					     DP_TRAINING_PATTERN_2 |
 					     DP_LINK_SCRAMBLING_DISABLE))
 			break;
 		udelay(400);
-		if (!intel_dp_get_link_status(intel_dp))
+		if (!intel_dp_get_link_status(intel_dp, link_status))
 			break;
 		/* Make sure clock is still ok */
-		if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+		if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			cr_tries++;
 			continue;
+		}
-		if (intel_channel_eq_ok(intel_dp)) {
+		if (intel_channel_eq_ok(intel_dp, link_status)) {
 			channel_eq = true;
 			cr_tries++;
 			continue;
+		}
 		/* Compute new intel_dp->train_set as requested by target */
-		intel_get_adjust_train(intel_dp);
+		intel_get_adjust_train(intel_dp, link_status);
 		++tries;
 	}
-	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
+	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
 		reg = DP | DP_LINK_TRAIN_OFF_CPT;
 	else
 		I915_WRITE(intel_dp->output_reg, DP);
 		POSTING_READ(intel_dp->output_reg);
 		udelay(100);
+	}
-	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
+	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
 	} else {
 		DP &= ~DP_LINK_TRAIN_MASK;
 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
+	}
 	POSTING_READ(intel_dp->output_reg);
+	msleep(17);
+	if (is_edp(intel_dp)) {
-	msleep(17);
+		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
+			DP |= DP_LINK_TRAIN_OFF_CPT;
 		else
-	if (is_edp(intel_dp))
+		DP |= DP_LINK_TRAIN_OFF;
 		DP |= DP_LINK_TRAIN_OFF;
 			msleep(50);
 		} else
 			intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
+	}
 	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
 	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
+	POSTING_READ(intel_dp->output_reg);
-	POSTING_READ(intel_dp->output_reg);
+	msleep(intel_dp->panel_power_down_delay);
+}
 static bool
+	}
 	return false;
+}
+static bool
+intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
+{
+	int ret;
+	ret = intel_dp_aux_native_read_retry(intel_dp,
+					     DP_DEVICE_SERVICE_IRQ_VECTOR,
+					     sink_irq_vector, 1);
+	if (!ret)
+		return false;
+	return true;
+}
+static void
+intel_dp_handle_test_request(struct intel_dp *intel_dp)
+{
+	/* NAK by default */
+	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
+}
 /*
  * According to DP spec
  * 5.1.2:
  */
 static void
 intel_dp_check_link_status(struct intel_dp *intel_dp)
+{
+	u8 sink_irq_vector;
+	u8 link_status[DP_LINK_STATUS_SIZE];
 	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 	if (!intel_dp->base.base.crtc)
 		return;
 	/* Try to read receiver status if the link appears to be up */
-	if (!intel_dp_get_link_status(intel_dp)) {
+	if (!intel_dp_get_link_status(intel_dp, link_status)) {
 		intel_dp_link_down(intel_dp);
 		return;
+	}
 	/* Now read the DPCD to see if it's actually running */
+	if (!intel_dp_get_dpcd(intel_dp)) {
+		intel_dp_link_down(intel_dp);
+		return;
+	}
+	/* Try to read the source of the interrupt */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
+		/* Clear interrupt source */
+		intel_dp_aux_native_write_1(intel_dp,
+					    DP_DEVICE_SERVICE_IRQ_VECTOR,
+					    sink_irq_vector);
+		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
-	if (!intel_dp_get_dpcd(intel_dp)) {
+			intel_dp_handle_test_request(intel_dp);
-		intel_dp_link_down(intel_dp);
+		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
-		return;
+			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+	}
-	if (!intel_channel_eq_ok(intel_dp)) {
+	if (!intel_channel_eq_ok(intel_dp, link_status)) {
 		return connector_status_disconnected;
 	return intel_dp_detect_dpcd(intel_dp);
+}
+static struct edid *
+intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct edid	*edid;
+	ironlake_edp_panel_vdd_on(intel_dp);
+	edid = drm_get_edid(connector, adapter);
+	ironlake_edp_panel_vdd_off(intel_dp, false);
+	return edid;
+}
+static int
+intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	int	ret;
+	ironlake_edp_panel_vdd_on(intel_dp);
+	ret = intel_ddc_get_modes(connector, adapter);
+	ironlake_edp_panel_vdd_off(intel_dp, false);
+	return ret;
+}
 /**
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
+ *
 	int ret;
 	/* We should parse the EDID data and find out if it has an audio sink
 	 */
-	ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
+	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
 	if (ret) {
-		if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
+		if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
 			struct drm_display_mode *newmode;
 			list_for_each_entry(newmode, &connector->probed_modes,
 					    head) {
-				if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
+				if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
-					dev_priv->panel_fixed_mode =
+					intel_dp->panel_fixed_mode =
 						drm_mode_duplicate(dev, newmode);
 					break;
+				}
-			}
+			}
+		}
 		return ret;
+	}
+	/* if eDP has no EDID, try to use fixed panel mode from VBT */
+	if (is_edp(intel_dp)) {
+		/* initialize panel mode from VBT if available for eDP */
+		if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
+			intel_dp->panel_fixed_mode =
+				drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
+			if (intel_dp->panel_fixed_mode) {
+				intel_dp->panel_fixed_mode->type |=
+					DRM_MODE_TYPE_PREFERRED;
 	/* if eDP has no EDID, try to use fixed panel mode from VBT */
-	if (is_edp(intel_dp)) {
+		}
-		if (dev_priv->panel_fixed_mode != NULL) {
+		if (intel_dp->panel_fixed_mode) {
 			struct drm_display_mode *mode;
-			mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
+			mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
 			drm_mode_probed_add(connector, mode);
 			return 1;
+{
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 //   i2c_del_adapter(&intel_dp->adapter);
+	drm_encoder_cleanup(encoder);
+	if (is_edp(intel_dp)) {
+//		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+		ironlake_panel_vdd_off_sync(intel_dp);
 	drm_encoder_cleanup(encoder);
 	kfree(intel_dp);
+}
 		if (encoder->crtc != crtc)
 			continue;
+		intel_dp = enc_to_intel_dp(encoder);
-		intel_dp = enc_to_intel_dp(encoder);
+		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
-		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
+		    intel_dp->base.type == INTEL_OUTPUT_EDP)
 			return intel_dp->output_reg;
+	}
 	else if (output_reg == DP_C || output_reg == PCH_DP_C)
 		intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
 	else if (output_reg == DP_D || output_reg == PCH_DP_D)
 		intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
-	if (is_edp(intel_dp))
+	if (is_edp(intel_dp)) {
+		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
+//		INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
+//				  ironlake_panel_vdd_work);
-		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
+	}
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;
 				HDMID_HOTPLUG_INT_STATUS;
 			name = "DPDDC-D";
 			break;
+	}
-	intel_dp_i2c_init(intel_dp, intel_connector, name);
 	/* Cache some DPCD data in the eDP case */
 	if (is_edp(intel_dp)) {
+		bool ret;
-		bool ret;
+		struct edp_power_seq	cur, vbt;
-		u32 pp_on, pp_div;
+		u32 pp_on, pp_off, pp_div;
 		pp_on = I915_READ(PCH_PP_ON_DELAYS);
-		pp_on = I915_READ(PCH_PP_ON_DELAYS);
+		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
+		pp_div = I915_READ(PCH_PP_DIVISOR);
+		/* Pull timing values out of registers */
+		cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
+			PANEL_POWER_UP_DELAY_SHIFT;
+		cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
+			PANEL_LIGHT_ON_DELAY_SHIFT;
+		cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
+			PANEL_LIGHT_OFF_DELAY_SHIFT;
+		cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
+			PANEL_POWER_DOWN_DELAY_SHIFT;
+		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+			       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
+		DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+			      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+		vbt = dev_priv->edp.pps;
+		DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+			      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
-		pp_div = I915_READ(PCH_PP_DIVISOR);
+#define get_delay(field)	((max(cur.field, vbt.field) + 9) / 10)
+		intel_dp->panel_power_up_delay = get_delay(t1_t3);
+		intel_dp->backlight_on_delay = get_delay(t8);
+		intel_dp->backlight_off_delay = get_delay(t9);
+		intel_dp->panel_power_down_delay = get_delay(t10);
+		intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
-		/* Get T3 & T12 values (note: VESA not bspec terminology) */
+		DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
-		dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
+			      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
+			      intel_dp->panel_power_cycle_delay);
 		dev_priv->panel_t3 /= 10; /* t3 in 100us units */
-		dev_priv->panel_t12 = pp_div & 0xf;
+		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
-		dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
+			      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
 		ironlake_edp_panel_vdd_on(intel_dp);
-		ironlake_edp_panel_vdd_on(intel_dp);
+		ret = intel_dp_get_dpcd(intel_dp);
-		ret = intel_dp_get_dpcd(intel_dp);
+		ironlake_edp_panel_vdd_off(intel_dp, false);
 		ironlake_edp_panel_vdd_off(intel_dp);
 		if (ret) {
 			intel_dp_destroy(&intel_connector->base);
 			return;
+		}
+	}
+	intel_dp_i2c_init(intel_dp, intel_connector, name);
 	intel_encoder->hot_plug = intel_dp_hot_plug;
-	if (is_edp(intel_dp)) {
-		/* initialize panel mode from VBT if available for eDP */
-		if (dev_priv->lfp_lvds_vbt_mode) {
-			dev_priv->panel_fixed_mode =
-				drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
-			if (dev_priv->panel_fixed_mode) {
-				dev_priv->panel_fixed_mode->type |=
-					DRM_MODE_TYPE_PREFERRED;
 	if (is_edp(intel_dp)) {
 		dev_priv->int_edp_connector = connector;
 		intel_panel_setup_backlight(dev);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c – Rev 2330 → 2342