WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_display.c

 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
 	DRM_FORMAT_ARGB8888,
 };
-void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 				struct intel_crtc_state *pipe_config);
 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 		if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 			WARN(1, "pipe_off wait timed out\n");
+	}
+}
-static const char *state_string(bool enabled)
-{
-	return enabled ? "on" : "off";
-}
 /* Only for pre-ILK configs */
 void assert_pll(struct drm_i915_private *dev_priv,
 		enum pipe pipe, bool state)
+{
 	val = I915_READ(DPLL(pipe));
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
-	     state_string(state), state_string(cur_state));
+			onoff(state), onoff(cur_state));
+}
 /* XXX: the dsi pll is shared between MIPI DSI ports */
 	mutex_unlock(&dev_priv->sb_lock);
 	cur_state = val & DSI_PLL_VCO_EN;
 	I915_STATE_WARN(cur_state != state,
 	     "DSI PLL state assertion failure (expected %s, current %s)\n",
-	     state_string(state), state_string(cur_state));
+			onoff(state), onoff(cur_state));
+}
 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 			bool state)
+{
 	bool cur_state;
 	struct intel_dpll_hw_state hw_state;
-	if (WARN (!pll,
-		  "asserting DPLL %s with no DPLL\n", state_string(state)))
+	if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
 		return;
 	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 	I915_STATE_WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s)\n",
-	     pll->name, state_string(state), state_string(cur_state));
+			pll->name, onoff(state), onoff(cur_state));
+}
 		u32 val = I915_READ(FDI_TX_CTL(pipe));
 		cur_state = !!(val & FDI_TX_ENABLE);
+	}
 	I915_STATE_WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
-	     state_string(state), state_string(cur_state));
+			onoff(state), onoff(cur_state));
+}
 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
-	     state_string(state), state_string(cur_state));
+			onoff(state), onoff(cur_state));
+}
 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_PLL_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
-	     state_string(state), state_string(cur_state));
+			onoff(state), onoff(cur_state));
+}
 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 	else
 		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 	I915_STATE_WARN(cur_state != state,
 	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
-	     pipe_name(pipe), state_string(state), state_string(cur_state));
+			pipe_name(pipe), onoff(state), onoff(cur_state));
+}
 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
 		cur_state = false;
+	}
 	I915_STATE_WARN(cur_state != state,
 	     "pipe %c assertion failure (expected %s, current %s)\n",
-	     pipe_name(pipe), state_string(state), state_string(cur_state));
+			pipe_name(pipe), onoff(state), onoff(cur_state));
+}
 static void assert_plane(struct drm_i915_private *dev_priv,
 	val = I915_READ(DSPCNTR(plane));
 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "plane %c assertion failure (expected %s, current %s)\n",
-	     plane_name(plane), state_string(state), state_string(cur_state));
+			plane_name(plane), onoff(state), onoff(cur_state));
+}
 		return;
+	}
 	I915_WRITE(reg, val | PIPECONF_ENABLE);
+	POSTING_READ(reg);
+	/*
+	 * Until the pipe starts DSL will read as 0, which would cause
+	 * an apparent vblank timestamp jump, which messes up also the
+	 * frame count when it's derived from the timestamps. So let's
+	 * wait for the pipe to start properly before we call
+	 * drm_crtc_vblank_on()
+	 */
+	if (dev->max_vblank_count == 0 &&
+	    wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
-	POSTING_READ(reg);
+		DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
+}
 /**
 		return true;
 #endif
 	return false;
+}
-unsigned int
-intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
-		  uint64_t fb_format_modifier, unsigned int plane)
+static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
 {
-	unsigned int tile_height;
+	return IS_GEN2(dev_priv) ? 2048 : 4096;
+}
+static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
-	uint32_t pixel_bytes;
+				     uint64_t fb_modifier, unsigned int cpp)
+{
-	switch (fb_format_modifier) {
-	case DRM_FORMAT_MOD_NONE:
+	switch (fb_modifier) {
-		tile_height = 1;
+	case DRM_FORMAT_MOD_NONE:
-		break;
+		return cpp;
+	case I915_FORMAT_MOD_X_TILED:
-	case I915_FORMAT_MOD_X_TILED:
+		if (IS_GEN2(dev_priv))
+			return 128;
-		tile_height = IS_GEN2(dev) ? 16 : 8;
+		else
+			return 512;
-		break;
+	case I915_FORMAT_MOD_Y_TILED:
-	case I915_FORMAT_MOD_Y_TILED:
+		if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
+			return 128;
-		tile_height = 32;
+		else
-		break;
-	case I915_FORMAT_MOD_Yf_TILED:
+			return 512;
-		pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
-		switch (pixel_bytes) {
+	case I915_FORMAT_MOD_Yf_TILED:
-		default:
-		case 1:
+		switch (cpp) {
-			tile_height = 64;
+		case 1:
-			break;
+			return 64;
-		case 2:
-		case 4:
+		case 2:
-			tile_height = 32;
+		case 4:
-			break;
-		case 8:
-			tile_height = 16;
+			return 128;
-			break;
+		case 8:
 		case 16:
-			WARN_ONCE(1,
+			return 256;
-				  "128-bit pixels are not supported for display!");
+		default:
-			tile_height = 16;
+			MISSING_CASE(cpp);
-			break;
+			return cpp;
+		}
 		break;
 	default:
-		MISSING_CASE(fb_format_modifier);
+		MISSING_CASE(fb_modifier);
-		tile_height = 1;
+		return cpp;
+	}
+}
+unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
-		break;
+			       uint64_t fb_modifier, unsigned int cpp)
+{
+	if (fb_modifier == DRM_FORMAT_MOD_NONE)
+		return 1;
 	else
 		return intel_tile_size(dev_priv) /
-	return tile_height;
+			intel_tile_width(dev_priv, fb_modifier, cpp);
 }
+unsigned int
-unsigned int
+intel_fb_align_height(struct drm_device *dev, unsigned int height,
+		      uint32_t pixel_format, uint64_t fb_modifier)
-intel_fb_align_height(struct drm_device *dev, unsigned int height,
+{
-		      uint32_t pixel_format, uint64_t fb_format_modifier)
+	unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
 	unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
 	return ALIGN(height, intel_tile_height(dev, pixel_format,
-					       fb_format_modifier, 0));
+	return ALIGN(height, tile_height);
+}
+static void
-static void
+intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
-intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
+			const struct drm_plane_state *plane_state)
 			const struct drm_plane_state *plane_state)
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
 	info->pixel_format = fb->pixel_format;
 	info->pitch = fb->pitches[0];
 	info->uv_offset = fb->offsets[1];
 	info->fb_modifier = fb->modifier[0];
+	tile_size = intel_tile_size(dev_priv);
-	tile_height = intel_tile_height(fb->dev, fb->pixel_format,
+	cpp = drm_format_plane_cpp(fb->pixel_format, 0);
-					fb->modifier[0], 0);
+	tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
+	tile_height = tile_size / tile_width;
-	tile_pitch = PAGE_SIZE / tile_height;
-	info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
+	info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
 	info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
-	info->size = info->width_pages * info->height_pages * PAGE_SIZE;
+	info->size = info->width_pages * info->height_pages * tile_size;
 	if (info->pixel_format == DRM_FORMAT_NV12) {
-		tile_height = intel_tile_height(fb->dev, fb->pixel_format,
+		cpp = drm_format_plane_cpp(fb->pixel_format, 1);
+		tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
-						fb->modifier[0], 1);
+		tile_height = tile_size / tile_width;
-		tile_pitch = PAGE_SIZE / tile_height;
-		info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
-		info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
+		info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
-						     tile_height);
-		info->size_uv = info->width_pages_uv * info->height_pages_uv *
+		info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
-				PAGE_SIZE;
+		info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
 	}
+}
-static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
+static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
+{
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		return 4 * 1024;
 	else
 		return 0;
+}
+static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
+					 uint64_t fb_modifier)
+{
+	switch (fb_modifier) {
+	case DRM_FORMAT_MOD_NONE:
+		return intel_linear_alignment(dev_priv);
+	case I915_FORMAT_MOD_X_TILED:
+		if (INTEL_INFO(dev_priv)->gen >= 9)
+			return 256 * 1024;
+		return 0;
+	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Yf_TILED:
+		return 1 * 1024 * 1024;
+	default:
+		MISSING_CASE(fb_modifier);
+		return 0;
+	}
+}
 int
 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			   struct drm_framebuffer *fb,
 			   const struct drm_plane_state *plane_state)
 	u32 alignment;
 	int ret;
-	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
-	switch (fb->modifier[0]) {
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
-	case DRM_FORMAT_MOD_NONE:
-		alignment = intel_linear_alignment(dev_priv);
-		break;
-	case I915_FORMAT_MOD_X_TILED:
-		if (INTEL_INFO(dev)->gen >= 9)
-			alignment = 256 * 1024;
-		else {
-			/* pin() will align the object as required by fence */
-			alignment = 0;
-		}
-		break;
-	case I915_FORMAT_MOD_Y_TILED:
-	case I915_FORMAT_MOD_Yf_TILED:
-		if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
-			  "Y tiling bo slipped through, driver bug!\n"))
-			return -EINVAL;
-		alignment = 1 * 1024 * 1024;
-		break;
-	default:
-		MISSING_CASE(fb->modifier[0]);
 		return -EINVAL;
 	alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
 	i915_gem_object_unpin_from_display_plane(obj, &view);
+}
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
-unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
+u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
-					     int *x, int *y,
+			      int *x, int *y,
-					     unsigned int tiling_mode,
+			      uint64_t fb_modifier,
-					     unsigned int cpp,
+			      unsigned int cpp,
-					     unsigned int pitch)
+			      unsigned int pitch)
 {
+	if (fb_modifier != DRM_FORMAT_MOD_NONE) {
-	if (tiling_mode != I915_TILING_NONE) {
+		unsigned int tile_size, tile_width, tile_height;
 		unsigned int tile_rows, tiles;
+		tile_size = intel_tile_size(dev_priv);
-		tile_rows = *y / 8;
+		tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
-		*y %= 8;
+		tile_height = tile_size / tile_width;
+		tile_rows = *y / tile_height;
+		*y %= tile_height;
-		tiles = *x / (512/cpp);
+		tiles = *x / (tile_width/cpp);
-		*x %= 512/cpp;
+		*x %= tile_width/cpp;
-		return tile_rows * pitch * 8 + tiles * 4096;
+		return tile_rows * pitch * tile_height + tiles * tile_size;
 	 * important and we should probably use that space with FBC or other
 	 * features. */
 	if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
 		return false;
+	mutex_lock(&dev->struct_mutex);
 	obj = i915_gem_object_create_stolen_for_preallocated(dev,
 							     base_aligned,
 							     base_aligned,
 							     size_aligned);
+	if (!obj) {
-	if (!obj)
+		mutex_unlock(&dev->struct_mutex);
+		return false;
 		return false;
 	obj->tiling_mode = plane_config->tiling;
 	mode_cmd.height = fb->height;
 	mode_cmd.pitches[0] = fb->pitches[0];
 	mode_cmd.modifier[0] = fb->modifier[0];
 	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 	mutex_lock(&dev->struct_mutex);
 	if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
 				   &mode_cmd, obj)) {
 		DRM_DEBUG_KMS("intel fb init failed\n");
 		goto out_unref_obj;
+	}
 	mutex_unlock(&dev->struct_mutex);
 	struct drm_i915_gem_object *obj;
 	struct drm_plane *primary = intel_crtc->base.primary;
 	struct drm_plane_state *plane_state = primary->state;
 	struct drm_crtc_state *crtc_state = intel_crtc->base.state;
 	struct intel_plane *intel_plane = to_intel_plane(primary);
+	struct intel_plane_state *intel_state =
+		to_intel_plane_state(plane_state);
 	struct drm_framebuffer *fb;
 	if (!plane_config->fb)
 	plane_state->crtc_x = 0;
 	plane_state->crtc_y = 0;
 	plane_state->crtc_w = fb->width;
 	plane_state->crtc_h = fb->height;
+	intel_state->src.x1 = plane_state->src_x;
+	intel_state->src.y1 = plane_state->src_y;
+	intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
+	intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
+	intel_state->dst.x1 = plane_state->crtc_x;
+	intel_state->dst.y1 = plane_state->crtc_y;
+	intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
+	intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
 	obj = intel_fb_obj(fb);
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dev_priv->preserve_bios_swizzle = true;
 	primary->crtc = primary->state->crtc = &intel_crtc->base;
 	intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
 	obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
+}
-static void i9xx_update_primary_plane(struct drm_crtc *crtc,
+static void i9xx_update_primary_plane(struct drm_plane *primary,
-				      struct drm_framebuffer *fb,
+				      const struct intel_crtc_state *crtc_state,
-				      int x, int y)
+				      const struct intel_plane_state *plane_state)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = primary->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-	struct drm_plane *primary = crtc->primary;
-	bool visible = to_intel_plane_state(primary->state)->visible;
+	struct drm_framebuffer *fb = plane_state->base.fb;
-	struct drm_i915_gem_object *obj;
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int plane = intel_crtc->plane;
-	unsigned long linear_offset;
+	u32 linear_offset;
 	u32 dspcntr;
-	i915_reg_t reg = DSPCNTR(plane);
-	int pixel_size;
-	if (!visible || !fb) {
-		I915_WRITE(reg, 0);
-		if (INTEL_INFO(dev)->gen >= 4)
-			I915_WRITE(DSPSURF(plane), 0);
-		else
+	i915_reg_t reg = DSPCNTR(plane);
-			I915_WRITE(DSPADDR(plane), 0);
-		POSTING_READ(reg);
-		return;
-	}
+	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
-	obj = intel_fb_obj(fb);
-	if (WARN_ON(obj == NULL))
-		return;
+	int x = plane_state->src.x1 >> 16;
-	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	int y = plane_state->src.y1 >> 16;
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
 		I915_WRITE(DSPSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
+			   ((crtc_state->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+			   (crtc_state->pipe_src_w - 1));
 		I915_WRITE(DSPPOS(plane), 0);
 	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
 		I915_WRITE(PRIMSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
+			   ((crtc_state->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+			   (crtc_state->pipe_src_w - 1));
 		I915_WRITE(PRIMPOS(plane), 0);
 		I915_WRITE(PRIMCNSTALPHA(plane), 0);
+	}
 		dspcntr |= DISPPLANE_TILED;
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
-	linear_offset = y * fb->pitches[0] + x * pixel_size;
+	linear_offset = y * fb->pitches[0] + x * cpp;
-	if (INTEL_INFO(dev)->gen >= 4) {
-		intel_crtc->dspaddr_offset =
+	if (INTEL_INFO(dev)->gen >= 4) {
-			intel_gen4_compute_page_offset(dev_priv,
+		intel_crtc->dspaddr_offset =
-						       &x, &y, obj->tiling_mode,
+			intel_compute_tile_offset(dev_priv, &x, &y,
-						       pixel_size,
+						  fb->modifier[0], cpp,
-						       fb->pitches[0]);
+						  fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
 	} else {
 		intel_crtc->dspaddr_offset = linear_offset;
 	}
-	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
+	if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
-		x += (intel_crtc->config->pipe_src_w - 1);
+		x += (crtc_state->pipe_src_w - 1);
-		y += (intel_crtc->config->pipe_src_h - 1);
+		y += (crtc_state->pipe_src_h - 1);
 		/* Finding the last pixel of the last line of the display
 		data and adding to linear_offset*/
 	} else
 		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
 	POSTING_READ(reg);
+}
-static void ironlake_update_primary_plane(struct drm_crtc *crtc,
+static void i9xx_disable_primary_plane(struct drm_plane *primary,
-					  struct drm_framebuffer *fb,
-					  int x, int y)
+				       struct drm_crtc *crtc)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_plane *primary = crtc->primary;
-	bool visible = to_intel_plane_state(primary->state)->visible;
-	struct drm_i915_gem_object *obj;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int plane = intel_crtc->plane;
-	unsigned long linear_offset;
-	u32 dspcntr;
-	i915_reg_t reg = DSPCNTR(plane);
-	int pixel_size;
+	int plane = intel_crtc->plane;
-	if (!visible || !fb) {
+	I915_WRITE(DSPCNTR(plane), 0);
+	if (INTEL_INFO(dev_priv)->gen >= 4)
-		I915_WRITE(reg, 0);
+		I915_WRITE(DSPSURF(plane), 0);
-		I915_WRITE(DSPSURF(plane), 0);
+	else
-		POSTING_READ(reg);
+		I915_WRITE(DSPADDR(plane), 0);
+	POSTING_READ(DSPCNTR(plane));
+}
+static void ironlake_update_primary_plane(struct drm_plane *primary,
+					  const struct intel_crtc_state *crtc_state,
+					  const struct intel_plane_state *plane_state)
+{
+	struct drm_device *dev = primary->dev;
-		return;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	}
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_framebuffer *fb = plane_state->base.fb;
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-	obj = intel_fb_obj(fb);
+	int plane = intel_crtc->plane;
-	if (WARN_ON(obj == NULL))
+	u32 linear_offset;
+	u32 dspcntr;
+	i915_reg_t reg = DSPCNTR(plane);
-		return;
+	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
-	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	int x = plane_state->src.x1 >> 16;
 	int y = plane_state->src.y1 >> 16;
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 		dspcntr |= DISPPLANE_TILED;
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
-	linear_offset = y * fb->pitches[0] + x * pixel_size;
+	linear_offset = y * fb->pitches[0] + x * cpp;
-	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(dev_priv,
+	intel_crtc->dspaddr_offset =
-					       &x, &y, obj->tiling_mode,
+		intel_compute_tile_offset(dev_priv, &x, &y,
-					       pixel_size,
+					  fb->modifier[0], cpp,
-					       fb->pitches[0]);
+					  fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
-	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
+	if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
 		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
-			x += (intel_crtc->config->pipe_src_w - 1);
+			x += (crtc_state->pipe_src_w - 1);
-			y += (intel_crtc->config->pipe_src_h - 1);
+			y += (crtc_state->pipe_src_h - 1);
 			/* Finding the last pixel of the last line of the display
 			data and adding to linear_offset*/
 			linear_offset +=
-				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
+				(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
-				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
+				(crtc_state->pipe_src_w - 1) * cpp;
 		I915_WRITE(DSPLINOFF(plane), linear_offset);
+	}
 	POSTING_READ(reg);
+}
-u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
+u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
-			      uint32_t pixel_format)
+			      uint64_t fb_modifier, uint32_t pixel_format)
-{
-	u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
-	/*
-	 * The stride is either expressed as a multiple of 64 bytes
-	 * chunks for linear buffers or in number of tiles for tiled
-	 * buffers.
-	 */
-	switch (fb_modifier) {
+{
-	case DRM_FORMAT_MOD_NONE:
-		return 64;
-	case I915_FORMAT_MOD_X_TILED:
-		if (INTEL_INFO(dev)->gen == 2)
-			return 128;
-		return 512;
-	case I915_FORMAT_MOD_Y_TILED:
-		/* No need to check for old gens and Y tiling since this is
-		 * about the display engine and those will be blocked before
-		 * we get here.
-		 */
-		return 128;
-	case I915_FORMAT_MOD_Yf_TILED:
-		if (bits_per_pixel == 8)
-			return 64;
-		else
-			return 128;
-	default:
-		MISSING_CASE(fb_modifier);
+	if (fb_modifier == DRM_FORMAT_MOD_NONE) {
+		return 64;
+	} else {
+		int cpp = drm_format_plane_cpp(pixel_format, 0);
-		return 64;
+		return intel_tile_width(dev_priv, fb_modifier, cpp);
+	}
+}
 		return -1;
 	offset = vma->node.start;
 	if (plane == 1) {
-		offset += vma->ggtt_view.params.rotation_info.uv_start_page *
+		offset += vma->ggtt_view.params.rotated.uv_start_page *
 			  PAGE_SIZE;
+	}
 	return 0;
 }
-static void skylake_update_primary_plane(struct drm_crtc *crtc,
+static void skylake_update_primary_plane(struct drm_plane *plane,
-					 struct drm_framebuffer *fb,
+					 const struct intel_crtc_state *crtc_state,
-					 int x, int y)
+					 const struct intel_plane_state *plane_state)
+{
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = plane->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_plane *plane = crtc->primary;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-	bool visible = to_intel_plane_state(plane->state)->visible;
+	struct drm_framebuffer *fb = plane_state->base.fb;
-	struct drm_i915_gem_object *obj;
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int pipe = intel_crtc->pipe;
 	u32 plane_ctl, stride_div, stride;
 	u32 tile_height, plane_offset, plane_size;
-	unsigned int rotation;
+	unsigned int rotation = plane_state->base.rotation;
 	int x_offset, y_offset;
 	u32 surf_addr;
-	struct intel_crtc_state *crtc_state = intel_crtc->config;
+	int scaler_id = plane_state->scaler_id;
-	struct intel_plane_state *plane_state;
+	int src_x = plane_state->src.x1 >> 16;
-	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
-	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
-	int scaler_id = -1;
+	int src_y = plane_state->src.y1 >> 16;
-	plane_state = to_intel_plane_state(plane->state);
+	int src_w = drm_rect_width(&plane_state->src) >> 16;
+	int src_h = drm_rect_height(&plane_state->src) >> 16;
-	if (!visible || !fb) {
+	int dst_x = plane_state->dst.x1;
-		I915_WRITE(PLANE_CTL(pipe, 0), 0);
+	int dst_y = plane_state->dst.y1;
-		I915_WRITE(PLANE_SURF(pipe, 0), 0);
-		POSTING_READ(PLANE_CTL(pipe, 0));
-		return;
+	int dst_w = drm_rect_width(&plane_state->dst);
 	int dst_h = drm_rect_height(&plane_state->dst);
 	plane_ctl = PLANE_CTL_ENABLE |
 		    PLANE_CTL_PIPE_GAMMA_ENABLE |
 		    PLANE_CTL_PIPE_CSC_ENABLE;
-	plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
-	plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
+	plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
-	rotation = plane->state->rotation;
+	plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
-	plane_ctl |= skl_plane_ctl_rotation(rotation);
+	plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 	plane_ctl |= skl_plane_ctl_rotation(rotation);
-	obj = intel_fb_obj(fb);
-	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
-					       fb->pixel_format);
-	surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
-	WARN_ON(drm_rect_width(&plane_state->src) == 0);
-	scaler_id = plane_state->scaler_id;
-	src_x = plane_state->src.x1 >> 16;
-	src_y = plane_state->src.y1 >> 16;
-	src_w = drm_rect_width(&plane_state->src) >> 16;
-	src_h = drm_rect_height(&plane_state->src) >> 16;
 	dst_x = plane_state->dst.x1;
+	stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+					       fb->pixel_format);
-	dst_y = plane_state->dst.y1;
+	surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
-	dst_w = drm_rect_width(&plane_state->dst);
-	dst_h = drm_rect_height(&plane_state->dst);
 	WARN_ON(drm_rect_width(&plane_state->src) == 0);
-	WARN_ON(x != src_x || y != src_y);
+	if (intel_rotation_90_or_270(rotation)) {
-	if (intel_rotation_90_or_270(rotation)) {
+		int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 		/* stride = Surface height in tiles */
-		tile_height = intel_tile_height(dev, fb->pixel_format,
+		/* stride = Surface height in tiles */
-						fb->modifier[0], 0);
+		tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
 		stride = DIV_ROUND_UP(fb->height, tile_height);
-		x_offset = stride * tile_height - y - src_h;
+		x_offset = stride * tile_height - src_y - src_h;
-		y_offset = x;
+		y_offset = src_x;
 		plane_size = (src_w - 1) << 16 | (src_h - 1);
 	} else {
 	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
 	POSTING_READ(PLANE_SURF(pipe, 0));
-}
-/* Assume fb object is pinned & idle & fenced and just update base pointers */
+}
-static int
-intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
+static void skylake_disable_primary_plane(struct drm_plane *primary,
-			   int x, int y, enum mode_set_atomic state)
+					  struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_device *dev = crtc->dev;
+	int pipe = to_intel_crtc(crtc)->pipe;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	I915_WRITE(PLANE_CTL(pipe, 0), 0);
+	I915_WRITE(PLANE_SURF(pipe, 0), 0);
+	POSTING_READ(PLANE_SURF(pipe, 0));
+}
+/* Assume fb object is pinned & idle & fenced and just update base pointers */
+static int
+intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
-	if (dev_priv->fbc.deactivate)
+			   int x, int y, enum mode_set_atomic state)
 		dev_priv->fbc.deactivate(dev_priv);
 	/* Support for kgdboc is disabled, this needs a major rework. */
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+	DRM_ERROR("legacy panic handler not supported any more.\n");
 		struct intel_plane_state *plane_state;
 		drm_modeset_lock_crtc(crtc, &plane->base);
 		plane_state = to_intel_plane_state(plane->base.state);
+		if (plane_state->visible)
+			plane->update_plane(&plane->base,
-		if (crtc->state->active && plane_state->base.fb)
+					    to_intel_crtc_state(crtc->state),
-			plane->commit_plane(&plane->base, plane_state);
+					    plane_state);
 	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
 	struct intel_crtc_state *pipe_config =
 		to_intel_crtc_state(crtc->base.state);
 	struct drm_device *dev = crtc->base.dev;
-	if (atomic->wait_vblank)
-		intel_wait_for_vblank(dev, crtc->pipe);
 	intel_frontbuffer_flip(dev, atomic->fb_bits);
-		crtc->wm.cxsr_allowed = true;
+	crtc->wm.cxsr_allowed = true;
 	if (pipe_config->update_wm_post && pipe_config->base.active)
 		intel_update_watermarks(&crtc->base);
 	if (atomic->update_fbc)
-		intel_fbc_update(crtc);
+		intel_fbc_post_update(crtc);
 	if (atomic->post_enable_primary)
+		intel_post_enable_primary(&crtc->base);
 		intel_post_enable_primary(&crtc->base);
 	memset(atomic, 0, sizeof(*atomic));
 	memset(atomic, 0, sizeof(*atomic));
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
-static void intel_pre_plane_update(struct intel_crtc *crtc)
+	struct intel_crtc_state *pipe_config =
-{
+		to_intel_crtc_state(crtc->base.state);
-	struct drm_device *dev = crtc->base.dev;
+	struct drm_atomic_state *old_state = old_crtc_state->base.state;
+	struct drm_plane *primary = crtc->base.primary;
+	struct drm_plane_state *old_pri_state =
+		drm_atomic_get_existing_plane_state(old_state, primary);
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	bool modeset = needs_modeset(&pipe_config->base);
-	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
+	if (atomic->update_fbc)
-	struct intel_crtc_state *pipe_config =
+		intel_fbc_pre_update(crtc);
-		to_intel_crtc_state(crtc->base.state);
+	if (old_pri_state) {
 		struct intel_plane_state *primary_state =
+			to_intel_plane_state(primary->state);
+		struct intel_plane_state *old_primary_state =
-	if (atomic->disable_fbc)
+			to_intel_plane_state(old_pri_state);
 		intel_fbc_deactivate(crtc);
 		if (old_primary_state->visible &&
-	if (crtc->atomic.disable_ips)
+		    (modeset || !primary_state->visible))
 	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
 	if (intel_crtc->config->has_pch_encoder)
 		intel_wait_for_vblank(dev, pipe);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
-	intel_fbc_enable(intel_crtc);
+	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
+}
 /* IPS only exists on ULT machines and is tied to pipe A. */
 	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
 	if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
+	}
-	intel_fbc_enable(intel_crtc);
+}
 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
+{
 		ironlake_fdi_pll_disable(intel_crtc);
+	}
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
-	intel_fbc_disable_crtc(intel_crtc);
+	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
+}
 		intel_ddi_fdi_disable(crtc);
 		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
 						      true);
-	}
 	intel_fbc_disable_crtc(intel_crtc);
+}
 static void i9xx_pfit_enable(struct intel_crtc *crtc)
 		MISSING_CASE(intel_encoder->type);
 		return POWER_DOMAIN_AUX_A;
+	}
+}
+static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
-static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
+					    struct intel_crtc_state *crtc_state)
+{
 	struct drm_device *dev = crtc->dev;
-	struct intel_encoder *intel_encoder;
+	struct drm_encoder *encoder;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	unsigned long mask;
-	enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
-	if (!crtc->state->active)
+	if (!crtc_state->base.active)
 		return 0;
 	mask = BIT(POWER_DOMAIN_PIPE(pipe));
 	mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
-	if (intel_crtc->config->pch_pfit.enabled ||
+	if (crtc_state->pch_pfit.enabled ||
+	    crtc_state->pch_pfit.force_thru)
+		mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
 	    intel_crtc->config->pch_pfit.force_thru)
+	drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
-		mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
+		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
+		mask |= BIT(intel_display_port_power_domain(intel_encoder));
-	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
+	}
-		mask |= BIT(intel_display_port_power_domain(intel_encoder));
+	return mask;
+}
 	return mask;
 static unsigned long
 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
-static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
+			       struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum intel_display_power_domain domain;
-	enum intel_display_power_domain domain;
+	unsigned long domains, new_domains, old_domains;
 	for_each_power_domain(domain, domains)
 		intel_display_power_put(dev_priv, domain);
-}
-static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
-{
-	struct drm_device *dev = state->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long put_domains[I915_MAX_PIPES] = {};
-	struct drm_crtc_state *crtc_state;
-	struct drm_crtc *crtc;
-	int i;
-	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-		if (needs_modeset(crtc->state))
-			put_domains[to_intel_crtc(crtc)->pipe] =
-				modeset_get_crtc_power_domains(crtc);
-	}
-	if (dev_priv->display.modeset_commit_cdclk) {
-		unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
-		if (cdclk != dev_priv->cdclk_freq &&
-		    !WARN_ON(!state->allow_modeset))
-			dev_priv->display.modeset_commit_cdclk(state);
-	}
-	for (i = 0; i < I915_MAX_PIPES; i++)
-		if (put_domains[i])
-			modeset_put_power_domains(dev_priv, put_domains[i]);
+}
 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
+{
 		return 288000;
 	else
 		return 144000;
+}
-/* Compute the max pixel clock for new configuration. Uses atomic state if
- * that's non-NULL, look at current state otherwise. */
+/* Compute the max pixel clock for new configuration. */
 static int intel_mode_max_pixclk(struct drm_device *dev,
 				 struct drm_atomic_state *state)
+{
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-{
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc;
+	struct drm_crtc *crtc;
-	struct intel_crtc_state *crtc_state;
+	struct drm_crtc_state *crtc_state;
+	unsigned max_pixclk = 0, i;
-	int max_pixclk = 0;
+	enum pipe pipe;
-	for_each_intel_crtc(dev, intel_crtc) {
-		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-		if (IS_ERR(crtc_state))
+	memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
-			return PTR_ERR(crtc_state);
+	       sizeof(intel_state->min_pixclk));
-		if (!crtc_state->base.enable)
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		int pixclk = 0;
-			continue;
+		if (crtc_state->enable)
+			pixclk = crtc_state->adjusted_mode.crtc_clock;
+		intel_state->min_pixclk[i] = pixclk;
+	}
 		max_pixclk = max(max_pixclk,
-				 crtc_state->base.adjusted_mode.crtc_clock);
+	for_each_pipe(dev_priv, pipe)
 		max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
 	return max_pixclk;
+}
+static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
-static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
+	struct drm_device *dev = state->dev;
-{
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_device *dev = state->dev;
+	int max_pixclk = intel_mode_max_pixclk(dev, state);
+	struct intel_atomic_state *intel_state =
+		to_intel_atomic_state(state);
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	if (max_pixclk < 0)
-	int max_pixclk = intel_mode_max_pixclk(dev, state);
+		return max_pixclk;
-	if (max_pixclk < 0)
+	intel_state->cdclk = intel_state->dev_cdclk =
-		return max_pixclk;
+		valleyview_calc_cdclk(dev_priv, max_pixclk);
-	to_intel_atomic_state(state)->cdclk =
+	if (!intel_state->active_crtcs)
+		intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
-		valleyview_calc_cdclk(dev_priv, max_pixclk);
+	return 0;
+}
-	return 0;
 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct drm_device *dev = state->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	int max_pixclk = intel_mode_max_pixclk(dev, state);
-static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
+	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(state);
 	struct drm_device *dev = state->dev;
+}
 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
-	struct drm_device *dev = old_state->dev;
-	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+	struct drm_device *dev = old_state->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_atomic_state *old_intel_state =
+		to_intel_atomic_state(old_state);
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned req_cdclk = old_intel_state->dev_cdclk;
 	/*
 	 * FIXME: We can end up here with all power domains off, yet
 	assert_vblank_disabled(crtc);
 	drm_crtc_vblank_on(crtc);
 	for_each_encoder_on_crtc(dev, crtc, encoder)
-		encoder->enable(encoder);
-	intel_fbc_enable(intel_crtc);
+		encoder->enable(encoder);
+}
 static void i9xx_pfit_disable(struct intel_crtc *crtc)
 		if (encoder->post_pll_disable)
 			encoder->post_pll_disable(encoder);
 	if (!IS_GEN2(dev))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-	intel_fbc_disable_crtc(intel_crtc);
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+}
 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
 		to_intel_plane_state(crtc->primary->state)->visible = false;
+	}
 	dev_priv->display.crtc_disable(crtc);
+	intel_crtc->active = false;
-	intel_crtc->active = false;
+	intel_fbc_disable(intel_crtc);
 	intel_update_watermarks(crtc);
 	intel_disable_shared_dpll(intel_crtc);
 	domains = intel_crtc->enabled_power_domains;
 	for_each_power_domain(domain, domains)
+		intel_display_power_put(dev_priv, domain);
+	intel_crtc->enabled_power_domains = 0;
-		intel_display_power_put(dev_priv, domain);
+	dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
-	intel_crtc->enabled_power_domains = 0;
+	dev_priv->min_pixclk[intel_crtc->pipe] = 0;
+}
 /*
  * turn all crtc's off, but do not adjust state
  * This has to be paired with a call to intel_modeset_setup_hw_state.
  */
-int intel_display_suspend(struct drm_device *dev)
 int intel_display_suspend(struct drm_device *dev)
-	struct drm_mode_config *config = &dev->mode_config;
-	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
-	struct drm_atomic_state *state;
+{
-	struct drm_crtc *crtc;
-	unsigned crtc_mask = 0;
-	int ret = 0;
-	if (WARN_ON(!ctx))
-		return 0;
-	lockdep_assert_held(&ctx->ww_ctx);
-	state = drm_atomic_state_alloc(dev);
-	if (WARN_ON(!state))
-		return -ENOMEM;
-	state->acquire_ctx = ctx;
-	state->allow_modeset = true;
-	for_each_crtc(dev, crtc) {
-		struct drm_crtc_state *crtc_state =
-			drm_atomic_get_crtc_state(state, crtc);
-		ret = PTR_ERR_OR_ZERO(crtc_state);
-		if (ret)
-			goto free;
-		if (!crtc_state->active)
-			continue;
-		crtc_state->active = false;
-		crtc_mask |= 1 << drm_crtc_index(crtc);
-	}
-	if (crtc_mask) {
-		ret = drm_atomic_commit(state);
-		if (!ret) {
-			for_each_crtc(dev, crtc)
-				if (crtc_mask & (1 << drm_crtc_index(crtc)))
-					crtc->state->active = true;
+	struct drm_i915_private *dev_priv = to_i915(dev);
-			return ret;
+	struct drm_atomic_state *state;
 	int ret;
+	state = drm_atomic_helper_suspend(dev);
+	ret = PTR_ERR_OR_ZERO(state);
-free:
+	if (ret)
-	if (ret)
+		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
-		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
+	else
-	drm_atomic_state_free(state);
+		dev_priv->modeset_restore_state = state;
+ *
  * Enable the PLL for @pipe using the supplied @dpll config. To be used
  * in cases where we need the PLL enabled even when @pipe is not going to
  * be enabled.
  */
-void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
+int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
-		      const struct dpll *dpll)
+		     const struct dpll *dpll)
+{
 	struct intel_crtc *crtc =
 		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
-	struct intel_crtc_state pipe_config = {
+	struct intel_crtc_state *pipe_config;
+	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
+	if (!pipe_config)
+		return -ENOMEM;
-		.base.crtc = &crtc->base,
+	pipe_config->base.crtc = &crtc->base;
-		.pixel_multiplier = 1,
+	pipe_config->pixel_multiplier = 1;
-		.dpll = *dpll,
+	pipe_config->dpll = *dpll;
-	};
 	if (IS_CHERRYVIEW(dev)) {
-		chv_compute_dpll(crtc, &pipe_config);
+		chv_compute_dpll(crtc, pipe_config);
-		chv_prepare_pll(crtc, &pipe_config);
+		chv_prepare_pll(crtc, pipe_config);
-		chv_enable_pll(crtc, &pipe_config);
+		chv_enable_pll(crtc, pipe_config);
 	} else {
-		vlv_compute_dpll(crtc, &pipe_config);
+		vlv_compute_dpll(crtc, pipe_config);
-		vlv_prepare_pll(crtc, &pipe_config);
+		vlv_prepare_pll(crtc, pipe_config);
-		vlv_enable_pll(crtc, &pipe_config);
+		vlv_enable_pll(crtc, pipe_config);
+	}
+	kfree(pipe_config);
 	return 0;
+}
 /**
 			return;
+	}
 	pipe_config->gmch_pfit.control = tmp;
-	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
-	if (INTEL_INFO(dev)->gen < 5)
-		pipe_config->gmch_pfit.lvds_border_bits =
-			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
+	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
+}
 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
 static void ironlake_init_pch_refclk(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_encoder *encoder;
-	struct intel_encoder *encoder;
+	int i;
 	u32 val, final;
 	bool has_lvds = false;
 	bool has_cpu_edp = false;
 	bool has_panel = false;
 	bool has_ck505 = false;
+	bool can_ssc = false;
-	bool can_ssc = false;
+	bool using_ssc_source = false;
 	/* We need to take the global config into account */
 	for_each_intel_encoder(dev, encoder) {
 	} else {
 		has_ck505 = false;
 		can_ssc = true;
+	}
+	/* Check if any DPLLs are using the SSC source */
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		u32 temp = I915_READ(PCH_DPLL(i));
+		if (!(temp & DPLL_VCO_ENABLE))
+			continue;
+		if ((temp & PLL_REF_INPUT_MASK) ==
+		    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+			using_ssc_source = true;
+			break;
+		}
+	}
-	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
+	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
-		      has_panel, has_lvds, has_ck505);
+		      has_panel, has_lvds, has_ck505, using_ssc_source);
 	/* Ironlake: try to setup display ref clock before DPLL
 	 * enabling. This is only under driver's control after
 				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
 			else
 				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
 		} else
 			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-	} else {
+	} else if (using_ssc_source) {
-		final |= DREF_SSC_SOURCE_DISABLE;
+		final |= DREF_SSC_SOURCE_ENABLE;
-		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+		final |= DREF_SSC1_ENABLE;
+	}
 	if (final == val)
 		I915_WRITE(PCH_DREF_CONTROL, val);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	} else {
-		DRM_DEBUG_KMS("Disabling SSC entirely\n");
+		DRM_DEBUG_KMS("Disabling CPU source output\n");
 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 		/* Turn off CPU output */
 		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+		I915_WRITE(PCH_DREF_CONTROL, val);
+		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 		I915_WRITE(PCH_DREF_CONTROL, val);
-		POSTING_READ(PCH_DREF_CONTROL);
+		if (!using_ssc_source) {
-		udelay(200);
+			DRM_DEBUG_KMS("Disabling SSC source\n");
-		I915_WRITE(PCH_DREF_CONTROL, val);
+			I915_WRITE(PCH_DREF_CONTROL, val);
-		POSTING_READ(PCH_DREF_CONTROL);
+			POSTING_READ(PCH_DREF_CONTROL);
-		udelay(200);
+			udelay(200);
+		}
+	}
 	BUG_ON(val != final);
 	val = I915_READ(PLANE_SIZE(pipe, 0));
 	fb->height = ((val >> 16) & 0xfff) + 1;
 	fb->width = ((val >> 0) & 0x1fff) + 1;
 	val = I915_READ(PLANE_STRIDE(pipe, 0));
-	stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
+	stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
 						fb->pixel_format);
 	fb->pitches[0] = (val & 0x3ff) * stride_mult;
 	if (HAS_PCH_LPT_LP(dev)) {
 		val = I915_READ(SOUTH_DSPCLK_GATE_D);
 		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
 		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+	}
-	intel_prepare_ddi(dev);
+}
 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+	struct drm_device *dev = old_state->dev;
+	struct intel_atomic_state *old_intel_state =
-	struct drm_device *dev = old_state->dev;
+		to_intel_atomic_state(old_state);
-	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+	unsigned int req_cdclk = old_intel_state->dev_cdclk;
 	broxton_set_cdclk(dev, req_cdclk);
+}
+/* compute the max rate for new configuration */
+static int ilk_max_pixel_rate(struct drm_atomic_state *state)
-/* compute the max rate for new configuration */
+{
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-static int ilk_max_pixel_rate(struct drm_atomic_state *state)
+	struct drm_i915_private *dev_priv = state->dev->dev_private;
-{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *cstate;
-	struct intel_crtc *intel_crtc;
+	struct intel_crtc_state *crtc_state;
-	struct intel_crtc_state *crtc_state;
+	unsigned max_pixel_rate = 0, i;
-	int max_pixel_rate = 0;
+	enum pipe pipe;
-	for_each_intel_crtc(state->dev, intel_crtc) {
+	memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
-		int pixel_rate;
+	       sizeof(intel_state->min_pixclk));
 	for_each_crtc_in_state(state, crtc, cstate, i) {
+		int pixel_rate;
 		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-		if (IS_ERR(crtc_state))
+		crtc_state = to_intel_crtc_state(cstate);
-			return PTR_ERR(crtc_state);
+		if (!crtc_state->base.enable) {
 			intel_state->min_pixclk[i] = 0;
-		if (!crtc_state->base.enable)
+			continue;
 			continue;
+		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
+		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
 			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+}
 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
-	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	int max_pixclk = ilk_max_pixel_rate(state);
 	int cdclk;
 		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
-			  cdclk, dev_priv->max_cdclk_freq);
+			      cdclk, dev_priv->max_cdclk_freq);
 		return -EINVAL;
+	}
+	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+	if (!intel_state->active_crtcs)
-	to_intel_atomic_state(state)->cdclk = cdclk;
+		intel_state->dev_cdclk = 337500;
 	return 0;
+}
+static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
-static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+	struct drm_device *dev = old_state->dev;
 	struct intel_atomic_state *old_intel_state =
-	struct drm_device *dev = old_state->dev;
+		to_intel_atomic_state(old_state);
-	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+	unsigned req_cdclk = old_intel_state->dev_cdclk;
 	broadwell_set_cdclk(dev, req_cdclk);
+}
+static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
+				      struct intel_crtc_state *crtc_state)
+{
 	struct intel_encoder *intel_encoder =
+		intel_ddi_get_crtc_new_encoder(crtc_state);
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
-				      struct intel_crtc_state *crtc_state)
+	if (intel_encoder->type != INTEL_OUTPUT_DSI) {
 		if (!intel_ddi_pll_select(crtc, crtc_state))
 		intel_display_power_put(dev_priv, power_domain);
 	return ret;
 }
 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
-static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
+			       const struct intel_plane_state *plane_state)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t cntl = 0, size = 0;
-	if (on) {
+	if (plane_state && plane_state->visible) {
-		unsigned int width = intel_crtc->base.cursor->state->crtc_w;
+		unsigned int width = plane_state->base.crtc_w;
-		unsigned int height = intel_crtc->base.cursor->state->crtc_h;
+		unsigned int height = plane_state->base.crtc_h;
 		unsigned int stride = roundup_pow_of_two(width) * 4;
 		POSTING_READ(CURCNTR(PIPE_A));
 		intel_crtc->cursor_cntl = cntl;
+	}
+}
+static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
-static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
+			       const struct intel_plane_state *plane_state)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	uint32_t cntl = 0;
-	if (on) {
+	if (plane_state && plane_state->visible) {
 		cntl = MCURSOR_GAMMA_ENABLE;
-		switch (intel_crtc->base.cursor->state->crtc_w) {
+		switch (plane_state->base.crtc_w) {
 			case 64:
 				cntl |= CURSOR_MODE_64_ARGB_AX;
 				break;
 			case 128:
 				cntl |= CURSOR_MODE_128_ARGB_AX;
 				break;
 			case 256:
 				cntl |= CURSOR_MODE_256_ARGB_AX;
 				break;
 			default:
-				MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
+				MISSING_CASE(plane_state->base.crtc_w);
 				return;
+		}
 		cntl |= pipe << 28; /* Connect to correct pipe */
-		if (HAS_DDI(dev))
-			cntl |= CURSOR_PIPE_CSC_ENABLE;
+		if (HAS_DDI(dev))
+			cntl |= CURSOR_PIPE_CSC_ENABLE;
 		if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
-	if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
+			cntl |= CURSOR_ROTATE_180;
 		cntl |= CURSOR_ROTATE_180;
 	intel_crtc->cursor_base = base;
+}
 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
 void intel_crtc_update_cursor(struct drm_crtc *crtc,
-				     bool on)
+				     const struct intel_plane_state *plane_state)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
-	struct drm_plane_state *cursor_state = crtc->cursor->state;
-	int x = cursor_state->crtc_x;
-	int y = cursor_state->crtc_y;
-	u32 base = 0, pos = 0;
+	int pipe = intel_crtc->pipe;
-	base = intel_crtc->cursor_addr;
-	if (x >= intel_crtc->config->pipe_src_w)
+	u32 base = intel_crtc->cursor_addr;
+	u32 pos = 0;
-		on = false;
+	if (plane_state) {
-	if (y >= intel_crtc->config->pipe_src_h)
+		int x = plane_state->base.crtc_x;
-		on = false;
-	if (x < 0) {
-		if (x + cursor_state->crtc_w <= 0)
+		int y = plane_state->base.crtc_y;
 			on = false;
 		if (x < 0) {
-		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+			pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
-		x = -x;
+			x = -x;
-	}
-	pos |= x << CURSOR_X_SHIFT;
 	if (y < 0) {
-		if (y + cursor_state->crtc_h <= 0)
+		pos |= x << CURSOR_X_SHIFT;
 			on = false;
 		if (y < 0) {
-		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
-		y = -y;
 			pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
-	pos |= y << CURSOR_Y_SHIFT;
+			y = -y;
+		}
-	I915_WRITE(CURPOS(pipe), pos);
+		pos |= y << CURSOR_Y_SHIFT;
+		/* ILK+ do this automagically */
-	/* ILK+ do this automagically */
+		if (HAS_GMCH_DISPLAY(dev) &&
+		    plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+			base += (plane_state->base.crtc_h *
-	if (HAS_GMCH_DISPLAY(dev) &&
+				 plane_state->base.crtc_w - 1) * 4;
-	    crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
+		}
 		base += (cursor_state->crtc_h *
-			 cursor_state->crtc_w - 1) * 4;
 	I915_WRITE(CURPOS(pipe), pos);
 	if (IS_845G(dev) || IS_I865G(dev))
-		i845_update_cursor(crtc, base, on);
+		i845_update_cursor(crtc, base, plane_state);
 		return NULL;
 	if (obj->base.size < mode->vdisplay * fb->pitches[0])
+		return NULL;
 		return NULL;
 	drm_framebuffer_reference(fb);
 	return fb;
 #else
 	return NULL;
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_crtc *crtc = NULL;
 	struct drm_device *dev = encoder->dev;
 	struct drm_framebuffer *fb;
 	struct drm_mode_config *config = &dev->mode_config;
-	struct drm_atomic_state *state = NULL;
+	struct drm_atomic_state *state = NULL, *restore_state = NULL;
 	struct drm_connector_state *connector_state;
 	struct intel_crtc_state *crtc_state;
 	int ret, i = -1;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 		      connector->base.id, connector->name,
+		      encoder->base.id, encoder->name);
-		      encoder->base.id, encoder->name);
+	old->restore_state = NULL;
 retry:
 	ret = drm_modeset_lock(&config->connection_mutex, ctx);
 	 *   - try to find the first unused crtc that can drive this connector,
 	 *     and use that if we find one
 	 */
 	/* See if we already have a CRTC for this connector */
-	if (encoder->crtc) {
+	if (connector->state->crtc) {
-		crtc = encoder->crtc;
+		crtc = connector->state->crtc;
 		ret = drm_modeset_lock(&crtc->mutex, ctx);
-		if (ret)
-			goto fail;
-		ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
-		if (ret)
-			goto fail;
-		old->dpms_mode = connector->dpms;
+		if (ret)
-		old->load_detect_temp = false;
-		/* Make sure the crtc and connector are running */
-		if (connector->dpms != DRM_MODE_DPMS_ON)
+			goto fail;
 			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
 		/* Make sure the crtc and connector are running */
-		return true;
+		goto found;
+	}
 	/* Find an unused one (if possible) */
+	for_each_crtc(dev, possible_crtc) {
+		i++;
+		if (!(encoder->possible_crtcs & (1 << i)))
+			continue;
-	for_each_crtc(dev, possible_crtc) {
+		ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
+		if (ret)
-		i++;
+			goto fail;
-		if (!(encoder->possible_crtcs & (1 << i)))
+		if (possible_crtc->state->enable) {
-			continue;
+			drm_modeset_unlock(&possible_crtc->mutex);
-		if (possible_crtc->state->enable)
+			continue;
 	if (!crtc) {
 		DRM_DEBUG_KMS("no pipe available for load-detect\n");
 		goto fail;
+	}
-	ret = drm_modeset_lock(&crtc->mutex, ctx);
-	if (ret)
+found:
+	intel_crtc = to_intel_crtc(crtc);
 		goto fail;
 	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
 	if (ret)
-		goto fail;
-	intel_crtc = to_intel_crtc(crtc);
-	old->dpms_mode = connector->dpms;
-	old->load_detect_temp = true;
-	old->release_fb = NULL;
+		goto fail;
+	state = drm_atomic_state_alloc(dev);
+	restore_state = drm_atomic_state_alloc(dev);
-	state = drm_atomic_state_alloc(dev);
+	if (!state || !restore_state) {
+		ret = -ENOMEM;
-	if (!state)
+		goto fail;
+	}
 		return false;
 	state->acquire_ctx = ctx;
-	state->acquire_ctx = ctx;
+	restore_state->acquire_ctx = ctx;
 	connector_state = drm_atomic_get_connector_state(state, connector);
 	if (IS_ERR(connector_state)) {
+		ret = PTR_ERR(connector_state);
-		ret = PTR_ERR(connector_state);
+		goto fail;
 		goto fail;
 	ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
-	connector_state->crtc = crtc;
+	if (ret)
 	 */
 	fb = mode_fits_in_fbdev(dev, mode);
 	if (fb == NULL) {
 		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
 		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
-		old->release_fb = fb;
 	} else
 		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
 	if (IS_ERR(fb)) {
 		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
 		goto fail;
 	ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
 	if (ret)
 		goto fail;
+	drm_framebuffer_unreference(fb);
+	ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
+	if (ret)
+		goto fail;
+	ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
+	if (!ret)
+		ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
+	if (!ret)
+		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
+	if (ret) {
+		DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
+		goto fail;
+	}
 	drm_mode_copy(&crtc_state->base.mode, mode);
-	if (drm_atomic_commit(state)) {
-		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
+	ret = drm_atomic_commit(state);
-		if (old->release_fb)
+	if (ret) {
+		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
-			old->release_fb->funcs->destroy(old->release_fb);
+		goto fail;
 		goto fail;
-	crtc->primary->crtc = crtc;
+	old->restore_state = restore_state;
 	/* let the connector get through one full cycle before testing */
+	intel_wait_for_vblank(dev, intel_crtc->pipe);
-	intel_wait_for_vblank(dev, intel_crtc->pipe);
+	return true;
 	return true;
 fail:
-fail:
+	drm_atomic_state_free(state);
-	drm_atomic_state_free(state);
+	drm_atomic_state_free(restore_state);
 void intel_release_load_detect_pipe(struct drm_connector *connector,
 				    struct intel_load_detect_pipe *old,
 				    struct drm_modeset_acquire_ctx *ctx)
-{
 	struct drm_device *dev = connector->dev;
 	struct intel_encoder *intel_encoder =
 		intel_attached_encoder(connector);
-	struct drm_encoder *encoder = &intel_encoder->base;
-	struct drm_crtc *crtc = encoder->crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_atomic_state *state;
+	struct drm_encoder *encoder = &intel_encoder->base;
-	struct drm_connector_state *connector_state;
-	struct intel_crtc_state *crtc_state;
+	struct drm_atomic_state *state = old->restore_state;
 	int ret;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
-		      connector->base.id, connector->name,
-		      encoder->base.id, encoder->name);
 		      connector->base.id, connector->name,
-	if (old->load_detect_temp) {
-		state = drm_atomic_state_alloc(dev);
-		if (!state)
-			goto fail;
-		state->acquire_ctx = ctx;
-		connector_state = drm_atomic_get_connector_state(state, connector);
-		if (IS_ERR(connector_state))
-			goto fail;
-		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-		if (IS_ERR(crtc_state))
-			goto fail;
-		connector_state->best_encoder = NULL;
-		connector_state->crtc = NULL;
-		crtc_state->base.enable = crtc_state->base.active = false;
-		ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
-, 0);
-		if (ret)
-			goto fail;
-		ret = drm_atomic_commit(state);
-		if (ret)
-			goto fail;
-		if (old->release_fb) {
-			drm_framebuffer_unregister_private(old->release_fb);
-			drm_framebuffer_unreference(old->release_fb);
+		      encoder->base.id, encoder->name);
-		}
-		return;
-	}
-	/* Switch crtc and encoder back off if necessary */
+	if (!state)
-	if (old->dpms_mode != DRM_MODE_DPMS_ON)
-		connector->funcs->dpms(connector, old->dpms_mode);
+		return;
-	return;
+	ret = drm_atomic_commit(state);
+	if (ret) {
-fail:
+		DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
-	DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
+		drm_atomic_state_free(state);
 	drm_atomic_state_free(state);
+}
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 	struct drm_display_mode *mode;
-	struct intel_crtc_state pipe_config;
+	struct intel_crtc_state *pipe_config;
 	int htot = I915_READ(HTOTAL(cpu_transcoder));
 	int hsync = I915_READ(HSYNC(cpu_transcoder));
 	int vtot = I915_READ(VTOTAL(cpu_transcoder));
 	int vsync = I915_READ(VSYNC(cpu_transcoder));
 	enum pipe pipe = intel_crtc->pipe;
 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 	if (!mode)
+		return NULL;
+	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
+	if (!pipe_config) {
+		kfree(mode);
+		return NULL;
 		return NULL;
 	/*
 	 * Construct a pipe_config sufficient for getting the clock info
 	 * back out of crtc_clock_get.
+	 *
 	 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
 	 * to use a real value here instead.
 	 */
-	pipe_config.cpu_transcoder = (enum transcoder) pipe;
+	pipe_config->cpu_transcoder = (enum transcoder) pipe;
-	pipe_config.pixel_multiplier = 1;
+	pipe_config->pixel_multiplier = 1;
-	pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
+	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
-	pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
+	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
-	pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
+	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
-	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
+	i9xx_crtc_clock_get(intel_crtc, pipe_config);
-	mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
+	mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
 	mode->hdisplay = (htot & 0xffff) + 1;
 	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
 	mode->vsync_start = (vsync & 0xffff) + 1;
 	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
+	drm_mode_set_name(mode);
-	drm_mode_set_name(mode);
+	kfree(pipe_config);
 	return mode;
+}
 	work = intel_crtc->unpin_work;
 	intel_crtc->unpin_work = NULL;
 	spin_unlock_irq(&dev->event_lock);
 	if (work) {
-//		cancel_work_sync(&work->work);
+		cancel_work_sync(&work->work);
 		kfree(work);
+	}
 	if (work->flip_queued_req)
 		i915_gem_request_assign(&work->flip_queued_req, NULL);
 	mutex_unlock(&dev->struct_mutex);
+	intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
-	intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
+	intel_fbc_post_update(crtc);
 	drm_framebuffer_unreference(work->old_fb);
 	 */
 	if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
 		return true;
+	/*
+	 * BDW signals flip done immediately if the plane
+	 * is disabled, even if the plane enable is already
+	 * armed to occur at the next vblank :(
+	 */
 	/*
 	 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
 	 * used the same base address. In that case the mmio flip might
 	 * have completed, but the CS hasn't even executed the flip yet.
+	 *
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	if (intel_rotation_90_or_270(rotation)) {
 		/* stride = Surface height in tiles */
-		tile_height = intel_tile_height(dev, fb->pixel_format,
+		tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
-						fb->modifier[0], 0);
 		stride = DIV_ROUND_UP(fb->height, tile_height);
 	} else {
-	stride = fb->pitches[0] /
+		stride = fb->pitches[0] /
-		 intel_fb_stride_alignment(dev, fb->modifier[0],
+			intel_fb_stride_alignment(dev_priv, fb->modifier[0],
-					   fb->pixel_format);
+						  fb->pixel_format);
+	}
 	/*
 	drm_framebuffer_reference(work->old_fb);
 	drm_gem_object_reference(&obj->base);
 	crtc->primary->fb = fb;
+	update_state_fb(crtc->primary);
-	update_state_fb(crtc->primary);
+	intel_fbc_pre_update(intel_crtc);
 	work->pending_flip_obj = obj;
 		i915_gem_request_assign(&work->flip_queued_req,
 					obj->last_write_req);
 	} else {
 		if (!request) {
-			ret = i915_gem_request_alloc(ring, ring->default_context, &request);
+			request = i915_gem_request_alloc(ring, NULL);
+			if (IS_ERR(request)) {
-			if (ret)
+				ret = PTR_ERR(request);
 				goto cleanup_unpin;
+			}
+		}
 		ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
 						   page_flip_flags);
 	i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
 			  to_intel_plane(primary)->frontbuffer_bit);
-	mutex_unlock(&dev->struct_mutex);
 	mutex_unlock(&dev->struct_mutex);
 	intel_fbc_deactivate(intel_crtc);
 	intel_frontbuffer_flip_prepare(dev,
 				       to_intel_plane(primary)->frontbuffer_bit);
 	trace_i915_flip_request(intel_crtc->plane, obj);
 	return 0;
 cleanup_unpin:
 	intel_unpin_fb_obj(fb, crtc->primary->state);
 cleanup_pending:
-	if (request)
+	if (!IS_ERR_OR_NULL(request))
 	struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
 	struct drm_crtc *crtc = crtc_state->crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_plane *plane = plane_state->plane;
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_plane_state *old_plane_state =
 		to_intel_plane_state(plane->state);
 	int idx = intel_crtc->base.base.id, ret;
-	int i = drm_plane_index(plane);
 	bool mode_changed = needs_modeset(crtc_state);
 	bool was_crtc_enabled = crtc->state->active;
 	bool is_crtc_enabled = crtc_state->active;
 	bool turn_off, turn_on, visible, was_visible;
 	struct drm_framebuffer *fb = plane_state->fb;
 	visible = to_intel_plane_state(plane_state)->visible;
 	if (!was_crtc_enabled && WARN_ON(was_visible))
+		was_visible = false;
-		was_visible = false;
+	/*
+	 * Visibility is calculated as if the crtc was on, but
+	 * after scaler setup everything depends on it being off
+	 * when the crtc isn't active.
+	 */
-	if (!is_crtc_enabled && WARN_ON(visible))
+	if (!is_crtc_enabled)
-		visible = false;
+		to_intel_plane_state(plane_state)->visible = visible = false;
+	if (!was_visible && !visible)
+		return 0;
-	if (!was_visible && !visible)
+	if (fb != old_plane_state->base.fb)
-		return 0;
+		pipe_config->fb_changed = true;
 			pipe_config->disable_cxsr = true;
 	} else if (turn_off) {
 		pipe_config->update_wm_post = true;
 		/* must disable cxsr around plane enable/disable */
-		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-			if (is_crtc_enabled)
-				intel_crtc->atomic.wait_vblank = true;
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
-			pipe_config->disable_cxsr = true;
 			pipe_config->disable_cxsr = true;
 	} else if (intel_wm_need_update(plane, plane_state)) {
 		/* FIXME bollocks */
 		pipe_config->update_wm_pre = true;
 		pipe_config->update_wm_post = true;
 		intel_crtc->atomic.fb_bits |=
 			to_intel_plane(plane)->frontbuffer_bit;
 	switch (plane->type) {
-	case DRM_PLANE_TYPE_PRIMARY:
-		intel_crtc->atomic.pre_disable_primary = turn_off;
+	case DRM_PLANE_TYPE_PRIMARY:
+		intel_crtc->atomic.post_enable_primary = turn_on;
-		intel_crtc->atomic.post_enable_primary = turn_on;
-		if (turn_off) {
-			/*
-			 * FIXME: Actually if we will still have any other
-			 * plane enabled on the pipe we could let IPS enabled
-			 * still, but for now lets consider that when we make
-			 * primary invisible by setting DSPCNTR to 0 on
-			 * update_primary_plane function IPS needs to be
-			 * disable.
-			 */
-			intel_crtc->atomic.disable_ips = true;
-			intel_crtc->atomic.disable_fbc = true;
-		}
-		/*
-		 * FBC does not work on some platforms for rotated
-		 * planes, so disable it when rotation is not 0 and
-		 * update it when rotation is set back to 0.
-		 *
-		 * FIXME: This is redundant with the fbc update done in
-		 * the primary plane enable function except that that
-		 * one is done too late. We eventually need to unify
-		 * this.
-		 */
-		if (visible &&
-		    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
-		    dev_priv->fbc.crtc == intel_crtc &&
-		    plane_state->rotation != BIT(DRM_ROTATE_0))
-			intel_crtc->atomic.disable_fbc = true;
-		/*
-		 * BDW signals flip done immediately if the plane
-		 * is disabled, even if the plane enable is already
-		 * armed to occur at the next vblank :(
-		 */
-		if (turn_on && IS_BROADWELL(dev))
-			intel_crtc->atomic.wait_vblank = true;
 		intel_crtc->atomic.update_fbc = true;
 		intel_crtc->atomic.update_fbc |= visible || mode_changed;
 		break;
 	case DRM_PLANE_TYPE_CURSOR:
 		break;
 		 * cstate->update_wm was already set above, so this flag will
 		 * take effect when we commit and program watermarks.
 		 */
 		if (IS_IVYBRIDGE(dev) &&
 		    needs_scaling(to_intel_plane_state(plane_state)) &&
-		    !needs_scaling(old_plane_state)) {
+		    !needs_scaling(old_plane_state))
-			to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
+			pipe_config->disable_lp_wm = true;
-		} else if (turn_off && !mode_changed) {
-			intel_crtc->atomic.wait_vblank = true;
-			intel_crtc->atomic.update_sprite_watermarks |=
-<< i;
-		}
 		break;
+	}
 	return 0;
 	if (exact || !m || !n || !m2 || !n2)
 		return false;
 	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
-	if (m > m2) {
+	if (n > n2) {
-		while (m > m2) {
+		while (n > n2) {
 			m2 <<= 1;
 			n2 <<= 1;
 		}
-	} else if (m < m2) {
+	} else if (n < n2) {
-		while (m < m2) {
+		while (n < n2) {
 			m <<= 1;
 			n <<= 1;
+		}
+	}
-		}
+	if (n != n2)
 		return false;
-	return m == m2 && n == n2;
+	return intel_fuzzy_clock_check(m, m2);
+}
 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
+{
 	struct drm_device *dev = state->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_shared_dpll_config *shared_dpll = NULL;
-	struct intel_crtc *intel_crtc;
-	struct intel_crtc_state *intel_crtc_state;
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *crtc_state;
 	int i;
 	if (!dev_priv->display.crtc_compute_clock)
 		return;
-	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-		int dpll;
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-		intel_crtc = to_intel_crtc(crtc);
-		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		dpll = intel_crtc_state->shared_dpll;
+		int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll;
+		if (!needs_modeset(crtc_state))
+			continue;
-		if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
+		to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE;
 			continue;
+		if (old_dpll == DPLL_ID_PRIVATE)
-		intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
+			continue;
 		if (!shared_dpll)
 			shared_dpll = intel_atomic_get_shared_dpll_state(state);
 	return ret;
+}
 static int intel_modeset_checks(struct drm_atomic_state *state)
 {
-	struct drm_device *dev = state->dev;
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	struct drm_i915_private *dev_priv = state->dev->dev_private;
+	struct drm_crtc *crtc;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc_state *crtc_state;
-	int ret;
+	int ret = 0, i;
 	if (!check_digital_port_conflicts(state)) {
 		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
+		return -EINVAL;
+	}
+	intel_state->modeset = true;
+	intel_state->active_crtcs = dev_priv->active_crtcs;
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		if (crtc_state->active)
+			intel_state->active_crtcs |= 1 << i;
+		else
-		return -EINVAL;
+			intel_state->active_crtcs &= ~(1 << i);
+	}
 	/*
 	 * See if the config requires any additional preparation, e.g.
 	 * to adjust global state with pipes off.  We need to do this
 	 * here so we can get the modeset_pipe updated config for the new
 	 * mode set on this crtc.  For other crtcs we need to use the
-	 * adjusted_mode bits in the crtc directly.
-	 */
-	if (dev_priv->display.modeset_calc_cdclk) {
+	 * adjusted_mode bits in the crtc directly.
-		unsigned int cdclk;
+	 */
-		ret = dev_priv->display.modeset_calc_cdclk(state);
+	if (dev_priv->display.modeset_calc_cdclk) {
 		ret = dev_priv->display.modeset_calc_cdclk(state);
 		cdclk = to_intel_atomic_state(state)->cdclk;
+		if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+			ret = intel_modeset_all_pipes(state);
-		if (!ret && cdclk != dev_priv->cdclk_freq)
+		if (ret < 0)
-			ret = intel_modeset_all_pipes(state);
+			return ret;
-		if (ret < 0)
+		DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
-			return ret;
+			      intel_state->cdclk, intel_state->dev_cdclk);
 	} else
-		to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
+		to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
  * @state: state to validate
  */
 static int intel_atomic_check(struct drm_device *dev,
 			      struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *crtc_state;
 	int ret, i;
 	bool any_ms = false;
 		ret = intel_modeset_pipe_config(crtc, pipe_config);
 		if (ret)
 			return ret;
 		if (i915.fastboot &&
-		    intel_pipe_config_compare(state->dev,
+		    intel_pipe_config_compare(dev,
 					to_intel_crtc_state(crtc->state),
 					pipe_config, true)) {
 			crtc_state->mode_changed = false;
 			to_intel_crtc_state(crtc_state)->update_pipe = true;
 		ret = intel_modeset_checks(state);
 		if (ret)
 			return ret;
 	} else
-		intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
+		intel_state->cdclk = dev_priv->cdclk_freq;
-	ret = drm_atomic_helper_check_planes(state->dev, state);
+	ret = drm_atomic_helper_check_planes(dev, state);
+	if (ret)
-	if (ret)
+		return ret;
 		return ret;
 	intel_fbc_choose_crtc(dev_priv, state);
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
+static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
+					  struct drm_i915_private *dev_priv,
+					  unsigned crtc_mask)
+{
+	unsigned last_vblank_count[I915_MAX_PIPES];
+	enum pipe pipe;
+	int ret;
+	if (!crtc_mask)
+		return;
+	for_each_pipe(dev_priv, pipe) {
+		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+		if (!((1 << pipe) & crtc_mask))
+			continue;
+		ret = drm_crtc_vblank_get(crtc);
+		if (WARN_ON(ret != 0)) {
+			crtc_mask &= ~(1 << pipe);
+			continue;
+		}
+		last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
+	}
+	for_each_pipe(dev_priv, pipe) {
+		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+		long lret;
+		if (!((1 << pipe) & crtc_mask))
+			continue;
+		lret = wait_event_timeout(dev->vblank[pipe].queue,
+				last_vblank_count[pipe] !=
+					drm_crtc_vblank_count(crtc),
+				msecs_to_jiffies(50));
+		WARN_ON(!lret);
+		drm_crtc_vblank_put(crtc);
+	}
+}
+static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
+{
+	/* fb updated, need to unpin old fb */
+	if (crtc_state->fb_changed)
+		return true;
+	/* wm changes, need vblank before final wm's */
+	if (crtc_state->update_wm_post)
+		return true;
+	/*
+	 * cxsr is re-enabled after vblank.
+	 * This is already handled by crtc_state->update_wm_post,
+	 * but added for clarity.
+	 */
+	if (crtc_state->disable_cxsr)
+		return true;
+	return false;
+}
 /**
  * intel_atomic_commit - commit validated state object
  * @dev: DRM device
  */
 static int intel_atomic_commit(struct drm_device *dev,
 			       struct drm_atomic_state *state,
 			       bool async)
+{
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc_state *crtc_state;
 	struct drm_crtc *crtc;
-	int ret = 0;
+	int ret = 0, i;
-	int i;
+	bool hw_check = intel_state->modeset;
+	unsigned long put_domains[I915_MAX_PIPES] = {};
-	bool any_ms = false;
+	unsigned crtc_vblank_mask = 0;
 	ret = intel_atomic_prepare_commit(dev, state, async);
 	if (ret) {
 		DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
 		return ret;
+	}
+	drm_atomic_helper_swap_state(dev, state);
+	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
+	if (intel_state->modeset) {
+		memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
+		       sizeof(intel_state->min_pixclk));
+		dev_priv->active_crtcs = intel_state->active_crtcs;
+		dev_priv->atomic_cdclk_freq = intel_state->cdclk;
-	drm_atomic_helper_swap_state(dev, state);
+		intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
 	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+		if (needs_modeset(crtc->state) ||
+		    to_intel_crtc_state(crtc->state)->update_pipe) {
+			hw_check = true;
+			put_domains[to_intel_crtc(crtc)->pipe] =
 				modeset_get_crtc_power_domains(crtc,
-	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+					to_intel_crtc_state(crtc->state));
-		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+		}
 		if (!needs_modeset(crtc->state))
-			continue;
+		if (!needs_modeset(crtc->state))
 			continue;
 		any_ms = true;
+		intel_pre_plane_update(to_intel_crtc_state(crtc_state));
 		intel_pre_plane_update(intel_crtc);
 		if (crtc_state->active) {
-		if (crtc_state->active) {
+			intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
-			intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
+			dev_priv->display.crtc_disable(crtc);
 	/* Only after disabling all output pipelines that will be changed can we
 	 * update the the output configuration. */
 	intel_modeset_update_crtc_state(state);
-	if (any_ms) {
+	if (intel_state->modeset) {
+		intel_shared_dpll_commit(state);
+		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
-		intel_shared_dpll_commit(state);
 		if (dev_priv->display.modeset_commit_cdclk &&
-		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
+		    intel_state->dev_cdclk != dev_priv->cdclk_freq)
-		modeset_update_crtc_power_domains(state);
+			dev_priv->display.modeset_commit_cdclk(state);
+	}
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		bool modeset = needs_modeset(crtc->state);
-		bool update_pipe = !modeset &&
-			to_intel_crtc_state(crtc->state)->update_pipe;
+		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		unsigned long put_domains = 0;
+		bool modeset = needs_modeset(crtc->state);
 		struct intel_crtc_state *pipe_config =
-		if (modeset)
+			to_intel_crtc_state(crtc->state);
-			intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+		bool update_pipe = !modeset && pipe_config->update_pipe;
-		if (modeset && crtc->state->active) {
-			update_scanline_offset(to_intel_crtc(crtc));
-			dev_priv->display.crtc_enable(crtc);
-		}
-		if (update_pipe) {
 			put_domains = modeset_get_crtc_power_domains(crtc);
+		if (modeset && crtc->state->active) {
+			update_scanline_offset(to_intel_crtc(crtc));
+			dev_priv->display.crtc_enable(crtc);
+		}
 			/* make sure intel_modeset_check_state runs */
-			any_ms = true;
+		if (!modeset)
 			intel_pre_plane_update(to_intel_crtc_state(crtc_state));
-		if (!modeset)
-			intel_pre_plane_update(intel_crtc);
+		if (crtc->state->active && intel_crtc->atomic.update_fbc)
-		if (crtc->state->active &&
-		    (crtc->state->planes_changed || update_pipe))
-		drm_atomic_helper_commit_planes_on_crtc(crtc_state);
 			intel_fbc_enable(intel_crtc);
 		if (put_domains)
+		if (crtc->state->active &&
-			modeset_put_power_domains(dev_priv, put_domains);
+		    (crtc->state->planes_changed || update_pipe))
+			drm_atomic_helper_commit_planes_on_crtc(crtc_state);
+		if (pipe_config->base.active && needs_vblank_wait(pipe_config))
+			crtc_vblank_mask |= 1 << i;
+	}
+	/* FIXME: add subpixel order */
+	if (!state->legacy_cursor_update)
+		intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
-		intel_post_plane_update(intel_crtc);
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
 		intel_post_plane_update(to_intel_crtc(crtc));
-		if (modeset)
-			intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
+		if (put_domains[i])
 			modeset_put_power_domains(dev_priv, put_domains[i]);
+	}
+	if (intel_state->modeset)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
+	mutex_lock(&dev->struct_mutex);
+	drm_atomic_helper_cleanup_planes(dev, state);
+	mutex_unlock(&dev->struct_mutex);
+	if (hw_check)
+		intel_modeset_check_state(dev, state);
+	drm_atomic_state_free(state);
-	/* FIXME: add subpixel order */
+	/* As one of the primary mmio accessors, KMS has a high likelihood
 	 * of triggering bugs in unclaimed access. After we finish
-	drm_atomic_helper_wait_for_vblanks(dev, state);
+	 * modesetting, see if an error has been flagged, and if so
 	int max_scale;
 	struct drm_device *dev;
 	struct drm_i915_private *dev_priv;
 	int crtc_clock, cdclk;
-	if (!intel_crtc || !crtc_state)
+	if (!intel_crtc || !crtc_state->base.enable)
 		return DRM_PLANE_HELPER_NO_SCALING;
 	dev = intel_crtc->base.dev;
 					     min_scale, max_scale,
 					     can_position, true,
 					     &state->visible);
+}
-static void
-intel_commit_primary_plane(struct drm_plane *plane,
-			   struct intel_plane_state *state)
-{
-	struct drm_crtc *crtc = state->base.crtc;
-	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	crtc = crtc ? crtc : plane->crtc;
-	dev_priv->display.update_primary_plane(crtc, fb,
-					       state->src.x1 >> 16,
-					       state->src.y1 >> 16);
-}
-static void
-intel_disable_primary_plane(struct drm_plane *plane,
-			    struct drm_crtc *crtc)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
-}
 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 				    struct drm_crtc_state *old_crtc_state)
+{
 	struct drm_device *dev = crtc->dev;
+	}
 	primary->pipe = pipe;
 	primary->plane = pipe;
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
 	primary->check_plane = intel_check_primary_plane;
-	primary->commit_plane = intel_commit_primary_plane;
-	primary->disable_plane = intel_disable_primary_plane;
 	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
 		primary->plane = !pipe;
 	if (INTEL_INFO(dev)->gen >= 9) {
 		intel_primary_formats = skl_primary_formats;
+		num_formats = ARRAY_SIZE(skl_primary_formats);
+		primary->update_plane = skylake_update_primary_plane;
+		primary->disable_plane = skylake_disable_primary_plane;
+	} else if (HAS_PCH_SPLIT(dev)) {
+		intel_primary_formats = i965_primary_formats;
+		num_formats = ARRAY_SIZE(i965_primary_formats);
+		primary->update_plane = ironlake_update_primary_plane;
-		num_formats = ARRAY_SIZE(skl_primary_formats);
+		primary->disable_plane = i9xx_disable_primary_plane;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
 		intel_primary_formats = i965_primary_formats;
+		num_formats = ARRAY_SIZE(i965_primary_formats);
+		primary->update_plane = i9xx_update_primary_plane;
-		num_formats = ARRAY_SIZE(i965_primary_formats);
+		primary->disable_plane = i9xx_disable_primary_plane;
 	} else {
 		intel_primary_formats = i8xx_primary_formats;
+		num_formats = ARRAY_SIZE(i8xx_primary_formats);
+		primary->update_plane = i9xx_update_primary_plane;
-		num_formats = ARRAY_SIZE(i8xx_primary_formats);
+		primary->disable_plane = i9xx_disable_primary_plane;
+	}
 	drm_universal_plane_init(dev, &primary->base, 0,
 static void
 intel_disable_cursor_plane(struct drm_plane *plane,
 			   struct drm_crtc *crtc)
+{
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-{
+	intel_crtc->cursor_addr = 0;
-	intel_crtc_update_cursor(crtc, false);
+	intel_crtc_update_cursor(crtc, NULL);
+}
+static void
-static void
+intel_update_cursor_plane(struct drm_plane *plane,
-intel_commit_cursor_plane(struct drm_plane *plane,
+			  const struct intel_crtc_state *crtc_state,
-			  struct intel_plane_state *state)
+			  const struct intel_plane_state *state)
+{
 	struct drm_crtc *crtc = crtc_state->base.crtc;
-	struct drm_crtc *crtc = state->base.crtc;
-	struct drm_device *dev = plane->dev;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_crtc *intel_crtc;
+	struct drm_device *dev = plane->dev;
-	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
-	uint32_t addr;
-	crtc = crtc ? crtc : plane->crtc;
+	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
-	intel_crtc = to_intel_crtc(crtc);
+	uint32_t addr;
 	if (!obj)
 		addr = 0;
 	else if (!INTEL_INFO(dev)->cursor_needs_physical)
 		addr = i915_gem_obj_ggtt_offset(obj);
-	else
-		addr = obj->phys_handle->busaddr;
+	else
-	intel_crtc->cursor_addr = addr;
+		addr = obj->phys_handle->busaddr;
-	if (crtc->state->active)
+	intel_crtc->cursor_addr = addr;
-		intel_crtc_update_cursor(crtc, state->visible);
+	intel_crtc_update_cursor(crtc, state);
 	cursor->max_downscale = 1;
 	cursor->pipe = pipe;
 	cursor->plane = pipe;
 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
 	cursor->check_plane = intel_check_cursor_plane;
-	cursor->commit_plane = intel_commit_cursor_plane;
+	cursor->update_plane = intel_update_cursor_plane;
 	cursor->disable_plane = intel_disable_cursor_plane;
 	drm_universal_plane_init(dev, &cursor->base, 0,
 				 &intel_plane_funcs,
 			 uint32_t pixel_format)
+{
 	u32 gen = INTEL_INFO(dev)->gen;
+	if (gen >= 9) {
+		int cpp = drm_format_plane_cpp(pixel_format, 0);
 	if (gen >= 9) {
 		/* "The stride in bytes must not exceed the of the size of 8K
 		 *  pixels and 32K bytes."
 		 */
-		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
+		return min(8192 * cpp, 32768);
 	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		return 32*1024;
 	} else if (gen >= 4) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
 static int intel_framebuffer_init(struct drm_device *dev,
 				  struct intel_framebuffer *intel_fb,
 				  struct drm_mode_fb_cmd2 *mode_cmd,
 				  struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	unsigned int aligned_height;
 	int ret;
 	u32 pitch_limit, stride_alignment;
 		DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
 			  mode_cmd->modifier[0]);
 		return -EINVAL;
+	}
+	stride_alignment = intel_fb_stride_alignment(dev_priv,
-	stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
+						     mode_cmd->modifier[0],
 						     mode_cmd->pixel_format);
 	if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
 		DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
 			  mode_cmd->pitches[0], stride_alignment);
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
-	intel_fb->obj = obj;
-	intel_fb->obj->framebuffer_references++;
+	intel_fb->obj = obj;
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
 		DRM_ERROR("framebuffer init failed %d\n", ret);
+		return ret;
+	}
-		return ret;
+	intel_fb->obj->framebuffer_references++;
 	kolibri_framebuffer_init(intel_fb);
 	kolibri_framebuffer_init(intel_fb);
 	return 0;
+}
 			skylake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
-		dev_priv->display.update_primary_plane =
-			skylake_update_primary_plane;
 	} else if (HAS_DDI(dev)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
-		dev_priv->display.update_primary_plane =
-			ironlake_update_primary_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			ironlake_crtc_compute_clock;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
-		dev_priv->display.update_primary_plane =
-			ironlake_update_primary_plane;
 	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = valleyview_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
-		dev_priv->display.update_primary_plane =
-			i9xx_update_primary_plane;
 	} else {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = i9xx_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
-		dev_priv->display.update_primary_plane =
-			i9xx_update_primary_plane;
+	}
 	/* Returns the core display clock speed */
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 	POSTING_READ(vga_reg);
+}
 void intel_modeset_init_hw(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	intel_update_cdclk(dev);
-	intel_update_cdclk(dev);
+	dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
 	intel_prepare_ddi(dev);
 	intel_init_clock_gating(dev);
 	intel_enable_gt_powersave(dev);
+}
+/*
+ * Calculate what we think the watermarks should be for the state we've read
+ * out of the hardware and then immediately program those watermarks so that
+ * we ensure the hardware settings match our internal state.
+ *
+ * We can calculate what we think WM's should be by creating a duplicate of the
+ * current state (which was constructed during hardware readout) and running it
+ * through the atomic check code to calculate new watermark values in the
+ * state object.
+ */
+static void sanitize_watermarks(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_atomic_state *state;
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *cstate;
+	struct drm_modeset_acquire_ctx ctx;
+	int ret;
+	int i;
+	/* Only supported on platforms that use atomic watermark design */
+	if (!dev_priv->display.program_watermarks)
+		return;
+	/*
+	 * We need to hold connection_mutex before calling duplicate_state so
+	 * that the connector loop is protected.
+	 */
+	drm_modeset_acquire_init(&ctx, 0);
+retry:
+	ret = drm_modeset_lock_all_ctx(dev, &ctx);
+	if (ret == -EDEADLK) {
+		drm_modeset_backoff(&ctx);
+		goto retry;
+	} else if (WARN_ON(ret)) {
+		goto fail;
+	}
+	state = drm_atomic_helper_duplicate_state(dev, &ctx);
+	if (WARN_ON(IS_ERR(state)))
+		goto fail;
+	ret = intel_atomic_check(dev, state);
+	if (ret) {
+		/*
+		 * If we fail here, it means that the hardware appears to be
+		 * programmed in a way that shouldn't be possible, given our
+		 * understanding of watermark requirements.  This might mean a
+		 * mistake in the hardware readout code or a mistake in the
+		 * watermark calculations for a given platform.  Raise a WARN
+		 * so that this is noticeable.
+		 *
+		 * If this actually happens, we'll have to just leave the
+		 * BIOS-programmed watermarks untouched and hope for the best.
+		 */
+		WARN(true, "Could not determine valid watermarks for inherited state\n");
+		goto fail;
+	}
+	/* Write calculated watermark values back */
+	to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
+	for_each_crtc_in_state(state, crtc, cstate, i) {
+		struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
+		dev_priv->display.program_watermarks(cs);
+	}
+	drm_atomic_state_free(state);
+fail:
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+}
 void intel_modeset_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 		 * If the fb is shared between multiple heads, we'll
 		 * just get the first one.
 		 */
 		intel_find_initial_plane_obj(crtc, &plane_config);
+	}
+	/*
+	 * Make sure hardware watermarks really match the state we read out.
+	 * Note that we need to do this after reconstructing the BIOS fb's
+	 * since the watermark calculation done here will use pstate->fb.
+	 */
+	sanitize_watermarks(dev);
+}
 static void intel_enable_pipe_a(struct drm_device *dev)
+{
 		return true;
 	return false;
+}
+static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct intel_connector *connector;
+	for_each_connector_on_encoder(dev, &encoder->base, connector)
+		return true;
+	return false;
+}
 static void intel_sanitize_crtc(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 		WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
 		crtc->base.state->active = crtc->active;
 		crtc->base.enabled = crtc->active;
+		crtc->base.state->connector_mask = 0;
-		crtc->base.state->connector_mask = 0;
+		crtc->base.state->encoder_mask = 0;
 		/* Because we only establish the connector -> encoder ->
 		 * crtc links if something is active, this means the
 static void intel_sanitize_encoder(struct intel_encoder *encoder)
+{
 	struct intel_connector *connector;
-	struct drm_device *dev = encoder->base.dev;
-	bool active = false;
+	struct drm_device *dev = encoder->base.dev;
 	/* We need to check both for a crtc link (meaning that the
 	 * encoder is active and trying to read from a pipe) and the
 	 * pipe itself being active. */
-	bool has_active_crtc = encoder->base.crtc &&
-		to_intel_crtc(encoder->base.crtc)->active;
-	for_each_intel_connector(dev, connector) {
-		if (connector->base.encoder != &encoder->base)
-			continue;
-		active = true;
-		break;
+	bool has_active_crtc = encoder->base.crtc &&
 		to_intel_crtc(encoder->base.crtc)->active;
-	if (active && !has_active_crtc) {
+	if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	int i;
+	dev_priv->active_crtcs = 0;
 	for_each_intel_crtc(dev, crtc) {
-		__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
-		memset(crtc->config, 0, sizeof(*crtc->config));
+		struct intel_crtc_state *crtc_state = crtc->config;
-		crtc->config->base.crtc = &crtc->base;
+		int pixclk = 0;
+		__drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
-		crtc->active = dev_priv->display.get_pipe_config(crtc,
+		memset(crtc_state, 0, sizeof(*crtc_state));
+		crtc_state->base.crtc = &crtc->base;
-								 crtc->config);
+		crtc_state->base.active = crtc_state->base.enable =
+			dev_priv->display.get_pipe_config(crtc, crtc_state);
+		crtc->base.enabled = crtc_state->base.enable;
+		crtc->active = crtc_state->base.active;
+		if (crtc_state->base.active) {
+			dev_priv->active_crtcs |= 1 << crtc->pipe;
+			if (IS_BROADWELL(dev_priv)) {
+				pixclk = ilk_pipe_pixel_rate(crtc_state);
+				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+				if (crtc_state->ips_enabled)
+					pixclk = DIV_ROUND_UP(pixclk * 100, 95);
+			} else if (IS_VALLEYVIEW(dev_priv) ||
+				   IS_CHERRYVIEW(dev_priv) ||
+				   IS_BROXTON(dev_priv))
+				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
+			else
+				WARN_ON(dev_priv->display.modeset_calc_cdclk);
+		}
 		crtc->base.state->active = crtc->active;
-		crtc->base.enabled = crtc->active;
+		dev_priv->min_pixclk[crtc->pipe] = pixclk;
 				 * because anything calling .crtc_disable may
 				 * rely on the connector_mask being accurate.
 				 */
 				encoder->base.crtc->state->connector_mask |=
 << drm_connector_index(&connector->base);
+				encoder->base.crtc->state->encoder_mask |=
+<< drm_encoder_index(&encoder->base);
+			}
 		} else {
 			connector->base.dpms = DRM_MODE_DPMS_OFF;
 		ilk_wm_get_hw_state(dev);
 	for_each_intel_crtc(dev, crtc) {
 		unsigned long put_domains;
-		put_domains = modeset_get_crtc_power_domains(&crtc->base);
+		put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
 		if (WARN_ON(put_domains))
 			modeset_put_power_domains(dev_priv, put_domains);
+	}
+	intel_display_set_init_power(dev_priv, false);
-	intel_display_set_init_power(dev_priv, false);
+	intel_fbc_init_pipe_state(dev_priv);
+}
 void intel_display_resume(struct drm_device *dev)
-{
-	struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
+{
-	struct intel_connector *conn;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_atomic_state *state = dev_priv->modeset_restore_state;
-	struct intel_plane *plane;
+	struct drm_modeset_acquire_ctx ctx;
-	struct drm_crtc *crtc;
+	int ret;
+	bool setup = false;
+	dev_priv->modeset_restore_state = NULL;
+	/*
-	int ret;
+	 * This is a cludge because with real atomic modeset mode_config.mutex
+	 * won't be taken. Unfortunately some probed state like
+	 * audio_codec_enable is still protected by mode_config.mutex, so lock
-	if (!state)
+	 * it here for now.
+	 */
+	mutex_lock(&dev->mode_config.mutex);
+	drm_modeset_acquire_init(&ctx, 0);
-		return;
+retry:
+	ret = drm_modeset_lock_all_ctx(dev, &ctx);
+	/*
-	state->acquire_ctx = dev->mode_config.acquire_ctx;
+	 * With MST, the number of connectors can change between suspend and
+	 * resume, which means that the state we want to restore might now be
+	 * impossible to use since it'll be pointing to non-existant
-	/* preserve complete old state, including dpll */
+	 * connectors.
-	intel_atomic_get_shared_dpll_state(state);
+	 */
+	if (ret == 0 && state &&
-	for_each_crtc(dev, crtc) {
+	    state->num_connector != dev->mode_config.num_connector) {
-		struct drm_crtc_state *crtc_state =
+		drm_atomic_state_free(state);
-			drm_atomic_get_crtc_state(state, crtc);
+		state = NULL;
+	}
-		ret = PTR_ERR_OR_ZERO(crtc_state);
+	if (ret == 0 && !setup) {
+		setup = true;
+		intel_modeset_setup_hw_state(dev);
+		i915_redisable_vga(dev);
+	}
+	if (ret == 0 && state) {
+		struct drm_crtc_state *crtc_state;
-		if (ret)
+		struct drm_crtc *crtc;
+		int i;
 			goto err;
-		/* force a restore */
+		state->acquire_ctx = &ctx;
-		crtc_state->mode_changed = true;
-	}
+		for_each_crtc_in_state(state, crtc, crtc_state, i) {
-	for_each_intel_plane(dev, plane) {
+			/*
+			 * Force recalculation even if we restore
+			 * current state. With fast modeset this may not result
-		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
+			 * in a modeset when the state is compatible.
-		if (ret)
+			 */
-			goto err;
+			crtc_state->mode_changed = true;
-	}
+		}
 	for_each_intel_connector(dev, conn) {
-		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
+		ret = drm_atomic_commit(state);
 		if (ret)
-			goto err;
+	if (ret == -EDEADLK) {
 		drm_modeset_backoff(&ctx);
 		goto retry;
 	intel_modeset_setup_hw_state(dev);
-	i915_redisable_vga(dev);
-	ret = drm_atomic_commit(state);
+	drm_modeset_drop_locks(&ctx);
-	if (!ret)
-		return;
+	drm_modeset_acquire_fini(&ctx);
 	mutex_unlock(&dev->mode_config.mutex);
 	 */
 	drm_kms_helper_poll_fini(dev);
 	intel_unregister_dsm_handler();
-	intel_fbc_disable(dev_priv);
+	intel_fbc_global_disable(dev_priv);
 	drm_mode_config_cleanup(dev);
 	intel_cleanup_overlay(dev);
-	mutex_lock(&dev->struct_mutex);
+	intel_cleanup_overlay(dev);
 	intel_cleanup_gt_powersave(dev);
-	mutex_unlock(&dev->struct_mutex);
+	intel_cleanup_gt_powersave(dev);
 #endif
+	}
 	return 0;
-}
 #ifdef CONFIG_DEBUG_FS
 struct intel_display_error_state {
 		err_printf(m, "PWR_WELL_CTL2: %08x\n",
 			   error->power_well_driver);
 	for_each_pipe(dev_priv, i) {
 		err_printf(m, "Pipe [%d]:\n", i);
 		err_printf(m, "  Power: %s\n",
-			   error->pipe[i].power_domain_on ? "on" : "off");
+			   onoff(error->pipe[i].power_domain_on));
 		err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
 		err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
 		err_printf(m, "Plane [%d]:\n", i);
 	for (i = 0; i < error->num_transcoders; i++) {
 		err_printf(m, "CPU transcoder: %c\n",
 			   transcoder_name(error->transcoder[i].cpu_transcoder));
 		err_printf(m, "  Power: %s\n",
-			   error->transcoder[i].power_domain_on ? "on" : "off");
+			   onoff(error->transcoder[i].power_domain_on));
 		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
 		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
 		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
 		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
 		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
 		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
 		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
+	}
-}
-#endif
-void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
-{
-	struct intel_crtc *crtc;
-	for_each_intel_crtc(dev, crtc) {
-		struct intel_unpin_work *work;
-		spin_lock_irq(&dev->event_lock);
-		work = crtc->unpin_work;
-		if (work && work->event &&
-		    work->event->base.file_priv == file) {
-			kfree(work->event);
-			work->event = NULL;
-		}
-		spin_unlock_irq(&dev->event_lock);
-	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 6937 → 7144