WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_display.c

 		MISSING_CASE(fb_modifier);
 		return 64;
+	}
+}
-unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
 				     struct drm_i915_gem_object *obj,
 				     unsigned int plane)
+{
 	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
 	struct i915_vma *vma;
-	unsigned char *offset;
+	u64 offset;
 	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
 		view = &i915_ggtt_view_rotated;
 	vma = i915_gem_obj_to_ggtt_view(obj, view);
 	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
 		view->type))
 		return -1;
-	offset = (unsigned char *)vma->node.start;
+	offset = vma->node.start;
+	if (plane == 1) {
+		offset += vma->ggtt_view.rotation_info.uv_start_page *
-	if (plane == 1) {
+			  PAGE_SIZE;
 		offset += vma->ggtt_view.rotation_info.uv_start_page *
 			  PAGE_SIZE;
 	WARN_ON(upper_32_bits(offset));
 	int pipe = intel_crtc->pipe;
 	u32 plane_ctl, stride_div, stride;
 	u32 tile_height, plane_offset, plane_size;
 	unsigned int rotation;
 	int x_offset, y_offset;
-	unsigned long surf_addr;
+	u32 surf_addr;
 	struct intel_crtc_state *crtc_state = intel_crtc->config;
 	struct intel_plane_state *plane_state;
 	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
 	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
 	int scaler_id = -1;
 	DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
 		      intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
 	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-		&state->scaler_state.scaler_id, DRM_ROTATE_0,
+		&state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
 		state->pipe_src_w, state->pipe_src_h,
 		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
 static void ironlake_init_pch_refclk(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_encoder *encoder;
-	struct intel_encoder *encoder;
+	int i;
 	u32 val, final;
 	bool has_lvds = false;
 	bool has_cpu_edp = false;
 	bool has_panel = false;
 	bool has_ck505 = false;
+	bool can_ssc = false;
-	bool can_ssc = false;
+	bool using_ssc_source = false;
 	/* We need to take the global config into account */
 	for_each_intel_encoder(dev, encoder) {
 	} else {
 		has_ck505 = false;
 		can_ssc = true;
+	}
+	/* Check if any DPLLs are using the SSC source */
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		u32 temp = I915_READ(PCH_DPLL(i));
+		if (!(temp & DPLL_VCO_ENABLE))
+			continue;
+		if ((temp & PLL_REF_INPUT_MASK) ==
+		    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+			using_ssc_source = true;
+			break;
+		}
+	}
-	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
+	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
-		      has_panel, has_lvds, has_ck505);
+		      has_panel, has_lvds, has_ck505, using_ssc_source);
 	/* Ironlake: try to setup display ref clock before DPLL
 	 * enabling. This is only under driver's control after
 				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
 			else
 				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
 		} else
 			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-	} else {
+	} else if (using_ssc_source) {
-		final |= DREF_SSC_SOURCE_DISABLE;
+		final |= DREF_SSC_SOURCE_ENABLE;
-		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+		final |= DREF_SSC1_ENABLE;
+	}
 	if (final == val)
 		I915_WRITE(PCH_DREF_CONTROL, val);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	} else {
-		DRM_DEBUG_KMS("Disabling SSC entirely\n");
+		DRM_DEBUG_KMS("Disabling CPU source output\n");
 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 		/* Turn off CPU output */
 		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+		I915_WRITE(PCH_DREF_CONTROL, val);
+		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 		I915_WRITE(PCH_DREF_CONTROL, val);
-		POSTING_READ(PCH_DREF_CONTROL);
+		if (!using_ssc_source) {
-		udelay(200);
+			DRM_DEBUG_KMS("Disabling SSC source\n");
 		I915_WRITE(PCH_DREF_CONTROL, val);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
+	}
+	}
 	BUG_ON(val != final);
 	mutex_lock(&dev_priv->rps.hw_lock);
 	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
+	mutex_unlock(&dev_priv->rps.hw_lock);
-	mutex_unlock(&dev_priv->rps.hw_lock);
+	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 	intel_update_cdclk(dev);
 		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
 			      bpp, connector->base.display_info.bpc*3);
 		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
+	}
-	/* Clamp bpp to default limit on screens without EDID 1.4 */
+	/* Clamp bpp to 8 on screens without EDID 1.4 */
-	if (connector->base.display_info.bpc == 0) {
-		int type = connector->base.connector_type;
-		int clamp_bpp = 24;
-		/* Fall back to 18 bpp when DP sink capability is unknown. */
-		if (type == DRM_MODE_CONNECTOR_DisplayPort ||
-		    type == DRM_MODE_CONNECTOR_eDP)
-			clamp_bpp = 18;
-		if (bpp > clamp_bpp) {
+	if (connector->base.display_info.bpc == 0 && bpp > 24) {
-			DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
+		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
-				      bpp, clamp_bpp);
+			      bpp);
-			pipe_config->pipe_bpp = clamp_bpp;
 		pipe_config->pipe_bpp = 24;
+	}
+}
 			intel_dp_init(dev, PCH_DP_C, PORT_C);
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
+	} else if (IS_VALLEYVIEW(dev)) {
+		bool has_edp, has_port;
 	} else if (IS_VALLEYVIEW(dev)) {
 		/*
 		 * The DP_DETECTED bit is the latched state of the DDC
 		 * SDA pin at boot. However since eDP doesn't require DDC
 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
 		 * eDP ports may have been muxed to an alternate function.
 		 * Thus we can't rely on the DP_DETECTED bit alone to detect
 		 * eDP ports. Consult the VBT as well as DP_DETECTED to
+		 * detect eDP ports.
+		 *
+		 * Sadly the straps seem to be missing sometimes even for HDMI
+		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
+		 * and VBT for the presence of the port. Additionally we can't
+		 * trust the port type the VBT declares as we've seen at least
-		 * detect eDP ports.
+		 * HDMI ports that the VBT claim are DP or eDP.
+		 */
+		has_edp = intel_dp_is_edp(dev, PORT_B);
-		 */
+		has_port = intel_bios_is_port_present(dev_priv, PORT_B);
-		if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
+		if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
+			has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
-		    !intel_dp_is_edp(dev, PORT_B))
+		if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
-			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
-		if (I915_READ(VLV_DP_B) & DP_DETECTED ||
-		    intel_dp_is_edp(dev, PORT_B))
+			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
-			intel_dp_init(dev, VLV_DP_B, PORT_B);
+		has_edp = intel_dp_is_edp(dev, PORT_C);
+		has_port = intel_bios_is_port_present(dev_priv, PORT_C);
+		if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
-		if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
+			has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
-		    !intel_dp_is_edp(dev, PORT_C))
-			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
-		if (I915_READ(VLV_DP_C) & DP_DETECTED ||
-		    intel_dp_is_edp(dev, PORT_C))
+		if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
+			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
-			intel_dp_init(dev, VLV_DP_C, PORT_C);
+		if (IS_CHERRYVIEW(dev)) {
+			/*
-		if (IS_CHERRYVIEW(dev)) {
+			 * eDP not supported on port D,
-			/* eDP not supported on port D, so don't check VBT */
+			 * so no need to worry about it
-			if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
+			 */
+			has_port = intel_bios_is_port_present(dev_priv, PORT_D);
+			if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
-				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
+				intel_dp_init(dev, CHV_DP_D, PORT_D);
-			if (I915_READ(CHV_DP_D) & DP_DETECTED)
+			if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
-				intel_dp_init(dev, CHV_DP_D, PORT_D);
+				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
+		}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 6320 → 6660