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Rev 6296 Rev 6320
Line 3943... Line 3943...
3943
				      intel_crtc->pipe,
3943
				      intel_crtc->pipe,
3944
				      work->event);
3944
				      work->event);
Line 3945... Line 3945...
3945
 
3945
 
Line 3946... Line 3946...
3946
	drm_crtc_vblank_put(&intel_crtc->base);
3946
	drm_crtc_vblank_put(&intel_crtc->base);
3947
 
3947
 
Line 3948... Line 3948...
3948
//	wake_up_all(&dev_priv->pending_flip_queue);
3948
	wake_up_all(&dev_priv->pending_flip_queue);
3949
//	queue_work(dev_priv->wq, &work->work);
3949
	queue_work(dev_priv->wq, &work->work);
3950
 
3950
 
3951
//	trace_i915_flip_complete(intel_crtc->plane,
3951
	trace_i915_flip_complete(intel_crtc->plane,
3952
//				 work->pending_flip_obj);
3952
				 work->pending_flip_obj);
3953
}
3953
}
3954
#if 0
3954
 
3955
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3955
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Line 3975... Line 3975...
3975
		mutex_lock(&dev->struct_mutex);
3975
		mutex_lock(&dev->struct_mutex);
3976
		intel_finish_fb(crtc->primary->fb);
3976
		intel_finish_fb(crtc->primary->fb);
3977
		mutex_unlock(&dev->struct_mutex);
3977
		mutex_unlock(&dev->struct_mutex);
3978
	}
3978
	}
3979
}
3979
}
3980
#endif
-
 
Line 3981... Line 3980...
3981
 
3980
 
3982
/* Program iCLKIP clock to the desired frequency */
3981
/* Program iCLKIP clock to the desired frequency */
3983
static void lpt_program_iclkip(struct drm_crtc *crtc)
3982
static void lpt_program_iclkip(struct drm_crtc *crtc)
3984
{
3983
{
Line 4849... Line 4848...
4849
		i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4848
		i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4850
				  plane->frontbuffer_bit);
4849
				  plane->frontbuffer_bit);
4851
		mutex_unlock(&dev->struct_mutex);
4850
		mutex_unlock(&dev->struct_mutex);
4852
	}
4851
	}
Line -... Line 4852...
-
 
4852
 
-
 
4853
	if (atomic->wait_for_flips)
-
 
4854
		intel_crtc_wait_for_pending_flips(&crtc->base);
4853
 
4855
 
4854
	if (atomic->disable_fbc)
4856
	if (atomic->disable_fbc)
Line 4855... Line 4857...
4855
		intel_fbc_disable_crtc(crtc);
4857
		intel_fbc_disable_crtc(crtc);
4856
 
4858
 
Line 4881... Line 4883...
4881
	/*
4883
	/*
4882
	 * FIXME: Once we grow proper nuclear flip support out of this we need
4884
	 * FIXME: Once we grow proper nuclear flip support out of this we need
4883
	 * to compute the mask of flip planes precisely. For the time being
4885
	 * to compute the mask of flip planes precisely. For the time being
4884
	 * consider this a flip to a NULL plane.
4886
	 * consider this a flip to a NULL plane.
4885
	 */
4887
	 */
4886
//	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4888
	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4887
}
4889
}
Line 4888... Line 4890...
4888
 
4890
 
4889
static void ironlake_crtc_enable(struct drm_crtc *crtc)
4891
static void ironlake_crtc_enable(struct drm_crtc *crtc)
4890
{
4892
{
Line 6318... Line 6320...
6318
 
6320
 
6319
	if (!intel_crtc->active)
6321
	if (!intel_crtc->active)
Line 6320... Line 6322...
6320
		return;
6322
		return;
-
 
6323
 
6321
 
6324
	if (to_intel_plane_state(crtc->primary->state)->visible) {
Line 6322... Line 6325...
6322
	if (to_intel_plane_state(crtc->primary->state)->visible) {
6325
		intel_crtc_wait_for_pending_flips(crtc);
6323
		intel_pre_disable_primary(crtc);
6326
		intel_pre_disable_primary(crtc);
6324
 
6327
 
Line 10908... Line 10911...
10908
	smp_wmb();
10911
	smp_wmb();
10909
	atomic_set(&work->pending, INTEL_FLIP_PENDING);
10912
	atomic_set(&work->pending, INTEL_FLIP_PENDING);
10910
	/* and that it is marked active as soon as the irq could fire. */
10913
	/* and that it is marked active as soon as the irq could fire. */
10911
	smp_wmb();
10914
	smp_wmb();
10912
}
10915
}
10913
#if 0
10916
 
10914
static int intel_gen2_queue_flip(struct drm_device *dev,
10917
static int intel_gen2_queue_flip(struct drm_device *dev,
10915
				 struct drm_crtc *crtc,
10918
				 struct drm_crtc *crtc,
10916
				 struct drm_framebuffer *fb,
10919
				 struct drm_framebuffer *fb,
10917
				 struct drm_i915_gem_object *obj,
10920
				 struct drm_i915_gem_object *obj,
10918
				 struct drm_i915_gem_request *req,
10921
				 struct drm_i915_gem_request *req,
Line 11371... Line 11374...
11371
	struct drm_i915_private *dev_priv = dev->dev_private;
11374
	struct drm_i915_private *dev_priv = dev->dev_private;
11372
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11375
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11373
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11376
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11374
	struct intel_unpin_work *work;
11377
	struct intel_unpin_work *work;
Line 11375... Line -...
11375
 
-
 
11376
	WARN_ON(!in_interrupt());
-
 
11377
 
11378
 
11378
	if (crtc == NULL)
11379
	if (crtc == NULL)
Line 11379... Line 11380...
11379
		return;
11380
		return;
11380
 
11381
 
Line 11389... Line 11390...
11389
	if (work != NULL &&
11390
	if (work != NULL &&
11390
	    drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11391
	    drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11391
		intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11392
		intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11392
	spin_unlock(&dev->event_lock);
11393
	spin_unlock(&dev->event_lock);
11393
}
11394
}
11394
#endif
11395
 
11395
static int intel_crtc_page_flip(struct drm_crtc *crtc,
11396
static int intel_crtc_page_flip(struct drm_crtc *crtc,
11396
				struct drm_framebuffer *fb,
11397
				struct drm_framebuffer *fb,
11397
				struct drm_pending_vblank_event *event,
11398
				struct drm_pending_vblank_event *event,
11398
				uint32_t page_flip_flags)
11399
				uint32_t page_flip_flags)
11399
{
11400
{
Line 11439... Line 11440...
11439
		return -ENOMEM;
11440
		return -ENOMEM;
Line 11440... Line 11441...
11440
 
11441
 
11441
	work->event = event;
11442
	work->event = event;
11442
	work->crtc = crtc;
11443
	work->crtc = crtc;
11443
	work->old_fb = old_fb;
11444
	work->old_fb = old_fb;
Line 11444... Line 11445...
11444
//	INIT_WORK(&work->work, intel_unpin_work_fn);
11445
	INIT_WORK(&work->work, intel_unpin_work_fn);
11445
 
11446
 
11446
	ret = drm_crtc_vblank_get(crtc);
11447
	ret = drm_crtc_vblank_get(crtc);
Line 11466... Line 11467...
11466
		}
11467
		}
11467
	}
11468
	}
11468
	intel_crtc->unpin_work = work;
11469
	intel_crtc->unpin_work = work;
11469
	spin_unlock_irq(&dev->event_lock);
11470
	spin_unlock_irq(&dev->event_lock);
Line 11470... Line 11471...
11470
 
11471
 
11471
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11472
//   if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
Line 11472... Line 11473...
11472
		flush_workqueue(dev_priv->wq);
11473
//       flush_workqueue(dev_priv->wq);
11473
 
11474
 
11474
	/* Reference the objects for the scheduled work. */
11475
	/* Reference the objects for the scheduled work. */
Line 11925... Line 11926...
11925
		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11926
		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11926
			      bpp, connector->base.display_info.bpc*3);
11927
			      bpp, connector->base.display_info.bpc*3);
11927
		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11928
		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11928
	}
11929
	}
Line 11929... Line 11930...
11929
 
11930
 
11930
	/* Clamp bpp to 8 on screens without EDID 1.4 */
11931
	/* Clamp bpp to default limit on screens without EDID 1.4 */
-
 
11932
	if (connector->base.display_info.bpc == 0) {
-
 
11933
		int type = connector->base.connector_type;
-
 
11934
		int clamp_bpp = 24;
-
 
11935
 
-
 
11936
		/* Fall back to 18 bpp when DP sink capability is unknown. */
-
 
11937
		if (type == DRM_MODE_CONNECTOR_DisplayPort ||
-
 
11938
		    type == DRM_MODE_CONNECTOR_eDP)
-
 
11939
			clamp_bpp = 18;
-
 
11940
 
11931
	if (connector->base.display_info.bpc == 0 && bpp > 24) {
11941
		if (bpp > clamp_bpp) {
11932
		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11942
			DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11933
			      bpp);
11943
				      bpp, clamp_bpp);
-
 
11944
			pipe_config->pipe_bpp = clamp_bpp;
11934
		pipe_config->pipe_bpp = 24;
11945
		}
11935
	}
11946
	}
Line 11936... Line 11947...
11936
}
11947
}
11937
 
11948
 
Line 13315... Line 13326...
13315
 
13326
 
13316
static const struct drm_crtc_funcs intel_crtc_funcs = {
13327
static const struct drm_crtc_funcs intel_crtc_funcs = {
13317
	.gamma_set = intel_crtc_gamma_set,
13328
	.gamma_set = intel_crtc_gamma_set,
13318
	.set_config = drm_atomic_helper_set_config,
13329
	.set_config = drm_atomic_helper_set_config,
13319
	.destroy = intel_crtc_destroy,
13330
	.destroy = intel_crtc_destroy,
13320
//	.page_flip = intel_crtc_page_flip,
13331
	.page_flip = intel_crtc_page_flip,
13321
	.atomic_duplicate_state = intel_crtc_duplicate_state,
13332
	.atomic_duplicate_state = intel_crtc_duplicate_state,
13322
	.atomic_destroy_state = intel_crtc_destroy_state,
13333
	.atomic_destroy_state = intel_crtc_destroy_state,
Line 13323... Line 13334...
13323
};
13334
};
Line 13532... Line 13543...
13532
	struct drm_framebuffer *fb = state->base.fb;
13543
	struct drm_framebuffer *fb = state->base.fb;
13533
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13544
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13534
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13545
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13535
	bool can_position = false;
13546
	bool can_position = false;
Line -... Line 13547...
-
 
13547
 
13536
 
13548
	if (INTEL_INFO(plane->dev)->gen >= 9) {
13537
	/* use scaler when colorkey is not required */
-
 
13538
	if (INTEL_INFO(plane->dev)->gen >= 9 &&
13549
	/* use scaler when colorkey is not required */
13539
	    state->ckey.flags == I915_SET_COLORKEY_NONE) {
13550
		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13540
		min_scale = 1;
13551
		min_scale = 1;
-
 
13552
		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13541
		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13553
		}
13542
		can_position = true;
13554
		can_position = true;
Line 13543... Line 13555...
13543
	}
13555
	}
13544
 
13556
 
Line 14626... Line 14638...
14626
			broxton_modeset_commit_cdclk;
14638
			broxton_modeset_commit_cdclk;
14627
		dev_priv->display.modeset_calc_cdclk =
14639
		dev_priv->display.modeset_calc_cdclk =
14628
			broxton_modeset_calc_cdclk;
14640
			broxton_modeset_calc_cdclk;
14629
	}
14641
	}
Line -... Line 14642...
-
 
14642
 
-
 
14643
	switch (INTEL_INFO(dev)->gen) {
-
 
14644
	case 2:
-
 
14645
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
Line -... Line 14646...
-
 
14646
		break;
-
 
14647
 
-
 
14648
	case 3:
Line -... Line 14649...
-
 
14649
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
-
 
14650
		break;
-
 
14651
 
-
 
14652
	case 4:
Line -... Line 14653...
-
 
14653
	case 5:
-
 
14654
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
-
 
14655
		break;
-
 
14656
 
-
 
14657
	case 6:
-
 
14658
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
-
 
14659
		break;
-
 
14660
	case 7:
-
 
14661
	case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
-
 
14662
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
-
 
14663
		break;
-
 
14664
	case 9:
14630
 
14665
		/* Drop through - unsupported since execlist only. */
Line 14631... Line 14666...
14631
 
14666
	default:
14632
 
14667
		/* Default just returns -ENODEV to indicate unsupported */
Line 14633... Line 14668...
14633
 
14668
		dev_priv->display.queue_flip = intel_default_queue_flip;