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Rev 5367 Rev 6084
Line 35... Line 35...
35
#include 
35
#include 
36
#include "intel_drv.h"
36
#include "intel_drv.h"
37
#include 
37
#include 
38
#include "i915_drv.h"
38
#include "i915_drv.h"
39
#include "i915_trace.h"
39
#include "i915_trace.h"
-
 
40
#include 
-
 
41
#include 
40
#include 
42
#include 
41
#include 
43
#include 
42
#include 
44
#include 
43
#include 
45
#include 
44
#include 
46
#include 
Line 45... Line -...
45
 
-
 
46
/* Primary plane formats supported by all gen */
-
 
47
#define COMMON_PRIMARY_FORMATS \
-
 
48
	DRM_FORMAT_C8, \
-
 
49
	DRM_FORMAT_RGB565, \
-
 
50
	DRM_FORMAT_XRGB8888, \
-
 
51
	DRM_FORMAT_ARGB8888
-
 
52
 
47
 
53
/* Primary plane formats for gen <= 3 */
48
/* Primary plane formats for gen <= 3 */
54
static const uint32_t intel_primary_formats_gen2[] = {
49
static const uint32_t i8xx_primary_formats[] = {
-
 
50
	DRM_FORMAT_C8,
55
	COMMON_PRIMARY_FORMATS,
51
	DRM_FORMAT_RGB565,
56
	DRM_FORMAT_XRGB1555,
52
	DRM_FORMAT_XRGB1555,
57
	DRM_FORMAT_ARGB1555,
53
	DRM_FORMAT_XRGB8888,
Line 58... Line 54...
58
};
54
};
59
 
55
 
60
/* Primary plane formats for gen >= 4 */
56
/* Primary plane formats for gen >= 4 */
-
 
57
static const uint32_t i965_primary_formats[] = {
-
 
58
	DRM_FORMAT_C8,
61
static const uint32_t intel_primary_formats_gen4[] = {
59
	DRM_FORMAT_RGB565,
-
 
60
	DRM_FORMAT_XRGB8888,
-
 
61
	DRM_FORMAT_XBGR8888,
-
 
62
	DRM_FORMAT_XRGB2101010,
-
 
63
	DRM_FORMAT_XBGR2101010,
-
 
64
};
-
 
65
 
-
 
66
static const uint32_t skl_primary_formats[] = {
-
 
67
	DRM_FORMAT_C8,
-
 
68
	DRM_FORMAT_RGB565,
-
 
69
	DRM_FORMAT_XRGB8888,
62
	COMMON_PRIMARY_FORMATS, \
70
	DRM_FORMAT_XBGR8888,
63
	DRM_FORMAT_XBGR8888,
71
	DRM_FORMAT_ARGB8888,
64
	DRM_FORMAT_ABGR8888,
-
 
65
	DRM_FORMAT_XRGB2101010,
72
	DRM_FORMAT_ABGR8888,
-
 
73
	DRM_FORMAT_XRGB2101010,
-
 
74
	DRM_FORMAT_XBGR2101010,
-
 
75
	DRM_FORMAT_YUYV,
66
	DRM_FORMAT_ARGB2101010,
76
	DRM_FORMAT_YVYU,
67
	DRM_FORMAT_XBGR2101010,
77
	DRM_FORMAT_UYVY,
Line 68... Line 78...
68
	DRM_FORMAT_ABGR2101010,
78
	DRM_FORMAT_VYUY,
69
};
79
};
70
 
80
 
71
/* Cursor formats */
81
/* Cursor formats */
Line 72... Line 82...
72
static const uint32_t intel_cursor_formats[] = {
82
static const uint32_t intel_cursor_formats[] = {
Line 73... Line 83...
73
	DRM_FORMAT_ARGB8888,
83
	DRM_FORMAT_ARGB8888,
74
};
84
};
75
 
85
 
76
void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
86
void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Line 77... Line -...
77
 
-
 
78
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
-
 
79
				struct intel_crtc_config *pipe_config);
87
 
80
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
88
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81
				    struct intel_crtc_config *pipe_config);
89
				struct intel_crtc_state *pipe_config);
82
 
90
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83
static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
91
				   struct intel_crtc_state *pipe_config);
Line 93... Line 101...
93
					 struct intel_link_m_n *m2_n2);
101
					 struct intel_link_m_n *m2_n2);
94
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
102
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95
static void haswell_set_pipeconf(struct drm_crtc *crtc);
103
static void haswell_set_pipeconf(struct drm_crtc *crtc);
96
static void intel_set_pipe_csc(struct drm_crtc *crtc);
104
static void intel_set_pipe_csc(struct drm_crtc *crtc);
97
static void vlv_prepare_pll(struct intel_crtc *crtc,
105
static void vlv_prepare_pll(struct intel_crtc *crtc,
98
			    const struct intel_crtc_config *pipe_config);
106
			    const struct intel_crtc_state *pipe_config);
99
static void chv_prepare_pll(struct intel_crtc *crtc,
107
static void chv_prepare_pll(struct intel_crtc *crtc,
100
			    const struct intel_crtc_config *pipe_config);
108
			    const struct intel_crtc_state *pipe_config);
101
 
-
 
-
 
109
static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
-
 
110
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
102
static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
111
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
103
{
-
 
104
	if (!connector->mst_port)
112
	struct intel_crtc_state *crtc_state);
-
 
113
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
105
		return connector->encoder;
114
			   int num_connectors);
106
	else
-
 
-
 
115
static void skylake_pfit_enable(struct intel_crtc *crtc);
-
 
116
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
-
 
117
static void ironlake_pfit_enable(struct intel_crtc *crtc);
-
 
118
static void intel_modeset_setup_hw_state(struct drm_device *dev);
107
		return &connector->mst_port->mst_encoders[pipe]->base;
119
static void intel_pre_disable_primary(struct drm_crtc *crtc);
108
}
-
 
Line 109... Line 120...
109
 
120
 
110
typedef struct {
121
typedef struct {
111
    int min, max;
122
	int	min, max;
Line 120... Line 131...
120
struct intel_limit {
131
struct intel_limit {
121
    intel_range_t   dot, vco, n, m, m1, m2, p, p1;
132
	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
122
    intel_p2_t      p2;
133
	intel_p2_t	    p2;
123
};
134
};
Line -... Line 135...
-
 
135
 
-
 
136
/* returns HPLL frequency in kHz */
-
 
137
static int valleyview_get_vco(struct drm_i915_private *dev_priv)
-
 
138
{
-
 
139
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
-
 
140
 
-
 
141
	/* Obtain SKU information */
-
 
142
	mutex_lock(&dev_priv->sb_lock);
-
 
143
	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
-
 
144
		CCK_FUSE_HPLL_FREQ_MASK;
-
 
145
	mutex_unlock(&dev_priv->sb_lock);
-
 
146
 
-
 
147
	return vco_freq[hpll_freq] * 1000;
-
 
148
}
-
 
149
 
-
 
150
static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
-
 
151
				  const char *name, u32 reg)
-
 
152
{
-
 
153
	u32 val;
-
 
154
	int divider;
-
 
155
 
-
 
156
	if (dev_priv->hpll_freq == 0)
-
 
157
		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
-
 
158
 
-
 
159
	mutex_lock(&dev_priv->sb_lock);
-
 
160
	val = vlv_cck_read(dev_priv, reg);
-
 
161
	mutex_unlock(&dev_priv->sb_lock);
-
 
162
 
-
 
163
	divider = val & CCK_FREQUENCY_VALUES;
-
 
164
 
-
 
165
	WARN((val & CCK_FREQUENCY_STATUS) !=
-
 
166
	     (divider << CCK_FREQUENCY_STATUS_SHIFT),
-
 
167
	     "%s change in progress\n", name);
-
 
168
 
-
 
169
	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
-
 
170
}
124
 
171
 
125
int
172
int
126
intel_pch_rawclk(struct drm_device *dev)
173
intel_pch_rawclk(struct drm_device *dev)
127
{
174
{
Line 128... Line 175...
128
	struct drm_i915_private *dev_priv = dev->dev_private;
175
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 129... Line 176...
129
 
176
 
130
	WARN_ON(!HAS_PCH_SPLIT(dev));
177
	WARN_ON(!HAS_PCH_SPLIT(dev));
Line -... Line 178...
-
 
178
 
-
 
179
	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
-
 
180
}
-
 
181
 
-
 
182
/* hrawclock is 1/4 the FSB frequency */
-
 
183
int intel_hrawclk(struct drm_device *dev)
-
 
184
{
-
 
185
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
186
	uint32_t clkcfg;
-
 
187
 
-
 
188
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-
 
189
	if (IS_VALLEYVIEW(dev))
-
 
190
		return 200;
-
 
191
 
-
 
192
	clkcfg = I915_READ(CLKCFG);
-
 
193
	switch (clkcfg & CLKCFG_FSB_MASK) {
-
 
194
	case CLKCFG_FSB_400:
-
 
195
		return 100;
-
 
196
	case CLKCFG_FSB_533:
-
 
197
		return 133;
-
 
198
	case CLKCFG_FSB_667:
-
 
199
		return 166;
-
 
200
	case CLKCFG_FSB_800:
-
 
201
		return 200;
-
 
202
	case CLKCFG_FSB_1067:
-
 
203
		return 266;
-
 
204
	case CLKCFG_FSB_1333:
-
 
205
		return 333;
-
 
206
	/* these two are just a guess; one of them might be right */
-
 
207
	case CLKCFG_FSB_1600:
-
 
208
	case CLKCFG_FSB_1600_ALT:
-
 
209
		return 400;
-
 
210
	default:
-
 
211
		return 133;
-
 
212
	}
-
 
213
}
-
 
214
 
-
 
215
static void intel_update_czclk(struct drm_i915_private *dev_priv)
-
 
216
{
-
 
217
	if (!IS_VALLEYVIEW(dev_priv))
-
 
218
		return;
-
 
219
 
-
 
220
	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
-
 
221
						      CCK_CZ_CLOCK_CONTROL);
131
 
222
 
132
	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
223
	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
133
}
224
}
134
 
225
 
135
static inline u32 /* units of 100MHz */
226
static inline u32 /* units of 100MHz */
Line 385... Line 476...
385
	 * since those are the strictest limits we have.  The fast
476
	 * since those are the strictest limits we have.  The fast
386
	 * clock and actual rate limits are more relaxed, so checking
477
	 * clock and actual rate limits are more relaxed, so checking
387
	 * them would make no difference.
478
	 * them would make no difference.
388
	 */
479
	 */
389
	.dot = { .min = 25000 * 5, .max = 540000 * 5},
480
	.dot = { .min = 25000 * 5, .max = 540000 * 5},
390
	.vco = { .min = 4860000, .max = 6700000 },
481
	.vco = { .min = 4800000, .max = 6480000 },
391
	.n = { .min = 1, .max = 1 },
482
	.n = { .min = 1, .max = 1 },
392
	.m1 = { .min = 2, .max = 2 },
483
	.m1 = { .min = 2, .max = 2 },
393
	.m2 = { .min = 24 << 22, .max = 175 << 22 },
484
	.m2 = { .min = 24 << 22, .max = 175 << 22 },
394
	.p1 = { .min = 2, .max = 4 },
485
	.p1 = { .min = 2, .max = 4 },
395
	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
486
	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
396
};
487
};
Line 397... Line 488...
397
 
488
 
-
 
489
static const intel_limit_t intel_limits_bxt = {
-
 
490
	/* FIXME: find real dot limits */
-
 
491
	.dot = { .min = 0, .max = INT_MAX },
-
 
492
	.vco = { .min = 4800000, .max = 6700000 },
-
 
493
	.n = { .min = 1, .max = 1 },
-
 
494
	.m1 = { .min = 2, .max = 2 },
-
 
495
	/* FIXME: find real m2 limits */
-
 
496
	.m2 = { .min = 2 << 22, .max = 255 << 22 },
-
 
497
	.p1 = { .min = 2, .max = 4 },
-
 
498
	.p2 = { .p2_slow = 1, .p2_fast = 20 },
-
 
499
};
-
 
500
 
-
 
501
static bool
398
static void vlv_clock(int refclk, intel_clock_t *clock)
502
needs_modeset(struct drm_crtc_state *state)
399
{
-
 
400
	clock->m = clock->m1 * clock->m2;
-
 
401
	clock->p = clock->p1 * clock->p2;
503
{
402
	if (WARN_ON(clock->n == 0 || clock->p == 0))
-
 
403
		return;
-
 
404
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
-
 
405
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
504
	return drm_atomic_crtc_needs_modeset(state);
Line 406... Line 505...
406
}
505
}
407
 
506
 
408
/**
507
/**
Line 424... Line 523...
424
 * Returns whether any output on the specified pipe will have the specified
523
 * Returns whether any output on the specified pipe will have the specified
425
 * type after a staged modeset is complete, i.e., the same as
524
 * type after a staged modeset is complete, i.e., the same as
426
 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525
 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427
 * encoder->crtc.
526
 * encoder->crtc.
428
 */
527
 */
429
static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
528
static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
-
 
529
				      int type)
430
{
530
{
431
	struct drm_device *dev = crtc->base.dev;
531
	struct drm_atomic_state *state = crtc_state->base.state;
-
 
532
	struct drm_connector *connector;
-
 
533
	struct drm_connector_state *connector_state;
432
	struct intel_encoder *encoder;
534
	struct intel_encoder *encoder;
-
 
535
	int i, num_connectors = 0;
-
 
536
 
-
 
537
	for_each_connector_in_state(state, connector, connector_state, i) {
-
 
538
		if (connector_state->crtc != crtc_state->base.crtc)
-
 
539
			continue;
Line -... Line 540...
-
 
540
 
-
 
541
		num_connectors++;
433
 
542
 
434
	for_each_intel_encoder(dev, encoder)
543
		encoder = to_intel_encoder(connector_state->best_encoder);
435
		if (encoder->new_crtc == crtc && encoder->type == type)
544
		if (encoder->type == type)
-
 
545
			return true;
-
 
546
	}
-
 
547
 
Line 436... Line 548...
436
			return true;
548
	WARN_ON(num_connectors == 0);
437
 
549
 
Line 438... Line 550...
438
	return false;
550
	return false;
439
}
551
}
440
 
552
 
441
static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
553
static const intel_limit_t *
442
						int refclk)
554
intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
Line 443... Line 555...
443
{
555
{
444
	struct drm_device *dev = crtc->base.dev;
556
	struct drm_device *dev = crtc_state->base.crtc->dev;
445
	const intel_limit_t *limit;
557
	const intel_limit_t *limit;
446
 
558
 
447
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
559
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
448
		if (intel_is_dual_link_lvds(dev)) {
560
		if (intel_is_dual_link_lvds(dev)) {
Line 460... Line 572...
460
		limit = &intel_limits_ironlake_dac;
572
		limit = &intel_limits_ironlake_dac;
Line 461... Line 573...
461
 
573
 
462
	return limit;
574
	return limit;
Line -... Line 575...
-
 
575
}
463
}
576
 
464
 
577
static const intel_limit_t *
465
static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
578
intel_g4x_limit(struct intel_crtc_state *crtc_state)
466
{
579
{
Line 467... Line 580...
467
	struct drm_device *dev = crtc->base.dev;
580
	struct drm_device *dev = crtc_state->base.crtc->dev;
468
	const intel_limit_t *limit;
581
	const intel_limit_t *limit;
469
 
582
 
470
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
583
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
471
		if (intel_is_dual_link_lvds(dev))
584
		if (intel_is_dual_link_lvds(dev))
472
			limit = &intel_limits_g4x_dual_channel_lvds;
585
			limit = &intel_limits_g4x_dual_channel_lvds;
473
		else
586
		else
474
			limit = &intel_limits_g4x_single_channel_lvds;
587
			limit = &intel_limits_g4x_single_channel_lvds;
475
	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
588
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
476
		   intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
589
		   intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
477
		limit = &intel_limits_g4x_hdmi;
590
		limit = &intel_limits_g4x_hdmi;
478
	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
591
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
Line 479... Line 592...
479
		limit = &intel_limits_g4x_sdvo;
592
		limit = &intel_limits_g4x_sdvo;
480
	} else /* The option is for other outputs */
593
	} else /* The option is for other outputs */
Line -... Line 594...
-
 
594
		limit = &intel_limits_i9xx_sdvo;
481
		limit = &intel_limits_i9xx_sdvo;
595
 
482
 
596
	return limit;
483
	return limit;
597
}
484
}
598
 
Line -... Line 599...
-
 
599
static const intel_limit_t *
-
 
600
intel_limit(struct intel_crtc_state *crtc_state, int refclk)
485
 
601
{
486
static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
602
	struct drm_device *dev = crtc_state->base.crtc->dev;
487
{
603
	const intel_limit_t *limit;
488
	struct drm_device *dev = crtc->base.dev;
604
 
489
	const intel_limit_t *limit;
605
	if (IS_BROXTON(dev))
490
 
606
		limit = &intel_limits_bxt;
491
	if (HAS_PCH_SPLIT(dev))
607
	else if (HAS_PCH_SPLIT(dev))
492
		limit = intel_ironlake_limit(crtc, refclk);
608
		limit = intel_ironlake_limit(crtc_state, refclk);
493
	else if (IS_G4X(dev)) {
609
	else if (IS_G4X(dev)) {
494
		limit = intel_g4x_limit(crtc);
610
		limit = intel_g4x_limit(crtc_state);
495
	} else if (IS_PINEVIEW(dev)) {
611
	} else if (IS_PINEVIEW(dev)) {
496
		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
612
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
497
			limit = &intel_limits_pineview_lvds;
613
			limit = &intel_limits_pineview_lvds;
498
		else
614
		else
499
			limit = &intel_limits_pineview_sdvo;
615
			limit = &intel_limits_pineview_sdvo;
500
	} else if (IS_CHERRYVIEW(dev)) {
616
	} else if (IS_CHERRYVIEW(dev)) {
501
		limit = &intel_limits_chv;
617
		limit = &intel_limits_chv;
502
	} else if (IS_VALLEYVIEW(dev)) {
618
	} else if (IS_VALLEYVIEW(dev)) {
503
		limit = &intel_limits_vlv;
619
		limit = &intel_limits_vlv;
504
	} else if (!IS_GEN2(dev)) {
620
	} else if (!IS_GEN2(dev)) {
505
		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
621
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
506
			limit = &intel_limits_i9xx_lvds;
622
			limit = &intel_limits_i9xx_lvds;
507
		else
623
		else
508
			limit = &intel_limits_i9xx_sdvo;
624
			limit = &intel_limits_i9xx_sdvo;
509
	} else {
625
	} else {
510
		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
626
		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
511
			limit = &intel_limits_i8xx_lvds;
627
			limit = &intel_limits_i8xx_lvds;
512
		else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
628
		else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
Line -... Line 629...
-
 
629
			limit = &intel_limits_i8xx_dvo;
-
 
630
		else
-
 
631
			limit = &intel_limits_i8xx_dac;
-
 
632
	}
-
 
633
	return limit;
-
 
634
}
-
 
635
 
-
 
636
/*
513
			limit = &intel_limits_i8xx_dvo;
637
 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
514
		else
638
 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
515
			limit = &intel_limits_i8xx_dac;
639
 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
516
	}
640
 * The helpers' return value is the rate of the clock that is fed to the
517
	return limit;
641
 * display engine's pipe which can be the above fast dot clock rate or a
518
}
642
 * divided-down version of it.
519
 
643
 */
520
/* m1 is reserved as 0 in Pineview, n is a ring counter */
644
/* m1 is reserved as 0 in Pineview, n is a ring counter */
521
static void pineview_clock(int refclk, intel_clock_t *clock)
645
static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
-
 
646
{
-
 
647
	clock->m = clock->m2 + 2;
522
{
648
	clock->p = clock->p1 * clock->p2;
Line 523... Line 649...
523
	clock->m = clock->m2 + 2;
649
	if (WARN_ON(clock->n == 0 || clock->p == 0))
524
	clock->p = clock->p1 * clock->p2;
650
		return 0;
525
	if (WARN_ON(clock->n == 0 || clock->p == 0))
651
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
526
		return;
652
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Line 527... Line 653...
527
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
653
 
528
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
654
	return clock->dot;
529
}
655
}
530
 
656
 
531
static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657
static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532
{
658
{
533
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534
}
660
}
-
 
661
 
-
 
662
static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
535
 
663
{
Line 536... Line 664...
536
static void i9xx_clock(int refclk, intel_clock_t *clock)
664
	clock->m = i9xx_dpll_compute_m(clock);
537
{
665
	clock->p = clock->p1 * clock->p2;
538
	clock->m = i9xx_dpll_compute_m(clock);
666
	if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
539
	clock->p = clock->p1 * clock->p2;
667
		return 0;
540
	if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
668
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
541
		return;
669
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
-
 
670
 
-
 
671
	return clock->dot;
-
 
672
}
-
 
673
 
-
 
674
static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
-
 
675
{
-
 
676
	clock->m = clock->m1 * clock->m2;
-
 
677
	clock->p = clock->p1 * clock->p2;
-
 
678
	if (WARN_ON(clock->n == 0 || clock->p == 0))
-
 
679
		return 0;
-
 
680
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
-
 
681
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
542
	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
682
 
543
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
683
	return clock->dot / 5;
544
}
684
}
-
 
685
 
-
 
686
int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
545
 
687
{
Line 546... Line 688...
546
static void chv_clock(int refclk, intel_clock_t *clock)
688
	clock->m = clock->m1 * clock->m2;
547
{
689
	clock->p = clock->p1 * clock->p2;
548
	clock->m = clock->m1 * clock->m2;
690
	if (WARN_ON(clock->n == 0 || clock->p == 0))
Line 571... Line 713...
571
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
713
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
572
		INTELPllInvalid("m2 out of range\n");
714
		INTELPllInvalid("m2 out of range\n");
573
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
715
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
574
		INTELPllInvalid("m1 out of range\n");
716
		INTELPllInvalid("m1 out of range\n");
Line 575... Line 717...
575
 
717
 
576
	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
718
	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
577
		if (clock->m1 <= clock->m2)
719
		if (clock->m1 <= clock->m2)
Line 578... Line 720...
578
		INTELPllInvalid("m1 <= m2\n");
720
			INTELPllInvalid("m1 <= m2\n");
579
 
721
 
580
	if (!IS_VALLEYVIEW(dev)) {
722
	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
581
		if (clock->p < limit->p.min || limit->p.max < clock->p)
723
		if (clock->p < limit->p.min || limit->p.max < clock->p)
582
			INTELPllInvalid("p out of range\n");
724
			INTELPllInvalid("p out of range\n");
583
	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
725
		if (clock->m < limit->m.min || limit->m.max < clock->m)
Line 593... Line 735...
593
		INTELPllInvalid("dot out of range\n");
735
		INTELPllInvalid("dot out of range\n");
Line 594... Line 736...
594
 
736
 
595
	return true;
737
	return true;
Line 596... Line 738...
596
}
738
}
597
 
739
 
598
static bool
740
static int
599
i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
741
i9xx_select_p2_div(const intel_limit_t *limit,
600
		    int target, int refclk, intel_clock_t *match_clock,
742
		   const struct intel_crtc_state *crtc_state,
601
		    intel_clock_t *best_clock)
743
		   int target)
602
{
-
 
603
	struct drm_device *dev = crtc->base.dev;
-
 
Line 604... Line 744...
604
	intel_clock_t clock;
744
{
605
	int err = target;
745
	struct drm_device *dev = crtc_state->base.crtc->dev;
606
 
746
 
607
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
747
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
608
		/*
748
		/*
609
		 * For LVDS just rely on its current settings for dual-channel.
749
		 * For LVDS just rely on its current settings for dual-channel.
610
		 * We haven't figured out how to reliably set up different
750
		 * We haven't figured out how to reliably set up different
611
		 * single/dual channel state, if we even can.
751
		 * single/dual channel state, if we even can.
612
		 */
752
		 */
613
		if (intel_is_dual_link_lvds(dev))
753
		if (intel_is_dual_link_lvds(dev))
614
			clock.p2 = limit->p2.p2_fast;
754
			return limit->p2.p2_fast;
615
		else
755
		else
616
			clock.p2 = limit->p2.p2_slow;
756
			return limit->p2.p2_slow;
617
	} else {
757
	} else {
618
		if (target < limit->p2.dot_limit)
758
		if (target < limit->p2.dot_limit)
-
 
759
			return limit->p2.p2_slow;
619
			clock.p2 = limit->p2.p2_slow;
760
		else
Line -... Line 761...
-
 
761
			return limit->p2.p2_fast;
-
 
762
	}
-
 
763
}
-
 
764
 
-
 
765
static bool
-
 
766
i9xx_find_best_dpll(const intel_limit_t *limit,
-
 
767
		    struct intel_crtc_state *crtc_state,
-
 
768
		    int target, int refclk, intel_clock_t *match_clock,
-
 
769
		    intel_clock_t *best_clock)
-
 
770
{
620
		else
771
	struct drm_device *dev = crtc_state->base.crtc->dev;
Line -... Line 772...
-
 
772
	intel_clock_t clock;
-
 
773
	int err = target;
621
			clock.p2 = limit->p2.p2_fast;
774
 
622
	}
775
	memset(best_clock, 0, sizeof(*best_clock));
623
 
776
 
624
	memset(best_clock, 0, sizeof(*best_clock));
777
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
625
 
778
 
Line 633... Line 786...
633
			     clock.n <= limit->n.max; clock.n++) {
786
			     clock.n <= limit->n.max; clock.n++) {
634
				for (clock.p1 = limit->p1.min;
787
				for (clock.p1 = limit->p1.min;
635
					clock.p1 <= limit->p1.max; clock.p1++) {
788
					clock.p1 <= limit->p1.max; clock.p1++) {
636
					int this_err;
789
					int this_err;
Line 637... Line 790...
637
 
790
 
638
					i9xx_clock(refclk, &clock);
791
					i9xx_calc_dpll_params(refclk, &clock);
639
					if (!intel_PLL_is_valid(dev, limit,
792
					if (!intel_PLL_is_valid(dev, limit,
640
								&clock))
793
								&clock))
641
						continue;
794
						continue;
642
					if (match_clock &&
795
					if (match_clock &&
Line 655... Line 808...
655
 
808
 
656
	return (err != target);
809
	return (err != target);
Line 657... Line 810...
657
}
810
}
658
 
811
 
-
 
812
static bool
659
static bool
813
pnv_find_best_dpll(const intel_limit_t *limit,
660
pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
814
		   struct intel_crtc_state *crtc_state,
661
		   int target, int refclk, intel_clock_t *match_clock,
815
		   int target, int refclk, intel_clock_t *match_clock,
662
		   intel_clock_t *best_clock)
816
		   intel_clock_t *best_clock)
663
{
817
{
664
	struct drm_device *dev = crtc->base.dev;
818
	struct drm_device *dev = crtc_state->base.crtc->dev;
Line 665... Line -...
665
	intel_clock_t clock;
-
 
666
	int err = target;
-
 
667
 
-
 
668
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
-
 
669
		/*
-
 
670
		 * For LVDS just rely on its current settings for dual-channel.
-
 
671
		 * We haven't figured out how to reliably set up different
-
 
672
		 * single/dual channel state, if we even can.
-
 
673
		 */
-
 
674
		if (intel_is_dual_link_lvds(dev))
-
 
675
			clock.p2 = limit->p2.p2_fast;
-
 
676
		else
-
 
677
			clock.p2 = limit->p2.p2_slow;
-
 
678
	} else {
-
 
679
		if (target < limit->p2.dot_limit)
-
 
680
			clock.p2 = limit->p2.p2_slow;
-
 
681
		else
-
 
682
			clock.p2 = limit->p2.p2_fast;
819
	intel_clock_t clock;
Line -... Line 820...
-
 
820
	int err = target;
-
 
821
 
683
	}
822
	memset(best_clock, 0, sizeof(*best_clock));
684
 
823
 
685
	memset(best_clock, 0, sizeof(*best_clock));
824
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
 
825
 
687
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688
	     clock.m1++) {
827
	     clock.m1++) {
689
		for (clock.m2 = limit->m2.min;
828
		for (clock.m2 = limit->m2.min;
690
		     clock.m2 <= limit->m2.max; clock.m2++) {
829
		     clock.m2 <= limit->m2.max; clock.m2++) {
691
			for (clock.n = limit->n.min;
830
			for (clock.n = limit->n.min;
Line 692... Line 831...
692
			     clock.n <= limit->n.max; clock.n++) {
831
			     clock.n <= limit->n.max; clock.n++) {
693
				for (clock.p1 = limit->p1.min;
832
				for (clock.p1 = limit->p1.min;
694
					clock.p1 <= limit->p1.max; clock.p1++) {
833
					clock.p1 <= limit->p1.max; clock.p1++) {
695
					int this_err;
834
					int this_err;
696
 
835
 
697
					pineview_clock(refclk, &clock);
836
					pnv_calc_dpll_params(refclk, &clock);
Line 714... Line 853...
714
 
853
 
715
	return (err != target);
854
	return (err != target);
Line 716... Line 855...
716
}
855
}
717
 
856
 
-
 
857
static bool
718
static bool
858
g4x_find_best_dpll(const intel_limit_t *limit,
719
g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
859
		   struct intel_crtc_state *crtc_state,
720
			int target, int refclk, intel_clock_t *match_clock,
860
		   int target, int refclk, intel_clock_t *match_clock,
721
			intel_clock_t *best_clock)
861
		   intel_clock_t *best_clock)
722
{
862
{
723
	struct drm_device *dev = crtc->base.dev;
863
	struct drm_device *dev = crtc_state->base.crtc->dev;
724
	intel_clock_t clock;
864
	intel_clock_t clock;
725
	int max_n;
865
	int max_n;
726
	bool found;
866
	bool found = false;
727
	/* approximately equals target * 0.00585 */
-
 
728
	int err_most = (target >> 8) + (target >> 9);
-
 
729
	found = false;
-
 
730
 
-
 
731
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
-
 
732
		if (intel_is_dual_link_lvds(dev))
-
 
733
			clock.p2 = limit->p2.p2_fast;
-
 
734
		else
-
 
735
			clock.p2 = limit->p2.p2_slow;
-
 
736
	} else {
-
 
737
		if (target < limit->p2.dot_limit)
-
 
738
			clock.p2 = limit->p2.p2_slow;
-
 
739
		else
-
 
Line 740... Line 867...
740
			clock.p2 = limit->p2.p2_fast;
867
	/* approximately equals target * 0.00585 */
-
 
868
	int err_most = (target >> 8) + (target >> 9);
-
 
869
 
-
 
870
	memset(best_clock, 0, sizeof(*best_clock));
741
	}
871
 
742
 
872
	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
743
	memset(best_clock, 0, sizeof(*best_clock));
873
 
744
	max_n = limit->n.max;
874
	max_n = limit->n.max;
745
	/* based on hardware requirement, prefer smaller n to precision */
875
	/* based on hardware requirement, prefer smaller n to precision */
Line 751... Line 881...
751
			     clock.m2 >= limit->m2.min; clock.m2--) {
881
			     clock.m2 >= limit->m2.min; clock.m2--) {
752
				for (clock.p1 = limit->p1.max;
882
				for (clock.p1 = limit->p1.max;
753
				     clock.p1 >= limit->p1.min; clock.p1--) {
883
				     clock.p1 >= limit->p1.min; clock.p1--) {
754
					int this_err;
884
					int this_err;
Line 755... Line 885...
755
 
885
 
756
					i9xx_clock(refclk, &clock);
886
					i9xx_calc_dpll_params(refclk, &clock);
757
					if (!intel_PLL_is_valid(dev, limit,
887
					if (!intel_PLL_is_valid(dev, limit,
758
								&clock))
888
								&clock))
Line 759... Line 889...
759
						continue;
889
						continue;
Line 770... Line 900...
770
		}
900
		}
771
	}
901
	}
772
	return found;
902
	return found;
773
}
903
}
Line -... Line 904...
-
 
904
 
-
 
905
/*
-
 
906
 * Check if the calculated PLL configuration is more optimal compared to the
-
 
907
 * best configuration and error found so far. Return the calculated error.
-
 
908
 */
-
 
909
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
-
 
910
			       const intel_clock_t *calculated_clock,
-
 
911
			       const intel_clock_t *best_clock,
-
 
912
			       unsigned int best_error_ppm,
-
 
913
			       unsigned int *error_ppm)
-
 
914
{
-
 
915
	/*
-
 
916
	 * For CHV ignore the error and consider only the P value.
-
 
917
	 * Prefer a bigger P value based on HW requirements.
-
 
918
	 */
-
 
919
	if (IS_CHERRYVIEW(dev)) {
-
 
920
		*error_ppm = 0;
-
 
921
 
-
 
922
		return calculated_clock->p > best_clock->p;
-
 
923
	}
-
 
924
 
-
 
925
	if (WARN_ON_ONCE(!target_freq))
-
 
926
		return false;
-
 
927
 
-
 
928
	*error_ppm = div_u64(1000000ULL *
-
 
929
				abs(target_freq - calculated_clock->dot),
-
 
930
			     target_freq);
-
 
931
	/*
-
 
932
	 * Prefer a better P value over a better (smaller) error if the error
-
 
933
	 * is small. Ensure this preference for future configurations too by
-
 
934
	 * setting the error to 0.
-
 
935
	 */
-
 
936
	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
-
 
937
		*error_ppm = 0;
-
 
938
 
-
 
939
		return true;
-
 
940
	}
-
 
941
 
-
 
942
	return *error_ppm + 10 < best_error_ppm;
-
 
943
}
774
 
944
 
775
static bool
945
static bool
-
 
946
vlv_find_best_dpll(const intel_limit_t *limit,
776
vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
947
		   struct intel_crtc_state *crtc_state,
777
			int target, int refclk, intel_clock_t *match_clock,
948
		   int target, int refclk, intel_clock_t *match_clock,
778
			intel_clock_t *best_clock)
949
		   intel_clock_t *best_clock)
-
 
950
{
779
{
951
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
780
	struct drm_device *dev = crtc->base.dev;
952
	struct drm_device *dev = crtc->base.dev;
781
	intel_clock_t clock;
953
	intel_clock_t clock;
782
	unsigned int bestppm = 1000000;
954
	unsigned int bestppm = 1000000;
783
	/* min update 19.2 MHz */
955
	/* min update 19.2 MHz */
Line 794... Line 966...
794
			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966
			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795
			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967
			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796
				clock.p = clock.p1 * clock.p2;
968
				clock.p = clock.p1 * clock.p2;
797
				/* based on hardware requirement, prefer bigger m1,m2 values */
969
				/* based on hardware requirement, prefer bigger m1,m2 values */
798
				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970
				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799
					unsigned int ppm, diff;
971
					unsigned int ppm;
Line 800... Line 972...
800
 
972
 
801
					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973
					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
Line 802... Line 974...
802
								     refclk * clock.m1);
974
								     refclk * clock.m1);
Line 803... Line 975...
803
 
975
 
804
					vlv_clock(refclk, &clock);
976
					vlv_calc_dpll_params(refclk, &clock);
805
 
977
 
Line 806... Line 978...
806
					if (!intel_PLL_is_valid(dev, limit,
978
					if (!intel_PLL_is_valid(dev, limit,
-
 
979
								&clock))
-
 
980
						continue;
807
								&clock))
981
 
-
 
982
					if (!vlv_PLL_is_optimal(dev, target,
Line 808... Line -...
808
						continue;
-
 
809
 
-
 
810
					diff = abs(clock.dot - target);
983
								&clock,
811
					ppm = div_u64(1000000ULL * diff, target);
-
 
812
 
-
 
813
					if (ppm < 100 && clock.p > best_clock->p) {
-
 
814
							bestppm = 0;
-
 
815
						*best_clock = clock;
984
								best_clock,
816
						found = true;
-
 
817
						}
985
								bestppm, &ppm))
818
 
986
						continue;
819
					if (bestppm >= 10 && ppm < bestppm - 10) {
987
 
820
						bestppm = ppm;
988
					*best_clock = clock;
821
						*best_clock = clock;
989
					bestppm = ppm;
822
						found = true;
-
 
Line 823... Line 990...
823
						}
990
					found = true;
824
						}
991
				}
Line 825... Line 992...
825
					}
992
			}
826
				}
993
		}
-
 
994
	}
827
			}
995
 
828
 
996
	return found;
829
	return found;
997
}
-
 
998
 
830
}
999
static bool
-
 
1000
chv_find_best_dpll(const intel_limit_t *limit,
831
 
1001
		   struct intel_crtc_state *crtc_state,
832
static bool
1002
		   int target, int refclk, intel_clock_t *match_clock,
833
chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
1003
		   intel_clock_t *best_clock)
Line 834... Line 1004...
834
		   int target, int refclk, intel_clock_t *match_clock,
1004
{
-
 
1005
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Line 835... Line 1006...
835
		   intel_clock_t *best_clock)
1006
	struct drm_device *dev = crtc->base.dev;
836
{
1007
	unsigned int best_error_ppm;
837
	struct drm_device *dev = crtc->base.dev;
1008
	intel_clock_t clock;
838
	intel_clock_t clock;
1009
	uint64_t m2;
Line 851... Line 1022...
851
 
1022
 
852
	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023
	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853
		for (clock.p2 = limit->p2.p2_fast;
1024
		for (clock.p2 = limit->p2.p2_fast;
854
				clock.p2 >= limit->p2.p2_slow;
1025
				clock.p2 >= limit->p2.p2_slow;
-
 
1026
				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Line 855... Line 1027...
855
				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1027
			unsigned int error_ppm;
Line 856... Line 1028...
856
 
1028
 
857
			clock.p = clock.p1 * clock.p2;
1029
			clock.p = clock.p1 * clock.p2;
Line 862... Line 1034...
862
			if (m2 > INT_MAX/clock.m1)
1034
			if (m2 > INT_MAX/clock.m1)
863
				continue;
1035
				continue;
Line 864... Line 1036...
864
 
1036
 
Line 865... Line 1037...
865
			clock.m2 = m2;
1037
			clock.m2 = m2;
Line 866... Line 1038...
866
 
1038
 
867
			chv_clock(refclk, &clock);
1039
			chv_calc_dpll_params(refclk, &clock);
Line 868... Line 1040...
868
 
1040
 
869
			if (!intel_PLL_is_valid(dev, limit, &clock))
-
 
870
				continue;
1041
			if (!intel_PLL_is_valid(dev, limit, &clock))
-
 
1042
				continue;
-
 
1043
 
871
 
1044
			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
-
 
1045
						best_error_ppm, &error_ppm))
872
			/* based on hardware requirement, prefer bigger p
1046
				continue;
873
			 */
1047
 
874
			if (clock.p > best_clock->p) {
1048
			*best_clock = clock;
875
				*best_clock = clock;
-
 
Line 876... Line 1049...
876
				found = true;
1049
			best_error_ppm = error_ppm;
877
			}
1050
			found = true;
Line -... Line 1051...
-
 
1051
		}
-
 
1052
	}
-
 
1053
 
-
 
1054
	return found;
-
 
1055
}
-
 
1056
 
-
 
1057
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
-
 
1058
			intel_clock_t *best_clock)
-
 
1059
{
878
		}
1060
	int refclk = i9xx_get_refclk(crtc_state, 0);
879
	}
1061
 
880
 
1062
	return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
Line 881... Line 1063...
881
	return found;
1063
				  target_clock, refclk, NULL, best_clock);
Line 891... Line 1073...
891
	 * We can ditch the adjusted_mode.crtc_clock check as soon
1073
	 * We can ditch the adjusted_mode.crtc_clock check as soon
892
	 * as Haswell has gained clock readout/fastboot support.
1074
	 * as Haswell has gained clock readout/fastboot support.
893
	 *
1075
	 *
894
	 * We can ditch the crtc->primary->fb check as soon as we can
1076
	 * We can ditch the crtc->primary->fb check as soon as we can
895
	 * properly reconstruct framebuffers.
1077
	 * properly reconstruct framebuffers.
-
 
1078
	 *
-
 
1079
	 * FIXME: The intel_crtc->active here should be switched to
-
 
1080
	 * crtc->state->active once we have proper CRTC states wired up
-
 
1081
	 * for atomic.
896
	 */
1082
	 */
897
	return intel_crtc->active && crtc->primary->fb &&
1083
	return intel_crtc->active && crtc->primary->state->fb &&
898
		intel_crtc->config.adjusted_mode.crtc_clock;
1084
		intel_crtc->config->base.adjusted_mode.crtc_clock;
899
}
1085
}
Line 900... Line 1086...
900
 
1086
 
901
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902
					     enum pipe pipe)
1088
					     enum pipe pipe)
903
{
1089
{
904
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Line 905... Line 1091...
905
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
 
1092
 
Line 907... Line 1093...
907
	return intel_crtc->config.cpu_transcoder;
1093
	return intel_crtc->config->cpu_transcoder;
908
}
1094
}
909
 
1095
 
Line 918... Line 1104...
918
		line_mask = DSL_LINEMASK_GEN2;
1104
		line_mask = DSL_LINEMASK_GEN2;
919
	else
1105
	else
920
		line_mask = DSL_LINEMASK_GEN3;
1106
		line_mask = DSL_LINEMASK_GEN3;
Line 921... Line 1107...
921
 
1107
 
922
	line1 = I915_READ(reg) & line_mask;
1108
	line1 = I915_READ(reg) & line_mask;
923
	mdelay(5);
1109
	msleep(5);
Line 924... Line 1110...
924
	line2 = I915_READ(reg) & line_mask;
1110
	line2 = I915_READ(reg) & line_mask;
925
 
1111
 
Line 944... Line 1130...
944
 */
1130
 */
945
static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131
static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946
{
1132
{
947
	struct drm_device *dev = crtc->base.dev;
1133
	struct drm_device *dev = crtc->base.dev;
948
	struct drm_i915_private *dev_priv = dev->dev_private;
1134
	struct drm_i915_private *dev_priv = dev->dev_private;
949
	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
1135
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
950
	enum pipe pipe = crtc->pipe;
1136
	enum pipe pipe = crtc->pipe;
Line 951... Line 1137...
951
 
1137
 
952
	if (INTEL_INFO(dev)->gen >= 4) {
1138
	if (INTEL_INFO(dev)->gen >= 4) {
Line 961... Line 1147...
961
		if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147
		if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962
			WARN(1, "pipe_off wait timed out\n");
1148
			WARN(1, "pipe_off wait timed out\n");
963
	}
1149
	}
964
}
1150
}
Line 965... Line -...
965
 
-
 
966
/*
-
 
967
 * ibx_digital_port_connected - is the specified port connected?
-
 
968
 * @dev_priv: i915 private structure
-
 
969
 * @port: the port to test
-
 
970
 *
-
 
971
 * Returns true if @port is connected, false otherwise.
-
 
972
 */
-
 
973
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
-
 
974
				struct intel_digital_port *port)
-
 
975
{
-
 
976
	u32 bit;
-
 
977
 
-
 
978
	if (HAS_PCH_IBX(dev_priv->dev)) {
-
 
979
		switch (port->port) {
-
 
980
		case PORT_B:
-
 
981
			bit = SDE_PORTB_HOTPLUG;
-
 
982
			break;
-
 
983
		case PORT_C:
-
 
984
			bit = SDE_PORTC_HOTPLUG;
-
 
985
			break;
-
 
986
		case PORT_D:
-
 
987
			bit = SDE_PORTD_HOTPLUG;
-
 
988
			break;
-
 
989
		default:
-
 
990
			return true;
-
 
991
		}
-
 
992
	} else {
-
 
993
		switch (port->port) {
-
 
994
		case PORT_B:
-
 
995
			bit = SDE_PORTB_HOTPLUG_CPT;
-
 
996
			break;
-
 
997
		case PORT_C:
-
 
998
			bit = SDE_PORTC_HOTPLUG_CPT;
-
 
999
			break;
-
 
1000
		case PORT_D:
-
 
1001
			bit = SDE_PORTD_HOTPLUG_CPT;
-
 
1002
			break;
-
 
1003
		default:
-
 
1004
			return true;
-
 
1005
		}
-
 
1006
	}
-
 
1007
 
-
 
1008
	return I915_READ(SDEISR) & bit;
-
 
1009
}
-
 
1010
 
1151
 
1011
static const char *state_string(bool enabled)
1152
static const char *state_string(bool enabled)
1012
{
1153
{
1013
	return enabled ? "on" : "off";
1154
	return enabled ? "on" : "off";
Line 1014... Line 1155...
1014
}
1155
}
1015
 
1156
 
1016
/* Only for pre-ILK configs */
1157
/* Only for pre-ILK configs */
1017
void assert_pll(struct drm_i915_private *dev_priv,
1158
void assert_pll(struct drm_i915_private *dev_priv,
1018
		       enum pipe pipe, bool state)
-
 
1019
{
1159
		enum pipe pipe, bool state)
1020
	int reg;
1160
{
Line 1021... Line -...
1021
	u32 val;
-
 
1022
	bool cur_state;
1161
	u32 val;
1023
 
1162
	bool cur_state;
1024
	reg = DPLL(pipe);
1163
 
1025
	val = I915_READ(reg);
1164
	val = I915_READ(DPLL(pipe));
1026
	cur_state = !!(val & DPLL_VCO_ENABLE);
1165
	cur_state = !!(val & DPLL_VCO_ENABLE);
1027
	WARN(cur_state != state,
1166
	I915_STATE_WARN(cur_state != state,
Line 1028... Line 1167...
1028
	     "PLL state assertion failure (expected %s, current %s)\n",
1167
	     "PLL state assertion failure (expected %s, current %s)\n",
1029
	     state_string(state), state_string(cur_state));
1168
	     state_string(state), state_string(cur_state));
1030
}
1169
}
1031
 
1170
 
1032
/* XXX: the dsi pll is shared between MIPI DSI ports */
1171
/* XXX: the dsi pll is shared between MIPI DSI ports */
Line 1033... Line 1172...
1033
static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172
static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034
{
1173
{
1035
	u32 val;
1174
	u32 val;
Line 1036... Line 1175...
1036
	bool cur_state;
1175
	bool cur_state;
1037
 
1176
 
1038
	mutex_lock(&dev_priv->dpio_lock);
1177
	mutex_lock(&dev_priv->sb_lock);
1039
	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178
	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040
	mutex_unlock(&dev_priv->dpio_lock);
1179
	mutex_unlock(&dev_priv->sb_lock);
1041
 
1180
 
1042
	cur_state = val & DSI_PLL_VCO_EN;
1181
	cur_state = val & DSI_PLL_VCO_EN;
Line 1050... Line 1189...
1050
struct intel_shared_dpll *
1189
struct intel_shared_dpll *
1051
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052
{
1191
{
1053
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Line 1054... Line 1193...
1054
 
1193
 
1055
	if (crtc->config.shared_dpll < 0)
1194
	if (crtc->config->shared_dpll < 0)
Line 1056... Line 1195...
1056
		return NULL;
1195
		return NULL;
1057
 
1196
 
Line 1058... Line 1197...
1058
	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1197
	return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1059
}
1198
}
1060
 
1199
 
Line 1069... Line 1208...
1069
	if (WARN (!pll,
1208
	if (WARN (!pll,
1070
		  "asserting DPLL %s with no DPLL\n", state_string(state)))
1209
		  "asserting DPLL %s with no DPLL\n", state_string(state)))
1071
		return;
1210
		return;
Line 1072... Line 1211...
1072
 
1211
 
1073
	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212
	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074
	WARN(cur_state != state,
1213
	I915_STATE_WARN(cur_state != state,
1075
	     "%s assertion failure (expected %s, current %s)\n",
1214
	     "%s assertion failure (expected %s, current %s)\n",
1076
	     pll->name, state_string(state), state_string(cur_state));
1215
	     pll->name, state_string(state), state_string(cur_state));
Line 1077... Line 1216...
1077
}
1216
}
1078
 
1217
 
1079
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080
			  enum pipe pipe, bool state)
-
 
1081
{
-
 
1082
	int reg;
1219
			  enum pipe pipe, bool state)
1083
	u32 val;
1220
{
1084
	bool cur_state;
1221
	bool cur_state;
Line 1085... Line 1222...
1085
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086
								      pipe);
1223
								      pipe);
1087
 
1224
 
1088
	if (HAS_DDI(dev_priv->dev)) {
-
 
1089
		/* DDI does not have a specific FDI_TX register */
1225
	if (HAS_DDI(dev_priv->dev)) {
1090
		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1226
		/* DDI does not have a specific FDI_TX register */
1091
		val = I915_READ(reg);
1227
		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1092
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
-
 
1093
	} else {
1228
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1094
	reg = FDI_TX_CTL(pipe);
1229
	} else {
1095
	val = I915_READ(reg);
1230
		u32 val = I915_READ(FDI_TX_CTL(pipe));
1096
	cur_state = !!(val & FDI_TX_ENABLE);
1231
		cur_state = !!(val & FDI_TX_ENABLE);
1097
	}
1232
	}
1098
	WARN(cur_state != state,
1233
	I915_STATE_WARN(cur_state != state,
1099
	     "FDI TX state assertion failure (expected %s, current %s)\n",
1234
	     "FDI TX state assertion failure (expected %s, current %s)\n",
1100
	     state_string(state), state_string(cur_state));
1235
	     state_string(state), state_string(cur_state));
Line 1101... Line 1236...
1101
}
1236
}
1102
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
 
-
 
1105
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1239
 
1106
			  enum pipe pipe, bool state)
1240
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
Line 1107... Line 1241...
1107
{
1241
			  enum pipe pipe, bool state)
1108
	int reg;
-
 
1109
	u32 val;
1242
{
1110
	bool cur_state;
1243
	u32 val;
1111
 
1244
	bool cur_state;
1112
	reg = FDI_RX_CTL(pipe);
1245
 
1113
	val = I915_READ(reg);
1246
	val = I915_READ(FDI_RX_CTL(pipe));
1114
	cur_state = !!(val & FDI_RX_ENABLE);
1247
	cur_state = !!(val & FDI_RX_ENABLE);
1115
	WARN(cur_state != state,
1248
	I915_STATE_WARN(cur_state != state,
Line 1116... Line 1249...
1116
	     "FDI RX state assertion failure (expected %s, current %s)\n",
1249
	     "FDI RX state assertion failure (expected %s, current %s)\n",
1117
	     state_string(state), state_string(cur_state));
1250
	     state_string(state), state_string(cur_state));
1118
}
1251
}
1119
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
-
 
1120
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1252
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
Line 1121... Line 1253...
1121
 
1253
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1254
 
1123
				      enum pipe pipe)
1255
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
Line 1124... Line 1256...
1124
{
1256
				      enum pipe pipe)
1125
	int reg;
1257
{
1126
	u32 val;
1258
	u32 val;
Line 1127... Line 1259...
1127
 
1259
 
1128
	/* ILK FDI PLL is always enabled */
-
 
1129
	if (INTEL_INFO(dev_priv->dev)->gen == 5)
1260
	/* ILK FDI PLL is always enabled */
1130
		return;
1261
	if (INTEL_INFO(dev_priv->dev)->gen == 5)
Line 1131... Line 1262...
1131
 
1262
		return;
1132
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
1263
 
1133
	if (HAS_DDI(dev_priv->dev))
1264
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
1134
		return;
-
 
1135
 
1265
	if (HAS_DDI(dev_priv->dev))
1136
	reg = FDI_TX_CTL(pipe);
1266
		return;
Line 1137... Line 1267...
1137
	val = I915_READ(reg);
1267
 
1138
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
-
 
1139
}
1268
	val = I915_READ(FDI_TX_CTL(pipe));
1140
 
1269
	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1270
}
1142
		       enum pipe pipe, bool state)
1271
 
1143
{
1272
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
Line 1144... Line 1273...
1144
	int reg;
1273
		       enum pipe pipe, bool state)
Line 1188... Line 1317...
1188
	val = I915_READ(pp_reg);
1317
	val = I915_READ(pp_reg);
1189
	if (!(val & PANEL_POWER_ON) ||
1318
	if (!(val & PANEL_POWER_ON) ||
1190
	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319
	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191
		locked = false;
1320
		locked = false;
Line 1192... Line 1321...
1192
 
1321
 
1193
	WARN(panel_pipe == pipe && locked,
1322
	I915_STATE_WARN(panel_pipe == pipe && locked,
1194
	     "panel assertion failure, pipe %c regs locked\n",
1323
	     "panel assertion failure, pipe %c regs locked\n",
1195
	     pipe_name(pipe));
1324
	     pipe_name(pipe));
Line 1196... Line 1325...
1196
}
1325
}
Line 1200... Line 1329...
1200
{
1329
{
1201
	struct drm_device *dev = dev_priv->dev;
1330
	struct drm_device *dev = dev_priv->dev;
1202
	bool cur_state;
1331
	bool cur_state;
Line 1203... Line 1332...
1203
 
1332
 
1204
	if (IS_845G(dev) || IS_I865G(dev))
1333
	if (IS_845G(dev) || IS_I865G(dev))
1205
		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1334
		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1206
	else
1335
	else
Line 1207... Line 1336...
1207
		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
 
1337
 
1209
	WARN(cur_state != state,
1338
	I915_STATE_WARN(cur_state != state,
1210
	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339
	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1340
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1212
}
1341
}
Line 1213... Line 1342...
1213
#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342
#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214
#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
 
1344
 
1216
void assert_pipe(struct drm_i915_private *dev_priv,
-
 
1217
			enum pipe pipe, bool state)
-
 
1218
{
1345
void assert_pipe(struct drm_i915_private *dev_priv,
1219
	int reg;
1346
		 enum pipe pipe, bool state)
1220
	u32 val;
1347
{
Line 1221... Line 1348...
1221
	bool cur_state;
1348
	bool cur_state;
Line 1229... Line 1356...
1229
 
1356
 
1230
	if (!intel_display_power_is_enabled(dev_priv,
1357
	if (!intel_display_power_is_enabled(dev_priv,
1231
				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358
				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232
		cur_state = false;
1359
		cur_state = false;
1233
	} else {
1360
	} else {
1234
	reg = PIPECONF(cpu_transcoder);
-
 
1235
	val = I915_READ(reg);
1361
		u32 val = I915_READ(PIPECONF(cpu_transcoder));
1236
	cur_state = !!(val & PIPECONF_ENABLE);
1362
		cur_state = !!(val & PIPECONF_ENABLE);
Line 1237... Line 1363...
1237
	}
1363
	}
1238
 
1364
 
1239
	WARN(cur_state != state,
1365
	I915_STATE_WARN(cur_state != state,
1240
	     "pipe %c assertion failure (expected %s, current %s)\n",
1366
	     "pipe %c assertion failure (expected %s, current %s)\n",
Line 1241... Line 1367...
1241
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1367
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1242
}
1368
}
1243
 
1369
 
1244
static void assert_plane(struct drm_i915_private *dev_priv,
-
 
1245
			 enum plane plane, bool state)
1370
static void assert_plane(struct drm_i915_private *dev_priv,
1246
{
1371
			 enum plane plane, bool state)
Line 1247... Line -...
1247
	int reg;
-
 
1248
	u32 val;
1372
{
1249
	bool cur_state;
1373
	u32 val;
1250
 
1374
	bool cur_state;
1251
	reg = DSPCNTR(plane);
1375
 
1252
	val = I915_READ(reg);
1376
	val = I915_READ(DSPCNTR(plane));
1253
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
Line 1254... Line 1378...
1254
	WARN(cur_state != state,
1378
	I915_STATE_WARN(cur_state != state,
Line 1261... Line 1385...
1261
 
1385
 
1262
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263
				   enum pipe pipe)
1387
				   enum pipe pipe)
1264
{
1388
{
1265
	struct drm_device *dev = dev_priv->dev;
1389
	struct drm_device *dev = dev_priv->dev;
1266
	int reg, i;
-
 
1267
	u32 val;
-
 
Line 1268... Line 1390...
1268
	int cur_pipe;
1390
	int i;
1269
 
1391
 
1270
	/* Primary planes are fixed to pipes on gen4+ */
-
 
1271
	if (INTEL_INFO(dev)->gen >= 4) {
1392
	/* Primary planes are fixed to pipes on gen4+ */
1272
		reg = DSPCNTR(pipe);
1393
	if (INTEL_INFO(dev)->gen >= 4) {
1273
		val = I915_READ(reg);
1394
		u32 val = I915_READ(DSPCNTR(pipe));
1274
		WARN(val & DISPLAY_PLANE_ENABLE,
1395
		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1275
		     "plane %c assertion failure, should be disabled but not\n",
1396
		     "plane %c assertion failure, should be disabled but not\n",
1276
		     plane_name(pipe));
1397
		     plane_name(pipe));
Line 1277... Line 1398...
1277
		return;
1398
		return;
1278
	}
1399
	}
1279
 
-
 
1280
	/* Need to check both planes against the pipe */
1400
 
1281
	for_each_pipe(dev_priv, i) {
1401
	/* Need to check both planes against the pipe */
1282
		reg = DSPCNTR(i);
1402
	for_each_pipe(dev_priv, i) {
1283
		val = I915_READ(reg);
1403
		u32 val = I915_READ(DSPCNTR(i));
1284
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404
		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285
			DISPPLANE_SEL_PIPE_SHIFT;
1405
			DISPPLANE_SEL_PIPE_SHIFT;
1286
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406
		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
Line 1288... Line 1408...
1288
		     plane_name(i), pipe_name(pipe));
1408
		     plane_name(i), pipe_name(pipe));
1289
	}
1409
	}
1290
}
1410
}
1291
 
1411
 
1292
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293
				    enum pipe pipe)
-
 
Line 1294... Line 1413...
1294
{
1413
				    enum pipe pipe)
1295
	struct drm_device *dev = dev_priv->dev;
1414
{
1296
	int reg, sprite;
1415
	struct drm_device *dev = dev_priv->dev;
1297
	u32 val;
1416
	int sprite;
1298
 
1417
 
1299
	if (INTEL_INFO(dev)->gen >= 9) {
1418
	if (INTEL_INFO(dev)->gen >= 9) {
1300
		for_each_sprite(pipe, sprite) {
1419
		for_each_sprite(dev_priv, pipe, sprite) {
1301
			val = I915_READ(PLANE_CTL(pipe, sprite));
1420
			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1302
			WARN(val & PLANE_CTL_ENABLE,
1421
			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1303
			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422
			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304
			     sprite, pipe_name(pipe));
-
 
1305
		}
1423
			     sprite, pipe_name(pipe));
1306
	} else if (IS_VALLEYVIEW(dev)) {
1424
		}
1307
		for_each_sprite(pipe, sprite) {
1425
	} else if (IS_VALLEYVIEW(dev)) {
1308
			reg = SPCNTR(pipe, sprite);
1426
		for_each_sprite(dev_priv, pipe, sprite) {
1309
		val = I915_READ(reg);
1427
			u32 val = I915_READ(SPCNTR(pipe, sprite));
1310
			WARN(val & SP_ENABLE,
-
 
1311
			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1428
			I915_STATE_WARN(val & SP_ENABLE,
1312
			     sprite_name(pipe, sprite), pipe_name(pipe));
1429
			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1313
		}
1430
			     sprite_name(pipe, sprite), pipe_name(pipe));
1314
	} else if (INTEL_INFO(dev)->gen >= 7) {
1431
		}
1315
		reg = SPRCTL(pipe);
1432
	} else if (INTEL_INFO(dev)->gen >= 7) {
1316
		val = I915_READ(reg);
-
 
1317
		WARN(val & SPRITE_ENABLE,
1433
		u32 val = I915_READ(SPRCTL(pipe));
1318
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1434
		I915_STATE_WARN(val & SPRITE_ENABLE,
1319
		     plane_name(pipe), pipe_name(pipe));
1435
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1320
	} else if (INTEL_INFO(dev)->gen >= 5) {
1436
		     plane_name(pipe), pipe_name(pipe));
1321
		reg = DVSCNTR(pipe);
1437
	} else if (INTEL_INFO(dev)->gen >= 5) {
1322
		val = I915_READ(reg);
1438
		u32 val = I915_READ(DVSCNTR(pipe));
Line 1323... Line 1439...
1323
		WARN(val & DVS_ENABLE,
1439
		I915_STATE_WARN(val & DVS_ENABLE,
1324
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325
		     plane_name(pipe), pipe_name(pipe));
1441
		     plane_name(pipe), pipe_name(pipe));
1326
	}
1442
	}
1327
}
1443
}
Line 1328... Line 1444...
1328
 
1444
 
1329
static void assert_vblank_disabled(struct drm_crtc *crtc)
1445
static void assert_vblank_disabled(struct drm_crtc *crtc)
1330
{
1446
{
1331
	if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447
	if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
Line 1332... Line 1448...
1332
		drm_crtc_vblank_put(crtc);
1448
		drm_crtc_vblank_put(crtc);
Line 1333... Line 1449...
1333
}
1449
}
1334
 
1450
 
1335
static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451
static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336
{
1452
{
1337
	u32 val;
1453
	u32 val;
Line 1338... Line 1454...
1338
	bool enabled;
1454
	bool enabled;
1339
 
1455
 
1340
	WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
	I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
 
-
 
1342
	val = I915_READ(PCH_DREF_CONTROL);
1457
 
1343
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1458
	val = I915_READ(PCH_DREF_CONTROL);
Line 1344... Line 1459...
1344
			    DREF_SUPERSPREAD_SOURCE_MASK));
1459
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1345
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
-
 
1346
}
1460
			    DREF_SUPERSPREAD_SOURCE_MASK));
1347
 
1461
	I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1462
}
1349
				       enum pipe pipe)
1463
 
1350
{
1464
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
Line 1351... Line 1465...
1351
	int reg;
1465
					   enum pipe pipe)
Line 1433... Line 1547...
1433
 
1547
 
1434
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435
				   enum pipe pipe, int reg, u32 port_sel)
1549
				   enum pipe pipe, int reg, u32 port_sel)
1436
{
1550
{
1437
	u32 val = I915_READ(reg);
1551
	u32 val = I915_READ(reg);
1438
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552
	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Line 1440... Line 1554...
1440
	     reg, pipe_name(pipe));
1554
	     reg, pipe_name(pipe));
1441
 
1555
 
1442
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556
	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443
	     && (val & DP_PIPEB_SELECT),
1557
	     && (val & DP_PIPEB_SELECT),
Line 1444... Line 1558...
1444
	     "IBX PCH dp port still using transcoder B\n");
1558
	     "IBX PCH dp port still using transcoder B\n");
1445
}
1559
}
1446
 
1560
 
1447
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448
				     enum pipe pipe, int reg)
1562
				     enum pipe pipe, int reg)
1449
{
1563
{
1450
	u32 val = I915_READ(reg);
1564
	u32 val = I915_READ(reg);
Line 1451... Line 1565...
1451
	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565
	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453
	     reg, pipe_name(pipe));
1567
	     reg, pipe_name(pipe));
1454
 
1568
 
Line 1455... Line 1569...
1455
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569
	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456
	     && (val & SDVO_PIPE_B_SELECT),
1570
	     && (val & SDVO_PIPE_B_SELECT),
1457
	     "IBX PCH hdmi port still using transcoder B\n");
1571
	     "IBX PCH hdmi port still using transcoder B\n");
1458
}
-
 
1459
 
1572
}
Line 1460... Line 1573...
1460
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1573
 
1461
				      enum pipe pipe)
1574
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1462
{
1575
				      enum pipe pipe)
Line 1463... Line -...
1463
	int reg;
-
 
1464
	u32 val;
1576
{
1465
 
1577
	u32 val;
1466
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1578
 
1467
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1579
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
Line 1468... Line -...
1468
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
-
 
1469
 
1580
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1470
	reg = PCH_ADPA;
1581
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471
	val = I915_READ(reg);
1582
 
1472
	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583
	val = I915_READ(PCH_ADPA);
Line 1473... Line 1584...
1473
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1584
	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1474
	     pipe_name(pipe));
1585
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1475
 
1586
	     pipe_name(pipe));
1476
	reg = PCH_LVDS;
1587
 
Line 1477... Line -...
1477
	val = I915_READ(reg);
-
 
1478
	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
-
 
1479
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
-
 
1480
	     pipe_name(pipe));
-
 
1481
 
-
 
1482
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
-
 
1483
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
-
 
1484
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
-
 
1485
}
-
 
1486
 
-
 
1487
static void intel_init_dpio(struct drm_device *dev)
-
 
1488
{
-
 
1489
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
1490
 
-
 
1491
	if (!IS_VALLEYVIEW(dev))
-
 
1492
		return;
-
 
1493
 
-
 
1494
	/*
-
 
1495
	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
-
 
1496
	 * CHV x1 PHY (DP/HDMI D)
-
 
1497
	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588
	val = I915_READ(PCH_LVDS);
1498
	 */
1589
	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1499
	if (IS_CHERRYVIEW(dev)) {
1590
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1500
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591
	     pipe_name(pipe));
1501
		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592
 
1502
	} else {
1593
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1503
	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
Line 1542... Line 1633...
1542
	POSTING_READ(reg);
1633
	POSTING_READ(reg);
1543
	udelay(150); /* wait for warmup */
1634
	udelay(150); /* wait for warmup */
1544
}
1635
}
Line 1545... Line 1636...
1545
 
1636
 
1546
static void chv_enable_pll(struct intel_crtc *crtc,
1637
static void chv_enable_pll(struct intel_crtc *crtc,
1547
			   const struct intel_crtc_config *pipe_config)
1638
			   const struct intel_crtc_state *pipe_config)
1548
{
1639
{
1549
	struct drm_device *dev = crtc->base.dev;
1640
	struct drm_device *dev = crtc->base.dev;
1550
	struct drm_i915_private *dev_priv = dev->dev_private;
1641
	struct drm_i915_private *dev_priv = dev->dev_private;
1551
	int pipe = crtc->pipe;
1642
	int pipe = crtc->pipe;
Line 1554... Line 1645...
1554
 
1645
 
Line 1555... Line 1646...
1555
	assert_pipe_disabled(dev_priv, crtc->pipe);
1646
	assert_pipe_disabled(dev_priv, crtc->pipe);
Line 1556... Line 1647...
1556
 
1647
 
Line 1557... Line 1648...
1557
	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
 
1649
 
1559
	mutex_lock(&dev_priv->dpio_lock);
1650
	mutex_lock(&dev_priv->sb_lock);
1560
 
1651
 
Line -... Line 1652...
-
 
1652
	/* Enable back the 10bit clock to display controller */
-
 
1653
	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1561
	/* Enable back the 10bit clock to display controller */
1654
	tmp |= DPIO_DCLKP_EN;
1562
	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1655
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1563
	tmp |= DPIO_DCLKP_EN;
1656
 
1564
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1657
	mutex_unlock(&dev_priv->sb_lock);
Line 1576... Line 1669...
1576
		DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
		DRM_ERROR("PLL %d failed to lock\n", pipe);
Line 1577... Line 1670...
1577
 
1670
 
1578
	/* not sure when this should be written */
1671
	/* not sure when this should be written */
1579
	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672
	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580
	POSTING_READ(DPLL_MD(pipe));
-
 
1581
 
-
 
1582
	mutex_unlock(&dev_priv->dpio_lock);
1673
	POSTING_READ(DPLL_MD(pipe));
Line 1583... Line 1674...
1583
}
1674
}
1584
 
1675
 
1585
static int intel_num_dvo_pipes(struct drm_device *dev)
1676
static int intel_num_dvo_pipes(struct drm_device *dev)
1586
{
1677
{
Line 1587... Line 1678...
1587
	struct intel_crtc *crtc;
1678
	struct intel_crtc *crtc;
1588
	int count = 0;
1679
	int count = 0;
1589
 
1680
 
Line 1590... Line 1681...
1590
	for_each_intel_crtc(dev, crtc)
1681
	for_each_intel_crtc(dev, crtc)
1591
		count += crtc->active &&
1682
		count += crtc->base.state->active &&
Line 1592... Line 1683...
1592
			intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
			intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
 
1684
 
1594
	return count;
1685
	return count;
1595
}
1686
}
1596
 
1687
 
1597
static void i9xx_enable_pll(struct intel_crtc *crtc)
1688
static void i9xx_enable_pll(struct intel_crtc *crtc)
Line 1598... Line 1689...
1598
{
1689
{
Line 1599... Line 1690...
1599
	struct drm_device *dev = crtc->base.dev;
1690
	struct drm_device *dev = crtc->base.dev;
1600
	struct drm_i915_private *dev_priv = dev->dev_private;
1691
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 1621... Line 1712...
1621
		dpll |= DPLL_DVO_2X_MODE;
1712
		dpll |= DPLL_DVO_2X_MODE;
1622
		I915_WRITE(DPLL(!crtc->pipe),
1713
		I915_WRITE(DPLL(!crtc->pipe),
1623
			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714
			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624
	}
1715
	}
Line -... Line 1716...
-
 
1716
 
-
 
1717
	/*
-
 
1718
	 * Apparently we need to have VGA mode enabled prior to changing
-
 
1719
	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
-
 
1720
	 * dividers, even though the register value does change.
-
 
1721
	 */
-
 
1722
	I915_WRITE(reg, 0);
-
 
1723
 
-
 
1724
	I915_WRITE(reg, dpll);
1625
 
1725
 
1626
	/* Wait for the clocks to stabilize. */
1726
	/* Wait for the clocks to stabilize. */
1627
	POSTING_READ(reg);
1727
	POSTING_READ(reg);
Line 1628... Line 1728...
1628
	udelay(150);
1728
	udelay(150);
1629
 
1729
 
1630
	if (INTEL_INFO(dev)->gen >= 4) {
1730
	if (INTEL_INFO(dev)->gen >= 4) {
1631
		I915_WRITE(DPLL_MD(crtc->pipe),
1731
		I915_WRITE(DPLL_MD(crtc->pipe),
1632
			   crtc->config.dpll_hw_state.dpll_md);
1732
			   crtc->config->dpll_hw_state.dpll_md);
1633
	} else {
1733
	} else {
1634
		/* The pixel multiplier can only be updated once the
1734
		/* The pixel multiplier can only be updated once the
1635
		 * DPLL is enabled and the clocks are stable.
1735
		 * DPLL is enabled and the clocks are stable.
Line 1667... Line 1767...
1667
	enum pipe pipe = crtc->pipe;
1767
	enum pipe pipe = crtc->pipe;
Line 1668... Line 1768...
1668
 
1768
 
1669
	/* Disable DVO 2x clock on both PLLs if necessary */
1769
	/* Disable DVO 2x clock on both PLLs if necessary */
1670
	if (IS_I830(dev) &&
1770
	if (IS_I830(dev) &&
1671
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672
	    intel_num_dvo_pipes(dev) == 1) {
1772
	    !intel_num_dvo_pipes(dev)) {
1673
		I915_WRITE(DPLL(PIPE_B),
1773
		I915_WRITE(DPLL(PIPE_B),
1674
			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774
			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675
		I915_WRITE(DPLL(PIPE_A),
1775
		I915_WRITE(DPLL(PIPE_A),
1676
			   I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776
			   I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
Line 1682... Line 1782...
1682
		return;
1782
		return;
Line 1683... Line 1783...
1683
 
1783
 
1684
	/* Make sure the pipe isn't still relying on us */
1784
	/* Make sure the pipe isn't still relying on us */
Line 1685... Line 1785...
1685
	assert_pipe_disabled(dev_priv, pipe);
1785
	assert_pipe_disabled(dev_priv, pipe);
1686
 
1786
 
1687
	I915_WRITE(DPLL(pipe), 0);
1787
	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
Line 1688... Line 1788...
1688
	POSTING_READ(DPLL(pipe));
1788
	POSTING_READ(DPLL(pipe));
1689
}
1789
}
1690
 
1790
 
Line 1691... Line 1791...
1691
static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791
static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692
{
1792
{
Line 1693... Line 1793...
1693
	u32 val = 0;
1793
	u32 val;
1694
 
1794
 
1695
	/* Make sure the pipe isn't still relying on us */
1795
	/* Make sure the pipe isn't still relying on us */
1696
	assert_pipe_disabled(dev_priv, pipe);
1796
	assert_pipe_disabled(dev_priv, pipe);
-
 
1797
 
1697
 
1798
	/*
1698
	/*
1799
	 * Leave integrated clock source and reference clock enabled for pipe B.
1699
	 * Leave integrated clock source and reference clock enabled for pipe B.
1800
	 * The latter is needed for VGA hotplug / manual detection.
1700
	 * The latter is needed for VGA hotplug / manual detection.
1801
	 */
Line 1701... Line 1802...
1701
	 */
1802
	val = DPLL_VGA_MODE_DIS;
Line 1713... Line 1814...
1713
 
1814
 
1714
	/* Make sure the pipe isn't still relying on us */
1815
	/* Make sure the pipe isn't still relying on us */
Line 1715... Line 1816...
1715
	assert_pipe_disabled(dev_priv, pipe);
1816
	assert_pipe_disabled(dev_priv, pipe);
1716
 
1817
 
-
 
1818
	/* Set PLL en = 0 */
1717
	/* Set PLL en = 0 */
1819
	val = DPLL_SSC_REF_CLK_CHV |
1718
	val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820
		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1719
	if (pipe != PIPE_A)
1821
	if (pipe != PIPE_A)
1720
		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822
		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
Line 1721... Line 1823...
1721
	I915_WRITE(DPLL(pipe), val);
1823
	I915_WRITE(DPLL(pipe), val);
Line 1722... Line 1824...
1722
	POSTING_READ(DPLL(pipe));
1824
	POSTING_READ(DPLL(pipe));
1723
 
1825
 
1724
	mutex_lock(&dev_priv->dpio_lock);
1826
	mutex_lock(&dev_priv->sb_lock);
1725
 
1827
 
Line 1726... Line -...
1726
	/* Disable 10bit clock to display controller */
-
 
1727
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
-
 
1728
	val &= ~DPIO_DCLKP_EN;
-
 
1729
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
-
 
1730
 
-
 
1731
	/* disable left/right clock distribution */
-
 
1732
	if (pipe != PIPE_B) {
-
 
1733
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-
 
1734
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-
 
1735
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-
 
1736
	} else {
-
 
1737
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828
	/* Disable 10bit clock to display controller */
1738
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
Line 1739... Line 1830...
1739
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830
	val &= ~DPIO_DCLKP_EN;
1740
	}
1831
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
-
 
1832
 
1741
 
1833
	mutex_unlock(&dev_priv->sb_lock);
1742
	mutex_unlock(&dev_priv->dpio_lock);
1834
}
1743
}
1835
 
Line 1744... Line 1836...
1744
 
1836
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Line 1754... Line 1846...
1754
		dpll_reg = DPLL(0);
1846
		dpll_reg = DPLL(0);
1755
		break;
1847
		break;
1756
	case PORT_C:
1848
	case PORT_C:
1757
		port_mask = DPLL_PORTC_READY_MASK;
1849
		port_mask = DPLL_PORTC_READY_MASK;
1758
		dpll_reg = DPLL(0);
1850
		dpll_reg = DPLL(0);
-
 
1851
		expected_mask <<= 4;
1759
		break;
1852
		break;
1760
	case PORT_D:
1853
	case PORT_D:
1761
		port_mask = DPLL_PORTD_READY_MASK;
1854
		port_mask = DPLL_PORTD_READY_MASK;
1762
		dpll_reg = DPIO_PHY_STATUS;
1855
		dpll_reg = DPIO_PHY_STATUS;
1763
		break;
1856
		break;
1764
	default:
1857
	default:
1765
		BUG();
1858
		BUG();
1766
	}
1859
	}
Line 1767... Line 1860...
1767
 
1860
 
1768
	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1861
	if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1769
		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1862
		WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1770
		     port_name(dport->port), I915_READ(dpll_reg));
1863
		     port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
Line 1771... Line 1864...
1771
}
1864
}
1772
 
1865
 
1773
static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866
static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
Line 1832... Line 1925...
1832
	struct drm_device *dev = crtc->base.dev;
1925
	struct drm_device *dev = crtc->base.dev;
1833
	struct drm_i915_private *dev_priv = dev->dev_private;
1926
	struct drm_i915_private *dev_priv = dev->dev_private;
1834
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Line 1835... Line 1928...
1835
 
1928
 
1836
	/* PCH only available on ILK+ */
1929
	/* PCH only available on ILK+ */
1837
	BUG_ON(INTEL_INFO(dev)->gen < 5);
-
 
1838
	if (WARN_ON(pll == NULL))
1930
	if (INTEL_INFO(dev)->gen < 5)
Line -... Line 1931...
-
 
1931
		return;
-
 
1932
 
-
 
1933
	if (pll == NULL)
1839
	       return;
1934
		return;
1840
 
1935
 
Line 1841... Line 1936...
1841
	if (WARN_ON(pll->config.crtc_mask == 0))
1936
	if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1842
		return;
1937
		return;
1843
 
1938
 
Line 1894... Line 1989...
1894
	val = I915_READ(reg);
1989
	val = I915_READ(reg);
1895
	pipeconf_val = I915_READ(PIPECONF(pipe));
1990
	pipeconf_val = I915_READ(PIPECONF(pipe));
Line 1896... Line 1991...
1896
 
1991
 
1897
	if (HAS_PCH_IBX(dev_priv->dev)) {
1992
	if (HAS_PCH_IBX(dev_priv->dev)) {
1898
		/*
1993
		/*
1899
		 * make the BPC in transcoder be consistent with
1994
		 * Make the BPC in transcoder be consistent with
-
 
1995
		 * that in pipeconf reg. For HDMI we must use 8bpc
1900
		 * that in pipeconf reg.
1996
		 * here for both 8bpc and 12bpc.
1901
		 */
1997
		 */
-
 
1998
		val &= ~PIPECONF_BPC_MASK;
-
 
1999
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
-
 
2000
			val |= PIPECONF_8BPC;
1902
		val &= ~PIPECONF_BPC_MASK;
2001
		else
1903
		val |= pipeconf_val & PIPECONF_BPC_MASK;
2002
			val |= pipeconf_val & PIPECONF_BPC_MASK;
Line 1904... Line 2003...
1904
	}
2003
	}
1905
 
2004
 
Line 1929... Line 2028...
1929
	/* FDI must be feeding us bits for PCH ports */
2028
	/* FDI must be feeding us bits for PCH ports */
1930
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Line 1932... Line 2031...
1932
 
2031
 
1933
	/* Workaround: set timing override bit. */
2032
	/* Workaround: set timing override bit. */
1934
	val = I915_READ(_TRANSA_CHICKEN2);
2033
	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1935
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Line 1936... Line 2035...
1936
	I915_WRITE(_TRANSA_CHICKEN2, val);
2035
	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1937
 
2036
 
Line 1938... Line 2037...
1938
	val = TRANS_ENABLE;
2037
	val = TRANS_ENABLE;
Line 1989... Line 2088...
1989
	/* wait for PCH transcoder off, transcoder state */
2088
	/* wait for PCH transcoder off, transcoder state */
1990
	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089
	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991
		DRM_ERROR("Failed to disable PCH transcoder\n");
2090
		DRM_ERROR("Failed to disable PCH transcoder\n");
Line 1992... Line 2091...
1992
 
2091
 
1993
	/* Workaround: clear timing override bit. */
2092
	/* Workaround: clear timing override bit. */
1994
	val = I915_READ(_TRANSA_CHICKEN2);
2093
	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1995
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996
	I915_WRITE(_TRANSA_CHICKEN2, val);
2095
	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
Line 1997... Line 2096...
1997
}
2096
}
1998
 
2097
 
1999
/**
2098
/**
Line 2012... Line 2111...
2012
								      pipe);
2111
								      pipe);
2013
	enum pipe pch_transcoder;
2112
	enum pipe pch_transcoder;
2014
	int reg;
2113
	int reg;
2015
	u32 val;
2114
	u32 val;
Line -... Line 2115...
-
 
2115
 
-
 
2116
	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2016
 
2117
 
2017
	assert_planes_disabled(dev_priv, pipe);
2118
	assert_planes_disabled(dev_priv, pipe);
2018
	assert_cursor_disabled(dev_priv, pipe);
2119
	assert_cursor_disabled(dev_priv, pipe);
Line 2019... Line 2120...
2019
	assert_sprites_disabled(dev_priv, pipe);
2120
	assert_sprites_disabled(dev_priv, pipe);
Line 2026... Line 2127...
2026
	/*
2127
	/*
2027
	 * A pipe without a PLL won't actually be able to drive bits from
2128
	 * A pipe without a PLL won't actually be able to drive bits from
2028
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2129
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029
	 * need the check.
2130
	 * need the check.
2030
	 */
2131
	 */
2031
	if (!HAS_PCH_SPLIT(dev_priv->dev))
2132
	if (HAS_GMCH_DISPLAY(dev_priv->dev))
2032
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033
			assert_dsi_pll_enabled(dev_priv);
2134
			assert_dsi_pll_enabled(dev_priv);
2034
		else
2135
		else
2035
		assert_pll_enabled(dev_priv, pipe);
2136
			assert_pll_enabled(dev_priv, pipe);
2036
	else {
2137
	else {
2037
		if (crtc->config.has_pch_encoder) {
2138
		if (crtc->config->has_pch_encoder) {
2038
			/* if driving the PCH, we need FDI enabled */
2139
			/* if driving the PCH, we need FDI enabled */
2039
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040
			assert_fdi_tx_pll_enabled(dev_priv,
2141
			assert_fdi_tx_pll_enabled(dev_priv,
2041
						  (enum pipe) cpu_transcoder);
2142
						  (enum pipe) cpu_transcoder);
2042
		}
2143
		}
Line 2066... Line 2167...
2066
 * Will wait until the pipe has shut down before returning.
2167
 * Will wait until the pipe has shut down before returning.
2067
 */
2168
 */
2068
static void intel_disable_pipe(struct intel_crtc *crtc)
2169
static void intel_disable_pipe(struct intel_crtc *crtc)
2069
{
2170
{
2070
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071
	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2172
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2072
	enum pipe pipe = crtc->pipe;
2173
	enum pipe pipe = crtc->pipe;
2073
	int reg;
2174
	int reg;
2074
	u32 val;
2175
	u32 val;
Line -... Line 2176...
-
 
2176
 
-
 
2177
	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2075
 
2178
 
2076
    /*
2179
	/*
2077
	 * Make sure planes won't keep trying to pump pixels to us,
2180
	 * Make sure planes won't keep trying to pump pixels to us,
2078
	 * or we might hang the display.
2181
	 * or we might hang the display.
2079
	 */
2182
	 */
Line 2088... Line 2191...
2088
 
2191
 
2089
	/*
2192
	/*
2090
	 * Double wide has implications for planes
2193
	 * Double wide has implications for planes
2091
	 * so best keep it disabled when not needed.
2194
	 * so best keep it disabled when not needed.
2092
	 */
2195
	 */
2093
	if (crtc->config.double_wide)
2196
	if (crtc->config->double_wide)
Line 2094... Line 2197...
2094
		val &= ~PIPECONF_DOUBLE_WIDE;
2197
		val &= ~PIPECONF_DOUBLE_WIDE;
2095
 
2198
 
2096
	/* Don't disable pipe or pipe PLLs if needed */
2199
	/* Don't disable pipe or pipe PLLs if needed */
Line 2101... Line 2204...
2101
	I915_WRITE(reg, val);
2204
	I915_WRITE(reg, val);
2102
	if ((val & PIPECONF_ENABLE) == 0)
2205
	if ((val & PIPECONF_ENABLE) == 0)
2103
		intel_wait_for_pipe_off(crtc);
2206
		intel_wait_for_pipe_off(crtc);
2104
}
2207
}
Line 2105... Line -...
2105
 
-
 
2106
/*
-
 
2107
 * Plane regs are double buffered, going from enabled->disabled needs a
-
 
2108
 * trigger in order to latch.  The display address reg provides this.
-
 
2109
 */
2208
 
2110
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
-
 
2111
				      enum plane plane)
2209
static bool need_vtd_wa(struct drm_device *dev)
2112
{
2210
{
2113
	struct drm_device *dev = dev_priv->dev;
2211
#ifdef CONFIG_INTEL_IOMMU
2114
	u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
-
 
2115
 
2212
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
-
 
2213
		return true;
2116
	I915_WRITE(reg, I915_READ(reg));
2214
#endif
2117
	POSTING_READ(reg);
2215
	return false;
Line 2118... Line 2216...
2118
}
2216
}
2119
 
2217
 
-
 
2218
unsigned int
-
 
2219
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2120
/**
2220
		  uint64_t fb_format_modifier, unsigned int plane)
2121
 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2221
{
2122
 * @plane:  plane to be enabled
2222
	unsigned int tile_height;
-
 
2223
	uint32_t pixel_bytes;
-
 
2224
 
-
 
2225
	switch (fb_format_modifier) {
-
 
2226
	case DRM_FORMAT_MOD_NONE:
-
 
2227
		tile_height = 1;
2123
 * @crtc: crtc for the plane
2228
		break;
-
 
2229
	case I915_FORMAT_MOD_X_TILED:
-
 
2230
		tile_height = IS_GEN2(dev) ? 16 : 8;
-
 
2231
		break;
2124
 *
2232
	case I915_FORMAT_MOD_Y_TILED:
-
 
2233
		tile_height = 32;
2125
 * Enable @plane on @crtc, making sure that the pipe is running first.
2234
		break;
2126
 */
2235
	case I915_FORMAT_MOD_Yf_TILED:
-
 
2236
		pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2127
static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2237
		switch (pixel_bytes) {
2128
					  struct drm_crtc *crtc)
2238
		default:
-
 
2239
		case 1:
-
 
2240
			tile_height = 64;
-
 
2241
			break;
2129
{
2242
		case 2:
-
 
2243
		case 4:
-
 
2244
			tile_height = 32;
2130
	struct drm_device *dev = plane->dev;
2245
			break;
2131
	struct drm_i915_private *dev_priv = dev->dev_private;
2246
		case 8:
-
 
2247
			tile_height = 16;
-
 
2248
			break;
2132
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
		case 16:
2133
 
2250
			WARN_ONCE(1,
-
 
2251
				  "128-bit pixels are not supported for display!");
2134
	/* If the pipe isn't enabled, we can't pump pixels and may hang */
2252
			tile_height = 16;
-
 
2253
			break;
-
 
2254
		}
2135
	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2255
		break;
-
 
2256
	default:
2136
 
2257
		MISSING_CASE(fb_format_modifier);
2137
	if (intel_crtc->primary_enabled)
2258
		tile_height = 1;
2138
		return;
-
 
Line 2139... Line -...
2139
 
-
 
2140
	intel_crtc->primary_enabled = true;
2259
		break;
-
 
2260
	}
Line 2141... Line 2261...
2141
 
2261
 
2142
	dev_priv->display.update_primary_plane(crtc, plane->fb,
2262
	return tile_height;
2143
					       crtc->x, crtc->y);
2263
}
2144
 
-
 
2145
	/*
2264
 
2146
	 * BDW signals flip done immediately if the plane
2265
unsigned int
2147
	 * is disabled, even if the plane enable is already
2266
intel_fb_align_height(struct drm_device *dev, unsigned int height,
2148
	 * armed to occur at the next vblank :(
2267
		      uint32_t pixel_format, uint64_t fb_format_modifier)
Line 2149... Line -...
2149
	 */
-
 
2150
	if (IS_BROADWELL(dev))
-
 
2151
		intel_wait_for_vblank(dev, intel_crtc->pipe);
-
 
2152
}
-
 
2153
 
-
 
2154
/**
-
 
2155
 * intel_disable_primary_hw_plane - disable the primary hardware plane
2268
{
2156
 * @plane: plane to be disabled
2269
	return ALIGN(height, intel_tile_height(dev, pixel_format,
2157
 * @crtc: crtc for the plane
2270
					       fb_format_modifier, 0));
2158
 *
2271
}
2159
 * Disable @plane on @crtc, making sure that the pipe is running first.
-
 
2160
 */
2272
 
2161
static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2273
static int
Line 2162... Line 2274...
2162
					   struct drm_crtc *crtc)
2274
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
Line -... Line 2275...
-
 
2275
			const struct drm_plane_state *plane_state)
-
 
2276
{
-
 
2277
	struct intel_rotation_info *info = &view->rotation_info;
2163
{
2278
	unsigned int tile_height, tile_pitch;
2164
	struct drm_device *dev = plane->dev;
2279
 
Line 2165... Line 2280...
2165
	struct drm_i915_private *dev_priv = dev->dev_private;
2280
	*view = i915_ggtt_view_normal;
Line -... Line 2281...
-
 
2281
 
-
 
2282
	if (!plane_state)
-
 
2283
		return 0;
-
 
2284
 
-
 
2285
	if (!intel_rotation_90_or_270(plane_state->rotation))
-
 
2286
		return 0;
2166
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287
 
-
 
2288
	*view = i915_ggtt_view_rotated;
-
 
2289
 
-
 
2290
	info->height = fb->height;
-
 
2291
	info->pixel_format = fb->pixel_format;
-
 
2292
	info->pitch = fb->pitches[0];
-
 
2293
	info->uv_offset = fb->offsets[1];
-
 
2294
	info->fb_modifier = fb->modifier[0];
-
 
2295
 
-
 
2296
	tile_height = intel_tile_height(fb->dev, fb->pixel_format,
-
 
2297
					fb->modifier[0], 0);
-
 
2298
	tile_pitch = PAGE_SIZE / tile_height;
-
 
2299
	info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2167
 
2300
	info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
-
 
2301
	info->size = info->width_pages * info->height_pages * PAGE_SIZE;
-
 
2302
 
2168
	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2303
	if (info->pixel_format == DRM_FORMAT_NV12) {
Line 2169... Line -...
2169
 
-
 
2170
	if (!intel_crtc->primary_enabled)
-
 
2171
		return;
-
 
2172
 
-
 
2173
	intel_crtc->primary_enabled = false;
2304
		tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2174
 
-
 
2175
	dev_priv->display.update_primary_plane(crtc, plane->fb,
-
 
2176
					       crtc->x, crtc->y);
2305
						fb->modifier[0], 1);
Line 2177... Line 2306...
2177
}
2306
		tile_pitch = PAGE_SIZE / tile_height;
2178
 
2307
		info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
-
 
2308
		info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2179
static bool need_vtd_wa(struct drm_device *dev)
2309
						     tile_height);
2180
{
-
 
-
 
2310
		info->size_uv = info->width_pages_uv * info->height_pages_uv *
-
 
2311
				PAGE_SIZE;
-
 
2312
	}
2181
#ifdef CONFIG_INTEL_IOMMU
2313
 
2182
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2314
	return 0;
-
 
2315
}
-
 
2316
 
2183
		return true;
2317
static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
Line 2184... Line 2318...
2184
#endif
2318
{
2185
	return false;
2319
	if (INTEL_INFO(dev_priv)->gen >= 9)
2186
}
2320
		return 256 * 1024;
-
 
2321
	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2187
 
2322
		 IS_VALLEYVIEW(dev_priv))
-
 
2323
		return 128 * 1024;
2188
static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2324
	else if (INTEL_INFO(dev_priv)->gen >= 4)
2189
{
2325
		return 4 * 1024;
2190
	int tile_height;
2326
	else
2191
 
2327
		return 0;
-
 
2328
}
2192
	tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2329
 
2193
	return ALIGN(height, tile_height);
2330
int
Line 2194... Line 2331...
2194
}
2331
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
Line 2195... Line 2332...
2195
 
2332
			   struct drm_framebuffer *fb,
2196
int
2333
			   const struct drm_plane_state *plane_state,
2197
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
-
 
2198
			   struct drm_framebuffer *fb,
-
 
2199
			   struct intel_engine_cs *pipelined)
-
 
2200
{
2334
			   struct intel_engine_cs *pipelined,
2201
	struct drm_device *dev = fb->dev;
-
 
2202
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
2203
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-
 
2204
	u32 alignment;
-
 
2205
	int ret;
2335
			   struct drm_i915_gem_request **pipelined_request)
2206
 
2336
{
2207
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
	struct drm_device *dev = fb->dev;
2208
 
2338
	struct drm_i915_private *dev_priv = dev->dev_private;
2209
	switch (obj->tiling_mode) {
2339
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2210
	case I915_TILING_NONE:
2340
	struct i915_ggtt_view view;
2211
		if (INTEL_INFO(dev)->gen >= 9)
2341
	u32 alignment;
2212
			alignment = 256 * 1024;
2342
	int ret;
2213
		else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2343
 
2214
			alignment = 128 * 1024;
2344
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
-
 
2345
 
-
 
2346
	switch (fb->modifier[0]) {
2215
		else if (INTEL_INFO(dev)->gen >= 4)
2347
	case DRM_FORMAT_MOD_NONE:
2216
			alignment = 4 * 1024;
2348
		alignment = intel_linear_alignment(dev_priv);
-
 
2349
		break;
-
 
2350
	case I915_FORMAT_MOD_X_TILED:
2217
		else
2351
		if (INTEL_INFO(dev)->gen >= 9)
-
 
2352
			alignment = 256 * 1024;
2218
			alignment = 64 * 1024;
2353
		else {
2219
		break;
2354
			/* pin() will align the object as required by fence */
Line -... Line 2355...
-
 
2355
			alignment = 0;
-
 
2356
		}
-
 
2357
		break;
-
 
2358
	case I915_FORMAT_MOD_Y_TILED:
2220
	case I915_TILING_X:
2359
	case I915_FORMAT_MOD_Yf_TILED:
2221
		if (INTEL_INFO(dev)->gen >= 9)
2360
		if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2222
			alignment = 256 * 1024;
2361
			  "Y tiling bo slipped through, driver bug!\n"))
2223
		else {
2362
			return -EINVAL;
2224
		/* pin() will align the object as required by fence */
2363
		alignment = 1 * 1024 * 1024;
Line 2248... Line 2387...
2248
	 * pin/unpin/fence and not more.
2387
	 * pin/unpin/fence and not more.
2249
	 */
2388
	 */
2250
	intel_runtime_pm_get(dev_priv);
2389
	intel_runtime_pm_get(dev_priv);
Line 2251... Line 2390...
2251
 
2390
 
2252
	dev_priv->mm.interruptible = false;
2391
	dev_priv->mm.interruptible = false;
-
 
2392
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2253
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2393
						   pipelined_request, &view);
2254
	if (ret)
2394
	if (ret)
Line 2255... Line 2395...
2255
		goto err_interruptible;
2395
		goto err_interruptible;
2256
 
2396
 
2257
	/* Install a fence for tiled scan-out. Pre-i965 always needs a
2397
	/* Install a fence for tiled scan-out. Pre-i965 always needs a
2258
	 * fence, whereas 965+ only requires a fence if using
2398
	 * fence, whereas 965+ only requires a fence if using
2259
	 * framebuffer compression.  For simplicity, we always install
2399
	 * framebuffer compression.  For simplicity, we always install
-
 
2400
	 * a fence as the cost is not that onerous.
2260
	 * a fence as the cost is not that onerous.
2401
	 */
-
 
2402
	if (view.type == I915_GGTT_VIEW_NORMAL) {
-
 
2403
		ret = i915_gem_object_get_fence(obj);
-
 
2404
		if (ret == -EDEADLK) {
-
 
2405
			/*
-
 
2406
			 * -EDEADLK means there are no free fences
-
 
2407
			 * no pending flips.
-
 
2408
			 *
-
 
2409
			 * This is propagated to atomic, but it uses
-
 
2410
			 * -EDEADLK to force a locking recovery, so
-
 
2411
			 * change the returned error to -EBUSY.
-
 
2412
			 */
2261
	 */
2413
			ret = -EBUSY;
2262
	ret = i915_gem_object_get_fence(obj);
2414
			goto err_unpin;
Line 2263... Line 2415...
2263
	if (ret)
2415
		} else if (ret)
-
 
2416
			goto err_unpin;
Line 2264... Line 2417...
2264
		goto err_unpin;
2417
 
2265
 
2418
		i915_gem_object_pin_fence(obj);
2266
	i915_gem_object_pin_fence(obj);
2419
	}
Line 2267... Line 2420...
2267
 
2420
 
2268
	dev_priv->mm.interruptible = true;
2421
	dev_priv->mm.interruptible = true;
2269
	intel_runtime_pm_put(dev_priv);
2422
	intel_runtime_pm_put(dev_priv);
2270
	return 0;
2423
	return 0;
2271
 
2424
 
2272
err_unpin:
2425
err_unpin:
2273
	i915_gem_object_unpin_from_display_plane(obj);
2426
	i915_gem_object_unpin_from_display_plane(obj, &view);
Line 2274... Line 2427...
2274
err_interruptible:
2427
err_interruptible:
-
 
2428
	dev_priv->mm.interruptible = true;
2275
	dev_priv->mm.interruptible = true;
2429
	intel_runtime_pm_put(dev_priv);
-
 
2430
	return ret;
-
 
2431
}
-
 
2432
 
-
 
2433
static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2276
	intel_runtime_pm_put(dev_priv);
2434
			       const struct drm_plane_state *plane_state)
Line -... Line 2435...
-
 
2435
{
-
 
2436
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-
 
2437
	struct i915_ggtt_view view;
-
 
2438
	int ret;
2277
	return ret;
2439
 
-
 
2440
	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2278
}
2441
 
2279
 
2442
	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
Line 2280... Line 2443...
2280
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2443
	WARN_ONCE(ret, "Couldn't get view from plane state!");
2281
{
2444
 
2282
	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2445
	if (view.type == I915_GGTT_VIEW_NORMAL)
-
 
2446
		i915_gem_object_unpin_fence(obj);
2283
 
2447
 
2284
	i915_gem_object_unpin_fence(obj);
2448
	i915_gem_object_unpin_from_display_plane(obj, &view);
2285
//	i915_gem_object_unpin_from_display_plane(obj);
2449
}
2286
}
2450
 
2287
 
2451
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
Line 2301... Line 2465...
2301
		tiles = *x / (512/cpp);
2465
		tiles = *x / (512/cpp);
2302
		*x %= 512/cpp;
2466
		*x %= 512/cpp;
Line 2303... Line 2467...
2303
 
2467
 
2304
	return tile_rows * pitch * 8 + tiles * 4096;
2468
		return tile_rows * pitch * 8 + tiles * 4096;
-
 
2469
	} else {
2305
	} else {
2470
		unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
Line 2306... Line 2471...
2306
		unsigned int offset;
2471
		unsigned int offset;
2307
 
2472
 
2308
		offset = *y * pitch + *x * cpp;
2473
		offset = *y * pitch + *x * cpp;
2309
		*y = 0;
2474
		*y = (offset & alignment) / pitch;
2310
		*x = (offset & 4095) / cpp;
2475
		*x = ((offset & alignment) - *y * pitch) / cpp;
2311
		return offset & -4096;
2476
		return offset & ~alignment;
Line 2312... Line 2477...
2312
	}
2477
	}
2313
}
2478
}
2314
 
2479
 
2315
int intel_format_to_fourcc(int format)
2480
static int i9xx_format_to_fourcc(int format)
2316
{
2481
{
2317
	switch (format) {
2482
	switch (format) {
Line 2331... Line 2496...
2331
	case DISPPLANE_RGBX101010:
2496
	case DISPPLANE_RGBX101010:
2332
		return DRM_FORMAT_XBGR2101010;
2497
		return DRM_FORMAT_XBGR2101010;
2333
	}
2498
	}
2334
}
2499
}
Line -... Line 2500...
-
 
2500
 
-
 
2501
static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
-
 
2502
{
-
 
2503
	switch (format) {
-
 
2504
	case PLANE_CTL_FORMAT_RGB_565:
-
 
2505
		return DRM_FORMAT_RGB565;
-
 
2506
	default:
-
 
2507
	case PLANE_CTL_FORMAT_XRGB_8888:
-
 
2508
		if (rgb_order) {
-
 
2509
			if (alpha)
-
 
2510
				return DRM_FORMAT_ABGR8888;
-
 
2511
			else
-
 
2512
				return DRM_FORMAT_XBGR8888;
-
 
2513
		} else {
-
 
2514
			if (alpha)
-
 
2515
				return DRM_FORMAT_ARGB8888;
-
 
2516
			else
-
 
2517
				return DRM_FORMAT_XRGB8888;
-
 
2518
		}
-
 
2519
	case PLANE_CTL_FORMAT_XRGB_2101010:
-
 
2520
		if (rgb_order)
-
 
2521
			return DRM_FORMAT_XBGR2101010;
-
 
2522
		else
-
 
2523
			return DRM_FORMAT_XRGB2101010;
-
 
2524
	}
-
 
2525
}
-
 
2526
 
2335
 
2527
static bool
2336
static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2528
intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2337
				  struct intel_plane_config *plane_config)
2529
			      struct intel_initial_plane_config *plane_config)
2338
{
2530
{
-
 
2531
	struct drm_device *dev = crtc->base.dev;
2339
	struct drm_device *dev = crtc->base.dev;
2532
	struct drm_i915_private *dev_priv = to_i915(dev);
2340
	struct drm_i915_gem_object *obj = NULL;
2533
	struct drm_i915_gem_object *obj = NULL;
2341
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2534
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
-
 
2535
	struct drm_framebuffer *fb = &plane_config->fb->base;
-
 
2536
	u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
-
 
2537
	u32 size_aligned = round_up(plane_config->base + plane_config->size,
-
 
2538
				    PAGE_SIZE);
-
 
2539
 
Line 2342... Line 2540...
2342
	u32 base = plane_config->base;
2540
	size_aligned -= base_aligned;
2343
 
2541
 
Line 2344... Line 2542...
2344
	if (plane_config->size == 0)
2542
	if (plane_config->size == 0)
2345
		return false;
2543
		return false;
2346
 
2544
 
-
 
2545
	/* If the FB is too big, just don't use it since fbdev is not very
2347
	obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2546
	 * important and we should probably use that space with FBC or other
Line 2348... Line 2547...
2348
							     plane_config->size);
2547
	 * features. */
2349
	if (!obj)
2548
	if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2350
		return false;
-
 
2351
 
2549
		return false;
2352
    obj->map_and_fenceable=true;
2550
 
2353
    main_fb_obj = obj;
-
 
2354
 
2551
	obj = i915_gem_object_create_stolen_for_preallocated(dev,
-
 
2552
							     base_aligned,
Line -... Line 2553...
-
 
2553
							     base_aligned,
-
 
2554
							     size_aligned);
-
 
2555
	if (!obj)
-
 
2556
		return false;
2355
	if (plane_config->tiled) {
2557
 
2356
		obj->tiling_mode = I915_TILING_X;
2558
	obj->tiling_mode = plane_config->tiling;
2357
		obj->stride = crtc->base.primary->fb->pitches[0];
2559
	if (obj->tiling_mode == I915_TILING_X)
2358
	}
2560
		obj->stride = fb->pitches[0];
-
 
2561
 
-
 
2562
	mode_cmd.pixel_format = fb->pixel_format;
Line 2359... Line 2563...
2359
 
2563
	mode_cmd.width = fb->width;
2360
	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
-
 
2361
	mode_cmd.width = crtc->base.primary->fb->width;
2564
	mode_cmd.height = fb->height;
2362
	mode_cmd.height = crtc->base.primary->fb->height;
2565
	mode_cmd.pitches[0] = fb->pitches[0];
2363
	mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2566
	mode_cmd.modifier[0] = fb->modifier[0];
2364
 
2567
	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2365
	mutex_lock(&dev->struct_mutex);
2568
 
2366
 
-
 
2367
	if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
-
 
2368
				   &mode_cmd, obj)) {
2569
	mutex_lock(&dev->struct_mutex);
Line 2369... Line 2570...
2369
		DRM_DEBUG_KMS("intel fb init failed\n");
2570
	if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2370
		goto out_unref_obj;
2571
				   &mode_cmd, obj)) {
Line 2371... Line 2572...
2371
	}
2572
		DRM_DEBUG_KMS("intel fb init failed\n");
2372
 
2573
		goto out_unref_obj;
2373
	obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2574
	}
2374
	mutex_unlock(&dev->struct_mutex);
2575
	mutex_unlock(&dev->struct_mutex);
2375
 
2576
 
Line -... Line 2577...
-
 
2577
	DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
-
 
2578
	return true;
-
 
2579
 
-
 
2580
out_unref_obj:
-
 
2581
	drm_gem_object_unreference(&obj->base);
-
 
2582
	mutex_unlock(&dev->struct_mutex);
-
 
2583
	return false;
-
 
2584
}
-
 
2585
 
-
 
2586
/* Update plane->state->fb to match plane->fb after driver-internal updates */
-
 
2587
static void
-
 
2588
update_state_fb(struct drm_plane *plane)
-
 
2589
{
-
 
2590
	if (plane->fb == plane->state->fb)
-
 
2591
		return;
2376
	DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2592
 
2377
	return true;
2593
	if (plane->state->fb)
2378
 
2594
		drm_framebuffer_unreference(plane->state->fb);
2379
out_unref_obj:
2595
	plane->state->fb = plane->fb;
2380
	drm_gem_object_unreference(&obj->base);
2596
	if (plane->state->fb)
2381
	mutex_unlock(&dev->struct_mutex);
2597
		drm_framebuffer_reference(plane->state->fb);
2382
	return false;
2598
}
2383
}
2599
 
-
 
2600
static void
-
 
2601
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
-
 
2602
			     struct intel_initial_plane_config *plane_config)
-
 
2603
{
-
 
2604
	struct drm_device *dev = intel_crtc->base.dev;
Line 2384... Line 2605...
2384
 
2605
	struct drm_i915_private *dev_priv = dev->dev_private;
2385
static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2606
	struct drm_crtc *c;
Line 2386... Line 2607...
2386
				 struct intel_plane_config *plane_config)
2607
	struct intel_crtc *i;
-
 
2608
	struct drm_i915_gem_object *obj;
2387
{
2609
	struct drm_plane *primary = intel_crtc->base.primary;
-
 
2610
	struct drm_plane_state *plane_state = primary->state;
Line 2388... Line 2611...
2388
	struct drm_device *dev = intel_crtc->base.dev;
2611
	struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2389
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
Line 2390... Line 2612...
2390
	struct drm_crtc *c;
2612
	struct intel_plane *intel_plane = to_intel_plane(primary);
2391
	struct intel_crtc *i;
2613
	struct drm_framebuffer *fb;
2392
	struct drm_i915_gem_object *obj;
2614
 
2393
 
2615
	if (!plane_config->fb)
Line 2411... Line 2633...
2411
			continue;
2633
			continue;
Line 2412... Line 2634...
2412
 
2634
 
2413
		if (!i->active)
2635
		if (!i->active)
Line 2414... Line 2636...
2414
			continue;
2636
			continue;
2415
 
2637
 
2416
		obj = intel_fb_obj(c->primary->fb);
2638
		fb = c->primary->fb;
Line -... Line 2639...
-
 
2639
		if (!fb)
2417
		if (obj == NULL)
2640
			continue;
-
 
2641
 
-
 
2642
		obj = intel_fb_obj(fb);
-
 
2643
		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
-
 
2644
			drm_framebuffer_reference(fb);
-
 
2645
			goto valid_fb;
-
 
2646
		}
-
 
2647
	}
-
 
2648
 
-
 
2649
	/*
-
 
2650
	 * We've failed to reconstruct the BIOS FB.  Current display state
-
 
2651
	 * indicates that the primary plane is visible, but has a NULL FB,
-
 
2652
	 * which will lead to problems later if we don't fix it up.  The
-
 
2653
	 * simplest solution is to just disable the primary plane now and
-
 
2654
	 * pretend the BIOS never had it enabled.
-
 
2655
	 */
-
 
2656
	to_intel_plane_state(plane_state)->visible = false;
-
 
2657
	crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
-
 
2658
	intel_pre_disable_primary(&intel_crtc->base);
-
 
2659
	intel_plane->disable_plane(primary, &intel_crtc->base);
-
 
2660
 
-
 
2661
	return;
-
 
2662
 
-
 
2663
valid_fb:
-
 
2664
	plane_state->src_x = 0;
-
 
2665
	plane_state->src_y = 0;
-
 
2666
	plane_state->src_w = fb->width << 16;
-
 
2667
	plane_state->src_h = fb->height << 16;
-
 
2668
 
-
 
2669
	plane_state->crtc_x = 0;
-
 
2670
	plane_state->crtc_y = 0;
-
 
2671
	plane_state->crtc_w = fb->width;
2418
			continue;
2672
	plane_state->crtc_h = fb->height;
2419
 
2673
 
Line 2420... Line 2674...
2420
		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2674
	obj = intel_fb_obj(fb);
2421
			if (obj->tiling_mode != I915_TILING_NONE)
2675
	if (obj->tiling_mode != I915_TILING_NONE)
-
 
2676
		dev_priv->preserve_bios_swizzle = true;
-
 
2677
 
2422
				dev_priv->preserve_bios_swizzle = true;
2678
	drm_framebuffer_reference(fb);
2423
 
-
 
2424
			drm_framebuffer_reference(c->primary->fb);
-
 
2425
			intel_crtc->base.primary->fb = c->primary->fb;
-
 
2426
			obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2679
	primary->fb = primary->state->fb = fb;
Line 2427... Line 2680...
2427
			break;
2680
	primary->crtc = primary->state->crtc = &intel_crtc->base;
2428
		}
2681
	intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2429
	}
2682
	obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2430
}
2683
}
2431
 
2684
 
2432
static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2685
static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2433
				     struct drm_framebuffer *fb,
2686
				      struct drm_framebuffer *fb,
-
 
2687
				      int x, int y)
-
 
2688
{
2434
				     int x, int y)
2689
	struct drm_device *dev = crtc->dev;
2435
{
2690
	struct drm_i915_private *dev_priv = dev->dev_private;
2436
    struct drm_device *dev = crtc->dev;
2691
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437
    struct drm_i915_private *dev_priv = dev->dev_private;
2692
	struct drm_plane *primary = crtc->primary;
2438
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693
	bool visible = to_intel_plane_state(primary->state)->visible;
2439
	struct drm_i915_gem_object *obj;
2694
	struct drm_i915_gem_object *obj;
Line 2440... Line 2695...
2440
    int plane = intel_crtc->plane;
2695
	int plane = intel_crtc->plane;
2441
	unsigned long linear_offset;
2696
	unsigned long linear_offset;
2442
    u32 dspcntr;
2697
	u32 dspcntr;
2443
	u32 reg = DSPCNTR(plane);
2698
	u32 reg = DSPCNTR(plane);
2444
	int pixel_size;
2699
	int pixel_size;
2445
 
2700
 
Line 2469... Line 2724...
2469
 
2724
 
2470
		/* pipesrc and dspsize control the size that is scaled from,
2725
		/* pipesrc and dspsize control the size that is scaled from,
2471
		 * which should always be the user's requested size.
2726
		 * which should always be the user's requested size.
2472
		 */
2727
		 */
2473
		I915_WRITE(DSPSIZE(plane),
2728
		I915_WRITE(DSPSIZE(plane),
2474
			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
2729
			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
2475
			   (intel_crtc->config.pipe_src_w - 1));
2730
			   (intel_crtc->config->pipe_src_w - 1));
2476
		I915_WRITE(DSPPOS(plane), 0);
2731
		I915_WRITE(DSPPOS(plane), 0);
2477
	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2732
	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2478
		I915_WRITE(PRIMSIZE(plane),
2733
		I915_WRITE(PRIMSIZE(plane),
2479
			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
2734
			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
2480
			   (intel_crtc->config.pipe_src_w - 1));
2735
			   (intel_crtc->config->pipe_src_w - 1));
2481
		I915_WRITE(PRIMPOS(plane), 0);
2736
		I915_WRITE(PRIMPOS(plane), 0);
2482
		I915_WRITE(PRIMCNSTALPHA(plane), 0);
2737
		I915_WRITE(PRIMCNSTALPHA(plane), 0);
Line 2483... Line 2738...
2483
	}
2738
	}
2484
 
2739
 
2485
	switch (fb->pixel_format) {
2740
	switch (fb->pixel_format) {
2486
	case DRM_FORMAT_C8:
2741
	case DRM_FORMAT_C8:
2487
        dspcntr |= DISPPLANE_8BPP;
2742
		dspcntr |= DISPPLANE_8BPP;
2488
        break;
-
 
2489
	case DRM_FORMAT_XRGB1555:
2743
		break;
2490
	case DRM_FORMAT_ARGB1555:
2744
	case DRM_FORMAT_XRGB1555:
2491
		dspcntr |= DISPPLANE_BGRX555;
2745
		dspcntr |= DISPPLANE_BGRX555;
2492
		break;
2746
		break;
2493
	case DRM_FORMAT_RGB565:
2747
	case DRM_FORMAT_RGB565:
2494
		dspcntr |= DISPPLANE_BGRX565;
2748
		dspcntr |= DISPPLANE_BGRX565;
2495
		break;
-
 
2496
	case DRM_FORMAT_XRGB8888:
2749
		break;
2497
	case DRM_FORMAT_ARGB8888:
2750
	case DRM_FORMAT_XRGB8888:
2498
		dspcntr |= DISPPLANE_BGRX888;
2751
		dspcntr |= DISPPLANE_BGRX888;
2499
		break;
-
 
2500
	case DRM_FORMAT_XBGR8888:
2752
		break;
2501
	case DRM_FORMAT_ABGR8888:
2753
	case DRM_FORMAT_XBGR8888:
2502
		dspcntr |= DISPPLANE_RGBX888;
2754
		dspcntr |= DISPPLANE_RGBX888;
2503
		break;
-
 
2504
	case DRM_FORMAT_XRGB2101010:
2755
		break;
2505
	case DRM_FORMAT_ARGB2101010:
2756
	case DRM_FORMAT_XRGB2101010:
2506
		dspcntr |= DISPPLANE_BGRX101010;
2757
		dspcntr |= DISPPLANE_BGRX101010;
2507
        break;
-
 
2508
	case DRM_FORMAT_XBGR2101010:
2758
		break;
2509
	case DRM_FORMAT_ABGR2101010:
2759
	case DRM_FORMAT_XBGR2101010:
2510
		dspcntr |= DISPPLANE_RGBX101010;
2760
		dspcntr |= DISPPLANE_RGBX101010;
2511
        break;
2761
		break;
2512
    default:
2762
	default:
Line 2522... Line 2772...
2522
 
2772
 
Line 2523... Line 2773...
2523
	linear_offset = y * fb->pitches[0] + x * pixel_size;
2773
	linear_offset = y * fb->pitches[0] + x * pixel_size;
2524
 
2774
 
2525
	if (INTEL_INFO(dev)->gen >= 4) {
2775
	if (INTEL_INFO(dev)->gen >= 4) {
-
 
2776
		intel_crtc->dspaddr_offset =
2526
		intel_crtc->dspaddr_offset =
2777
			intel_gen4_compute_page_offset(dev_priv,
2527
			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2778
						       &x, &y, obj->tiling_mode,
2528
						       pixel_size,
2779
						       pixel_size,
2529
							   fb->pitches[0]);
2780
						       fb->pitches[0]);
2530
		linear_offset -= intel_crtc->dspaddr_offset;
2781
		linear_offset -= intel_crtc->dspaddr_offset;
2531
	} else {
2782
	} else {
Line 2532... Line 2783...
2532
		intel_crtc->dspaddr_offset = linear_offset;
2783
		intel_crtc->dspaddr_offset = linear_offset;
2533
	}
2784
	}
Line 2534... Line 2785...
2534
 
2785
 
2535
	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2786
	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Line 2536... Line 2787...
2536
		dspcntr |= DISPPLANE_ROTATE_180;
2787
		dspcntr |= DISPPLANE_ROTATE_180;
2537
 
2788
 
2538
		x += (intel_crtc->config.pipe_src_w - 1);
2789
		x += (intel_crtc->config->pipe_src_w - 1);
2539
		y += (intel_crtc->config.pipe_src_h - 1);
2790
		y += (intel_crtc->config->pipe_src_h - 1);
2540
 
2791
 
2541
		/* Finding the last pixel of the last line of the display
2792
		/* Finding the last pixel of the last line of the display
Line -... Line 2793...
-
 
2793
		data and adding to linear_offset*/
-
 
2794
		linear_offset +=
-
 
2795
			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2542
		data and adding to linear_offset*/
2796
			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
Line 2543... Line -...
2543
		linear_offset +=
-
 
2544
			(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
-
 
2545
			(intel_crtc->config.pipe_src_w - 1) * pixel_size;
-
 
2546
	}
2797
	}
2547
 
2798
 
2548
	I915_WRITE(reg, dspcntr);
2799
	intel_crtc->adjusted_x = x;
2549
 
2800
	intel_crtc->adjusted_y = y;
2550
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2801
 
Line 2566... Line 2817...
2566
					 int x, int y)
2817
					  int x, int y)
2567
{
2818
{
2568
    struct drm_device *dev = crtc->dev;
2819
	struct drm_device *dev = crtc->dev;
2569
    struct drm_i915_private *dev_priv = dev->dev_private;
2820
	struct drm_i915_private *dev_priv = dev->dev_private;
2570
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
2822
	struct drm_plane *primary = crtc->primary;
-
 
2823
	bool visible = to_intel_plane_state(primary->state)->visible;
2571
	struct drm_i915_gem_object *obj;
2824
	struct drm_i915_gem_object *obj;
2572
    int plane = intel_crtc->plane;
2825
	int plane = intel_crtc->plane;
2573
	unsigned long linear_offset;
2826
	unsigned long linear_offset;
2574
    u32 dspcntr;
2827
	u32 dspcntr;
2575
	u32 reg = DSPCNTR(plane);
2828
	u32 reg = DSPCNTR(plane);
2576
	int pixel_size;
2829
	int pixel_size;
Line 2577... Line 2830...
2577
 
2830
 
2578
	if (!intel_crtc->primary_enabled) {
2831
	if (!visible || !fb) {
2579
		I915_WRITE(reg, 0);
2832
		I915_WRITE(reg, 0);
2580
		I915_WRITE(DSPSURF(plane), 0);
2833
		I915_WRITE(DSPSURF(plane), 0);
2581
		POSTING_READ(reg);
2834
		POSTING_READ(reg);
2582
		return;
2835
		return;
Line 2601... Line 2854...
2601
        break;
2854
		break;
2602
	case DRM_FORMAT_RGB565:
2855
	case DRM_FORMAT_RGB565:
2603
		dspcntr |= DISPPLANE_BGRX565;
2856
		dspcntr |= DISPPLANE_BGRX565;
2604
        break;
2857
		break;
2605
	case DRM_FORMAT_XRGB8888:
2858
	case DRM_FORMAT_XRGB8888:
2606
	case DRM_FORMAT_ARGB8888:
-
 
2607
		dspcntr |= DISPPLANE_BGRX888;
2859
		dspcntr |= DISPPLANE_BGRX888;
2608
		break;
2860
		break;
2609
	case DRM_FORMAT_XBGR8888:
2861
	case DRM_FORMAT_XBGR8888:
2610
	case DRM_FORMAT_ABGR8888:
-
 
2611
		dspcntr |= DISPPLANE_RGBX888;
2862
		dspcntr |= DISPPLANE_RGBX888;
2612
		break;
2863
		break;
2613
	case DRM_FORMAT_XRGB2101010:
2864
	case DRM_FORMAT_XRGB2101010:
2614
	case DRM_FORMAT_ARGB2101010:
-
 
2615
		dspcntr |= DISPPLANE_BGRX101010;
2865
		dspcntr |= DISPPLANE_BGRX101010;
2616
		break;
2866
		break;
2617
	case DRM_FORMAT_XBGR2101010:
2867
	case DRM_FORMAT_XBGR2101010:
2618
	case DRM_FORMAT_ABGR2101010:
-
 
2619
		dspcntr |= DISPPLANE_RGBX101010;
2868
		dspcntr |= DISPPLANE_RGBX101010;
2620
        break;
2869
		break;
2621
    default:
2870
	default:
2622
		BUG();
2871
		BUG();
2623
    }
2872
	}
Line 2628... Line 2877...
2628
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2877
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2629
    dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2878
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Line 2630... Line 2879...
2630
 
2879
 
2631
	linear_offset = y * fb->pitches[0] + x * pixel_size;
2880
	linear_offset = y * fb->pitches[0] + x * pixel_size;
2632
	intel_crtc->dspaddr_offset =
2881
	intel_crtc->dspaddr_offset =
-
 
2882
		intel_gen4_compute_page_offset(dev_priv,
2633
		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2883
					       &x, &y, obj->tiling_mode,
2634
					       pixel_size,
2884
					       pixel_size,
2635
						   fb->pitches[0]);
2885
					       fb->pitches[0]);
2636
	linear_offset -= intel_crtc->dspaddr_offset;
2886
	linear_offset -= intel_crtc->dspaddr_offset;
2637
	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2887
	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Line 2638... Line 2888...
2638
		dspcntr |= DISPPLANE_ROTATE_180;
2888
		dspcntr |= DISPPLANE_ROTATE_180;
2639
 
2889
 
2640
		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2890
		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
Line 2641... Line 2891...
2641
			x += (intel_crtc->config.pipe_src_w - 1);
2891
			x += (intel_crtc->config->pipe_src_w - 1);
2642
			y += (intel_crtc->config.pipe_src_h - 1);
2892
			y += (intel_crtc->config->pipe_src_h - 1);
2643
 
2893
 
2644
			/* Finding the last pixel of the last line of the display
2894
			/* Finding the last pixel of the last line of the display
2645
			data and adding to linear_offset*/
2895
			data and adding to linear_offset*/
2646
			linear_offset +=
2896
			linear_offset +=
2647
				(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2897
				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
Line -... Line 2898...
-
 
2898
				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
-
 
2899
		}
-
 
2900
	}
2648
				(intel_crtc->config.pipe_src_w - 1) * pixel_size;
2901
 
Line 2649... Line -...
2649
		}
-
 
2650
	}
-
 
2651
 
-
 
2652
	I915_WRITE(reg, dspcntr);
2902
	intel_crtc->adjusted_x = x;
2653
 
2903
	intel_crtc->adjusted_y = y;
2654
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2904
 
2655
		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2905
	I915_WRITE(reg, dspcntr);
2656
		      fb->pitches[0]);
2906
 
Line 2664... Line 2914...
2664
	I915_WRITE(DSPLINOFF(plane), linear_offset);
2914
		I915_WRITE(DSPLINOFF(plane), linear_offset);
2665
	}
2915
	}
2666
	POSTING_READ(reg);
2916
	POSTING_READ(reg);
2667
}
2917
}
Line -... Line 2918...
-
 
2918
 
-
 
2919
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
-
 
2920
			      uint32_t pixel_format)
-
 
2921
{
-
 
2922
	u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
-
 
2923
 
-
 
2924
	/*
-
 
2925
	 * The stride is either expressed as a multiple of 64 bytes
-
 
2926
	 * chunks for linear buffers or in number of tiles for tiled
-
 
2927
	 * buffers.
-
 
2928
	 */
-
 
2929
	switch (fb_modifier) {
-
 
2930
	case DRM_FORMAT_MOD_NONE:
-
 
2931
		return 64;
-
 
2932
	case I915_FORMAT_MOD_X_TILED:
-
 
2933
		if (INTEL_INFO(dev)->gen == 2)
-
 
2934
			return 128;
-
 
2935
		return 512;
-
 
2936
	case I915_FORMAT_MOD_Y_TILED:
-
 
2937
		/* No need to check for old gens and Y tiling since this is
-
 
2938
		 * about the display engine and those will be blocked before
-
 
2939
		 * we get here.
-
 
2940
		 */
-
 
2941
		return 128;
-
 
2942
	case I915_FORMAT_MOD_Yf_TILED:
-
 
2943
		if (bits_per_pixel == 8)
-
 
2944
			return 64;
-
 
2945
		else
-
 
2946
			return 128;
-
 
2947
	default:
-
 
2948
		MISSING_CASE(fb_modifier);
-
 
2949
		return 64;
-
 
2950
	}
-
 
2951
}
-
 
2952
 
-
 
2953
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
-
 
2954
				     struct drm_i915_gem_object *obj,
-
 
2955
				     unsigned int plane)
-
 
2956
{
-
 
2957
	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
-
 
2958
	struct i915_vma *vma;
-
 
2959
	unsigned char *offset;
-
 
2960
 
-
 
2961
	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
-
 
2962
		view = &i915_ggtt_view_rotated;
-
 
2963
 
-
 
2964
	vma = i915_gem_obj_to_ggtt_view(obj, view);
-
 
2965
	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
-
 
2966
		view->type))
-
 
2967
		return -1;
-
 
2968
 
-
 
2969
	offset = (unsigned char *)vma->node.start;
-
 
2970
 
-
 
2971
	if (plane == 1) {
-
 
2972
		offset += vma->ggtt_view.rotation_info.uv_start_page *
-
 
2973
			  PAGE_SIZE;
-
 
2974
	}
-
 
2975
 
-
 
2976
	return (unsigned long)offset;
-
 
2977
}
-
 
2978
 
-
 
2979
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
-
 
2980
{
-
 
2981
	struct drm_device *dev = intel_crtc->base.dev;
-
 
2982
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
2983
 
-
 
2984
	I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
-
 
2985
	I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
-
 
2986
	I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
-
 
2987
}
-
 
2988
 
-
 
2989
/*
-
 
2990
 * This function detaches (aka. unbinds) unused scalers in hardware
-
 
2991
 */
-
 
2992
static void skl_detach_scalers(struct intel_crtc *intel_crtc)
-
 
2993
{
-
 
2994
	struct intel_crtc_scaler_state *scaler_state;
-
 
2995
	int i;
-
 
2996
 
-
 
2997
	scaler_state = &intel_crtc->config->scaler_state;
-
 
2998
 
-
 
2999
	/* loop through and disable scalers that aren't in use */
-
 
3000
	for (i = 0; i < intel_crtc->num_scalers; i++) {
-
 
3001
		if (!scaler_state->scalers[i].in_use)
-
 
3002
			skl_detach_scaler(intel_crtc, i);
-
 
3003
	}
-
 
3004
}
-
 
3005
 
-
 
3006
u32 skl_plane_ctl_format(uint32_t pixel_format)
-
 
3007
{
-
 
3008
	switch (pixel_format) {
-
 
3009
	case DRM_FORMAT_C8:
-
 
3010
		return PLANE_CTL_FORMAT_INDEXED;
-
 
3011
	case DRM_FORMAT_RGB565:
-
 
3012
		return PLANE_CTL_FORMAT_RGB_565;
-
 
3013
	case DRM_FORMAT_XBGR8888:
-
 
3014
		return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
-
 
3015
	case DRM_FORMAT_XRGB8888:
-
 
3016
		return PLANE_CTL_FORMAT_XRGB_8888;
-
 
3017
	/*
-
 
3018
	 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-
 
3019
	 * to be already pre-multiplied. We need to add a knob (or a different
-
 
3020
	 * DRM_FORMAT) for user-space to configure that.
-
 
3021
	 */
-
 
3022
	case DRM_FORMAT_ABGR8888:
-
 
3023
		return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
-
 
3024
			PLANE_CTL_ALPHA_SW_PREMULTIPLY;
-
 
3025
	case DRM_FORMAT_ARGB8888:
-
 
3026
		return PLANE_CTL_FORMAT_XRGB_8888 |
-
 
3027
			PLANE_CTL_ALPHA_SW_PREMULTIPLY;
-
 
3028
	case DRM_FORMAT_XRGB2101010:
-
 
3029
		return PLANE_CTL_FORMAT_XRGB_2101010;
-
 
3030
	case DRM_FORMAT_XBGR2101010:
-
 
3031
		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
-
 
3032
	case DRM_FORMAT_YUYV:
-
 
3033
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
-
 
3034
	case DRM_FORMAT_YVYU:
-
 
3035
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
-
 
3036
	case DRM_FORMAT_UYVY:
-
 
3037
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
-
 
3038
	case DRM_FORMAT_VYUY:
-
 
3039
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
-
 
3040
	default:
-
 
3041
		MISSING_CASE(pixel_format);
-
 
3042
	}
-
 
3043
 
-
 
3044
	return 0;
-
 
3045
}
-
 
3046
 
-
 
3047
u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
-
 
3048
{
-
 
3049
	switch (fb_modifier) {
-
 
3050
	case DRM_FORMAT_MOD_NONE:
-
 
3051
		break;
-
 
3052
	case I915_FORMAT_MOD_X_TILED:
-
 
3053
		return PLANE_CTL_TILED_X;
-
 
3054
	case I915_FORMAT_MOD_Y_TILED:
-
 
3055
		return PLANE_CTL_TILED_Y;
-
 
3056
	case I915_FORMAT_MOD_Yf_TILED:
-
 
3057
		return PLANE_CTL_TILED_YF;
-
 
3058
	default:
-
 
3059
		MISSING_CASE(fb_modifier);
-
 
3060
	}
-
 
3061
 
-
 
3062
	return 0;
-
 
3063
}
-
 
3064
 
-
 
3065
u32 skl_plane_ctl_rotation(unsigned int rotation)
-
 
3066
{
-
 
3067
	switch (rotation) {
-
 
3068
	case BIT(DRM_ROTATE_0):
-
 
3069
		break;
-
 
3070
	/*
-
 
3071
	 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
-
 
3072
	 * while i915 HW rotation is clockwise, thats why this swapping.
-
 
3073
	 */
-
 
3074
	case BIT(DRM_ROTATE_90):
-
 
3075
		return PLANE_CTL_ROTATE_270;
-
 
3076
	case BIT(DRM_ROTATE_180):
-
 
3077
		return PLANE_CTL_ROTATE_180;
-
 
3078
	case BIT(DRM_ROTATE_270):
-
 
3079
		return PLANE_CTL_ROTATE_90;
-
 
3080
	default:
-
 
3081
		MISSING_CASE(rotation);
-
 
3082
	}
-
 
3083
 
-
 
3084
	return 0;
-
 
3085
}
2668
 
3086
 
2669
static void skylake_update_primary_plane(struct drm_crtc *crtc,
3087
static void skylake_update_primary_plane(struct drm_crtc *crtc,
2670
					 struct drm_framebuffer *fb,
3088
					 struct drm_framebuffer *fb,
2671
					 int x, int y)
3089
					 int x, int y)
2672
{
3090
{
2673
	struct drm_device *dev = crtc->dev;
3091
	struct drm_device *dev = crtc->dev;
2674
	struct drm_i915_private *dev_priv = dev->dev_private;
3092
	struct drm_i915_private *dev_priv = dev->dev_private;
2675
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
3094
	struct drm_plane *plane = crtc->primary;
2676
	struct intel_framebuffer *intel_fb;
3095
	bool visible = to_intel_plane_state(plane->state)->visible;
2677
	struct drm_i915_gem_object *obj;
3096
	struct drm_i915_gem_object *obj;
2678
	int pipe = intel_crtc->pipe;
3097
	int pipe = intel_crtc->pipe;
-
 
3098
	u32 plane_ctl, stride_div, stride;
-
 
3099
	u32 tile_height, plane_offset, plane_size;
-
 
3100
	unsigned int rotation;
-
 
3101
	int x_offset, y_offset;
-
 
3102
	unsigned long surf_addr;
-
 
3103
	struct intel_crtc_state *crtc_state = intel_crtc->config;
-
 
3104
	struct intel_plane_state *plane_state;
-
 
3105
	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
-
 
3106
	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
Line -... Line 3107...
-
 
3107
	int scaler_id = -1;
-
 
3108
 
2679
	u32 plane_ctl, stride;
3109
	plane_state = to_intel_plane_state(plane->state);
2680
 
3110
 
2681
	if (!intel_crtc->primary_enabled) {
3111
	if (!visible || !fb) {
2682
		I915_WRITE(PLANE_CTL(pipe, 0), 0);
3112
		I915_WRITE(PLANE_CTL(pipe, 0), 0);
2683
		I915_WRITE(PLANE_SURF(pipe, 0), 0);
3113
		I915_WRITE(PLANE_SURF(pipe, 0), 0);
2684
		POSTING_READ(PLANE_CTL(pipe, 0));
3114
		POSTING_READ(PLANE_CTL(pipe, 0));
Line 2685... Line 3115...
2685
		return;
3115
		return;
2686
	}
3116
	}
2687
 
3117
 
Line 2688... Line -...
2688
	plane_ctl = PLANE_CTL_ENABLE |
-
 
2689
		    PLANE_CTL_PIPE_GAMMA_ENABLE |
-
 
2690
		    PLANE_CTL_PIPE_CSC_ENABLE;
-
 
2691
 
-
 
2692
	switch (fb->pixel_format) {
-
 
2693
	case DRM_FORMAT_RGB565:
3118
	plane_ctl = PLANE_CTL_ENABLE |
2694
		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
-
 
2695
		break;
-
 
2696
	case DRM_FORMAT_XRGB8888:
-
 
2697
		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
-
 
2698
		break;
-
 
2699
	case DRM_FORMAT_XBGR8888:
-
 
2700
		plane_ctl |= PLANE_CTL_ORDER_RGBX;
3119
		    PLANE_CTL_PIPE_GAMMA_ENABLE |
2701
		plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
-
 
2702
		break;
-
 
2703
	case DRM_FORMAT_XRGB2101010:
3120
		    PLANE_CTL_PIPE_CSC_ENABLE;
2704
		plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
-
 
2705
		break;
-
 
2706
	case DRM_FORMAT_XBGR2101010:
-
 
2707
		plane_ctl |= PLANE_CTL_ORDER_RGBX;
-
 
2708
		plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
-
 
Line 2709... Line 3121...
2709
		break;
3121
 
2710
	default:
3122
	plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
Line -... Line 3123...
-
 
3123
	plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
-
 
3124
	plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
-
 
3125
 
-
 
3126
	rotation = plane->state->rotation;
2711
		BUG();
3127
	plane_ctl |= skl_plane_ctl_rotation(rotation);
2712
	}
3128
 
-
 
3129
	obj = intel_fb_obj(fb);
-
 
3130
	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
-
 
3131
					       fb->pixel_format);
-
 
3132
	surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
2713
 
3133
 
-
 
3134
	WARN_ON(drm_rect_width(&plane_state->src) == 0);
-
 
3135
 
-
 
3136
	scaler_id = plane_state->scaler_id;
-
 
3137
	src_x = plane_state->src.x1 >> 16;
-
 
3138
	src_y = plane_state->src.y1 >> 16;
2714
	intel_fb = to_intel_framebuffer(fb);
3139
	src_w = drm_rect_width(&plane_state->src) >> 16;
2715
	obj = intel_fb->obj;
3140
	src_h = drm_rect_height(&plane_state->src) >> 16;
-
 
3141
	dst_x = plane_state->dst.x1;
2716
 
3142
	dst_y = plane_state->dst.y1;
2717
	/*
3143
	dst_w = drm_rect_width(&plane_state->dst);
-
 
3144
	dst_h = drm_rect_height(&plane_state->dst);
2718
	 * The stride is either expressed as a multiple of 64 bytes chunks for
3145
 
-
 
3146
	WARN_ON(x != src_x || y != src_y);
-
 
3147
 
2719
	 * linear buffers or in number of tiles for tiled buffers.
3148
	if (intel_rotation_90_or_270(rotation)) {
2720
	 */
3149
		/* stride = Surface height in tiles */
-
 
3150
		tile_height = intel_tile_height(dev, fb->pixel_format,
2721
	switch (obj->tiling_mode) {
3151
						fb->modifier[0], 0);
2722
	case I915_TILING_NONE:
3152
		stride = DIV_ROUND_UP(fb->height, tile_height);
2723
		stride = fb->pitches[0] >> 6;
3153
		x_offset = stride * tile_height - y - src_h;
2724
		break;
3154
		y_offset = x;
2725
	case I915_TILING_X:
3155
		plane_size = (src_w - 1) << 16 | (src_h - 1);
-
 
3156
	} else {
Line 2726... Line 3157...
2726
		plane_ctl |= PLANE_CTL_TILED_X;
3157
		stride = fb->pitches[0] / stride_div;
2727
		stride = fb->pitches[0] >> 9;
-
 
2728
		break;
3158
		x_offset = x;
Line 2729... Line 3159...
2729
	default:
3159
		y_offset = y;
-
 
3160
		plane_size = (src_h - 1) << 16 | (src_w - 1);
-
 
3161
	}
-
 
3162
	plane_offset = y_offset << 16 | x_offset;
Line 2730... Line -...
2730
		BUG();
-
 
2731
	}
-
 
2732
 
3163
 
2733
	plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3164
	intel_crtc->adjusted_x = x_offset;
Line -... Line 3165...
-
 
3165
	intel_crtc->adjusted_y = y_offset;
-
 
3166
 
-
 
3167
	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-
 
3168
	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
-
 
3169
	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
-
 
3170
	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
-
 
3171
 
2734
	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
3172
	if (scaler_id >= 0) {
-
 
3173
		uint32_t ps_ctrl = 0;
2735
		plane_ctl |= PLANE_CTL_ROTATE_180;
3174
 
2736
 
-
 
2737
	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
-
 
2738
 
-
 
-
 
3175
		WARN_ON(!dst_w || !dst_h);
-
 
3176
		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
2739
	DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
3177
			crtc_state->scaler_state.scalers[scaler_id].mode;
2740
		      i915_gem_obj_ggtt_offset(obj),
-
 
Line 2741... Line 3178...
2741
		      x, y, fb->width, fb->height,
3178
		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
2742
		      fb->pitches[0]);
3179
		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
Line 2743... Line 3180...
2743
 
3180
		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
Line 2758... Line 3195...
2758
			   int x, int y, enum mode_set_atomic state)
3195
			   int x, int y, enum mode_set_atomic state)
2759
{
3196
{
2760
	struct drm_device *dev = crtc->dev;
3197
	struct drm_device *dev = crtc->dev;
2761
	struct drm_i915_private *dev_priv = dev->dev_private;
3198
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 2762... Line 3199...
2762
 
3199
 
2763
	if (dev_priv->display.disable_fbc)
3200
	if (dev_priv->fbc.disable_fbc)
Line 2764... Line 3201...
2764
		dev_priv->display.disable_fbc(dev);
3201
		dev_priv->fbc.disable_fbc(dev_priv);
Line 2765... Line 3202...
2765
 
3202
 
2766
	dev_priv->display.update_primary_plane(crtc, fb, x, y);
3203
	dev_priv->display.update_primary_plane(crtc, fb, x, y);
Line 2782... Line 3219...
2782
	}
3219
	}
2783
}
3220
}
Line 2784... Line 3221...
2784
 
3221
 
2785
static void intel_update_primary_planes(struct drm_device *dev)
3222
static void intel_update_primary_planes(struct drm_device *dev)
2786
{
-
 
2787
	struct drm_i915_private *dev_priv = dev->dev_private;
3223
{
Line 2788... Line 3224...
2788
	struct drm_crtc *crtc;
3224
	struct drm_crtc *crtc;
2789
 
3225
 
-
 
3226
	for_each_crtc(dev, crtc) {
Line 2790... Line 3227...
2790
	for_each_crtc(dev, crtc) {
3227
		struct intel_plane *plane = to_intel_plane(crtc->primary);
2791
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228
		struct intel_plane_state *plane_state;
2792
 
-
 
2793
		drm_modeset_lock(&crtc->mutex, NULL);
3229
 
2794
		/*
-
 
2795
		 * FIXME: Once we have proper support for primary planes (and
3230
		drm_modeset_lock_crtc(crtc, &plane->base);
2796
		 * disabling them without disabling the entire crtc) allow again
3231
 
2797
		 * a NULL crtc->primary->fb.
3232
		plane_state = to_intel_plane_state(plane->base.state);
2798
		 */
-
 
2799
		if (intel_crtc->active && crtc->primary->fb)
-
 
2800
			dev_priv->display.update_primary_plane(crtc,
-
 
-
 
3233
 
2801
							       crtc->primary->fb,
3234
		if (plane_state->base.fb)
2802
							       crtc->x,
3235
			plane->commit_plane(&plane->base, plane_state);
2803
							       crtc->y);
3236
 
Line 2804... Line 3237...
2804
		drm_modeset_unlock(&crtc->mutex);
3237
		drm_modeset_unlock_crtc(crtc);
2805
	}
3238
	}
2806
}
-
 
2807
 
-
 
2808
void intel_prepare_reset(struct drm_device *dev)
-
 
2809
{
3239
}
2810
	struct drm_i915_private *dev_priv = to_i915(dev);
3240
 
2811
	struct intel_crtc *crtc;
3241
void intel_prepare_reset(struct drm_device *dev)
Line 2812... Line 3242...
2812
 
3242
{
2813
	/* no reset support for gen2 */
3243
	/* no reset support for gen2 */
2814
	if (IS_GEN2(dev))
3244
	if (IS_GEN2(dev))
Line 2815... Line 3245...
2815
		return;
3245
		return;
2816
 
-
 
2817
	/* reset doesn't touch the display */
3246
 
2818
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3247
	/* reset doesn't touch the display */
2819
		return;
3248
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2820
 
3249
		return;
2821
	drm_modeset_lock_all(dev);
-
 
2822
 
-
 
2823
	/*
3250
 
2824
	 * Disabling the crtcs gracefully seems nicer. Also the
-
 
2825
	 * g33 docs say we should at least disable all the planes.
3251
	drm_modeset_lock_all(dev);
Line 2826... Line 3252...
2826
	 */
3252
	/*
2827
	for_each_intel_crtc(dev, crtc) {
3253
	 * Disabling the crtcs gracefully seems nicer. Also the
2828
		if (crtc->active)
3254
	 * g33 docs say we should at least disable all the planes.
Line 2850... Line 3276...
2850
		/*
3276
		/*
2851
		 * Flips in the rings have been nuked by the reset,
3277
		 * Flips in the rings have been nuked by the reset,
2852
		 * so update the base address of all primary
3278
		 * so update the base address of all primary
2853
		 * planes to the the last fb to make sure we're
3279
		 * planes to the the last fb to make sure we're
2854
		 * showing the correct fb after a reset.
3280
		 * showing the correct fb after a reset.
-
 
3281
		 *
-
 
3282
		 * FIXME: Atomic will make this obsolete since we won't schedule
-
 
3283
		 * CS-based flips (which might get lost in gpu resets) any more.
2855
		 */
3284
		 */
2856
		intel_update_primary_planes(dev);
3285
		intel_update_primary_planes(dev);
2857
		return;
3286
		return;
2858
	}
3287
	}
Line 2869... Line 3298...
2869
	spin_lock_irq(&dev_priv->irq_lock);
3298
	spin_lock_irq(&dev_priv->irq_lock);
2870
	if (dev_priv->display.hpd_irq_setup)
3299
	if (dev_priv->display.hpd_irq_setup)
2871
		dev_priv->display.hpd_irq_setup(dev);
3300
		dev_priv->display.hpd_irq_setup(dev);
2872
	spin_unlock_irq(&dev_priv->irq_lock);
3301
	spin_unlock_irq(&dev_priv->irq_lock);
Line 2873... Line 3302...
2873
 
3302
 
Line 2874... Line 3303...
2874
	intel_modeset_setup_hw_state(dev, true);
3303
	intel_display_resume(dev);
Line 2875... Line 3304...
2875
 
3304
 
2876
	intel_hpd_init(dev_priv);
3305
	intel_hpd_init(dev_priv);
Line 2877... Line 3306...
2877
 
3306
 
2878
	drm_modeset_unlock_all(dev);
3307
	drm_modeset_unlock_all(dev);
2879
}
3308
}
2880
 
3309
 
2881
static int
3310
static void
2882
intel_finish_fb(struct drm_framebuffer *old_fb)
3311
intel_finish_fb(struct drm_framebuffer *old_fb)
2883
{
3312
{
Line 2884... Line 3313...
2884
	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3313
	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2885
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3314
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2886
	bool was_interruptible = dev_priv->mm.interruptible;
3315
	bool was_interruptible = dev_priv->mm.interruptible;
-
 
3316
	int ret;
-
 
3317
 
-
 
3318
	/* Big Hammer, we also need to ensure that any pending
2887
	int ret;
3319
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2888
 
3320
	 * current scanout is retired before unpinning the old
2889
	/* Big Hammer, we also need to ensure that any pending
3321
	 * framebuffer. Note that we rely on userspace rendering
2890
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3322
	 * into the buffer attached to the pipe they are waiting
2891
	 * current scanout is retired before unpinning the old
3323
	 * on. If not, userspace generates a GPU hang with IPEHR
2892
	 * framebuffer.
3324
	 * point to the MI_WAIT_FOR_EVENT.
2893
	 *
3325
	 *
2894
	 * This should only fail upon a hung GPU, in which case we
3326
	 * This should only fail upon a hung GPU, in which case we
Line 2895... Line 3327...
2895
	 * can safely continue.
3327
	 * can safely continue.
2896
	 */
3328
	 */
Line 2897... Line 3329...
2897
	dev_priv->mm.interruptible = false;
3329
	dev_priv->mm.interruptible = false;
2898
	ret = i915_gem_object_finish_gpu(obj);
3330
	ret = i915_gem_object_wait_rendering(obj, true);
2899
	dev_priv->mm.interruptible = was_interruptible;
3331
	dev_priv->mm.interruptible = was_interruptible;
Line 2918... Line 3350...
2918
 
3350
 
2919
	return pending;
3351
	return pending;
2920
}
3352
}
Line 2921... Line 3353...
2921
#endif
3353
#endif
-
 
3354
 
2922
 
3355
static void intel_update_pipe_config(struct intel_crtc *crtc,
2923
static void intel_update_pipe_size(struct intel_crtc *crtc)
3356
				     struct intel_crtc_state *old_crtc_state)
2924
{
3357
{
2925
	struct drm_device *dev = crtc->base.dev;
3358
	struct drm_device *dev = crtc->base.dev;
-
 
3359
	struct drm_i915_private *dev_priv = dev->dev_private;
Line -... Line 3360...
-
 
3360
	struct intel_crtc_state *pipe_config =
-
 
3361
		to_intel_crtc_state(crtc->base.state);
-
 
3362
 
-
 
3363
	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
-
 
3364
	crtc->base.mode = crtc->base.state->mode;
-
 
3365
 
-
 
3366
	DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
2926
	struct drm_i915_private *dev_priv = dev->dev_private;
3367
		      old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
2927
	const struct drm_display_mode *adjusted_mode;
3368
		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Line 2928... Line 3369...
2928
 
3369
 
2929
	if (!i915.fastboot)
3370
	if (HAS_DDI(dev))
2930
		return;
3371
		intel_set_pipe_csc(&crtc->base);
2931
 
3372
 
2932
	/*
3373
	/*
2933
	 * Update pipe size and adjust fitter if needed: the reason for this is
3374
	 * Update pipe size and adjust fitter if needed: the reason for this is
2934
	 * that in compute_mode_changes we check the native mode (not the pfit
3375
	 * that in compute_mode_changes we check the native mode (not the pfit
2935
	 * mode) to see if we can flip rather than do a full mode set. In the
-
 
2936
	 * fastboot case, we'll flip, but if we don't update the pipesrc and
-
 
2937
	 * pfit state, we'll end up with a big fb scanned out into the wrong
-
 
2938
	 * sized surface.
-
 
2939
	 *
-
 
2940
	 * To fix this properly, we need to hoist the checks up into
3376
	 * mode) to see if we can flip rather than do a full mode set. In the
Line 2941... Line -...
2941
	 * compute_mode_changes (or above), check the actual pfit state and
-
 
2942
	 * whether the platform allows pfit disable with pipe active, and only
-
 
2943
	 * then update the pipesrc and pfit state, even on the flip path.
3377
	 * fastboot case, we'll flip, but if we don't update the pipesrc and
2944
	 */
3378
	 * pfit state, we'll end up with a big fb scanned out into the wrong
2945
 
3379
	 * sized surface.
2946
	adjusted_mode = &crtc->config.adjusted_mode;
-
 
2947
 
-
 
2948
	I915_WRITE(PIPESRC(crtc->pipe),
-
 
2949
		   ((adjusted_mode->crtc_hdisplay - 1) << 16) |
-
 
2950
		   (adjusted_mode->crtc_vdisplay - 1));
-
 
2951
	if (!crtc->config.pch_pfit.enabled &&
-
 
2952
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
-
 
2953
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
-
 
2954
		I915_WRITE(PF_CTL(crtc->pipe), 0);
-
 
2955
		I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
-
 
2956
		I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
-
 
2957
	}
-
 
2958
	crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
-
 
2959
	crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
-
 
2960
}
-
 
2961
 
-
 
2962
static int
-
 
2963
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
-
 
2964
		    struct drm_framebuffer *fb)
-
 
2965
{
-
 
2966
	struct drm_device *dev = crtc->dev;
-
 
2967
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
2968
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
Line 2969... Line -...
2969
	enum pipe pipe = intel_crtc->pipe;
-
 
2970
	struct drm_framebuffer *old_fb = crtc->primary->fb;
-
 
2971
	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
-
 
2972
	int ret;
-
 
2973
 
-
 
2974
 
-
 
2975
	/* no fb bound */
3380
	 */
2976
	if (!fb) {
-
 
2977
		DRM_ERROR("No FB bound\n");
-
 
2978
		return 0;
3381
 
2979
	}
-
 
2980
 
-
 
2981
	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
-
 
2982
		DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
-
 
2983
			  plane_name(intel_crtc->plane),
-
 
2984
				INTEL_INFO(dev)->num_pipes);
-
 
2985
		return -EINVAL;
-
 
2986
	}
-
 
2987
 
-
 
2988
	mutex_lock(&dev->struct_mutex);
-
 
2989
	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
-
 
2990
	if (ret == 0)
-
 
2991
		i915_gem_track_fb(old_obj, intel_fb_obj(fb),
-
 
2992
				  INTEL_FRONTBUFFER_PRIMARY(pipe));
-
 
2993
	mutex_unlock(&dev->struct_mutex);
-
 
2994
    if (ret != 0) {
-
 
2995
       DRM_ERROR("pin & fence failed\n");
3382
	I915_WRITE(PIPESRC(crtc->pipe),
2996
       return ret;
-
 
2997
    }
-
 
2998
 
-
 
2999
	dev_priv->display.update_primary_plane(crtc, fb, x, y);
-
 
3000
 
-
 
Line 3001... Line 3383...
3001
	if (intel_crtc->active)
3383
		   ((pipe_config->pipe_src_w - 1) << 16) |
3002
		intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
3384
		   (pipe_config->pipe_src_h - 1));
3003
 
3385
 
3004
	crtc->primary->fb = fb;
3386
	/* on skylake this is done by detaching scalers */
3005
	crtc->x = x;
3387
	if (INTEL_INFO(dev)->gen >= 9) {
-
 
3388
		skl_detach_scalers(crtc);
3006
	crtc->y = y;
3389
 
3007
 
3390
		if (pipe_config->pch_pfit.enabled)
3008
	if (old_fb) {
-
 
3009
		if (intel_crtc->active && old_fb != fb)
-
 
3010
		intel_wait_for_vblank(dev, intel_crtc->pipe);
-
 
3011
		mutex_lock(&dev->struct_mutex);
-
 
3012
		intel_unpin_fb_obj(old_obj);
-
 
3013
		mutex_unlock(&dev->struct_mutex);
-
 
3014
	}
3391
			skylake_pfit_enable(crtc);
Line 3015... Line 3392...
3015
 
3392
	} else if (HAS_PCH_SPLIT(dev)) {
3016
	mutex_lock(&dev->struct_mutex);
3393
		if (pipe_config->pch_pfit.enabled)
3017
	intel_update_fbc(dev);
3394
			ironlake_pfit_enable(crtc);
Line 3059... Line 3436...
3059
	if (IS_IVYBRIDGE(dev))
3436
	if (IS_IVYBRIDGE(dev))
3060
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3061
			   FDI_FE_ERRC_ENABLE);
3438
			   FDI_FE_ERRC_ENABLE);
3062
}
3439
}
Line 3063... Line -...
3063
 
-
 
3064
static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
-
 
3065
{
-
 
3066
	return crtc->base.enabled && crtc->active &&
-
 
3067
		crtc->config.has_pch_encoder;
-
 
3068
}
-
 
3069
 
-
 
3070
static void ivb_modeset_global_resources(struct drm_device *dev)
-
 
3071
{
-
 
3072
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
3073
	struct intel_crtc *pipe_B_crtc =
-
 
3074
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
-
 
3075
	struct intel_crtc *pipe_C_crtc =
-
 
3076
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
-
 
3077
	uint32_t temp;
-
 
3078
 
-
 
3079
	/*
-
 
3080
	 * When everything is off disable fdi C so that we could enable fdi B
-
 
3081
	 * with all lanes. Note that we don't care about enabled pipes without
-
 
3082
	 * an enabled pch encoder.
-
 
3083
	 */
-
 
3084
	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
-
 
3085
	    !pipe_has_enabled_pch(pipe_C_crtc)) {
-
 
3086
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
-
 
3087
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
-
 
3088
 
-
 
3089
		temp = I915_READ(SOUTH_CHICKEN1);
-
 
3090
		temp &= ~FDI_BC_BIFURCATION_SELECT;
-
 
3091
		DRM_DEBUG_KMS("disabling fdi C rx\n");
-
 
3092
		I915_WRITE(SOUTH_CHICKEN1, temp);
-
 
3093
	}
-
 
3094
}
-
 
3095
 
3440
 
3096
/* The FDI link training functions for ILK/Ibexpeak. */
3441
/* The FDI link training functions for ILK/Ibexpeak. */
3097
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3442
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3098
{
3443
{
3099
    struct drm_device *dev = crtc->dev;
3444
	struct drm_device *dev = crtc->dev;
Line 3117... Line 3462...
3117
 
3462
 
3118
    /* enable CPU FDI TX and PCH FDI RX */
3463
	/* enable CPU FDI TX and PCH FDI RX */
3119
    reg = FDI_TX_CTL(pipe);
3464
	reg = FDI_TX_CTL(pipe);
3120
    temp = I915_READ(reg);
3465
	temp = I915_READ(reg);
3121
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
3122
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3467
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3123
    temp &= ~FDI_LINK_TRAIN_NONE;
3468
	temp &= ~FDI_LINK_TRAIN_NONE;
3124
    temp |= FDI_LINK_TRAIN_PATTERN_1;
3469
	temp |= FDI_LINK_TRAIN_PATTERN_1;
Line 3125... Line 3470...
3125
    I915_WRITE(reg, temp | FDI_TX_ENABLE);
3470
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
Line 3215... Line 3560...
3215
 
3560
 
3216
    /* enable CPU FDI TX and PCH FDI RX */
3561
	/* enable CPU FDI TX and PCH FDI RX */
3217
    reg = FDI_TX_CTL(pipe);
3562
	reg = FDI_TX_CTL(pipe);
3218
    temp = I915_READ(reg);
3563
	temp = I915_READ(reg);
3219
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
3564
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
3220
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3565
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3221
    temp &= ~FDI_LINK_TRAIN_NONE;
3566
	temp &= ~FDI_LINK_TRAIN_NONE;
3222
    temp |= FDI_LINK_TRAIN_PATTERN_1;
3567
	temp |= FDI_LINK_TRAIN_PATTERN_1;
3223
    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3224
    /* SNB-B */
3569
	/* SNB-B */
Line 3366... Line 3711...
3366
 
3711
 
3367
    /* enable CPU FDI TX and PCH FDI RX */
3712
		/* enable CPU FDI TX and PCH FDI RX */
3368
    reg = FDI_TX_CTL(pipe);
3713
		reg = FDI_TX_CTL(pipe);
3369
    temp = I915_READ(reg);
3714
		temp = I915_READ(reg);
3370
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
3715
		temp &= ~FDI_DP_PORT_WIDTH_MASK;
3371
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3716
		temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3372
    temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3717
		temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3373
    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3718
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3374
		temp |= snb_b_fdi_train_param[j/2];
3719
		temp |= snb_b_fdi_train_param[j/2];
3375
	temp |= FDI_COMPOSITE_SYNC;
3720
		temp |= FDI_COMPOSITE_SYNC;
Line 3454... Line 3799...
3454
 
3799
 
3455
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3800
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3456
	reg = FDI_RX_CTL(pipe);
3801
	reg = FDI_RX_CTL(pipe);
3457
	temp = I915_READ(reg);
3802
	temp = I915_READ(reg);
3458
	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3803
	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3459
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3804
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3460
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3805
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Line 3461... Line 3806...
3461
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3806
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3462
 
3807
 
Line 3617... Line 3962...
3617
/* Program iCLKIP clock to the desired frequency */
3962
/* Program iCLKIP clock to the desired frequency */
3618
static void lpt_program_iclkip(struct drm_crtc *crtc)
3963
static void lpt_program_iclkip(struct drm_crtc *crtc)
3619
{
3964
{
3620
	struct drm_device *dev = crtc->dev;
3965
	struct drm_device *dev = crtc->dev;
3621
	struct drm_i915_private *dev_priv = dev->dev_private;
3966
	struct drm_i915_private *dev_priv = dev->dev_private;
3622
	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3967
	int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3623
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
3968
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
3624
	u32 temp;
3969
	u32 temp;
Line 3625... Line 3970...
3625
 
3970
 
Line 3626... Line 3971...
3626
	mutex_lock(&dev_priv->dpio_lock);
3971
	mutex_lock(&dev_priv->sb_lock);
3627
 
3972
 
3628
	/* It is necessary to ungate the pixclk gate prior to programming
3973
	/* It is necessary to ungate the pixclk gate prior to programming
3629
	 * the divisors, and gate it back when it is done.
3974
	 * the divisors, and gate it back when it is done.
Line 3698... Line 4043...
3698
	/* Wait for initialization time */
4043
	/* Wait for initialization time */
3699
	udelay(24);
4044
	udelay(24);
Line 3700... Line 4045...
3700
 
4045
 
Line 3701... Line 4046...
3701
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4046
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3702
 
4047
 
Line 3703... Line 4048...
3703
	mutex_unlock(&dev_priv->dpio_lock);
4048
	mutex_unlock(&dev_priv->sb_lock);
3704
}
4049
}
3705
 
4050
 
3706
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4051
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3707
						enum pipe pch_transcoder)
4052
						enum pipe pch_transcoder)
3708
{
4053
{
Line 3709... Line 4054...
3709
	struct drm_device *dev = crtc->base.dev;
4054
	struct drm_device *dev = crtc->base.dev;
3710
	struct drm_i915_private *dev_priv = dev->dev_private;
4055
	struct drm_i915_private *dev_priv = dev->dev_private;
3711
	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
4056
	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3712
 
4057
 
Line 3725... Line 4070...
3725
		   I915_READ(VSYNC(cpu_transcoder)));
4070
		   I915_READ(VSYNC(cpu_transcoder)));
3726
	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4071
	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3727
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
4072
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
3728
}
4073
}
Line 3729... Line 4074...
3729
 
4074
 
3730
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
4075
static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3731
{
4076
{
3732
	struct drm_i915_private *dev_priv = dev->dev_private;
4077
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 3733... Line 4078...
3733
	uint32_t temp;
4078
	uint32_t temp;
3734
 
4079
 
3735
	temp = I915_READ(SOUTH_CHICKEN1);
4080
	temp = I915_READ(SOUTH_CHICKEN1);
Line 3736... Line 4081...
3736
	if (temp & FDI_BC_BIFURCATION_SELECT)
4081
	if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3737
		return;
4082
		return;
Line -... Line 4083...
-
 
4083
 
-
 
4084
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3738
 
4085
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
-
 
4086
 
3739
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4087
	temp &= ~FDI_BC_BIFURCATION_SELECT;
3740
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4088
	if (enable)
3741
 
4089
		temp |= FDI_BC_BIFURCATION_SELECT;
3742
	temp |= FDI_BC_BIFURCATION_SELECT;
4090
 
Line 3743... Line 4091...
3743
	DRM_DEBUG_KMS("enabling fdi C rx\n");
4091
	DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3744
	I915_WRITE(SOUTH_CHICKEN1, temp);
4092
	I915_WRITE(SOUTH_CHICKEN1, temp);
3745
	POSTING_READ(SOUTH_CHICKEN1);
4093
	POSTING_READ(SOUTH_CHICKEN1);
3746
}
-
 
Line 3747... Line 4094...
3747
 
4094
}
3748
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095
 
3749
{
4096
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3750
	struct drm_device *dev = intel_crtc->base.dev;
4097
{
3751
	struct drm_i915_private *dev_priv = dev->dev_private;
4098
	struct drm_device *dev = intel_crtc->base.dev;
3752
 
4099
 
3753
	switch (intel_crtc->pipe) {
4100
	switch (intel_crtc->pipe) {
3754
	case PIPE_A:
4101
	case PIPE_A:
Line 3755... Line 4102...
3755
		break;
4102
		break;
3756
	case PIPE_B:
4103
	case PIPE_B:
3757
		if (intel_crtc->config.fdi_lanes > 2)
4104
		if (intel_crtc->config->fdi_lanes > 2)
Line 3758... Line 4105...
3758
			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
4105
			cpt_set_fdi_bc_bifurcation(dev, false);
3759
		else
4106
		else
3760
			cpt_enable_fdi_bc_bifurcation(dev);
4107
			cpt_set_fdi_bc_bifurcation(dev, true);
3761
 
4108
 
Line 3804... Line 4151...
3804
		u32 sel;
4151
		u32 sel;
Line 3805... Line 4152...
3805
 
4152
 
3806
		temp = I915_READ(PCH_DPLL_SEL);
4153
		temp = I915_READ(PCH_DPLL_SEL);
3807
		temp |= TRANS_DPLL_ENABLE(pipe);
4154
		temp |= TRANS_DPLL_ENABLE(pipe);
3808
		sel = TRANS_DPLLB_SEL(pipe);
4155
		sel = TRANS_DPLLB_SEL(pipe);
3809
		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
4156
		if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3810
			temp |= sel;
4157
			temp |= sel;
3811
		else
4158
		else
3812
			temp &= ~sel;
4159
			temp &= ~sel;
3813
		I915_WRITE(PCH_DPLL_SEL, temp);
4160
		I915_WRITE(PCH_DPLL_SEL, temp);
Line 3827... Line 4174...
3827
	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4174
	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Line 3828... Line 4175...
3828
 
4175
 
Line 3829... Line 4176...
3829
	intel_fdi_normal_train(crtc);
4176
	intel_fdi_normal_train(crtc);
3830
 
4177
 
3831
	/* For PCH DP, enable TRANS_DP_CTL */
4178
	/* For PCH DP, enable TRANS_DP_CTL */
3832
	if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
4179
	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3833
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4180
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3834
		reg = TRANS_DP_CTL(pipe);
4181
		reg = TRANS_DP_CTL(pipe);
3835
		temp = I915_READ(reg);
4182
		temp = I915_READ(reg);
3836
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
4183
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
3837
			  TRANS_DP_SYNC_MASK |
4184
			  TRANS_DP_SYNC_MASK |
3838
			  TRANS_DP_BPC_MASK);
-
 
3839
		temp |= (TRANS_DP_OUTPUT_ENABLE |
4185
			  TRANS_DP_BPC_MASK);
Line 3840... Line 4186...
3840
			 TRANS_DP_ENH_FRAMING);
4186
		temp |= TRANS_DP_OUTPUT_ENABLE;
3841
		temp |= bpc << 9; /* same format but at 11:9 */
4187
		temp |= bpc << 9; /* same format but at 11:9 */
3842
 
4188
 
Line 3868... Line 4214...
3868
static void lpt_pch_enable(struct drm_crtc *crtc)
4214
static void lpt_pch_enable(struct drm_crtc *crtc)
3869
{
4215
{
3870
	struct drm_device *dev = crtc->dev;
4216
	struct drm_device *dev = crtc->dev;
3871
	struct drm_i915_private *dev_priv = dev->dev_private;
4217
	struct drm_i915_private *dev_priv = dev->dev_private;
3872
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4218
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3873
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4219
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Line 3874... Line 4220...
3874
 
4220
 
Line 3875... Line 4221...
3875
	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4221
	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Line 3880... Line 4226...
3880
	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4226
	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Line 3881... Line 4227...
3881
 
4227
 
3882
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4228
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Line 3883... Line 4229...
3883
}
4229
}
3884
 
-
 
3885
void intel_put_shared_dpll(struct intel_crtc *crtc)
-
 
3886
{
-
 
3887
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-
 
3888
 
-
 
3889
	if (pll == NULL)
-
 
3890
		return;
4230
 
3891
 
-
 
3892
	if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
-
 
3893
		WARN(1, "bad %s crtc mask\n", pll->name);
-
 
3894
		return;
-
 
3895
	}
-
 
3896
 
-
 
3897
	pll->config.crtc_mask &= ~(1 << crtc->pipe);
-
 
3898
	if (pll->config.crtc_mask == 0) {
-
 
3899
		WARN_ON(pll->on);
-
 
3900
		WARN_ON(pll->active);
-
 
3901
	}
-
 
3902
 
-
 
3903
	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
-
 
3904
}
-
 
3905
 
4231
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3906
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
4232
						struct intel_crtc_state *crtc_state)
3907
{
4233
{
-
 
4234
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3908
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4235
	struct intel_shared_dpll *pll;
-
 
4236
	struct intel_shared_dpll_config *shared_dpll;
-
 
4237
	enum intel_dpll_id i;
-
 
4238
	int max = dev_priv->num_shared_dpll;
Line 3909... Line 4239...
3909
	struct intel_shared_dpll *pll;
4239
 
3910
	enum intel_dpll_id i;
4240
	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
3911
 
4241
 
3912
	if (HAS_PCH_IBX(dev_priv->dev)) {
4242
	if (HAS_PCH_IBX(dev_priv->dev)) {
Line 3913... Line 4243...
3913
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4243
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3914
		i = (enum intel_dpll_id) crtc->pipe;
4244
		i = (enum intel_dpll_id) crtc->pipe;
Line 3915... Line 4245...
3915
		pll = &dev_priv->shared_dplls[i];
4245
		pll = &dev_priv->shared_dplls[i];
Line 3916... Line 4246...
3916
 
4246
 
3917
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4247
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
Line -... Line 4248...
-
 
4248
			      crtc->base.base.id, pll->name);
-
 
4249
 
-
 
4250
		WARN_ON(shared_dpll[i].crtc_mask);
-
 
4251
 
-
 
4252
		goto found;
-
 
4253
	}
-
 
4254
 
-
 
4255
	if (IS_BROXTON(dev_priv->dev)) {
-
 
4256
		/* PLL is attached to port in bxt */
-
 
4257
		struct intel_encoder *encoder;
-
 
4258
		struct intel_digital_port *intel_dig_port;
-
 
4259
 
3918
			      crtc->base.base.id, pll->name);
4260
		encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
-
 
4261
		if (WARN_ON(!encoder))
-
 
4262
			return NULL;
-
 
4263
 
-
 
4264
		intel_dig_port = enc_to_dig_port(&encoder->base);
-
 
4265
		/* 1:1 mapping between ports and PLLs */
-
 
4266
		i = (enum intel_dpll_id)intel_dig_port->port;
-
 
4267
		pll = &dev_priv->shared_dplls[i];
-
 
4268
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
-
 
4269
			crtc->base.base.id, pll->name);
-
 
4270
		WARN_ON(shared_dpll[i].crtc_mask);
3919
 
4271
 
Line 3920... Line 4272...
3920
		WARN_ON(pll->new_config->crtc_mask);
4272
		goto found;
3921
 
4273
	} else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
3922
		goto found;
4274
		/* Do not consider SPLL */
Line 3923... Line 4275...
3923
	}
4275
		max = 2;
3924
 
4276
 
3925
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4277
	for (i = 0; i < max; i++) {
3926
		pll = &dev_priv->shared_dplls[i];
4278
		pll = &dev_priv->shared_dplls[i];
3927
 
4279
 
3928
		/* Only want to check enabled timings first */
4280
		/* Only want to check enabled timings first */
3929
		if (pll->new_config->crtc_mask == 0)
4281
		if (shared_dpll[i].crtc_mask == 0)
3930
			continue;
4282
			continue;
3931
 
4283
 
3932
		if (memcmp(&crtc->new_config->dpll_hw_state,
4284
		if (memcmp(&crtc_state->dpll_hw_state,
Line 3933... Line 4285...
3933
			   &pll->new_config->hw_state,
4285
			   &shared_dpll[i].hw_state,
3934
			   sizeof(pll->new_config->hw_state)) == 0) {
4286
			   sizeof(crtc_state->dpll_hw_state)) == 0) {
3935
			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4287
			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3936
				      crtc->base.base.id, pll->name,
4288
				      crtc->base.base.id, pll->name,
3937
				      pll->new_config->crtc_mask,
4289
				      shared_dpll[i].crtc_mask,
3938
				      pll->active);
4290
				      pll->active);
3939
			goto found;
4291
			goto found;
3940
		}
4292
		}
3941
	}
4293
	}
Line 3942... Line 4294...
3942
 
4294
 
Line 3943... Line 4295...
3943
	/* Ok no matching timings, maybe there's a free one? */
4295
	/* Ok no matching timings, maybe there's a free one? */
3944
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-
 
4297
		pll = &dev_priv->shared_dplls[i];
3945
		pll = &dev_priv->shared_dplls[i];
4298
		if (shared_dpll[i].crtc_mask == 0) {
Line 3946... Line 4299...
3946
		if (pll->new_config->crtc_mask == 0) {
4299
			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3947
			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4300
				      crtc->base.base.id, pll->name);
3948
				      crtc->base.base.id, pll->name);
4301
			goto found;
Line 3949... Line 4302...
3949
			goto found;
4302
		}
Line 3950... Line 4303...
3950
		}
4303
	}
3951
	}
4304
 
Line 3952... Line -...
3952
 
-
 
3953
	return NULL;
-
 
3954
 
-
 
3955
found:
-
 
3956
	if (pll->new_config->crtc_mask == 0)
-
 
3957
		pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
-
 
3958
 
-
 
3959
	crtc->new_config->shared_dpll = i;
-
 
3960
	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4305
	return NULL;
3961
			 pipe_name(crtc->pipe));
-
 
3962
 
4306
 
-
 
4307
found:
-
 
4308
	if (shared_dpll[i].crtc_mask == 0)
3963
	pll->new_config->crtc_mask |= 1 << crtc->pipe;
4309
		shared_dpll[i].hw_state =
3964
 
4310
			crtc_state->dpll_hw_state;
Line -... Line 4311...
-
 
4311
 
-
 
4312
	crtc_state->shared_dpll = i;
-
 
4313
	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
-
 
4314
			 pipe_name(crtc->pipe));
3965
	return pll;
4315
 
3966
}
4316
	shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
-
 
4317
 
-
 
4318
	return pll;
-
 
4319
}
Line 3967... Line 4320...
3967
 
4320
 
-
 
4321
static void intel_shared_dpll_commit(struct drm_atomic_state *state)
3968
/**
4322
{
3969
 * intel_shared_dpll_start_config - start a new PLL staged config
4323
	struct drm_i915_private *dev_priv = to_i915(state->dev);
3970
 * @dev_priv: DRM device
4324
	struct intel_shared_dpll_config *shared_dpll;
Line -... Line 4325...
-
 
4325
	struct intel_shared_dpll *pll;
-
 
4326
	enum intel_dpll_id i;
-
 
4327
 
3971
 * @clear_pipes: mask of pipes that will have their PLLs freed
4328
	if (!to_intel_atomic_state(state)->dpll_set)
-
 
4329
		return;
3972
 *
4330
 
-
 
4331
	shared_dpll = to_intel_atomic_state(state)->shared_dpll;
-
 
4332
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-
 
4333
		pll = &dev_priv->shared_dplls[i];
-
 
4334
		pll->config = shared_dpll[i];
-
 
4335
	}
-
 
4336
}
-
 
4337
 
-
 
4338
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
-
 
4339
{
-
 
4340
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4341
	int dslreg = PIPEDSL(pipe);
-
 
4342
	u32 temp;
Line -... Line 4343...
-
 
4343
 
-
 
4344
	temp = I915_READ(dslreg);
-
 
4345
	udelay(500);
-
 
4346
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
-
 
4347
		if (wait_for(I915_READ(dslreg) != temp, 5))
-
 
4348
			DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
-
 
4349
	}
-
 
4350
}
-
 
4351
 
-
 
4352
static int
-
 
4353
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
-
 
4354
		  unsigned scaler_user, int *scaler_id, unsigned int rotation,
-
 
4355
		  int src_w, int src_h, int dst_w, int dst_h)
-
 
4356
{
-
 
4357
	struct intel_crtc_scaler_state *scaler_state =
-
 
4358
		&crtc_state->scaler_state;
-
 
4359
	struct intel_crtc *intel_crtc =
-
 
4360
		to_intel_crtc(crtc_state->base.crtc);
-
 
4361
	int need_scaling;
-
 
4362
 
-
 
4363
	need_scaling = intel_rotation_90_or_270(rotation) ?
-
 
4364
		(src_h != dst_w || src_w != dst_h):
-
 
4365
		(src_w != dst_w || src_h != dst_h);
-
 
4366
 
-
 
4367
	/*
3973
 * Starts a new PLL staged config, copying the current config but
4368
	 * if plane is being disabled or scaler is no more required or force detach
-
 
4369
	 *  - free scaler binded to this plane/crtc
Line 3974... Line 4370...
3974
 * releasing the references of pipes specified in clear_pipes.
4370
	 *  - in order to do this, update crtc->scaler_usage
-
 
4371
	 *
-
 
4372
	 * Here scaler state in crtc_state is set free so that
-
 
4373
	 * scaler can be assigned to other user. Actual register
3975
 */
4374
	 * update to free the scaler is done in plane/panel-fit programming.
3976
static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4375
	 * For this purpose crtc/plane_state->scaler_id isn't reset here.
-
 
4376
	 */
3977
					  unsigned clear_pipes)
4377
	if (force_detach || !need_scaling) {
-
 
4378
		if (*scaler_id >= 0) {
3978
{
4379
			scaler_state->scaler_users &= ~(1 << scaler_user);
3979
	struct intel_shared_dpll *pll;
4380
			scaler_state->scalers[*scaler_id].in_use = 0;
Line -... Line 4381...
-
 
4381
 
-
 
4382
			DRM_DEBUG_KMS("scaler_user index %u.%u: "
-
 
4383
				"Staged freeing scaler id %d scaler_users = 0x%x\n",
-
 
4384
				intel_crtc->pipe, scaler_user, *scaler_id,
-
 
4385
				scaler_state->scaler_users);
-
 
4386
			*scaler_id = -1;
-
 
4387
		}
3980
	enum intel_dpll_id i;
4388
		return 0;
3981
 
4389
	}
Line -... Line 4390...
-
 
4390
 
-
 
4391
	/* range checks */
-
 
4392
	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
-
 
4393
		dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-
 
4394
 
-
 
4395
		src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
-
 
4396
		dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
-
 
4397
		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
-
 
4398
			"size is out of scaler range\n",
3982
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4399
			intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
3983
		pll = &dev_priv->shared_dplls[i];
4400
		return -EINVAL;
3984
 
4401
	}
3985
		pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4402
 
Line 3986... Line 4403...
3986
					  GFP_KERNEL);
4403
	/* mark this plane as a scaler user in crtc_state */
3987
		if (!pll->new_config)
4404
	scaler_state->scaler_users |= (1 << scaler_user);
Line 3988... Line 4405...
3988
			goto cleanup;
4405
	DRM_DEBUG_KMS("scaler_user index %u.%u: "
3989
 
-
 
3990
		pll->new_config->crtc_mask &= ~clear_pipes;
4406
		"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
3991
	}
4407
		intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
3992
 
4408
		scaler_state->scaler_users);
3993
	return 0;
-
 
3994
 
4409
 
Line -... Line 4410...
-
 
4410
	return 0;
-
 
4411
}
-
 
4412
 
-
 
4413
/**
-
 
4414
 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
-
 
4415
 *
-
 
4416
 * @state: crtc's scaler state
-
 
4417
 *
-
 
4418
 * Return
-
 
4419
 *     0 - scaler_usage updated successfully
3995
cleanup:
4420
 *    error - requested scaling cannot be supported or other error condition
-
 
4421
 */
3996
	while (--i >= 0) {
4422
int skl_update_scaler_crtc(struct intel_crtc_state *state)
3997
		pll = &dev_priv->shared_dplls[i];
-
 
3998
		kfree(pll->new_config);
-
 
Line 3999... Line 4423...
3999
		pll->new_config = NULL;
4423
{
4000
	}
4424
	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
-
 
4425
	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
-
 
4426
 
-
 
4427
	DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
Line 4001... Line 4428...
4001
 
4428
		      intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
Line -... Line 4429...
-
 
4429
 
-
 
4430
	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-
 
4431
		&state->scaler_state.scaler_id, DRM_ROTATE_0,
-
 
4432
		state->pipe_src_w, state->pipe_src_h,
-
 
4433
		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
-
 
4434
}
-
 
4435
 
-
 
4436
/**
-
 
4437
 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
-
 
4438
 *
-
 
4439
 * @state: crtc's scaler state
-
 
4440
 * @plane_state: atomic plane state to update
-
 
4441
 *
-
 
4442
 * Return
-
 
4443
 *     0 - scaler_usage updated successfully
-
 
4444
 *    error - requested scaling cannot be supported or other error condition
-
 
4445
 */
-
 
4446
static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
-
 
4447
				   struct intel_plane_state *plane_state)
4002
	return -ENOMEM;
4448
{
4003
}
4449
 
4004
 
4450
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-
 
4451
	struct intel_plane *intel_plane =
-
 
4452
		to_intel_plane(plane_state->base.plane);
-
 
4453
	struct drm_framebuffer *fb = plane_state->base.fb;
-
 
4454
	int ret;
-
 
4455
 
-
 
4456
	bool force_detach = !fb || !plane_state->visible;
-
 
4457
 
-
 
4458
	DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
-
 
4459
		      intel_plane->base.base.id, intel_crtc->pipe,
-
 
4460
		      drm_plane_index(&intel_plane->base));
-
 
4461
 
-
 
4462
	ret = skl_update_scaler(crtc_state, force_detach,
-
 
4463
				drm_plane_index(&intel_plane->base),
-
 
4464
				&plane_state->scaler_id,
-
 
4465
				plane_state->base.rotation,
-
 
4466
				drm_rect_width(&plane_state->src) >> 16,
-
 
4467
				drm_rect_height(&plane_state->src) >> 16,
-
 
4468
				drm_rect_width(&plane_state->dst),
-
 
4469
				drm_rect_height(&plane_state->dst));
4005
static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4470
 
Line -... Line 4471...
-
 
4471
	if (ret || plane_state->scaler_id < 0)
-
 
4472
		return ret;
-
 
4473
 
4006
{
4474
	/* check colorkey */
4007
	struct intel_shared_dpll *pll;
4475
	if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4008
	enum intel_dpll_id i;
-
 
4009
 
-
 
4010
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4476
		DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
Line 4011... Line -...
4011
		pll = &dev_priv->shared_dplls[i];
-
 
4012
 
-
 
4013
		WARN_ON(pll->new_config == &pll->config);
4477
			      intel_plane->base.base.id);
4014
 
4478
		return -EINVAL;
4015
		pll->config = *pll->new_config;
-
 
4016
		kfree(pll->new_config);
-
 
4017
		pll->new_config = NULL;
4479
	}
Line 4018... Line 4480...
4018
	}
4480
 
4019
}
4481
	/* Check src format */
4020
 
4482
	switch (fb->pixel_format) {
4021
static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4483
	case DRM_FORMAT_RGB565:
4022
{
4484
	case DRM_FORMAT_XBGR8888:
-
 
4485
	case DRM_FORMAT_XRGB8888:
-
 
4486
	case DRM_FORMAT_ABGR8888:
-
 
4487
	case DRM_FORMAT_ARGB8888:
-
 
4488
	case DRM_FORMAT_XRGB2101010:
-
 
4489
	case DRM_FORMAT_XBGR2101010:
-
 
4490
	case DRM_FORMAT_YUYV:
-
 
4491
	case DRM_FORMAT_YVYU:
-
 
4492
	case DRM_FORMAT_UYVY:
-
 
4493
	case DRM_FORMAT_VYUY:
-
 
4494
		break;
-
 
4495
	default:
-
 
4496
		DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
-
 
4497
			intel_plane->base.base.id, fb->base.id, fb->pixel_format);
-
 
4498
		return -EINVAL;
-
 
4499
	}
-
 
4500
 
-
 
4501
	return 0;
-
 
4502
}
Line 4023... Line -...
4023
	struct intel_shared_dpll *pll;
-
 
4024
	enum intel_dpll_id i;
-
 
4025
 
4503
 
4026
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-
 
4027
		pll = &dev_priv->shared_dplls[i];
4504
static void skylake_scaler_disable(struct intel_crtc *crtc)
4028
 
4505
{
Line 4029... Line 4506...
4029
		WARN_ON(pll->new_config == &pll->config);
4506
	int i;
4030
 
4507
 
4031
		kfree(pll->new_config);
4508
	for (i = 0; i < crtc->num_scalers; i++)
4032
		pll->new_config = NULL;
4509
		skl_detach_scaler(crtc, i);
4033
	}
4510
}
Line 4034... Line 4511...
4034
}
4511
 
4035
 
4512
static void skylake_pfit_enable(struct intel_crtc *crtc)
4036
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4513
{
4037
{
4514
	struct drm_device *dev = crtc->base.dev;
4038
	struct drm_i915_private *dev_priv = dev->dev_private;
4515
	struct drm_i915_private *dev_priv = dev->dev_private;
4039
	int dslreg = PIPEDSL(pipe);
4516
	int pipe = crtc->pipe;
4040
	u32 temp;
4517
	struct intel_crtc_scaler_state *scaler_state =
4041
 
4518
		&crtc->config->scaler_state;
4042
	temp = I915_READ(dslreg);
4519
 
4043
	udelay(500);
4520
	DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4044
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
4521
 
4045
		if (wait_for(I915_READ(dslreg) != temp, 5))
4522
	if (crtc->config->pch_pfit.enabled) {
4046
			DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
-
 
4047
	}
-
 
4048
}
-
 
4049
 
-
 
4050
static void skylake_pfit_enable(struct intel_crtc *crtc)
-
 
4051
{
-
 
4052
	struct drm_device *dev = crtc->base.dev;
-
 
4053
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4054
	int pipe = crtc->pipe;
-
 
4055
 
-
 
4056
	if (crtc->config.pch_pfit.enabled) {
-
 
4057
		I915_WRITE(PS_CTL(pipe), PS_ENABLE);
-
 
4058
		I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
-
 
4059
		I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
-
 
4060
	}
-
 
4061
}
-
 
4062
 
-
 
4063
static void ironlake_pfit_enable(struct intel_crtc *crtc)
-
 
4064
{
-
 
4065
	struct drm_device *dev = crtc->base.dev;
-
 
4066
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4067
	int pipe = crtc->pipe;
-
 
4068
 
-
 
4069
	if (crtc->config.pch_pfit.enabled) {
-
 
4070
		/* Force use of hard-coded filter coefficients
-
 
4071
		 * as some pre-programmed values are broken,
-
 
4072
		 * e.g. x201.
-
 
4073
		 */
-
 
4074
		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4523
		int id;
4075
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4524
 
Line 4076... Line 4525...
4076
						 PF_PIPE_SEL_IVB(pipe));
4525
		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4077
		else
4526
			DRM_ERROR("Requesting pfit without getting a scaler first\n");
4078
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4527
			return;
4079
		I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4528
		}
Line 4080... Line 4529...
4080
		I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4529
 
4081
	}
4530
		id = scaler_state->scaler_id;
Line 4082... Line 4531...
4082
}
4531
		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4083
 
4532
			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
Line 4145... Line 4594...
4145
void hsw_disable_ips(struct intel_crtc *crtc)
4594
void hsw_disable_ips(struct intel_crtc *crtc)
4146
{
4595
{
4147
	struct drm_device *dev = crtc->base.dev;
4596
	struct drm_device *dev = crtc->base.dev;
4148
	struct drm_i915_private *dev_priv = dev->dev_private;
4597
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 4149... Line 4598...
4149
 
4598
 
4150
	if (!crtc->config.ips_enabled)
4599
	if (!crtc->config->ips_enabled)
Line 4151... Line 4600...
4151
		return;
4600
		return;
4152
 
4601
 
4153
	assert_plane_enabled(dev_priv, crtc->plane);
4602
	assert_plane_enabled(dev_priv, crtc->plane);
Line 4172... Line 4621...
4172
{
4621
{
4173
	struct drm_device *dev = crtc->dev;
4622
	struct drm_device *dev = crtc->dev;
4174
	struct drm_i915_private *dev_priv = dev->dev_private;
4623
	struct drm_i915_private *dev_priv = dev->dev_private;
4175
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176
	enum pipe pipe = intel_crtc->pipe;
4625
	enum pipe pipe = intel_crtc->pipe;
4177
	int palreg = PALETTE(pipe);
-
 
4178
	int i;
4626
	int i;
4179
	bool reenable_ips = false;
4627
	bool reenable_ips = false;
Line 4180... Line 4628...
4180
 
4628
 
4181
	/* The clocks have to be on to load the palette. */
4629
	/* The clocks have to be on to load the palette. */
4182
	if (!crtc->enabled || !intel_crtc->active)
4630
	if (!crtc->state->active)
Line 4183... Line 4631...
4183
		return;
4631
		return;
4184
 
4632
 
4185
	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4633
	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4186
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4634
		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4187
			assert_dsi_pll_enabled(dev_priv);
4635
			assert_dsi_pll_enabled(dev_priv);
4188
		else
4636
		else
Line 4189... Line -...
4189
			assert_pll_enabled(dev_priv, pipe);
-
 
4190
	}
-
 
4191
 
-
 
4192
	/* use legacy palette for Ironlake */
-
 
4193
	if (!HAS_GMCH_DISPLAY(dev))
4637
			assert_pll_enabled(dev_priv, pipe);
4194
		palreg = LGC_PALETTE(pipe);
4638
	}
4195
 
4639
 
4196
	/* Workaround : Do not read or write the pipe palette/gamma data while
4640
	/* Workaround : Do not read or write the pipe palette/gamma data while
4197
	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4641
	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4198
	 */
4642
	 */
4199
	if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4643
	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4200
	    ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4644
	    ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4201
	     GAMMA_MODE_MODE_SPLIT)) {
4645
	     GAMMA_MODE_MODE_SPLIT)) {
Line 4202... Line 4646...
4202
		hsw_disable_ips(intel_crtc);
4646
		hsw_disable_ips(intel_crtc);
-
 
4647
		reenable_ips = true;
-
 
4648
	}
-
 
4649
 
-
 
4650
	for (i = 0; i < 256; i++) {
-
 
4651
		u32 palreg;
-
 
4652
 
-
 
4653
		if (HAS_GMCH_DISPLAY(dev))
4203
		reenable_ips = true;
4654
			palreg = PALETTE(pipe, i);
4204
	}
4655
		else
4205
 
4656
			palreg = LGC_PALETTE(pipe, i);
4206
	for (i = 0; i < 256; i++) {
4657
 
4207
		I915_WRITE(palreg + 4 * i,
4658
		I915_WRITE(palreg,
Line 4208... Line 4659...
4208
			   (intel_crtc->lut_r[i] << 16) |
4659
			   (intel_crtc->lut_r[i] << 16) |
4209
			   (intel_crtc->lut_g[i] << 8) |
4660
			   (intel_crtc->lut_g[i] << 8) |
4210
			   intel_crtc->lut_b[i]);
4661
			   intel_crtc->lut_b[i]);
Line 4211... Line 4662...
4211
	}
4662
	}
4212
 
4663
 
4213
	if (reenable_ips)
4664
	if (reenable_ips)
4214
		hsw_enable_ips(intel_crtc);
4665
		hsw_enable_ips(intel_crtc);
4215
}
4666
}
Line 4216... Line 4667...
4216
 
4667
 
4217
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4668
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
Line 4230... Line 4681...
4230
	/* Let userspace switch the overlay on again. In most cases userspace
4681
	/* Let userspace switch the overlay on again. In most cases userspace
4231
	 * has to recompute where to put it anyway.
4682
	 * has to recompute where to put it anyway.
4232
	 */
4683
	 */
4233
}
4684
}
Line -... Line 4685...
-
 
4685
 
-
 
4686
/**
-
 
4687
 * intel_post_enable_primary - Perform operations after enabling primary plane
-
 
4688
 * @crtc: the CRTC whose primary plane was just enabled
-
 
4689
 *
-
 
4690
 * Performs potentially sleeping operations that must be done after the primary
-
 
4691
 * plane is enabled, such as updating FBC and IPS.  Note that this may be
-
 
4692
 * called due to an explicit primary plane update, or due to an implicit
-
 
4693
 * re-enable that is caused when a sprite plane is updated to no longer
-
 
4694
 * completely hide the primary plane.
-
 
4695
 */
4234
 
4696
static void
4235
static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4697
intel_post_enable_primary(struct drm_crtc *crtc)
4236
{
4698
{
-
 
4699
	struct drm_device *dev = crtc->dev;
4237
	struct drm_device *dev = crtc->dev;
4700
	struct drm_i915_private *dev_priv = dev->dev_private;
4238
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line -... Line 4702...
-
 
4702
	int pipe = intel_crtc->pipe;
4239
	int pipe = intel_crtc->pipe;
4703
 
4240
 
4704
	/*
4241
	intel_enable_primary_hw_plane(crtc->primary, crtc);
4705
	 * BDW signals flip done immediately if the plane
-
 
4706
	 * is disabled, even if the plane enable is already
-
 
4707
	 * armed to occur at the next vblank :(
4242
	intel_enable_planes(crtc);
4708
	 */
Line -... Line 4709...
-
 
4709
	if (IS_BROADWELL(dev))
-
 
4710
		intel_wait_for_vblank(dev, pipe);
-
 
4711
 
-
 
4712
	/*
-
 
4713
	 * FIXME IPS should be fine as long as one plane is
-
 
4714
	 * enabled, but in practice it seems to have problems
4243
	intel_crtc_update_cursor(crtc, true);
4715
	 * when going from primary only to sprite only and vice
Line 4244... Line -...
4244
	intel_crtc_dpms_overlay(intel_crtc, true);
-
 
4245
 
-
 
4246
	hsw_enable_ips(intel_crtc);
-
 
4247
 
-
 
4248
	mutex_lock(&dev->struct_mutex);
4716
	 * versa.
4249
	intel_update_fbc(dev);
4717
	 */
4250
	mutex_unlock(&dev->struct_mutex);
4718
	hsw_enable_ips(intel_crtc);
-
 
4719
 
-
 
4720
	/*
4251
 
4721
	 * Gen2 reports pipe underruns whenever all planes are disabled.
4252
	/*
4722
	 * So don't enable underrun reporting before at least some planes
-
 
4723
	 * are enabled.
4253
	 * FIXME: Once we grow proper nuclear flip support out of this we need
4724
	 * FIXME: Need to fix the logic to work when we turn off all planes
-
 
4725
	 * but leave the pipe running.
-
 
4726
	 */
-
 
4727
	if (IS_GEN2(dev))
-
 
4728
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4254
	 * to compute the mask of flip planes precisely. For the time being
4729
 
Line -... Line 4730...
-
 
4730
	/* Underruns don't raise interrupts, so check manually. */
-
 
4731
	if (HAS_GMCH_DISPLAY(dev))
-
 
4732
		i9xx_check_fifo_underruns(dev_priv);
-
 
4733
}
-
 
4734
 
-
 
4735
/**
-
 
4736
 * intel_pre_disable_primary - Perform operations before disabling primary plane
-
 
4737
 * @crtc: the CRTC whose primary plane is to be disabled
-
 
4738
 *
-
 
4739
 * Performs potentially sleeping operations that must be done before the
-
 
4740
 * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4255
	 * consider this a flip from a NULL plane.
4741
 * be called due to an explicit primary plane update, or due to an implicit
4256
	 */
4742
 * disable that is caused when a sprite plane completely hides the primary
4257
	intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4743
 * plane.
4258
}
4744
 */
4259
 
4745
static void
4260
static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4746
intel_pre_disable_primary(struct drm_crtc *crtc)
4261
{
-
 
Line -... Line 4747...
-
 
4747
{
-
 
4748
	struct drm_device *dev = crtc->dev;
-
 
4749
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4750
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
4751
	int pipe = intel_crtc->pipe;
-
 
4752
 
-
 
4753
	/*
-
 
4754
	 * Gen2 reports pipe underruns whenever all planes are disabled.
Line -... Line 4755...
-
 
4755
	 * So diasble underrun reporting before all the planes get disabled.
-
 
4756
	 * FIXME: Need to fix the logic to work when we turn off all planes
-
 
4757
	 * but leave the pipe running.
-
 
4758
	 */
-
 
4759
	if (IS_GEN2(dev))
-
 
4760
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 
4761
 
-
 
4762
	/*
-
 
4763
	 * Vblank time updates from the shadow to live plane control register
-
 
4764
	 * are blocked if the memory self-refresh mode is active at that
-
 
4765
	 * moment. So to make sure the plane gets truly disabled, disable
4262
	struct drm_device *dev = crtc->dev;
4766
	 * first the self-refresh mode. The self-refresh enable bit in turn
4263
	struct drm_i915_private *dev_priv = dev->dev_private;
4767
	 * will be checked/applied by the HW only at the next frame start
-
 
4768
	 * event which is after the vblank start event, so we need to have a
Line -... Line 4769...
-
 
4769
	 * wait-for-vblank between disabling the plane and the pipe.
-
 
4770
	 */
-
 
4771
	if (HAS_GMCH_DISPLAY(dev)) {
-
 
4772
		intel_set_memory_cxsr(dev_priv, false);
-
 
4773
		dev_priv->wm.vlv.cxsr = false;
-
 
4774
		intel_wait_for_vblank(dev, pipe);
4264
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775
	}
-
 
4776
 
Line -... Line 4777...
-
 
4777
	/*
-
 
4778
	 * FIXME IPS should be fine as long as one plane is
-
 
4779
	 * enabled, but in practice it seems to have problems
-
 
4780
	 * when going from primary only to sprite only and vice
-
 
4781
	 * versa.
-
 
4782
	 */
-
 
4783
	hsw_disable_ips(intel_crtc);
-
 
4784
}
4265
	int pipe = intel_crtc->pipe;
4785
 
-
 
4786
static void intel_post_plane_update(struct intel_crtc *crtc)
-
 
4787
{
-
 
4788
	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
-
 
4789
	struct drm_device *dev = crtc->base.dev;
-
 
4790
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4791
	struct drm_plane *plane;
-
 
4792
 
4266
	int plane = intel_crtc->plane;
4793
	if (atomic->wait_vblank)
-
 
4794
		intel_wait_for_vblank(dev, crtc->pipe);
-
 
4795
 
-
 
4796
	intel_frontbuffer_flip(dev, atomic->fb_bits);
-
 
4797
 
-
 
4798
	if (atomic->disable_cxsr)
-
 
4799
		crtc->wm.cxsr_allowed = true;
-
 
4800
 
-
 
4801
	if (crtc->atomic.update_wm_post)
-
 
4802
		intel_update_watermarks(&crtc->base);
-
 
4803
 
-
 
4804
	if (atomic->update_fbc)
-
 
4805
		intel_fbc_update(dev_priv);
-
 
4806
 
-
 
4807
	if (atomic->post_enable_primary)
-
 
4808
		intel_post_enable_primary(&crtc->base);
-
 
4809
 
-
 
4810
	drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
-
 
4811
		intel_update_sprite_watermarks(plane, &crtc->base,
-
 
4812
					       0, 0, 0, false, false);
-
 
4813
 
-
 
4814
	memset(atomic, 0, sizeof(*atomic));
-
 
4815
}
-
 
4816
 
-
 
4817
static void intel_pre_plane_update(struct intel_crtc *crtc)
-
 
4818
{
-
 
4819
	struct drm_device *dev = crtc->base.dev;
-
 
4820
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4821
	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
-
 
4822
	struct drm_plane *p;
-
 
4823
 
-
 
4824
	/* Track fb's for any planes being disabled */
-
 
4825
	drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4267
 
4826
		struct intel_plane *plane = to_intel_plane(p);
-
 
4827
 
-
 
4828
		mutex_lock(&dev->struct_mutex);
-
 
4829
		i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
-
 
4830
				  plane->frontbuffer_bit);
-
 
4831
		mutex_unlock(&dev->struct_mutex);
4268
 
4832
	}
-
 
4833
 
-
 
4834
	if (atomic->disable_fbc)
-
 
4835
		intel_fbc_disable_crtc(crtc);
-
 
4836
 
-
 
4837
	if (crtc->atomic.disable_ips)
-
 
4838
		hsw_disable_ips(crtc);
-
 
4839
 
-
 
4840
	if (atomic->pre_disable_primary)
-
 
4841
		intel_pre_disable_primary(&crtc->base);
-
 
4842
 
-
 
4843
	if (atomic->disable_cxsr) {
-
 
4844
		crtc->wm.cxsr_allowed = false;
-
 
4845
		intel_set_memory_cxsr(dev_priv, false);
-
 
4846
	}
-
 
4847
}
-
 
4848
 
-
 
4849
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
-
 
4850
{
Line 4269... Line 4851...
4269
	if (dev_priv->fbc.plane == plane)
4851
	struct drm_device *dev = crtc->dev;
4270
		intel_disable_fbc(dev);
4852
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4271
 
4853
	struct drm_plane *p;
4272
	hsw_disable_ips(intel_crtc);
4854
	int pipe = intel_crtc->pipe;
Line 4290... Line 4872...
4290
    struct drm_i915_private *dev_priv = dev->dev_private;
4872
	struct drm_i915_private *dev_priv = dev->dev_private;
4291
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292
	struct intel_encoder *encoder;
4874
	struct intel_encoder *encoder;
4293
    int pipe = intel_crtc->pipe;
4875
	int pipe = intel_crtc->pipe;
Line 4294... Line -...
4294
 
-
 
4295
	WARN_ON(!crtc->enabled);
-
 
4296
 
4876
 
4297
    if (intel_crtc->active)
4877
	if (WARN_ON(intel_crtc->active))
Line 4298... Line 4878...
4298
        return;
4878
		return;
4299
 
4879
 
Line 4300... Line 4880...
4300
	if (intel_crtc->config.has_pch_encoder)
4880
	if (intel_crtc->config->has_pch_encoder)
4301
		intel_prepare_shared_dpll(intel_crtc);
4881
		intel_prepare_shared_dpll(intel_crtc);
Line 4302... Line 4882...
4302
 
4882
 
Line 4303... Line 4883...
4303
	if (intel_crtc->config.has_dp_encoder)
4883
	if (intel_crtc->config->has_dp_encoder)
4304
		intel_dp_set_m_n(intel_crtc);
4884
		intel_dp_set_m_n(intel_crtc, M1_N1);
4305
 
4885
 
4306
	intel_set_pipe_timings(intel_crtc);
4886
	intel_set_pipe_timings(intel_crtc);
Line 4307... Line 4887...
4307
 
4887
 
Line 4308... Line 4888...
4308
	if (intel_crtc->config.has_pch_encoder) {
4888
	if (intel_crtc->config->has_pch_encoder) {
Line 4319... Line 4899...
4319
 
4899
 
4320
	for_each_encoder_on_crtc(dev, crtc, encoder)
4900
	for_each_encoder_on_crtc(dev, crtc, encoder)
4321
		if (encoder->pre_enable)
4901
		if (encoder->pre_enable)
Line 4322... Line 4902...
4322
			encoder->pre_enable(encoder);
4902
			encoder->pre_enable(encoder);
4323
 
4903
 
4324
	if (intel_crtc->config.has_pch_encoder) {
4904
	if (intel_crtc->config->has_pch_encoder) {
4325
		/* Note: FDI PLL enabling _must_ be done before we enable the
4905
		/* Note: FDI PLL enabling _must_ be done before we enable the
4326
		 * cpu pipes, hence this is separate from all the other fdi/pch
4906
		 * cpu pipes, hence this is separate from all the other fdi/pch
4327
		 * enabling. */
4907
		 * enabling. */
Line 4340... Line 4920...
4340
    intel_crtc_load_lut(crtc);
4920
	intel_crtc_load_lut(crtc);
Line 4341... Line 4921...
4341
 
4921
 
4342
	intel_update_watermarks(crtc);
4922
	intel_update_watermarks(crtc);
Line 4343... Line 4923...
4343
	intel_enable_pipe(intel_crtc);
4923
	intel_enable_pipe(intel_crtc);
4344
 
4924
 
Line -... Line 4925...
-
 
4925
	if (intel_crtc->config->has_pch_encoder)
-
 
4926
		ironlake_pch_enable(crtc);
-
 
4927
 
4345
	if (intel_crtc->config.has_pch_encoder)
4928
	assert_vblank_disabled(crtc);
4346
        ironlake_pch_enable(crtc);
4929
	drm_crtc_vblank_on(crtc);
Line 4347... Line 4930...
4347
 
4930
 
4348
	for_each_encoder_on_crtc(dev, crtc, encoder)
4931
	for_each_encoder_on_crtc(dev, crtc, encoder)
4349
		encoder->enable(encoder);
-
 
4350
 
-
 
4351
	if (HAS_PCH_CPT(dev))
-
 
4352
		cpt_verify_modeset(dev, intel_crtc->pipe);
-
 
4353
 
-
 
4354
	assert_vblank_disabled(crtc);
4932
		encoder->enable(encoder);
Line 4355... Line 4933...
4355
	drm_crtc_vblank_on(crtc);
4933
 
4356
 
4934
	if (HAS_PCH_CPT(dev))
4357
	intel_crtc_enable_planes(crtc);
4935
		cpt_verify_modeset(dev, intel_crtc->pipe);
4358
}
4936
}
4359
 
4937
 
Line 4360... Line -...
4360
/* IPS only exists on ULT machines and is tied to pipe A. */
-
 
4361
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
-
 
4362
{
-
 
4363
	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
-
 
4364
}
-
 
4365
 
-
 
4366
/*
-
 
4367
 * This implements the workaround described in the "notes" section of the mode
-
 
4368
 * set sequence documentation. When going from no pipes or single pipe to
-
 
4369
 * multiple pipes, and planes are enabled after the pipe, we need to wait at
-
 
4370
 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
-
 
4371
 */
-
 
4372
static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
-
 
4373
{
-
 
4374
	struct drm_device *dev = crtc->base.dev;
-
 
4375
	struct intel_crtc *crtc_it, *other_active_crtc = NULL;
-
 
4376
 
-
 
4377
	/* We want to get the other_active_crtc only if there's only 1 other
-
 
4378
	 * active crtc. */
-
 
4379
	for_each_intel_crtc(dev, crtc_it) {
-
 
4380
		if (!crtc_it->active || crtc_it == crtc)
-
 
4381
			continue;
-
 
4382
 
-
 
4383
		if (other_active_crtc)
-
 
4384
		return;
-
 
4385
 
-
 
4386
		other_active_crtc = crtc_it;
-
 
4387
	}
-
 
4388
	if (!other_active_crtc)
-
 
4389
		return;
4938
/* IPS only exists on ULT machines and is tied to pipe A. */
4390
 
4939
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4391
	intel_wait_for_vblank(dev, other_active_crtc->pipe);
4940
{
4392
	intel_wait_for_vblank(dev, other_active_crtc->pipe);
4941
	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4393
}
4942
}
4394
 
4943
 
4395
static void haswell_crtc_enable(struct drm_crtc *crtc)
4944
static void haswell_crtc_enable(struct drm_crtc *crtc)
-
 
4945
{
-
 
4946
	struct drm_device *dev = crtc->dev;
-
 
4947
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 4396... Line -...
4396
{
-
 
4397
	struct drm_device *dev = crtc->dev;
-
 
4398
	struct drm_i915_private *dev_priv = dev->dev_private;
4948
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4399
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949
	struct intel_encoder *encoder;
Line 4400... Line 4950...
4400
	struct intel_encoder *encoder;
4950
	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4401
	int pipe = intel_crtc->pipe;
4951
	struct intel_crtc_state *pipe_config =
Line 4402... Line 4952...
4402
 
4952
		to_intel_crtc_state(crtc->state);
4403
	WARN_ON(!crtc->enabled);
4953
	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
Line 4404... Line 4954...
4404
 
4954
 
Line 4405... Line 4955...
4405
	if (intel_crtc->active)
4955
	if (WARN_ON(intel_crtc->active))
4406
		return;
4956
		return;
4407
 
4957
 
4408
	if (intel_crtc_to_shared_dpll(intel_crtc))
4958
	if (intel_crtc_to_shared_dpll(intel_crtc))
Line 4409... Line 4959...
4409
		intel_enable_shared_dpll(intel_crtc);
4959
		intel_enable_shared_dpll(intel_crtc);
4410
 
4960
 
4411
	if (intel_crtc->config.has_dp_encoder)
4961
	if (intel_crtc->config->has_dp_encoder)
4412
		intel_dp_set_m_n(intel_crtc);
4962
		intel_dp_set_m_n(intel_crtc, M1_N1);
Line 4413... Line 4963...
4413
 
4963
 
Line 4414... Line 4964...
4414
	intel_set_pipe_timings(intel_crtc);
4964
	intel_set_pipe_timings(intel_crtc);
Line 4415... Line 4965...
4415
 
4965
 
Line 4416... Line 4966...
4416
	if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4966
	if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4417
		I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4967
		I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
-
 
4968
			   intel_crtc->config->pixel_multiplier - 1);
-
 
4969
	}
4418
			   intel_crtc->config.pixel_multiplier - 1);
4970
 
4419
	}
4971
	if (intel_crtc->config->has_pch_encoder) {
-
 
4972
		intel_cpu_transcoder_set_m_n(intel_crtc,
Line 4420... Line 4973...
4420
 
4973
				     &intel_crtc->config->fdi_m_n, NULL);
4421
	if (intel_crtc->config.has_pch_encoder) {
4974
	}
4422
		intel_cpu_transcoder_set_m_n(intel_crtc,
4975
 
4423
				     &intel_crtc->config.fdi_m_n, NULL);
4976
	haswell_set_pipeconf(crtc);
4424
	}
4977
 
Line -... Line 4978...
-
 
4978
	intel_set_pipe_csc(crtc);
4425
 
4979
 
Line 4426... Line 4980...
4426
	haswell_set_pipeconf(crtc);
4980
	intel_crtc->active = true;
4427
 
4981
 
4428
	intel_set_pipe_csc(crtc);
4982
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4429
 
4983
	for_each_encoder_on_crtc(dev, crtc, encoder) {
Line 4430... Line 4984...
4430
	intel_crtc->active = true;
4984
		if (encoder->pre_pll_enable)
Line 4452... Line 5006...
4452
	 * clocks enabled
5006
	 * clocks enabled
4453
	 */
5007
	 */
4454
	intel_crtc_load_lut(crtc);
5008
	intel_crtc_load_lut(crtc);
Line 4455... Line 5009...
4455
 
5009
 
-
 
5010
	intel_ddi_set_pipe_settings(crtc);
4456
	intel_ddi_set_pipe_settings(crtc);
5011
	if (!is_dsi)
Line 4457... Line 5012...
4457
	intel_ddi_enable_transcoder_func(crtc);
5012
		intel_ddi_enable_transcoder_func(crtc);
4458
 
5013
 
Line 4459... Line 5014...
4459
	intel_update_watermarks(crtc);
5014
	intel_update_watermarks(crtc);
4460
	intel_enable_pipe(intel_crtc);
5015
	intel_enable_pipe(intel_crtc);
Line 4461... Line 5016...
4461
 
5016
 
4462
	if (intel_crtc->config.has_pch_encoder)
5017
	if (intel_crtc->config->has_pch_encoder)
Line -... Line 5018...
-
 
5018
		lpt_pch_enable(crtc);
-
 
5019
 
-
 
5020
	if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
4463
		lpt_pch_enable(crtc);
5021
		intel_ddi_set_vc_payload_alloc(crtc, true);
4464
 
5022
 
4465
	if (intel_crtc->config.dp_encoder_is_mst)
5023
	assert_vblank_disabled(crtc);
4466
		intel_ddi_set_vc_payload_alloc(crtc, true);
5024
	drm_crtc_vblank_on(crtc);
Line 4467... Line -...
4467
 
-
 
4468
	for_each_encoder_on_crtc(dev, crtc, encoder) {
-
 
4469
		encoder->enable(encoder);
-
 
4470
		intel_opregion_notify_encoder(encoder, true);
5025
 
4471
	}
5026
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4472
 
5027
		encoder->enable(encoder);
4473
	assert_vblank_disabled(crtc);
-
 
4474
	drm_crtc_vblank_on(crtc);
-
 
4475
 
-
 
4476
	/* If we change the relative order between pipe/planes enabling, we need
5028
		intel_opregion_notify_encoder(encoder, true);
4477
	 * to change the workaround. */
-
 
4478
	haswell_mode_set_planes_workaround(intel_crtc);
5029
	}
4479
	intel_crtc_enable_planes(crtc);
5030
 
4480
}
-
 
4481
 
-
 
4482
static void skylake_pfit_disable(struct intel_crtc *crtc)
-
 
4483
{
-
 
4484
	struct drm_device *dev = crtc->base.dev;
-
 
4485
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4486
	int pipe = crtc->pipe;
-
 
4487
 
-
 
4488
	/* To avoid upsetting the power well on haswell only disable the pfit if
5031
	/* If we change the relative order between pipe/planes enabling, we need
4489
	 * it's in use. The hw state code will make sure we get this right. */
5032
	 * to change the workaround. */
Line 4490... Line 5033...
4490
	if (crtc->config.pch_pfit.enabled) {
5033
	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4491
		I915_WRITE(PS_CTL(pipe), 0);
5034
	if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4492
		I915_WRITE(PS_WIN_POS(pipe), 0);
5035
		intel_wait_for_vblank(dev, hsw_workaround_pipe);
4493
		I915_WRITE(PS_WIN_SZ(pipe), 0);
5036
		intel_wait_for_vblank(dev, hsw_workaround_pipe);
4494
	}
5037
	}
Line 4495... Line 5038...
4495
}
5038
}
4496
 
5039
 
4497
static void ironlake_pfit_disable(struct intel_crtc *crtc)
5040
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4498
{
5041
{
4499
	struct drm_device *dev = crtc->base.dev;
5042
	struct drm_device *dev = crtc->base.dev;
4500
	struct drm_i915_private *dev_priv = dev->dev_private;
5043
	struct drm_i915_private *dev_priv = dev->dev_private;
4501
	int pipe = crtc->pipe;
5044
	int pipe = crtc->pipe;
4502
 
5045
 
Line 4516... Line 5059...
4516
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4517
	struct intel_encoder *encoder;
5060
	struct intel_encoder *encoder;
4518
    int pipe = intel_crtc->pipe;
5061
	int pipe = intel_crtc->pipe;
4519
    u32 reg, temp;
5062
	u32 reg, temp;
Line 4520... Line 5063...
4520
 
5063
 
4521
    if (!intel_crtc->active)
-
 
4522
        return;
-
 
4523
 
5064
	for_each_encoder_on_crtc(dev, crtc, encoder)
Line 4524... Line 5065...
4524
	intel_crtc_disable_planes(crtc);
5065
		encoder->disable(encoder);
4525
 
5066
 
Line 4526... Line -...
4526
	drm_crtc_vblank_off(crtc);
-
 
4527
	assert_vblank_disabled(crtc);
-
 
4528
 
-
 
4529
	for_each_encoder_on_crtc(dev, crtc, encoder)
5067
	drm_crtc_vblank_off(crtc);
4530
		encoder->disable(encoder);
5068
	assert_vblank_disabled(crtc);
Line 4531... Line 5069...
4531
 
5069
 
Line 4532... Line 5070...
4532
	if (intel_crtc->config.has_pch_encoder)
5070
	if (intel_crtc->config->has_pch_encoder)
-
 
5071
		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
-
 
5072
 
-
 
5073
	intel_disable_pipe(intel_crtc);
Line 4533... Line 5074...
4533
		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5074
 
4534
 
5075
	ironlake_pfit_disable(intel_crtc, false);
4535
	intel_disable_pipe(intel_crtc);
5076
 
Line 4536... Line 5077...
4536
 
5077
	if (intel_crtc->config->has_pch_encoder)
4537
	ironlake_pfit_disable(intel_crtc);
-
 
4538
 
-
 
4539
	for_each_encoder_on_crtc(dev, crtc, encoder)
5078
		ironlake_fdi_disable(crtc);
Line 4540... Line 5079...
4540
		if (encoder->post_disable)
5079
 
4541
			encoder->post_disable(encoder);
5080
	for_each_encoder_on_crtc(dev, crtc, encoder)
4542
 
5081
		if (encoder->post_disable)
Line 4558... Line 5097...
4558
        temp = I915_READ(PCH_DPLL_SEL);
5097
			temp = I915_READ(PCH_DPLL_SEL);
4559
			temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5098
			temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4560
        I915_WRITE(PCH_DPLL_SEL, temp);
5099
			I915_WRITE(PCH_DPLL_SEL, temp);
4561
    }
5100
		}
Line 4562... Line -...
4562
 
-
 
4563
    /* disable PCH DPLL */
-
 
4564
		intel_disable_shared_dpll(intel_crtc);
-
 
4565
 
5101
 
4566
	ironlake_fdi_pll_disable(intel_crtc);
5102
		ironlake_fdi_pll_disable(intel_crtc);
4567
	}
-
 
4568
 
-
 
4569
    intel_crtc->active = false;
-
 
4570
	intel_update_watermarks(crtc);
-
 
4571
 
-
 
4572
    mutex_lock(&dev->struct_mutex);
-
 
4573
    intel_update_fbc(dev);
-
 
4574
    mutex_unlock(&dev->struct_mutex);
5103
	}
Line 4575... Line 5104...
4575
}
5104
}
4576
 
5105
 
4577
static void haswell_crtc_disable(struct drm_crtc *crtc)
5106
static void haswell_crtc_disable(struct drm_crtc *crtc)
4578
{
5107
{
4579
	struct drm_device *dev = crtc->dev;
5108
	struct drm_device *dev = crtc->dev;
4580
	struct drm_i915_private *dev_priv = dev->dev_private;
5109
	struct drm_i915_private *dev_priv = dev->dev_private;
4581
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5110
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582
	struct intel_encoder *encoder;
-
 
4583
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
-
 
4584
 
-
 
4585
	if (!intel_crtc->active)
-
 
4586
		return;
5111
	struct intel_encoder *encoder;
4587
 
-
 
4588
	intel_crtc_disable_planes(crtc);
-
 
4589
 
-
 
Line 4590... Line 5112...
4590
	drm_crtc_vblank_off(crtc);
5112
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4591
	assert_vblank_disabled(crtc);
5113
	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4592
 
5114
 
4593
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5115
	for_each_encoder_on_crtc(dev, crtc, encoder) {
Line -... Line 5116...
-
 
5116
		intel_opregion_notify_encoder(encoder, false);
-
 
5117
		encoder->disable(encoder);
-
 
5118
	}
4594
		intel_opregion_notify_encoder(encoder, false);
5119
 
4595
		encoder->disable(encoder);
5120
	drm_crtc_vblank_off(crtc);
4596
	}
5121
	assert_vblank_disabled(crtc);
4597
 
5122
 
Line 4598... Line 5123...
4598
	if (intel_crtc->config.has_pch_encoder)
5123
	if (intel_crtc->config->has_pch_encoder)
4599
		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5124
		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
Line -... Line 5125...
-
 
5125
						      false);
4600
						      false);
5126
	intel_disable_pipe(intel_crtc);
Line 4601... Line 5127...
4601
	intel_disable_pipe(intel_crtc);
5127
 
4602
 
5128
	if (intel_crtc->config->dp_encoder_is_mst)
4603
	if (intel_crtc->config.dp_encoder_is_mst)
5129
		intel_ddi_set_vc_payload_alloc(crtc, false);
4604
		intel_ddi_set_vc_payload_alloc(crtc, false);
5130
 
Line -... Line 5131...
-
 
5131
	if (!is_dsi)
4605
 
5132
		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Line 4606... Line 5133...
4606
	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5133
 
4607
 
5134
	if (INTEL_INFO(dev)->gen >= 9)
4608
	if (IS_SKYLAKE(dev))
5135
		skylake_scaler_disable(intel_crtc);
4609
		skylake_pfit_disable(intel_crtc);
5136
	else
Line 4610... Line 5137...
4610
	else
5137
		ironlake_pfit_disable(intel_crtc, false);
4611
	ironlake_pfit_disable(intel_crtc);
5138
 
4612
 
5139
	if (!is_dsi)
4613
	intel_ddi_disable_pipe_clock(intel_crtc);
-
 
4614
 
-
 
4615
	if (intel_crtc->config.has_pch_encoder) {
-
 
4616
		lpt_disable_pch_transcoder(dev_priv);
-
 
4617
		intel_ddi_fdi_disable(crtc);
-
 
4618
	}
-
 
4619
 
-
 
4620
	for_each_encoder_on_crtc(dev, crtc, encoder)
-
 
4621
		if (encoder->post_disable)
-
 
4622
			encoder->post_disable(encoder);
-
 
4623
 
5140
		intel_ddi_disable_pipe_clock(intel_crtc);
Line 4624... Line -...
4624
	intel_crtc->active = false;
-
 
4625
	intel_update_watermarks(crtc);
-
 
4626
 
-
 
4627
	mutex_lock(&dev->struct_mutex);
-
 
4628
	intel_update_fbc(dev);
-
 
4629
	mutex_unlock(&dev->struct_mutex);
-
 
4630
 
-
 
4631
	if (intel_crtc_to_shared_dpll(intel_crtc))
5141
 
4632
		intel_disable_shared_dpll(intel_crtc);
5142
	if (intel_crtc->config->has_pch_encoder) {
4633
}
5143
		lpt_disable_pch_transcoder(dev_priv);
4634
 
5144
		intel_ddi_fdi_disable(crtc);
4635
static void ironlake_crtc_off(struct drm_crtc *crtc)
5145
	}
Line 4636... Line 5146...
4636
{
5146
 
4637
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5147
	for_each_encoder_on_crtc(dev, crtc, encoder)
Line 4638... Line 5148...
4638
	intel_put_shared_dpll(intel_crtc);
5148
		if (encoder->post_disable)
4639
}
5149
			encoder->post_disable(encoder);
4640
 
5150
}
Line 4672... Line 5182...
4672
		return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5182
		return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4673
	case PORT_C:
5183
	case PORT_C:
4674
		return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5184
		return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4675
	case PORT_D:
5185
	case PORT_D:
4676
		return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5186
		return POWER_DOMAIN_PORT_DDI_D_4_LANES;
-
 
5187
	case PORT_E:
-
 
5188
		return POWER_DOMAIN_PORT_DDI_E_2_LANES;
4677
	default:
5189
	default:
4678
		WARN_ON_ONCE(1);
5190
		MISSING_CASE(port);
4679
		return POWER_DOMAIN_PORT_OTHER;
5191
		return POWER_DOMAIN_PORT_OTHER;
4680
	}
5192
	}
4681
}
5193
}
Line -... Line 5194...
-
 
5194
 
-
 
5195
static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
-
 
5196
{
-
 
5197
	switch (port) {
-
 
5198
	case PORT_A:
-
 
5199
		return POWER_DOMAIN_AUX_A;
-
 
5200
	case PORT_B:
-
 
5201
		return POWER_DOMAIN_AUX_B;
-
 
5202
	case PORT_C:
-
 
5203
		return POWER_DOMAIN_AUX_C;
-
 
5204
	case PORT_D:
-
 
5205
		return POWER_DOMAIN_AUX_D;
-
 
5206
	case PORT_E:
-
 
5207
		/* FIXME: Check VBT for actual wiring of PORT E */
-
 
5208
		return POWER_DOMAIN_AUX_D;
-
 
5209
	default:
-
 
5210
		MISSING_CASE(port);
-
 
5211
		return POWER_DOMAIN_AUX_A;
-
 
5212
	}
-
 
5213
}
4682
 
5214
 
4683
#define for_each_power_domain(domain, mask)				\
5215
#define for_each_power_domain(domain, mask)				\
4684
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
5216
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
Line 4685... Line 5217...
4685
		if ((1 << (domain)) & (mask))
5217
		if ((1 << (domain)) & (mask))
Line 4709... Line 5241...
4709
	default:
5241
	default:
4710
		return POWER_DOMAIN_PORT_OTHER;
5242
		return POWER_DOMAIN_PORT_OTHER;
4711
	}
5243
	}
4712
}
5244
}
Line -... Line 5245...
-
 
5245
 
-
 
5246
enum intel_display_power_domain
-
 
5247
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
-
 
5248
{
-
 
5249
	struct drm_device *dev = intel_encoder->base.dev;
-
 
5250
	struct intel_digital_port *intel_dig_port;
-
 
5251
 
-
 
5252
	switch (intel_encoder->type) {
-
 
5253
	case INTEL_OUTPUT_UNKNOWN:
-
 
5254
	case INTEL_OUTPUT_HDMI:
-
 
5255
		/*
-
 
5256
		 * Only DDI platforms should ever use these output types.
-
 
5257
		 * We can get here after the HDMI detect code has already set
-
 
5258
		 * the type of the shared encoder. Since we can't be sure
-
 
5259
		 * what's the status of the given connectors, play safe and
-
 
5260
		 * run the DP detection too.
-
 
5261
		 */
-
 
5262
		WARN_ON_ONCE(!HAS_DDI(dev));
-
 
5263
	case INTEL_OUTPUT_DISPLAYPORT:
-
 
5264
	case INTEL_OUTPUT_EDP:
-
 
5265
		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
-
 
5266
		return port_to_aux_power_domain(intel_dig_port->port);
-
 
5267
	case INTEL_OUTPUT_DP_MST:
-
 
5268
		intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
-
 
5269
		return port_to_aux_power_domain(intel_dig_port->port);
-
 
5270
	default:
-
 
5271
		MISSING_CASE(intel_encoder->type);
-
 
5272
		return POWER_DOMAIN_AUX_A;
-
 
5273
	}
-
 
5274
}
4713
 
5275
 
4714
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5276
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4715
{
5277
{
4716
	struct drm_device *dev = crtc->dev;
5278
	struct drm_device *dev = crtc->dev;
4717
	struct intel_encoder *intel_encoder;
5279
	struct intel_encoder *intel_encoder;
4718
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5280
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719
	enum pipe pipe = intel_crtc->pipe;
5281
	enum pipe pipe = intel_crtc->pipe;
4720
	unsigned long mask;
5282
	unsigned long mask;
Line -... Line 5283...
-
 
5283
	enum transcoder transcoder;
-
 
5284
 
-
 
5285
	if (!crtc->state->active)
4721
	enum transcoder transcoder;
5286
		return 0;
Line 4722... Line 5287...
4722
 
5287
 
4723
	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5288
	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4724
 
5289
 
4725
	mask = BIT(POWER_DOMAIN_PIPE(pipe));
5290
	mask = BIT(POWER_DOMAIN_PIPE(pipe));
4726
	mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5291
	mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Line 4727... Line 5292...
4727
	if (intel_crtc->config.pch_pfit.enabled ||
5292
	if (intel_crtc->config->pch_pfit.enabled ||
4728
	    intel_crtc->config.pch_pfit.force_thru)
5293
	    intel_crtc->config->pch_pfit.force_thru)
Line 4729... Line 5294...
4729
		mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5294
		mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4730
 
5295
 
Line 4731... Line 5296...
4731
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5296
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4732
		mask |= BIT(intel_display_port_power_domain(intel_encoder));
5297
		mask |= BIT(intel_display_port_power_domain(intel_encoder));
4733
 
5298
 
4734
	return mask;
-
 
4735
}
5299
	return mask;
4736
 
-
 
4737
static void modeset_update_crtc_power_domains(struct drm_device *dev)
-
 
4738
{
-
 
4739
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
4740
	unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
-
 
4741
	struct intel_crtc *crtc;
-
 
4742
 
5300
}
-
 
5301
 
Line 4743... Line 5302...
4743
	/*
5302
static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
4744
	 * First get all needed power domains, then put all unneeded, to avoid
5303
{
Line 4745... Line 5304...
4745
	 * any unnecessary toggling of the power wells.
5304
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
Line 4746... Line 5305...
4746
	 */
5305
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747
	for_each_intel_crtc(dev, crtc) {
5306
	enum intel_display_power_domain domain;
4748
		enum intel_display_power_domain domain;
-
 
Line 4749... Line 5307...
4749
 
5307
	unsigned long domains, new_domains, old_domains;
4750
		if (!crtc->base.enabled)
-
 
-
 
5308
 
Line -... Line 5309...
-
 
5309
	old_domains = intel_crtc->enabled_power_domains;
4751
			continue;
5310
	intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
-
 
5311
 
4752
 
5312
	domains = new_domains & ~old_domains;
Line 4753... Line 5313...
4753
		pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5313
 
4754
 
5314
	for_each_power_domain(domain, domains)
-
 
5315
		intel_display_power_get(dev_priv, domain);
Line -... Line 5316...
-
 
5316
 
-
 
5317
	return old_domains & ~new_domains;
-
 
5318
}
-
 
5319
 
-
 
5320
static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
-
 
5321
				      unsigned long domains)
-
 
5322
{
-
 
5323
	enum intel_display_power_domain domain;
-
 
5324
 
-
 
5325
	for_each_power_domain(domain, domains)
-
 
5326
		intel_display_power_put(dev_priv, domain);
4755
		for_each_power_domain(domain, pipe_domains[crtc->pipe])
5327
}
-
 
5328
 
4756
			intel_display_power_get(dev_priv, domain);
5329
static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
Line -... Line 5330...
-
 
5330
{
-
 
5331
	struct drm_device *dev = state->dev;
-
 
5332
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5333
	unsigned long put_domains[I915_MAX_PIPES] = {};
-
 
5334
	struct drm_crtc_state *crtc_state;
4757
	}
5335
	struct drm_crtc *crtc;
4758
 
5336
	int i;
Line 4759... Line 5337...
4759
	if (dev_priv->display.modeset_global_resources)
5337
 
-
 
5338
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-
 
5339
		if (needs_modeset(crtc->state))
-
 
5340
			put_domains[to_intel_crtc(crtc)->pipe] =
-
 
5341
				modeset_get_crtc_power_domains(crtc);
4760
		dev_priv->display.modeset_global_resources(dev);
5342
	}
4761
 
5343
 
4762
	for_each_intel_crtc(dev, crtc) {
5344
	if (dev_priv->display.modeset_commit_cdclk) {
Line -... Line 5345...
-
 
5345
		unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
-
 
5346
 
4763
		enum intel_display_power_domain domain;
5347
		if (cdclk != dev_priv->cdclk_freq &&
4764
 
5348
		    !WARN_ON(!state->allow_modeset))
-
 
5349
			dev_priv->display.modeset_commit_cdclk(state);
4765
		for_each_power_domain(domain, crtc->enabled_power_domains)
5350
	}
4766
			intel_display_power_put(dev_priv, domain);
5351
 
-
 
5352
	for (i = 0; i < I915_MAX_PIPES; i++)
4767
 
5353
		if (put_domains[i])
-
 
5354
			modeset_put_power_domains(dev_priv, put_domains[i]);
Line -... Line 5355...
-
 
5355
}
-
 
5356
 
-
 
5357
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
-
 
5358
{
-
 
5359
	int max_cdclk_freq = dev_priv->max_cdclk_freq;
-
 
5360
 
-
 
5361
	if (INTEL_INFO(dev_priv)->gen >= 9 ||
-
 
5362
	    IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-
 
5363
		return max_cdclk_freq;
-
 
5364
	else if (IS_CHERRYVIEW(dev_priv))
-
 
5365
		return max_cdclk_freq*95/100;
-
 
5366
	else if (INTEL_INFO(dev_priv)->gen < 4)
-
 
5367
		return 2*max_cdclk_freq*90/100;
-
 
5368
	else
-
 
5369
		return max_cdclk_freq*90/100;
-
 
5370
}
-
 
5371
 
-
 
5372
static void intel_update_max_cdclk(struct drm_device *dev)
-
 
5373
{
-
 
5374
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5375
 
-
 
5376
	if (IS_SKYLAKE(dev)) {
-
 
5377
		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
-
 
5378
 
-
 
5379
		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
-
 
5380
			dev_priv->max_cdclk_freq = 675000;
-
 
5381
		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
-
 
5382
			dev_priv->max_cdclk_freq = 540000;
-
 
5383
		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
-
 
5384
			dev_priv->max_cdclk_freq = 450000;
-
 
5385
		else
-
 
5386
			dev_priv->max_cdclk_freq = 337500;
-
 
5387
	} else if (IS_BROADWELL(dev))  {
4768
		crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5388
		/*
-
 
5389
		 * FIXME with extra cooling we can allow
-
 
5390
		 * 540 MHz for ULX and 675 Mhz for ULT.
-
 
5391
		 * How can we know if extra cooling is
-
 
5392
		 * available? PCI ID, VTB, something else?
-
 
5393
		 */
-
 
5394
		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-
 
5395
			dev_priv->max_cdclk_freq = 450000;
-
 
5396
		else if (IS_BDW_ULX(dev))
-
 
5397
			dev_priv->max_cdclk_freq = 450000;
-
 
5398
		else if (IS_BDW_ULT(dev))
-
 
5399
			dev_priv->max_cdclk_freq = 540000;
-
 
5400
		else
4769
	}
5401
			dev_priv->max_cdclk_freq = 675000;
Line 4770... Line 5402...
4770
 
5402
	} else if (IS_CHERRYVIEW(dev)) {
4771
	intel_display_set_init_power(dev_priv, false);
5403
		dev_priv->max_cdclk_freq = 320000;
4772
}
5404
	} else if (IS_VALLEYVIEW(dev)) {
Line 4773... Line 5405...
4773
 
5405
		dev_priv->max_cdclk_freq = 400000;
4774
/* returns HPLL frequency in kHz */
5406
	} else {
4775
static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5407
		/* otherwise assume cdclk is fixed */
Line 4776... Line 5408...
4776
{
5408
		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
4777
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5409
	}
4778
 
5410
 
4779
	/* Obtain SKU information */
5411
	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
4780
	mutex_lock(&dev_priv->dpio_lock);
5412
 
-
 
5413
	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
-
 
5414
			 dev_priv->max_cdclk_freq);
-
 
5415
 
-
 
5416
	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
-
 
5417
			 dev_priv->max_dotclk_freq);
-
 
5418
}
4781
	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5419
 
-
 
5420
static void intel_update_cdclk(struct drm_device *dev)
-
 
5421
{
-
 
5422
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5423
 
-
 
5424
	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-
 
5425
	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
-
 
5426
			 dev_priv->cdclk_freq);
-
 
5427
 
-
 
5428
	/*
-
 
5429
	 * Program the gmbus_freq based on the cdclk frequency.
-
 
5430
	 * BSpec erroneously claims we should aim for 4MHz, but
-
 
5431
	 * in fact 1MHz is the correct frequency.
-
 
5432
	 */
-
 
5433
	if (IS_VALLEYVIEW(dev)) {
-
 
5434
		/*
-
 
5435
		 * Program the gmbus_freq based on the cdclk frequency.
-
 
5436
		 * BSpec erroneously claims we should aim for 4MHz, but
-
 
5437
		 * in fact 1MHz is the correct frequency.
-
 
5438
		 */
-
 
5439
		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
-
 
5440
	}
-
 
5441
 
-
 
5442
	if (dev_priv->max_cdclk_freq == 0)
-
 
5443
		intel_update_max_cdclk(dev);
-
 
5444
}
-
 
5445
 
-
 
5446
static void broxton_set_cdclk(struct drm_device *dev, int frequency)
-
 
5447
{
-
 
5448
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5449
	uint32_t divider;
-
 
5450
	uint32_t ratio;
-
 
5451
	uint32_t current_freq;
-
 
5452
	int ret;
-
 
5453
 
-
 
5454
	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
-
 
5455
	switch (frequency) {
-
 
5456
	case 144000:
-
 
5457
		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
-
 
5458
		ratio = BXT_DE_PLL_RATIO(60);
-
 
5459
		break;
-
 
5460
	case 288000:
-
 
5461
		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
-
 
5462
		ratio = BXT_DE_PLL_RATIO(60);
-
 
5463
		break;
-
 
5464
	case 384000:
-
 
5465
		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
-
 
5466
		ratio = BXT_DE_PLL_RATIO(60);
-
 
5467
		break;
-
 
5468
	case 576000:
-
 
5469
		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
-
 
5470
		ratio = BXT_DE_PLL_RATIO(60);
-
 
5471
		break;
-
 
5472
	case 624000:
-
 
5473
		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
-
 
5474
		ratio = BXT_DE_PLL_RATIO(65);
-
 
5475
		break;
-
 
5476
	case 19200:
-
 
5477
		/*
-
 
5478
		 * Bypass frequency with DE PLL disabled. Init ratio, divider
-
 
5479
		 * to suppress GCC warning.
-
 
5480
		 */
-
 
5481
		ratio = 0;
-
 
5482
		divider = 0;
-
 
5483
		break;
-
 
5484
	default:
-
 
5485
		DRM_ERROR("unsupported CDCLK freq %d", frequency);
-
 
5486
 
-
 
5487
		return;
-
 
5488
	}
-
 
5489
 
-
 
5490
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
5491
	/* Inform power controller of upcoming frequency change */
-
 
5492
	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
-
 
5493
				      0x80000000);
-
 
5494
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
5495
 
-
 
5496
	if (ret) {
-
 
5497
		DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
-
 
5498
			  ret, frequency);
-
 
5499
		return;
-
 
5500
	}
-
 
5501
 
-
 
5502
	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
-
 
5503
	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
-
 
5504
	current_freq = current_freq * 500 + 1000;
-
 
5505
 
-
 
5506
	/*
-
 
5507
	 * DE PLL has to be disabled when
-
 
5508
	 * - setting to 19.2MHz (bypass, PLL isn't used)
-
 
5509
	 * - before setting to 624MHz (PLL needs toggling)
-
 
5510
	 * - before setting to any frequency from 624MHz (PLL needs toggling)
-
 
5511
	 */
-
 
5512
	if (frequency == 19200 || frequency == 624000 ||
-
 
5513
	    current_freq == 624000) {
-
 
5514
		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
-
 
5515
		/* Timeout 200us */
-
 
5516
		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
-
 
5517
			     1))
-
 
5518
			DRM_ERROR("timout waiting for DE PLL unlock\n");
-
 
5519
	}
-
 
5520
 
-
 
5521
	if (frequency != 19200) {
-
 
5522
		uint32_t val;
-
 
5523
 
-
 
5524
		val = I915_READ(BXT_DE_PLL_CTL);
-
 
5525
		val &= ~BXT_DE_PLL_RATIO_MASK;
-
 
5526
		val |= ratio;
-
 
5527
		I915_WRITE(BXT_DE_PLL_CTL, val);
-
 
5528
 
-
 
5529
		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
-
 
5530
		/* Timeout 200us */
-
 
5531
		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
-
 
5532
			DRM_ERROR("timeout waiting for DE PLL lock\n");
-
 
5533
 
-
 
5534
		val = I915_READ(CDCLK_CTL);
-
 
5535
		val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
-
 
5536
		val |= divider;
-
 
5537
		/*
-
 
5538
		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
-
 
5539
		 * enable otherwise.
-
 
5540
		 */
-
 
5541
		val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
-
 
5542
		if (frequency >= 500000)
-
 
5543
			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
-
 
5544
 
-
 
5545
		val &= ~CDCLK_FREQ_DECIMAL_MASK;
-
 
5546
		/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
-
 
5547
		val |= (frequency - 1000) / 500;
-
 
5548
		I915_WRITE(CDCLK_CTL, val);
-
 
5549
	}
-
 
5550
 
-
 
5551
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
5552
	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
-
 
5553
				      DIV_ROUND_UP(frequency, 25000));
-
 
5554
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
5555
 
-
 
5556
	if (ret) {
-
 
5557
		DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
-
 
5558
			  ret, frequency);
-
 
5559
		return;
-
 
5560
	}
-
 
5561
 
-
 
5562
	intel_update_cdclk(dev);
-
 
5563
}
-
 
5564
 
-
 
5565
void broxton_init_cdclk(struct drm_device *dev)
-
 
5566
{
-
 
5567
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5568
	uint32_t val;
-
 
5569
 
-
 
5570
	/*
-
 
5571
	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
-
 
5572
	 * or else the reset will hang because there is no PCH to respond.
-
 
5573
	 * Move the handshake programming to initialization sequence.
-
 
5574
	 * Previously was left up to BIOS.
-
 
5575
	 */
-
 
5576
	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-
 
5577
	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
-
 
5578
	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
-
 
5579
 
-
 
5580
	/* Enable PG1 for cdclk */
-
 
5581
	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
-
 
5582
 
-
 
5583
	/* check if cd clock is enabled */
-
 
5584
	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
-
 
5585
		DRM_DEBUG_KMS("Display already initialized\n");
-
 
5586
		return;
-
 
5587
	}
-
 
5588
 
-
 
5589
	/*
-
 
5590
	 * FIXME:
-
 
5591
	 * - The initial CDCLK needs to be read from VBT.
-
 
5592
	 *   Need to make this change after VBT has changes for BXT.
-
 
5593
	 * - check if setting the max (or any) cdclk freq is really necessary
-
 
5594
	 *   here, it belongs to modeset time
-
 
5595
	 */
-
 
5596
	broxton_set_cdclk(dev, 624000);
-
 
5597
 
-
 
5598
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
-
 
5599
	POSTING_READ(DBUF_CTL);
-
 
5600
 
-
 
5601
	udelay(10);
-
 
5602
 
-
 
5603
	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
-
 
5604
		DRM_ERROR("DBuf power enable timeout!\n");
-
 
5605
}
-
 
5606
 
-
 
5607
void broxton_uninit_cdclk(struct drm_device *dev)
-
 
5608
{
-
 
5609
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5610
 
-
 
5611
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
-
 
5612
	POSTING_READ(DBUF_CTL);
-
 
5613
 
-
 
5614
	udelay(10);
-
 
5615
 
-
 
5616
	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-
 
5617
		DRM_ERROR("DBuf power disable timeout!\n");
-
 
5618
 
-
 
5619
	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
-
 
5620
	broxton_set_cdclk(dev, 19200);
-
 
5621
 
-
 
5622
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
-
 
5623
}
-
 
5624
 
-
 
5625
static const struct skl_cdclk_entry {
-
 
5626
	unsigned int freq;
-
 
5627
	unsigned int vco;
-
 
5628
} skl_cdclk_frequencies[] = {
-
 
5629
	{ .freq = 308570, .vco = 8640 },
-
 
5630
	{ .freq = 337500, .vco = 8100 },
-
 
5631
	{ .freq = 432000, .vco = 8640 },
-
 
5632
	{ .freq = 450000, .vco = 8100 },
-
 
5633
	{ .freq = 540000, .vco = 8100 },
-
 
5634
	{ .freq = 617140, .vco = 8640 },
-
 
5635
	{ .freq = 675000, .vco = 8100 },
-
 
5636
};
-
 
5637
 
-
 
5638
static unsigned int skl_cdclk_decimal(unsigned int freq)
-
 
5639
{
-
 
5640
	return (freq - 1000) / 500;
-
 
5641
}
-
 
5642
 
-
 
5643
static unsigned int skl_cdclk_get_vco(unsigned int freq)
-
 
5644
{
-
 
5645
	unsigned int i;
-
 
5646
 
-
 
5647
	for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
-
 
5648
		const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
-
 
5649
 
-
 
5650
		if (e->freq == freq)
-
 
5651
			return e->vco;
-
 
5652
	}
-
 
5653
 
-
 
5654
	return 8100;
-
 
5655
}
-
 
5656
 
-
 
5657
static void
-
 
5658
skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
-
 
5659
{
-
 
5660
	unsigned int min_freq;
-
 
5661
	u32 val;
-
 
5662
 
-
 
5663
	/* select the minimum CDCLK before enabling DPLL 0 */
-
 
5664
	val = I915_READ(CDCLK_CTL);
-
 
5665
	val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
-
 
5666
	val |= CDCLK_FREQ_337_308;
-
 
5667
 
-
 
5668
	if (required_vco == 8640)
-
 
5669
		min_freq = 308570;
-
 
5670
	else
-
 
5671
		min_freq = 337500;
-
 
5672
 
-
 
5673
	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
-
 
5674
 
-
 
5675
	I915_WRITE(CDCLK_CTL, val);
-
 
5676
	POSTING_READ(CDCLK_CTL);
-
 
5677
 
-
 
5678
	/*
-
 
5679
	 * We always enable DPLL0 with the lowest link rate possible, but still
-
 
5680
	 * taking into account the VCO required to operate the eDP panel at the
-
 
5681
	 * desired frequency. The usual DP link rates operate with a VCO of
-
 
5682
	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
-
 
5683
	 * The modeset code is responsible for the selection of the exact link
-
 
5684
	 * rate later on, with the constraint of choosing a frequency that
-
 
5685
	 * works with required_vco.
-
 
5686
	 */
-
 
5687
	val = I915_READ(DPLL_CTRL1);
-
 
5688
 
-
 
5689
	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
-
 
5690
		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
-
 
5691
	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-
 
5692
	if (required_vco == 8640)
-
 
5693
		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
-
 
5694
					    SKL_DPLL0);
-
 
5695
	else
-
 
5696
		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
-
 
5697
					    SKL_DPLL0);
-
 
5698
 
-
 
5699
	I915_WRITE(DPLL_CTRL1, val);
-
 
5700
	POSTING_READ(DPLL_CTRL1);
-
 
5701
 
-
 
5702
	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
-
 
5703
 
-
 
5704
	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
-
 
5705
		DRM_ERROR("DPLL0 not locked\n");
-
 
5706
}
-
 
5707
 
-
 
5708
static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
-
 
5709
{
-
 
5710
	int ret;
-
 
5711
	u32 val;
-
 
5712
 
-
 
5713
	/* inform PCU we want to change CDCLK */
-
 
5714
	val = SKL_CDCLK_PREPARE_FOR_CHANGE;
-
 
5715
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
5716
	ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
-
 
5717
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
5718
 
-
 
5719
	return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
-
 
5720
}
-
 
5721
 
-
 
5722
static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
-
 
5723
{
-
 
5724
	unsigned int i;
-
 
5725
 
-
 
5726
	for (i = 0; i < 15; i++) {
-
 
5727
		if (skl_cdclk_pcu_ready(dev_priv))
-
 
5728
			return true;
-
 
5729
		udelay(10);
-
 
5730
	}
-
 
5731
 
-
 
5732
	return false;
-
 
5733
}
-
 
5734
 
-
 
5735
static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
-
 
5736
{
-
 
5737
	struct drm_device *dev = dev_priv->dev;
-
 
5738
	u32 freq_select, pcu_ack;
-
 
5739
 
-
 
5740
	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
-
 
5741
 
-
 
5742
	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
-
 
5743
		DRM_ERROR("failed to inform PCU about cdclk change\n");
-
 
5744
		return;
-
 
5745
	}
-
 
5746
 
-
 
5747
	/* set CDCLK_CTL */
-
 
5748
	switch(freq) {
-
 
5749
	case 450000:
-
 
5750
	case 432000:
-
 
5751
		freq_select = CDCLK_FREQ_450_432;
-
 
5752
		pcu_ack = 1;
-
 
5753
		break;
-
 
5754
	case 540000:
-
 
5755
		freq_select = CDCLK_FREQ_540;
-
 
5756
		pcu_ack = 2;
-
 
5757
		break;
-
 
5758
	case 308570:
-
 
5759
	case 337500:
-
 
5760
	default:
-
 
5761
		freq_select = CDCLK_FREQ_337_308;
-
 
5762
		pcu_ack = 0;
-
 
5763
		break;
-
 
5764
	case 617140:
-
 
5765
	case 675000:
-
 
5766
		freq_select = CDCLK_FREQ_675_617;
-
 
5767
		pcu_ack = 3;
-
 
5768
		break;
-
 
5769
	}
-
 
5770
 
-
 
5771
	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
-
 
5772
	POSTING_READ(CDCLK_CTL);
-
 
5773
 
-
 
5774
	/* inform PCU of the change */
-
 
5775
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
5776
	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
-
 
5777
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
5778
 
-
 
5779
	intel_update_cdclk(dev);
-
 
5780
}
-
 
5781
 
-
 
5782
void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
-
 
5783
{
-
 
5784
	/* disable DBUF power */
-
 
5785
	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
-
 
5786
	POSTING_READ(DBUF_CTL);
-
 
5787
 
-
 
5788
	udelay(10);
-
 
5789
 
-
 
5790
	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-
 
5791
		DRM_ERROR("DBuf power disable timeout\n");
-
 
5792
 
-
 
5793
	/*
-
 
5794
	 * DMC assumes ownership of LCPLL and will get confused if we touch it.
-
 
5795
	 */
-
 
5796
	if (dev_priv->csr.dmc_payload) {
-
 
5797
		/* disable DPLL0 */
-
 
5798
		I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
-
 
5799
					~LCPLL_PLL_ENABLE);
-
 
5800
		if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
-
 
5801
			DRM_ERROR("Couldn't disable DPLL0\n");
-
 
5802
	}
-
 
5803
 
-
 
5804
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
-
 
5805
}
-
 
5806
 
-
 
5807
void skl_init_cdclk(struct drm_i915_private *dev_priv)
-
 
5808
{
-
 
5809
	u32 val;
-
 
5810
	unsigned int required_vco;
-
 
5811
 
-
 
5812
	/* enable PCH reset handshake */
-
 
5813
	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-
 
5814
	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
-
 
5815
 
-
 
5816
	/* enable PG1 and Misc I/O */
4782
		CCK_FUSE_HPLL_FREQ_MASK;
5817
	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Line 4783... Line 5818...
4783
	mutex_unlock(&dev_priv->dpio_lock);
5818
 
4784
 
5819
	/* DPLL0 not enabled (happens on early BIOS versions) */
4785
	return vco_freq[hpll_freq] * 1000;
5820
	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
4786
}
5821
		/* enable DPLL0 */
4787
 
5822
		required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
Line 4788... Line 5823...
4788
static void vlv_update_cdclk(struct drm_device *dev)
5823
		skl_dpll0_enable(dev_priv, required_vco);
-
 
5824
	}
Line 4789... Line 5825...
4789
{
5825
 
4790
	struct drm_i915_private *dev_priv = dev->dev_private;
5826
	/* set CDCLK to the frequency the BIOS chose */
4791
 
5827
	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
4792
	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5828
 
Line 4826... Line 5862...
4826
		     50)) {
5862
		     50)) {
4827
		DRM_ERROR("timed out waiting for CDclk change\n");
5863
		DRM_ERROR("timed out waiting for CDclk change\n");
4828
	}
5864
	}
4829
	mutex_unlock(&dev_priv->rps.hw_lock);
5865
	mutex_unlock(&dev_priv->rps.hw_lock);
Line -... Line 5866...
-
 
5866
 
-
 
5867
	mutex_lock(&dev_priv->sb_lock);
4830
 
5868
 
4831
	if (cdclk == 400000) {
5869
	if (cdclk == 400000) {
Line 4832... Line 5870...
4832
		u32 divider;
5870
		u32 divider;
Line 4833... Line -...
4833
 
-
 
4834
		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5871
 
4835
 
5872
		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4836
		mutex_lock(&dev_priv->dpio_lock);
5873
 
4837
		/* adjust cdclk divider */
5874
		/* adjust cdclk divider */
4838
		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5875
		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Line 4839... Line 5876...
4839
		val &= ~DISPLAY_FREQUENCY_VALUES;
5876
		val &= ~CCK_FREQUENCY_VALUES;
4840
		val |= divider;
5877
		val |= divider;
4841
		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5878
		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4842
 
5879
 
4843
		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
-
 
4844
			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5880
		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
Line 4845... Line -...
4845
			     50))
-
 
4846
			DRM_ERROR("timed out waiting for CDclk change\n");
5881
			      CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
4847
		mutex_unlock(&dev_priv->dpio_lock);
5882
			     50))
4848
	}
5883
			DRM_ERROR("timed out waiting for CDclk change\n");
Line 4849... Line 5884...
4849
 
5884
	}
Line 4859... Line 5894...
4859
	if (cdclk == 400000)
5894
	if (cdclk == 400000)
4860
		val |= 4500 / 250; /* 4.5 usec */
5895
		val |= 4500 / 250; /* 4.5 usec */
4861
	else
5896
	else
4862
		val |= 3000 / 250; /* 3.0 usec */
5897
		val |= 3000 / 250; /* 3.0 usec */
4863
	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5898
	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4864
	mutex_unlock(&dev_priv->dpio_lock);
-
 
Line -... Line 5899...
-
 
5899
 
-
 
5900
	mutex_unlock(&dev_priv->sb_lock);
4865
 
5901
 
4866
	vlv_update_cdclk(dev);
5902
	intel_update_cdclk(dev);
Line 4867... Line 5903...
4867
}
5903
}
4868
 
5904
 
4869
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5905
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4870
{
5906
{
Line 4871... Line 5907...
4871
	struct drm_i915_private *dev_priv = dev->dev_private;
5907
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
5908
	u32 val, cmd;
Line 4872... Line 5909...
4872
	u32 val, cmd;
5909
 
4873
 
-
 
4874
	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
-
 
4875
 
-
 
4876
	switch (cdclk) {
5910
	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
4877
	case 400000:
5911
						!= dev_priv->cdclk_freq);
4878
		cmd = 3;
-
 
4879
		break;
-
 
4880
	case 333333:
5912
 
4881
	case 320000:
-
 
4882
		cmd = 2;
-
 
4883
		break;
5913
	switch (cdclk) {
4884
	case 266667:
-
 
4885
		cmd = 1;
5914
	case 333333:
4886
		break;
5915
	case 320000:
4887
	case 200000:
5916
	case 266667:
4888
		cmd = 0;
5917
	case 200000:
4889
		break;
5918
		break;
Line -... Line 5919...
-
 
5919
	default:
-
 
5920
		MISSING_CASE(cdclk);
-
 
5921
		return;
-
 
5922
	}
-
 
5923
 
-
 
5924
	/*
-
 
5925
	 * Specs are full of misinformation, but testing on actual
4890
	default:
5926
	 * hardware has shown that we just need to write the desired
4891
		WARN_ON(1);
5927
	 * CCK divider into the Punit register.
4892
		return;
5928
	 */
4893
	}
5929
	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4894
 
5930
 
Line 4902... Line 5938...
4902
		     50)) {
5938
		     50)) {
4903
		DRM_ERROR("timed out waiting for CDclk change\n");
5939
		DRM_ERROR("timed out waiting for CDclk change\n");
4904
	}
5940
	}
4905
	mutex_unlock(&dev_priv->rps.hw_lock);
5941
	mutex_unlock(&dev_priv->rps.hw_lock);
Line 4906... Line 5942...
4906
 
5942
 
4907
	vlv_update_cdclk(dev);
5943
	intel_update_cdclk(dev);
Line 4908... Line 5944...
4908
}
5944
}
4909
 
5945
 
4910
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5946
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4911
				 int max_pixclk)
5947
				 int max_pixclk)
4912
{
-
 
4913
	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
-
 
4914
 
5948
{
4915
	/* FIXME: Punit isn't quite ready yet */
-
 
Line 4916... Line 5949...
4916
	if (IS_CHERRYVIEW(dev_priv->dev))
5949
	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4917
		return 400000;
5950
	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
4918
 
5951
 
4919
	/*
5952
	/*
4920
	 * Really only a few cases to deal with, as only 4 CDclks are supported:
5953
	 * Really only a few cases to deal with, as only 4 CDclks are supported:
4921
	 *   200MHz
5954
	 *   200MHz
4922
	 *   267MHz
5955
	 *   267MHz
4923
	 *   320/333MHz (depends on HPLL freq)
5956
	 *   320/333MHz (depends on HPLL freq)
4924
	 *   400MHz
5957
	 *   400MHz (VLV only)
4925
	 * So we check to see whether we're above 90% of the lower bin and
5958
	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
4926
	 * adjust if needed.
5959
	 * of the lower bin and adjust if needed.
4927
	 *
5960
	 *
4928
	 * We seem to get an unstable or solid color picture at 200MHz.
5961
	 * We seem to get an unstable or solid color picture at 200MHz.
-
 
5962
	 * Not sure what's wrong. For now use 200MHz only when all pipes
4929
	 * Not sure what's wrong. For now use 200MHz only when all pipes
5963
	 * are off.
4930
	 * are off.
5964
	 */
4931
	 */
5965
	if (!IS_CHERRYVIEW(dev_priv) &&
4932
	if (max_pixclk > freq_320*9/10)
5966
	    max_pixclk > freq_320*limit/100)
4933
		return 400000;
5967
		return 400000;
4934
	else if (max_pixclk > 266667*9/10)
5968
	else if (max_pixclk > 266667*limit/100)
4935
		return freq_320;
5969
		return freq_320;
4936
	else if (max_pixclk > 0)
5970
	else if (max_pixclk > 0)
4937
		return 266667;
5971
		return 266667;
Line -... Line 5972...
-
 
5972
	else
-
 
5973
		return 200000;
-
 
5974
}
-
 
5975
 
-
 
5976
static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
-
 
5977
			      int max_pixclk)
-
 
5978
{
-
 
5979
	/*
-
 
5980
	 * FIXME:
-
 
5981
	 * - remove the guardband, it's not needed on BXT
-
 
5982
	 * - set 19.2MHz bypass frequency if there are no active pipes
-
 
5983
	 */
-
 
5984
	if (max_pixclk > 576000*9/10)
-
 
5985
		return 624000;
-
 
5986
	else if (max_pixclk > 384000*9/10)
-
 
5987
		return 576000;
-
 
5988
	else if (max_pixclk > 288000*9/10)
-
 
5989
		return 384000;
-
 
5990
	else if (max_pixclk > 144000*9/10)
-
 
5991
		return 288000;
4938
	else
5992
	else
-
 
5993
		return 144000;
4939
		return 200000;
5994
}
-
 
5995
 
4940
}
5996
/* Compute the max pixel clock for new configuration. Uses atomic state if
4941
 
-
 
4942
/* compute the max pixel clock for new configuration */
5997
 * that's non-NULL, look at current state otherwise. */
-
 
5998
static int intel_mode_max_pixclk(struct drm_device *dev,
4943
static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5999
				 struct drm_atomic_state *state)
Line 4944... Line 6000...
4944
{
6000
{
-
 
6001
	struct intel_crtc *intel_crtc;
-
 
6002
	struct intel_crtc_state *crtc_state;
-
 
6003
	int max_pixclk = 0;
-
 
6004
 
4945
	struct drm_device *dev = dev_priv->dev;
6005
	for_each_intel_crtc(dev, intel_crtc) {
-
 
6006
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-
 
6007
		if (IS_ERR(crtc_state))
4946
	struct intel_crtc *intel_crtc;
6008
			return PTR_ERR(crtc_state);
4947
	int max_pixclk = 0;
6009
 
4948
 
6010
		if (!crtc_state->base.enable)
Line 4949... Line 6011...
4949
	for_each_intel_crtc(dev, intel_crtc) {
6011
			continue;
4950
		if (intel_crtc->new_enabled)
6012
 
Line 4951... Line 6013...
4951
			max_pixclk = max(max_pixclk,
6013
		max_pixclk = max(max_pixclk,
4952
					 intel_crtc->new_config->adjusted_mode.crtc_clock);
-
 
4953
	}
6014
				 crtc_state->base.adjusted_mode.crtc_clock);
-
 
6015
	}
4954
 
6016
 
4955
	return max_pixclk;
-
 
4956
}
6017
	return max_pixclk;
Line 4957... Line -...
4957
 
-
 
4958
static void valleyview_modeset_global_pipes(struct drm_device *dev,
6018
}
4959
					    unsigned *prepare_pipes)
6019
 
-
 
6020
static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
-
 
6021
{
-
 
6022
	struct drm_device *dev = state->dev;
Line -... Line 6023...
-
 
6023
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
6024
	int max_pixclk = intel_mode_max_pixclk(dev, state);
-
 
6025
 
-
 
6026
	if (max_pixclk < 0)
-
 
6027
		return max_pixclk;
-
 
6028
 
-
 
6029
	to_intel_atomic_state(state)->cdclk =
-
 
6030
		valleyview_calc_cdclk(dev_priv, max_pixclk);
-
 
6031
 
-
 
6032
	return 0;
-
 
6033
}
-
 
6034
 
-
 
6035
static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
-
 
6036
{
-
 
6037
	struct drm_device *dev = state->dev;
-
 
6038
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
6039
	int max_pixclk = intel_mode_max_pixclk(dev, state);
-
 
6040
 
4960
{
6041
	if (max_pixclk < 0)
-
 
6042
		return max_pixclk;
4961
	struct drm_i915_private *dev_priv = dev->dev_private;
6043
 
-
 
6044
	to_intel_atomic_state(state)->cdclk =
-
 
6045
		broxton_calc_cdclk(dev_priv, max_pixclk);
-
 
6046
 
-
 
6047
	return 0;
-
 
6048
}
-
 
6049
 
-
 
6050
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
-
 
6051
{
4962
	struct intel_crtc *intel_crtc;
6052
	unsigned int credits, default_credits;
-
 
6053
 
-
 
6054
	if (IS_CHERRYVIEW(dev_priv))
-
 
6055
		default_credits = PFI_CREDIT(12);
-
 
6056
	else
4963
	int max_pixclk = intel_mode_max_pixclk(dev_priv);
6057
		default_credits = PFI_CREDIT(8);
-
 
6058
 
-
 
6059
	if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
-
 
6060
		/* CHV suggested value is 31 or 63 */
-
 
6061
		if (IS_CHERRYVIEW(dev_priv))
-
 
6062
			credits = PFI_CREDIT_63;
-
 
6063
		else
-
 
6064
			credits = PFI_CREDIT(15);
-
 
6065
	} else {
-
 
6066
		credits = default_credits;
-
 
6067
	}
-
 
6068
 
-
 
6069
	/*
-
 
6070
	 * WA - write default credits before re-programming
-
 
6071
	 * FIXME: should we also set the resend bit here?
-
 
6072
	 */
-
 
6073
	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
-
 
6074
		   default_credits);
4964
 
6075
 
Line 4965... Line 6076...
4965
	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
6076
	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
4966
	    dev_priv->vlv_cdclk_freq)
6077
		   credits | PFI_CREDIT_RESEND);
-
 
6078
 
-
 
6079
	/*
4967
		return;
6080
	 * FIXME is this guaranteed to clear
4968
 
-
 
4969
	/* disable/enable all currently active pipes while we change cdclk */
-
 
Line 4970... Line -...
4970
	for_each_intel_crtc(dev, intel_crtc)
-
 
4971
		if (intel_crtc->base.enabled)
6081
	 * immediately or should we poll for it?
4972
			*prepare_pipes |= (1 << intel_crtc->pipe);
6082
	 */
4973
}
6083
	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
4974
 
6084
}
4975
static void valleyview_modeset_global_resources(struct drm_device *dev)
6085
 
Line 4993... Line 6103...
4993
		if (IS_CHERRYVIEW(dev))
6103
	if (IS_CHERRYVIEW(dev))
4994
			cherryview_set_cdclk(dev, req_cdclk);
6104
		cherryview_set_cdclk(dev, req_cdclk);
4995
		else
6105
	else
4996
		valleyview_set_cdclk(dev, req_cdclk);
6106
		valleyview_set_cdclk(dev, req_cdclk);
Line -... Line 6107...
-
 
6107
 
-
 
6108
	vlv_program_pfi_credits(dev_priv);
4997
 
6109
 
4998
		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6110
	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4999
	}
-
 
Line 5000... Line 6111...
5000
}
6111
}
5001
 
6112
 
5002
static void valleyview_crtc_enable(struct drm_crtc *crtc)
6113
static void valleyview_crtc_enable(struct drm_crtc *crtc)
5003
{
6114
{
5004
	struct drm_device *dev = crtc->dev;
6115
	struct drm_device *dev = crtc->dev;
5005
	struct drm_i915_private *dev_priv = to_i915(dev);
6116
	struct drm_i915_private *dev_priv = to_i915(dev);
5006
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007
	struct intel_encoder *encoder;
6118
	struct intel_encoder *encoder;
Line 5008... Line -...
5008
	int pipe = intel_crtc->pipe;
-
 
5009
	bool is_dsi;
-
 
5010
 
6119
	int pipe = intel_crtc->pipe;
5011
	WARN_ON(!crtc->enabled);
6120
	bool is_dsi;
Line 5012... Line 6121...
5012
 
6121
 
Line 5013... Line -...
5013
	if (intel_crtc->active)
-
 
5014
		return;
-
 
5015
 
-
 
5016
	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
-
 
5017
 
-
 
5018
	if (!is_dsi) {
-
 
5019
		if (IS_CHERRYVIEW(dev))
-
 
5020
			chv_prepare_pll(intel_crtc, &intel_crtc->config);
6122
	if (WARN_ON(intel_crtc->active))
5021
		else
6123
		return;
Line 5022... Line 6124...
5022
			vlv_prepare_pll(intel_crtc, &intel_crtc->config);
6124
 
Line 5023... Line 6125...
5023
	}
6125
	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5024
 
6126
 
Line 5043... Line 6145...
5043
	for_each_encoder_on_crtc(dev, crtc, encoder)
6145
	for_each_encoder_on_crtc(dev, crtc, encoder)
5044
		if (encoder->pre_pll_enable)
6146
		if (encoder->pre_pll_enable)
5045
			encoder->pre_pll_enable(encoder);
6147
			encoder->pre_pll_enable(encoder);
Line 5046... Line 6148...
5046
 
6148
 
5047
	if (!is_dsi) {
6149
	if (!is_dsi) {
-
 
6150
		if (IS_CHERRYVIEW(dev)) {
5048
		if (IS_CHERRYVIEW(dev))
6151
			chv_prepare_pll(intel_crtc, intel_crtc->config);
5049
			chv_enable_pll(intel_crtc, &intel_crtc->config);
6152
			chv_enable_pll(intel_crtc, intel_crtc->config);
-
 
6153
		} else {
5050
		else
6154
			vlv_prepare_pll(intel_crtc, intel_crtc->config);
-
 
6155
			vlv_enable_pll(intel_crtc, intel_crtc->config);
5051
			vlv_enable_pll(intel_crtc, &intel_crtc->config);
6156
		}
Line 5052... Line 6157...
5052
	}
6157
	}
5053
 
6158
 
5054
	for_each_encoder_on_crtc(dev, crtc, encoder)
6159
	for_each_encoder_on_crtc(dev, crtc, encoder)
Line 5055... Line 6160...
5055
		if (encoder->pre_enable)
6160
		if (encoder->pre_enable)
Line 5056... Line 6161...
5056
			encoder->pre_enable(encoder);
6161
			encoder->pre_enable(encoder);
Line 5057... Line -...
5057
 
-
 
5058
	i9xx_pfit_enable(intel_crtc);
6162
 
Line 5059... Line -...
5059
 
-
 
5060
	intel_crtc_load_lut(crtc);
-
 
5061
 
-
 
5062
	intel_update_watermarks(crtc);
6163
	i9xx_pfit_enable(intel_crtc);
5063
	intel_enable_pipe(intel_crtc);
6164
 
Line 5064... Line 6165...
5064
 
6165
	intel_crtc_load_lut(crtc);
5065
	for_each_encoder_on_crtc(dev, crtc, encoder)
-
 
5066
		encoder->enable(encoder);
-
 
5067
 
6166
 
5068
	assert_vblank_disabled(crtc);
6167
	intel_enable_pipe(intel_crtc);
Line 5069... Line 6168...
5069
	drm_crtc_vblank_on(crtc);
6168
 
5070
 
6169
	assert_vblank_disabled(crtc);
5071
	intel_crtc_enable_planes(crtc);
6170
	drm_crtc_vblank_on(crtc);
5072
 
6171
 
Line 5073... Line 6172...
5073
	/* Underruns don't raise interrupts, so check manually. */
6172
	for_each_encoder_on_crtc(dev, crtc, encoder)
5074
	i9xx_check_fifo_underruns(dev_priv);
6173
		encoder->enable(encoder);
5075
}
6174
}
Line 5076... Line 6175...
5076
 
6175
 
5077
static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6176
static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5078
{
6177
{
5079
	struct drm_device *dev = crtc->base.dev;
6178
	struct drm_device *dev = crtc->base.dev;
5080
	struct drm_i915_private *dev_priv = dev->dev_private;
6179
	struct drm_i915_private *dev_priv = dev->dev_private;
5081
 
6180
 
5082
	I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
6181
	I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
Line 5083... Line -...
5083
	I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
-
 
5084
}
-
 
5085
 
6182
	I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5086
static void i9xx_crtc_enable(struct drm_crtc *crtc)
6183
}
Line 5087... Line 6184...
5087
{
6184
 
Line 5088... Line 6185...
5088
    struct drm_device *dev = crtc->dev;
6185
static void i9xx_crtc_enable(struct drm_crtc *crtc)
5089
	struct drm_i915_private *dev_priv = to_i915(dev);
6186
{
Line 5090... Line 6187...
5090
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187
	struct drm_device *dev = crtc->dev;
Line 5091... Line 6188...
5091
	struct intel_encoder *encoder;
6188
	struct drm_i915_private *dev_priv = to_i915(dev);
Line 5121... Line 6218...
5121
	intel_crtc_load_lut(crtc);
6218
	intel_crtc_load_lut(crtc);
Line 5122... Line 6219...
5122
 
6219
 
5123
	intel_update_watermarks(crtc);
6220
	intel_update_watermarks(crtc);
Line 5124... Line -...
5124
	intel_enable_pipe(intel_crtc);
-
 
5125
 
-
 
5126
	for_each_encoder_on_crtc(dev, crtc, encoder)
-
 
5127
		encoder->enable(encoder);
6221
	intel_enable_pipe(intel_crtc);
5128
 
6222
 
Line 5129... Line -...
5129
	assert_vblank_disabled(crtc);
-
 
5130
	drm_crtc_vblank_on(crtc);
-
 
5131
 
-
 
5132
	intel_crtc_enable_planes(crtc);
-
 
5133
 
-
 
5134
	/*
-
 
5135
	 * Gen2 reports pipe underruns whenever all planes are disabled.
-
 
5136
	 * So don't enable underrun reporting before at least some planes
-
 
5137
	 * are enabled.
-
 
5138
	 * FIXME: Need to fix the logic to work when we turn off all planes
-
 
5139
	 * but leave the pipe running.
6223
	assert_vblank_disabled(crtc);
5140
	 */
-
 
5141
	if (IS_GEN2(dev))
-
 
5142
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6224
	drm_crtc_vblank_on(crtc);
5143
 
6225
 
Line 5144... Line 6226...
5144
	/* Underruns don't raise interrupts, so check manually. */
6226
	for_each_encoder_on_crtc(dev, crtc, encoder)
5145
	i9xx_check_fifo_underruns(dev_priv);
6227
		encoder->enable(encoder);
5146
}
6228
}
5147
 
6229
 
Line 5148... Line 6230...
5148
static void i9xx_pfit_disable(struct intel_crtc *crtc)
6230
static void i9xx_pfit_disable(struct intel_crtc *crtc)
5149
{
6231
{
Line 5150... Line 6232...
5150
	struct drm_device *dev = crtc->base.dev;
6232
	struct drm_device *dev = crtc->base.dev;
Line 5151... Line 6233...
5151
	struct drm_i915_private *dev_priv = dev->dev_private;
6233
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 5166... Line 6248...
5166
    struct drm_i915_private *dev_priv = dev->dev_private;
6248
	struct drm_i915_private *dev_priv = dev->dev_private;
5167
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168
	struct intel_encoder *encoder;
6250
	struct intel_encoder *encoder;
5169
    int pipe = intel_crtc->pipe;
6251
	int pipe = intel_crtc->pipe;
Line 5170... Line -...
5170
 
-
 
5171
    if (!intel_crtc->active)
-
 
5172
        return;
-
 
5173
 
-
 
5174
	/*
-
 
5175
	 * Gen2 reports pipe underruns whenever all planes are disabled.
-
 
5176
	 * So diasble underrun reporting before all the planes get disabled.
-
 
5177
	 * FIXME: Need to fix the logic to work when we turn off all planes
-
 
5178
	 * but leave the pipe running.
-
 
5179
	 */
-
 
5180
	if (IS_GEN2(dev))
-
 
5181
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 
5182
 
-
 
5183
	/*
-
 
5184
	 * Vblank time updates from the shadow to live plane control register
-
 
5185
	 * are blocked if the memory self-refresh mode is active at that
-
 
5186
	 * moment. So to make sure the plane gets truly disabled, disable
-
 
5187
	 * first the self-refresh mode. The self-refresh enable bit in turn
-
 
5188
	 * will be checked/applied by the HW only at the next frame start
-
 
5189
	 * event which is after the vblank start event, so we need to have a
-
 
5190
	 * wait-for-vblank between disabling the plane and the pipe.
-
 
5191
	 */
-
 
5192
	intel_set_memory_cxsr(dev_priv, false);
-
 
5193
	intel_crtc_disable_planes(crtc);
-
 
5194
 
6252
 
5195
	/*
6253
	/*
5196
	 * On gen2 planes are double buffered but the pipe isn't, so we must
6254
	 * On gen2 planes are double buffered but the pipe isn't, so we must
5197
	 * wait for planes to fully turn off before disabling the pipe.
6255
	 * wait for planes to fully turn off before disabling the pipe.
5198
	 * We also need to wait on all gmch platforms because of the
6256
	 * We also need to wait on all gmch platforms because of the
5199
	 * self-refresh mode constraint explained above.
6257
	 * self-refresh mode constraint explained above.
5200
	 */
6258
	 */
Line 5201... Line -...
5201
		intel_wait_for_vblank(dev, pipe);
-
 
5202
 
-
 
5203
	drm_crtc_vblank_off(crtc);
-
 
5204
	assert_vblank_disabled(crtc);
6259
	intel_wait_for_vblank(dev, pipe);
5205
 
6260
 
Line -... Line 6261...
-
 
6261
	for_each_encoder_on_crtc(dev, crtc, encoder)
-
 
6262
		encoder->disable(encoder);
-
 
6263
 
5206
	for_each_encoder_on_crtc(dev, crtc, encoder)
6264
	drm_crtc_vblank_off(crtc);
Line 5207... Line 6265...
5207
		encoder->disable(encoder);
6265
	assert_vblank_disabled(crtc);
Line 5208... Line 6266...
5208
 
6266
 
Line 5221... Line 6279...
5221
		vlv_disable_pll(dev_priv, pipe);
6279
			vlv_disable_pll(dev_priv, pipe);
5222
		else
6280
		else
5223
			i9xx_disable_pll(intel_crtc);
6281
			i9xx_disable_pll(intel_crtc);
5224
	}
6282
	}
Line -... Line 6283...
-
 
6283
 
-
 
6284
	for_each_encoder_on_crtc(dev, crtc, encoder)
-
 
6285
		if (encoder->post_pll_disable)
-
 
6286
			encoder->post_pll_disable(encoder);
5225
 
6287
 
5226
	if (!IS_GEN2(dev))
6288
	if (!IS_GEN2(dev))
5227
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 
5228
 
-
 
5229
    intel_crtc->active = false;
-
 
5230
	intel_update_watermarks(crtc);
-
 
5231
 
-
 
5232
	mutex_lock(&dev->struct_mutex);
-
 
5233
    intel_update_fbc(dev);
-
 
5234
	mutex_unlock(&dev->struct_mutex);
-
 
5235
}
-
 
5236
 
-
 
5237
static void i9xx_crtc_off(struct drm_crtc *crtc)
-
 
5238
{
6289
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Line 5239... Line -...
5239
}
-
 
5240
 
6290
}
5241
/* Master function to enable/disable CRTC and corresponding power wells */
6291
 
5242
void intel_crtc_control(struct drm_crtc *crtc, bool enable)
-
 
5243
{
-
 
5244
	struct drm_device *dev = crtc->dev;
6292
static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
-
 
6293
{
5245
	struct drm_i915_private *dev_priv = dev->dev_private;
6294
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295
	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Line 5247... Line -...
5247
	enum intel_display_power_domain domain;
-
 
5248
	unsigned long domains;
6296
	enum intel_display_power_domain domain;
5249
 
6297
	unsigned long domains;
5250
	if (enable) {
-
 
5251
		if (!intel_crtc->active) {
-
 
5252
			domains = get_crtc_power_domains(crtc);
-
 
Line -... Line 6298...
-
 
6298
 
5253
			for_each_power_domain(domain, domains)
6299
	if (!intel_crtc->active)
-
 
6300
		return;
-
 
6301
 
-
 
6302
	if (to_intel_plane_state(crtc->primary->state)->visible) {
5254
				intel_display_power_get(dev_priv, domain);
6303
		intel_pre_disable_primary(crtc);
5255
			intel_crtc->enabled_power_domains = domains;
6304
 
5256
 
-
 
5257
			dev_priv->display.crtc_enable(crtc);
6305
		intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
-
 
6306
		to_intel_plane_state(crtc->primary->state)->visible = false;
-
 
6307
	}
-
 
6308
 
Line 5258... Line 6309...
5258
		}
6309
	dev_priv->display.crtc_disable(crtc);
5259
	} else {
6310
	intel_crtc->active = false;
5260
		if (intel_crtc->active) {
6311
	intel_update_watermarks(crtc);
5261
			dev_priv->display.crtc_disable(crtc);
6312
	intel_disable_shared_dpll(intel_crtc);
5262
 
6313
 
5263
			domains = intel_crtc->enabled_power_domains;
-
 
5264
			for_each_power_domain(domain, domains)
-
 
Line 5265... Line 6314...
5265
				intel_display_power_put(dev_priv, domain);
6314
	domains = intel_crtc->enabled_power_domains;
-
 
6315
	for_each_power_domain(domain, domains)
5266
			intel_crtc->enabled_power_domains = 0;
6316
		intel_display_power_put(dev_priv, domain);
5267
		}
6317
	intel_crtc->enabled_power_domains = 0;
5268
	}
6318
}
5269
}
6319
 
-
 
6320
/*
-
 
6321
 * turn all crtc's off, but do not adjust state
5270
 
6322
 * This has to be paired with a call to intel_modeset_setup_hw_state.
5271
/**
6323
 */
-
 
6324
int intel_display_suspend(struct drm_device *dev)
5272
 * Sets the power management mode of the pipe and plane.
6325
{
Line 5273... Line 6326...
5273
 */
6326
	struct drm_mode_config *config = &dev->mode_config;
5274
void intel_crtc_update_dpms(struct drm_crtc *crtc)
6327
	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
Line -... Line 6328...
-
 
6328
	struct drm_atomic_state *state;
5275
{
6329
	struct drm_crtc *crtc;
-
 
6330
	unsigned crtc_mask = 0;
5276
	struct drm_device *dev = crtc->dev;
6331
	int ret = 0;
Line 5277... Line -...
5277
	struct intel_encoder *intel_encoder;
-
 
5278
	bool enable = false;
-
 
5279
 
6332
 
5280
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6333
	if (WARN_ON(!ctx))
5281
		enable |= intel_encoder->connectors_active;
-
 
5282
 
-
 
5283
	intel_crtc_control(crtc, enable);
-
 
Line -... Line 6334...
-
 
6334
		return 0;
5284
}
6335
 
5285
 
6336
	lockdep_assert_held(&ctx->ww_ctx);
Line 5286... Line 6337...
5286
static void intel_crtc_disable(struct drm_crtc *crtc)
6337
	state = drm_atomic_state_alloc(dev);
-
 
6338
	if (WARN_ON(!state))
5287
{
6339
		return -ENOMEM;
Line 5288... Line 6340...
5288
	struct drm_device *dev = crtc->dev;
6340
 
5289
	struct drm_connector *connector;
6341
	state->acquire_ctx = ctx;
-
 
6342
	state->allow_modeset = true;
5290
	struct drm_i915_private *dev_priv = dev->dev_private;
6343
 
5291
	struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
-
 
5292
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-
 
5293
 
6344
	for_each_crtc(dev, crtc) {
5294
	/* crtc should still be enabled when we disable it. */
-
 
5295
	WARN_ON(!crtc->enabled);
6345
		struct drm_crtc_state *crtc_state =
Line 5296... Line 6346...
5296
 
6346
			drm_atomic_get_crtc_state(state, crtc);
5297
	dev_priv->display.crtc_disable(crtc);
-
 
5298
	dev_priv->display.off(crtc);
6347
 
5299
 
-
 
Line -... Line 6348...
-
 
6348
		ret = PTR_ERR_OR_ZERO(crtc_state);
-
 
6349
		if (ret)
5300
	if (crtc->primary->fb) {
6350
			goto free;
5301
		mutex_lock(&dev->struct_mutex);
6351
 
Line 5302... Line 6352...
5302
		intel_unpin_fb_obj(old_obj);
6352
		if (!crtc_state->active)
5303
		i915_gem_track_fb(old_obj, NULL,
-
 
-
 
6353
			continue;
5304
				  INTEL_FRONTBUFFER_PRIMARY(pipe));
6354
 
-
 
6355
		crtc_state->active = false;
-
 
6356
		crtc_mask |= 1 << drm_crtc_index(crtc);
-
 
6357
	}
-
 
6358
 
-
 
6359
	if (crtc_mask) {
-
 
6360
		ret = drm_atomic_commit(state);
5305
		mutex_unlock(&dev->struct_mutex);
6361
 
Line 5306... Line 6362...
5306
		crtc->primary->fb = NULL;
6362
		if (!ret) {
5307
	}
6363
			for_each_crtc(dev, crtc)
5308
 
6364
				if (crtc_mask & (1 << drm_crtc_index(crtc)))
Line 5309... Line 6365...
5309
	/* Update computed state. */
6365
					crtc->state->active = true;
5310
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6366
 
5311
		if (!connector->encoder || !connector->encoder->crtc)
6367
			return ret;
Line 5312... Line -...
5312
			continue;
-
 
5313
 
-
 
5314
		if (connector->encoder->crtc != crtc)
-
 
5315
			continue;
-
 
5316
 
-
 
5317
		connector->dpms = DRM_MODE_DPMS_OFF;
-
 
5318
		to_intel_encoder(connector->encoder)->connectors_active = false;
-
 
5319
	}
-
 
5320
}
-
 
5321
 
-
 
5322
void intel_encoder_destroy(struct drm_encoder *encoder)
-
 
5323
{
-
 
5324
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
-
 
5325
 
-
 
5326
	drm_encoder_cleanup(encoder);
-
 
5327
	kfree(intel_encoder);
-
 
5328
}
6368
		}
5329
 
6369
	}
5330
/* Simple dpms helper for encoders with just one connector, no cloning and only
6370
 
5331
 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6371
free:
5332
 * state of the entire output pipe. */
-
 
5333
static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6372
	if (ret)
5334
{
-
 
5335
	if (mode == DRM_MODE_DPMS_ON) {
-
 
5336
		encoder->connectors_active = true;
-
 
Line 5337... Line 6373...
5337
 
6373
		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5338
		intel_crtc_update_dpms(encoder->base.crtc);
6374
	drm_atomic_state_free(state);
5339
	} else {
6375
	return ret;
Line 5340... Line 6376...
5340
		encoder->connectors_active = false;
6376
}
5341
 
6377
 
5342
		intel_crtc_update_dpms(encoder->base.crtc);
6378
void intel_encoder_destroy(struct drm_encoder *encoder)
Line 5343... Line -...
5343
	}
-
 
5344
}
6379
{
5345
 
-
 
5346
/* Cross check the actual hw state with our own modeset state tracking (and it's
6380
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Line 5347... Line 6381...
5347
 * internal consistency). */
6381
 
-
 
6382
	drm_encoder_cleanup(encoder);
-
 
6383
	kfree(intel_encoder);
5348
static void intel_connector_check_state(struct intel_connector *connector)
6384
}
5349
{
6385
 
Line 5350... Line 6386...
5350
	if (connector->get_hw_state(connector)) {
6386
/* Cross check the actual hw state with our own modeset state tracking (and it's
5351
		struct intel_encoder *encoder = connector->encoder;
-
 
5352
		struct drm_crtc *crtc;
-
 
5353
		bool encoder_enabled;
6387
 * internal consistency). */
Line -... Line 6388...
-
 
6388
static void intel_connector_check_state(struct intel_connector *connector)
5354
		enum pipe pipe;
6389
{
Line -... Line 6390...
-
 
6390
	struct drm_crtc *crtc = connector->base.state->crtc;
5355
 
6391
 
-
 
6392
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
-
 
6393
		      connector->base.base.id,
5356
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6394
		      connector->base.name);
5357
			      connector->base.base.id,
6395
 
5358
			      connector->base.name);
6396
	if (connector->get_hw_state(connector)) {
5359
 
-
 
5360
		/* there is no real hw state for MST connectors */
6397
		struct intel_encoder *encoder = connector->encoder;
5361
		if (connector->mst_port)
6398
		struct drm_connector_state *conn_state = connector->base.state;
Line 5362... Line -...
5362
			return;
-
 
5363
 
-
 
5364
		WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6399
 
5365
		     "wrong connector dpms state\n");
6400
		I915_STATE_WARN(!crtc,
5366
		WARN(connector->base.encoder != &encoder->base,
6401
			 "connector enabled without attached crtc\n");
5367
		     "active connector not linked to encoder\n");
-
 
5368
 
-
 
Line -... Line 6402...
-
 
6402
 
5369
		if (encoder) {
6403
		if (!crtc)
5370
		WARN(!encoder->connectors_active,
6404
			return;
Line 5371... Line 6405...
5371
		     "encoder->connectors_active not set\n");
6405
 
-
 
6406
		I915_STATE_WARN(!crtc->state->active,
-
 
6407
		      "connector is active, but attached crtc isn't\n");
-
 
6408
 
-
 
6409
		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
-
 
6410
			return;
-
 
6411
 
Line 5372... Line 6412...
5372
 
6412
		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5373
		encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6413
			"atomic encoder doesn't match attached encoder\n");
5374
		WARN(!encoder_enabled, "encoder not enabled\n");
6414
 
Line 5375... Line 6415...
5375
		if (WARN_ON(!encoder->base.crtc))
6415
		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
-
 
6416
			"attached encoder crtc differs from connector crtc\n");
-
 
6417
	} else {
-
 
6418
		I915_STATE_WARN(crtc && crtc->state->active,
-
 
6419
			"attached crtc is active, but connector isn't\n");
-
 
6420
		I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5376
			return;
6421
			"best encoder set without crtc!\n");
Line 5377... Line 6422...
5377
 
6422
	}
5378
		crtc = encoder->base.crtc;
6423
}
5379
 
6424
 
Line 5414... Line 6459...
5414
	struct intel_encoder *encoder = connector->encoder;
6459
	struct intel_encoder *encoder = connector->encoder;
Line 5415... Line 6460...
5415
 
6460
 
5416
	return encoder->get_hw_state(encoder, &pipe);
6461
	return encoder->get_hw_state(encoder, &pipe);
Line 5417... Line 6462...
5417
}
6462
}
5418
 
-
 
5419
static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6463
 
-
 
6464
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
-
 
6465
{
-
 
6466
	if (crtc_state->base.enable && crtc_state->has_pch_encoder)
-
 
6467
		return crtc_state->fdi_lanes;
-
 
6468
 
-
 
6469
	return 0;
-
 
6470
}
-
 
6471
 
-
 
6472
static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5420
				     struct intel_crtc_config *pipe_config)
6473
				     struct intel_crtc_state *pipe_config)
5421
{
6474
{
5422
	struct drm_i915_private *dev_priv = dev->dev_private;
6475
	struct drm_atomic_state *state = pipe_config->base.state;
Line 5423... Line 6476...
5423
	struct intel_crtc *pipe_B_crtc =
6476
	struct intel_crtc *other_crtc;
5424
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
6477
	struct intel_crtc_state *other_crtc_state;
5425
 
6478
 
5426
	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479
	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5427
		      pipe_name(pipe), pipe_config->fdi_lanes);
6480
		      pipe_name(pipe), pipe_config->fdi_lanes);
5428
	if (pipe_config->fdi_lanes > 4) {
6481
	if (pipe_config->fdi_lanes > 4) {
5429
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
Line 5430... Line 6483...
5430
			      pipe_name(pipe), pipe_config->fdi_lanes);
6483
			      pipe_name(pipe), pipe_config->fdi_lanes);
5431
		return false;
6484
		return -EINVAL;
5432
	}
6485
	}
5433
 
6486
 
5434
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6487
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5435
		if (pipe_config->fdi_lanes > 2) {
6488
		if (pipe_config->fdi_lanes > 2) {
5436
			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489
			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5437
				      pipe_config->fdi_lanes);
6490
				      pipe_config->fdi_lanes);
5438
			return false;
6491
			return -EINVAL;
Line 5439... Line 6492...
5439
		} else {
6492
		} else {
5440
			return true;
6493
			return 0;
Line 5441... Line 6494...
5441
		}
6494
		}
5442
	}
6495
	}
5443
 
6496
 
5444
	if (INTEL_INFO(dev)->num_pipes == 2)
6497
	if (INTEL_INFO(dev)->num_pipes == 2)
5445
		return true;
6498
		return 0;
-
 
6499
 
-
 
6500
	/* Ivybridge 3 pipe is really complicated */
-
 
6501
	switch (pipe) {
-
 
6502
	case PIPE_A:
-
 
6503
		return 0;
5446
 
6504
	case PIPE_B:
-
 
6505
		if (pipe_config->fdi_lanes <= 2)
-
 
6506
			return 0;
-
 
6507
 
5447
	/* Ivybridge 3 pipe is really complicated */
6508
		other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5448
	switch (pipe) {
6509
		other_crtc_state =
5449
	case PIPE_A:
6510
			intel_atomic_get_crtc_state(state, other_crtc);
5450
		return true;
6511
		if (IS_ERR(other_crtc_state))
5451
	case PIPE_B:
6512
			return PTR_ERR(other_crtc_state);
5452
		if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
6513
 
5453
		    pipe_config->fdi_lanes > 2) {
6514
		if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
5454
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
-
 
5455
				      pipe_name(pipe), pipe_config->fdi_lanes);
-
 
5456
			return false;
6515
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5457
		}
6516
				      pipe_name(pipe), pipe_config->fdi_lanes);
5458
		return true;
6517
			return -EINVAL;
5459
	case PIPE_C:
6518
		}
5460
		if (!pipe_has_enabled_pch(pipe_B_crtc) ||
6519
		return 0;
-
 
6520
	case PIPE_C:
-
 
6521
		if (pipe_config->fdi_lanes > 2) {
5461
		    pipe_B_crtc->config.fdi_lanes <= 2) {
6522
			DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
-
 
6523
				      pipe_name(pipe), pipe_config->fdi_lanes);
-
 
6524
			return -EINVAL;
-
 
6525
		}
-
 
6526
 
-
 
6527
		other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5462
			if (pipe_config->fdi_lanes > 2) {
6528
		other_crtc_state =
5463
				DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6529
			intel_atomic_get_crtc_state(state, other_crtc);
5464
					      pipe_name(pipe), pipe_config->fdi_lanes);
6530
		if (IS_ERR(other_crtc_state))
5465
				return false;
6531
			return PTR_ERR(other_crtc_state);
5466
			}
6532
 
5467
		} else {
6533
		if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
5468
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6534
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5469
			return false;
6535
			return -EINVAL;
Line 5470... Line 6536...
5470
		}
6536
		}
5471
		return true;
6537
		return 0;
5472
	default:
6538
	default:
5473
		BUG();
6539
		BUG();
5474
	}
6540
	}
5475
}
6541
}
5476
 
6542
 
5477
#define RETRY 1
6543
#define RETRY 1
Line 5478... Line 6544...
5478
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6544
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5479
				      struct intel_crtc_config *pipe_config)
6545
				       struct intel_crtc_state *pipe_config)
5480
{
6546
{
5481
	struct drm_device *dev = intel_crtc->base.dev;
6547
	struct drm_device *dev = intel_crtc->base.dev;
Line 5501... Line 6567...
5501
	pipe_config->fdi_lanes = lane;
6567
	pipe_config->fdi_lanes = lane;
Line 5502... Line 6568...
5502
 
6568
 
5503
	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6569
	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Line 5504... Line 6570...
5504
			       link_bw, &pipe_config->fdi_m_n);
6570
			       link_bw, &pipe_config->fdi_m_n);
5505
 
6571
 
5506
	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572
	ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5507
					    intel_crtc->pipe, pipe_config);
6573
				       intel_crtc->pipe, pipe_config);
5508
	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
6574
	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
5509
		pipe_config->pipe_bpp -= 2*3;
6575
		pipe_config->pipe_bpp -= 2*3;
5510
		DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576
		DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5511
			      pipe_config->pipe_bpp);
6577
			      pipe_config->pipe_bpp);
Line 5516... Line 6582...
5516
	}
6582
	}
Line 5517... Line 6583...
5517
 
6583
 
5518
	if (needs_recompute)
6584
	if (needs_recompute)
Line -... Line 6585...
-
 
6585
		return RETRY;
-
 
6586
 
-
 
6587
	return ret;
-
 
6588
}
-
 
6589
 
-
 
6590
static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
-
 
6591
				     struct intel_crtc_state *pipe_config)
-
 
6592
{
-
 
6593
	if (pipe_config->pipe_bpp > 24)
-
 
6594
		return false;
-
 
6595
 
-
 
6596
	/* HSW can handle pixel rate up to cdclk? */
-
 
6597
	if (IS_HASWELL(dev_priv->dev))
-
 
6598
		return true;
-
 
6599
 
-
 
6600
	/*
-
 
6601
	 * We compare against max which means we must take
-
 
6602
	 * the increased cdclk requirement into account when
-
 
6603
	 * calculating the new cdclk.
-
 
6604
	 *
-
 
6605
	 * Should measure whether using a lower cdclk w/o IPS
5519
		return RETRY;
6606
	 */
5520
 
6607
	return ilk_pipe_pixel_rate(pipe_config) <=
Line 5521... Line 6608...
5521
	return setup_ok ? 0 : -EINVAL;
6608
		dev_priv->max_cdclk_freq * 95 / 100;
5522
}
6609
}
5523
 
6610
 
-
 
6611
static void hsw_compute_ips_config(struct intel_crtc *crtc,
-
 
6612
				   struct intel_crtc_state *pipe_config)
-
 
6613
{
5524
static void hsw_compute_ips_config(struct intel_crtc *crtc,
6614
	struct drm_device *dev = crtc->base.dev;
5525
				   struct intel_crtc_config *pipe_config)
6615
	struct drm_i915_private *dev_priv = dev->dev_private;
5526
{
6616
 
5527
	pipe_config->ips_enabled = i915.enable_ips &&
6617
	pipe_config->ips_enabled = i915.enable_ips &&
Line 5528... Line 6618...
5528
				   hsw_crtc_supports_ips(crtc) &&
6618
		hsw_crtc_supports_ips(crtc) &&
5529
				   pipe_config->pipe_bpp <= 24;
6619
		pipe_config_supports_ips(dev_priv, pipe_config);
5530
}
6620
}
5531
 
6621
 
5532
static int intel_crtc_compute_config(struct intel_crtc *crtc,
6622
static int intel_crtc_compute_config(struct intel_crtc *crtc,
5533
				     struct intel_crtc_config *pipe_config)
6623
				     struct intel_crtc_state *pipe_config)
Line 5534... Line 6624...
5534
{
6624
{
5535
	struct drm_device *dev = crtc->base.dev;
6625
	struct drm_device *dev = crtc->base.dev;
5536
	struct drm_i915_private *dev_priv = dev->dev_private;
6626
	struct drm_i915_private *dev_priv = dev->dev_private;
5537
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-
 
Line 5538... Line 6627...
5538
 
6627
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5539
	/* FIXME should check pixel clock limits on all platforms */
6628
 
5540
	if (INTEL_INFO(dev)->gen < 4) {
6629
	/* FIXME should check pixel clock limits on all platforms */
5541
		int clock_limit =
6630
	if (INTEL_INFO(dev)->gen < 4) {
Line 5562... Line 6651...
5562
	 * Pipe horizontal size must be even in:
6651
	 * Pipe horizontal size must be even in:
5563
	 * - DVO ganged mode
6652
	 * - DVO ganged mode
5564
	 * - LVDS dual channel mode
6653
	 * - LVDS dual channel mode
5565
	 * - Double wide pipe
6654
	 * - Double wide pipe
5566
	 */
6655
	 */
5567
	if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6656
	if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
5568
	     intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6657
	     intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5569
		pipe_config->pipe_src_w &= ~1;
6658
		pipe_config->pipe_src_w &= ~1;
Line 5570... Line 6659...
5570
 
6659
 
5571
	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
6660
	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
5572
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6661
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5573
	 */
6662
	 */
5574
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6663
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5575
		adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6664
		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
Line 5576... Line -...
5576
		return -EINVAL;
-
 
5577
 
-
 
5578
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
-
 
5579
		pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
-
 
5580
	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
-
 
5581
		/* only a 8bpc pipe, with 6bpc dither through the panel fitter
-
 
5582
		 * for lvds. */
-
 
5583
		pipe_config->pipe_bpp = 8*3;
-
 
5584
	}
6665
		return -EINVAL;
5585
 
6666
 
Line 5586... Line 6667...
5586
	if (HAS_IPS(dev))
6667
	if (HAS_IPS(dev))
5587
		hsw_compute_ips_config(crtc, pipe_config);
6668
		hsw_compute_ips_config(crtc, pipe_config);
Line 5588... Line 6669...
5588
 
6669
 
5589
	if (pipe_config->has_pch_encoder)
6670
	if (pipe_config->has_pch_encoder)
Line 5590... Line 6671...
5590
		return ironlake_fdi_compute_config(crtc, pipe_config);
6671
		return ironlake_fdi_compute_config(crtc, pipe_config);
5591
 
6672
 
5592
	return 0;
6673
	return 0;
-
 
6674
}
-
 
6675
 
-
 
6676
static int skylake_get_display_clock_speed(struct drm_device *dev)
-
 
6677
{
-
 
6678
	struct drm_i915_private *dev_priv = to_i915(dev);
-
 
6679
	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
-
 
6680
	uint32_t cdctl = I915_READ(CDCLK_CTL);
-
 
6681
	uint32_t linkrate;
-
 
6682
 
-
 
6683
	if (!(lcpll1 & LCPLL_PLL_ENABLE))
-
 
6684
		return 24000; /* 24MHz is the cd freq with NSSC ref */
-
 
6685
 
-
 
6686
	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
-
 
6687
		return 540000;
-
 
6688
 
-
 
6689
	linkrate = (I915_READ(DPLL_CTRL1) &
-
 
6690
		    DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
-
 
6691
 
-
 
6692
	if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
-
 
6693
	    linkrate == DPLL_CTRL1_LINK_RATE_1080) {
-
 
6694
		/* vco 8640 */
-
 
6695
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
-
 
6696
		case CDCLK_FREQ_450_432:
5593
}
6697
			return 432000;
-
 
6698
		case CDCLK_FREQ_337_308:
-
 
6699
			return 308570;
5594
 
6700
		case CDCLK_FREQ_675_617:
-
 
6701
			return 617140;
-
 
6702
		default:
-
 
6703
			WARN(1, "Unknown cd freq selection\n");
-
 
6704
		}
-
 
6705
	} else {
-
 
6706
		/* vco 8100 */
-
 
6707
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
-
 
6708
		case CDCLK_FREQ_450_432:
-
 
6709
			return 450000;
-
 
6710
		case CDCLK_FREQ_337_308:
-
 
6711
			return 337500;
-
 
6712
		case CDCLK_FREQ_675_617:
Line 5595... Line 6713...
5595
static int valleyview_get_display_clock_speed(struct drm_device *dev)
6713
			return 675000;
5596
{
-
 
5597
	struct drm_i915_private *dev_priv = dev->dev_private;
6714
		default:
-
 
6715
			WARN(1, "Unknown cd freq selection\n");
Line -... Line 6716...
-
 
6716
		}
-
 
6717
	}
5598
	u32 val;
6718
 
-
 
6719
	/* error case, do as if DPLL0 isn't enabled */
-
 
6720
	return 24000;
5599
	int divider;
6721
}
-
 
6722
 
Line 5600... Line -...
5600
 
-
 
5601
	/* FIXME: Punit isn't quite ready yet */
6723
static int broxton_get_display_clock_speed(struct drm_device *dev)
5602
	if (IS_CHERRYVIEW(dev))
6724
{
Line 5603... Line 6725...
5603
		return 400000;
6725
	struct drm_i915_private *dev_priv = to_i915(dev);
Line 5604... Line 6726...
5604
 
6726
	uint32_t cdctl = I915_READ(CDCLK_CTL);
-
 
6727
	uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
-
 
6728
	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
5605
	if (dev_priv->hpll_freq == 0)
6729
	int cdclk;
5606
		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6730
 
-
 
6731
	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
-
 
6732
		return 19200;
-
 
6733
 
-
 
6734
	cdclk = 19200 * pll_ratio / 2;
-
 
6735
 
Line -... Line 6736...
-
 
6736
	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
-
 
6737
	case BXT_CDCLK_CD2X_DIV_SEL_1:
-
 
6738
		return cdclk;  /* 576MHz or 624MHz */
-
 
6739
	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
-
 
6740
		return cdclk * 2 / 3; /* 384MHz */
-
 
6741
	case BXT_CDCLK_CD2X_DIV_SEL_2:
5607
 
6742
		return cdclk / 2; /* 288MHz */
-
 
6743
	case BXT_CDCLK_CD2X_DIV_SEL_4:
-
 
6744
		return cdclk / 4; /* 144MHz */
-
 
6745
	}
-
 
6746
 
-
 
6747
	/* error case, do as if DE PLL isn't enabled */
-
 
6748
	return 19200;
-
 
6749
}
-
 
6750
 
-
 
6751
static int broadwell_get_display_clock_speed(struct drm_device *dev)
-
 
6752
{
-
 
6753
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
6754
	uint32_t lcpll = I915_READ(LCPLL_CTL);
-
 
6755
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
-
 
6756
 
-
 
6757
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
-
 
6758
		return 800000;
-
 
6759
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-
 
6760
		return 450000;
-
 
6761
	else if (freq == LCPLL_CLK_FREQ_450)
-
 
6762
		return 450000;
-
 
6763
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
-
 
6764
		return 540000;
-
 
6765
	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
-
 
6766
		return 337500;
-
 
6767
	else
-
 
6768
		return 675000;
-
 
6769
}
-
 
6770
 
-
 
6771
static int haswell_get_display_clock_speed(struct drm_device *dev)
-
 
6772
{
-
 
6773
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
6774
	uint32_t lcpll = I915_READ(LCPLL_CTL);
-
 
6775
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
-
 
6776
 
-
 
6777
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
-
 
6778
		return 800000;
-
 
6779
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-
 
6780
		return 450000;
-
 
6781
	else if (freq == LCPLL_CLK_FREQ_450)
-
 
6782
		return 450000;
-
 
6783
	else if (IS_HSW_ULT(dev))
-
 
6784
		return 337500;
-
 
6785
	else
-
 
6786
		return 540000;
5608
	mutex_lock(&dev_priv->dpio_lock);
6787
}
Line 5609... Line 6788...
5609
	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6788
 
5610
	mutex_unlock(&dev_priv->dpio_lock);
6789
static int valleyview_get_display_clock_speed(struct drm_device *dev)
5611
 
6790
{
5612
	divider = val & DISPLAY_FREQUENCY_VALUES;
6791
	return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
Line 5613... Line 6792...
5613
 
6792
				      CCK_DISPLAY_CLOCK_CONTROL);
5614
	WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6793
}
5615
	     (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6794
 
5616
	     "cdclk change in progress\n");
6795
static int ilk_get_display_clock_speed(struct drm_device *dev)
Line 5617... Line 6796...
5617
 
6796
{
5618
	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6797
	return 450000;
5619
}
6798
}
Line 5639... Line 6818...
5639
 
6818
 
Line 5640... Line 6819...
5640
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6819
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5641
 
6820
 
5642
	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6821
	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5643
	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6822
	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5644
		return 267000;
6823
		return 266667;
5645
	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6824
	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5646
		return 333000;
6825
		return 333333;
5647
	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6826
	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5648
		return 444000;
6827
		return 444444;
5649
	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6828
	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5650
		return 200000;
6829
		return 200000;
5651
	default:
6830
	default:
5652
		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6831
		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5653
	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6832
	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5654
		return 133000;
6833
		return 133333;
5655
	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6834
	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5656
		return 167000;
6835
		return 166667;
Line 5657... Line 6836...
5657
	}
6836
	}
5658
}
6837
}
5659
 
6838
 
Line 5660... Line 6839...
5660
static int i915gm_get_display_clock_speed(struct drm_device *dev)
6839
static int i915gm_get_display_clock_speed(struct drm_device *dev)
Line 5661... Line 6840...
5661
{
6840
{
5662
	u16 gcfgc = 0;
6841
	u16 gcfgc = 0;
5663
 
6842
 
5664
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6843
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5665
 
6844
 
5666
	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6845
	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5667
		return 133000;
6846
		return 133333;
5668
	else {
6847
	else {
5669
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6848
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5670
		case GC_DISPLAY_CLOCK_333_MHZ:
6849
		case GC_DISPLAY_CLOCK_333_MHZ:
5671
			return 333000;
6850
			return 333333;
5672
		default:
6851
		default:
Line 5673... Line 6852...
5673
		case GC_DISPLAY_CLOCK_190_200_MHZ:
6852
		case GC_DISPLAY_CLOCK_190_200_MHZ:
5674
			return 190000;
6853
			return 190000;
5675
		}
6854
		}
5676
	}
6855
	}
Line 5677... Line 6856...
5677
}
6856
}
5678
 
6857
 
5679
static int i865_get_display_clock_speed(struct drm_device *dev)
6858
static int i865_get_display_clock_speed(struct drm_device *dev)
-
 
6859
{
-
 
6860
	return 266667;
-
 
6861
}
-
 
6862
 
-
 
6863
static int i85x_get_display_clock_speed(struct drm_device *dev)
-
 
6864
{
-
 
6865
	u16 hpllcc = 0;
-
 
6866
 
-
 
6867
	/*
-
 
6868
	 * 852GM/852GMV only supports 133 MHz and the HPLLCC
-
 
6869
	 * encoding is different :(
-
 
6870
	 * FIXME is this the right way to detect 852GM/852GMV?
5680
{
6871
	 */
5681
	return 266000;
6872
	if (dev->pdev->revision == 0x1)
5682
}
6873
		return 133333;
5683
 
6874
 
5684
static int i855_get_display_clock_speed(struct drm_device *dev)
6875
//   pci_bus_read_config_word(dev->pdev->bus,
-
 
6876
//                PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
5685
{
6877
 
5686
	u16 hpllcc = 0;
6878
	/* Assume that the hardware is in the high speed state.  This
5687
	/* Assume that the hardware is in the high speed state.  This
6879
	 * should be the default.
5688
	 * should be the default.
6880
	 */
5689
	 */
6881
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5690
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6882
	case GC_CLOCK_133_200:
-
 
6883
	case GC_CLOCK_133_200_2:
-
 
6884
	case GC_CLOCK_100_200:
-
 
6885
		return 200000;
-
 
6886
	case GC_CLOCK_166_250:
5691
	case GC_CLOCK_133_200:
6887
		return 250000;
Line 5692... Line 6888...
5692
	case GC_CLOCK_100_200:
6888
	case GC_CLOCK_100_133:
5693
		return 200000;
6889
		return 133333;
5694
	case GC_CLOCK_166_250:
6890
	case GC_CLOCK_133_266:
Line 5695... Line 6891...
5695
		return 250000;
6891
	case GC_CLOCK_133_266_2:
5696
	case GC_CLOCK_100_133:
6892
	case GC_CLOCK_166_266:
-
 
6893
		return 266667;
-
 
6894
	}
-
 
6895
 
-
 
6896
	/* Shouldn't happen */
-
 
6897
	return 0;
-
 
6898
}
-
 
6899
 
-
 
6900
static int i830_get_display_clock_speed(struct drm_device *dev)
-
 
6901
{
-
 
6902
	return 133333;
-
 
6903
}
-
 
6904
 
-
 
6905
static unsigned int intel_hpll_vco(struct drm_device *dev)
-
 
6906
{
-
 
6907
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
6908
	static const unsigned int blb_vco[8] = {
-
 
6909
		[0] = 3200000,
-
 
6910
		[1] = 4000000,
-
 
6911
		[2] = 5333333,
-
 
6912
		[3] = 4800000,
-
 
6913
		[4] = 6400000,
-
 
6914
	};
-
 
6915
	static const unsigned int pnv_vco[8] = {
-
 
6916
		[0] = 3200000,
-
 
6917
		[1] = 4000000,
-
 
6918
		[2] = 5333333,
-
 
6919
		[3] = 4800000,
-
 
6920
		[4] = 2666667,
-
 
6921
	};
-
 
6922
	static const unsigned int cl_vco[8] = {
-
 
6923
		[0] = 3200000,
-
 
6924
		[1] = 4000000,
-
 
6925
		[2] = 5333333,
-
 
6926
		[3] = 6400000,
-
 
6927
		[4] = 3333333,
-
 
6928
		[5] = 3566667,
-
 
6929
		[6] = 4266667,
-
 
6930
	};
-
 
6931
	static const unsigned int elk_vco[8] = {
-
 
6932
		[0] = 3200000,
-
 
6933
		[1] = 4000000,
-
 
6934
		[2] = 5333333,
-
 
6935
		[3] = 4800000,
-
 
6936
	};
-
 
6937
	static const unsigned int ctg_vco[8] = {
-
 
6938
		[0] = 3200000,
-
 
6939
		[1] = 4000000,
-
 
6940
		[2] = 5333333,
-
 
6941
		[3] = 6400000,
-
 
6942
		[4] = 2666667,
-
 
6943
		[5] = 4266667,
-
 
6944
	};
-
 
6945
	const unsigned int *vco_table;
-
 
6946
	unsigned int vco;
-
 
6947
	uint8_t tmp = 0;
-
 
6948
 
-
 
6949
	/* FIXME other chipsets? */
-
 
6950
	if (IS_GM45(dev))
-
 
6951
		vco_table = ctg_vco;
-
 
6952
	else if (IS_G4X(dev))
-
 
6953
		vco_table = elk_vco;
-
 
6954
	else if (IS_CRESTLINE(dev))
-
 
6955
		vco_table = cl_vco;
-
 
6956
	else if (IS_PINEVIEW(dev))
-
 
6957
		vco_table = pnv_vco;
-
 
6958
	else if (IS_G33(dev))
-
 
6959
		vco_table = blb_vco;
-
 
6960
	else
-
 
6961
		return 0;
-
 
6962
 
-
 
6963
	tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
-
 
6964
 
-
 
6965
	vco = vco_table[tmp & 0x7];
-
 
6966
	if (vco == 0)
-
 
6967
		DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
-
 
6968
	else
-
 
6969
		DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
-
 
6970
 
-
 
6971
	return vco;
-
 
6972
}
-
 
6973
 
-
 
6974
static int gm45_get_display_clock_speed(struct drm_device *dev)
-
 
6975
{
-
 
6976
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
-
 
6977
	uint16_t tmp = 0;
-
 
6978
 
-
 
6979
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
-
 
6980
 
-
 
6981
	cdclk_sel = (tmp >> 12) & 0x1;
-
 
6982
 
-
 
6983
	switch (vco) {
-
 
6984
	case 2666667:
-
 
6985
	case 4000000:
-
 
6986
	case 5333333:
-
 
6987
		return cdclk_sel ? 333333 : 222222;
-
 
6988
	case 3200000:
-
 
6989
		return cdclk_sel ? 320000 : 228571;
-
 
6990
	default:
-
 
6991
		DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
-
 
6992
		return 222222;
-
 
6993
	}
-
 
6994
}
-
 
6995
 
-
 
6996
static int i965gm_get_display_clock_speed(struct drm_device *dev)
-
 
6997
{
-
 
6998
	static const uint8_t div_3200[] = { 16, 10,  8 };
-
 
6999
	static const uint8_t div_4000[] = { 20, 12, 10 };
-
 
7000
	static const uint8_t div_5333[] = { 24, 16, 14 };
-
 
7001
	const uint8_t *div_table;
-
 
7002
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
-
 
7003
	uint16_t tmp = 0;
-
 
7004
 
-
 
7005
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
-
 
7006
 
-
 
7007
	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
-
 
7008
 
-
 
7009
	if (cdclk_sel >= ARRAY_SIZE(div_3200))
-
 
7010
		goto fail;
-
 
7011
 
-
 
7012
	switch (vco) {
-
 
7013
	case 3200000:
-
 
7014
		div_table = div_3200;
-
 
7015
		break;
-
 
7016
	case 4000000:
-
 
7017
		div_table = div_4000;
-
 
7018
		break;
-
 
7019
	case 5333333:
-
 
7020
		div_table = div_5333;
5697
		return 133000;
7021
		break;
-
 
7022
	default:
-
 
7023
		goto fail;
-
 
7024
	}
-
 
7025
 
-
 
7026
	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
-
 
7027
 
-
 
7028
fail:
-
 
7029
	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
-
 
7030
	return 200000;
-
 
7031
}
-
 
7032
 
-
 
7033
static int g33_get_display_clock_speed(struct drm_device *dev)
-
 
7034
{
-
 
7035
	static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
-
 
7036
	static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
-
 
7037
	static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
-
 
7038
	static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
-
 
7039
	const uint8_t *div_table;
-
 
7040
	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
-
 
7041
	uint16_t tmp = 0;
-
 
7042
 
-
 
7043
	pci_read_config_word(dev->pdev, GCFGC, &tmp);
-
 
7044
 
-
 
7045
	cdclk_sel = (tmp >> 4) & 0x7;
-
 
7046
 
-
 
7047
	if (cdclk_sel >= ARRAY_SIZE(div_3200))
-
 
7048
		goto fail;
-
 
7049
 
-
 
7050
	switch (vco) {
-
 
7051
	case 3200000:
-
 
7052
		div_table = div_3200;
-
 
7053
		break;
-
 
7054
	case 4000000:
-
 
7055
		div_table = div_4000;
-
 
7056
		break;
-
 
7057
	case 4800000:
-
 
7058
		div_table = div_4800;
-
 
7059
		break;
-
 
7060
	case 5333333:
-
 
7061
		div_table = div_5333;
-
 
7062
		break;
5698
	}
7063
	default:
Line 5699... Line 7064...
5699
 
7064
		goto fail;
5700
	/* Shouldn't happen */
7065
	}
5701
	return 0;
7066
 
Line 5745... Line 7110...
5745
		return i915.panel_use_ssc != 0;
7110
		return i915.panel_use_ssc != 0;
5746
	return dev_priv->vbt.lvds_use_ssc
7111
	return dev_priv->vbt.lvds_use_ssc
5747
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7112
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5748
}
7113
}
Line 5749... Line 7114...
5749
 
7114
 
-
 
7115
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
5750
static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
7116
			   int num_connectors)
5751
{
7117
{
5752
	struct drm_device *dev = crtc->base.dev;
7118
	struct drm_device *dev = crtc_state->base.crtc->dev;
5753
	struct drm_i915_private *dev_priv = dev->dev_private;
7119
	struct drm_i915_private *dev_priv = dev->dev_private;
Line -... Line 7120...
-
 
7120
	int refclk;
-
 
7121
 
5754
	int refclk;
7122
	WARN_ON(!crtc_state->base.state);
5755
 
7123
 
5756
	if (IS_VALLEYVIEW(dev)) {
7124
	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
5757
		refclk = 100000;
7125
		refclk = 100000;
5758
	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
7126
	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
5759
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7127
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5760
		refclk = dev_priv->vbt.lvds_ssc_freq;
7128
		refclk = dev_priv->vbt.lvds_ssc_freq;
5761
		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7129
		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Line 5777... Line 7145...
5777
{
7145
{
5778
	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7146
	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5779
}
7147
}
Line 5780... Line 7148...
5780
 
7148
 
-
 
7149
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5781
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7150
				     struct intel_crtc_state *crtc_state,
5782
				     intel_clock_t *reduced_clock)
7151
				     intel_clock_t *reduced_clock)
5783
{
7152
{
5784
	struct drm_device *dev = crtc->base.dev;
7153
	struct drm_device *dev = crtc->base.dev;
Line 5785... Line 7154...
5785
	u32 fp, fp2 = 0;
7154
	u32 fp, fp2 = 0;
5786
 
7155
 
5787
	if (IS_PINEVIEW(dev)) {
7156
	if (IS_PINEVIEW(dev)) {
5788
		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
7157
		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5789
		if (reduced_clock)
7158
		if (reduced_clock)
5790
			fp2 = pnv_dpll_compute_fp(reduced_clock);
7159
			fp2 = pnv_dpll_compute_fp(reduced_clock);
5791
	} else {
7160
	} else {
5792
		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7161
		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5793
		if (reduced_clock)
7162
		if (reduced_clock)
Line 5794... Line 7163...
5794
			fp2 = i9xx_dpll_compute_fp(reduced_clock);
7163
			fp2 = i9xx_dpll_compute_fp(reduced_clock);
Line 5795... Line 7164...
5795
	}
7164
	}
5796
 
7165
 
5797
	crtc->new_config->dpll_hw_state.fp0 = fp;
7166
	crtc_state->dpll_hw_state.fp0 = fp;
5798
 
7167
 
5799
	crtc->lowfreq_avail = false;
7168
	crtc->lowfreq_avail = false;
5800
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
7169
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
5801
	    reduced_clock && i915.powersave) {
7170
	    reduced_clock) {
5802
		crtc->new_config->dpll_hw_state.fp1 = fp2;
7171
		crtc_state->dpll_hw_state.fp1 = fp2;
5803
		crtc->lowfreq_avail = true;
7172
		crtc->lowfreq_avail = true;
Line 5804... Line 7173...
5804
	} else {
7173
	} else {
5805
		crtc->new_config->dpll_hw_state.fp1 = fp;
7174
		crtc_state->dpll_hw_state.fp1 = fp;
Line 5853... Line 7222...
5853
					 struct intel_link_m_n *m2_n2)
7222
					 struct intel_link_m_n *m2_n2)
5854
{
7223
{
5855
	struct drm_device *dev = crtc->base.dev;
7224
	struct drm_device *dev = crtc->base.dev;
5856
	struct drm_i915_private *dev_priv = dev->dev_private;
7225
	struct drm_i915_private *dev_priv = dev->dev_private;
5857
	int pipe = crtc->pipe;
7226
	int pipe = crtc->pipe;
5858
	enum transcoder transcoder = crtc->config.cpu_transcoder;
7227
	enum transcoder transcoder = crtc->config->cpu_transcoder;
Line 5859... Line 7228...
5859
 
7228
 
5860
	if (INTEL_INFO(dev)->gen >= 5) {
7229
	if (INTEL_INFO(dev)->gen >= 5) {
5861
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7230
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5862
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7231
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5863
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7232
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5864
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7233
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5865
		/* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7234
		/* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5866
		 * for gen < 8) and if DRRS is supported (to make sure the
7235
		 * for gen < 8) and if DRRS is supported (to make sure the
5867
		 * registers are not unnecessarily accessed).
7236
		 * registers are not unnecessarily accessed).
5868
		 */
7237
		 */
5869
		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7238
		if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5870
			crtc->config.has_drrs) {
7239
			crtc->config->has_drrs) {
5871
			I915_WRITE(PIPE_DATA_M2(transcoder),
7240
			I915_WRITE(PIPE_DATA_M2(transcoder),
5872
					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7241
					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5873
			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7242
			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5874
			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7243
			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
Line 5880... Line 7249...
5880
		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7249
		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5881
		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7250
		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5882
	}
7251
	}
5883
}
7252
}
Line 5884... Line 7253...
5884
 
7253
 
5885
void intel_dp_set_m_n(struct intel_crtc *crtc)
7254
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
-
 
7255
{
-
 
7256
	struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
-
 
7257
 
-
 
7258
	if (m_n == M1_N1) {
-
 
7259
		dp_m_n = &crtc->config->dp_m_n;
-
 
7260
		dp_m2_n2 = &crtc->config->dp_m2_n2;
-
 
7261
	} else if (m_n == M2_N2) {
-
 
7262
 
-
 
7263
		/*
-
 
7264
		 * M2_N2 registers are not supported. Hence m2_n2 divider value
-
 
7265
		 * needs to be programmed into M1_N1.
-
 
7266
		 */
-
 
7267
		dp_m_n = &crtc->config->dp_m2_n2;
-
 
7268
	} else {
-
 
7269
		DRM_ERROR("Unsupported divider value\n");
-
 
7270
		return;
-
 
7271
	}
5886
{
7272
 
5887
	if (crtc->config.has_pch_encoder)
7273
	if (crtc->config->has_pch_encoder)
5888
		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
7274
		intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5889
	else
7275
	else
5890
		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
-
 
5891
						   &crtc->config.dp_m2_n2);
7276
		intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
Line 5892... Line 7277...
5892
}
7277
}
5893
 
7278
 
5894
static void vlv_update_pll(struct intel_crtc *crtc,
7279
static void vlv_compute_dpll(struct intel_crtc *crtc,
5895
			   struct intel_crtc_config *pipe_config)
7280
			     struct intel_crtc_state *pipe_config)
Line 5896... Line 7281...
5896
{
7281
{
5897
	u32 dpll, dpll_md;
7282
	u32 dpll, dpll_md;
5898
 
7283
 
5899
	/*
7284
	/*
5900
	 * Enable DPIO clock input. We should never disable the reference
7285
	 * Enable DPIO clock input. We should never disable the reference
5901
	 * clock for pipe B, since VGA hotplug / manual detection depends
7286
	 * clock for pipe B, since VGA hotplug / manual detection depends
5902
	 * on it.
7287
	 * on it.
5903
	 */
7288
	 */
5904
	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7289
	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
5905
		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7290
		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
5906
	/* We should never disable this, set it here for state tracking */
7291
	/* We should never disable this, set it here for state tracking */
5907
	if (crtc->pipe == PIPE_B)
7292
	if (crtc->pipe == PIPE_B)
Line 5913... Line 7298...
5913
		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
7298
		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
5914
	pipe_config->dpll_hw_state.dpll_md = dpll_md;
7299
	pipe_config->dpll_hw_state.dpll_md = dpll_md;
5915
}
7300
}
Line 5916... Line 7301...
5916
 
7301
 
5917
static void vlv_prepare_pll(struct intel_crtc *crtc,
7302
static void vlv_prepare_pll(struct intel_crtc *crtc,
5918
			    const struct intel_crtc_config *pipe_config)
7303
			    const struct intel_crtc_state *pipe_config)
5919
{
7304
{
5920
	struct drm_device *dev = crtc->base.dev;
7305
	struct drm_device *dev = crtc->base.dev;
5921
	struct drm_i915_private *dev_priv = dev->dev_private;
7306
	struct drm_i915_private *dev_priv = dev->dev_private;
5922
	int pipe = crtc->pipe;
7307
	int pipe = crtc->pipe;
5923
	u32 mdiv;
7308
	u32 mdiv;
5924
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
7309
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
Line 5925... Line 7310...
5925
	u32 coreclk, reg_val;
7310
	u32 coreclk, reg_val;
Line 5926... Line 7311...
5926
 
7311
 
5927
	mutex_lock(&dev_priv->dpio_lock);
7312
	mutex_lock(&dev_priv->sb_lock);
5928
 
7313
 
5929
	bestn = pipe_config->dpll.n;
7314
	bestn = pipe_config->dpll.n;
Line 5974... Line 7359...
5974
				 0x009f0003);
7359
				 0x009f0003);
5975
	else
7360
	else
5976
		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7361
		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5977
				 0x00d0000f);
7362
				 0x00d0000f);
Line 5978... Line 7363...
5978
 
7363
 
5979
	if (crtc->config.has_dp_encoder) {
7364
	if (pipe_config->has_dp_encoder) {
5980
		/* Use SSC source */
7365
		/* Use SSC source */
5981
		if (pipe == PIPE_A)
7366
		if (pipe == PIPE_A)
5982
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7367
			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5983
					 0x0df40000);
7368
					 0x0df40000);
Line 6000... Line 7385...
6000
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7385
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6001
		coreclk |= 0x01000000;
7386
		coreclk |= 0x01000000;
6002
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7387
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Line 6003... Line 7388...
6003
 
7388
 
6004
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7389
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6005
	mutex_unlock(&dev_priv->dpio_lock);
7390
	mutex_unlock(&dev_priv->sb_lock);
Line 6006... Line 7391...
6006
}
7391
}
6007
 
7392
 
6008
static void chv_update_pll(struct intel_crtc *crtc,
7393
static void chv_compute_dpll(struct intel_crtc *crtc,
6009
			   struct intel_crtc_config *pipe_config)
7394
			     struct intel_crtc_state *pipe_config)
6010
{
7395
{
6011
	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7396
	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6012
		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7397
		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6013
		DPLL_VCO_ENABLE;
7398
		DPLL_VCO_ENABLE;
Line 6014... Line 7399...
6014
	if (crtc->pipe != PIPE_A)
7399
	if (crtc->pipe != PIPE_A)
6015
		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7400
		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6016
 
7401
 
Line 6017... Line 7402...
6017
	pipe_config->dpll_hw_state.dpll_md =
7402
	pipe_config->dpll_hw_state.dpll_md =
6018
		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7403
		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6019
}
7404
}
6020
 
7405
 
6021
static void chv_prepare_pll(struct intel_crtc *crtc,
7406
static void chv_prepare_pll(struct intel_crtc *crtc,
6022
			    const struct intel_crtc_config *pipe_config)
7407
			    const struct intel_crtc_state *pipe_config)
6023
{
7408
{
6024
	struct drm_device *dev = crtc->base.dev;
7409
	struct drm_device *dev = crtc->base.dev;
6025
	struct drm_i915_private *dev_priv = dev->dev_private;
7410
	struct drm_i915_private *dev_priv = dev->dev_private;
6026
	int pipe = crtc->pipe;
7411
	int pipe = crtc->pipe;
-
 
7412
	int dpll_reg = DPLL(crtc->pipe);
6027
	int dpll_reg = DPLL(crtc->pipe);
7413
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
Line 6028... Line 7414...
6028
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
7414
	u32 loopfilter, tribuf_calcntr;
6029
	u32 loopfilter, intcoeff;
7415
	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6030
	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7416
	u32 dpio_val;
6031
	int refclk;
7417
	int vco;
6032
 
7418
 
6033
	bestn = pipe_config->dpll.n;
7419
	bestn = pipe_config->dpll.n;
-
 
7420
	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
-
 
7421
	bestm1 = pipe_config->dpll.m1;
-
 
7422
	bestm2 = pipe_config->dpll.m2 >> 22;
Line 6034... Line 7423...
6034
	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7423
	bestp1 = pipe_config->dpll.p1;
6035
	bestm1 = pipe_config->dpll.m1;
7424
	bestp2 = pipe_config->dpll.p2;
6036
	bestm2 = pipe_config->dpll.m2 >> 22;
7425
	vco = pipe_config->dpll.vco;
6037
	bestp1 = pipe_config->dpll.p1;
7426
	dpio_val = 0;
6038
	bestp2 = pipe_config->dpll.p2;
7427
	loopfilter = 0;
Line 6039... Line 7428...
6039
 
7428
 
Line 6040... Line 7429...
6040
	/*
7429
	/*
6041
	 * Enable Refclk and SSC
7430
	 * Enable Refclk and SSC
6042
	 */
7431
	 */
6043
	I915_WRITE(dpll_reg,
7432
	I915_WRITE(dpll_reg,
Line 6062... Line 7451...
6062
 
7451
 
6063
	/* M2 fraction division */
7452
	/* M2 fraction division */
Line 6064... Line 7453...
6064
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7453
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6065
 
7454
 
-
 
7455
	/* M2 fraction division enable */
-
 
7456
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
-
 
7457
	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6066
	/* M2 fraction division enable */
7458
	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
-
 
7459
	if (bestm2_frac)
-
 
7460
		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
-
 
7461
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
-
 
7462
 
-
 
7463
	/* Program digital lock detect threshold */
-
 
7464
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6067
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
7465
	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
-
 
7466
					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
-
 
7467
	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
-
 
7468
	if (!bestm2_frac)
Line 6068... Line 7469...
6068
		       DPIO_CHV_FRAC_DIV_EN |
7469
		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
-
 
7470
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6069
		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
7471
 
6070
 
7472
	/* Loop filter */
6071
	/* Loop filter */
7473
	if (vco == 5400000) {
-
 
7474
		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6072
	refclk = i9xx_get_refclk(crtc, 0);
7475
		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
-
 
7476
		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
-
 
7477
		tribuf_calcntr = 0x9;
-
 
7478
	} else if (vco <= 6200000) {
6073
	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
7479
		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6074
		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
7480
		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
-
 
7481
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
-
 
7482
		tribuf_calcntr = 0x9;
-
 
7483
	} else if (vco <= 6480000) {
6075
	if (refclk == 100000)
7484
		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6076
		intcoeff = 11;
7485
		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
-
 
7486
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6077
	else if (refclk == 38400)
7487
		tribuf_calcntr = 0x8;
6078
		intcoeff = 10;
7488
	} else {
-
 
7489
		/* Not supported. Apply the same limits as in the max case */
-
 
7490
		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
-
 
7491
		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6079
	else
7492
		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
Line -... Line 7493...
-
 
7493
		tribuf_calcntr = 0;
-
 
7494
	}
-
 
7495
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
-
 
7496
 
-
 
7497
	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6080
		intcoeff = 9;
7498
	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6081
	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
7499
	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6082
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7500
	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6083
 
7501
 
Line 6084... Line 7502...
6084
	/* AFC Recal */
7502
	/* AFC Recal */
6085
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7503
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
Line 6086... Line 7504...
6086
			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7504
			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6087
			DPIO_AFC_RECAL);
7505
			DPIO_AFC_RECAL);
6088
 
7506
 
Line 6102... Line 7520...
6102
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7520
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6103
		      const struct dpll *dpll)
7521
		      const struct dpll *dpll)
6104
{
7522
{
6105
	struct intel_crtc *crtc =
7523
	struct intel_crtc *crtc =
6106
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7524
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6107
	struct intel_crtc_config pipe_config = {
7525
	struct intel_crtc_state pipe_config = {
-
 
7526
		.base.crtc = &crtc->base,
6108
		.pixel_multiplier = 1,
7527
		.pixel_multiplier = 1,
6109
		.dpll = *dpll,
7528
		.dpll = *dpll,
6110
	};
7529
	};
Line 6111... Line 7530...
6111
 
7530
 
6112
	if (IS_CHERRYVIEW(dev)) {
7531
	if (IS_CHERRYVIEW(dev)) {
6113
		chv_update_pll(crtc, &pipe_config);
7532
		chv_compute_dpll(crtc, &pipe_config);
6114
		chv_prepare_pll(crtc, &pipe_config);
7533
		chv_prepare_pll(crtc, &pipe_config);
6115
		chv_enable_pll(crtc, &pipe_config);
7534
		chv_enable_pll(crtc, &pipe_config);
6116
	} else {
7535
	} else {
6117
		vlv_update_pll(crtc, &pipe_config);
7536
		vlv_compute_dpll(crtc, &pipe_config);
6118
		vlv_prepare_pll(crtc, &pipe_config);
7537
		vlv_prepare_pll(crtc, &pipe_config);
6119
		vlv_enable_pll(crtc, &pipe_config);
7538
		vlv_enable_pll(crtc, &pipe_config);
6120
	}
7539
	}
Line 6134... Line 7553...
6134
		chv_disable_pll(to_i915(dev), pipe);
7553
		chv_disable_pll(to_i915(dev), pipe);
6135
	else
7554
	else
6136
		vlv_disable_pll(to_i915(dev), pipe);
7555
		vlv_disable_pll(to_i915(dev), pipe);
6137
}
7556
}
Line 6138... Line 7557...
6138
 
7557
 
-
 
7558
static void i9xx_compute_dpll(struct intel_crtc *crtc,
6139
static void i9xx_update_pll(struct intel_crtc *crtc,
7559
			      struct intel_crtc_state *crtc_state,
6140
			    intel_clock_t *reduced_clock,
7560
			      intel_clock_t *reduced_clock,
6141
			    int num_connectors)
7561
			      int num_connectors)
6142
{
7562
{
6143
	struct drm_device *dev = crtc->base.dev;
7563
	struct drm_device *dev = crtc->base.dev;
6144
	struct drm_i915_private *dev_priv = dev->dev_private;
7564
	struct drm_i915_private *dev_priv = dev->dev_private;
6145
	u32 dpll;
7565
	u32 dpll;
6146
	bool is_sdvo;
7566
	bool is_sdvo;
Line 6147... Line 7567...
6147
	struct dpll *clock = &crtc->new_config->dpll;
7567
	struct dpll *clock = &crtc_state->dpll;
Line 6148... Line 7568...
6148
 
7568
 
6149
	i9xx_update_pll_dividers(crtc, reduced_clock);
7569
	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Line 6150... Line 7570...
6150
 
7570
 
Line 6151... Line 7571...
6151
	is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
7571
	is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6152
		intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
7572
		intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
6153
 
7573
 
6154
	dpll = DPLL_VGA_MODE_DIS;
7574
	dpll = DPLL_VGA_MODE_DIS;
Line 6155... Line 7575...
6155
 
7575
 
6156
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
7576
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
6157
		dpll |= DPLLB_MODE_LVDS;
7577
		dpll |= DPLLB_MODE_LVDS;
6158
	else
7578
	else
Line 6159... Line 7579...
6159
		dpll |= DPLLB_MODE_DAC_SERIAL;
7579
		dpll |= DPLLB_MODE_DAC_SERIAL;
6160
 
7580
 
Line 6161... Line 7581...
6161
	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7581
	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6162
		dpll |= (crtc->new_config->pixel_multiplier - 1)
7582
		dpll |= (crtc_state->pixel_multiplier - 1)
Line 6163... Line 7583...
6163
				<< SDVO_MULTIPLIER_SHIFT_HIRES;
7583
			<< SDVO_MULTIPLIER_SHIFT_HIRES;
6164
		}
7584
	}
6165
 
7585
 
Line 6192... Line 7612...
6192
		break;
7612
		break;
6193
	}
7613
	}
6194
	if (INTEL_INFO(dev)->gen >= 4)
7614
	if (INTEL_INFO(dev)->gen >= 4)
6195
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7615
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
Line 6196... Line 7616...
6196
 
7616
 
6197
	if (crtc->new_config->sdvo_tv_clock)
7617
	if (crtc_state->sdvo_tv_clock)
6198
		dpll |= PLL_REF_INPUT_TVCLKINBC;
7618
		dpll |= PLL_REF_INPUT_TVCLKINBC;
6199
	else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
7619
	else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6200
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7620
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6201
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7621
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6202
	else
7622
	else
Line 6203... Line 7623...
6203
		dpll |= PLL_REF_INPUT_DREFCLK;
7623
		dpll |= PLL_REF_INPUT_DREFCLK;
6204
 
7624
 
Line 6205... Line 7625...
6205
	dpll |= DPLL_VCO_ENABLE;
7625
	dpll |= DPLL_VCO_ENABLE;
6206
	crtc->new_config->dpll_hw_state.dpll = dpll;
7626
	crtc_state->dpll_hw_state.dpll = dpll;
6207
 
7627
 
6208
	if (INTEL_INFO(dev)->gen >= 4) {
7628
	if (INTEL_INFO(dev)->gen >= 4) {
6209
		u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
7629
		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6210
					<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
7630
			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
Line 6211... Line 7631...
6211
		crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
7631
		crtc_state->dpll_hw_state.dpll_md = dpll_md;
-
 
7632
	}
6212
	}
7633
}
6213
}
7634
 
6214
 
7635
static void i8xx_compute_dpll(struct intel_crtc *crtc,
6215
static void i8xx_update_pll(struct intel_crtc *crtc,
7636
			      struct intel_crtc_state *crtc_state,
6216
			    intel_clock_t *reduced_clock,
7637
			      intel_clock_t *reduced_clock,
6217
			    int num_connectors)
7638
			      int num_connectors)
6218
{
7639
{
Line 6219... Line 7640...
6219
	struct drm_device *dev = crtc->base.dev;
7640
	struct drm_device *dev = crtc->base.dev;
Line 6220... Line 7641...
6220
	struct drm_i915_private *dev_priv = dev->dev_private;
7641
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 6221... Line 7642...
6221
	u32 dpll;
7642
	u32 dpll;
6222
	struct dpll *clock = &crtc->new_config->dpll;
7643
	struct dpll *clock = &crtc_state->dpll;
6223
 
7644
 
6224
	i9xx_update_pll_dividers(crtc, reduced_clock);
7645
	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6225
 
7646
 
6226
	dpll = DPLL_VGA_MODE_DIS;
7647
	dpll = DPLL_VGA_MODE_DIS;
6227
 
7648
 
6228
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
7649
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6229
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7650
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6230
	} else {
7651
	} else {
Line 6231... Line 7652...
6231
		if (clock->p1 == 2)
7652
		if (clock->p1 == 2)
6232
			dpll |= PLL_P1_DIVIDE_BY_TWO;
7653
			dpll |= PLL_P1_DIVIDE_BY_TWO;
Line 6233... Line 7654...
6233
		else
7654
		else
6234
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7655
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6235
		if (clock->p2 == 4)
7656
		if (clock->p2 == 4)
6236
			dpll |= PLL_P2_DIVIDE_BY_4;
7657
			dpll |= PLL_P2_DIVIDE_BY_4;
6237
	}
7658
	}
Line 6238... Line 7659...
6238
 
7659
 
6239
	if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
7660
	if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
6240
		dpll |= DPLL_DVO_2X_MODE;
7661
		dpll |= DPLL_DVO_2X_MODE;
Line 6241... Line 7662...
6241
 
7662
 
6242
	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
7663
	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6243
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7664
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6244
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7665
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6245
	else
7666
	else
6246
		dpll |= PLL_REF_INPUT_DREFCLK;
7667
		dpll |= PLL_REF_INPUT_DREFCLK;
6247
 
7668
 
6248
	dpll |= DPLL_VCO_ENABLE;
-
 
6249
	crtc->new_config->dpll_hw_state.dpll = dpll;
7669
	dpll |= DPLL_VCO_ENABLE;
6250
}
7670
	crtc_state->dpll_hw_state.dpll = dpll;
Line 6251... Line 7671...
6251
 
7671
}
6252
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7672
 
Line 6312... Line 7732...
6312
 
7732
 
6313
	/* pipesrc controls the size that is scaled from, which should
7733
	/* pipesrc controls the size that is scaled from, which should
6314
	 * always be the user's requested size.
7734
	 * always be the user's requested size.
6315
	 */
7735
	 */
6316
	I915_WRITE(PIPESRC(pipe),
7736
	I915_WRITE(PIPESRC(pipe),
6317
		   ((intel_crtc->config.pipe_src_w - 1) << 16) |
7737
		   ((intel_crtc->config->pipe_src_w - 1) << 16) |
6318
		   (intel_crtc->config.pipe_src_h - 1));
7738
		   (intel_crtc->config->pipe_src_h - 1));
Line 6319... Line 7739...
6319
}
7739
}
6320
 
7740
 
6321
static void intel_get_pipe_timings(struct intel_crtc *crtc,
7741
static void intel_get_pipe_timings(struct intel_crtc *crtc,
6322
				   struct intel_crtc_config *pipe_config)
7742
				   struct intel_crtc_state *pipe_config)
6323
{
7743
{
6324
	struct drm_device *dev = crtc->base.dev;
7744
	struct drm_device *dev = crtc->base.dev;
6325
	struct drm_i915_private *dev_priv = dev->dev_private;
7745
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 6326... Line 7746...
6326
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7746
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6327
	uint32_t tmp;
7747
	uint32_t tmp;
6328
 
7748
 
6329
	tmp = I915_READ(HTOTAL(cpu_transcoder));
7749
	tmp = I915_READ(HTOTAL(cpu_transcoder));
6330
	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7750
	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6331
	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7751
	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6332
	tmp = I915_READ(HBLANK(cpu_transcoder));
7752
	tmp = I915_READ(HBLANK(cpu_transcoder));
6333
	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7753
	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6334
	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7754
	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
Line 6335... Line 7755...
6335
	tmp = I915_READ(HSYNC(cpu_transcoder));
7755
	tmp = I915_READ(HSYNC(cpu_transcoder));
6336
	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7756
	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6337
	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7757
	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6338
 
7758
 
6339
	tmp = I915_READ(VTOTAL(cpu_transcoder));
7759
	tmp = I915_READ(VTOTAL(cpu_transcoder));
6340
	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7760
	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6341
	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7761
	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6342
	tmp = I915_READ(VBLANK(cpu_transcoder));
7762
	tmp = I915_READ(VBLANK(cpu_transcoder));
6343
	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7763
	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
Line 6344... Line 7764...
6344
	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7764
	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6345
	tmp = I915_READ(VSYNC(cpu_transcoder));
7765
	tmp = I915_READ(VSYNC(cpu_transcoder));
6346
	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7766
	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6347
	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7767
	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6348
 
7768
 
Line 6349... Line 7769...
6349
	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7769
	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6350
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7770
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6351
		pipe_config->adjusted_mode.crtc_vtotal += 1;
7771
		pipe_config->base.adjusted_mode.crtc_vtotal += 1;
Line 6352... Line 7772...
6352
		pipe_config->adjusted_mode.crtc_vblank_end += 1;
7772
		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6353
	}
7773
	}
6354
 
7774
 
Line 6355... Line 7775...
6355
	tmp = I915_READ(PIPESRC(crtc->pipe));
7775
	tmp = I915_READ(PIPESRC(crtc->pipe));
6356
	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7776
	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6357
	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7777
	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6358
 
7778
 
6359
	pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
7779
	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6360
	pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
7780
	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6361
}
7781
}
6362
 
7782
 
6363
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7783
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6364
					     struct intel_crtc_config *pipe_config)
7784
				 struct intel_crtc_state *pipe_config)
6365
{
7785
{
6366
	mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
7786
	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
Line 6367... Line 7787...
6367
	mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
7787
	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
-
 
7788
	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
Line 6368... Line 7789...
6368
	mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
7789
	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6369
	mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
7790
 
-
 
7791
	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
-
 
7792
	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
-
 
7793
	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
-
 
7794
	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6370
 
7795
 
Line 6371... Line 7796...
6371
	mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
7796
	mode->flags = pipe_config->base.adjusted_mode.flags;
6372
	mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
7797
	mode->type = DRM_MODE_TYPE_DRIVER;
6373
	mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
7798
 
Line 6389... Line 7814...
6389
 
7814
 
6390
	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7815
	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6391
	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7816
	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Line 6392... Line 7817...
6392
		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7817
		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6393
 
7818
 
Line 6394... Line 7819...
6394
	if (intel_crtc->config.double_wide)
7819
	if (intel_crtc->config->double_wide)
6395
			pipeconf |= PIPECONF_DOUBLE_WIDE;
7820
		pipeconf |= PIPECONF_DOUBLE_WIDE;
6396
 
7821
 
6397
	/* only g4x and later have fancy bpc/dither controls */
7822
	/* only g4x and later have fancy bpc/dither controls */
6398
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7823
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6399
		/* Bspec claims that we can't use dithering for 30bpp pipes. */
7824
		/* Bspec claims that we can't use dithering for 30bpp pipes. */
Line 6400... Line 7825...
6400
		if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
7825
		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6401
			pipeconf |= PIPECONF_DITHER_EN |
7826
			pipeconf |= PIPECONF_DITHER_EN |
6402
				    PIPECONF_DITHER_TYPE_SP;
7827
				    PIPECONF_DITHER_TYPE_SP;
6403
 
7828
 
6404
		switch (intel_crtc->config.pipe_bpp) {
7829
		switch (intel_crtc->config->pipe_bpp) {
6405
		case 18:
7830
		case 18:
Line 6424... Line 7849...
6424
		} else {
7849
		} else {
6425
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7850
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6426
		}
7851
		}
6427
	}
7852
	}
Line 6428... Line 7853...
6428
 
7853
 
6429
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7854
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6430
		if (INTEL_INFO(dev)->gen < 4 ||
7855
		if (INTEL_INFO(dev)->gen < 4 ||
6431
		    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7856
		    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6432
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7857
			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6433
	else
7858
		else
6434
			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7859
			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6435
	} else
7860
	} else
Line 6436... Line 7861...
6436
		pipeconf |= PIPECONF_PROGRESSIVE;
7861
		pipeconf |= PIPECONF_PROGRESSIVE;
6437
 
7862
 
Line 6438... Line 7863...
6438
	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
7863
	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6439
			pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7864
		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6440
 
7865
 
Line 6441... Line 7866...
6441
	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7866
	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
-
 
7867
	POSTING_READ(PIPECONF(intel_crtc->pipe));
6442
	POSTING_READ(PIPECONF(intel_crtc->pipe));
7868
}
6443
}
7869
 
6444
 
7870
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6445
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
7871
				   struct intel_crtc_state *crtc_state)
6446
{
7872
{
6447
	struct drm_device *dev = crtc->base.dev;
7873
	struct drm_device *dev = crtc->base.dev;
6448
	struct drm_i915_private *dev_priv = dev->dev_private;
7874
	struct drm_i915_private *dev_priv = dev->dev_private;
6449
	int refclk, num_connectors = 0;
7875
	int refclk, num_connectors = 0;
6450
	intel_clock_t clock, reduced_clock;
7876
	intel_clock_t clock;
-
 
7877
	bool ok;
-
 
7878
	bool is_dsi = false;
-
 
7879
	struct intel_encoder *encoder;
-
 
7880
	const intel_limit_t *limit;
Line -... Line 7881...
-
 
7881
	struct drm_atomic_state *state = crtc_state->base.state;
-
 
7882
	struct drm_connector *connector;
-
 
7883
	struct drm_connector_state *connector_state;
6451
	bool ok, has_reduced_clock = false;
7884
	int i;
6452
	bool is_lvds = false, is_dsi = false;
7885
 
6453
	struct intel_encoder *encoder;
7886
	memset(&crtc_state->dpll_hw_state, 0,
Line -... Line 7887...
-
 
7887
	       sizeof(crtc_state->dpll_hw_state));
-
 
7888
 
6454
	const intel_limit_t *limit;
7889
	for_each_connector_in_state(state, connector, connector_state, i) {
6455
 
-
 
6456
	for_each_intel_encoder(dev, encoder) {
-
 
6457
		if (encoder->new_crtc != crtc)
-
 
6458
			continue;
7890
		if (connector_state->crtc != &crtc->base)
6459
 
7891
			continue;
6460
		switch (encoder->type) {
7892
 
6461
		case INTEL_OUTPUT_LVDS:
7893
		encoder = to_intel_encoder(connector_state->best_encoder);
6462
			is_lvds = true;
7894
 
Line 6472... Line 7904...
6472
	}
7904
	}
Line 6473... Line 7905...
6473
 
7905
 
6474
	if (is_dsi)
7906
	if (is_dsi)
Line 6475... Line 7907...
6475
		return 0;
7907
		return 0;
6476
 
7908
 
Line 6477... Line 7909...
6477
	if (!crtc->new_config->clock_set) {
7909
	if (!crtc_state->clock_set) {
6478
	refclk = i9xx_get_refclk(crtc, num_connectors);
7910
		refclk = i9xx_get_refclk(crtc_state, num_connectors);
6479
 
7911
 
6480
	/*
7912
		/*
6481
		 * Returns a set of divisors for the desired target clock with
7913
		 * Returns a set of divisors for the desired target clock with
6482
		 * the given refclk, or FALSE.  The returned values represent
7914
		 * the given refclk, or FALSE.  The returned values represent
6483
		 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7915
		 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6484
		 * 2) / p1 / p2.
7916
		 * 2) / p1 / p2.
6485
	 */
7917
		 */
6486
	limit = intel_limit(crtc, refclk);
7918
		limit = intel_limit(crtc_state, refclk);
6487
	ok = dev_priv->display.find_dpll(limit, crtc,
7919
		ok = dev_priv->display.find_dpll(limit, crtc_state,
6488
						 crtc->new_config->port_clock,
7920
						 crtc_state->port_clock,
6489
					 refclk, NULL, &clock);
7921
						 refclk, NULL, &clock);
6490
		if (!ok) {
7922
		if (!ok) {
Line 6491... Line -...
6491
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
-
 
6492
		return -EINVAL;
-
 
6493
	}
-
 
6494
 
-
 
6495
	if (is_lvds && dev_priv->lvds_downclock_avail) {
-
 
6496
		/*
-
 
6497
			 * Ensure we match the reduced clock's P to the target
-
 
6498
			 * clock.  If the clocks don't match, we can't switch
-
 
6499
			 * the display clock by using the FP0/FP1. In such case
-
 
6500
			 * we will disable the LVDS downclock feature.
-
 
6501
		*/
-
 
6502
		has_reduced_clock =
-
 
6503
			dev_priv->display.find_dpll(limit, crtc,
-
 
6504
						    dev_priv->lvds_downclock,
7923
			DRM_ERROR("Couldn't find PLL settings for mode!\n");
6505
						    refclk, &clock,
7924
			return -EINVAL;
6506
						    &reduced_clock);
7925
		}
6507
	}
7926
 
6508
	/* Compat-code for transition, will disappear. */
7927
		/* Compat-code for transition, will disappear. */
6509
		crtc->new_config->dpll.n = clock.n;
7928
		crtc_state->dpll.n = clock.n;
6510
		crtc->new_config->dpll.m1 = clock.m1;
7929
		crtc_state->dpll.m1 = clock.m1;
Line 6511... Line 7930...
6511
		crtc->new_config->dpll.m2 = clock.m2;
7930
		crtc_state->dpll.m2 = clock.m2;
6512
		crtc->new_config->dpll.p1 = clock.p1;
-
 
6513
		crtc->new_config->dpll.p2 = clock.p2;
7931
		crtc_state->dpll.p1 = clock.p1;
6514
	}
7932
		crtc_state->dpll.p2 = clock.p2;
6515
 
7933
	}
6516
	if (IS_GEN2(dev)) {
7934
 
6517
		i8xx_update_pll(crtc,
7935
	if (IS_GEN2(dev)) {
6518
				has_reduced_clock ? &reduced_clock : NULL,
7936
		i8xx_compute_dpll(crtc, crtc_state, NULL,
6519
				num_connectors);
7937
				  num_connectors);
6520
	} else if (IS_CHERRYVIEW(dev)) {
-
 
6521
		chv_update_pll(crtc, crtc->new_config);
7938
	} else if (IS_CHERRYVIEW(dev)) {
6522
	} else if (IS_VALLEYVIEW(dev)) {
7939
		chv_compute_dpll(crtc, crtc_state);
6523
		vlv_update_pll(crtc, crtc->new_config);
7940
	} else if (IS_VALLEYVIEW(dev)) {
Line 6524... Line 7941...
6524
	} else {
7941
		vlv_compute_dpll(crtc, crtc_state);
6525
		i9xx_update_pll(crtc,
7942
	} else {
Line 6526... Line 7943...
6526
				has_reduced_clock ? &reduced_clock : NULL,
7943
		i9xx_compute_dpll(crtc, crtc_state, NULL,
6527
				num_connectors);
7944
				  num_connectors);
6528
	}
7945
	}
6529
 
7946
 
6530
	return 0;
7947
	return 0;
6531
}
7948
}
Line 6559... Line 7976...
6559
		pipe_config->gmch_pfit.lvds_border_bits =
7976
		pipe_config->gmch_pfit.lvds_border_bits =
6560
			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7977
			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6561
}
7978
}
Line 6562... Line 7979...
6562
 
7979
 
6563
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7980
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6564
			       struct intel_crtc_config *pipe_config)
7981
			       struct intel_crtc_state *pipe_config)
6565
{
7982
{
6566
	struct drm_device *dev = crtc->base.dev;
7983
	struct drm_device *dev = crtc->base.dev;
6567
	struct drm_i915_private *dev_priv = dev->dev_private;
7984
	struct drm_i915_private *dev_priv = dev->dev_private;
6568
	int pipe = pipe_config->cpu_transcoder;
7985
	int pipe = pipe_config->cpu_transcoder;
Line 6572... Line 7989...
6572
 
7989
 
6573
	/* In case of MIPI DPLL will not even be used */
7990
	/* In case of MIPI DPLL will not even be used */
6574
	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7991
	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
Line 6575... Line 7992...
6575
		return;
7992
		return;
6576
 
7993
 
6577
	mutex_lock(&dev_priv->dpio_lock);
7994
	mutex_lock(&dev_priv->sb_lock);
Line 6578... Line 7995...
6578
	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7995
	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6579
	mutex_unlock(&dev_priv->dpio_lock);
7996
	mutex_unlock(&dev_priv->sb_lock);
6580
 
7997
 
6581
	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7998
	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6582
	clock.m2 = mdiv & DPIO_M2DIV_MASK;
7999
	clock.m2 = mdiv & DPIO_M2DIV_MASK;
Line 6583... Line -...
6583
	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
-
 
6584
	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
-
 
6585
	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
-
 
6586
 
8000
	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6587
	vlv_clock(refclk, &clock);
8001
	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
Line -... Line 8002...
-
 
8002
	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6588
 
8003
 
6589
	/* clock.dot is the fast clock */
8004
	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
6590
	pipe_config->port_clock = clock.dot / 5;
8005
}
6591
}
8006
 
6592
 
8007
static void
6593
static void i9xx_get_plane_config(struct intel_crtc *crtc,
8008
i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6594
				  struct intel_plane_config *plane_config)
8009
			      struct intel_initial_plane_config *plane_config)
6595
{
8010
{
6596
	struct drm_device *dev = crtc->base.dev;
8011
	struct drm_device *dev = crtc->base.dev;
-
 
8012
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8013
	u32 val, base, offset;
Line -... Line 8014...
-
 
8014
	int pipe = crtc->pipe, plane = crtc->plane;
-
 
8015
	int fourcc, pixel_format;
-
 
8016
	unsigned int aligned_height;
-
 
8017
	struct drm_framebuffer *fb;
6597
	struct drm_i915_private *dev_priv = dev->dev_private;
8018
	struct intel_framebuffer *intel_fb;
6598
	u32 val, base, offset;
8019
 
6599
	int pipe = crtc->pipe, plane = crtc->plane;
8020
	val = I915_READ(DSPCNTR(plane));
6600
	int fourcc, pixel_format;
8021
	if (!(val & DISPLAY_PLANE_ENABLE))
6601
	int aligned_height;
8022
		return;
Line 6602... Line 8023...
6602
 
8023
 
Line 6603... Line 8024...
6603
	crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
8024
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6604
	if (!crtc->base.primary->fb) {
8025
	if (!intel_fb) {
6605
		DRM_DEBUG_KMS("failed to alloc fb\n");
8026
		DRM_DEBUG_KMS("failed to alloc fb\n");
-
 
8027
		return;
-
 
8028
	}
-
 
8029
 
Line 6606... Line 8030...
6606
		return;
8030
	fb = &intel_fb->base;
6607
	}
8031
 
6608
 
8032
	if (INTEL_INFO(dev)->gen >= 4) {
6609
	val = I915_READ(DSPCNTR(plane));
-
 
6610
 
8033
		if (val & DISPPLANE_TILED) {
Line 6611... Line 8034...
6611
	if (INTEL_INFO(dev)->gen >= 4)
8034
			plane_config->tiling = I915_TILING_X;
6612
		if (val & DISPPLANE_TILED)
8035
			fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6613
			plane_config->tiled = true;
8036
		}
6614
 
8037
	}
6615
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8038
 
6616
	fourcc = intel_format_to_fourcc(pixel_format);
8039
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6617
	crtc->base.primary->fb->pixel_format = fourcc;
8040
	fourcc = i9xx_format_to_fourcc(pixel_format);
6618
	crtc->base.primary->fb->bits_per_pixel =
8041
	fb->pixel_format = fourcc;
6619
		drm_format_plane_cpp(fourcc, 0) * 8;
8042
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6620
 
8043
 
Line 6621... Line 8044...
6621
	if (INTEL_INFO(dev)->gen >= 4) {
8044
	if (INTEL_INFO(dev)->gen >= 4) {
6622
		if (plane_config->tiled)
8045
		if (plane_config->tiling)
6623
			offset = I915_READ(DSPTILEOFF(plane));
8046
			offset = I915_READ(DSPTILEOFF(plane));
Line 6624... Line 8047...
6624
		else
8047
		else
6625
			offset = I915_READ(DSPLINOFF(plane));
8048
			offset = I915_READ(DSPLINOFF(plane));
-
 
8049
		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
Line 6626... Line 8050...
6626
		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8050
	} else {
-
 
8051
		base = I915_READ(DSPADDR(plane));
6627
	} else {
8052
	}
6628
		base = I915_READ(DSPADDR(plane));
8053
	plane_config->base = base;
6629
	}
8054
 
6630
	plane_config->base = base;
8055
	val = I915_READ(PIPESRC(pipe));
6631
 
8056
	fb->width = ((val >> 16) & 0xfff) + 1;
6632
	val = I915_READ(PIPESRC(pipe));
8057
	fb->height = ((val >> 0) & 0xfff) + 1;
6633
	crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
8058
 
6634
	crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
-
 
6635
 
-
 
6636
	val = I915_READ(DSPSTRIDE(pipe));
8059
	val = I915_READ(DSPSTRIDE(pipe));
6637
	crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
8060
//   fb->pitches[0] = val & 0xffffffc0;
Line -... Line 8061...
-
 
8061
	fb->pitches[0] = 2560*4;
6638
 
8062
 
Line 6639... Line 8063...
6639
	aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
8063
	aligned_height = intel_fb_align_height(dev, fb->height,
6640
					    plane_config->tiled);
8064
					       fb->pixel_format,
6641
 
8065
					       fb->modifier[0]);
6642
	plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
8066
 
6643
					aligned_height);
8067
//   plane_config->size = fb->pitches[0] * aligned_height;
6644
 
8068
 	plane_config->size = i915_fbsize*1024*1024;
6645
	DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8069
 
6646
		      pipe, plane, crtc->base.primary->fb->width,
8070
	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6647
		      crtc->base.primary->fb->height,
8071
		      pipe_name(pipe), plane, fb->width, fb->height,
6648
		      crtc->base.primary->fb->bits_per_pixel, base,
8072
		      fb->bits_per_pixel, base, fb->pitches[0],
Line 6649... Line 8073...
6649
		      crtc->base.primary->fb->pitches[0],
8073
		      plane_config->size);
6650
		      plane_config->size);
8074
 
6651
 
8075
	plane_config->fb = intel_fb;
6652
}
8076
}
6653
 
8077
 
-
 
8078
static void chv_crtc_clock_get(struct intel_crtc *crtc,
6654
static void chv_crtc_clock_get(struct intel_crtc *crtc,
8079
			       struct intel_crtc_state *pipe_config)
Line 6655... Line 8080...
6655
			       struct intel_crtc_config *pipe_config)
8080
{
6656
{
8081
	struct drm_device *dev = crtc->base.dev;
-
 
8082
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8083
	int pipe = pipe_config->cpu_transcoder;
6657
	struct drm_device *dev = crtc->base.dev;
8084
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
6658
	struct drm_i915_private *dev_priv = dev->dev_private;
8085
	intel_clock_t clock;
6659
	int pipe = pipe_config->cpu_transcoder;
8086
	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
Line 6660... Line -...
6660
	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-
 
6661
	intel_clock_t clock;
-
 
6662
	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
-
 
6663
	int refclk = 100000;
8087
	int refclk = 100000;
6664
 
8088
 
Line 6665... Line 8089...
6665
	mutex_lock(&dev_priv->dpio_lock);
8089
	mutex_lock(&dev_priv->sb_lock);
6666
	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8090
	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6667
	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8091
	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6668
	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8092
	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6669
	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8093
	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6670
	mutex_unlock(&dev_priv->dpio_lock);
8094
	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
Line 6766... Line 8190...
6766
	else if (IS_VALLEYVIEW(dev))
8190
	else if (IS_VALLEYVIEW(dev))
6767
		vlv_crtc_clock_get(crtc, pipe_config);
8191
		vlv_crtc_clock_get(crtc, pipe_config);
6768
	else
8192
	else
6769
		i9xx_crtc_clock_get(crtc, pipe_config);
8193
		i9xx_crtc_clock_get(crtc, pipe_config);
Line -... Line 8194...
-
 
8194
 
-
 
8195
	/*
-
 
8196
	 * Normally the dotclock is filled in by the encoder .get_config()
-
 
8197
	 * but in case the pipe is enabled w/o any ports we need a sane
-
 
8198
	 * default.
-
 
8199
	 */
-
 
8200
	pipe_config->base.adjusted_mode.crtc_clock =
-
 
8201
		pipe_config->port_clock / pipe_config->pixel_multiplier;
6770
 
8202
 
6771
	return true;
8203
	return true;
Line 6772... Line 8204...
6772
}
8204
}
6773
 
8205
 
Line 7027... Line 8459...
7027
	struct drm_i915_private *dev_priv = dev->dev_private;
8459
	struct drm_i915_private *dev_priv = dev->dev_private;
7028
	uint32_t reg, tmp;
8460
	uint32_t reg, tmp;
Line 7029... Line 8461...
7029
 
8461
 
7030
	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8462
	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7031
		with_spread = true;
-
 
7032
	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8463
		with_spread = true;
7033
		 with_fdi, "LP PCH doesn't have FDI\n"))
8464
	if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
Line 7034... Line 8465...
7034
		with_fdi = false;
8465
		with_fdi = false;
Line 7035... Line 8466...
7035
 
8466
 
7036
	mutex_lock(&dev_priv->dpio_lock);
8467
	mutex_lock(&dev_priv->sb_lock);
7037
 
8468
 
7038
	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8469
	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
Line 7051... Line 8482...
7051
			lpt_reset_fdi_mphy(dev_priv);
8482
			lpt_reset_fdi_mphy(dev_priv);
7052
			lpt_program_fdi_mphy(dev_priv);
8483
			lpt_program_fdi_mphy(dev_priv);
7053
		}
8484
		}
7054
	}
8485
	}
Line 7055... Line -...
7055
 
-
 
7056
	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8486
 
7057
	       SBI_GEN0 : SBI_DBUFF0;
8487
	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
7058
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8488
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7059
	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8489
	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
Line 7060... Line 8490...
7060
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8490
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7061
 
8491
 
Line 7062... Line 8492...
7062
	mutex_unlock(&dev_priv->dpio_lock);
8492
	mutex_unlock(&dev_priv->sb_lock);
7063
}
8493
}
7064
 
8494
 
7065
/* Sequence to disable CLKOUT_DP */
8495
/* Sequence to disable CLKOUT_DP */
7066
static void lpt_disable_clkout_dp(struct drm_device *dev)
8496
static void lpt_disable_clkout_dp(struct drm_device *dev)
Line 7067... Line 8497...
7067
{
8497
{
Line 7068... Line -...
7068
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
7069
	uint32_t reg, tmp;
8498
	struct drm_i915_private *dev_priv = dev->dev_private;
7070
 
8499
	uint32_t reg, tmp;
7071
	mutex_lock(&dev_priv->dpio_lock);
8500
 
7072
 
8501
	mutex_lock(&dev_priv->sb_lock);
Line 7073... Line 8502...
7073
	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8502
 
Line 7085... Line 8514...
7085
		}
8514
		}
7086
		tmp |= SBI_SSCCTL_DISABLE;
8515
		tmp |= SBI_SSCCTL_DISABLE;
7087
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8516
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7088
	}
8517
	}
Line 7089... Line 8518...
7089
 
8518
 
7090
	mutex_unlock(&dev_priv->dpio_lock);
8519
	mutex_unlock(&dev_priv->sb_lock);
Line 7091... Line 8520...
7091
}
8520
}
7092
 
8521
 
7093
static void lpt_init_pch_refclk(struct drm_device *dev)
8522
static void lpt_init_pch_refclk(struct drm_device *dev)
Line 7120... Line 8549...
7120
		ironlake_init_pch_refclk(dev);
8549
		ironlake_init_pch_refclk(dev);
7121
	else if (HAS_PCH_LPT(dev))
8550
	else if (HAS_PCH_LPT(dev))
7122
		lpt_init_pch_refclk(dev);
8551
		lpt_init_pch_refclk(dev);
7123
}
8552
}
Line 7124... Line 8553...
7124
 
8553
 
7125
static int ironlake_get_refclk(struct drm_crtc *crtc)
8554
static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
7126
{
8555
{
7127
	struct drm_device *dev = crtc->dev;
8556
	struct drm_device *dev = crtc_state->base.crtc->dev;
-
 
8557
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8558
	struct drm_atomic_state *state = crtc_state->base.state;
-
 
8559
	struct drm_connector *connector;
7128
	struct drm_i915_private *dev_priv = dev->dev_private;
8560
	struct drm_connector_state *connector_state;
7129
	struct intel_encoder *encoder;
8561
	struct intel_encoder *encoder;
7130
	int num_connectors = 0;
8562
	int num_connectors = 0, i;
Line 7131... Line 8563...
7131
	bool is_lvds = false;
8563
	bool is_lvds = false;
7132
 
8564
 
7133
	for_each_intel_encoder(dev, encoder) {
8565
	for_each_connector_in_state(state, connector, connector_state, i) {
Line -... Line 8566...
-
 
8566
		if (connector_state->crtc != crtc_state->base.crtc)
-
 
8567
			continue;
7134
		if (encoder->new_crtc != to_intel_crtc(crtc))
8568
 
7135
			continue;
8569
		encoder = to_intel_encoder(connector_state->best_encoder);
7136
 
8570
 
7137
		switch (encoder->type) {
8571
		switch (encoder->type) {
7138
		case INTEL_OUTPUT_LVDS:
8572
		case INTEL_OUTPUT_LVDS:
Line 7160... Line 8594...
7160
	int pipe = intel_crtc->pipe;
8594
	int pipe = intel_crtc->pipe;
7161
	uint32_t val;
8595
	uint32_t val;
Line 7162... Line 8596...
7162
 
8596
 
Line 7163... Line 8597...
7163
	val = 0;
8597
	val = 0;
7164
 
8598
 
7165
	switch (intel_crtc->config.pipe_bpp) {
8599
	switch (intel_crtc->config->pipe_bpp) {
7166
	case 18:
8600
	case 18:
7167
		val |= PIPECONF_6BPC;
8601
		val |= PIPECONF_6BPC;
7168
		break;
8602
		break;
Line 7178... Line 8612...
7178
	default:
8612
	default:
7179
		/* Case prevented by intel_choose_pipe_bpp_dither. */
8613
		/* Case prevented by intel_choose_pipe_bpp_dither. */
7180
		BUG();
8614
		BUG();
7181
	}
8615
	}
Line 7182... Line 8616...
7182
 
8616
 
7183
	if (intel_crtc->config.dither)
8617
	if (intel_crtc->config->dither)
Line 7184... Line 8618...
7184
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8618
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7185
 
8619
 
7186
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8620
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7187
		val |= PIPECONF_INTERLACED_ILK;
8621
		val |= PIPECONF_INTERLACED_ILK;
Line 7188... Line 8622...
7188
	else
8622
	else
7189
		val |= PIPECONF_PROGRESSIVE;
8623
		val |= PIPECONF_PROGRESSIVE;
Line 7190... Line 8624...
7190
 
8624
 
7191
	if (intel_crtc->config.limited_color_range)
8625
	if (intel_crtc->config->limited_color_range)
7192
		val |= PIPECONF_COLOR_RANGE_SELECT;
8626
		val |= PIPECONF_COLOR_RANGE_SELECT;
Line 7215... Line 8649...
7215
	 * with these coeff/postoff values and adjust to get the best
8649
	 * with these coeff/postoff values and adjust to get the best
7216
	 * accuracy. Perhaps we even need to take the bpc value into
8650
	 * accuracy. Perhaps we even need to take the bpc value into
7217
	 * consideration.
8651
	 * consideration.
7218
	 */
8652
	 */
Line 7219... Line 8653...
7219
 
8653
 
7220
	if (intel_crtc->config.limited_color_range)
8654
	if (intel_crtc->config->limited_color_range)
Line 7221... Line 8655...
7221
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8655
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7222
 
8656
 
7223
	/*
8657
	/*
Line 7239... Line 8673...
7239
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8673
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
Line 7240... Line 8674...
7240
 
8674
 
7241
	if (INTEL_INFO(dev)->gen > 6) {
8675
	if (INTEL_INFO(dev)->gen > 6) {
Line 7242... Line 8676...
7242
		uint16_t postoff = 0;
8676
		uint16_t postoff = 0;
7243
 
8677
 
Line 7244... Line 8678...
7244
		if (intel_crtc->config.limited_color_range)
8678
		if (intel_crtc->config->limited_color_range)
7245
			postoff = (16 * (1 << 12) / 255) & 0x1fff;
8679
			postoff = (16 * (1 << 12) / 255) & 0x1fff;
7246
 
8680
 
Line 7247... Line 8681...
7247
		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8681
		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7248
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8682
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7249
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8683
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
Line 7250... Line 8684...
7250
 
8684
 
7251
		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8685
		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
Line 7252... Line 8686...
7252
	} else {
8686
	} else {
7253
		uint32_t mode = CSC_MODE_YUV_TO_RGB;
8687
		uint32_t mode = CSC_MODE_YUV_TO_RGB;
7254
 
8688
 
Line 7263... Line 8697...
7263
{
8697
{
7264
	struct drm_device *dev = crtc->dev;
8698
	struct drm_device *dev = crtc->dev;
7265
	struct drm_i915_private *dev_priv = dev->dev_private;
8699
	struct drm_i915_private *dev_priv = dev->dev_private;
7266
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8700
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7267
	enum pipe pipe = intel_crtc->pipe;
8701
	enum pipe pipe = intel_crtc->pipe;
7268
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8702
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7269
	uint32_t val;
8703
	uint32_t val;
Line 7270... Line 8704...
7270
 
8704
 
Line 7271... Line 8705...
7271
	val = 0;
8705
	val = 0;
7272
 
8706
 
Line 7273... Line 8707...
7273
	if (IS_HASWELL(dev) && intel_crtc->config.dither)
8707
	if (IS_HASWELL(dev) && intel_crtc->config->dither)
7274
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8708
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7275
 
8709
 
7276
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8710
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Line 7277... Line 8711...
7277
		val |= PIPECONF_INTERLACED_ILK;
8711
		val |= PIPECONF_INTERLACED_ILK;
Line 7285... Line 8719...
7285
	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8719
	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Line 7286... Line 8720...
7286
 
8720
 
7287
	if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8721
	if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Line 7288... Line 8722...
7288
		val = 0;
8722
		val = 0;
7289
 
8723
 
7290
		switch (intel_crtc->config.pipe_bpp) {
8724
		switch (intel_crtc->config->pipe_bpp) {
7291
		case 18:
8725
		case 18:
7292
			val |= PIPEMISC_DITHER_6_BPC;
8726
			val |= PIPEMISC_DITHER_6_BPC;
7293
			break;
8727
			break;
Line 7303... Line 8737...
7303
		default:
8737
		default:
7304
			/* Case prevented by pipe_config_set_bpp. */
8738
			/* Case prevented by pipe_config_set_bpp. */
7305
			BUG();
8739
			BUG();
7306
		}
8740
		}
Line 7307... Line 8741...
7307
 
8741
 
7308
		if (intel_crtc->config.dither)
8742
		if (intel_crtc->config->dither)
Line 7309... Line 8743...
7309
			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8743
			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7310
 
8744
 
7311
		I915_WRITE(PIPEMISC(pipe), val);
8745
		I915_WRITE(PIPEMISC(pipe), val);
Line 7312... Line 8746...
7312
	}
8746
	}
-
 
8747
}
7313
}
8748
 
7314
 
8749
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7315
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8750
				    struct intel_crtc_state *crtc_state,
7316
				    intel_clock_t *clock,
8751
				    intel_clock_t *clock,
7317
				    bool *has_reduced_clock,
8752
				    bool *has_reduced_clock,
7318
				    intel_clock_t *reduced_clock)
8753
				    intel_clock_t *reduced_clock)
7319
{
-
 
7320
	struct drm_device *dev = crtc->dev;
8754
{
7321
	struct drm_i915_private *dev_priv = dev->dev_private;
8755
	struct drm_device *dev = crtc->dev;
7322
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8756
	struct drm_i915_private *dev_priv = dev->dev_private;
7323
	int refclk;
-
 
7324
	const intel_limit_t *limit;
-
 
Line 7325... Line 8757...
7325
	bool ret, is_lvds = false;
8757
	int refclk;
Line 7326... Line 8758...
7326
 
8758
	const intel_limit_t *limit;
7327
	is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
8759
	bool ret;
7328
 
8760
 
7329
	refclk = ironlake_get_refclk(crtc);
8761
	refclk = ironlake_get_refclk(crtc_state);
7330
 
8762
 
7331
	/*
8763
	/*
7332
	 * Returns a set of divisors for the desired target clock with the given
8764
	 * Returns a set of divisors for the desired target clock with the given
7333
	 * refclk, or FALSE.  The returned values represent the clock equation:
8765
	 * refclk, or FALSE.  The returned values represent the clock equation:
7334
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8766
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7335
	 */
8767
	 */
7336
	limit = intel_limit(intel_crtc, refclk);
8768
	limit = intel_limit(crtc_state, refclk);
Line 7337... Line -...
7337
	ret = dev_priv->display.find_dpll(limit, intel_crtc,
-
 
7338
					  intel_crtc->new_config->port_clock,
-
 
7339
					  refclk, NULL, clock);
-
 
7340
	if (!ret)
-
 
7341
		return false;
-
 
7342
 
-
 
7343
	if (is_lvds && dev_priv->lvds_downclock_avail) {
-
 
7344
		/*
-
 
7345
		 * Ensure we match the reduced clock's P to the target clock.
-
 
7346
		 * If the clocks don't match, we can't switch the display clock
-
 
7347
		 * by using the FP0/FP1. In such case we will disable the LVDS
-
 
7348
		 * downclock feature.
-
 
7349
		*/
-
 
7350
		*has_reduced_clock =
-
 
7351
			dev_priv->display.find_dpll(limit, intel_crtc,
8769
	ret = dev_priv->display.find_dpll(limit, crtc_state,
7352
						     dev_priv->lvds_downclock,
8770
					  crtc_state->port_clock,
Line 7353... Line 8771...
7353
						    refclk, clock,
8771
					  refclk, NULL, clock);
7354
						     reduced_clock);
8772
	if (!ret)
Line 7372... Line 8790...
7372
{
8790
{
7373
	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8791
	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7374
}
8792
}
Line 7375... Line 8793...
7375
 
8793
 
-
 
8794
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7376
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8795
				      struct intel_crtc_state *crtc_state,
7377
				      u32 *fp,
8796
				      u32 *fp,
7378
				      intel_clock_t *reduced_clock, u32 *fp2)
8797
				      intel_clock_t *reduced_clock, u32 *fp2)
7379
{
8798
{
7380
	struct drm_crtc *crtc = &intel_crtc->base;
8799
	struct drm_crtc *crtc = &intel_crtc->base;
7381
	struct drm_device *dev = crtc->dev;
8800
	struct drm_device *dev = crtc->dev;
-
 
8801
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8802
	struct drm_atomic_state *state = crtc_state->base.state;
-
 
8803
	struct drm_connector *connector;
7382
	struct drm_i915_private *dev_priv = dev->dev_private;
8804
	struct drm_connector_state *connector_state;
7383
	struct intel_encoder *intel_encoder;
8805
	struct intel_encoder *encoder;
7384
	uint32_t dpll;
8806
	uint32_t dpll;
7385
	int factor, num_connectors = 0;
8807
	int factor, num_connectors = 0, i;
Line 7386... Line 8808...
7386
	bool is_lvds = false, is_sdvo = false;
8808
	bool is_lvds = false, is_sdvo = false;
7387
 
8809
 
7388
	for_each_intel_encoder(dev, intel_encoder) {
8810
	for_each_connector_in_state(state, connector, connector_state, i) {
Line -... Line 8811...
-
 
8811
		if (connector_state->crtc != crtc_state->base.crtc)
-
 
8812
			continue;
7389
		if (intel_encoder->new_crtc != to_intel_crtc(crtc))
8813
 
7390
			continue;
8814
		encoder = to_intel_encoder(connector_state->best_encoder);
7391
 
8815
 
7392
		switch (intel_encoder->type) {
8816
		switch (encoder->type) {
7393
		case INTEL_OUTPUT_LVDS:
8817
		case INTEL_OUTPUT_LVDS:
7394
			is_lvds = true;
8818
			is_lvds = true;
Line 7409... Line 8833...
7409
    if (is_lvds) {
8833
	if (is_lvds) {
7410
        if ((intel_panel_use_ssc(dev_priv) &&
8834
		if ((intel_panel_use_ssc(dev_priv) &&
7411
		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
8835
		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
7412
		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8836
		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7413
            factor = 25;
8837
			factor = 25;
7414
	} else if (intel_crtc->new_config->sdvo_tv_clock)
8838
	} else if (crtc_state->sdvo_tv_clock)
7415
        factor = 20;
8839
		factor = 20;
Line 7416... Line 8840...
7416
 
8840
 
7417
	if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
8841
	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
Line 7418... Line 8842...
7418
		*fp |= FP_CB_TUNE;
8842
		*fp |= FP_CB_TUNE;
7419
 
8843
 
Line 7425... Line 8849...
7425
    if (is_lvds)
8849
	if (is_lvds)
7426
        dpll |= DPLLB_MODE_LVDS;
8850
		dpll |= DPLLB_MODE_LVDS;
7427
    else
8851
	else
7428
        dpll |= DPLLB_MODE_DAC_SERIAL;
8852
		dpll |= DPLLB_MODE_DAC_SERIAL;
Line 7429... Line 8853...
7429
 
8853
 
7430
	dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
8854
	dpll |= (crtc_state->pixel_multiplier - 1)
Line 7431... Line 8855...
7431
				<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8855
		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7432
 
8856
 
7433
	if (is_sdvo)
8857
	if (is_sdvo)
7434
		dpll |= DPLL_SDVO_HIGH_SPEED;
8858
		dpll |= DPLL_SDVO_HIGH_SPEED;
Line 7435... Line 8859...
7435
	if (intel_crtc->new_config->has_dp_encoder)
8859
	if (crtc_state->has_dp_encoder)
7436
		dpll |= DPLL_SDVO_HIGH_SPEED;
8860
		dpll |= DPLL_SDVO_HIGH_SPEED;
7437
 
8861
 
7438
    /* compute bitmask from p1 value */
8862
	/* compute bitmask from p1 value */
Line 7439... Line 8863...
7439
	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8863
	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7440
    /* also FPA1 */
8864
	/* also FPA1 */
7441
	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8865
	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7442
 
8866
 
7443
	switch (intel_crtc->new_config->dpll.p2) {
8867
	switch (crtc_state->dpll.p2) {
7444
    case 5:
8868
	case 5:
Line 7461... Line 8885...
7461
        dpll |= PLL_REF_INPUT_DREFCLK;
8885
		dpll |= PLL_REF_INPUT_DREFCLK;
Line 7462... Line 8886...
7462
 
8886
 
7463
	return dpll | DPLL_VCO_ENABLE;
8887
	return dpll | DPLL_VCO_ENABLE;
Line 7464... Line 8888...
7464
}
8888
}
-
 
8889
 
7465
 
8890
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7466
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
8891
				       struct intel_crtc_state *crtc_state)
7467
{
8892
{
7468
	struct drm_device *dev = crtc->base.dev;
8893
	struct drm_device *dev = crtc->base.dev;
7469
	intel_clock_t clock, reduced_clock;
8894
	intel_clock_t clock, reduced_clock;
7470
	u32 dpll = 0, fp = 0, fp2 = 0;
8895
	u32 dpll = 0, fp = 0, fp2 = 0;
7471
	bool ok, has_reduced_clock = false;
8896
	bool ok, has_reduced_clock = false;
Line -... Line 8897...
-
 
8897
	bool is_lvds = false;
-
 
8898
	struct intel_shared_dpll *pll;
-
 
8899
 
7472
	bool is_lvds = false;
8900
	memset(&crtc_state->dpll_hw_state, 0,
Line 7473... Line 8901...
7473
	struct intel_shared_dpll *pll;
8901
	       sizeof(crtc_state->dpll_hw_state));
7474
 
8902
 
Line 7475... Line 8903...
7475
	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8903
	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7476
 
8904
 
7477
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8905
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7478
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8906
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7479
 
8907
 
7480
	ok = ironlake_compute_clocks(&crtc->base, &clock,
8908
	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7481
				     &has_reduced_clock, &reduced_clock);
8909
				     &has_reduced_clock, &reduced_clock);
7482
	if (!ok && !crtc->new_config->clock_set) {
8910
	if (!ok && !crtc_state->clock_set) {
7483
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
8911
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
7484
		return -EINVAL;
8912
		return -EINVAL;
7485
	}
8913
	}
7486
	/* Compat-code for transition, will disappear. */
8914
	/* Compat-code for transition, will disappear. */
7487
	if (!crtc->new_config->clock_set) {
8915
	if (!crtc_state->clock_set) {
7488
		crtc->new_config->dpll.n = clock.n;
8916
		crtc_state->dpll.n = clock.n;
Line 7489... Line 8917...
7489
		crtc->new_config->dpll.m1 = clock.m1;
8917
		crtc_state->dpll.m1 = clock.m1;
7490
		crtc->new_config->dpll.m2 = clock.m2;
8918
		crtc_state->dpll.m2 = clock.m2;
7491
		crtc->new_config->dpll.p1 = clock.p1;
8919
		crtc_state->dpll.p1 = clock.p1;
7492
		crtc->new_config->dpll.p2 = clock.p2;
8920
		crtc_state->dpll.p2 = clock.p2;
7493
	}
8921
	}
Line 7494... Line 8922...
7494
 
8922
 
7495
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8923
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7496
	if (crtc->new_config->has_pch_encoder) {
8924
	if (crtc_state->has_pch_encoder) {
Line 7497... Line 8925...
7497
		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
8925
		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7498
	if (has_reduced_clock)
8926
		if (has_reduced_clock)
7499
			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8927
			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7500
 
8928
 
7501
		dpll = ironlake_compute_dpll(crtc,
8929
		dpll = ironlake_compute_dpll(crtc, crtc_state,
7502
					     &fp, &reduced_clock,
8930
					     &fp, &reduced_clock,
Line 7503... Line 8931...
7503
					     has_reduced_clock ? &fp2 : NULL);
8931
					     has_reduced_clock ? &fp2 : NULL);
7504
 
8932
 
7505
		crtc->new_config->dpll_hw_state.dpll = dpll;
8933
		crtc_state->dpll_hw_state.dpll = dpll;
7506
		crtc->new_config->dpll_hw_state.fp0 = fp;
8934
		crtc_state->dpll_hw_state.fp0 = fp;
7507
		if (has_reduced_clock)
8935
		if (has_reduced_clock)
7508
			crtc->new_config->dpll_hw_state.fp1 = fp2;
8936
			crtc_state->dpll_hw_state.fp1 = fp2;
7509
		else
8937
		else
Line 7510... Line 8938...
7510
			crtc->new_config->dpll_hw_state.fp1 = fp;
8938
			crtc_state->dpll_hw_state.fp1 = fp;
7511
 
8939
 
7512
		pll = intel_get_shared_dpll(crtc);
8940
		pll = intel_get_shared_dpll(crtc, crtc_state);
7513
		if (pll == NULL) {
8941
		if (pll == NULL) {
Line 7514... Line 8942...
7514
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8942
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Line 7561... Line 8989...
7561
		/* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8989
		/* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7562
		 * gen < 8) and if DRRS is supported (to make sure the
8990
		 * gen < 8) and if DRRS is supported (to make sure the
7563
		 * registers are not unnecessarily read).
8991
		 * registers are not unnecessarily read).
7564
		 */
8992
		 */
7565
		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8993
		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7566
			crtc->config.has_drrs) {
8994
			crtc->config->has_drrs) {
7567
			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8995
			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7568
			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
8996
			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
7569
			m2_n2->gmch_m =	I915_READ(PIPE_DATA_M2(transcoder))
8997
			m2_n2->gmch_m =	I915_READ(PIPE_DATA_M2(transcoder))
7570
					& ~TU_SIZE_MASK;
8998
					& ~TU_SIZE_MASK;
7571
			m2_n2->gmch_n =	I915_READ(PIPE_DATA_N2(transcoder));
8999
			m2_n2->gmch_n =	I915_READ(PIPE_DATA_N2(transcoder));
Line 7582... Line 9010...
7582
			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9010
			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7583
	}
9011
	}
7584
}
9012
}
Line 7585... Line 9013...
7585
 
9013
 
7586
void intel_dp_get_m_n(struct intel_crtc *crtc,
9014
void intel_dp_get_m_n(struct intel_crtc *crtc,
7587
		      struct intel_crtc_config *pipe_config)
9015
		      struct intel_crtc_state *pipe_config)
7588
{
9016
{
7589
	if (crtc->config.has_pch_encoder)
9017
	if (pipe_config->has_pch_encoder)
7590
		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9018
		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7591
	else
9019
	else
7592
		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9020
		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7593
					     &pipe_config->dp_m_n,
9021
					     &pipe_config->dp_m_n,
7594
					     &pipe_config->dp_m2_n2);
9022
					     &pipe_config->dp_m2_n2);
Line 7595... Line 9023...
7595
}
9023
}
7596
 
9024
 
7597
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9025
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7598
					struct intel_crtc_config *pipe_config)
9026
					struct intel_crtc_state *pipe_config)
7599
{
9027
{
7600
	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9028
	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Line 7601... Line 9029...
7601
				     &pipe_config->fdi_m_n, NULL);
9029
				     &pipe_config->fdi_m_n, NULL);
7602
}
9030
}
7603
 
9031
 
7604
static void skylake_get_pfit_config(struct intel_crtc *crtc,
9032
static void skylake_get_pfit_config(struct intel_crtc *crtc,
7605
				    struct intel_crtc_config *pipe_config)
9033
				    struct intel_crtc_state *pipe_config)
-
 
9034
{
7606
{
9035
	struct drm_device *dev = crtc->base.dev;
7607
	struct drm_device *dev = crtc->base.dev;
-
 
7608
	struct drm_i915_private *dev_priv = dev->dev_private;
9036
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
9037
	struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
Line -... Line 9038...
-
 
9038
	uint32_t ps_ctrl = 0;
7609
	uint32_t tmp;
9039
	int id = -1;
-
 
9040
	int i;
-
 
9041
 
-
 
9042
	/* find scaler attached to this pipe */
7610
 
9043
	for (i = 0; i < crtc->num_scalers; i++) {
7611
	tmp = I915_READ(PS_CTL(crtc->pipe));
9044
		ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
7612
 
9045
		if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
-
 
9046
			id = i;
-
 
9047
			pipe_config->pch_pfit.enabled = true;
-
 
9048
			pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
-
 
9049
			pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
-
 
9050
			break;
-
 
9051
		}
-
 
9052
	}
-
 
9053
 
-
 
9054
	scaler_state->scaler_id = id;
-
 
9055
	if (id >= 0) {
-
 
9056
		scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
-
 
9057
	} else {
-
 
9058
		scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
-
 
9059
	}
-
 
9060
}
-
 
9061
 
-
 
9062
static void
-
 
9063
skylake_get_initial_plane_config(struct intel_crtc *crtc,
-
 
9064
				 struct intel_initial_plane_config *plane_config)
-
 
9065
{
-
 
9066
	struct drm_device *dev = crtc->base.dev;
-
 
9067
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
9068
	u32 val, base, offset, stride_mult, tiling;
-
 
9069
	int pipe = crtc->pipe;
-
 
9070
	int fourcc, pixel_format;
-
 
9071
	unsigned int aligned_height;
-
 
9072
	struct drm_framebuffer *fb;
-
 
9073
	struct intel_framebuffer *intel_fb;
-
 
9074
 
-
 
9075
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-
 
9076
	if (!intel_fb) {
-
 
9077
		DRM_DEBUG_KMS("failed to alloc fb\n");
-
 
9078
		return;
-
 
9079
	}
-
 
9080
 
-
 
9081
	fb = &intel_fb->base;
-
 
9082
 
-
 
9083
	val = I915_READ(PLANE_CTL(pipe, 0));
-
 
9084
	if (!(val & PLANE_CTL_ENABLE))
-
 
9085
		goto error;
-
 
9086
 
-
 
9087
	pixel_format = val & PLANE_CTL_FORMAT_MASK;
-
 
9088
	fourcc = skl_format_to_fourcc(pixel_format,
-
 
9089
				      val & PLANE_CTL_ORDER_RGBX,
-
 
9090
				      val & PLANE_CTL_ALPHA_MASK);
-
 
9091
	fb->pixel_format = fourcc;
-
 
9092
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
-
 
9093
 
-
 
9094
	tiling = val & PLANE_CTL_TILED_MASK;
-
 
9095
	switch (tiling) {
-
 
9096
	case PLANE_CTL_TILED_LINEAR:
-
 
9097
		fb->modifier[0] = DRM_FORMAT_MOD_NONE;
-
 
9098
		break;
-
 
9099
	case PLANE_CTL_TILED_X:
-
 
9100
		plane_config->tiling = I915_TILING_X;
-
 
9101
		fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
-
 
9102
		break;
-
 
9103
	case PLANE_CTL_TILED_Y:
-
 
9104
		fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
-
 
9105
		break;
-
 
9106
	case PLANE_CTL_TILED_YF:
-
 
9107
		fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7613
	if (tmp & PS_ENABLE) {
9108
		break;
-
 
9109
	default:
-
 
9110
		MISSING_CASE(tiling);
-
 
9111
		goto error;
-
 
9112
	}
-
 
9113
 
-
 
9114
	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
-
 
9115
	plane_config->base = base;
-
 
9116
 
-
 
9117
	offset = I915_READ(PLANE_OFFSET(pipe, 0));
-
 
9118
 
-
 
9119
	val = I915_READ(PLANE_SIZE(pipe, 0));
-
 
9120
	fb->height = ((val >> 16) & 0xfff) + 1;
-
 
9121
	fb->width = ((val >> 0) & 0x1fff) + 1;
-
 
9122
 
-
 
9123
	val = I915_READ(PLANE_STRIDE(pipe, 0));
-
 
9124
	stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
-
 
9125
						fb->pixel_format);
-
 
9126
//   fb->pitches[0] = (val & 0x3ff) * stride_mult;
-
 
9127
    fb->pitches[0] = 2560*4;
-
 
9128
 
-
 
9129
	aligned_height = intel_fb_align_height(dev, fb->height,
-
 
9130
					       fb->pixel_format,
-
 
9131
					       fb->modifier[0]);
-
 
9132
 
-
 
9133
//   plane_config->size = fb->pitches[0] * aligned_height;
-
 
9134
    plane_config->size = i915_fbsize*1024*1024;
-
 
9135
 
-
 
9136
	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
-
 
9137
		      pipe_name(pipe), fb->width, fb->height,
-
 
9138
		      fb->bits_per_pixel, base, fb->pitches[0],
-
 
9139
		      plane_config->size);
-
 
9140
 
-
 
9141
	plane_config->fb = intel_fb;
7614
		pipe_config->pch_pfit.enabled = true;
9142
	return;
Line 7615... Line 9143...
7615
		pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
9143
 
7616
		pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
9144
error:
7617
	}
9145
	kfree(fb);
7618
}
9146
}
7619
 
9147
 
7620
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9148
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
Line 7639... Line 9167...
7639
				PF_PIPE_SEL_IVB(crtc->pipe));
9167
				PF_PIPE_SEL_IVB(crtc->pipe));
7640
		}
9168
		}
7641
	}
9169
	}
7642
}
9170
}
Line -... Line 9171...
-
 
9171
 
7643
 
9172
static void
7644
static void ironlake_get_plane_config(struct intel_crtc *crtc,
9173
ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7645
				      struct intel_plane_config *plane_config)
9174
				  struct intel_initial_plane_config *plane_config)
7646
{
9175
{
7647
	struct drm_device *dev = crtc->base.dev;
9176
	struct drm_device *dev = crtc->base.dev;
7648
	struct drm_i915_private *dev_priv = dev->dev_private;
9177
	struct drm_i915_private *dev_priv = dev->dev_private;
7649
	u32 val, base, offset;
9178
	u32 val, base, offset;
7650
	int pipe = crtc->pipe, plane = crtc->plane;
9179
	int pipe = crtc->pipe;
7651
	int fourcc, pixel_format;
9180
	int fourcc, pixel_format;
-
 
9181
	unsigned int aligned_height;
-
 
9182
	struct drm_framebuffer *fb;
Line -... Line 9183...
-
 
9183
	struct intel_framebuffer *intel_fb;
-
 
9184
 
-
 
9185
	val = I915_READ(DSPCNTR(pipe));
-
 
9186
	if (!(val & DISPLAY_PLANE_ENABLE))
7652
	int aligned_height;
9187
		return;
7653
 
9188
 
7654
	crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
9189
	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7655
	if (!crtc->base.primary->fb) {
9190
	if (!intel_fb) {
7656
		DRM_DEBUG_KMS("failed to alloc fb\n");
9191
		DRM_DEBUG_KMS("failed to alloc fb\n");
Line 7657... Line 9192...
7657
		return;
9192
		return;
Line 7658... Line 9193...
7658
	}
9193
	}
7659
 
9194
 
7660
	val = I915_READ(DSPCNTR(plane));
9195
	fb = &intel_fb->base;
-
 
9196
 
-
 
9197
	if (INTEL_INFO(dev)->gen >= 4) {
-
 
9198
		if (val & DISPPLANE_TILED) {
Line 7661... Line 9199...
7661
 
9199
			plane_config->tiling = I915_TILING_X;
7662
	if (INTEL_INFO(dev)->gen >= 4)
9200
			fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7663
		if (val & DISPPLANE_TILED)
9201
		}
7664
			plane_config->tiled = true;
-
 
7665
 
9202
	}
Line 7666... Line 9203...
7666
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9203
 
7667
	fourcc = intel_format_to_fourcc(pixel_format);
9204
	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7668
	crtc->base.primary->fb->pixel_format = fourcc;
9205
	fourcc = i9xx_format_to_fourcc(pixel_format);
7669
	crtc->base.primary->fb->bits_per_pixel =
9206
	fb->pixel_format = fourcc;
7670
		drm_format_plane_cpp(fourcc, 0) * 8;
9207
	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7671
 
9208
 
7672
	base = I915_READ(DSPSURF(plane)) & 0xfffff000;
9209
	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7673
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9210
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7674
		offset = I915_READ(DSPOFFSET(plane));
9211
		offset = I915_READ(DSPOFFSET(pipe));
7675
	} else {
9212
	} else {
Line 7676... Line 9213...
7676
		if (plane_config->tiled)
9213
		if (plane_config->tiling)
7677
			offset = I915_READ(DSPTILEOFF(plane));
9214
			offset = I915_READ(DSPTILEOFF(pipe));
7678
		else
9215
		else
Line 7679... Line 9216...
7679
			offset = I915_READ(DSPLINOFF(plane));
9216
			offset = I915_READ(DSPLINOFF(pipe));
7680
	}
9217
	}
7681
	plane_config->base = base;
-
 
7682
 
-
 
7683
	val = I915_READ(PIPESRC(pipe));
9218
	plane_config->base = base;
7684
	crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
-
 
7685
	crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
-
 
7686
 
-
 
Line 7687... Line 9219...
7687
	val = I915_READ(DSPSTRIDE(pipe));
9219
 
7688
	crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
9220
	val = I915_READ(PIPESRC(pipe));
7689
 
9221
	fb->width = ((val >> 16) & 0xfff) + 1;
-
 
9222
	fb->height = ((val >> 0) & 0xfff) + 1;
-
 
9223
 
-
 
9224
	val = I915_READ(DSPSTRIDE(pipe));
-
 
9225
//   fb->pitches[0] = val & 0xffffffc0;
-
 
9226
    fb->pitches[0] = 2560*4;
7690
	aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
9227
 
7691
					    plane_config->tiled);
9228
	aligned_height = intel_fb_align_height(dev, fb->height,
7692
 
9229
					       fb->pixel_format,
-
 
9230
					       fb->modifier[0]);
-
 
9231
 
7693
	plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
9232
//   plane_config->size = fb->pitches[0] * aligned_height;
Line 7694... Line 9233...
7694
					aligned_height);
9233
    plane_config->size = i915_fbsize*1024*1024;
7695
 
9234
 
7696
	DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9235
	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7697
		      pipe, plane, crtc->base.primary->fb->width,
9236
		      pipe_name(pipe), fb->width, fb->height,
7698
		      crtc->base.primary->fb->height,
9237
		      fb->bits_per_pixel, base, fb->pitches[0],
7699
		      crtc->base.primary->fb->bits_per_pixel, base,
9238
		      plane_config->size);
Line 7787... Line 9326...
7787
{
9326
{
7788
	struct drm_device *dev = dev_priv->dev;
9327
	struct drm_device *dev = dev_priv->dev;
7789
	struct intel_crtc *crtc;
9328
	struct intel_crtc *crtc;
Line 7790... Line 9329...
7790
 
9329
 
7791
	for_each_intel_crtc(dev, crtc)
9330
	for_each_intel_crtc(dev, crtc)
7792
		WARN(crtc->active, "CRTC for pipe %c enabled\n",
9331
		I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
Line 7793... Line 9332...
7793
		     pipe_name(crtc->pipe));
9332
		     pipe_name(crtc->pipe));
7794
 
9333
 
7795
	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9334
	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7796
	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9335
	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7797
	WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9336
	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7798
	WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9337
	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7799
	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9338
	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7800
	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9339
	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7801
	     "CPU PWM1 enabled\n");
9340
	     "CPU PWM1 enabled\n");
7802
	if (IS_HASWELL(dev))
9341
	if (IS_HASWELL(dev))
7803
	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9342
		I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7804
	     "CPU PWM2 enabled\n");
9343
		     "CPU PWM2 enabled\n");
7805
	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9344
	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7806
	     "PCH PWM1 enabled\n");
9345
	     "PCH PWM1 enabled\n");
7807
	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9346
	I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
Line 7808... Line 9347...
7808
	     "Utility pin enabled\n");
9347
	     "Utility pin enabled\n");
7809
	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9348
	I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7810
 
9349
 
7811
	/*
9350
	/*
7812
	 * In theory we can still leave IRQs enabled, as long as only the HPD
9351
	 * In theory we can still leave IRQs enabled, as long as only the HPD
7813
	 * interrupts remain enabled. We used to check for that, but since it's
9352
	 * interrupts remain enabled. We used to check for that, but since it's
7814
	 * gen-specific and since we only disable LCPLL after we fully disable
9353
	 * gen-specific and since we only disable LCPLL after we fully disable
7815
	 * the interrupts, the check below should be enough.
9354
	 * the interrupts, the check below should be enough.
Line 7816... Line 9355...
7816
	 */
9355
	 */
7817
	WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9356
	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7818
}
9357
}
Line 7910... Line 9449...
7910
		return;
9449
		return;
Line 7911... Line 9450...
7911
 
9450
 
7912
	/*
9451
	/*
7913
	 * Make sure we're not on PC8 state before disabling PC8, otherwise
9452
	 * Make sure we're not on PC8 state before disabling PC8, otherwise
7914
	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
-
 
7915
	 *
-
 
7916
	 * The other problem is that hsw_restore_lcpll() is called as part of
-
 
7917
	 * the runtime PM resume sequence, so we can't just call
-
 
7918
	 * gen6_gt_force_wake_get() because that function calls
-
 
7919
	 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
-
 
7920
	 * while we are on the resume sequence. So to solve this problem we have
-
 
7921
	 * to call special forcewake code that doesn't touch runtime PM and
-
 
7922
	 * doesn't enable the forcewake delayed work.
9453
	 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7923
	 */
-
 
7924
	spin_lock_irq(&dev_priv->uncore.lock);
-
 
7925
	if (dev_priv->uncore.forcewake_count++ == 0)
9454
	 */
7926
		dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
-
 
Line 7927... Line 9455...
7927
	spin_unlock_irq(&dev_priv->uncore.lock);
9455
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7928
 
9456
 
7929
	if (val & LCPLL_POWER_DOWN_ALLOW) {
9457
	if (val & LCPLL_POWER_DOWN_ALLOW) {
7930
		val &= ~LCPLL_POWER_DOWN_ALLOW;
9458
		val &= ~LCPLL_POWER_DOWN_ALLOW;
Line 7952... Line 9480...
7952
		if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9480
		if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7953
					LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9481
					LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7954
			DRM_ERROR("Switching back to LCPLL failed\n");
9482
			DRM_ERROR("Switching back to LCPLL failed\n");
7955
	}
9483
	}
Line 7956... Line -...
7956
 
-
 
7957
	/* See the big comment above. */
-
 
7958
	spin_lock_irq(&dev_priv->uncore.lock);
-
 
7959
	if (--dev_priv->uncore.forcewake_count == 0)
9484
 
7960
		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
9485
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7961
	spin_unlock_irq(&dev_priv->uncore.lock);
9486
	intel_update_cdclk(dev_priv->dev);
Line 7962... Line 9487...
7962
}
9487
}
7963
 
9488
 
7964
/*
9489
/*
Line 7989... Line 9514...
7989
	struct drm_device *dev = dev_priv->dev;
9514
	struct drm_device *dev = dev_priv->dev;
7990
	uint32_t val;
9515
	uint32_t val;
Line 7991... Line 9516...
7991
 
9516
 
Line 7992... Line 9517...
7992
	DRM_DEBUG_KMS("Enabling package C8+\n");
9517
	DRM_DEBUG_KMS("Enabling package C8+\n");
7993
 
9518
 
7994
	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9519
	if (HAS_PCH_LPT_LP(dev)) {
7995
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
9520
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
7996
		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9521
		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
Line 8009... Line 9534...
8009
	DRM_DEBUG_KMS("Disabling package C8+\n");
9534
	DRM_DEBUG_KMS("Disabling package C8+\n");
Line 8010... Line 9535...
8010
 
9535
 
8011
	hsw_restore_lcpll(dev_priv);
9536
	hsw_restore_lcpll(dev_priv);
Line 8012... Line 9537...
8012
	lpt_init_pch_refclk(dev);
9537
	lpt_init_pch_refclk(dev);
8013
 
9538
 
8014
	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9539
	if (HAS_PCH_LPT_LP(dev)) {
8015
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
9540
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
8016
		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9541
		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
Line 8017... Line 9542...
8017
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9542
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8018
	}
9543
	}
Line -... Line 9544...
-
 
9544
 
-
 
9545
	intel_prepare_ddi(dev);
-
 
9546
}
-
 
9547
 
-
 
9548
static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
-
 
9549
{
-
 
9550
	struct drm_device *dev = old_state->dev;
-
 
9551
	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
-
 
9552
 
-
 
9553
	broxton_set_cdclk(dev, req_cdclk);
-
 
9554
}
-
 
9555
 
-
 
9556
/* compute the max rate for new configuration */
-
 
9557
static int ilk_max_pixel_rate(struct drm_atomic_state *state)
-
 
9558
{
-
 
9559
	struct intel_crtc *intel_crtc;
-
 
9560
	struct intel_crtc_state *crtc_state;
-
 
9561
	int max_pixel_rate = 0;
-
 
9562
 
-
 
9563
	for_each_intel_crtc(state->dev, intel_crtc) {
-
 
9564
		int pixel_rate;
-
 
9565
 
-
 
9566
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-
 
9567
		if (IS_ERR(crtc_state))
-
 
9568
			return PTR_ERR(crtc_state);
-
 
9569
 
-
 
9570
		if (!crtc_state->base.enable)
-
 
9571
			continue;
-
 
9572
 
-
 
9573
		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
-
 
9574
 
-
 
9575
		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-
 
9576
		if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
-
 
9577
			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
-
 
9578
 
-
 
9579
		max_pixel_rate = max(max_pixel_rate, pixel_rate);
-
 
9580
	}
-
 
9581
 
-
 
9582
	return max_pixel_rate;
-
 
9583
}
-
 
9584
 
-
 
9585
static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
-
 
9586
{
-
 
9587
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
9588
	uint32_t val, data;
-
 
9589
	int ret;
-
 
9590
 
-
 
9591
	if (WARN((I915_READ(LCPLL_CTL) &
-
 
9592
		  (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
-
 
9593
		   LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
-
 
9594
		   LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
-
 
9595
		   LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
-
 
9596
		 "trying to change cdclk frequency with cdclk not enabled\n"))
-
 
9597
		return;
-
 
9598
 
-
 
9599
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
9600
	ret = sandybridge_pcode_write(dev_priv,
-
 
9601
				      BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
-
 
9602
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
9603
	if (ret) {
-
 
9604
		DRM_ERROR("failed to inform pcode about cdclk change\n");
-
 
9605
		return;
-
 
9606
	}
-
 
9607
 
-
 
9608
	val = I915_READ(LCPLL_CTL);
-
 
9609
	val |= LCPLL_CD_SOURCE_FCLK;
-
 
9610
	I915_WRITE(LCPLL_CTL, val);
-
 
9611
 
-
 
9612
	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
-
 
9613
			       LCPLL_CD_SOURCE_FCLK_DONE, 1))
-
 
9614
		DRM_ERROR("Switching to FCLK failed\n");
-
 
9615
 
-
 
9616
	val = I915_READ(LCPLL_CTL);
-
 
9617
	val &= ~LCPLL_CLK_FREQ_MASK;
-
 
9618
 
-
 
9619
	switch (cdclk) {
-
 
9620
	case 450000:
-
 
9621
		val |= LCPLL_CLK_FREQ_450;
-
 
9622
		data = 0;
-
 
9623
		break;
-
 
9624
	case 540000:
-
 
9625
		val |= LCPLL_CLK_FREQ_54O_BDW;
-
 
9626
		data = 1;
-
 
9627
		break;
-
 
9628
	case 337500:
-
 
9629
		val |= LCPLL_CLK_FREQ_337_5_BDW;
-
 
9630
		data = 2;
-
 
9631
		break;
-
 
9632
	case 675000:
-
 
9633
		val |= LCPLL_CLK_FREQ_675_BDW;
-
 
9634
		data = 3;
-
 
9635
		break;
-
 
9636
	default:
-
 
9637
		WARN(1, "invalid cdclk frequency\n");
-
 
9638
		return;
-
 
9639
	}
-
 
9640
 
-
 
9641
	I915_WRITE(LCPLL_CTL, val);
-
 
9642
 
-
 
9643
	val = I915_READ(LCPLL_CTL);
-
 
9644
	val &= ~LCPLL_CD_SOURCE_FCLK;
-
 
9645
	I915_WRITE(LCPLL_CTL, val);
-
 
9646
 
-
 
9647
	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
-
 
9648
				LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
-
 
9649
		DRM_ERROR("Switching back to LCPLL failed\n");
-
 
9650
 
-
 
9651
	mutex_lock(&dev_priv->rps.hw_lock);
-
 
9652
	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
-
 
9653
	mutex_unlock(&dev_priv->rps.hw_lock);
-
 
9654
 
-
 
9655
	intel_update_cdclk(dev);
-
 
9656
 
-
 
9657
	WARN(cdclk != dev_priv->cdclk_freq,
8019
 
9658
	     "cdclk requested %d kHz but got %d kHz\n",
8020
	intel_prepare_ddi(dev);
9659
	     cdclk, dev_priv->cdclk_freq);
-
 
9660
}
-
 
9661
 
-
 
9662
static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
-
 
9663
{
-
 
9664
	struct drm_i915_private *dev_priv = to_i915(state->dev);
-
 
9665
	int max_pixclk = ilk_max_pixel_rate(state);
-
 
9666
	int cdclk;
-
 
9667
 
-
 
9668
	/*
-
 
9669
	 * FIXME should also account for plane ratio
-
 
9670
	 * once 64bpp pixel formats are supported.
-
 
9671
	 */
-
 
9672
	if (max_pixclk > 540000)
-
 
9673
		cdclk = 675000;
-
 
9674
	else if (max_pixclk > 450000)
-
 
9675
		cdclk = 540000;
-
 
9676
	else if (max_pixclk > 337500)
-
 
9677
		cdclk = 450000;
-
 
9678
	else
-
 
9679
		cdclk = 337500;
-
 
9680
 
-
 
9681
	/*
-
 
9682
	 * FIXME move the cdclk caclulation to
-
 
9683
	 * compute_config() so we can fail gracegully.
-
 
9684
	 */
-
 
9685
	if (cdclk > dev_priv->max_cdclk_freq) {
-
 
9686
		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
-
 
9687
			  cdclk, dev_priv->max_cdclk_freq);
-
 
9688
		cdclk = dev_priv->max_cdclk_freq;
-
 
9689
	}
-
 
9690
 
-
 
9691
	to_intel_atomic_state(state)->cdclk = cdclk;
-
 
9692
 
-
 
9693
	return 0;
-
 
9694
}
-
 
9695
 
-
 
9696
static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
-
 
9697
{
-
 
9698
	struct drm_device *dev = old_state->dev;
-
 
9699
	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
-
 
9700
 
-
 
9701
	broadwell_set_cdclk(dev, req_cdclk);
-
 
9702
}
8021
}
9703
 
8022
 
9704
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
Line 8023... Line 9705...
8023
static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
9705
				      struct intel_crtc_state *crtc_state)
Line 8024... Line 9706...
8024
{
9706
{
8025
	if (!intel_ddi_pll_select(crtc))
9707
	if (!intel_ddi_pll_select(crtc, crtc_state))
Line -... Line 9708...
-
 
9708
		return -EINVAL;
-
 
9709
 
-
 
9710
	crtc->lowfreq_avail = false;
-
 
9711
 
-
 
9712
	return 0;
-
 
9713
}
-
 
9714
 
-
 
9715
static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
-
 
9716
				enum port port,
-
 
9717
				struct intel_crtc_state *pipe_config)
-
 
9718
{
-
 
9719
	switch (port) {
-
 
9720
	case PORT_A:
-
 
9721
		pipe_config->ddi_pll_sel = SKL_DPLL0;
-
 
9722
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
-
 
9723
		break;
-
 
9724
	case PORT_B:
-
 
9725
		pipe_config->ddi_pll_sel = SKL_DPLL1;
-
 
9726
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
-
 
9727
		break;
-
 
9728
	case PORT_C:
-
 
9729
		pipe_config->ddi_pll_sel = SKL_DPLL2;
8026
		return -EINVAL;
9730
		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8027
 
9731
		break;
8028
	crtc->lowfreq_avail = false;
9732
	default:
8029
 
9733
		DRM_ERROR("Incorrect port type\n");
8030
	return 0;
9734
	}
Line 8031... Line 9735...
8031
}
9735
}
8032
 
9736
 
Line 8033... Line 9737...
8033
static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9737
static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
-
 
9738
				enum port port,
-
 
9739
				struct intel_crtc_state *pipe_config)
-
 
9740
{
-
 
9741
	u32 temp, dpll_ctl1;
-
 
9742
 
-
 
9743
	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
-
 
9744
	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
-
 
9745
 
-
 
9746
	switch (pipe_config->ddi_pll_sel) {
8034
				enum port port,
9747
	case SKL_DPLL0:
8035
				struct intel_crtc_config *pipe_config)
9748
		/*
8036
{
9749
		 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8037
	u32 temp;
9750
		 * of the shared DPLL framework and thus needs to be read out
8038
 
9751
		 * separately
Line 8052... Line 9765...
8052
	}
9765
	}
8053
}
9766
}
Line 8054... Line 9767...
8054
 
9767
 
8055
static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9768
static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8056
				enum port port,
9769
				enum port port,
8057
				struct intel_crtc_config *pipe_config)
9770
				struct intel_crtc_state *pipe_config)
8058
{
9771
{
Line 8059... Line 9772...
8059
	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9772
	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8060
 
9773
 
8061
	switch (pipe_config->ddi_pll_sel) {
9774
	switch (pipe_config->ddi_pll_sel) {
8062
	case PORT_CLK_SEL_WRPLL1:
9775
	case PORT_CLK_SEL_WRPLL1:
8063
		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9776
		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8064
		break;
9777
		break;
8065
	case PORT_CLK_SEL_WRPLL2:
9778
	case PORT_CLK_SEL_WRPLL2:
-
 
9779
		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
-
 
9780
		break;
8066
		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9781
	case PORT_CLK_SEL_SPLL:
8067
		break;
9782
		pipe_config->shared_dpll = DPLL_ID_SPLL;
Line 8068... Line 9783...
8068
	}
9783
	}
8069
}
9784
}
8070
 
9785
 
8071
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9786
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8072
				       struct intel_crtc_config *pipe_config)
9787
				       struct intel_crtc_state *pipe_config)
8073
{
9788
{
8074
	struct drm_device *dev = crtc->base.dev;
9789
	struct drm_device *dev = crtc->base.dev;
Line 8081... Line 9796...
8081
 
9796
 
Line 8082... Line 9797...
8082
	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9797
	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8083
 
9798
 
-
 
9799
	if (IS_SKYLAKE(dev))
-
 
9800
		skylake_get_ddi_pll(dev_priv, port, pipe_config);
8084
	if (IS_SKYLAKE(dev))
9801
	else if (IS_BROXTON(dev))
8085
		skylake_get_ddi_pll(dev_priv, port, pipe_config);
9802
		bxt_get_ddi_pll(dev_priv, port, pipe_config);
Line 8086... Line 9803...
8086
	else
9803
	else
8087
		haswell_get_ddi_pll(dev_priv, port, pipe_config);
9804
		haswell_get_ddi_pll(dev_priv, port, pipe_config);
Line 8109... Line 9826...
8109
		ironlake_get_fdi_m_n_config(crtc, pipe_config);
9826
		ironlake_get_fdi_m_n_config(crtc, pipe_config);
8110
	}
9827
	}
8111
}
9828
}
Line 8112... Line 9829...
8112
 
9829
 
8113
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9830
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8114
				    struct intel_crtc_config *pipe_config)
9831
				    struct intel_crtc_state *pipe_config)
8115
{
9832
{
8116
	struct drm_device *dev = crtc->base.dev;
9833
	struct drm_device *dev = crtc->base.dev;
8117
	struct drm_i915_private *dev_priv = dev->dev_private;
9834
	struct drm_i915_private *dev_priv = dev->dev_private;
8118
	enum intel_display_power_domain pfit_domain;
9835
	enum intel_display_power_domain pfit_domain;
Line 8157... Line 9874...
8157
 
9874
 
Line 8158... Line 9875...
8158
	haswell_get_ddi_port_state(crtc, pipe_config);
9875
	haswell_get_ddi_port_state(crtc, pipe_config);
Line -... Line 9876...
-
 
9876
 
-
 
9877
	intel_get_pipe_timings(crtc, pipe_config);
-
 
9878
 
-
 
9879
	if (INTEL_INFO(dev)->gen >= 9) {
8159
 
9880
		skl_init_scalers(dev, crtc, pipe_config);
-
 
9881
	}
-
 
9882
 
-
 
9883
	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
-
 
9884
 
-
 
9885
	if (INTEL_INFO(dev)->gen >= 9) {
-
 
9886
		pipe_config->scaler_state.scaler_id = -1;
8160
	intel_get_pipe_timings(crtc, pipe_config);
9887
		pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
8161
 
9888
	}
8162
	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9889
 
8163
	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9890
	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8164
		if (IS_SKYLAKE(dev))
9891
		if (INTEL_INFO(dev)->gen >= 9)
8165
			skylake_get_pfit_config(crtc, pipe_config);
9892
			skylake_get_pfit_config(crtc, pipe_config);
Line 8179... Line 9906...
8179
	}
9906
	}
Line 8180... Line 9907...
8180
 
9907
 
8181
	return true;
9908
	return true;
Line 8182... Line 9909...
8182
}
9909
}
8183
 
9910
 
8184
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9911
static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
8185
{
9912
{
8186
	struct drm_device *dev = crtc->dev;
9913
	struct drm_device *dev = crtc->dev;
8187
	struct drm_i915_private *dev_priv = dev->dev_private;
9914
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 8188... Line 9915...
8188
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9915
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8189
	uint32_t cntl = 0, size = 0;
9916
	uint32_t cntl = 0, size = 0;
8190
 
9917
 
8191
	if (base) {
9918
	if (on) {
Line 8192... Line 9919...
8192
		unsigned int width = intel_crtc->cursor_width;
9919
		unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8193
		unsigned int height = intel_crtc->cursor_height;
9920
		unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8194
		unsigned int stride = roundup_pow_of_two(width) * 4;
9921
		unsigned int stride = roundup_pow_of_two(width) * 4;
Line 8219... Line 9946...
8219
	     intel_crtc->cursor_size != size ||
9946
	     intel_crtc->cursor_size != size ||
8220
	     intel_crtc->cursor_cntl != cntl)) {
9947
	     intel_crtc->cursor_cntl != cntl)) {
8221
		/* On these chipsets we can only modify the base/size/stride
9948
		/* On these chipsets we can only modify the base/size/stride
8222
		 * whilst the cursor is disabled.
9949
		 * whilst the cursor is disabled.
8223
		 */
9950
		 */
8224
			I915_WRITE(_CURACNTR, 0);
9951
		I915_WRITE(CURCNTR(PIPE_A), 0);
8225
			POSTING_READ(_CURACNTR);
9952
		POSTING_READ(CURCNTR(PIPE_A));
8226
			intel_crtc->cursor_cntl = 0;
9953
		intel_crtc->cursor_cntl = 0;
8227
		}
9954
	}
Line 8228... Line 9955...
8228
 
9955
 
8229
	if (intel_crtc->cursor_base != base) {
9956
	if (intel_crtc->cursor_base != base) {
8230
		I915_WRITE(_CURABASE, base);
9957
		I915_WRITE(CURBASE(PIPE_A), base);
8231
		intel_crtc->cursor_base = base;
9958
		intel_crtc->cursor_base = base;
Line 8232... Line 9959...
8232
	}
9959
	}
8233
 
9960
 
8234
	if (intel_crtc->cursor_size != size) {
9961
	if (intel_crtc->cursor_size != size) {
8235
		I915_WRITE(CURSIZE, size);
9962
		I915_WRITE(CURSIZE, size);
Line 8236... Line 9963...
8236
		intel_crtc->cursor_size = size;
9963
		intel_crtc->cursor_size = size;
8237
	}
9964
	}
8238
 
9965
 
8239
	if (intel_crtc->cursor_cntl != cntl) {
9966
	if (intel_crtc->cursor_cntl != cntl) {
8240
	I915_WRITE(_CURACNTR, cntl);
9967
		I915_WRITE(CURCNTR(PIPE_A), cntl);
8241
		POSTING_READ(_CURACNTR);
9968
		POSTING_READ(CURCNTR(PIPE_A));
Line 8242... Line 9969...
8242
		intel_crtc->cursor_cntl = cntl;
9969
		intel_crtc->cursor_cntl = cntl;
8243
	}
9970
	}
8244
}
9971
}
8245
 
9972
 
8246
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9973
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
8247
{
9974
{
8248
	struct drm_device *dev = crtc->dev;
9975
	struct drm_device *dev = crtc->dev;
Line 8249... Line -...
8249
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8250
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9976
	struct drm_i915_private *dev_priv = dev->dev_private;
8251
	int pipe = intel_crtc->pipe;
9977
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8252
	uint32_t cntl;
9978
	int pipe = intel_crtc->pipe;
8253
 
9979
	uint32_t cntl = 0;
8254
	cntl = 0;
9980
 
8255
		if (base) {
9981
	if (on) {
8256
		cntl = MCURSOR_GAMMA_ENABLE;
9982
		cntl = MCURSOR_GAMMA_ENABLE;
8257
		switch (intel_crtc->cursor_width) {
9983
		switch (intel_crtc->base.cursor->state->crtc_w) {
8258
			case 64:
9984
			case 64:
8259
				cntl |= CURSOR_MODE_64_ARGB_AX;
9985
				cntl |= CURSOR_MODE_64_ARGB_AX;
8260
				break;
9986
				break;
8261
			case 128:
9987
			case 128:
8262
				cntl |= CURSOR_MODE_128_ARGB_AX;
9988
				cntl |= CURSOR_MODE_128_ARGB_AX;
8263
				break;
9989
				break;
8264
			case 256:
9990
			case 256:
8265
				cntl |= CURSOR_MODE_256_ARGB_AX;
9991
				cntl |= CURSOR_MODE_256_ARGB_AX;
8266
				break;
9992
				break;
Line 8267... Line 9993...
8267
			default:
9993
			default:
8268
				WARN_ON(1);
9994
				MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8269
				return;
9995
				return;
Line 8270... Line 9996...
8270
			}
9996
		}
8271
			cntl |= pipe << 28; /* Connect to correct pipe */
9997
		cntl |= pipe << 28; /* Connect to correct pipe */
Line 8272... Line 9998...
8272
 
9998
 
8273
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9999
		if (HAS_DDI(dev))
8274
			cntl |= CURSOR_PIPE_CSC_ENABLE;
10000
			cntl |= CURSOR_PIPE_CSC_ENABLE;
Line 8296... Line 10022...
8296
{
10022
{
8297
	struct drm_device *dev = crtc->dev;
10023
	struct drm_device *dev = crtc->dev;
8298
	struct drm_i915_private *dev_priv = dev->dev_private;
10024
	struct drm_i915_private *dev_priv = dev->dev_private;
8299
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10025
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8300
	int pipe = intel_crtc->pipe;
10026
	int pipe = intel_crtc->pipe;
-
 
10027
	struct drm_plane_state *cursor_state = crtc->cursor->state;
8301
	int x = crtc->cursor_x;
10028
	int x = cursor_state->crtc_x;
8302
	int y = crtc->cursor_y;
10029
	int y = cursor_state->crtc_y;
8303
	u32 base = 0, pos = 0;
10030
	u32 base = 0, pos = 0;
Line 8304... Line -...
8304
 
-
 
8305
	if (on)
10031
 
Line 8306... Line 10032...
8306
		base = intel_crtc->cursor_addr;
10032
	base = intel_crtc->cursor_addr;
8307
 
10033
 
Line 8308... Line 10034...
8308
	if (x >= intel_crtc->config.pipe_src_w)
10034
	if (x >= intel_crtc->config->pipe_src_w)
8309
			base = 0;
10035
		on = false;
Line 8310... Line 10036...
8310
 
10036
 
8311
	if (y >= intel_crtc->config.pipe_src_h)
10037
	if (y >= intel_crtc->config->pipe_src_h)
8312
		base = 0;
10038
		on = false;
Line 8313... Line 10039...
8313
 
10039
 
8314
	if (x < 0) {
10040
	if (x < 0) {
8315
		if (x + intel_crtc->cursor_width <= 0)
10041
		if (x + cursor_state->crtc_w <= 0)
8316
			base = 0;
10042
			on = false;
Line 8317... Line 10043...
8317
 
10043
 
8318
		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10044
		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8319
		x = -x;
10045
		x = -x;
Line 8320... Line 10046...
8320
	}
10046
	}
8321
	pos |= x << CURSOR_X_SHIFT;
10047
	pos |= x << CURSOR_X_SHIFT;
8322
 
10048
 
8323
	if (y < 0) {
10049
	if (y < 0) {
Line 8324... Line -...
8324
		if (y + intel_crtc->cursor_height <= 0)
-
 
8325
			base = 0;
-
 
8326
 
-
 
8327
		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10050
		if (y + cursor_state->crtc_h <= 0)
Line 8328... Line 10051...
8328
		y = -y;
10051
			on = false;
8329
	}
10052
 
8330
	pos |= y << CURSOR_Y_SHIFT;
10053
		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8331
 
10054
		y = -y;
8332
	if (base == 0 && intel_crtc->cursor_base == 0)
10055
	}
8333
		return;
10056
	pos |= y << CURSOR_Y_SHIFT;
Line 8334... Line 10057...
8334
 
10057
 
8335
	I915_WRITE(CURPOS(pipe), pos);
10058
	I915_WRITE(CURPOS(pipe), pos);
8336
 
10059
 
8337
	/* ILK+ do this automagically */
10060
	/* ILK+ do this automagically */
8338
	if (HAS_GMCH_DISPLAY(dev) &&
10061
	if (HAS_GMCH_DISPLAY(dev) &&
Line 8339... Line 10062...
8339
		to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
10062
	    crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8340
		base += (intel_crtc->cursor_height *
10063
		base += (cursor_state->crtc_h *
8341
			intel_crtc->cursor_width - 1) * 4;
10064
			 cursor_state->crtc_w - 1) * 4;
Line 8382... Line 10105...
8382
	}
10105
	}
Line 8383... Line 10106...
8383
 
10106
 
8384
	return true;
10107
	return true;
Line 8385... Line -...
8385
}
-
 
8386
 
-
 
8387
static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
-
 
8388
				     struct drm_i915_gem_object *obj,
-
 
8389
				 uint32_t width, uint32_t height)
-
 
8390
{
-
 
8391
	struct drm_device *dev = crtc->dev;
-
 
8392
	struct drm_i915_private *dev_priv = to_i915(dev);
-
 
8393
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
8394
	enum pipe pipe = intel_crtc->pipe;
-
 
8395
	unsigned old_width;
-
 
8396
	uint32_t addr;
-
 
8397
	int ret;
-
 
8398
 
-
 
8399
	/* if we want to turn off the cursor ignore width and height */
-
 
8400
	if (!obj) {
-
 
8401
		DRM_DEBUG_KMS("cursor off\n");
-
 
8402
		addr = 0;
-
 
8403
		mutex_lock(&dev->struct_mutex);
-
 
8404
		goto finish;
-
 
8405
	}
-
 
8406
 
-
 
8407
	/* we only need to pin inside GTT if cursor is non-phy */
-
 
8408
	mutex_lock(&dev->struct_mutex);
-
 
8409
	if (!INTEL_INFO(dev)->cursor_needs_physical) {
-
 
8410
		unsigned alignment;
-
 
8411
 
-
 
8412
		/*
-
 
8413
		 * Global gtt pte registers are special registers which actually
-
 
8414
		 * forward writes to a chunk of system memory. Which means that
-
 
8415
		 * there is no risk that the register values disappear as soon
-
 
8416
		 * as we call intel_runtime_pm_put(), so it is correct to wrap
-
 
8417
		 * only the pin/unpin/fence and not more.
-
 
8418
		 */
-
 
8419
		intel_runtime_pm_get(dev_priv);
-
 
8420
 
-
 
8421
		/* Note that the w/a also requires 2 PTE of padding following
-
 
8422
		 * the bo. We currently fill all unused PTE with the shadow
-
 
8423
		 * page and so we should always have valid PTE following the
-
 
8424
		 * cursor preventing the VT-d warning.
-
 
8425
		 */
-
 
8426
		alignment = 0;
-
 
8427
		if (need_vtd_wa(dev))
-
 
8428
			alignment = 64*1024;
-
 
8429
 
-
 
8430
		ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
-
 
8431
		if (ret) {
-
 
8432
			DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
-
 
8433
			intel_runtime_pm_put(dev_priv);
-
 
8434
			goto fail_locked;
-
 
8435
		}
-
 
8436
 
-
 
8437
		ret = i915_gem_object_put_fence(obj);
-
 
8438
		if (ret) {
-
 
8439
			DRM_DEBUG_KMS("failed to release fence for cursor");
-
 
8440
			intel_runtime_pm_put(dev_priv);
-
 
8441
			goto fail_unpin;
-
 
8442
		}
-
 
8443
 
-
 
8444
		addr = i915_gem_obj_ggtt_offset(obj);
-
 
8445
 
-
 
8446
		intel_runtime_pm_put(dev_priv);
-
 
8447
	} else {
-
 
8448
       int align = IS_I830(dev) ? 16 * 1024 : 256;
-
 
8449
       ret = 1;//i915_gem_object_attach_phys(obj, align);
-
 
8450
       if (ret) {
-
 
8451
           DRM_DEBUG_KMS("failed to attach phys object\n");
-
 
8452
           goto fail_locked;
-
 
8453
       }
-
 
8454
       addr = obj->phys_handle->busaddr;
-
 
8455
	}
-
 
8456
 
-
 
8457
 finish:
-
 
8458
	if (intel_crtc->cursor_bo) {
-
 
8459
		if (!INTEL_INFO(dev)->cursor_needs_physical)
-
 
8460
			i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
-
 
8461
	}
-
 
8462
 
-
 
8463
	i915_gem_track_fb(intel_crtc->cursor_bo, obj,
-
 
8464
			  INTEL_FRONTBUFFER_CURSOR(pipe));
-
 
8465
	mutex_unlock(&dev->struct_mutex);
-
 
8466
 
-
 
8467
	old_width = intel_crtc->cursor_width;
-
 
8468
 
-
 
8469
	intel_crtc->cursor_addr = addr;
-
 
8470
	intel_crtc->cursor_bo = obj;
-
 
8471
	intel_crtc->cursor_width = width;
-
 
8472
	intel_crtc->cursor_height = height;
-
 
8473
 
-
 
8474
	if (intel_crtc->active) {
-
 
8475
		if (old_width != width)
-
 
8476
			intel_update_watermarks(crtc);
-
 
8477
		intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
-
 
8478
 
-
 
8479
		intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
-
 
8480
	}
-
 
8481
 
-
 
8482
	return 0;
-
 
8483
fail_unpin:
-
 
8484
	i915_gem_object_unpin_from_display_plane(obj);
-
 
8485
fail_locked:
-
 
8486
	mutex_unlock(&dev->struct_mutex);
-
 
8487
	return ret;
-
 
8488
}
10108
}
8489
 
10109
 
8490
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10110
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8491
				 u16 *blue, uint32_t start, uint32_t size)
10111
				 u16 *blue, uint32_t start, uint32_t size)
8492
{
10112
{
Line 8589... Line 10209...
8589
 
10209
 
8590
static struct drm_framebuffer *
10210
static struct drm_framebuffer *
8591
mode_fits_in_fbdev(struct drm_device *dev,
10211
mode_fits_in_fbdev(struct drm_device *dev,
8592
		   struct drm_display_mode *mode)
10212
		   struct drm_display_mode *mode)
8593
{
10213
{
8594
#ifdef CONFIG_DRM_I915_FBDEV
10214
#ifdef CONFIG_DRM_FBDEV_EMULATION
8595
	struct drm_i915_private *dev_priv = dev->dev_private;
10215
	struct drm_i915_private *dev_priv = dev->dev_private;
8596
	struct drm_i915_gem_object *obj;
10216
	struct drm_i915_gem_object *obj;
Line 8597... Line 10217...
8597
	struct drm_framebuffer *fb;
10217
	struct drm_framebuffer *fb;
Line 8617... Line 10237...
8617
#else
10237
#else
8618
	return NULL;
10238
	return NULL;
8619
#endif
10239
#endif
8620
}
10240
}
Line -... Line 10241...
-
 
10241
 
-
 
10242
static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
-
 
10243
					   struct drm_crtc *crtc,
-
 
10244
					   struct drm_display_mode *mode,
-
 
10245
					   struct drm_framebuffer *fb,
-
 
10246
					   int x, int y)
-
 
10247
{
-
 
10248
	struct drm_plane_state *plane_state;
-
 
10249
	int hdisplay, vdisplay;
-
 
10250
	int ret;
-
 
10251
 
-
 
10252
	plane_state = drm_atomic_get_plane_state(state, crtc->primary);
-
 
10253
	if (IS_ERR(plane_state))
-
 
10254
		return PTR_ERR(plane_state);
-
 
10255
 
-
 
10256
	if (mode)
-
 
10257
		drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
-
 
10258
	else
-
 
10259
		hdisplay = vdisplay = 0;
-
 
10260
 
-
 
10261
	ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
-
 
10262
	if (ret)
-
 
10263
		return ret;
-
 
10264
	drm_atomic_set_fb_for_plane(plane_state, fb);
-
 
10265
	plane_state->crtc_x = 0;
-
 
10266
	plane_state->crtc_y = 0;
-
 
10267
	plane_state->crtc_w = hdisplay;
-
 
10268
	plane_state->crtc_h = vdisplay;
-
 
10269
	plane_state->src_x = x << 16;
-
 
10270
	plane_state->src_y = y << 16;
-
 
10271
	plane_state->src_w = hdisplay << 16;
-
 
10272
	plane_state->src_h = vdisplay << 16;
-
 
10273
 
-
 
10274
	return 0;
-
 
10275
}
8621
 
10276
 
8622
bool intel_get_load_detect_pipe(struct drm_connector *connector,
10277
bool intel_get_load_detect_pipe(struct drm_connector *connector,
8623
				struct drm_display_mode *mode,
10278
				struct drm_display_mode *mode,
8624
				struct intel_load_detect_pipe *old,
10279
				struct intel_load_detect_pipe *old,
8625
				struct drm_modeset_acquire_ctx *ctx)
10280
				struct drm_modeset_acquire_ctx *ctx)
Line 8631... Line 10286...
8631
	struct drm_encoder *encoder = &intel_encoder->base;
10286
	struct drm_encoder *encoder = &intel_encoder->base;
8632
	struct drm_crtc *crtc = NULL;
10287
	struct drm_crtc *crtc = NULL;
8633
	struct drm_device *dev = encoder->dev;
10288
	struct drm_device *dev = encoder->dev;
8634
	struct drm_framebuffer *fb;
10289
	struct drm_framebuffer *fb;
8635
	struct drm_mode_config *config = &dev->mode_config;
10290
	struct drm_mode_config *config = &dev->mode_config;
-
 
10291
	struct drm_atomic_state *state = NULL;
-
 
10292
	struct drm_connector_state *connector_state;
-
 
10293
	struct intel_crtc_state *crtc_state;
8636
	int ret, i = -1;
10294
	int ret, i = -1;
Line 8637... Line 10295...
8637
 
10295
 
8638
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10296
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8639
		      connector->base.id, connector->name,
10297
		      connector->base.id, connector->name,
Line 8640... Line 10298...
8640
		      encoder->base.id, encoder->name);
10298
		      encoder->base.id, encoder->name);
8641
 
10299
 
8642
retry:
10300
retry:
8643
	ret = drm_modeset_lock(&config->connection_mutex, ctx);
10301
	ret = drm_modeset_lock(&config->connection_mutex, ctx);
Line 8644... Line 10302...
8644
	if (ret)
10302
	if (ret)
8645
		goto fail_unlock;
10303
		goto fail;
8646
 
10304
 
8647
	/*
10305
	/*
Line 8658... Line 10316...
8658
	if (encoder->crtc) {
10316
	if (encoder->crtc) {
8659
		crtc = encoder->crtc;
10317
		crtc = encoder->crtc;
Line 8660... Line 10318...
8660
 
10318
 
8661
		ret = drm_modeset_lock(&crtc->mutex, ctx);
10319
		ret = drm_modeset_lock(&crtc->mutex, ctx);
8662
		if (ret)
10320
		if (ret)
8663
			goto fail_unlock;
10321
			goto fail;
8664
		ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10322
		ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8665
		if (ret)
10323
		if (ret)
Line 8666... Line 10324...
8666
			goto fail_unlock;
10324
			goto fail;
8667
 
10325
 
Line 8668... Line 10326...
8668
		old->dpms_mode = connector->dpms;
10326
		old->dpms_mode = connector->dpms;
Line 8678... Line 10336...
8678
	/* Find an unused one (if possible) */
10336
	/* Find an unused one (if possible) */
8679
	for_each_crtc(dev, possible_crtc) {
10337
	for_each_crtc(dev, possible_crtc) {
8680
		i++;
10338
		i++;
8681
		if (!(encoder->possible_crtcs & (1 << i)))
10339
		if (!(encoder->possible_crtcs & (1 << i)))
8682
			continue;
10340
			continue;
8683
		if (possible_crtc->enabled)
10341
		if (possible_crtc->state->enable)
8684
			continue;
-
 
8685
		/* This can occur when applying the pipe A quirk on resume. */
-
 
8686
		if (to_intel_crtc(possible_crtc)->new_enabled)
-
 
8687
			continue;
10342
			continue;
Line 8688... Line 10343...
8688
 
10343
 
8689
			crtc = possible_crtc;
10344
		crtc = possible_crtc;
8690
			break;
10345
		break;
Line 8693... Line 10348...
8693
	/*
10348
	/*
8694
	 * If we didn't find an unused CRTC, don't use any.
10349
	 * If we didn't find an unused CRTC, don't use any.
8695
	 */
10350
	 */
8696
	if (!crtc) {
10351
	if (!crtc) {
8697
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
10352
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
8698
		goto fail_unlock;
10353
		goto fail;
8699
	}
10354
	}
Line 8700... Line 10355...
8700
 
10355
 
8701
	ret = drm_modeset_lock(&crtc->mutex, ctx);
10356
	ret = drm_modeset_lock(&crtc->mutex, ctx);
8702
	if (ret)
10357
	if (ret)
8703
		goto fail_unlock;
10358
		goto fail;
8704
	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10359
	ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8705
	if (ret)
10360
	if (ret)
8706
		goto fail_unlock;
-
 
8707
	intel_encoder->new_crtc = to_intel_crtc(crtc);
-
 
Line 8708... Line 10361...
8708
	to_intel_connector(connector)->new_encoder = intel_encoder;
10361
		goto fail;
8709
 
-
 
8710
	intel_crtc = to_intel_crtc(crtc);
-
 
8711
	intel_crtc->new_enabled = true;
10362
 
8712
	intel_crtc->new_config = &intel_crtc->config;
10363
	intel_crtc = to_intel_crtc(crtc);
8713
	old->dpms_mode = connector->dpms;
10364
	old->dpms_mode = connector->dpms;
Line -... Line 10365...
-
 
10365
	old->load_detect_temp = true;
-
 
10366
	old->release_fb = NULL;
-
 
10367
 
-
 
10368
	state = drm_atomic_state_alloc(dev);
-
 
10369
	if (!state)
-
 
10370
		return false;
-
 
10371
 
-
 
10372
	state->acquire_ctx = ctx;
-
 
10373
 
-
 
10374
	connector_state = drm_atomic_get_connector_state(state, connector);
-
 
10375
	if (IS_ERR(connector_state)) {
-
 
10376
		ret = PTR_ERR(connector_state);
-
 
10377
		goto fail;
-
 
10378
	}
-
 
10379
 
-
 
10380
	connector_state->crtc = crtc;
-
 
10381
	connector_state->best_encoder = &intel_encoder->base;
-
 
10382
 
-
 
10383
	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-
 
10384
	if (IS_ERR(crtc_state)) {
-
 
10385
		ret = PTR_ERR(crtc_state);
-
 
10386
		goto fail;
-
 
10387
	}
8714
	old->load_detect_temp = true;
10388
 
8715
	old->release_fb = NULL;
10389
	crtc_state->base.active = crtc_state->base.enable = true;
Line 8716... Line 10390...
8716
 
10390
 
8717
	if (!mode)
10391
	if (!mode)
Line 8734... Line 10408...
8734
	if (IS_ERR(fb)) {
10408
	if (IS_ERR(fb)) {
8735
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10409
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8736
		goto fail;
10410
		goto fail;
8737
	}
10411
	}
Line 8738... Line 10412...
8738
 
10412
 
-
 
10413
	ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
-
 
10414
	if (ret)
-
 
10415
		goto fail;
-
 
10416
 
-
 
10417
	drm_mode_copy(&crtc_state->base.mode, mode);
-
 
10418
 
8739
	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
10419
	if (drm_atomic_commit(state)) {
8740
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10420
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8741
		if (old->release_fb)
10421
		if (old->release_fb)
8742
			old->release_fb->funcs->destroy(old->release_fb);
10422
			old->release_fb->funcs->destroy(old->release_fb);
8743
		goto fail;
10423
		goto fail;
-
 
10424
	}
Line 8744... Line 10425...
8744
	}
10425
	crtc->primary->crtc = crtc;
8745
 
10426
 
8746
	/* let the connector get through one full cycle before testing */
10427
	/* let the connector get through one full cycle before testing */
Line 8747... Line 10428...
8747
	intel_wait_for_vblank(dev, intel_crtc->pipe);
10428
	intel_wait_for_vblank(dev, intel_crtc->pipe);
8748
	return true;
10429
	return true;
8749
 
10430
 
8750
 fail:
-
 
8751
	intel_crtc->new_enabled = crtc->enabled;
10431
fail:
8752
	if (intel_crtc->new_enabled)
-
 
8753
		intel_crtc->new_config = &intel_crtc->config;
-
 
8754
	else
10432
	drm_atomic_state_free(state);
8755
		intel_crtc->new_config = NULL;
10433
	state = NULL;
8756
fail_unlock:
10434
 
8757
	if (ret == -EDEADLK) {
10435
	if (ret == -EDEADLK) {
Line 8758... Line 10436...
8758
		drm_modeset_backoff(ctx);
10436
		drm_modeset_backoff(ctx);
8759
		goto retry;
10437
		goto retry;
Line 8760... Line 10438...
8760
	}
10438
	}
8761
 
10439
 
-
 
10440
	return false;
8762
	return false;
10441
}
-
 
10442
 
8763
}
10443
void intel_release_load_detect_pipe(struct drm_connector *connector,
8764
 
10444
				    struct intel_load_detect_pipe *old,
8765
void intel_release_load_detect_pipe(struct drm_connector *connector,
10445
				    struct drm_modeset_acquire_ctx *ctx)
8766
				    struct intel_load_detect_pipe *old)
10446
{
8767
{
10447
	struct drm_device *dev = connector->dev;
-
 
10448
	struct intel_encoder *intel_encoder =
-
 
10449
		intel_attached_encoder(connector);
-
 
10450
	struct drm_encoder *encoder = &intel_encoder->base;
-
 
10451
	struct drm_crtc *crtc = encoder->crtc;
Line 8768... Line 10452...
8768
	struct intel_encoder *intel_encoder =
10452
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8769
		intel_attached_encoder(connector);
10453
	struct drm_atomic_state *state;
8770
	struct drm_encoder *encoder = &intel_encoder->base;
10454
	struct drm_connector_state *connector_state;
Line 8771... Line 10455...
8771
	struct drm_crtc *crtc = encoder->crtc;
10455
	struct intel_crtc_state *crtc_state;
8772
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10456
	int ret;
-
 
10457
 
-
 
10458
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
-
 
10459
		      connector->base.id, connector->name,
8773
 
10460
		      encoder->base.id, encoder->name);
-
 
10461
 
-
 
10462
	if (old->load_detect_temp) {
-
 
10463
		state = drm_atomic_state_alloc(dev);
-
 
10464
		if (!state)
-
 
10465
			goto fail;
-
 
10466
 
-
 
10467
		state->acquire_ctx = ctx;
-
 
10468
 
-
 
10469
		connector_state = drm_atomic_get_connector_state(state, connector);
8774
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10470
		if (IS_ERR(connector_state))
8775
		      connector->base.id, connector->name,
10471
			goto fail;
-
 
10472
 
-
 
10473
		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
-
 
10474
		if (IS_ERR(crtc_state))
8776
		      encoder->base.id, encoder->name);
10475
			goto fail;
-
 
10476
 
-
 
10477
		connector_state->best_encoder = NULL;
-
 
10478
		connector_state->crtc = NULL;
-
 
10479
 
-
 
10480
		crtc_state->base.enable = crtc_state->base.active = false;
-
 
10481
 
-
 
10482
		ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
Line 8777... Line 10483...
8777
 
10483
						      0, 0);
8778
	if (old->load_detect_temp) {
10484
		if (ret)
8779
		to_intel_connector(connector)->new_encoder = NULL;
10485
			goto fail;
8780
		intel_encoder->new_crtc = NULL;
10486
 
Line 8791... Line 10497...
8791
	}
10497
	}
Line 8792... Line 10498...
8792
 
10498
 
8793
	/* Switch crtc and encoder back off if necessary */
10499
	/* Switch crtc and encoder back off if necessary */
8794
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
10500
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
-
 
10501
		connector->funcs->dpms(connector, old->dpms_mode);
-
 
10502
 
-
 
10503
	return;
-
 
10504
fail:
-
 
10505
	DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
8795
		connector->funcs->dpms(connector, old->dpms_mode);
10506
	drm_atomic_state_free(state);
Line 8796... Line 10507...
8796
}
10507
}
8797
 
10508
 
8798
static int i9xx_pll_refclk(struct drm_device *dev,
10509
static int i9xx_pll_refclk(struct drm_device *dev,
8799
			   const struct intel_crtc_config *pipe_config)
10510
			   const struct intel_crtc_state *pipe_config)
8800
{
10511
{
Line 8801... Line 10512...
8801
	struct drm_i915_private *dev_priv = dev->dev_private;
10512
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 8811... Line 10522...
8811
		return 48000;
10522
		return 48000;
8812
}
10523
}
Line 8813... Line 10524...
8813
 
10524
 
8814
/* Returns the clock of the currently programmed mode of the given pipe. */
10525
/* Returns the clock of the currently programmed mode of the given pipe. */
8815
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10526
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8816
				struct intel_crtc_config *pipe_config)
10527
				struct intel_crtc_state *pipe_config)
8817
{
10528
{
8818
	struct drm_device *dev = crtc->base.dev;
10529
	struct drm_device *dev = crtc->base.dev;
8819
	struct drm_i915_private *dev_priv = dev->dev_private;
10530
	struct drm_i915_private *dev_priv = dev->dev_private;
8820
	int pipe = pipe_config->cpu_transcoder;
10531
	int pipe = pipe_config->cpu_transcoder;
8821
	u32 dpll = pipe_config->dpll_hw_state.dpll;
10532
	u32 dpll = pipe_config->dpll_hw_state.dpll;
8822
	u32 fp;
10533
	u32 fp;
-
 
10534
	intel_clock_t clock;
8823
	intel_clock_t clock;
10535
	int port_clock;
Line 8824... Line 10536...
8824
	int refclk = i9xx_pll_refclk(dev, pipe_config);
10536
	int refclk = i9xx_pll_refclk(dev, pipe_config);
8825
 
10537
 
8826
	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10538
	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Line 8859... Line 10571...
8859
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
10571
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
8860
			return;
10572
			return;
8861
		}
10573
		}
Line 8862... Line 10574...
8862
 
10574
 
8863
		if (IS_PINEVIEW(dev))
10575
		if (IS_PINEVIEW(dev))
8864
			pineview_clock(refclk, &clock);
10576
			port_clock = pnv_calc_dpll_params(refclk, &clock);
8865
		else
10577
		else
8866
			i9xx_clock(refclk, &clock);
10578
			port_clock = i9xx_calc_dpll_params(refclk, &clock);
8867
	} else {
10579
	} else {
8868
		u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10580
		u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Line 8869... Line 10581...
8869
		bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10581
		bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Line 8887... Line 10599...
8887
				clock.p2 = 4;
10599
				clock.p2 = 4;
8888
			else
10600
			else
8889
				clock.p2 = 2;
10601
				clock.p2 = 2;
8890
		}
10602
		}
Line 8891... Line 10603...
8891
 
10603
 
8892
		i9xx_clock(refclk, &clock);
10604
		port_clock = i9xx_calc_dpll_params(refclk, &clock);
Line 8893... Line 10605...
8893
	}
10605
	}
8894
 
10606
 
8895
	/*
10607
	/*
8896
	 * This value includes pixel_multiplier. We will use
10608
	 * This value includes pixel_multiplier. We will use
8897
	 * port_clock to compute adjusted_mode.crtc_clock in the
10609
	 * port_clock to compute adjusted_mode.crtc_clock in the
8898
	 * encoder's get_config() function.
10610
	 * encoder's get_config() function.
8899
	 */
10611
	 */
Line 8900... Line 10612...
8900
	pipe_config->port_clock = clock.dot;
10612
	pipe_config->port_clock = port_clock;
8901
}
10613
}
8902
 
10614
 
Line 8918... Line 10630...
8918
 
10630
 
8919
	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10631
	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
Line 8920... Line 10632...
8920
}
10632
}
8921
 
10633
 
8922
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10634
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8923
				   struct intel_crtc_config *pipe_config)
10635
				   struct intel_crtc_state *pipe_config)
Line 8924... Line 10636...
8924
{
10636
{
8925
	struct drm_device *dev = crtc->base.dev;
10637
	struct drm_device *dev = crtc->base.dev;
Line 8931... Line 10643...
8931
	 * This value does not include pixel_multiplier.
10643
	 * This value does not include pixel_multiplier.
8932
	 * We will check that port_clock and adjusted_mode.crtc_clock
10644
	 * We will check that port_clock and adjusted_mode.crtc_clock
8933
	 * agree once we know their relationship in the encoder's
10645
	 * agree once we know their relationship in the encoder's
8934
	 * get_config() function.
10646
	 * get_config() function.
8935
	 */
10647
	 */
8936
	pipe_config->adjusted_mode.crtc_clock =
10648
	pipe_config->base.adjusted_mode.crtc_clock =
8937
		intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10649
		intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8938
					 &pipe_config->fdi_m_n);
10650
					 &pipe_config->fdi_m_n);
8939
}
10651
}
Line 8940... Line 10652...
8940
 
10652
 
8941
/** Returns the currently programmed mode of the given pipe. */
10653
/** Returns the currently programmed mode of the given pipe. */
8942
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10654
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8943
					     struct drm_crtc *crtc)
10655
					     struct drm_crtc *crtc)
8944
{
10656
{
8945
	struct drm_i915_private *dev_priv = dev->dev_private;
10657
	struct drm_i915_private *dev_priv = dev->dev_private;
8946
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10658
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8947
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
10659
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8948
	struct drm_display_mode *mode;
10660
	struct drm_display_mode *mode;
8949
	struct intel_crtc_config pipe_config;
10661
	struct intel_crtc_state pipe_config;
8950
	int htot = I915_READ(HTOTAL(cpu_transcoder));
10662
	int htot = I915_READ(HTOTAL(cpu_transcoder));
8951
	int hsync = I915_READ(HSYNC(cpu_transcoder));
10663
	int hsync = I915_READ(HSYNC(cpu_transcoder));
8952
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
10664
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
8953
	int vsync = I915_READ(VSYNC(cpu_transcoder));
10665
	int vsync = I915_READ(VSYNC(cpu_transcoder));
Line 8984... Line 10696...
8984
	drm_mode_set_name(mode);
10696
	drm_mode_set_name(mode);
Line 8985... Line 10697...
8985
 
10697
 
8986
	return mode;
10698
	return mode;
Line 8987... Line -...
8987
}
-
 
8988
 
-
 
8989
static void intel_decrease_pllclock(struct drm_crtc *crtc)
-
 
8990
{
-
 
8991
	struct drm_device *dev = crtc->dev;
-
 
8992
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
8993
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
8994
 
-
 
8995
	if (!HAS_GMCH_DISPLAY(dev))
-
 
8996
		return;
-
 
8997
 
-
 
8998
	if (!dev_priv->lvds_downclock_avail)
-
 
8999
		return;
-
 
9000
 
-
 
9001
	/*
-
 
9002
	 * Since this is called by a timer, we should never get here in
-
 
9003
	 * the manual case.
-
 
9004
	 */
-
 
9005
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
-
 
9006
		int pipe = intel_crtc->pipe;
-
 
9007
		int dpll_reg = DPLL(pipe);
-
 
9008
		int dpll;
-
 
9009
 
-
 
9010
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
-
 
9011
 
-
 
9012
		assert_panel_unlocked(dev_priv, pipe);
-
 
9013
 
-
 
9014
		dpll = I915_READ(dpll_reg);
-
 
9015
		dpll |= DISPLAY_RATE_SELECT_FPA1;
-
 
9016
		I915_WRITE(dpll_reg, dpll);
-
 
9017
		intel_wait_for_vblank(dev, pipe);
-
 
9018
		dpll = I915_READ(dpll_reg);
-
 
9019
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
-
 
9020
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
-
 
9021
	}
-
 
9022
 
-
 
9023
}
10699
}
9024
 
10700
 
9025
void intel_mark_busy(struct drm_device *dev)
10701
void intel_mark_busy(struct drm_device *dev)
Line 9026... Line 10702...
9026
{
10702
{
9027
	struct drm_i915_private *dev_priv = dev->dev_private;
10703
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 9028... Line 10704...
9028
 
10704
 
9029
	if (dev_priv->mm.busy)
10705
	if (dev_priv->mm.busy)
-
 
10706
		return;
-
 
10707
 
9030
		return;
10708
	intel_runtime_pm_get(dev_priv);
9031
 
10709
	i915_update_gfx_val(dev_priv);
Line 9032... Line 10710...
9032
	intel_runtime_pm_get(dev_priv);
10710
	if (INTEL_INFO(dev)->gen >= 6)
9033
	i915_update_gfx_val(dev_priv);
10711
		gen6_rps_busy(dev_priv);
9034
	dev_priv->mm.busy = true;
10712
	dev_priv->mm.busy = true;
9035
}
-
 
Line 9036... Line 10713...
9036
 
10713
}
9037
void intel_mark_idle(struct drm_device *dev)
10714
 
Line 9038... Line 10715...
9038
{
10715
void intel_mark_idle(struct drm_device *dev)
Line 9039... Line -...
9039
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
9040
	struct drm_crtc *crtc;
-
 
9041
 
-
 
9042
	if (!dev_priv->mm.busy)
-
 
9043
		return;
-
 
9044
 
-
 
9045
	dev_priv->mm.busy = false;
-
 
9046
 
-
 
9047
	if (!i915.powersave)
-
 
9048
		goto out;
-
 
9049
 
10716
{
9050
	for_each_crtc(dev, crtc) {
10717
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 9051... Line -...
9051
		if (!crtc->primary->fb)
-
 
9052
			continue;
10718
 
9053
 
10719
	if (!dev_priv->mm.busy)
Line 9054... Line 10720...
9054
		intel_decrease_pllclock(crtc);
10720
		return;
9055
	}
10721
 
Line 9085... Line 10751...
9085
#if 0
10751
#if 0
9086
static void intel_unpin_work_fn(struct work_struct *__work)
10752
static void intel_unpin_work_fn(struct work_struct *__work)
9087
{
10753
{
9088
	struct intel_unpin_work *work =
10754
	struct intel_unpin_work *work =
9089
		container_of(__work, struct intel_unpin_work, work);
10755
		container_of(__work, struct intel_unpin_work, work);
-
 
10756
	struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9090
	struct drm_device *dev = work->crtc->dev;
10757
	struct drm_device *dev = crtc->base.dev;
9091
	enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10758
	struct drm_plane *primary = crtc->base.primary;
Line 9092... Line 10759...
9092
 
10759
 
9093
	mutex_lock(&dev->struct_mutex);
10760
	mutex_lock(&dev->struct_mutex);
9094
	intel_unpin_fb_obj(work->old_fb_obj);
10761
	intel_unpin_fb_obj(work->old_fb, primary->state);
9095
	drm_gem_object_unreference(&work->pending_flip_obj->base);
-
 
Line 9096... Line 10762...
9096
	drm_gem_object_unreference(&work->old_fb_obj->base);
10762
	drm_gem_object_unreference(&work->pending_flip_obj->base);
-
 
10763
 
9097
 
10764
	if (work->flip_queued_req)
Line 9098... Line 10765...
9098
	intel_update_fbc(dev);
10765
		i915_gem_request_assign(&work->flip_queued_req, NULL);
-
 
10766
	mutex_unlock(&dev->struct_mutex);
Line 9099... Line 10767...
9099
	mutex_unlock(&dev->struct_mutex);
10767
 
9100
 
10768
	intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
Line 9101... Line 10769...
9101
	intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10769
	drm_framebuffer_unreference(work->old_fb);
9102
 
10770
 
Line 9103... Line 10771...
9103
	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10771
	BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
Line 9193... Line 10861...
9193
	 * yet actually completed. But in case the base address is the same
10861
	 * yet actually completed. But in case the base address is the same
9194
	 * anyway, we don't really care.
10862
	 * anyway, we don't really care.
9195
	 */
10863
	 */
9196
	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10864
	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9197
		crtc->unpin_work->gtt_offset &&
10865
		crtc->unpin_work->gtt_offset &&
9198
		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10866
		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
9199
				    crtc->unpin_work->flip_count);
10867
				    crtc->unpin_work->flip_count);
9200
}
10868
}
Line 9201... Line 10869...
9201
 
10869
 
9202
void intel_prepare_page_flip(struct drm_device *dev, int plane)
10870
void intel_prepare_page_flip(struct drm_device *dev, int plane)
Line 9219... Line 10887...
9219
	if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10887
	if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9220
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10888
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9221
	spin_unlock_irqrestore(&dev->event_lock, flags);
10889
	spin_unlock_irqrestore(&dev->event_lock, flags);
9222
}
10890
}
Line 9223... Line 10891...
9223
 
10891
 
9224
static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10892
static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
9225
{
10893
{
9226
	/* Ensure that the work item is consistent when activating it ... */
10894
	/* Ensure that the work item is consistent when activating it ... */
9227
	smp_wmb();
10895
	smp_wmb();
9228
	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10896
	atomic_set(&work->pending, INTEL_FLIP_PENDING);
9229
	/* and that it is marked active as soon as the irq could fire. */
10897
	/* and that it is marked active as soon as the irq could fire. */
9230
	smp_wmb();
10898
	smp_wmb();
Line 9231... Line 10899...
9231
}
10899
}
9232
 
10900
 
9233
static int intel_gen2_queue_flip(struct drm_device *dev,
10901
static int intel_gen2_queue_flip(struct drm_device *dev,
9234
				 struct drm_crtc *crtc,
10902
				 struct drm_crtc *crtc,
9235
				 struct drm_framebuffer *fb,
10903
				 struct drm_framebuffer *fb,
9236
				 struct drm_i915_gem_object *obj,
10904
				 struct drm_i915_gem_object *obj,
9237
				 struct intel_engine_cs *ring,
10905
				 struct drm_i915_gem_request *req,
-
 
10906
				 uint32_t flags)
9238
				 uint32_t flags)
10907
{
9239
{
10908
	struct intel_engine_cs *ring = req->ring;
9240
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10909
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 9241... Line 10910...
9241
	u32 flip_mask;
10910
	u32 flip_mask;
9242
	int ret;
10911
	int ret;
9243
 
10912
 
Line 9244... Line 10913...
9244
	ret = intel_ring_begin(ring, 6);
10913
	ret = intel_ring_begin(req, 6);
9245
	if (ret)
10914
	if (ret)
Line 9258... Line 10927...
9258
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10927
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9259
	intel_ring_emit(ring, fb->pitches[0]);
10928
	intel_ring_emit(ring, fb->pitches[0]);
9260
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10929
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9261
	intel_ring_emit(ring, 0); /* aux display base address, unused */
10930
	intel_ring_emit(ring, 0); /* aux display base address, unused */
Line 9262... Line 10931...
9262
 
10931
 
9263
	intel_mark_page_flip_active(intel_crtc);
-
 
9264
	__intel_ring_advance(ring);
10932
	intel_mark_page_flip_active(intel_crtc->unpin_work);
9265
	return 0;
10933
	return 0;
Line 9266... Line 10934...
9266
}
10934
}
9267
 
10935
 
9268
static int intel_gen3_queue_flip(struct drm_device *dev,
10936
static int intel_gen3_queue_flip(struct drm_device *dev,
9269
				 struct drm_crtc *crtc,
10937
				 struct drm_crtc *crtc,
9270
				 struct drm_framebuffer *fb,
10938
				 struct drm_framebuffer *fb,
9271
				 struct drm_i915_gem_object *obj,
10939
				 struct drm_i915_gem_object *obj,
9272
				 struct intel_engine_cs *ring,
10940
				 struct drm_i915_gem_request *req,
-
 
10941
				 uint32_t flags)
9273
				 uint32_t flags)
10942
{
9274
{
10943
	struct intel_engine_cs *ring = req->ring;
9275
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10944
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 9276... Line 10945...
9276
	u32 flip_mask;
10945
	u32 flip_mask;
9277
	int ret;
10946
	int ret;
9278
 
10947
 
Line 9279... Line 10948...
9279
	ret = intel_ring_begin(ring, 6);
10948
	ret = intel_ring_begin(req, 6);
9280
	if (ret)
10949
	if (ret)
Line 9290... Line 10959...
9290
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10959
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291
	intel_ring_emit(ring, fb->pitches[0]);
10960
	intel_ring_emit(ring, fb->pitches[0]);
9292
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10961
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9293
	intel_ring_emit(ring, MI_NOOP);
10962
	intel_ring_emit(ring, MI_NOOP);
Line 9294... Line 10963...
9294
 
10963
 
9295
	intel_mark_page_flip_active(intel_crtc);
-
 
9296
	__intel_ring_advance(ring);
10964
	intel_mark_page_flip_active(intel_crtc->unpin_work);
9297
	return 0;
10965
	return 0;
Line 9298... Line 10966...
9298
}
10966
}
9299
 
10967
 
9300
static int intel_gen4_queue_flip(struct drm_device *dev,
10968
static int intel_gen4_queue_flip(struct drm_device *dev,
9301
				 struct drm_crtc *crtc,
10969
				 struct drm_crtc *crtc,
9302
				 struct drm_framebuffer *fb,
10970
				 struct drm_framebuffer *fb,
9303
				 struct drm_i915_gem_object *obj,
10971
				 struct drm_i915_gem_object *obj,
9304
				 struct intel_engine_cs *ring,
10972
				 struct drm_i915_gem_request *req,
-
 
10973
				 uint32_t flags)
9305
				 uint32_t flags)
10974
{
9306
{
10975
	struct intel_engine_cs *ring = req->ring;
9307
	struct drm_i915_private *dev_priv = dev->dev_private;
10976
	struct drm_i915_private *dev_priv = dev->dev_private;
9308
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10977
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 9309... Line 10978...
9309
	uint32_t pf, pipesrc;
10978
	uint32_t pf, pipesrc;
9310
	int ret;
10979
	int ret;
9311
 
10980
 
Line 9312... Line 10981...
9312
	ret = intel_ring_begin(ring, 4);
10981
	ret = intel_ring_begin(req, 4);
9313
	if (ret)
10982
	if (ret)
Line 9329... Line 10998...
9329
	 */
10998
	 */
9330
	pf = 0;
10999
	pf = 0;
9331
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11000
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9332
	intel_ring_emit(ring, pf | pipesrc);
11001
	intel_ring_emit(ring, pf | pipesrc);
Line 9333... Line 11002...
9333
 
11002
 
9334
	intel_mark_page_flip_active(intel_crtc);
-
 
9335
	__intel_ring_advance(ring);
11003
	intel_mark_page_flip_active(intel_crtc->unpin_work);
9336
	return 0;
11004
	return 0;
Line 9337... Line 11005...
9337
}
11005
}
9338
 
11006
 
9339
static int intel_gen6_queue_flip(struct drm_device *dev,
11007
static int intel_gen6_queue_flip(struct drm_device *dev,
9340
				 struct drm_crtc *crtc,
11008
				 struct drm_crtc *crtc,
9341
				 struct drm_framebuffer *fb,
11009
				 struct drm_framebuffer *fb,
9342
				 struct drm_i915_gem_object *obj,
11010
				 struct drm_i915_gem_object *obj,
9343
				 struct intel_engine_cs *ring,
11011
				 struct drm_i915_gem_request *req,
-
 
11012
				 uint32_t flags)
9344
				 uint32_t flags)
11013
{
9345
{
11014
	struct intel_engine_cs *ring = req->ring;
9346
	struct drm_i915_private *dev_priv = dev->dev_private;
11015
	struct drm_i915_private *dev_priv = dev->dev_private;
9347
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11016
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 9348... Line 11017...
9348
	uint32_t pf, pipesrc;
11017
	uint32_t pf, pipesrc;
9349
	int ret;
11018
	int ret;
9350
 
11019
 
Line 9351... Line 11020...
9351
	ret = intel_ring_begin(ring, 4);
11020
	ret = intel_ring_begin(req, 4);
9352
	if (ret)
11021
	if (ret)
Line 9365... Line 11034...
9365
	 */
11034
	 */
9366
	pf = 0;
11035
	pf = 0;
9367
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11036
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9368
	intel_ring_emit(ring, pf | pipesrc);
11037
	intel_ring_emit(ring, pf | pipesrc);
Line 9369... Line 11038...
9369
 
11038
 
9370
	intel_mark_page_flip_active(intel_crtc);
-
 
9371
	__intel_ring_advance(ring);
11039
	intel_mark_page_flip_active(intel_crtc->unpin_work);
9372
	return 0;
11040
	return 0;
Line 9373... Line 11041...
9373
}
11041
}
9374
 
11042
 
9375
static int intel_gen7_queue_flip(struct drm_device *dev,
11043
static int intel_gen7_queue_flip(struct drm_device *dev,
9376
				 struct drm_crtc *crtc,
11044
				 struct drm_crtc *crtc,
9377
				 struct drm_framebuffer *fb,
11045
				 struct drm_framebuffer *fb,
9378
				 struct drm_i915_gem_object *obj,
11046
				 struct drm_i915_gem_object *obj,
9379
				 struct intel_engine_cs *ring,
11047
				 struct drm_i915_gem_request *req,
-
 
11048
				 uint32_t flags)
9380
				 uint32_t flags)
11049
{
9381
{
11050
	struct intel_engine_cs *ring = req->ring;
9382
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 9383... Line 11052...
9383
	uint32_t plane_bit = 0;
11052
	uint32_t plane_bit = 0;
Line 9418... Line 11087...
9418
	 * cacheline, if we ever start emitting more commands before
11087
	 * cacheline, if we ever start emitting more commands before
9419
	 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11088
	 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9420
	 * then do the cacheline alignment, and finally emit the
11089
	 * then do the cacheline alignment, and finally emit the
9421
	 * MI_DISPLAY_FLIP.
11090
	 * MI_DISPLAY_FLIP.
9422
	 */
11091
	 */
9423
	ret = intel_ring_cacheline_align(ring);
11092
	ret = intel_ring_cacheline_align(req);
9424
	if (ret)
11093
	if (ret)
9425
		return ret;
11094
		return ret;
Line 9426... Line 11095...
9426
 
11095
 
9427
	ret = intel_ring_begin(ring, len);
11096
	ret = intel_ring_begin(req, len);
9428
	if (ret)
11097
	if (ret)
Line 9429... Line 11098...
9429
		return ret;
11098
		return ret;
9430
 
11099
 
Line 9442... Line 11111...
9442
		intel_ring_emit(ring, DERRMR);
11111
		intel_ring_emit(ring, DERRMR);
9443
		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11112
		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9444
					DERRMR_PIPEB_PRI_FLIP_DONE |
11113
					DERRMR_PIPEB_PRI_FLIP_DONE |
9445
					DERRMR_PIPEC_PRI_FLIP_DONE));
11114
					DERRMR_PIPEC_PRI_FLIP_DONE));
9446
		if (IS_GEN8(dev))
11115
		if (IS_GEN8(dev))
9447
			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11116
			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
9448
					      MI_SRM_LRM_GLOBAL_GTT);
11117
					      MI_SRM_LRM_GLOBAL_GTT);
9449
		else
11118
		else
9450
		intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11119
			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
9451
				MI_SRM_LRM_GLOBAL_GTT);
11120
					      MI_SRM_LRM_GLOBAL_GTT);
9452
		intel_ring_emit(ring, DERRMR);
11121
		intel_ring_emit(ring, DERRMR);
9453
		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11122
		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9454
		if (IS_GEN8(dev)) {
11123
		if (IS_GEN8(dev)) {
9455
			intel_ring_emit(ring, 0);
11124
			intel_ring_emit(ring, 0);
Line 9460... Line 11129...
9460
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11129
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9461
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11130
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9462
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11131
	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9463
	intel_ring_emit(ring, (MI_NOOP));
11132
	intel_ring_emit(ring, (MI_NOOP));
Line 9464... Line 11133...
9464
 
11133
 
9465
	intel_mark_page_flip_active(intel_crtc);
-
 
9466
	__intel_ring_advance(ring);
11134
	intel_mark_page_flip_active(intel_crtc->unpin_work);
9467
	return 0;
11135
	return 0;
Line -... Line 11136...
-
 
11136
}
-
 
11137
 
-
 
11138
static bool use_mmio_flip(struct intel_engine_cs *ring,
-
 
11139
			  struct drm_i915_gem_object *obj)
-
 
11140
{
-
 
11141
	/*
-
 
11142
	 * This is not being used for older platforms, because
-
 
11143
	 * non-availability of flip done interrupt forces us to use
-
 
11144
	 * CS flips. Older platforms derive flip done using some clever
-
 
11145
	 * tricks involving the flip_pending status bits and vblank irqs.
-
 
11146
	 * So using MMIO flips there would disrupt this mechanism.
-
 
11147
	 */
-
 
11148
 
-
 
11149
	if (ring == NULL)
-
 
11150
		return true;
-
 
11151
 
-
 
11152
	if (INTEL_INFO(ring->dev)->gen < 5)
-
 
11153
		return false;
-
 
11154
 
-
 
11155
	if (i915.use_mmio_flip < 0)
-
 
11156
		return false;
-
 
11157
	else if (i915.use_mmio_flip > 0)
-
 
11158
		return true;
-
 
11159
	else if (i915.enable_execlists)
-
 
11160
		return true;
-
 
11161
	else
-
 
11162
		return ring != i915_gem_request_get_ring(obj->last_write_req);
-
 
11163
}
-
 
11164
 
-
 
11165
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
-
 
11166
			     struct intel_unpin_work *work)
-
 
11167
{
-
 
11168
	struct drm_device *dev = intel_crtc->base.dev;
-
 
11169
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11170
	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-
 
11171
	const enum pipe pipe = intel_crtc->pipe;
-
 
11172
	u32 ctl, stride;
-
 
11173
 
-
 
11174
	ctl = I915_READ(PLANE_CTL(pipe, 0));
-
 
11175
	ctl &= ~PLANE_CTL_TILED_MASK;
-
 
11176
	switch (fb->modifier[0]) {
-
 
11177
	case DRM_FORMAT_MOD_NONE:
-
 
11178
		break;
-
 
11179
	case I915_FORMAT_MOD_X_TILED:
-
 
11180
		ctl |= PLANE_CTL_TILED_X;
-
 
11181
		break;
-
 
11182
	case I915_FORMAT_MOD_Y_TILED:
-
 
11183
		ctl |= PLANE_CTL_TILED_Y;
-
 
11184
		break;
-
 
11185
	case I915_FORMAT_MOD_Yf_TILED:
-
 
11186
		ctl |= PLANE_CTL_TILED_YF;
-
 
11187
		break;
-
 
11188
	default:
-
 
11189
		MISSING_CASE(fb->modifier[0]);
-
 
11190
	}
-
 
11191
 
-
 
11192
	/*
-
 
11193
	 * The stride is either expressed as a multiple of 64 bytes chunks for
-
 
11194
	 * linear buffers or in number of tiles for tiled buffers.
-
 
11195
	 */
-
 
11196
	stride = fb->pitches[0] /
-
 
11197
		 intel_fb_stride_alignment(dev, fb->modifier[0],
-
 
11198
					   fb->pixel_format);
-
 
11199
 
-
 
11200
	/*
-
 
11201
	 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
-
 
11202
	 * PLANE_SURF updates, the update is then guaranteed to be atomic.
-
 
11203
	 */
-
 
11204
	I915_WRITE(PLANE_CTL(pipe, 0), ctl);
-
 
11205
	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
-
 
11206
 
-
 
11207
	I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
-
 
11208
	POSTING_READ(PLANE_SURF(pipe, 0));
-
 
11209
}
-
 
11210
 
-
 
11211
static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
-
 
11212
			     struct intel_unpin_work *work)
-
 
11213
{
-
 
11214
	struct drm_device *dev = intel_crtc->base.dev;
-
 
11215
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11216
	struct intel_framebuffer *intel_fb =
-
 
11217
		to_intel_framebuffer(intel_crtc->base.primary->fb);
-
 
11218
	struct drm_i915_gem_object *obj = intel_fb->obj;
-
 
11219
	u32 dspcntr;
-
 
11220
	u32 reg;
-
 
11221
 
-
 
11222
	reg = DSPCNTR(intel_crtc->plane);
-
 
11223
	dspcntr = I915_READ(reg);
-
 
11224
 
-
 
11225
	if (obj->tiling_mode != I915_TILING_NONE)
-
 
11226
		dspcntr |= DISPPLANE_TILED;
-
 
11227
	else
-
 
11228
		dspcntr &= ~DISPPLANE_TILED;
-
 
11229
 
-
 
11230
	I915_WRITE(reg, dspcntr);
-
 
11231
 
-
 
11232
	I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
-
 
11233
	POSTING_READ(DSPSURF(intel_crtc->plane));
-
 
11234
}
-
 
11235
 
-
 
11236
/*
-
 
11237
 * XXX: This is the temporary way to update the plane registers until we get
-
 
11238
 * around to using the usual plane update functions for MMIO flips
-
 
11239
 */
-
 
11240
static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
-
 
11241
{
-
 
11242
	struct intel_crtc *crtc = mmio_flip->crtc;
-
 
11243
	struct intel_unpin_work *work;
-
 
11244
 
-
 
11245
	spin_lock_irq(&crtc->base.dev->event_lock);
-
 
11246
	work = crtc->unpin_work;
-
 
11247
	spin_unlock_irq(&crtc->base.dev->event_lock);
-
 
11248
	if (work == NULL)
-
 
11249
		return;
-
 
11250
 
-
 
11251
	intel_mark_page_flip_active(work);
-
 
11252
 
-
 
11253
	intel_pipe_update_start(crtc);
-
 
11254
 
-
 
11255
	if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
-
 
11256
		skl_do_mmio_flip(crtc, work);
-
 
11257
	else
-
 
11258
		/* use_mmio_flip() retricts MMIO flips to ilk+ */
-
 
11259
		ilk_do_mmio_flip(crtc, work);
-
 
11260
 
-
 
11261
	intel_pipe_update_end(crtc);
-
 
11262
}
-
 
11263
 
-
 
11264
static void intel_mmio_flip_work_func(struct work_struct *work)
-
 
11265
{
-
 
11266
	struct intel_mmio_flip *mmio_flip =
-
 
11267
		container_of(work, struct intel_mmio_flip, work);
-
 
11268
 
-
 
11269
	if (mmio_flip->req) {
-
 
11270
		WARN_ON(__i915_wait_request(mmio_flip->req,
-
 
11271
					    mmio_flip->crtc->reset_counter,
-
 
11272
					    false, NULL,
-
 
11273
					    &mmio_flip->i915->rps.mmioflips));
-
 
11274
		i915_gem_request_unreference__unlocked(mmio_flip->req);
-
 
11275
	}
-
 
11276
 
-
 
11277
	intel_do_mmio_flip(mmio_flip);
-
 
11278
	kfree(mmio_flip);
9468
}
11279
}
9469
 
11280
 
9470
static int intel_default_queue_flip(struct drm_device *dev,
11281
static int intel_queue_mmio_flip(struct drm_device *dev,
9471
				    struct drm_crtc *crtc,
11282
				 struct drm_crtc *crtc,
9472
				    struct drm_framebuffer *fb,
11283
				 struct drm_framebuffer *fb,
9473
				    struct drm_i915_gem_object *obj,
11284
				 struct drm_i915_gem_object *obj,
9474
				    struct intel_engine_cs *ring,
11285
				 struct intel_engine_cs *ring,
-
 
11286
				 uint32_t flags)
-
 
11287
{
-
 
11288
	struct intel_mmio_flip *mmio_flip;
-
 
11289
 
-
 
11290
	mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
-
 
11291
	if (mmio_flip == NULL)
-
 
11292
		return -ENOMEM;
-
 
11293
 
-
 
11294
	mmio_flip->i915 = to_i915(dev);
-
 
11295
	mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
-
 
11296
	mmio_flip->crtc = to_intel_crtc(crtc);
-
 
11297
 
-
 
11298
	INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
-
 
11299
	schedule_work(&mmio_flip->work);
-
 
11300
 
-
 
11301
	return 0;
-
 
11302
}
-
 
11303
 
-
 
11304
static int intel_default_queue_flip(struct drm_device *dev,
-
 
11305
				    struct drm_crtc *crtc,
-
 
11306
				    struct drm_framebuffer *fb,
-
 
11307
				    struct drm_i915_gem_object *obj,
-
 
11308
				    struct drm_i915_gem_request *req,
9475
				    uint32_t flags)
11309
				    uint32_t flags)
9476
{
11310
{
Line -... Line 11311...
-
 
11311
	return -ENODEV;
-
 
11312
}
-
 
11313
 
-
 
11314
static bool __intel_pageflip_stall_check(struct drm_device *dev,
-
 
11315
					 struct drm_crtc *crtc)
-
 
11316
{
-
 
11317
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11318
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11319
	struct intel_unpin_work *work = intel_crtc->unpin_work;
-
 
11320
	u32 addr;
-
 
11321
 
-
 
11322
	if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
-
 
11323
		return true;
-
 
11324
 
-
 
11325
	if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
-
 
11326
		return false;
-
 
11327
 
-
 
11328
	if (!work->enable_stall_check)
-
 
11329
		return false;
-
 
11330
 
-
 
11331
	if (work->flip_ready_vblank == 0) {
-
 
11332
		if (work->flip_queued_req &&
-
 
11333
		    !i915_gem_request_completed(work->flip_queued_req, true))
-
 
11334
			return false;
-
 
11335
 
-
 
11336
		work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
-
 
11337
	}
-
 
11338
 
-
 
11339
	if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
-
 
11340
		return false;
-
 
11341
 
-
 
11342
	/* Potential stall - if we see that the flip has happened,
-
 
11343
	 * assume a missed interrupt. */
-
 
11344
	if (INTEL_INFO(dev)->gen >= 4)
-
 
11345
		addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
-
 
11346
	else
-
 
11347
		addr = I915_READ(DSPADDR(intel_crtc->plane));
-
 
11348
 
-
 
11349
	/* There is a potential issue here with a false positive after a flip
-
 
11350
	 * to the same address. We could address this by checking for a
-
 
11351
	 * non-incrementing frame counter.
-
 
11352
	 */
-
 
11353
	return addr == work->gtt_offset;
-
 
11354
}
-
 
11355
 
-
 
11356
void intel_check_page_flip(struct drm_device *dev, int pipe)
-
 
11357
{
-
 
11358
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11359
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
-
 
11360
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11361
	struct intel_unpin_work *work;
-
 
11362
 
-
 
11363
	WARN_ON(!in_interrupt());
-
 
11364
 
-
 
11365
	if (crtc == NULL)
-
 
11366
		return;
-
 
11367
 
-
 
11368
	spin_lock(&dev->event_lock);
-
 
11369
	work = intel_crtc->unpin_work;
-
 
11370
	if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
-
 
11371
		WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
-
 
11372
			 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
-
 
11373
		page_flip_completed(intel_crtc);
-
 
11374
		work = NULL;
-
 
11375
	}
-
 
11376
	if (work != NULL &&
-
 
11377
	    drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
-
 
11378
		intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
9477
	return -ENODEV;
11379
	spin_unlock(&dev->event_lock);
9478
}
11380
}
9479
 
11381
 
9480
static int intel_crtc_page_flip(struct drm_crtc *crtc,
11382
static int intel_crtc_page_flip(struct drm_crtc *crtc,
9481
				struct drm_framebuffer *fb,
11383
				struct drm_framebuffer *fb,
9482
				struct drm_pending_vblank_event *event,
11384
				struct drm_pending_vblank_event *event,
9483
				uint32_t page_flip_flags)
11385
				uint32_t page_flip_flags)
9484
{
11386
{
9485
	struct drm_device *dev = crtc->dev;
11387
	struct drm_device *dev = crtc->dev;
9486
	struct drm_i915_private *dev_priv = dev->dev_private;
11388
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11389
	struct drm_framebuffer *old_fb = crtc->primary->fb;
9487
	struct drm_framebuffer *old_fb = crtc->primary->fb;
11390
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9488
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11391
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9489
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11392
	struct drm_plane *primary = crtc->primary;
-
 
11393
	enum pipe pipe = intel_crtc->pipe;
-
 
11394
	struct intel_unpin_work *work;
9490
	enum pipe pipe = intel_crtc->pipe;
11395
	struct intel_engine_cs *ring;
Line 9491... Line 11396...
9491
	struct intel_unpin_work *work;
11396
	bool mmio_flip;
9492
	struct intel_engine_cs *ring;
11397
	struct drm_i915_gem_request *request = NULL;
9493
	int ret;
11398
	int ret;
Line 9520... Line 11425...
9520
	if (work == NULL)
11425
	if (work == NULL)
9521
		return -ENOMEM;
11426
		return -ENOMEM;
Line 9522... Line 11427...
9522
 
11427
 
9523
	work->event = event;
11428
	work->event = event;
9524
	work->crtc = crtc;
11429
	work->crtc = crtc;
9525
	work->old_fb_obj = intel_fb_obj(old_fb);
11430
	work->old_fb = old_fb;
Line 9526... Line 11431...
9526
	INIT_WORK(&work->work, intel_unpin_work_fn);
11431
	INIT_WORK(&work->work, intel_unpin_work_fn);
9527
 
11432
 
9528
	ret = drm_crtc_vblank_get(crtc);
11433
	ret = drm_crtc_vblank_get(crtc);
Line 9551... Line 11456...
9551
	spin_unlock_irq(&dev->event_lock);
11456
	spin_unlock_irq(&dev->event_lock);
Line 9552... Line 11457...
9552
 
11457
 
9553
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11458
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
Line 9554... Line -...
9554
		flush_workqueue(dev_priv->wq);
-
 
9555
 
-
 
9556
	ret = i915_mutex_lock_interruptible(dev);
-
 
9557
	if (ret)
-
 
9558
		goto cleanup;
11459
		flush_workqueue(dev_priv->wq);
9559
 
11460
 
9560
	/* Reference the objects for the scheduled work. */
11461
	/* Reference the objects for the scheduled work. */
Line 9561... Line 11462...
9561
	drm_gem_object_reference(&work->old_fb_obj->base);
11462
	drm_framebuffer_reference(work->old_fb);
-
 
11463
	drm_gem_object_reference(&obj->base);
Line 9562... Line 11464...
9562
	drm_gem_object_reference(&obj->base);
11464
 
Line -... Line 11465...
-
 
11465
	crtc->primary->fb = fb;
-
 
11466
	update_state_fb(crtc->primary);
-
 
11467
 
-
 
11468
	work->pending_flip_obj = obj;
9563
 
11469
 
9564
	crtc->primary->fb = fb;
11470
	ret = i915_mutex_lock_interruptible(dev);
Line 9565... Line 11471...
9565
 
11471
	if (ret)
9566
	work->pending_flip_obj = obj;
11472
		goto cleanup;
Line 9567... Line 11473...
9567
 
11473
 
9568
	atomic_inc(&intel_crtc->unpin_work_count);
11474
	atomic_inc(&intel_crtc->unpin_work_count);
9569
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11475
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9570
 
11476
 
9571
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11477
	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9572
		work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11478
		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
9573
 
11479
 
9574
	if (IS_VALLEYVIEW(dev)) {
11480
	if (IS_VALLEYVIEW(dev)) {
9575
		ring = &dev_priv->ring[BCS];
11481
		ring = &dev_priv->ring[BCS];
9576
		if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
11482
		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9577
			/* vlv: DISPLAY_FLIP fails to change tiling */
11483
			/* vlv: DISPLAY_FLIP fails to change tiling */
9578
			ring = NULL;
11484
			ring = NULL;
9579
	} else if (IS_IVYBRIDGE(dev)) {
11485
	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9580
		ring = &dev_priv->ring[BCS];
11486
		ring = &dev_priv->ring[BCS];
Line -... Line 11487...
-
 
11487
	} else if (INTEL_INFO(dev)->gen >= 7) {
-
 
11488
		ring = i915_gem_request_get_ring(obj->last_write_req);
-
 
11489
		if (ring == NULL || ring->id != RCS)
-
 
11490
			ring = &dev_priv->ring[BCS];
-
 
11491
	} else {
-
 
11492
		ring = &dev_priv->ring[RCS];
-
 
11493
	}
9581
	} else if (INTEL_INFO(dev)->gen >= 7) {
11494
 
-
 
11495
	mmio_flip = use_mmio_flip(ring, obj);
-
 
11496
 
9582
		ring = obj->ring;
11497
	/* When using CS flips, we want to emit semaphores between rings.
9583
		if (ring == NULL || ring->id != RCS)
11498
	 * However, when using mmio flips we will create a task to do the
Line -... Line 11499...
-
 
11499
	 * synchronisation, so all we want here is to pin the framebuffer
9584
			ring = &dev_priv->ring[BCS];
11500
	 * into the display plane and skip any waits.
9585
	} else {
11501
	 */
Line 9586... Line 11502...
9586
		ring = &dev_priv->ring[RCS];
11502
	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
9587
	}
11503
					 crtc->primary->state,
9588
 
11504
					 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
9589
	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
11505
	if (ret)
9590
	if (ret)
11506
		goto cleanup_pending;
Line 9591... Line 11507...
9591
		goto cleanup_pending;
11507
 
9592
 
11508
	work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
9593
	work->gtt_offset =
11509
						  obj, 0);
-
 
11510
	work->gtt_offset += intel_crtc->dspaddr_offset;
-
 
11511
 
-
 
11512
	if (mmio_flip) {
-
 
11513
		ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
-
 
11514
					    page_flip_flags);
-
 
11515
		if (ret)
9594
		i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
11516
			goto cleanup_unpin;
9595
 
11517
 
9596
	if (use_mmio_flip(ring, obj)) {
11518
		i915_gem_request_assign(&work->flip_queued_req,
9597
		ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11519
					obj->last_write_req);
Line 9598... Line -...
9598
					    page_flip_flags);
-
 
9599
		if (ret)
11520
	} else {
9600
			goto cleanup_unpin;
11521
		if (!request) {
Line 9601... Line 11522...
9601
 
11522
			ret = i915_gem_request_alloc(ring, ring->default_context, &request);
9602
		work->flip_queued_seqno = obj->last_write_seqno;
11523
			if (ret)
Line 9603... Line 11524...
9603
		work->flip_queued_ring = obj->ring;
11524
				goto cleanup_unpin;
9604
	} else {
11525
		}
Line 9605... Line 11526...
9605
		ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11526
 
9606
				page_flip_flags);
11527
		ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
9607
	if (ret)
11528
						   page_flip_flags);
Line -... Line 11529...
-
 
11529
		if (ret)
-
 
11530
			goto cleanup_unpin;
-
 
11531
 
-
 
11532
		i915_gem_request_assign(&work->flip_queued_req, request);
9608
		goto cleanup_unpin;
11533
	}
Line 9609... Line 11534...
9609
 
11534
 
Line 9610... Line 11535...
9610
		work->flip_queued_seqno = intel_ring_get_seqno(ring);
11535
	if (request)
9611
		work->flip_queued_ring = ring;
11536
		i915_add_request_no_flush(request);
9612
	}
11537
 
-
 
11538
	work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
-
 
11539
	work->enable_stall_check = true;
9613
 
11540
 
9614
	work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
-
 
9615
	work->enable_stall_check = true;
-
 
9616
 
-
 
9617
	i915_gem_track_fb(work->old_fb_obj, obj,
11541
	i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9618
			  INTEL_FRONTBUFFER_PRIMARY(pipe));
-
 
9619
 
11542
			  to_intel_plane(primary)->frontbuffer_bit);
-
 
11543
	mutex_unlock(&dev->struct_mutex);
-
 
11544
 
-
 
11545
	intel_fbc_disable_crtc(intel_crtc);
-
 
11546
	intel_frontbuffer_flip_prepare(dev,
-
 
11547
				       to_intel_plane(primary)->frontbuffer_bit);
-
 
11548
 
9620
	intel_disable_fbc(dev);
11549
	trace_i915_flip_request(intel_crtc->plane, obj);
9621
	intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11550
 
9622
	mutex_unlock(&dev->struct_mutex);
11551
	return 0;
Line 9623... Line 11552...
9623
 
11552
 
9624
	trace_i915_flip_request(intel_crtc->plane, obj);
11553
cleanup_unpin:
9625
 
11554
	intel_unpin_fb_obj(fb, crtc->primary->state);
Line 9626... Line 11555...
9626
	return 0;
11555
cleanup_pending:
-
 
11556
	if (request)
-
 
11557
		i915_gem_request_cancel(request);
-
 
11558
	atomic_dec(&intel_crtc->unpin_work_count);
9627
 
11559
	mutex_unlock(&dev->struct_mutex);
-
 
11560
cleanup:
-
 
11561
	crtc->primary->fb = old_fb;
-
 
11562
	update_state_fb(crtc->primary);
-
 
11563
 
-
 
11564
	drm_gem_object_unreference_unlocked(&obj->base);
-
 
11565
	drm_framebuffer_unreference(work->old_fb);
-
 
11566
 
-
 
11567
	spin_lock_irq(&dev->event_lock);
-
 
11568
	intel_crtc->unpin_work = NULL;
-
 
11569
	spin_unlock_irq(&dev->event_lock);
-
 
11570
 
9628
cleanup_unpin:
11571
	drm_crtc_vblank_put(crtc);
-
 
11572
free_work:
-
 
11573
	kfree(work);
-
 
11574
 
-
 
11575
	if (ret == -EIO) {
-
 
11576
		struct drm_atomic_state *state;
9629
	intel_unpin_fb_obj(obj);
11577
		struct drm_plane_state *plane_state;
-
 
11578
 
-
 
11579
out_hang:
-
 
11580
		state = drm_atomic_state_alloc(dev);
-
 
11581
		if (!state)
-
 
11582
			return -ENOMEM;
-
 
11583
		state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
-
 
11584
 
9630
cleanup_pending:
11585
retry:
9631
	atomic_dec(&intel_crtc->unpin_work_count);
11586
		plane_state = drm_atomic_get_plane_state(state, primary);
9632
	crtc->primary->fb = old_fb;
11587
		ret = PTR_ERR_OR_ZERO(plane_state);
9633
	drm_gem_object_unreference(&work->old_fb_obj->base);
11588
		if (!ret) {
9634
	drm_gem_object_unreference(&obj->base);
11589
			drm_atomic_set_fb_for_plane(plane_state, fb);
9635
	mutex_unlock(&dev->struct_mutex);
11590
 
9636
 
11591
			ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
9637
cleanup:
11592
			if (!ret)
9638
	spin_lock_irq(&dev->event_lock);
11593
				ret = drm_atomic_commit(state);
Line 9639... Line -...
9639
	intel_crtc->unpin_work = NULL;
-
 
9640
	spin_unlock_irq(&dev->event_lock);
-
 
9641
 
-
 
9642
	drm_crtc_vblank_put(crtc);
-
 
Line 9643... Line 11594...
9643
free_work:
11594
		}
-
 
11595
 
-
 
11596
		if (ret == -EDEADLK) {
-
 
11597
			drm_modeset_backoff(state->acquire_ctx);
-
 
11598
			drm_atomic_state_clear(state);
-
 
11599
			goto retry;
-
 
11600
		}
-
 
11601
 
-
 
11602
		if (ret)
-
 
11603
			drm_atomic_state_free(state);
-
 
11604
 
-
 
11605
		if (ret == 0 && event) {
-
 
11606
			spin_lock_irq(&dev->event_lock);
-
 
11607
			drm_send_vblank_event(dev, pipe, event);
-
 
11608
			spin_unlock_irq(&dev->event_lock);
-
 
11609
		}
-
 
11610
	}
-
 
11611
	return ret;
-
 
11612
}
-
 
11613
#endif
-
 
11614
 
-
 
11615
 
-
 
11616
/**
-
 
11617
 * intel_wm_need_update - Check whether watermarks need updating
-
 
11618
 * @plane: drm plane
-
 
11619
 * @state: new plane state
-
 
11620
 *
-
 
11621
 * Check current plane state versus the new one to determine whether
-
 
11622
 * watermarks need to be recalculated.
-
 
11623
 *
-
 
11624
 * Returns true or false.
-
 
11625
 */
-
 
11626
static bool intel_wm_need_update(struct drm_plane *plane,
-
 
11627
				 struct drm_plane_state *state)
-
 
11628
{
-
 
11629
	/* Update watermarks on tiling changes. */
-
 
11630
	if (!plane->state->fb || !state->fb ||
-
 
11631
	    plane->state->fb->modifier[0] != state->fb->modifier[0] ||
-
 
11632
	    plane->state->rotation != state->rotation)
-
 
11633
		return true;
-
 
11634
 
-
 
11635
	if (plane->state->crtc_w != state->crtc_w)
-
 
11636
		return true;
-
 
11637
 
-
 
11638
	return false;
-
 
11639
}
-
 
11640
 
-
 
11641
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
-
 
11642
				    struct drm_plane_state *plane_state)
-
 
11643
{
-
 
11644
	struct drm_crtc *crtc = crtc_state->crtc;
-
 
11645
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11646
	struct drm_plane *plane = plane_state->plane;
-
 
11647
	struct drm_device *dev = crtc->dev;
-
 
11648
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11649
	struct intel_plane_state *old_plane_state =
-
 
11650
		to_intel_plane_state(plane->state);
-
 
11651
	int idx = intel_crtc->base.base.id, ret;
-
 
11652
	int i = drm_plane_index(plane);
-
 
11653
	bool mode_changed = needs_modeset(crtc_state);
-
 
11654
	bool was_crtc_enabled = crtc->state->active;
-
 
11655
	bool is_crtc_enabled = crtc_state->active;
-
 
11656
 
-
 
11657
	bool turn_off, turn_on, visible, was_visible;
-
 
11658
	struct drm_framebuffer *fb = plane_state->fb;
-
 
11659
 
-
 
11660
	if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
-
 
11661
	    plane->type != DRM_PLANE_TYPE_CURSOR) {
-
 
11662
		ret = skl_update_scaler_plane(
-
 
11663
			to_intel_crtc_state(crtc_state),
-
 
11664
			to_intel_plane_state(plane_state));
-
 
11665
		if (ret)
-
 
11666
			return ret;
-
 
11667
	}
-
 
11668
 
-
 
11669
	/*
-
 
11670
	 * Disabling a plane is always okay; we just need to update
-
 
11671
	 * fb tracking in a special way since cleanup_fb() won't
-
 
11672
	 * get called by the plane helpers.
-
 
11673
	 */
-
 
11674
	if (old_plane_state->base.fb && !fb)
-
 
11675
		intel_crtc->atomic.disabled_planes |= 1 << i;
-
 
11676
 
-
 
11677
	was_visible = old_plane_state->visible;
-
 
11678
	visible = to_intel_plane_state(plane_state)->visible;
-
 
11679
 
-
 
11680
	if (!was_crtc_enabled && WARN_ON(was_visible))
-
 
11681
		was_visible = false;
-
 
11682
 
-
 
11683
	if (!is_crtc_enabled && WARN_ON(visible))
-
 
11684
		visible = false;
-
 
11685
 
-
 
11686
	if (!was_visible && !visible)
-
 
11687
		return 0;
-
 
11688
 
-
 
11689
	turn_off = was_visible && (!visible || mode_changed);
-
 
11690
	turn_on = visible && (!was_visible || mode_changed);
-
 
11691
 
-
 
11692
	DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
-
 
11693
			 plane->base.id, fb ? fb->base.id : -1);
9644
	kfree(work);
11694
 
-
 
11695
	DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
-
 
11696
			 plane->base.id, was_visible, visible,
-
 
11697
			 turn_off, turn_on, mode_changed);
-
 
11698
 
-
 
11699
	if (turn_on) {
-
 
11700
		intel_crtc->atomic.update_wm_pre = true;
-
 
11701
		/* must disable cxsr around plane enable/disable */
-
 
11702
		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-
 
11703
			intel_crtc->atomic.disable_cxsr = true;
-
 
11704
			/* to potentially re-enable cxsr */
-
 
11705
			intel_crtc->atomic.wait_vblank = true;
-
 
11706
			intel_crtc->atomic.update_wm_post = true;
-
 
11707
		}
-
 
11708
	} else if (turn_off) {
-
 
11709
		intel_crtc->atomic.update_wm_post = true;
-
 
11710
		/* must disable cxsr around plane enable/disable */
-
 
11711
		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-
 
11712
			if (is_crtc_enabled)
-
 
11713
				intel_crtc->atomic.wait_vblank = true;
-
 
11714
			intel_crtc->atomic.disable_cxsr = true;
-
 
11715
		}
-
 
11716
	} else if (intel_wm_need_update(plane, plane_state)) {
-
 
11717
		intel_crtc->atomic.update_wm_pre = true;
-
 
11718
	}
-
 
11719
 
-
 
11720
	if (visible || was_visible)
-
 
11721
		intel_crtc->atomic.fb_bits |=
-
 
11722
			to_intel_plane(plane)->frontbuffer_bit;
-
 
11723
 
-
 
11724
	switch (plane->type) {
-
 
11725
	case DRM_PLANE_TYPE_PRIMARY:
9645
 
11726
		intel_crtc->atomic.wait_for_flips = true;
-
 
11727
		intel_crtc->atomic.pre_disable_primary = turn_off;
9646
	if (ret == -EIO) {
11728
		intel_crtc->atomic.post_enable_primary = turn_on;
-
 
11729
 
9647
out_hang:
11730
		if (turn_off) {
9648
//       intel_crtc_wait_for_pending_flips(crtc);
11731
			/*
9649
		ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
-
 
9650
		if (ret == 0 && event) {
-
 
9651
			spin_lock_irq(&dev->event_lock);
-
 
9652
			drm_send_vblank_event(dev, pipe, event);
-
 
9653
			spin_unlock_irq(&dev->event_lock);
-
 
Line -... Line 11732...
-
 
11732
			 * FIXME: Actually if we will still have any other
-
 
11733
			 * plane enabled on the pipe we could let IPS enabled
-
 
11734
			 * still, but for now lets consider that when we make
-
 
11735
			 * primary invisible by setting DSPCNTR to 0 on
-
 
11736
			 * update_primary_plane function IPS needs to be
-
 
11737
			 * disable.
-
 
11738
			 */
-
 
11739
			intel_crtc->atomic.disable_ips = true;
-
 
11740
 
-
 
11741
			intel_crtc->atomic.disable_fbc = true;
-
 
11742
		}
-
 
11743
 
-
 
11744
		/*
-
 
11745
		 * FBC does not work on some platforms for rotated
9654
		}
11746
		 * planes, so disable it when rotation is not 0 and
-
 
11747
		 * update it when rotation is set back to 0.
-
 
11748
		 *
-
 
11749
		 * FIXME: This is redundant with the fbc update done in
-
 
11750
		 * the primary plane enable function except that that
9655
	}
11751
		 * one is done too late. We eventually need to unify
9656
	return ret;
11752
		 * this.
9657
}
11753
		 */
-
 
11754
 
-
 
11755
		if (visible &&
-
 
11756
		    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
-
 
11757
		    dev_priv->fbc.crtc == intel_crtc &&
9658
#endif
11758
		    plane_state->rotation != BIT(DRM_ROTATE_0))
Line 9659... Line 11759...
9659
 
11759
			intel_crtc->atomic.disable_fbc = true;
9660
static struct drm_crtc_helper_funcs intel_helper_funcs = {
11760
 
-
 
11761
		/*
-
 
11762
		 * BDW signals flip done immediately if the plane
-
 
11763
		 * is disabled, even if the plane enable is already
9661
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
11764
		 * armed to occur at the next vblank :(
9662
	.load_lut = intel_crtc_load_lut,
11765
		 */
Line -... Line 11766...
-
 
11766
		if (turn_on && IS_BROADWELL(dev))
9663
};
11767
			intel_crtc->atomic.wait_vblank = true;
-
 
11768
 
-
 
11769
		intel_crtc->atomic.update_fbc |= visible || mode_changed;
9664
 
11770
		break;
-
 
11771
	case DRM_PLANE_TYPE_CURSOR:
-
 
11772
		break;
-
 
11773
	case DRM_PLANE_TYPE_OVERLAY:
Line 9665... Line 11774...
9665
/**
11774
		if (turn_off && !mode_changed) {
9666
 * intel_modeset_update_staged_output_state
11775
			intel_crtc->atomic.wait_vblank = true;
9667
 *
11776
			intel_crtc->atomic.update_sprite_watermarks |=
-
 
11777
				1 << i;
9668
 * Updates the staged output configuration state, e.g. after we've read out the
11778
		}
-
 
11779
	}
-
 
11780
	return 0;
-
 
11781
}
9669
 * current hw state.
11782
 
-
 
11783
static bool encoders_cloneable(const struct intel_encoder *a,
-
 
11784
			       const struct intel_encoder *b)
9670
 */
11785
{
Line 9671... Line -...
9671
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
-
 
9672
{
-
 
9673
	struct intel_crtc *crtc;
-
 
9674
	struct intel_encoder *encoder;
11786
	/* masks could be asymmetric, so check both ways */
9675
	struct intel_connector *connector;
-
 
9676
 
11787
	return a == b || (a->cloneable & (1 << b->type) &&
9677
	list_for_each_entry(connector, &dev->mode_config.connector_list,
11788
			  b->cloneable & (1 << a->type));
9678
			    base.head) {
-
 
9679
		connector->new_encoder =
11789
}
9680
			to_intel_encoder(connector->base.encoder);
11790
 
-
 
11791
static bool check_single_encoder_cloning(struct drm_atomic_state *state,
-
 
11792
					 struct intel_crtc *crtc,
-
 
11793
					 struct intel_encoder *encoder)
-
 
11794
{
-
 
11795
	struct intel_encoder *source_encoder;
-
 
11796
	struct drm_connector *connector;
Line 9681... Line 11797...
9681
	}
11797
	struct drm_connector_state *connector_state;
9682
 
-
 
9683
	for_each_intel_encoder(dev, encoder) {
11798
	int i;
-
 
11799
 
9684
		encoder->new_crtc =
11800
	for_each_connector_in_state(state, connector, connector_state, i) {
Line 9685... Line 11801...
9685
			to_intel_crtc(encoder->base.crtc);
11801
		if (connector_state->crtc != &crtc->base)
9686
	}
-
 
9687
 
11802
			continue;
Line -... Line 11803...
-
 
11803
 
-
 
11804
		source_encoder =
-
 
11805
			to_intel_encoder(connector_state->best_encoder);
-
 
11806
		if (!encoders_cloneable(encoder, source_encoder))
-
 
11807
			return false;
-
 
11808
	}
-
 
11809
 
-
 
11810
	return true;
-
 
11811
}
-
 
11812
 
-
 
11813
static bool check_encoder_cloning(struct drm_atomic_state *state,
-
 
11814
				  struct intel_crtc *crtc)
-
 
11815
{
-
 
11816
	struct intel_encoder *encoder;
-
 
11817
	struct drm_connector *connector;
-
 
11818
	struct drm_connector_state *connector_state;
-
 
11819
	int i;
-
 
11820
 
-
 
11821
	for_each_connector_in_state(state, connector, connector_state, i) {
-
 
11822
		if (connector_state->crtc != &crtc->base)
-
 
11823
			continue;
-
 
11824
 
-
 
11825
		encoder = to_intel_encoder(connector_state->best_encoder);
-
 
11826
		if (!check_single_encoder_cloning(state, crtc, encoder))
-
 
11827
			return false;
-
 
11828
	}
-
 
11829
 
-
 
11830
	return true;
-
 
11831
}
-
 
11832
 
-
 
11833
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
-
 
11834
				   struct drm_crtc_state *crtc_state)
-
 
11835
{
-
 
11836
	struct drm_device *dev = crtc->dev;
-
 
11837
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11838
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11839
	struct intel_crtc_state *pipe_config =
-
 
11840
		to_intel_crtc_state(crtc_state);
-
 
11841
	struct drm_atomic_state *state = crtc_state->state;
-
 
11842
	int ret;
-
 
11843
	bool mode_changed = needs_modeset(crtc_state);
-
 
11844
 
-
 
11845
	if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
-
 
11846
		DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
-
 
11847
		return -EINVAL;
-
 
11848
	}
-
 
11849
 
-
 
11850
	if (mode_changed && !crtc_state->active)
-
 
11851
		intel_crtc->atomic.update_wm_post = true;
-
 
11852
 
-
 
11853
	if (mode_changed && crtc_state->enable &&
-
 
11854
	    dev_priv->display.crtc_compute_clock &&
-
 
11855
	    !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
-
 
11856
		ret = dev_priv->display.crtc_compute_clock(intel_crtc,
9688
	for_each_intel_crtc(dev, crtc) {
11857
							   pipe_config);
-
 
11858
		if (ret)
9689
		crtc->new_enabled = crtc->base.enabled;
11859
			return ret;
-
 
11860
	}
-
 
11861
 
-
 
11862
	ret = 0;
-
 
11863
	if (INTEL_INFO(dev)->gen >= 9) {
-
 
11864
		if (mode_changed)
-
 
11865
			ret = skl_update_scaler_crtc(pipe_config);
-
 
11866
 
9690
 
11867
		if (!ret)
9691
		if (crtc->new_enabled)
11868
			ret = intel_atomic_setup_scalers(dev, intel_crtc,
Line 9692... Line 11869...
9692
			crtc->new_config = &crtc->config;
11869
							 pipe_config);
9693
		else
11870
	}
9694
			crtc->new_config = NULL;
11871
 
9695
	}
11872
	return ret;
9696
}
11873
}
Line 9697... Line 11874...
9697
 
11874
 
9698
/**
11875
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
Line 9746... Line 11923...
9746
	}
11923
	}
9747
}
11924
}
Line 9748... Line 11925...
9748
 
11925
 
9749
static int
11926
static int
9750
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
-
 
9751
		    struct drm_framebuffer *fb,
11927
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9752
		    struct intel_crtc_config *pipe_config)
11928
			  struct intel_crtc_state *pipe_config)
9753
{
11929
{
-
 
11930
	struct drm_device *dev = crtc->base.dev;
9754
	struct drm_device *dev = crtc->base.dev;
11931
	struct drm_atomic_state *state;
-
 
11932
	struct drm_connector *connector;
9755
	struct intel_connector *connector;
11933
	struct drm_connector_state *connector_state;
Line 9756... Line -...
9756
	int bpp;
-
 
9757
 
-
 
9758
	switch (fb->pixel_format) {
-
 
9759
	case DRM_FORMAT_C8:
-
 
9760
		bpp = 8*3; /* since we go through a colormap */
-
 
9761
		break;
-
 
9762
	case DRM_FORMAT_XRGB1555:
-
 
9763
	case DRM_FORMAT_ARGB1555:
11934
	int bpp, i;
9764
		/* checked in intel_framebuffer_init already */
-
 
9765
		if (WARN_ON(INTEL_INFO(dev)->gen > 3))
-
 
9766
			return -EINVAL;
-
 
9767
	case DRM_FORMAT_RGB565:
-
 
9768
		bpp = 6*3; /* min is 18bpp */
-
 
9769
		break;
-
 
9770
	case DRM_FORMAT_XBGR8888:
-
 
9771
	case DRM_FORMAT_ABGR8888:
-
 
9772
		/* checked in intel_framebuffer_init already */
-
 
9773
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
-
 
9774
			return -EINVAL;
-
 
9775
	case DRM_FORMAT_XRGB8888:
-
 
9776
	case DRM_FORMAT_ARGB8888:
-
 
9777
		bpp = 8*3;
-
 
9778
		break;
-
 
9779
	case DRM_FORMAT_XRGB2101010:
-
 
9780
	case DRM_FORMAT_ARGB2101010:
-
 
9781
	case DRM_FORMAT_XBGR2101010:
-
 
9782
	case DRM_FORMAT_ABGR2101010:
-
 
9783
		/* checked in intel_framebuffer_init already */
-
 
9784
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
11935
 
-
 
11936
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
9785
			return -EINVAL;
11937
		bpp = 10*3;
9786
		bpp = 10*3;
-
 
9787
		break;
11938
	else if (INTEL_INFO(dev)->gen >= 5)
9788
	/* TODO: gen4+ supports 16 bpc floating point, too. */
-
 
9789
	default:
11939
		bpp = 12*3;
9790
		DRM_DEBUG_KMS("unsupported depth\n");
11940
	else
Line 9791... Line 11941...
9791
		return -EINVAL;
11941
		bpp = 8*3;
Line -... Line 11942...
-
 
11942
 
-
 
11943
 
9792
	}
11944
	pipe_config->pipe_bpp = bpp;
9793
 
11945
 
9794
	pipe_config->pipe_bpp = bpp;
-
 
9795
 
-
 
9796
	/* Clamp display bpp to EDID value */
11946
	state = pipe_config->base.state;
9797
	list_for_each_entry(connector, &dev->mode_config.connector_list,
11947
 
Line 9798... Line 11948...
9798
			    base.head) {
11948
	/* Clamp display bpp to EDID value */
-
 
11949
	for_each_connector_in_state(state, connector, connector_state, i) {
9799
		if (!connector->new_encoder ||
11950
		if (connector_state->crtc != &crtc->base)
Line 9800... Line 11951...
9800
		    connector->new_encoder->new_crtc != crtc)
11951
			continue;
9801
			continue;
11952
 
Line 9816... Line 11967...
9816
		mode->crtc_vdisplay, mode->crtc_vsync_start,
11967
		mode->crtc_vdisplay, mode->crtc_vsync_start,
9817
		mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11968
		mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9818
}
11969
}
Line 9819... Line 11970...
9819
 
11970
 
9820
static void intel_dump_pipe_config(struct intel_crtc *crtc,
11971
static void intel_dump_pipe_config(struct intel_crtc *crtc,
9821
				   struct intel_crtc_config *pipe_config,
11972
				   struct intel_crtc_state *pipe_config,
9822
				   const char *context)
11973
				   const char *context)
-
 
11974
{
-
 
11975
	struct drm_device *dev = crtc->base.dev;
-
 
11976
	struct drm_plane *plane;
-
 
11977
	struct intel_plane *intel_plane;
-
 
11978
	struct intel_plane_state *state;
-
 
11979
	struct drm_framebuffer *fb;
9823
{
11980
 
9824
	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
11981
	DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
Line 9825... Line 11982...
9825
		      context, pipe_name(crtc->pipe));
11982
		      context, pipe_config, pipe_name(crtc->pipe));
9826
 
11983
 
9827
	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11984
	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9828
	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11985
	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9829
		      pipe_config->pipe_bpp, pipe_config->dither);
11986
		      pipe_config->pipe_bpp, pipe_config->dither);
9830
	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11987
	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9831
		      pipe_config->has_pch_encoder,
11988
		      pipe_config->has_pch_encoder,
9832
		      pipe_config->fdi_lanes,
11989
		      pipe_config->fdi_lanes,
9833
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11990
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9834
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11991
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9835
		      pipe_config->fdi_m_n.tu);
11992
		      pipe_config->fdi_m_n.tu);
-
 
11993
	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9836
	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11994
		      pipe_config->has_dp_encoder,
9837
		      pipe_config->has_dp_encoder,
11995
		      pipe_config->lane_count,
9838
		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11996
		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
Line 9839... Line 11997...
9839
		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11997
		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9840
		      pipe_config->dp_m_n.tu);
11998
		      pipe_config->dp_m_n.tu);
-
 
11999
 
9841
 
12000
	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9842
	DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12001
		      pipe_config->has_dp_encoder,
9843
		      pipe_config->has_dp_encoder,
12002
		      pipe_config->lane_count,
9844
		      pipe_config->dp_m2_n2.gmch_m,
12003
		      pipe_config->dp_m2_n2.gmch_m,
9845
		      pipe_config->dp_m2_n2.gmch_n,
12004
		      pipe_config->dp_m2_n2.gmch_n,
Line 9850... Line 12009...
9850
	DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12009
	DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9851
		      pipe_config->has_audio,
12010
		      pipe_config->has_audio,
9852
		      pipe_config->has_infoframe);
12011
		      pipe_config->has_infoframe);
Line 9853... Line 12012...
9853
 
12012
 
9854
	DRM_DEBUG_KMS("requested mode:\n");
12013
	DRM_DEBUG_KMS("requested mode:\n");
9855
	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
12014
	drm_mode_debug_printmodeline(&pipe_config->base.mode);
9856
	DRM_DEBUG_KMS("adjusted mode:\n");
12015
	DRM_DEBUG_KMS("adjusted mode:\n");
9857
	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
12016
	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
9858
	intel_dump_crtc_timings(&pipe_config->adjusted_mode);
12017
	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
9859
	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12018
	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9860
	DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12019
	DRM_DEBUG_KMS("pipe src size: %dx%d\n",
-
 
12020
		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
-
 
12021
	DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
-
 
12022
		      crtc->num_scalers,
-
 
12023
		      pipe_config->scaler_state.scaler_users,
9861
		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12024
		      pipe_config->scaler_state.scaler_id);
9862
	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12025
	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9863
		      pipe_config->gmch_pfit.control,
12026
		      pipe_config->gmch_pfit.control,
9864
		      pipe_config->gmch_pfit.pgm_ratios,
12027
		      pipe_config->gmch_pfit.pgm_ratios,
9865
		      pipe_config->gmch_pfit.lvds_border_bits);
12028
		      pipe_config->gmch_pfit.lvds_border_bits);
9866
	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12029
	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9867
		      pipe_config->pch_pfit.pos,
12030
		      pipe_config->pch_pfit.pos,
9868
		      pipe_config->pch_pfit.size,
12031
		      pipe_config->pch_pfit.size,
9869
		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12032
		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9870
	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12033
	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9871
	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
-
 
Line -... Line 12034...
-
 
12034
	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
-
 
12035
 
-
 
12036
	if (IS_BROXTON(dev)) {
-
 
12037
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
-
 
12038
			      "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
-
 
12039
			      "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
-
 
12040
			      pipe_config->ddi_pll_sel,
-
 
12041
			      pipe_config->dpll_hw_state.ebb0,
-
 
12042
			      pipe_config->dpll_hw_state.ebb4,
-
 
12043
			      pipe_config->dpll_hw_state.pll0,
-
 
12044
			      pipe_config->dpll_hw_state.pll1,
-
 
12045
			      pipe_config->dpll_hw_state.pll2,
-
 
12046
			      pipe_config->dpll_hw_state.pll3,
-
 
12047
			      pipe_config->dpll_hw_state.pll6,
-
 
12048
			      pipe_config->dpll_hw_state.pll8,
-
 
12049
			      pipe_config->dpll_hw_state.pll9,
-
 
12050
			      pipe_config->dpll_hw_state.pll10,
-
 
12051
			      pipe_config->dpll_hw_state.pcsdw12);
-
 
12052
	} else if (IS_SKYLAKE(dev)) {
-
 
12053
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
-
 
12054
			      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
9872
}
12055
			      pipe_config->ddi_pll_sel,
9873
 
12056
			      pipe_config->dpll_hw_state.ctrl1,
-
 
12057
			      pipe_config->dpll_hw_state.cfgcr1,
-
 
12058
			      pipe_config->dpll_hw_state.cfgcr2);
-
 
12059
	} else if (HAS_DDI(dev)) {
-
 
12060
		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
-
 
12061
			      pipe_config->ddi_pll_sel,
9874
static bool encoders_cloneable(const struct intel_encoder *a,
12062
			      pipe_config->dpll_hw_state.wrpll,
9875
			       const struct intel_encoder *b)
12063
			      pipe_config->dpll_hw_state.spll);
-
 
12064
	} else {
9876
{
12065
		DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
-
 
12066
			      "fp0: 0x%x, fp1: 0x%x\n",
-
 
12067
			      pipe_config->dpll_hw_state.dpll,
9877
	/* masks could be asymmetric, so check both ways */
12068
			      pipe_config->dpll_hw_state.dpll_md,
9878
	return a == b || (a->cloneable & (1 << b->type) &&
12069
			      pipe_config->dpll_hw_state.fp0,
Line 9879... Line -...
9879
			  b->cloneable & (1 << a->type));
-
 
9880
}
12070
			      pipe_config->dpll_hw_state.fp1);
9881
 
-
 
9882
static bool check_single_encoder_cloning(struct intel_crtc *crtc,
12071
	}
9883
					 struct intel_encoder *encoder)
12072
 
9884
{
-
 
9885
	struct drm_device *dev = crtc->base.dev;
-
 
9886
	struct intel_encoder *source_encoder;
12073
	DRM_DEBUG_KMS("planes on this crtc\n");
9887
 
12074
	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
Line 9888... Line 12075...
9888
	for_each_intel_encoder(dev, source_encoder) {
12075
		intel_plane = to_intel_plane(plane);
9889
		if (source_encoder->new_crtc != crtc)
12076
		if (intel_plane->pipe != crtc->pipe)
9890
			continue;
-
 
9891
 
-
 
9892
		if (!encoders_cloneable(encoder, source_encoder))
12077
			continue;
9893
			return false;
-
 
9894
	}
-
 
9895
 
12078
 
9896
	return true;
-
 
9897
}
12079
		state = to_intel_plane_state(plane->state);
-
 
12080
		fb = state->base.fb;
9898
 
12081
		if (!fb) {
9899
static bool check_encoder_cloning(struct intel_crtc *crtc)
-
 
9900
{
12082
			DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
9901
	struct drm_device *dev = crtc->base.dev;
12083
				"disabled, scaler_id = %d\n",
9902
	struct intel_encoder *encoder;
12084
				plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
9903
 
-
 
9904
	for_each_intel_encoder(dev, encoder) {
-
 
9905
		if (encoder->new_crtc != crtc)
-
 
9906
			continue;
12085
				plane->base.id, intel_plane->pipe,
Line -... Line 12086...
-
 
12086
				(crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
-
 
12087
				drm_plane_index(plane), state->scaler_id);
-
 
12088
			continue;
-
 
12089
		}
-
 
12090
 
-
 
12091
		DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
-
 
12092
			plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
-
 
12093
			plane->base.id, intel_plane->pipe,
9907
 
12094
			crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
-
 
12095
			drm_plane_index(plane));
-
 
12096
		DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
-
 
12097
			fb->base.id, fb->width, fb->height, fb->pixel_format);
-
 
12098
		DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
-
 
12099
			state->scaler_id,
-
 
12100
			state->src.x1 >> 16, state->src.y1 >> 16,
9908
		if (!check_single_encoder_cloning(crtc, encoder))
12101
			drm_rect_width(&state->src) >> 16,
Line 9909... Line 12102...
9909
			return false;
12102
			drm_rect_height(&state->src) >> 16,
9910
	}
12103
			state->dst.x1, state->dst.y1,
-
 
12104
			drm_rect_width(&state->dst), drm_rect_height(&state->dst));
9911
 
12105
	}
9912
	return true;
12106
}
Line 9913... Line 12107...
9913
}
12107
 
9914
 
12108
static bool check_digital_port_conflicts(struct drm_atomic_state *state)
9915
static bool check_digital_port_conflicts(struct drm_device *dev)
12109
{
9916
{
12110
	struct drm_device *dev = state->dev;
9917
	struct intel_connector *connector;
12111
	struct drm_connector *connector;
9918
	unsigned int used_ports = 0;
12112
	unsigned int used_ports = 0;
9919
 
12113
 
9920
	/*
12114
	/*
Line -... Line 12115...
-
 
12115
	 * Walk the connector list instead of the encoder
9921
	 * Walk the connector list instead of the encoder
12116
	 * list to detect the problem on ddi platforms
-
 
12117
	 * where there's just one encoder per digital port.
-
 
12118
	 */
-
 
12119
	drm_for_each_connector(connector, dev) {
9922
	 * list to detect the problem on ddi platforms
12120
		struct drm_connector_state *connector_state;
Line -... Line 12121...
-
 
12121
		struct intel_encoder *encoder;
-
 
12122
 
9923
	 * where there's just one encoder per digital port.
12123
		connector_state = drm_atomic_get_existing_connector_state(state, connector);
Line 9924... Line 12124...
9924
	 */
12124
		if (!connector_state)
9925
	list_for_each_entry(connector,
12125
			connector_state = connector->state;
9926
			    &dev->mode_config.connector_list, base.head) {
12126
 
9927
		struct intel_encoder *encoder = connector->new_encoder;
12127
		if (!connector_state->best_encoder)
Line 9952... Line 12152...
9952
	}
12152
	}
Line 9953... Line 12153...
9953
 
12153
 
9954
	return true;
12154
	return true;
Line -... Line 12155...
-
 
12155
}
-
 
12156
 
-
 
12157
static void
-
 
12158
clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
9955
}
12159
{
-
 
12160
	struct drm_crtc_state tmp_state;
-
 
12161
	struct intel_crtc_scaler_state scaler_state;
-
 
12162
	struct intel_dpll_hw_state dpll_hw_state;
-
 
12163
	enum intel_dpll_id shared_dpll;
-
 
12164
	uint32_t ddi_pll_sel;
-
 
12165
	bool force_thru;
-
 
12166
 
-
 
12167
	/* FIXME: before the switch to atomic started, a new pipe_config was
-
 
12168
	 * kzalloc'd. Code that depends on any field being zero should be
-
 
12169
	 * fixed, so that the crtc_state can be safely duplicated. For now,
-
 
12170
	 * only fields that are know to not cause problems are preserved. */
-
 
12171
 
-
 
12172
	tmp_state = crtc_state->base;
-
 
12173
	scaler_state = crtc_state->scaler_state;
-
 
12174
	shared_dpll = crtc_state->shared_dpll;
-
 
12175
	dpll_hw_state = crtc_state->dpll_hw_state;
-
 
12176
	ddi_pll_sel = crtc_state->ddi_pll_sel;
-
 
12177
	force_thru = crtc_state->pch_pfit.force_thru;
-
 
12178
 
-
 
12179
	memset(crtc_state, 0, sizeof *crtc_state);
-
 
12180
 
-
 
12181
	crtc_state->base = tmp_state;
-
 
12182
	crtc_state->scaler_state = scaler_state;
-
 
12183
	crtc_state->shared_dpll = shared_dpll;
-
 
12184
	crtc_state->dpll_hw_state = dpll_hw_state;
-
 
12185
	crtc_state->ddi_pll_sel = ddi_pll_sel;
-
 
12186
	crtc_state->pch_pfit.force_thru = force_thru;
-
 
12187
}
9956
 
12188
 
9957
static struct intel_crtc_config *
12189
static int
9958
intel_modeset_pipe_config(struct drm_crtc *crtc,
-
 
9959
			  struct drm_framebuffer *fb,
12190
intel_modeset_pipe_config(struct drm_crtc *crtc,
9960
			    struct drm_display_mode *mode)
12191
			  struct intel_crtc_state *pipe_config)
9961
{
12192
{
9962
	struct drm_device *dev = crtc->dev;
12193
	struct drm_atomic_state *state = pipe_config->base.state;
-
 
12194
	struct intel_encoder *encoder;
9963
	struct intel_encoder *encoder;
12195
	struct drm_connector *connector;
-
 
12196
	struct drm_connector_state *connector_state;
9964
	struct intel_crtc_config *pipe_config;
12197
	int base_bpp, ret = -EINVAL;
Line 9965... Line -...
9965
	int plane_bpp, ret = -EINVAL;
-
 
9966
	bool retry = true;
-
 
9967
 
-
 
9968
	if (!check_encoder_cloning(to_intel_crtc(crtc))) {
-
 
9969
		DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
-
 
9970
		return ERR_PTR(-EINVAL);
-
 
9971
	}
-
 
9972
 
-
 
9973
	if (!check_digital_port_conflicts(dev)) {
-
 
9974
		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
-
 
9975
		return ERR_PTR(-EINVAL);
12198
	int i;
9976
	}
-
 
9977
 
-
 
9978
	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
-
 
9979
	if (!pipe_config)
-
 
9980
		return ERR_PTR(-ENOMEM);
-
 
Line 9981... Line 12199...
9981
 
12199
	bool retry = true;
9982
	drm_mode_copy(&pipe_config->adjusted_mode, mode);
12200
 
9983
	drm_mode_copy(&pipe_config->requested_mode, mode);
-
 
Line 9984... Line 12201...
9984
 
12201
	clear_intel_crtc_state(pipe_config);
9985
	pipe_config->cpu_transcoder =
12202
 
9986
		(enum transcoder) to_intel_crtc(crtc)->pipe;
12203
	pipe_config->cpu_transcoder =
9987
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
12204
		(enum transcoder) to_intel_crtc(crtc)->pipe;
9988
 
12205
 
9989
	/*
12206
	/*
9990
	 * Sanitize sync polarity flags based on requested ones. If neither
12207
	 * Sanitize sync polarity flags based on requested ones. If neither
9991
	 * positive or negative polarity is requested, treat this as meaning
12208
	 * positive or negative polarity is requested, treat this as meaning
Line 9992... Line 12209...
9992
	 * negative polarity.
12209
	 * negative polarity.
9993
	 */
12210
	 */
9994
	if (!(pipe_config->adjusted_mode.flags &
12211
	if (!(pipe_config->base.adjusted_mode.flags &
Line 9995... Line -...
9995
	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-
 
9996
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
-
 
9997
 
-
 
9998
	if (!(pipe_config->adjusted_mode.flags &
-
 
9999
	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12212
	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10000
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12213
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10001
 
12214
 
10002
	/* Compute a starting value for pipe_config->pipe_bpp taking the source
12215
	if (!(pipe_config->base.adjusted_mode.flags &
Line 10003... Line 12216...
10003
	 * plane pixel format and any sink constraints into account. Returns the
12216
	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10004
	 * source plane bpp so that dithering can be selected on mismatches
12217
		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10005
	 * after encoders and crtc also have had their say. */
12218
 
10006
	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12219
	base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10007
					      fb, pipe_config);
12220
					     pipe_config);
10008
	if (plane_bpp < 0)
12221
	if (base_bpp < 0)
10009
		goto fail;
12222
		goto fail;
10010
 
12223
 
10011
	/*
12224
	/*
10012
	 * Determine the real pipe dimensions. Note that stereo modes can
12225
	 * Determine the real pipe dimensions. Note that stereo modes can
10013
	 * increase the actual pipe size due to the frame doubling and
12226
	 * increase the actual pipe size due to the frame doubling and
Line 10014... Line 12227...
10014
	 * insertion of additional space for blanks between the frame. This
12227
	 * insertion of additional space for blanks between the frame. This
10015
	 * is stored in the crtc timings. We use the requested mode to do this
12228
	 * is stored in the crtc timings. We use the requested mode to do this
10016
	 * computation to clearly distinguish it from the adjusted mode, which
12229
	 * computation to clearly distinguish it from the adjusted mode, which
10017
	 * can be changed by the connectors in the below retry loop.
12230
	 * can be changed by the connectors in the below retry loop.
Line 10018... Line 12231...
10018
	 */
12231
	 */
10019
	drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
12232
	drm_crtc_get_hv_timing(&pipe_config->base.mode,
-
 
12233
			       &pipe_config->pipe_src_w,
Line 10020... Line 12234...
10020
	pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
12234
			       &pipe_config->pipe_src_h);
10021
	pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
12235
 
10022
 
12236
encoder_retry:
10023
encoder_retry:
12237
	/* Ensure the port clock defaults are reset when retrying. */
10024
	/* Ensure the port clock defaults are reset when retrying. */
12238
	pipe_config->port_clock = 0;
10025
	pipe_config->port_clock = 0;
-
 
10026
	pipe_config->pixel_multiplier = 1;
12239
	pipe_config->pixel_multiplier = 1;
10027
 
12240
 
Line -... Line 12241...
-
 
12241
	/* Fill in default crtc timings, allow encoders to overwrite them. */
-
 
12242
	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10028
	/* Fill in default crtc timings, allow encoders to overwrite them. */
12243
			      CRTC_STEREO_DOUBLE);
10029
	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
12244
 
10030
 
12245
	/* Pass our mode to the connectors and the CRTC to give them a chance to
10031
	/* Pass our mode to the connectors and the CRTC to give them a chance to
12246
	 * adjust it according to limitations or connector properties, and also
10032
	 * adjust it according to limitations or connector properties, and also
12247
	 * a chance to reject the mode entirely.
Line 10033... Line 12248...
10033
	 * a chance to reject the mode entirely.
12248
	 */
10034
	 */
12249
	for_each_connector_in_state(state, connector, connector_state, i) {
10035
	for_each_intel_encoder(dev, encoder) {
12250
		if (connector_state->crtc != crtc)
10036
 
12251
			continue;
10037
		if (&encoder->new_crtc->base != crtc)
12252
 
Line 10038... Line 12253...
10038
			continue;
12253
		encoder = to_intel_encoder(connector_state->best_encoder);
10039
 
12254
 
10040
			if (!(encoder->compute_config(encoder, pipe_config))) {
12255
		if (!(encoder->compute_config(encoder, pipe_config))) {
Line 10064... Line 12279...
10064
		DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12279
		DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10065
		retry = false;
12280
		retry = false;
10066
		goto encoder_retry;
12281
		goto encoder_retry;
10067
	}
12282
	}
Line -... Line 12283...
-
 
12283
 
-
 
12284
	/* Dithering seems to not pass-through bits correctly when it should, so
10068
 
12285
	 * only enable it on 6bpc panels. */
10069
	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
12286
	pipe_config->dither = pipe_config->pipe_bpp == 6*3;
10070
	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12287
	DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
Line 10071... Line -...
10071
		      plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
-
 
10072
 
12288
		      base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10073
	return pipe_config;
-
 
10074
fail:
12289
 
10075
	kfree(pipe_config);
12290
fail:
Line 10076... Line -...
10076
	return ERR_PTR(ret);
-
 
10077
}
-
 
10078
 
12291
	return ret;
10079
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
12292
}
10080
 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
-
 
10081
static void
12293
 
10082
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
12294
static void
10083
			     unsigned *prepare_pipes, unsigned *disable_pipes)
-
 
10084
{
-
 
10085
	struct intel_crtc *intel_crtc;
-
 
10086
	struct drm_device *dev = crtc->dev;
12295
intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10087
	struct intel_encoder *encoder;
-
 
10088
	struct intel_connector *connector;
-
 
10089
	struct drm_crtc *tmp_crtc;
-
 
10090
 
-
 
10091
	*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
-
 
10092
 
-
 
10093
	/* Check which crtcs have changed outputs connected to them, these need
-
 
10094
	 * to be part of the prepare_pipes mask. We don't (yet) support global
-
 
10095
	 * modeset across multiple crtcs, so modeset_pipes will only have one
-
 
10096
	 * bit set at most. */
-
 
10097
	list_for_each_entry(connector, &dev->mode_config.connector_list,
-
 
10098
			    base.head) {
-
 
10099
		if (connector->base.encoder == &connector->new_encoder->base)
-
 
10100
			continue;
-
 
10101
 
-
 
10102
		if (connector->base.encoder) {
-
 
10103
			tmp_crtc = connector->base.encoder->crtc;
-
 
10104
 
-
 
10105
			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
-
 
10106
		}
-
 
10107
 
-
 
10108
		if (connector->new_encoder)
-
 
10109
			*prepare_pipes |=
-
 
10110
				1 << connector->new_encoder->new_crtc->pipe;
-
 
10111
	}
-
 
10112
 
12296
{
10113
	for_each_intel_encoder(dev, encoder) {
-
 
10114
		if (encoder->base.crtc == &encoder->new_crtc->base)
-
 
10115
			continue;
-
 
10116
 
-
 
10117
		if (encoder->base.crtc) {
-
 
10118
			tmp_crtc = encoder->base.crtc;
-
 
10119
 
-
 
10120
			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
-
 
10121
		}
-
 
10122
 
-
 
Line 10123... Line 12297...
10123
		if (encoder->new_crtc)
12297
	struct drm_crtc *crtc;
10124
			*prepare_pipes |= 1 << encoder->new_crtc->pipe;
12298
	struct drm_crtc_state *crtc_state;
10125
	}
12299
	int i;
10126
 
-
 
Line -... Line 12300...
-
 
12300
 
10127
	/* Check for pipes that will be enabled/disabled ... */
12301
	/* Double check state. */
10128
	for_each_intel_crtc(dev, intel_crtc) {
12302
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
10129
		if (intel_crtc->base.enabled == intel_crtc->new_enabled)
12303
		to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
10130
			continue;
12304
 
10131
 
12305
		/* Update hwmode for vblank functions */
10132
		if (!intel_crtc->new_enabled)
-
 
10133
			*disable_pipes |= 1 << intel_crtc->pipe;
-
 
10134
		else
-
 
10135
			*prepare_pipes |= 1 << intel_crtc->pipe;
-
 
10136
	}
-
 
10137
 
-
 
10138
 
-
 
10139
	/* set_mode is also used to update properties on life display pipes. */
-
 
10140
	intel_crtc = to_intel_crtc(crtc);
-
 
10141
	if (intel_crtc->new_enabled)
-
 
10142
		*prepare_pipes |= 1 << intel_crtc->pipe;
-
 
10143
 
-
 
10144
	/*
-
 
10145
	 * For simplicity do a full modeset on any pipe where the output routing
-
 
10146
	 * changed. We could be more clever, but that would require us to be
-
 
10147
	 * more careful with calling the relevant encoder->mode_set functions.
-
 
10148
	 */
-
 
10149
	if (*prepare_pipes)
-
 
10150
		*modeset_pipes = *prepare_pipes;
-
 
10151
 
-
 
10152
	/* ... and mask these out. */
-
 
10153
	*modeset_pipes &= ~(*disable_pipes);
-
 
10154
	*prepare_pipes &= ~(*disable_pipes);
-
 
10155
 
-
 
10156
	/*
-
 
10157
	 * HACK: We don't (yet) fully support global modesets. intel_set_config
-
 
10158
	 * obies this rule, but the modeset restore mode of
-
 
10159
	 * intel_modeset_setup_hw_state does not.
-
 
10160
	 */
-
 
10161
	*modeset_pipes &= 1 << intel_crtc->pipe;
12306
		if (crtc->state->active)
Line 10162... Line 12307...
10162
	*prepare_pipes &= 1 << intel_crtc->pipe;
12307
			crtc->hwmode = crtc->state->adjusted_mode;
10163
 
12308
		else
10164
	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
12309
			crtc->hwmode.crtc_clock = 0;
10165
		      *modeset_pipes, *prepare_pipes, *disable_pipes);
-
 
Line 10166... Line -...
10166
}
-
 
10167
 
12310
	}
10168
static bool intel_crtc_in_use(struct drm_crtc *crtc)
12311
}
Line -... Line 12312...
-
 
12312
 
10169
{
12313
static bool intel_fuzzy_clock_check(int clock1, int clock2)
10170
	struct drm_encoder *encoder;
-
 
10171
	struct drm_device *dev = crtc->dev;
-
 
10172
 
-
 
10173
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
-
 
10174
		if (encoder->crtc == crtc)
-
 
10175
			return true;
-
 
10176
 
-
 
10177
	return false;
-
 
10178
}
-
 
10179
 
-
 
10180
static void
-
 
10181
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
-
 
10182
{
-
 
10183
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
10184
	struct intel_encoder *intel_encoder;
-
 
Line 10185... Line -...
10185
	struct intel_crtc *intel_crtc;
-
 
10186
	struct drm_connector *connector;
-
 
10187
 
12314
{
10188
	intel_shared_dpll_commit(dev_priv);
-
 
10189
 
-
 
Line 10190... Line 12315...
10190
	for_each_intel_encoder(dev, intel_encoder) {
12315
	int diff;
-
 
12316
 
Line 10191... Line 12317...
10191
		if (!intel_encoder->base.crtc)
12317
	if (clock1 == clock2)
10192
			continue;
-
 
10193
 
-
 
10194
		intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
-
 
10195
 
-
 
10196
		if (prepare_pipes & (1 << intel_crtc->pipe))
-
 
10197
			intel_encoder->connectors_active = false;
12318
		return true;
Line 10198... Line 12319...
10198
	}
12319
 
-
 
12320
	if (!clock1 || !clock2)
10199
 
12321
		return false;
10200
	intel_modeset_commit_output_state(dev);
12322
 
-
 
12323
	diff = abs(clock1 - clock2);
Line -... Line 12324...
-
 
12324
 
10201
 
12325
	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
-
 
12326
		return true;
-
 
12327
 
-
 
12328
	return false;
-
 
12329
}
-
 
12330
 
Line 10202... Line 12331...
10202
	/* Double check state. */
12331
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10203
	for_each_intel_crtc(dev, intel_crtc) {
-
 
10204
		WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
12332
	list_for_each_entry((intel_crtc), \
Line 10205... Line 12333...
10205
		WARN_ON(intel_crtc->new_config &&
12333
			    &(dev)->mode_config.crtc_list, \
10206
			intel_crtc->new_config != &intel_crtc->config);
-
 
10207
		WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
-
 
10208
	}
-
 
Line -... Line 12334...
-
 
12334
			    base.head) \
10209
 
12335
		if (mask & (1 <<(intel_crtc)->pipe))
-
 
12336
 
10210
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12337
static bool
10211
		if (!connector->encoder || !connector->encoder->crtc)
12338
intel_compare_m_n(unsigned int m, unsigned int n,
-
 
12339
		  unsigned int m2, unsigned int n2,
-
 
12340
		  bool exact)
-
 
12341
{
-
 
12342
	if (m == m2 && n == n2)
10212
			continue;
12343
		return true;
10213
 
-
 
10214
		intel_crtc = to_intel_crtc(connector->encoder->crtc);
12344
 
Line 10215... Line -...
10215
 
-
 
10216
		if (prepare_pipes & (1 << intel_crtc->pipe)) {
-
 
10217
			struct drm_property *dpms_property =
-
 
10218
				dev->mode_config.dpms_property;
-
 
10219
 
12345
	if (exact || !m || !n || !m2 || !n2)
10220
			connector->dpms = DRM_MODE_DPMS_ON;
-
 
10221
			drm_object_property_set_value(&connector->base,
12346
		return false;
10222
							 dpms_property,
-
 
10223
							 DRM_MODE_DPMS_ON);
-
 
Line -... Line 12347...
-
 
12347
 
-
 
12348
	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
-
 
12349
 
10224
 
12350
	if (m > m2) {
-
 
12351
		while (m > m2) {
-
 
12352
			m2 <<= 1;
-
 
12353
			n2 <<= 1;
-
 
12354
		}
-
 
12355
	} else if (m < m2) {
-
 
12356
		while (m < m2) {
-
 
12357
			m <<= 1;
-
 
12358
			n <<= 1;
Line 10225... Line -...
10225
			intel_encoder = to_intel_encoder(connector->encoder);
-
 
10226
			intel_encoder->connectors_active = true;
12359
		}
-
 
12360
	}
Line 10227... Line 12361...
10227
		}
12361
 
10228
	}
12362
	return m == m2 && n == n2;
Line 10229... Line -...
10229
 
-
 
10230
}
-
 
10231
 
-
 
10232
static bool intel_fuzzy_clock_check(int clock1, int clock2)
-
 
10233
{
-
 
10234
	int diff;
-
 
10235
 
12363
}
10236
	if (clock1 == clock2)
12364
 
10237
		return true;
12365
static bool
10238
 
12366
intel_compare_link_m_n(const struct intel_link_m_n *m_n,
-
 
12367
		       struct intel_link_m_n *m2_n2,
10239
	if (!clock1 || !clock2)
12368
		       bool adjust)
-
 
12369
{
-
 
12370
	if (m_n->tu == m2_n2->tu &&
-
 
12371
	    intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
-
 
12372
			      m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
-
 
12373
	    intel_compare_m_n(m_n->link_m, m_n->link_n,
-
 
12374
			      m2_n2->link_m, m2_n2->link_n, !adjust)) {
-
 
12375
		if (adjust)
-
 
12376
			*m2_n2 = *m_n;
-
 
12377
 
-
 
12378
		return true;
10240
		return false;
12379
	}
10241
 
12380
 
10242
	diff = abs(clock1 - clock2);
12381
	return false;
10243
 
12382
}
10244
	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12383
 
10245
		return true;
12384
static bool
10246
 
12385
intel_pipe_config_compare(struct drm_device *dev,
10247
	return false;
12386
			  struct intel_crtc_state *current_config,
Line 10248... Line 12387...
10248
}
12387
			  struct intel_crtc_state *pipe_config,
10249
 
12388
			  bool adjust)
10250
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12389
{
10251
	list_for_each_entry((intel_crtc), \
12390
	bool ret = true;
10252
			    &(dev)->mode_config.crtc_list, \
12391
 
10253
			    base.head) \
12392
#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
-
 
12393
	do { \
-
 
12394
		if (!adjust) \
-
 
12395
			DRM_ERROR(fmt, ##__VA_ARGS__); \
-
 
12396
		else \
-
 
12397
			DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
-
 
12398
	} while (0)
-
 
12399
 
-
 
12400
#define PIPE_CONF_CHECK_X(name)	\
-
 
12401
	if (current_config->name != pipe_config->name) { \
-
 
12402
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
-
 
12403
			  "(expected 0x%08x, found 0x%08x)\n", \
-
 
12404
			  current_config->name, \
-
 
12405
			  pipe_config->name); \
-
 
12406
		ret = false; \
-
 
12407
	}
-
 
12408
 
-
 
12409
#define PIPE_CONF_CHECK_I(name)	\
-
 
12410
	if (current_config->name != pipe_config->name) { \
-
 
12411
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
-
 
12412
			  "(expected %i, found %i)\n", \
-
 
12413
			  current_config->name, \
-
 
12414
			  pipe_config->name); \
-
 
12415
		ret = false; \
-
 
12416
	}
-
 
12417
 
-
 
12418
#define PIPE_CONF_CHECK_M_N(name) \
-
 
12419
	if (!intel_compare_link_m_n(¤t_config->name, \
-
 
12420
				    &pipe_config->name,\
-
 
12421
				    adjust)) { \
-
 
12422
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
-
 
12423
			  "(expected tu %i gmch %i/%i link %i/%i, " \
-
 
12424
			  "found tu %i, gmch %i/%i link %i/%i)\n", \
-
 
12425
			  current_config->name.tu, \
-
 
12426
			  current_config->name.gmch_m, \
-
 
12427
			  current_config->name.gmch_n, \
-
 
12428
			  current_config->name.link_m, \
-
 
12429
			  current_config->name.link_n, \
-
 
12430
			  pipe_config->name.tu, \
-
 
12431
			  pipe_config->name.gmch_m, \
-
 
12432
			  pipe_config->name.gmch_n, \
-
 
12433
			  pipe_config->name.link_m, \
-
 
12434
			  pipe_config->name.link_n); \
-
 
12435
		ret = false; \
-
 
12436
	}
-
 
12437
 
-
 
12438
#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
-
 
12439
	if (!intel_compare_link_m_n(¤t_config->name, \
10254
		if (mask & (1 <<(intel_crtc)->pipe))
12440
				    &pipe_config->name, adjust) && \
10255
 
12441
	    !intel_compare_link_m_n(¤t_config->alt_name, \
Line 10256... Line 12442...
10256
static bool
12442
				    &pipe_config->name, adjust)) { \
10257
intel_pipe_config_compare(struct drm_device *dev,
12443
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
10258
			  struct intel_crtc_config *current_config,
12444
			  "(expected tu %i gmch %i/%i link %i/%i, " \
10259
			  struct intel_crtc_config *pipe_config)
12445
			  "or tu %i gmch %i/%i link %i/%i, " \
10260
{
12446
			  "found tu %i, gmch %i/%i link %i/%i)\n", \
10261
#define PIPE_CONF_CHECK_X(name)	\
12447
			  current_config->name.tu, \
10262
	if (current_config->name != pipe_config->name) { \
12448
			  current_config->name.gmch_m, \
10263
		DRM_ERROR("mismatch in " #name " " \
12449
			  current_config->name.gmch_n, \
10264
			  "(expected 0x%08x, found 0x%08x)\n", \
12450
			  current_config->name.link_m, \
10265
			  current_config->name, \
12451
			  current_config->name.link_n, \
10266
			  pipe_config->name); \
12452
			  current_config->alt_name.tu, \
10267
		return false; \
12453
			  current_config->alt_name.gmch_m, \
10268
	}
12454
			  current_config->alt_name.gmch_n, \
10269
 
12455
			  current_config->alt_name.link_m, \
10270
#define PIPE_CONF_CHECK_I(name)	\
12456
			  current_config->alt_name.link_n, \
Line 10271... Line 12457...
10271
	if (current_config->name != pipe_config->name) { \
12457
			  pipe_config->name.tu, \
10272
		DRM_ERROR("mismatch in " #name " " \
12458
			  pipe_config->name.gmch_m, \
10273
			  "(expected %i, found %i)\n", \
12459
			  pipe_config->name.gmch_n, \
10274
			  current_config->name, \
12460
			  pipe_config->name.link_m, \
10275
			  pipe_config->name); \
12461
			  pipe_config->name.link_n); \
10276
		return false; \
12462
		ret = false; \
10277
	}
12463
	}
10278
 
12464
 
Line 10279... Line 12465...
10279
/* This is required for BDW+ where there is only one set of registers for
12465
/* This is required for BDW+ where there is only one set of registers for
10280
 * switching between high and low RR.
12466
 * switching between high and low RR.
10281
 * This macro can be used whenever a comparison has to be made between one
12467
 * This macro can be used whenever a comparison has to be made between one
10282
 * hw state and multiple sw state variables.
12468
 * hw state and multiple sw state variables.
10283
 */
12469
 */
10284
#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12470
#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10285
	if ((current_config->name != pipe_config->name) && \
12471
	if ((current_config->name != pipe_config->name) && \
10286
		(current_config->alt_name != pipe_config->name)) { \
12472
		(current_config->alt_name != pipe_config->name)) { \
Line 10287... Line 12473...
10287
			DRM_ERROR("mismatch in " #name " " \
12473
			INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
10288
				  "(expected %i or %i, found %i)\n", \
12474
				  "(expected %i or %i, found %i)\n", \
Line 10289... Line 12475...
10289
				  current_config->name, \
12475
				  current_config->name, \
Line 10290... Line 12476...
10290
				  current_config->alt_name, \
12476
				  current_config->alt_name, \
10291
				  pipe_config->name); \
12477
				  pipe_config->name); \
10292
			return false; \
-
 
10293
	}
-
 
10294
 
-
 
10295
#define PIPE_CONF_CHECK_FLAGS(name, mask)	\
-
 
10296
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
12478
			ret = false; \
Line 10297... Line 12479...
10297
		DRM_ERROR("mismatch in " #name "(" #mask ") "	   \
12479
	}
-
 
12480
 
Line 10298... Line 12481...
10298
			  "(expected %i, found %i)\n", \
12481
#define PIPE_CONF_CHECK_FLAGS(name, mask)	\
10299
			  current_config->name & (mask), \
-
 
10300
			  pipe_config->name & (mask)); \
-
 
10301
		return false; \
-
 
10302
	}
-
 
10303
 
12482
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
10304
#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12483
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
10305
	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12484
			  "(expected %i, found %i)\n", \
10306
		DRM_ERROR("mismatch in " #name " " \
-
 
10307
			  "(expected %i, found %i)\n", \
-
 
10308
			  current_config->name, \
-
 
10309
			  pipe_config->name); \
-
 
10310
		return false; \
12485
			  current_config->name & (mask), \
10311
	}
-
 
10312
 
12486
			  pipe_config->name & (mask)); \
10313
#define PIPE_CONF_QUIRK(quirk)	\
-
 
10314
	((current_config->quirks | pipe_config->quirks) & (quirk))
-
 
10315
 
-
 
10316
	PIPE_CONF_CHECK_I(cpu_transcoder);
-
 
10317
 
12487
		ret = false; \
10318
	PIPE_CONF_CHECK_I(has_pch_encoder);
-
 
10319
	PIPE_CONF_CHECK_I(fdi_lanes);
12488
	}
10320
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12489
 
10321
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12490
#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10322
	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12491
	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10323
	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12492
		INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
10324
	PIPE_CONF_CHECK_I(fdi_m_n.tu);
12493
			  "(expected %i, found %i)\n", \
10325
 
12494
			  current_config->name, \
10326
	PIPE_CONF_CHECK_I(has_dp_encoder);
12495
			  pipe_config->name); \
10327
 
12496
		ret = false; \
10328
	if (INTEL_INFO(dev)->gen < 8) {
12497
	}
10329
	PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12498
 
10330
	PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12499
#define PIPE_CONF_QUIRK(quirk)	\
10331
	PIPE_CONF_CHECK_I(dp_m_n.link_m);
12500
	((current_config->quirks | pipe_config->quirks) & (quirk))
10332
	PIPE_CONF_CHECK_I(dp_m_n.link_n);
12501
 
Line 10333... Line 12502...
10333
	PIPE_CONF_CHECK_I(dp_m_n.tu);
12502
	PIPE_CONF_CHECK_I(cpu_transcoder);
10334
 
12503
 
10335
		if (current_config->has_drrs) {
12504
	PIPE_CONF_CHECK_I(has_pch_encoder);
10336
			PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12505
	PIPE_CONF_CHECK_I(fdi_lanes);
10337
			PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12506
	PIPE_CONF_CHECK_M_N(fdi_m_n);
10338
			PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12507
 
Line 10339... Line 12508...
10339
			PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12508
	PIPE_CONF_CHECK_I(has_dp_encoder);
Line 10340... Line 12509...
10340
			PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12509
	PIPE_CONF_CHECK_I(lane_count);
10341
		}
12510
 
Line 10342... Line 12511...
10342
	} else {
12511
	if (INTEL_INFO(dev)->gen < 8) {
10343
		PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12512
		PIPE_CONF_CHECK_M_N(dp_m_n);
10344
		PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12513
 
10345
		PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12514
		if (current_config->has_drrs)
10346
		PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12515
			PIPE_CONF_CHECK_M_N(dp_m2_n2);
10347
		PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12516
	} else
10348
	}
12517
		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
10349
 
12518
 
10350
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
12519
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10351
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
12520
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
Line 10352... Line -...
10352
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
-
 
10353
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
-
 
10354
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
-
 
10355
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
-
 
10356
 
-
 
10357
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
-
 
10358
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
-
 
10359
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
-
 
10360
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
-
 
10361
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
-
 
10362
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
-
 
10363
 
-
 
10364
		PIPE_CONF_CHECK_I(pixel_multiplier);
12521
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10365
	PIPE_CONF_CHECK_I(has_hdmi_sink);
12522
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10366
	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12523
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10367
	    IS_VALLEYVIEW(dev))
12524
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10368
		PIPE_CONF_CHECK_I(limited_color_range);
12525
 
10369
	PIPE_CONF_CHECK_I(has_infoframe);
12526
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
-
 
12527
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
-
 
12528
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
-
 
12529
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
Line 10370... Line 12530...
10370
 
12530
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10371
	PIPE_CONF_CHECK_I(has_audio);
12531
	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10372
 
12532
 
10373
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
12533
	PIPE_CONF_CHECK_I(pixel_multiplier);
-
 
12534
	PIPE_CONF_CHECK_I(has_hdmi_sink);
-
 
12535
	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
-
 
12536
	    IS_VALLEYVIEW(dev))
10374
			      DRM_MODE_FLAG_INTERLACE);
12537
		PIPE_CONF_CHECK_I(limited_color_range);
Line 10375... Line 12538...
10375
 
12538
	PIPE_CONF_CHECK_I(has_infoframe);
10376
	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12539
 
10377
		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
12540
	PIPE_CONF_CHECK_I(has_audio);
Line 10421... Line 12584...
10421
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12584
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10422
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12585
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10423
	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12586
	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10424
	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12587
	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10425
	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12588
	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
-
 
12589
	PIPE_CONF_CHECK_X(dpll_hw_state.spll);
10426
	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12590
	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10427
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12591
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10428
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12592
	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
Line 10429... Line 12593...
10429
 
12593
 
10430
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12594
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
Line 10431... Line 12595...
10431
		PIPE_CONF_CHECK_I(pipe_bpp);
12595
		PIPE_CONF_CHECK_I(pipe_bpp);
10432
 
12596
 
Line 10433... Line 12597...
10433
		PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
12597
	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10434
		PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12598
	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10435
 
12599
 
10436
#undef PIPE_CONF_CHECK_X
12600
#undef PIPE_CONF_CHECK_X
10437
#undef PIPE_CONF_CHECK_I
12601
#undef PIPE_CONF_CHECK_I
10438
#undef PIPE_CONF_CHECK_I_ALT
12602
#undef PIPE_CONF_CHECK_I_ALT
-
 
12603
#undef PIPE_CONF_CHECK_FLAGS
Line 10439... Line 12604...
10439
#undef PIPE_CONF_CHECK_FLAGS
12604
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10440
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
12605
#undef PIPE_CONF_QUIRK
Line 10441... Line 12606...
10441
#undef PIPE_CONF_QUIRK
12606
#undef INTEL_ERR_OR_DBG_KMS
10442
 
12607
 
10443
	return true;
12608
	return ret;
Line 10462... Line 12627...
10462
 
12627
 
10463
		if (!intel_crtc->active)
12628
		if (!intel_crtc->active)
Line 10464... Line 12629...
10464
			continue;
12629
			continue;
10465
 
12630
 
10466
		/* planes */
12631
		/* planes */
10467
		for_each_plane(pipe, plane) {
12632
		for_each_plane(dev_priv, pipe, plane) {
Line 10468... Line 12633...
10468
			hw_entry = &hw_ddb.plane[pipe][plane];
12633
			hw_entry = &hw_ddb.plane[pipe][plane];
10469
			sw_entry = &sw_ddb->plane[pipe][plane];
12634
			sw_entry = &sw_ddb->plane[pipe][plane];
Line 10477... Line 12642...
10477
				  sw_entry->start, sw_entry->end,
12642
				  sw_entry->start, sw_entry->end,
10478
				  hw_entry->start, hw_entry->end);
12643
				  hw_entry->start, hw_entry->end);
10479
		}
12644
		}
Line 10480... Line 12645...
10480
 
12645
 
10481
		/* cursor */
12646
		/* cursor */
10482
		hw_entry = &hw_ddb.cursor[pipe];
12647
		hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
Line 10483... Line 12648...
10483
		sw_entry = &sw_ddb->cursor[pipe];
12648
		sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
10484
 
12649
 
Line 10485... Line 12650...
10485
		if (skl_ddb_entry_equal(hw_entry, sw_entry))
12650
		if (skl_ddb_entry_equal(hw_entry, sw_entry))
Line 10492... Line 12657...
10492
			  hw_entry->start, hw_entry->end);
12657
			  hw_entry->start, hw_entry->end);
10493
	}
12658
	}
10494
}
12659
}
Line 10495... Line 12660...
10495
 
12660
 
10496
static void
12661
static void
-
 
12662
check_connector_state(struct drm_device *dev,
10497
check_connector_state(struct drm_device *dev)
12663
		      struct drm_atomic_state *old_state)
-
 
12664
{
10498
{
12665
	struct drm_connector_state *old_conn_state;
-
 
12666
	struct drm_connector *connector;
-
 
12667
	int i;
-
 
12668
 
-
 
12669
	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
-
 
12670
		struct drm_encoder *encoder = connector->encoder;
Line 10499... Line -...
10499
	struct intel_connector *connector;
-
 
10500
 
-
 
10501
	list_for_each_entry(connector, &dev->mode_config.connector_list,
12671
		struct drm_connector_state *state = connector->state;
10502
			    base.head) {
12672
 
10503
		/* This also checks the encoder/connector hw state with the
12673
		/* This also checks the encoder/connector hw state with the
Line 10504... Line 12674...
10504
		 * ->get_hw_state callbacks. */
12674
		 * ->get_hw_state callbacks. */
10505
		intel_connector_check_state(connector);
12675
		intel_connector_check_state(to_intel_connector(connector));
10506
 
12676
 
10507
		WARN(&connector->new_encoder->base != connector->base.encoder,
12677
		I915_STATE_WARN(state->best_encoder != encoder,
Line 10508... Line 12678...
10508
		     "connector's staged encoder doesn't match current encoder\n");
12678
		     "connector's atomic encoder doesn't match legacy encoder\n");
10509
	}
12679
	}
Line 10515... Line 12685...
10515
	struct intel_encoder *encoder;
12685
	struct intel_encoder *encoder;
10516
	struct intel_connector *connector;
12686
	struct intel_connector *connector;
Line 10517... Line 12687...
10517
 
12687
 
10518
	for_each_intel_encoder(dev, encoder) {
12688
	for_each_intel_encoder(dev, encoder) {
10519
		bool enabled = false;
-
 
10520
		bool active = false;
12689
		bool enabled = false;
Line 10521... Line 12690...
10521
		enum pipe pipe, tracked_pipe;
12690
		enum pipe pipe;
10522
 
12691
 
10523
		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12692
		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
Line 10524... Line -...
10524
			      encoder->base.base.id,
-
 
10525
			      encoder->base.name);
-
 
10526
 
-
 
10527
		WARN(&encoder->new_crtc->base != encoder->base.crtc,
-
 
10528
		     "encoder's stage crtc doesn't match current crtc\n");
-
 
10529
		WARN(encoder->connectors_active && !encoder->base.crtc,
12693
			      encoder->base.base.id,
10530
		     "encoder's active_connectors set, but no crtc\n");
-
 
10531
 
12694
			      encoder->base.name);
10532
		list_for_each_entry(connector, &dev->mode_config.connector_list,
12695
 
10533
				    base.head) {
12696
		for_each_intel_connector(dev, connector) {
-
 
12697
			if (connector->base.state->best_encoder != &encoder->base)
10534
			if (connector->base.encoder != &encoder->base)
12698
				continue;
10535
				continue;
12699
			enabled = true;
-
 
12700
 
10536
			enabled = true;
12701
			I915_STATE_WARN(connector->base.state->crtc !=
10537
			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
-
 
10538
				active = true;
-
 
10539
		}
-
 
10540
		/*
-
 
10541
		 * for MST connectors if we unplug the connector is gone
-
 
10542
		 * away but the encoder is still connected to a crtc
-
 
10543
		 * until a modeset happens in response to the hotplug.
-
 
Line 10544... Line 12702...
10544
		 */
12702
					encoder->base.crtc,
10545
		if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12703
			     "connector's crtc doesn't match encoder crtc\n");
10546
			continue;
12704
		}
10547
 
12705
 
10548
		WARN(!!encoder->base.crtc != enabled,
-
 
10549
		     "encoder's enabled state mismatch "
-
 
Line 10550... Line 12706...
10550
		     "(expected %i, found %i)\n",
12706
		I915_STATE_WARN(!!encoder->base.crtc != enabled,
10551
		     !!encoder->base.crtc, enabled);
-
 
10552
		WARN(active && !encoder->base.crtc,
12707
		     "encoder's enabled state mismatch "
Line 10553... Line 12708...
10553
		     "active encoder with no crtc\n");
12708
		     "(expected %i, found %i)\n",
10554
 
12709
		     !!encoder->base.crtc, enabled);
10555
		WARN(encoder->connectors_active != active,
12710
 
10556
		     "encoder's computed active state doesn't match tracked active state "
-
 
10557
		     "(expected %i, found %i)\n", active, encoder->connectors_active);
-
 
10558
 
-
 
10559
		active = encoder->get_hw_state(encoder, &pipe);
-
 
10560
		WARN(active != encoder->connectors_active,
-
 
10561
		     "encoder's hw state doesn't match sw tracking "
-
 
10562
		     "(expected %i, found %i)\n",
-
 
10563
		     encoder->connectors_active, active);
-
 
10564
 
-
 
10565
		if (!encoder->base.crtc)
-
 
10566
			continue;
12711
		if (!encoder->base.crtc) {
10567
 
12712
			bool active;
10568
		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12713
 
10569
		WARN(active && pipe != tracked_pipe,
12714
			active = encoder->get_hw_state(encoder, &pipe);
Line 10570... Line 12715...
10570
		     "active encoder's pipe doesn't match"
12715
			I915_STATE_WARN(active,
10571
		     "(expected %i, found %i)\n",
12716
			     "encoder detached but still enabled on pipe %c.\n",
10572
		     tracked_pipe, pipe);
12717
			     pipe_name(pipe));
10573
 
12718
		}
10574
	}
-
 
10575
}
12719
	}
10576
 
12720
}
-
 
12721
 
-
 
12722
static void
Line 10577... Line 12723...
10577
static void
12723
check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
10578
check_crtc_state(struct drm_device *dev)
12724
{
-
 
12725
	struct drm_i915_private *dev_priv = dev->dev_private;
10579
{
12726
	struct intel_encoder *encoder;
Line -... Line 12727...
-
 
12727
	struct drm_crtc_state *old_crtc_state;
10580
	struct drm_i915_private *dev_priv = dev->dev_private;
12728
	struct drm_crtc *crtc;
-
 
12729
	int i;
Line -... Line 12730...
-
 
12730
 
-
 
12731
	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
-
 
12732
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10581
	struct intel_crtc *crtc;
12733
		struct intel_crtc_state *pipe_config, *sw_config;
10582
	struct intel_encoder *encoder;
12734
		bool active;
Line 10583... Line 12735...
10583
	struct intel_crtc_config pipe_config;
12735
 
10584
 
12736
		if (!needs_modeset(crtc->state) &&
Line 10585... Line -...
10585
	for_each_intel_crtc(dev, crtc) {
-
 
10586
		bool enabled = false;
12737
		    !to_intel_crtc_state(crtc->state)->update_pipe)
10587
		bool active = false;
-
 
10588
 
-
 
10589
		memset(&pipe_config, 0, sizeof(pipe_config));
-
 
10590
 
12738
			continue;
10591
		DRM_DEBUG_KMS("[CRTC:%d]\n",
-
 
Line 10592... Line 12739...
10592
			      crtc->base.base.id);
12739
 
10593
 
12740
		__drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
10594
		WARN(crtc->active && !crtc->base.enabled,
12741
		pipe_config = to_intel_crtc_state(old_crtc_state);
10595
		     "active crtc, but not enabled in sw tracking\n");
12742
		memset(pipe_config, 0, sizeof(*pipe_config));
10596
 
-
 
10597
		for_each_intel_encoder(dev, encoder) {
-
 
Line 10598... Line 12743...
10598
			if (encoder->base.crtc != &crtc->base)
12743
		pipe_config->base.crtc = crtc;
10599
				continue;
12744
		pipe_config->base.state = old_state;
-
 
12745
 
Line 10600... Line 12746...
10600
			enabled = true;
12746
		DRM_DEBUG_KMS("[CRTC:%d]\n",
10601
			if (encoder->connectors_active)
12747
			      crtc->base.id);
10602
				active = true;
12748
 
10603
		}
-
 
Line 10604... Line 12749...
10604
 
12749
		active = dev_priv->display.get_pipe_config(intel_crtc,
10605
		WARN(active != crtc->active,
12750
							   pipe_config);
-
 
12751
 
-
 
12752
		/* hw state is inconsistent with the pipe quirk */
-
 
12753
		if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
-
 
12754
		    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10606
		     "crtc's computed active state doesn't match tracked active state "
12755
			active = crtc->state->active;
-
 
12756
 
-
 
12757
		I915_STATE_WARN(crtc->state->active != active,
-
 
12758
		     "crtc active state doesn't match with hw state "
10607
		     "(expected %i, found %i)\n", active, crtc->active);
12759
		     "(expected %i, found %i)\n", crtc->state->active, active);
-
 
12760
 
10608
		WARN(enabled != crtc->base.enabled,
12761
		I915_STATE_WARN(intel_crtc->active != crtc->state->active,
10609
		     "crtc's computed enabled state doesn't match tracked enabled state "
12762
		     "transitional active state does not match atomic hw state "
10610
		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);
12763
		     "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
Line 10611... Line 12764...
10611
 
12764
 
10612
		active = dev_priv->display.get_pipe_config(crtc,
12765
		for_each_encoder_on_crtc(dev, crtc, encoder) {
10613
							   &pipe_config);
-
 
Line 10614... Line 12766...
10614
 
12766
			enum pipe pipe;
10615
		/* hw state is inconsistent with the pipe quirk */
12767
 
-
 
12768
			active = encoder->get_hw_state(encoder, &pipe);
10616
		if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12769
			I915_STATE_WARN(active != crtc->state->active,
10617
		    (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12770
				"[ENCODER:%i] active %i with crtc active %i\n",
10618
			active = crtc->active;
12771
				encoder->base.base.id, active, crtc->state->active);
10619
 
12772
 
10620
		for_each_intel_encoder(dev, encoder) {
12773
			I915_STATE_WARN(active && intel_crtc->pipe != pipe,
10621
			enum pipe pipe;
12774
					"Encoder connected to wrong pipe %c\n",
10622
			if (encoder->base.crtc != &crtc->base)
12775
					pipe_name(pipe));
10623
				continue;
12776
 
Line 10657... Line 12810...
10657
 
12810
 
Line 10658... Line 12811...
10658
		DRM_DEBUG_KMS("%s\n", pll->name);
12811
		DRM_DEBUG_KMS("%s\n", pll->name);
Line 10659... Line 12812...
10659
 
12812
 
10660
		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12813
		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10661
 
12814
 
10662
		WARN(pll->active > hweight32(pll->config.crtc_mask),
12815
		I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10663
		     "more active pll users than references: %i vs %i\n",
12816
		     "more active pll users than references: %i vs %i\n",
10664
		     pll->active, hweight32(pll->config.crtc_mask));
12817
		     pll->active, hweight32(pll->config.crtc_mask));
10665
		WARN(pll->active && !pll->on,
12818
		I915_STATE_WARN(pll->active && !pll->on,
10666
		     "pll in active use but not on in sw tracking\n");
12819
		     "pll in active use but not on in sw tracking\n");
10667
		WARN(pll->on && !pll->active,
12820
		I915_STATE_WARN(pll->on && !pll->active,
10668
		     "pll in on but not on in use in sw tracking\n");
12821
		     "pll in on but not on in use in sw tracking\n");
Line 10669... Line 12822...
10669
		WARN(pll->on != active,
12822
		I915_STATE_WARN(pll->on != active,
10670
		     "pll on state mismatch (expected %i, found %i)\n",
12823
		     "pll on state mismatch (expected %i, found %i)\n",
10671
		     pll->on, active);
12824
		     pll->on, active);
10672
 
12825
 
10673
		for_each_intel_crtc(dev, crtc) {
12826
		for_each_intel_crtc(dev, crtc) {
10674
			if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
12827
			if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
10675
				enabled_crtcs++;
12828
				enabled_crtcs++;
10676
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12829
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10677
				active_crtcs++;
12830
				active_crtcs++;
10678
		}
12831
		}
10679
		WARN(pll->active != active_crtcs,
12832
		I915_STATE_WARN(pll->active != active_crtcs,
10680
		     "pll active crtcs mismatch (expected %i, found %i)\n",
12833
		     "pll active crtcs mismatch (expected %i, found %i)\n",
Line 10681... Line 12834...
10681
		     pll->active, active_crtcs);
12834
		     pll->active, active_crtcs);
10682
		WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12835
		I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10683
		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
12836
		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
10684
		     hweight32(pll->config.crtc_mask), enabled_crtcs);
12837
		     hweight32(pll->config.crtc_mask), enabled_crtcs);
10685
 
12838
 
Line 10686... Line 12839...
10686
		WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12839
		I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10687
				       sizeof(dpll_hw_state)),
12840
				       sizeof(dpll_hw_state)),
-
 
12841
		     "pll hw state mismatch\n");
10688
		     "pll hw state mismatch\n");
12842
	}
10689
	}
12843
}
10690
}
12844
 
10691
 
12845
static void
10692
void
12846
intel_modeset_check_state(struct drm_device *dev,
10693
intel_modeset_check_state(struct drm_device *dev)
12847
			  struct drm_atomic_state *old_state)
10694
{
12848
{
Line 10695... Line 12849...
10695
	check_wm_state(dev);
12849
	check_wm_state(dev);
10696
	check_connector_state(dev);
12850
	check_connector_state(dev, old_state);
10697
	check_encoder_state(dev);
12851
	check_encoder_state(dev);
10698
	check_crtc_state(dev);
12852
	check_crtc_state(dev, old_state);
10699
	check_shared_dpll_state(dev);
12853
	check_shared_dpll_state(dev);
10700
}
12854
}
10701
 
12855
 
10702
void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
12856
void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10703
				     int dotclock)
12857
				     int dotclock)
10704
{
12858
{
10705
	/*
12859
	/*
Line 10706... Line 12860...
10706
	 * FDI already provided one idea for the dotclock.
12860
	 * FDI already provided one idea for the dotclock.
10707
	 * Yell if the encoder disagrees.
12861
	 * Yell if the encoder disagrees.
10708
	 */
12862
	 */
Line 10732... Line 12886...
10732
	 * type. For DP ports it behaves like most other platforms, but on HDMI
12886
	 * type. For DP ports it behaves like most other platforms, but on HDMI
10733
	 * there's an extra 1 line difference. So we need to add two instead of
12887
	 * there's an extra 1 line difference. So we need to add two instead of
10734
	 * one to the value.
12888
	 * one to the value.
10735
	 */
12889
	 */
10736
	if (IS_GEN2(dev)) {
12890
	if (IS_GEN2(dev)) {
10737
		const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
12891
		const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
10738
		int vtotal;
12892
		int vtotal;
Line 10739... Line 12893...
10739
 
12893
 
10740
		vtotal = mode->crtc_vtotal;
12894
		vtotal = adjusted_mode->crtc_vtotal;
10741
		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12895
		if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Line 10742... Line 12896...
10742
			vtotal /= 2;
12896
			vtotal /= 2;
10743
 
12897
 
10744
		crtc->scanline_offset = vtotal - 1;
12898
		crtc->scanline_offset = vtotal - 1;
10745
	} else if (HAS_DDI(dev) &&
12899
	} else if (HAS_DDI(dev) &&
10746
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12900
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10747
		crtc->scanline_offset = 2;
12901
		crtc->scanline_offset = 2;
10748
	} else
12902
	} else
Line 10749... Line -...
10749
		crtc->scanline_offset = 1;
-
 
10750
}
-
 
10751
 
-
 
10752
static struct intel_crtc_config *
-
 
10753
intel_modeset_compute_config(struct drm_crtc *crtc,
-
 
10754
			     struct drm_display_mode *mode,
-
 
10755
			     struct drm_framebuffer *fb,
-
 
10756
			     unsigned *modeset_pipes,
-
 
10757
			     unsigned *prepare_pipes,
-
 
10758
			     unsigned *disable_pipes)
-
 
10759
{
-
 
10760
	struct intel_crtc_config *pipe_config = NULL;
-
 
10761
 
-
 
10762
	intel_modeset_affected_pipes(crtc, modeset_pipes,
-
 
10763
				     prepare_pipes, disable_pipes);
-
 
10764
 
-
 
10765
	if ((*modeset_pipes) == 0)
-
 
10766
		goto out;
-
 
10767
 
-
 
10768
	/*
-
 
10769
	 * Note this needs changes when we start tracking multiple modes
-
 
10770
	 * and crtcs.  At that point we'll need to compute the whole config
-
 
10771
	 * (i.e. one pipe_config for each crtc) rather than just the one
-
 
10772
	 * for this crtc.
-
 
10773
	 */
-
 
10774
	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
-
 
10775
	if (IS_ERR(pipe_config)) {
-
 
10776
		goto out;
-
 
10777
	}
-
 
10778
	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
-
 
10779
			       "[modeset]");
-
 
10780
 
-
 
10781
out:
-
 
10782
	return pipe_config;
12903
		crtc->scanline_offset = 1;
10783
}
-
 
10784
 
-
 
10785
static int __intel_set_mode(struct drm_crtc *crtc,
-
 
10786
		    struct drm_display_mode *mode,
-
 
10787
			    int x, int y, struct drm_framebuffer *fb,
-
 
10788
			    struct intel_crtc_config *pipe_config,
-
 
10789
			    unsigned modeset_pipes,
12904
}
10790
			    unsigned prepare_pipes,
12905
 
10791
			    unsigned disable_pipes)
12906
static void intel_modeset_clear_plls(struct drm_atomic_state *state)
10792
{
12907
{
10793
	struct drm_device *dev = crtc->dev;
12908
	struct drm_device *dev = state->dev;
10794
	struct drm_i915_private *dev_priv = dev->dev_private;
12909
	struct drm_i915_private *dev_priv = to_i915(dev);
10795
	struct drm_display_mode *saved_mode;
-
 
10796
	struct intel_crtc *intel_crtc;
12910
	struct intel_shared_dpll_config *shared_dpll = NULL;
10797
	int ret = 0;
12911
	struct intel_crtc *intel_crtc;
10798
 
12912
	struct intel_crtc_state *intel_crtc_state;
Line 10799... Line 12913...
10799
	saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
12913
	struct drm_crtc *crtc;
-
 
12914
	struct drm_crtc_state *crtc_state;
Line 10800... Line -...
10800
	if (!saved_mode)
-
 
10801
		return -ENOMEM;
12915
	int i;
-
 
12916
 
Line 10802... Line -...
10802
 
-
 
10803
	*saved_mode = crtc->mode;
-
 
10804
 
-
 
10805
	if (modeset_pipes)
-
 
10806
		to_intel_crtc(crtc)->new_config = pipe_config;
12917
	if (!dev_priv->display.crtc_compute_clock)
10807
 
12918
		return;
10808
	/*
-
 
10809
	 * See if the config requires any additional preparation, e.g.
-
 
10810
	 * to adjust global state with pipes off.  We need to do this
12919
 
Line 10811... Line 12920...
10811
	 * here so we can get the modeset_pipe updated config for the new
12920
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
10812
	 * mode set on this crtc.  For other crtcs we need to use the
12921
		int dpll;
10813
	 * adjusted_mode bits in the crtc directly.
-
 
Line 10814... Line -...
10814
	 */
-
 
10815
	if (IS_VALLEYVIEW(dev)) {
12922
 
Line 10816... Line -...
10816
		valleyview_modeset_global_pipes(dev, &prepare_pipes);
-
 
10817
 
12923
		intel_crtc = to_intel_crtc(crtc);
10818
		/* may have added more to prepare_pipes than we should */
12924
		intel_crtc_state = to_intel_crtc_state(crtc_state);
Line 10819... Line -...
10819
		prepare_pipes &= ~disable_pipes;
-
 
10820
	}
12925
		dpll = intel_crtc_state->shared_dpll;
10821
 
-
 
10822
	if (dev_priv->display.crtc_compute_clock) {
-
 
10823
		unsigned clear_pipes = modeset_pipes | disable_pipes;
-
 
10824
 
-
 
10825
		ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12926
 
10826
		if (ret)
12927
		if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
Line 10827... Line -...
10827
			goto done;
-
 
10828
 
-
 
10829
		for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
-
 
10830
			ret = dev_priv->display.crtc_compute_clock(intel_crtc);
-
 
10831
			if (ret) {
-
 
10832
				intel_shared_dpll_abort_config(dev_priv);
-
 
10833
				goto done;
-
 
10834
			}
-
 
10835
		}
-
 
10836
	}
-
 
10837
 
-
 
10838
	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
-
 
10839
		intel_crtc_disable(&intel_crtc->base);
-
 
10840
 
-
 
10841
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
-
 
10842
		if (intel_crtc->base.enabled)
-
 
10843
			dev_priv->display.crtc_disable(&intel_crtc->base);
-
 
10844
	}
-
 
10845
 
-
 
10846
	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
-
 
10847
	 * to set it here already despite that we pass it down the callchain.
-
 
10848
	 *
-
 
10849
	 * Note we'll need to fix this up when we start tracking multiple
12928
			continue;
10850
	 * pipes; here we assume a single modeset_pipe and only track the
12929
 
10851
	 * single crtc and mode.
-
 
10852
	 */
12930
		intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
10853
	if (modeset_pipes) {
-
 
10854
		crtc->mode = *mode;
-
 
10855
		/* mode_set/enable/disable functions rely on a correct pipe
-
 
10856
		 * config. */
-
 
10857
		to_intel_crtc(crtc)->config = *pipe_config;
-
 
10858
		to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
12931
 
10859
 
-
 
10860
		/*
-
 
10861
		 * Calculate and store various constants which
-
 
10862
		 * are later needed by vblank and swap-completion
-
 
10863
		 * timestamping. They are derived from true hwmode.
-
 
10864
		 */
12932
		if (!shared_dpll)
10865
		drm_calc_timestamping_constants(crtc,
-
 
10866
						&pipe_config->adjusted_mode);
12933
			shared_dpll = intel_atomic_get_shared_dpll_state(state);
10867
	}
-
 
10868
 
-
 
10869
	/* Only after disabling all output pipelines that will be changed can we
-
 
10870
	 * update the the output configuration. */
-
 
10871
	intel_modeset_update_state(dev, prepare_pipes);
-
 
10872
 
-
 
10873
	modeset_update_crtc_power_domains(dev);
-
 
10874
 
-
 
10875
	/* Set up the DPLL and any encoders state that needs to adjust or depend
-
 
10876
	 * on the DPLL.
-
 
10877
	 */
-
 
10878
	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
-
 
10879
		struct drm_framebuffer *old_fb = crtc->primary->fb;
-
 
10880
		struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
-
 
10881
		struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-
 
10882
 
-
 
10883
		mutex_lock(&dev->struct_mutex);
-
 
10884
		ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
-
 
10885
		if (ret != 0) {
-
 
10886
			DRM_ERROR("pin & fence failed\n");
-
 
10887
			mutex_unlock(&dev->struct_mutex);
-
 
10888
			goto done;
-
 
10889
		}
-
 
10890
		if (old_fb)
-
 
10891
			intel_unpin_fb_obj(old_obj);
-
 
10892
		i915_gem_track_fb(old_obj, obj,
-
 
10893
				  INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
-
 
10894
		mutex_unlock(&dev->struct_mutex);
-
 
10895
 
-
 
10896
		crtc->primary->fb = fb;
-
 
10897
		crtc->x = x;
-
 
10898
		crtc->y = y;
-
 
10899
	}
-
 
10900
 
-
 
10901
	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
-
 
10902
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
-
 
10903
		update_scanline_offset(intel_crtc);
-
 
10904
 
-
 
10905
		dev_priv->display.crtc_enable(&intel_crtc->base);
-
 
10906
	}
-
 
10907
 
12934
 
10908
	/* FIXME: add subpixel order */
-
 
10909
done:
-
 
10910
	if (ret && crtc->enabled)
-
 
10911
		crtc->mode = *saved_mode;
-
 
10912
 
-
 
10913
	kfree(pipe_config);
-
 
10914
	kfree(saved_mode);
12935
		shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
-
 
12936
	}
-
 
12937
}
-
 
12938
 
-
 
12939
/*
-
 
12940
 * This implements the workaround described in the "notes" section of the mode
-
 
12941
 * set sequence documentation. When going from no pipes or single pipe to
10915
	return ret;
12942
 * multiple pipes, and planes are enabled after the pipe, we need to wait at
Line 10916... Line 12943...
10916
}
12943
 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
-
 
12944
 */
10917
 
12945
static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
Line -... Line 12946...
-
 
12946
{
10918
static int intel_set_mode_pipes(struct drm_crtc *crtc,
12947
	struct drm_crtc_state *crtc_state;
10919
		     struct drm_display_mode *mode,
-
 
Line -... Line 12948...
-
 
12948
	struct intel_crtc *intel_crtc;
-
 
12949
	struct drm_crtc *crtc;
10920
				int x, int y, struct drm_framebuffer *fb,
12950
	struct intel_crtc_state *first_crtc_state = NULL;
-
 
12951
	struct intel_crtc_state *other_crtc_state = NULL;
-
 
12952
	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
-
 
12953
	int i;
-
 
12954
 
10921
				struct intel_crtc_config *pipe_config,
12955
	/* look at all crtc's that are going to be enabled in during modeset */
Line 10922... Line -...
10922
				unsigned modeset_pipes,
-
 
10923
				unsigned prepare_pipes,
12956
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
10924
				unsigned disable_pipes)
12957
		intel_crtc = to_intel_crtc(crtc);
10925
{
-
 
10926
	int ret;
12958
 
10927
 
-
 
Line 10928... Line 12959...
10928
	ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12959
		if (!crtc_state->active || !needs_modeset(crtc_state))
10929
			       prepare_pipes, disable_pipes);
12960
			continue;
10930
 
-
 
10931
	if (ret == 0)
12961
 
Line -... Line 12962...
-
 
12962
		if (first_crtc_state) {
10932
		intel_modeset_check_state(crtc->dev);
12963
			other_crtc_state = to_intel_crtc_state(crtc_state);
10933
 
12964
			break;
Line 10934... Line -...
10934
	return ret;
-
 
10935
}
12965
		} else {
10936
 
-
 
10937
static int intel_set_mode(struct drm_crtc *crtc,
-
 
Line 10938... Line 12966...
10938
			  struct drm_display_mode *mode,
12966
			first_crtc_state = to_intel_crtc_state(crtc_state);
10939
			  int x, int y, struct drm_framebuffer *fb)
-
 
10940
{
12967
			first_pipe = intel_crtc->pipe;
10941
	struct intel_crtc_config *pipe_config;
12968
		}
Line 10942... Line 12969...
10942
	unsigned modeset_pipes, prepare_pipes, disable_pipes;
12969
	}
-
 
12970
 
-
 
12971
	/* No workaround needed? */
Line 10943... Line 12972...
10943
 
12972
	if (!first_crtc_state)
-
 
12973
		return 0;
10944
	pipe_config = intel_modeset_compute_config(crtc, mode, fb,
12974
 
10945
						   &modeset_pipes,
12975
	/* w/a possibly needed, check how many crtc's are already enabled. */
-
 
12976
	for_each_intel_crtc(state->dev, intel_crtc) {
10946
						   &prepare_pipes,
12977
		struct intel_crtc_state *pipe_config;
-
 
12978
 
Line 10947... Line -...
10947
						   &disable_pipes);
-
 
10948
 
-
 
10949
	if (IS_ERR(pipe_config))
-
 
10950
		return PTR_ERR(pipe_config);
12979
		pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
10951
 
12980
		if (IS_ERR(pipe_config))
Line 10952... Line 12981...
10952
	return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12981
			return PTR_ERR(pipe_config);
10953
				    modeset_pipes, prepare_pipes,
-
 
10954
				    disable_pipes);
12982
 
10955
}
12983
		pipe_config->hsw_workaround_pipe = INVALID_PIPE;
10956
 
-
 
10957
void intel_crtc_restore_mode(struct drm_crtc *crtc)
12984
 
10958
{
12985
		if (!pipe_config->base.active ||
10959
	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
-
 
10960
}
-
 
10961
 
-
 
10962
#undef for_each_intel_crtc_masked
-
 
10963
 
-
 
10964
static void intel_set_config_free(struct intel_set_config *config)
-
 
Line 10965... Line 12986...
10965
{
12986
		    needs_modeset(&pipe_config->base))
10966
	if (!config)
12987
			continue;
10967
		return;
12988
 
10968
 
12989
		/* 2 or more enabled crtcs means no need for w/a */
10969
	kfree(config->save_connector_encoders);
12990
		if (enabled_pipe != INVALID_PIPE)
Line 10970... Line -...
10970
	kfree(config->save_encoder_crtcs);
-
 
10971
	kfree(config->save_crtc_enabled);
-
 
10972
	kfree(config);
-
 
10973
}
12991
			return 0;
10974
 
12992
 
Line 10975... Line -...
10975
static int intel_set_config_save_state(struct drm_device *dev,
-
 
10976
				       struct intel_set_config *config)
-
 
10977
{
-
 
10978
	struct drm_crtc *crtc;
-
 
10979
	struct drm_encoder *encoder;
-
 
10980
	struct drm_connector *connector;
12993
		enabled_pipe = intel_crtc->pipe;
10981
	int count;
-
 
10982
 
-
 
Line 10983... Line -...
10983
	config->save_crtc_enabled =
-
 
10984
		kcalloc(dev->mode_config.num_crtc,
12994
	}
10985
			sizeof(bool), GFP_KERNEL);
12995
 
10986
	if (!config->save_crtc_enabled)
12996
	if (enabled_pipe != INVALID_PIPE)
Line -... Line 12997...
-
 
12997
		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
10987
		return -ENOMEM;
12998
	else if (other_crtc_state)
10988
 
-
 
10989
	config->save_encoder_crtcs =
12999
		other_crtc_state->hsw_workaround_pipe = first_pipe;
10990
		kcalloc(dev->mode_config.num_encoder,
13000
 
Line 10991... Line 13001...
10991
			sizeof(struct drm_crtc *), GFP_KERNEL);
13001
	return 0;
10992
	if (!config->save_encoder_crtcs)
13002
}
Line 10993... Line 13003...
10993
		return -ENOMEM;
13003
 
10994
 
-
 
10995
	config->save_connector_encoders =
13004
static int intel_modeset_all_pipes(struct drm_atomic_state *state)
10996
		kcalloc(dev->mode_config.num_connector,
-
 
10997
			sizeof(struct drm_encoder *), GFP_KERNEL);
13005
{
10998
	if (!config->save_connector_encoders)
13006
	struct drm_crtc *crtc;
10999
		return -ENOMEM;
13007
	struct drm_crtc_state *crtc_state;
11000
 
-
 
11001
	/* Copy data. Note that driver private data is not affected.
-
 
11002
	 * Should anything bad happen only the expected state is
-
 
11003
	 * restored, not the drivers personal bookkeeping.
-
 
Line 11004... Line 13008...
11004
	 */
13008
	int ret = 0;
11005
	count = 0;
13009
 
11006
	for_each_crtc(dev, crtc) {
-
 
11007
		config->save_crtc_enabled[count++] = crtc->enabled;
13010
	/* add all active pipes to the state */
11008
	}
13011
	for_each_crtc(state->dev, crtc) {
Line 11009... Line 13012...
11009
 
13012
		crtc_state = drm_atomic_get_crtc_state(state, crtc);
-
 
13013
		if (IS_ERR(crtc_state))
-
 
13014
			return PTR_ERR(crtc_state);
11010
	count = 0;
13015
 
11011
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
13016
		if (!crtc_state->active || needs_modeset(crtc_state))
11012
		config->save_encoder_crtcs[count++] = encoder->crtc;
13017
			continue;
11013
	}
13018
 
-
 
13019
		crtc_state->mode_changed = true;
-
 
13020
 
Line 11014... Line -...
11014
 
-
 
11015
	count = 0;
-
 
11016
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-
 
11017
		config->save_connector_encoders[count++] = connector->encoder;
13021
		ret = drm_atomic_add_affected_connectors(state, crtc);
11018
	}
-
 
11019
 
-
 
Line 11020... Line 13022...
11020
	return 0;
13022
		if (ret)
11021
}
13023
			break;
11022
 
-
 
11023
static void intel_set_config_restore_state(struct drm_device *dev,
13024
 
Line 11024... Line 13025...
11024
					   struct intel_set_config *config)
13025
		ret = drm_atomic_add_affected_planes(state, crtc);
11025
{
13026
		if (ret)
-
 
13027
			break;
-
 
13028
	}
Line 11026... Line 13029...
11026
	struct intel_crtc *crtc;
13029
 
11027
	struct intel_encoder *encoder;
-
 
Line 11028... Line -...
11028
	struct intel_connector *connector;
-
 
11029
	int count;
13030
	return ret;
11030
 
13031
}
11031
	count = 0;
-
 
11032
	for_each_intel_crtc(dev, crtc) {
-
 
Line 11033... Line 13032...
11033
		crtc->new_enabled = config->save_crtc_enabled[count++];
13032
 
11034
 
13033
static int intel_modeset_checks(struct drm_atomic_state *state)
Line -... Line 13034...
-
 
13034
{
-
 
13035
	struct drm_device *dev = state->dev;
-
 
13036
	struct drm_i915_private *dev_priv = dev->dev_private;
11035
		if (crtc->new_enabled)
13037
	int ret;
-
 
13038
 
11036
			crtc->new_config = &crtc->config;
13039
	if (!check_digital_port_conflicts(state)) {
11037
		else
13040
		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11038
			crtc->new_config = NULL;
13041
		return -EINVAL;
-
 
13042
	}
-
 
13043
 
-
 
13044
	/*
-
 
13045
	 * See if the config requires any additional preparation, e.g.
Line 11039... Line -...
11039
	}
-
 
11040
 
-
 
11041
	count = 0;
-
 
11042
	for_each_intel_encoder(dev, encoder) {
-
 
11043
		encoder->new_crtc =
-
 
11044
			to_intel_crtc(config->save_encoder_crtcs[count++]);
-
 
11045
	}
-
 
11046
 
13046
	 * to adjust global state with pipes off.  We need to do this
11047
	count = 0;
-
 
11048
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
-
 
11049
		connector->new_encoder =
13047
	 * here so we can get the modeset_pipe updated config for the new
11050
			to_intel_encoder(config->save_connector_encoders[count++]);
-
 
11051
	}
-
 
11052
}
13048
	 * mode set on this crtc.  For other crtcs we need to use the
Line 11053... Line -...
11053
 
-
 
11054
static bool
-
 
11055
is_crtc_connector_off(struct drm_mode_set *set)
-
 
11056
{
-
 
11057
	int i;
13049
	 * adjusted_mode bits in the crtc directly.
11058
 
-
 
11059
	if (set->num_connectors == 0)
-
 
11060
		return false;
-
 
11061
 
-
 
11062
	if (WARN_ON(set->connectors == NULL))
13050
	 */
11063
		return false;
-
 
11064
 
-
 
11065
	for (i = 0; i < set->num_connectors; i++)
-
 
11066
		if (set->connectors[i]->encoder &&
13051
	if (dev_priv->display.modeset_calc_cdclk) {
11067
		    set->connectors[i]->encoder->crtc == set->crtc &&
-
 
11068
		    set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
-
 
Line 11069... Line 13052...
11069
			return true;
13052
		unsigned int cdclk;
11070
 
13053
 
Line 11071... Line -...
11071
	return false;
-
 
11072
}
13054
		ret = dev_priv->display.modeset_calc_cdclk(state);
11073
 
13055
 
11074
static void
-
 
11075
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
13056
		cdclk = to_intel_atomic_state(state)->cdclk;
11076
				      struct intel_set_config *config)
-
 
Line 11077... Line 13057...
11077
{
13057
		if (!ret && cdclk != dev_priv->cdclk_freq)
11078
 
13058
			ret = intel_modeset_all_pipes(state);
-
 
13059
 
-
 
13060
		if (ret < 0)
11079
	/* We should be able to check here if the fb has the same properties
13061
			return ret;
Line 11080... Line -...
11080
	 * and then just flip_or_move it */
-
 
11081
	if (is_crtc_connector_off(set)) {
-
 
11082
			config->mode_changed = true;
13062
	} else
11083
	} else if (set->crtc->primary->fb != set->fb) {
-
 
11084
		/*
-
 
11085
		 * If we have no fb, we can only flip as long as the crtc is
-
 
11086
		 * active, otherwise we need a full mode set.  The crtc may
-
 
11087
		 * be active if we've only disabled the primary plane, or
-
 
11088
		 * in fastboot situations.
13063
		to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
Line 11089... Line 13064...
11089
		 */
13064
 
11090
		if (set->crtc->primary->fb == NULL) {
13065
	intel_modeset_clear_plls(state);
11091
			struct intel_crtc *intel_crtc =
-
 
11092
				to_intel_crtc(set->crtc);
-
 
Line 11093... Line -...
11093
 
-
 
11094
			if (intel_crtc->active) {
-
 
11095
				DRM_DEBUG_KMS("crtc has no fb, will flip\n");
13066
 
11096
				config->fb_changed = true;
13067
	if (IS_HASWELL(dev))
11097
			} else {
-
 
11098
				DRM_DEBUG_KMS("inactive crtc, full mode set\n");
-
 
11099
			config->mode_changed = true;
-
 
11100
			}
13068
		return haswell_mode_set_planes_workaround(state);
11101
		} else if (set->fb == NULL) {
-
 
11102
			config->mode_changed = true;
-
 
Line 11103... Line -...
11103
		} else if (set->fb->pixel_format !=
-
 
11104
			   set->crtc->primary->fb->pixel_format) {
13069
 
11105
			config->mode_changed = true;
-
 
11106
		} else {
-
 
11107
			config->fb_changed = true;
13070
	return 0;
11108
	}
-
 
11109
	}
13071
}
Line -... Line 13072...
-
 
13072
 
11110
 
13073
/**
11111
	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
13074
 * intel_atomic_check - validate state object
11112
		config->fb_changed = true;
13075
 * @dev: drm device
-
 
13076
 * @state: state to validate
-
 
13077
 */
11113
 
13078
static int intel_atomic_check(struct drm_device *dev,
Line -... Line 13079...
-
 
13079
			      struct drm_atomic_state *state)
-
 
13080
{
Line 11114... Line -...
11114
	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
-
 
11115
		DRM_DEBUG_KMS("modes are different, full mode set\n");
13081
	struct drm_crtc *crtc;
11116
		drm_mode_debug_printmodeline(&set->crtc->mode);
13082
	struct drm_crtc_state *crtc_state;
11117
		drm_mode_debug_printmodeline(set->mode);
13083
	int ret, i;
11118
		config->mode_changed = true;
13084
	bool any_ms = false;
11119
	}
-
 
Line 11120... Line -...
11120
 
-
 
11121
	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
13085
 
11122
			set->crtc->base.id, config->mode_changed, config->fb_changed);
13086
	ret = drm_atomic_helper_check_modeset(dev, state);
11123
}
13087
	if (ret)
-
 
13088
		return ret;
Line 11124... Line 13089...
11124
 
13089
 
11125
static int
13090
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
Line -... Line 13091...
-
 
13091
		struct intel_crtc_state *pipe_config =
-
 
13092
			to_intel_crtc_state(crtc_state);
-
 
13093
 
11126
intel_modeset_stage_output_state(struct drm_device *dev,
13094
		memset(&to_intel_crtc(crtc)->atomic, 0,
-
 
13095
		       sizeof(struct intel_crtc_atomic_commit));
Line 11127... Line -...
11127
				 struct drm_mode_set *set,
-
 
11128
				 struct intel_set_config *config)
13096
 
11129
{
-
 
11130
	struct intel_connector *connector;
13097
		/* Catch I915_MODE_FLAG_INHERITED */
Line -... Line 13098...
-
 
13098
		if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
-
 
13099
			crtc_state->mode_changed = true;
-
 
13100
 
11131
	struct intel_encoder *encoder;
13101
		if (!crtc_state->enable) {
-
 
13102
			if (needs_modeset(crtc_state))
-
 
13103
				any_ms = true;
-
 
13104
			continue;
-
 
13105
		}
-
 
13106
 
-
 
13107
		if (!needs_modeset(crtc_state))
-
 
13108
			continue;
-
 
13109
 
-
 
13110
		/* FIXME: For only active_changed we shouldn't need to do any
-
 
13111
		 * state recomputation at all. */
-
 
13112
 
-
 
13113
		ret = drm_atomic_add_affected_connectors(state, crtc);
-
 
13114
		if (ret)
-
 
13115
			return ret;
-
 
13116
 
-
 
13117
		ret = intel_modeset_pipe_config(crtc, pipe_config);
11132
	struct intel_crtc *crtc;
13118
		if (ret)
11133
	int ro;
13119
			return ret;
-
 
13120
 
-
 
13121
		if (i915.fastboot &&
-
 
13122
		    intel_pipe_config_compare(state->dev,
-
 
13123
					to_intel_crtc_state(crtc->state),
-
 
13124
					pipe_config, true)) {
-
 
13125
			crtc_state->mode_changed = false;
-
 
13126
			to_intel_crtc_state(crtc_state)->update_pipe = true;
11134
 
13127
		}
11135
	/* The upper layers ensure that we either disable a crtc or have a list
13128
 
11136
	 * of connectors. For paranoia, double-check this. */
-
 
Line 11137... Line 13129...
11137
	WARN_ON(!set->fb && (set->num_connectors != 0));
13129
		if (needs_modeset(crtc_state)) {
11138
	WARN_ON(set->fb && (set->num_connectors == 0));
-
 
11139
 
13130
			any_ms = true;
11140
	list_for_each_entry(connector, &dev->mode_config.connector_list,
13131
 
11141
			    base.head) {
-
 
Line 11142... Line -...
11142
		/* Otherwise traverse passed in connector list and get encoders
-
 
11143
		 * for them. */
13132
			ret = drm_atomic_add_affected_planes(state, crtc);
11144
		for (ro = 0; ro < set->num_connectors; ro++) {
-
 
11145
			if (set->connectors[ro] == &connector->base) {
-
 
11146
				connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
-
 
11147
				break;
-
 
11148
			}
-
 
11149
		}
-
 
11150
 
-
 
11151
		/* If we disable the crtc, disable all its connectors. Also, if
-
 
11152
		 * the connector is on the changing crtc but not on the new
-
 
Line 11153... Line 13133...
11153
		 * connector list, disable it. */
13133
			if (ret)
11154
		if ((!set->fb || ro == set->num_connectors) &&
13134
				return ret;
11155
		    connector->base.encoder &&
-
 
11156
		    connector->base.encoder->crtc == set->crtc) {
-
 
Line 11157... Line -...
11157
			connector->new_encoder = NULL;
-
 
11158
 
-
 
11159
			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
-
 
11160
				connector->base.base.id,
-
 
11161
				connector->base.name);
13135
		}
11162
		}
-
 
11163
 
-
 
11164
 
-
 
11165
		if (&connector->new_encoder->base != connector->base.encoder) {
-
 
11166
			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
13136
 
11167
			config->mode_changed = true;
-
 
11168
		}
-
 
11169
	}
-
 
11170
	/* connector->new_encoder is now updated for all connectors. */
-
 
11171
 
-
 
11172
	/* Update crtc of enabled connectors. */
-
 
Line -... Line 13137...
-
 
13137
		intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11173
	list_for_each_entry(connector, &dev->mode_config.connector_list,
13138
				       needs_modeset(crtc_state) ?
-
 
13139
				       "[modeset]" : "[fastset]");
11174
			    base.head) {
13140
	}
-
 
13141
 
11175
		struct drm_crtc *new_crtc;
13142
	if (any_ms) {
11176
 
13143
		ret = intel_modeset_checks(state);
-
 
13144
 
11177
		if (!connector->new_encoder)
13145
		if (ret)
11178
			continue;
13146
			return ret;
Line 11179... Line 13147...
11179
 
13147
	} else
11180
		new_crtc = connector->new_encoder->base.crtc;
-
 
11181
 
13148
		to_intel_atomic_state(state)->cdclk =
11182
		for (ro = 0; ro < set->num_connectors; ro++) {
13149
			to_i915(state->dev)->cdclk_freq;
11183
			if (set->connectors[ro] == &connector->base)
-
 
Line 11184... Line 13150...
11184
				new_crtc = set->crtc;
13150
 
11185
		}
-
 
11186
 
-
 
11187
		/* Make sure the new CRTC will work with the encoder */
13151
	return drm_atomic_helper_check_planes(state->dev, state);
11188
		if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
-
 
Line -... Line 13152...
-
 
13152
}
11189
					   new_crtc)) {
13153
 
11190
			return -EINVAL;
13154
/**
Line -... Line 13155...
-
 
13155
 * intel_atomic_commit - commit validated state object
11191
		}
13156
 * @dev: DRM device
11192
		connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
-
 
11193
 
13157
 * @state: the top-level driver state object
11194
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13158
 * @async: asynchronous commit
11195
			connector->base.base.id,
13159
 *
11196
			connector->base.name,
-
 
11197
			new_crtc->base.id);
13160
 * This function commits a top-level state object that has been validated
11198
	}
13161
 * with drm_atomic_helper_check().
Line 11199... Line -...
11199
 
-
 
11200
	/* Check for any encoders that needs to be disabled. */
13162
 *
11201
	for_each_intel_encoder(dev, encoder) {
13163
 * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
11202
		int num_connectors = 0;
13164
 * we can only handle plane-related operations and do not yet support
11203
		list_for_each_entry(connector,
13165
 * asynchronous commit.
Line 11204... Line -...
11204
				    &dev->mode_config.connector_list,
-
 
11205
				    base.head) {
13166
 *
11206
			if (connector->new_encoder == encoder) {
13167
 * RETURNS
11207
				WARN_ON(!connector->new_encoder->new_crtc);
-
 
Line 11208... Line 13168...
11208
				num_connectors++;
13168
 * Zero for success or -errno.
11209
			}
13169
 */
11210
		}
13170
static int intel_atomic_commit(struct drm_device *dev,
Line 11211... Line -...
11211
 
-
 
11212
		if (num_connectors == 0)
-
 
11213
		encoder->new_crtc = NULL;
13171
			       struct drm_atomic_state *state,
11214
		else if (num_connectors > 1)
-
 
11215
			return -EINVAL;
-
 
11216
 
13172
			       bool async)
11217
		/* Only now check for crtc changes so we don't miss encoders
-
 
11218
		 * that will be disabled. */
-
 
Line 11219... Line -...
11219
		if (&encoder->new_crtc->base != encoder->base.crtc) {
-
 
11220
			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
-
 
11221
			config->mode_changed = true;
13173
{
Line 11222... Line -...
11222
		}
-
 
11223
	}
13174
	struct drm_i915_private *dev_priv = dev->dev_private;
11224
	/* Now we've also updated encoder->new_crtc for all encoders. */
13175
	struct drm_crtc *crtc;
Line 11225... Line -...
11225
	list_for_each_entry(connector, &dev->mode_config.connector_list,
-
 
11226
			    base.head) {
-
 
11227
		if (connector->new_encoder)
-
 
11228
			if (connector->new_encoder != connector->encoder)
13176
	struct drm_crtc_state *crtc_state;
11229
				connector->encoder = connector->new_encoder;
-
 
11230
	}
-
 
11231
	for_each_intel_crtc(dev, crtc) {
13177
	int ret = 0;
Line 11232... Line 13178...
11232
		crtc->new_enabled = false;
13178
	int i;
11233
 
-
 
11234
		for_each_intel_encoder(dev, encoder) {
-
 
11235
			if (encoder->new_crtc == crtc) {
-
 
11236
				crtc->new_enabled = true;
-
 
11237
				break;
-
 
11238
			}
-
 
11239
		}
-
 
11240
 
-
 
11241
		if (crtc->new_enabled != crtc->base.enabled) {
-
 
Line 11242... Line -...
11242
			DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
-
 
11243
				      crtc->new_enabled ? "en" : "dis");
13179
	bool any_ms = false;
11244
			config->mode_changed = true;
-
 
11245
		}
-
 
11246
 
-
 
Line 11247... Line -...
11247
		if (crtc->new_enabled)
-
 
11248
			crtc->new_config = &crtc->config;
-
 
11249
		else
-
 
11250
			crtc->new_config = NULL;
-
 
11251
	}
13180
 
Line 11252... Line -...
11252
 
-
 
11253
	return 0;
13181
	if (async) {
11254
}
13182
		DRM_DEBUG_KMS("i915 does not yet support async commit\n");
Line 11255... Line -...
11255
 
-
 
11256
static void disable_crtc_nofb(struct intel_crtc *crtc)
-
 
11257
{
-
 
11258
	struct drm_device *dev = crtc->base.dev;
-
 
11259
	struct intel_encoder *encoder;
13183
		return -EINVAL;
11260
	struct intel_connector *connector;
-
 
11261
 
-
 
11262
	DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
-
 
11263
		      pipe_name(crtc->pipe));
-
 
11264
 
-
 
11265
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
-
 
11266
		if (connector->new_encoder &&
-
 
Line 11267... Line -...
11267
		    connector->new_encoder->new_crtc == crtc)
-
 
11268
			connector->new_encoder = NULL;
-
 
11269
	}
-
 
11270
 
-
 
11271
	for_each_intel_encoder(dev, encoder) {
-
 
11272
		if (encoder->new_crtc == crtc)
13184
	}
11273
			encoder->new_crtc = NULL;
13185
 
Line 11274... Line 13186...
11274
	}
13186
	ret = drm_atomic_helper_prepare_planes(dev, state);
-
 
13187
	if (ret)
11275
 
13188
		return ret;
11276
	crtc->new_enabled = false;
13189
 
11277
	crtc->new_config = NULL;
-
 
11278
}
13190
	drm_atomic_helper_swap_state(dev, state);
-
 
13191
 
Line 11279... Line -...
11279
 
-
 
11280
static int intel_crtc_set_config(struct drm_mode_set *set)
13192
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
11281
{
13193
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11282
	struct drm_device *dev;
13194
 
11283
	struct drm_mode_set save_set;
13195
		if (!needs_modeset(crtc->state))
11284
	struct intel_set_config *config;
13196
			continue;
11285
	struct intel_crtc_config *pipe_config;
-
 
-
 
13197
 
Line 11286... Line 13198...
11286
	unsigned modeset_pipes, prepare_pipes, disable_pipes;
13198
		any_ms = true;
Line -... Line 13199...
-
 
13199
		intel_pre_plane_update(intel_crtc);
11287
	int ret;
13200
 
-
 
13201
		if (crtc_state->active) {
-
 
13202
			intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
11288
 
13203
			dev_priv->display.crtc_disable(crtc);
-
 
13204
			intel_crtc->active = false;
Line 11289... Line -...
11289
	BUG_ON(!set);
-
 
11290
	BUG_ON(!set->crtc);
-
 
11291
	BUG_ON(!set->crtc->helper_private);
-
 
11292
 
-
 
11293
	/* Enforce sane interface api - has been abused by the fb helper. */
13205
			intel_disable_shared_dpll(intel_crtc);
11294
	BUG_ON(!set->mode && set->fb);
13206
		}
11295
	BUG_ON(set->fb && set->num_connectors == 0);
-
 
11296
 
13207
	}
Line 11297... Line -...
11297
	if (set->fb) {
-
 
11298
		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13208
 
11299
				set->crtc->base.id, set->fb->base.id,
13209
	/* Only after disabling all output pipelines that will be changed can we
11300
				(int)set->num_connectors, set->x, set->y);
-
 
11301
	} else {
13210
	 * update the the output configuration. */
11302
		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
-
 
11303
	}
13211
	intel_modeset_update_crtc_state(state);
11304
 
-
 
11305
	dev = set->crtc->dev;
-
 
11306
 
-
 
11307
	ret = -ENOMEM;
13212
 
Line 11308... Line 13213...
11308
	config = kzalloc(sizeof(*config), GFP_KERNEL);
13213
	if (any_ms) {
11309
	if (!config)
-
 
11310
		goto out_config;
-
 
11311
 
13214
		intel_shared_dpll_commit(state);
11312
	ret = intel_set_config_save_state(dev, config);
13215
 
11313
	if (ret)
-
 
11314
		goto out_config;
-
 
11315
 
-
 
11316
	save_set.crtc = set->crtc;
-
 
11317
	save_set.mode = &set->crtc->mode;
-
 
11318
	save_set.x = set->crtc->x;
-
 
11319
	save_set.y = set->crtc->y;
-
 
11320
	save_set.fb = set->crtc->primary->fb;
-
 
11321
 
-
 
11322
	/* Compute whether we need a full modeset, only an fb base update or no
-
 
11323
	 * change at all. In the future we might also check whether only the
-
 
11324
	 * mode changed, e.g. for LVDS where we only change the panel fitter in
-
 
11325
	 * such cases. */
-
 
11326
	intel_set_config_compute_mode_changes(set, config);
-
 
11327
 
-
 
11328
	ret = intel_modeset_stage_output_state(dev, set, config);
13216
		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
Line 11329... Line -...
11329
	if (ret)
-
 
11330
		goto fail;
13217
		modeset_update_crtc_power_domains(state);
11331
 
-
 
11332
	pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
-
 
Line 11333... Line 13218...
11333
						   set->fb,
13218
	}
11334
						   &modeset_pipes,
13219
 
11335
						   &prepare_pipes,
13220
	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
11336
						   &disable_pipes);
13221
	for_each_crtc_in_state(state, crtc, crtc_state, i) {
11337
	if (IS_ERR(pipe_config)) {
13222
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
13223
		bool modeset = needs_modeset(crtc->state);
-
 
13224
		bool update_pipe = !modeset &&
11338
		ret = PTR_ERR(pipe_config);
13225
			to_intel_crtc_state(crtc->state)->update_pipe;
Line 11339... Line 13226...
11339
		goto fail;
13226
		unsigned long put_domains = 0;
11340
	} else if (pipe_config) {
13227
 
11341
		if (pipe_config->has_audio !=
13228
		if (modeset && crtc->state->active) {
Line 11522... Line 13409...
11522
		dev_priv->num_shared_dpll = 0;
13409
		dev_priv->num_shared_dpll = 0;
Line 11523... Line 13410...
11523
 
13410
 
11524
	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13411
	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Line -... Line 13412...
-
 
13412
}
-
 
13413
 
-
 
13414
/**
-
 
13415
 * intel_prepare_plane_fb - Prepare fb for usage on plane
-
 
13416
 * @plane: drm plane to prepare for
-
 
13417
 * @fb: framebuffer to prepare for presentation
-
 
13418
 *
-
 
13419
 * Prepares a framebuffer for usage on a display plane.  Generally this
-
 
13420
 * involves pinning the underlying object and updating the frontbuffer tracking
-
 
13421
 * bits.  Some older platforms need special physical address handling for
-
 
13422
 * cursor planes.
-
 
13423
 *
11525
}
13424
 * Returns 0 on success, negative error code on failure.
11526
 
13425
 */
-
 
13426
int
11527
static int
13427
intel_prepare_plane_fb(struct drm_plane *plane,
11528
intel_primary_plane_disable(struct drm_plane *plane)
13428
		       const struct drm_plane_state *new_state)
-
 
13429
{
-
 
13430
	struct drm_device *dev = plane->dev;
11529
{
13431
	struct drm_framebuffer *fb = new_state->fb;
-
 
13432
	struct intel_plane *intel_plane = to_intel_plane(plane);
-
 
13433
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Line 11530... Line 13434...
11530
	struct drm_device *dev = plane->dev;
13434
	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11531
	struct intel_crtc *intel_crtc;
13435
	int ret = 0;
Line 11532... Line -...
11532
 
-
 
11533
	if (!plane->fb)
-
 
11534
		return 0;
13436
 
Line 11535... Line -...
11535
 
-
 
11536
	BUG_ON(!plane->crtc);
13437
	if (!obj)
11537
 
13438
		return 0;
11538
	intel_crtc = to_intel_crtc(plane->crtc);
13439
 
11539
 
13440
	mutex_lock(&dev->struct_mutex);
11540
	/*
13441
 
11541
	 * Even though we checked plane->fb above, it's still possible that
13442
	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
-
 
13443
	    INTEL_INFO(dev)->cursor_needs_physical) {
11542
	 * the primary plane has been implicitly disabled because the crtc
13444
		int align = IS_I830(dev) ? 16 * 1024 : 256;
11543
	 * coordinates given weren't visible, or because we detected
13445
        ret = 1;
11544
	 * that it was 100% covered by a sprite plane.  Or, the CRTC may be
-
 
11545
	 * off and we've set a fb, but haven't actually turned on the CRTC yet.
-
 
Line 11546... Line 13446...
11546
	 * In either case, we need to unpin the FB and let the fb pointer get
13446
		if (ret)
11547
	 * updated, but otherwise we don't need to touch the hardware.
13447
			DRM_DEBUG_KMS("failed to attach phys object\n");
Line 11548... Line -...
11548
	 */
-
 
11549
	if (!intel_crtc->primary_enabled)
-
 
11550
		goto disable_unpin;
-
 
11551
 
-
 
11552
//   intel_crtc_wait_for_pending_flips(plane->crtc);
-
 
11553
	intel_disable_primary_hw_plane(plane, plane->crtc);
13448
	} else {
11554
 
-
 
Line 11555... Line 13449...
11555
disable_unpin:
13449
		ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
11556
	mutex_lock(&dev->struct_mutex);
13450
	}
Line -... Line 13451...
-
 
13451
 
-
 
13452
	if (ret == 0)
-
 
13453
		i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
-
 
13454
 
-
 
13455
	mutex_unlock(&dev->struct_mutex);
-
 
13456
 
-
 
13457
	return ret;
11557
	i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
13458
}
11558
			  INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
13459
 
11559
	intel_unpin_fb_obj(intel_fb_obj(plane->fb));
13460
/**
11560
	mutex_unlock(&dev->struct_mutex);
13461
 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11561
	plane->fb = NULL;
-
 
11562
 
-
 
11563
	return 0;
13462
 * @plane: drm plane to clean up for
11564
}
13463
 * @fb: old framebuffer that was on plane
11565
 
-
 
Line -... Line 13464...
-
 
13464
 *
-
 
13465
 * Cleans up a framebuffer that has just been removed from a plane.
-
 
13466
 */
11566
static int
13467
void
11567
intel_check_primary_plane(struct drm_plane *plane,
13468
intel_cleanup_plane_fb(struct drm_plane *plane,
11568
			  struct intel_plane_state *state)
13469
		       const struct drm_plane_state *old_state)
11569
{
13470
{
11570
	struct drm_crtc *crtc = state->crtc;
13471
	struct drm_device *dev = plane->dev;
-
 
13472
	struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
11571
	struct drm_framebuffer *fb = state->fb;
13473
 
Line 11572... Line 13474...
11572
	struct drm_rect *dest = &state->dst;
13474
	if (!obj)
11573
	struct drm_rect *src = &state->src;
-
 
11574
	const struct drm_rect *clip = &state->clip;
13475
		return;
11575
 
13476
 
11576
	return drm_plane_helper_check_update(plane, crtc, fb,
13477
	if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11577
					     src, dest, clip,
-
 
11578
					     DRM_PLANE_HELPER_NO_SCALING,
13478
	    !INTEL_INFO(dev)->cursor_needs_physical) {
11579
					     DRM_PLANE_HELPER_NO_SCALING,
-
 
11580
					     false, true, &state->visible);
-
 
11581
}
13479
		mutex_lock(&dev->struct_mutex);
11582
 
-
 
11583
static int
13480
		intel_unpin_fb_obj(old_state->fb, old_state);
Line -... Line 13481...
-
 
13481
		mutex_unlock(&dev->struct_mutex);
-
 
13482
	}
Line -... Line 13483...
-
 
13483
}
-
 
13484
 
-
 
13485
int
-
 
13486
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
Line 11584... Line 13487...
11584
intel_prepare_primary_plane(struct drm_plane *plane,
13487
{
11585
			    struct intel_plane_state *state)
13488
	int max_scale;
11586
{
-
 
-
 
13489
	struct drm_device *dev;
11587
	struct drm_crtc *crtc = state->crtc;
13490
	struct drm_i915_private *dev_priv;
11588
	struct drm_framebuffer *fb = state->fb;
13491
	int crtc_clock, cdclk;
11589
	struct drm_device *dev = crtc->dev;
-
 
11590
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13492
 
11591
	enum pipe pipe = intel_crtc->pipe;
13493
	if (!intel_crtc || !crtc_state)
11592
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13494
		return DRM_PLANE_HELPER_NO_SCALING;
11593
	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13495
 
-
 
13496
	dev = intel_crtc->base.dev;
11594
	int ret;
13497
	dev_priv = dev->dev_private;
-
 
13498
	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
11595
 
13499
	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
Line 11596... Line 13500...
11596
 
13500
 
-
 
13501
	if (!crtc_clock || !cdclk)
-
 
13502
		return DRM_PLANE_HELPER_NO_SCALING;
-
 
13503
 
-
 
13504
	/*
-
 
13505
	 * skl max scale is lower of:
-
 
13506
	 *    close to 3 but not 3, -1 is for that purpose
-
 
13507
	 *            or
-
 
13508
	 *    cdclk/crtc_clock
-
 
13509
	 */
-
 
13510
	max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
-
 
13511
 
-
 
13512
	return max_scale;
-
 
13513
}
-
 
13514
 
-
 
13515
static int
-
 
13516
intel_check_primary_plane(struct drm_plane *plane,
-
 
13517
			  struct intel_crtc_state *crtc_state,
-
 
13518
			  struct intel_plane_state *state)
-
 
13519
{
-
 
13520
	struct drm_crtc *crtc = state->base.crtc;
-
 
13521
	struct drm_framebuffer *fb = state->base.fb;
-
 
13522
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
-
 
13523
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
11597
 
13524
	bool can_position = false;
Line 11598... Line 13525...
11598
	if (old_obj != obj) {
13525
 
11599
		mutex_lock(&dev->struct_mutex);
13526
	/* use scaler when colorkey is not required */
11600
		ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
13527
	if (INTEL_INFO(plane->dev)->gen >= 9 &&
11601
		if (ret == 0)
13528
	    state->ckey.flags == I915_SET_COLORKEY_NONE) {
11602
			i915_gem_track_fb(old_obj, obj,
13529
		min_scale = 1;
11603
					  INTEL_FRONTBUFFER_PRIMARY(pipe));
13530
		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
11604
		mutex_unlock(&dev->struct_mutex);
13531
		can_position = true;
11605
		if (ret != 0) {
13532
	}
11606
			DRM_DEBUG_KMS("pin & fence failed\n");
13533
 
11607
		return ret;
-
 
11608
		}
-
 
11609
	}
-
 
11610
 
-
 
11611
	return 0;
-
 
11612
}
13534
	return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
Line -... Line 13535...
-
 
13535
					     &state->dst, &state->clip,
-
 
13536
					     min_scale, max_scale,
-
 
13537
					     can_position, true,
11613
 
13538
					     &state->visible);
11614
static void
13539
}
11615
intel_commit_primary_plane(struct drm_plane *plane,
13540
 
Line 11616... Line -...
11616
			   struct intel_plane_state *state)
-
 
11617
{
-
 
11618
	struct drm_crtc *crtc = state->crtc;
-
 
11619
	struct drm_framebuffer *fb = state->fb;
-
 
11620
	struct drm_device *dev = crtc->dev;
-
 
11621
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
11622
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11623
	enum pipe pipe = intel_crtc->pipe;
-
 
11624
	struct drm_framebuffer *old_fb = plane->fb;
-
 
11625
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-
 
11626
	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13541
static void
11627
	struct intel_plane *intel_plane = to_intel_plane(plane);
-
 
11628
	struct drm_rect *src = &state->src;
-
 
11629
 
-
 
11630
	crtc->primary->fb = fb;
-
 
11631
	crtc->x = src->x1 >> 16;
-
 
11632
	crtc->y = src->y1 >> 16;
-
 
11633
 
-
 
11634
	intel_plane->crtc_x = state->orig_dst.x1;
-
 
11635
	intel_plane->crtc_y = state->orig_dst.y1;
-
 
11636
	intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
-
 
11637
	intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
-
 
11638
	intel_plane->src_x = state->orig_src.x1;
-
 
11639
	intel_plane->src_y = state->orig_src.y1;
-
 
11640
	intel_plane->src_w = drm_rect_width(&state->orig_src);
-
 
11641
	intel_plane->src_h = drm_rect_height(&state->orig_src);
-
 
11642
	intel_plane->obj = obj;
-
 
11643
 
-
 
11644
	if (intel_crtc->active) {
-
 
11645
		/*
-
 
11646
		 * FBC does not work on some platforms for rotated
-
 
11647
		 * planes, so disable it when rotation is not 0 and
-
 
11648
		 * update it when rotation is set back to 0.
-
 
11649
		 *
-
 
11650
		 * FIXME: This is redundant with the fbc update done in
-
 
11651
		 * the primary plane enable function except that that
-
 
11652
		 * one is done too late. We eventually need to unify
-
 
11653
		 * this.
-
 
11654
		 */
-
 
11655
		if (intel_crtc->primary_enabled &&
-
 
11656
		    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
-
 
11657
		    dev_priv->fbc.plane == intel_crtc->plane &&
-
 
11658
		    intel_plane->rotation != BIT(DRM_ROTATE_0)) {
-
 
11659
			intel_disable_fbc(dev);
-
 
11660
		}
-
 
11661
 
-
 
11662
		if (state->visible) {
13542
intel_commit_primary_plane(struct drm_plane *plane,
11663
			bool was_enabled = intel_crtc->primary_enabled;
-
 
11664
 
-
 
11665
			/* FIXME: kill this fastboot hack */
-
 
11666
			intel_update_pipe_size(intel_crtc);
-
 
11667
 
-
 
11668
			intel_crtc->primary_enabled = true;
-
 
11669
 
-
 
11670
			dev_priv->display.update_primary_plane(crtc, plane->fb,
-
 
11671
					crtc->x, crtc->y);
-
 
11672
 
-
 
11673
	/*
-
 
Line 11674... Line 13543...
11674
			 * BDW signals flip done immediately if the plane
13543
			   struct intel_plane_state *state)
11675
			 * is disabled, even if the plane enable is already
13544
{
11676
			 * armed to occur at the next vblank :(
13545
	struct drm_crtc *crtc = state->base.crtc;
11677
			 */
13546
	struct drm_framebuffer *fb = state->base.fb;
Line -... Line 13547...
-
 
13547
	struct drm_device *dev = plane->dev;
11678
			if (IS_BROADWELL(dev) && !was_enabled)
13548
	struct drm_i915_private *dev_priv = dev->dev_private;
11679
				intel_wait_for_vblank(dev, intel_crtc->pipe);
13549
	struct intel_crtc *intel_crtc;
-
 
13550
	struct drm_rect *src = &state->src;
11680
		} else {
13551
 
-
 
13552
	crtc = crtc ? crtc : plane->crtc;
Line 11681... Line -...
11681
			/*
-
 
11682
			 * If clipping results in a non-visible primary plane,
-
 
11683
			 * we'll disable the primary plane.  Note that this is
13553
	intel_crtc = to_intel_crtc(crtc);
11684
			 * a bit different than what happens if userspace
-
 
11685
			 * explicitly disables the plane by passing fb=0
13554
 
Line 11686... Line -...
11686
	 * because plane->fb still gets set and pinned.
-
 
11687
	 */
13555
	plane->fb = fb;
11688
			intel_disable_primary_hw_plane(plane, crtc);
13556
	crtc->x = src->x1 >> 16;
11689
		}
-
 
11690
 
-
 
11691
		intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
-
 
11692
 
13557
	crtc->y = src->y1 >> 16;
11693
		mutex_lock(&dev->struct_mutex);
13558
 
11694
		intel_update_fbc(dev);
13559
	if (!crtc->state->active)
11695
		mutex_unlock(&dev->struct_mutex);
13560
		return;
11696
	}
-
 
11697
 
13561
 
11698
	if (old_fb && old_fb != fb) {
13562
	dev_priv->display.update_primary_plane(crtc, fb,
Line 11699... Line 13563...
11699
		if (intel_crtc->active)
13563
					       state->src.x1 >> 16,
11700
			intel_wait_for_vblank(dev, intel_crtc->pipe);
-
 
11701
 
-
 
11702
		mutex_lock(&dev->struct_mutex);
-
 
11703
		intel_unpin_fb_obj(old_obj);
-
 
11704
				mutex_unlock(&dev->struct_mutex);
-
 
11705
		}
-
 
11706
}
-
 
11707
 
-
 
11708
static int
-
 
11709
intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
13564
					       state->src.y1 >> 16);
11710
			     struct drm_framebuffer *fb, int crtc_x, int crtc_y,
-
 
11711
			     unsigned int crtc_w, unsigned int crtc_h,
-
 
11712
			     uint32_t src_x, uint32_t src_y,
-
 
11713
			     uint32_t src_w, uint32_t src_h)
-
 
11714
{
-
 
Line -... Line 13565...
-
 
13565
}
11715
	struct intel_plane_state state;
13566
 
11716
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13567
static void
Line 11717... Line -...
11717
	int ret;
-
 
11718
 
13568
intel_disable_primary_plane(struct drm_plane *plane,
11719
	state.crtc = crtc;
13569
			    struct drm_crtc *crtc)
Line -... Line 13570...
-
 
13570
{
11720
	state.fb = fb;
13571
	struct drm_device *dev = plane->dev;
11721
 
13572
	struct drm_i915_private *dev_priv = dev->dev_private;
11722
	/* sample coordinates in 16.16 fixed point */
13573
 
-
 
13574
	dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
Line -... Line 13575...
-
 
13575
}
11723
	state.src.x1 = src_x;
13576
 
-
 
13577
static void intel_begin_crtc_commit(struct drm_crtc *crtc,
-
 
13578
				    struct drm_crtc_state *old_crtc_state)
Line 11724... Line 13579...
11724
	state.src.x2 = src_x + src_w;
13579
{
-
 
13580
	struct drm_device *dev = crtc->dev;
11725
	state.src.y1 = src_y;
13581
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line -... Line 13582...
-
 
13582
	struct intel_crtc_state *old_intel_state =
-
 
13583
		to_intel_crtc_state(old_crtc_state);
-
 
13584
	bool modeset = needs_modeset(crtc->state);
-
 
13585
 
11726
	state.src.y2 = src_y + src_h;
13586
	if (intel_crtc->atomic.update_wm_pre)
-
 
13587
		intel_update_watermarks(crtc);
-
 
13588
 
11727
 
13589
	/* Perform vblank evasion around commit operation */
11728
	/* integer pixels */
13590
	if (crtc->state->active)
11729
	state.dst.x1 = crtc_x;
13591
		intel_pipe_update_start(intel_crtc);
11730
	state.dst.x2 = crtc_x + crtc_w;
13592
 
11731
	state.dst.y1 = crtc_y;
13593
	if (modeset)
11732
	state.dst.y2 = crtc_y + crtc_h;
13594
		return;
Line 11733... Line 13595...
11733
 
13595
 
11734
	state.clip.x1 = 0;
13596
	if (to_intel_crtc_state(crtc->state)->update_pipe)
11735
	state.clip.y1 = 0;
13597
		intel_update_pipe_config(intel_crtc, old_intel_state);
11736
	state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
13598
	else if (INTEL_INFO(dev)->gen >= 9)
-
 
13599
		skl_detach_scalers(intel_crtc);
-
 
13600
}
11737
	state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
13601
 
-
 
13602
static void intel_finish_crtc_commit(struct drm_crtc *crtc,
-
 
13603
				     struct drm_crtc_state *old_crtc_state)
-
 
13604
{
11738
 
13605
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Line 11739... Line 13606...
11739
	state.orig_src = state.src;
13606
 
11740
	state.orig_dst = state.dst;
13607
	if (crtc->state->active)
11741
 
13608
		intel_pipe_update_end(intel_crtc);
11742
	ret = intel_check_primary_plane(plane, &state);
13609
}
-
 
13610
 
11743
	if (ret)
13611
/**
11744
		return ret;
13612
 * intel_plane_destroy - destroy a plane
Line 11745... Line 13613...
11745
 
13613
 * @plane: plane to destroy
11746
	ret = intel_prepare_primary_plane(plane, &state);
13614
 *
11747
	if (ret)
13615
 * Common destruction function for all types of planes (primary, cursor,
Line -... Line 13616...
-
 
13616
 * sprite).
-
 
13617
 */
-
 
13618
void intel_plane_destroy(struct drm_plane *plane)
-
 
13619
{
-
 
13620
	struct intel_plane *intel_plane = to_intel_plane(plane);
-
 
13621
	drm_plane_cleanup(plane);
-
 
13622
	kfree(intel_plane);
11748
		return ret;
13623
}
11749
 
13624
 
-
 
13625
const struct drm_plane_funcs intel_plane_funcs = {
-
 
13626
	.update_plane = drm_atomic_helper_update_plane,
-
 
13627
	.disable_plane = drm_atomic_helper_disable_plane,
-
 
13628
	.destroy = intel_plane_destroy,
11750
	intel_commit_primary_plane(plane, &state);
13629
	.set_property = drm_atomic_helper_plane_set_property,
11751
 
13630
	.atomic_get_property = intel_plane_atomic_get_property,
-
 
13631
	.atomic_set_property = intel_plane_atomic_set_property,
-
 
13632
	.atomic_duplicate_state = intel_plane_duplicate_state,
11752
	return 0;
13633
	.atomic_destroy_state = intel_plane_destroy_state,
-
 
13634
 
11753
}
13635
};
11754
 
13636
 
Line 11755... Line 13637...
11755
/* Common destruction function for both primary and cursor planes */
13637
static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
-
 
13638
						    int pipe)
-
 
13639
{
-
 
13640
	struct intel_plane *primary;
11756
static void intel_plane_destroy(struct drm_plane *plane)
13641
	struct intel_plane_state *state;
11757
{
13642
	const uint32_t *intel_primary_formats;
11758
	struct intel_plane *intel_plane = to_intel_plane(plane);
13643
	unsigned int num_formats;
11759
	drm_plane_cleanup(plane);
13644
 
11760
	kfree(intel_plane);
13645
	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11761
}
13646
	if (primary == NULL)
Line 11762... Line 13647...
11762
 
13647
		return NULL;
11763
static const struct drm_plane_funcs intel_primary_plane_funcs = {
13648
 
11764
	.update_plane = intel_primary_plane_setplane,
13649
	state = intel_create_plane_state(&primary->base);
11765
	.disable_plane = intel_primary_plane_disable,
13650
	if (!state) {
Line 11766... Line 13651...
11766
	.destroy = intel_plane_destroy,
13651
		kfree(primary);
11767
	.set_property = intel_plane_set_property
-
 
11768
};
-
 
11769
 
13652
		return NULL;
11770
static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
-
 
11771
						    int pipe)
-
 
11772
{
-
 
11773
	struct intel_plane *primary;
-
 
11774
	const uint32_t *intel_primary_formats;
-
 
11775
	int num_formats;
-
 
11776
 
13653
	}
-
 
13654
	primary->base.state = &state->base;
Line 11777... Line 13655...
11777
	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13655
 
11778
	if (primary == NULL)
13656
	primary->can_scale = false;
Line 11779... Line -...
11779
		return NULL;
-
 
11780
 
13657
	primary->max_downscale = 1;
11781
	primary->can_scale = false;
13658
	if (INTEL_INFO(dev)->gen >= 9) {
11782
	primary->max_downscale = 1;
13659
		primary->can_scale = true;
-
 
13660
		state->scaler_id = -1;
11783
	primary->pipe = pipe;
13661
	}
Line 11784... Line 13662...
11784
	primary->plane = pipe;
13662
	primary->pipe = pipe;
-
 
13663
	primary->plane = pipe;
Line -... Line 13664...
-
 
13664
	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
11785
	primary->rotation = BIT(DRM_ROTATE_0);
13665
	primary->check_plane = intel_check_primary_plane;
-
 
13666
	primary->commit_plane = intel_commit_primary_plane;
-
 
13667
	primary->disable_plane = intel_disable_primary_plane;
-
 
13668
	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
-
 
13669
		primary->plane = !pipe;
-
 
13670
 
11786
	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13671
	if (INTEL_INFO(dev)->gen >= 9) {
Line 11787... Line 13672...
11787
		primary->plane = !pipe;
13672
		intel_primary_formats = skl_primary_formats;
11788
 
13673
		num_formats = ARRAY_SIZE(skl_primary_formats);
-
 
13674
	} else if (INTEL_INFO(dev)->gen >= 4) {
11789
	if (INTEL_INFO(dev)->gen <= 3) {
13675
		intel_primary_formats = i965_primary_formats;
11790
		intel_primary_formats = intel_primary_formats_gen2;
13676
		num_formats = ARRAY_SIZE(i965_primary_formats);
11791
		num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13677
	} else {
11792
	} else {
-
 
11793
		intel_primary_formats = intel_primary_formats_gen4;
13678
		intel_primary_formats = i8xx_primary_formats;
11794
		num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
-
 
11795
	}
-
 
11796
 
-
 
11797
	drm_universal_plane_init(dev, &primary->base, 0,
13679
		num_formats = ARRAY_SIZE(i8xx_primary_formats);
11798
				 &intel_primary_plane_funcs,
13680
	}
11799
				 intel_primary_formats, num_formats,
13681
 
11800
				 DRM_PLANE_TYPE_PRIMARY);
13682
	drm_universal_plane_init(dev, &primary->base, 0,
Line 11801... Line 13683...
11801
 
13683
				 &intel_plane_funcs,
11802
	if (INTEL_INFO(dev)->gen >= 4) {
13684
				 intel_primary_formats, num_formats,
11803
		if (!dev->mode_config.rotation_property)
13685
				 DRM_PLANE_TYPE_PRIMARY);
11804
			dev->mode_config.rotation_property =
13686
 
11805
				drm_mode_create_rotation_property(dev,
13687
	if (INTEL_INFO(dev)->gen >= 4)
11806
							BIT(DRM_ROTATE_0) |
13688
		intel_create_rotation_property(dev, primary);
11807
							BIT(DRM_ROTATE_180));
13689
 
Line 11808... Line -...
11808
		if (dev->mode_config.rotation_property)
-
 
11809
			drm_object_attach_property(&primary->base.base,
13690
	drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
11810
				dev->mode_config.rotation_property,
13691
 
11811
				primary->rotation);
13692
	return &primary->base;
Line 11812... Line 13693...
11812
	}
13693
}
11813
 
-
 
11814
	return &primary->base;
-
 
11815
}
13694
 
11816
 
13695
void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
-
 
13696
{
11817
static int
13697
	if (!dev->mode_config.rotation_property) {
11818
intel_cursor_plane_disable(struct drm_plane *plane)
13698
		unsigned long flags = BIT(DRM_ROTATE_0) |
Line 11819... Line 13699...
11819
{
13699
			BIT(DRM_ROTATE_180);
11820
	if (!plane->fb)
13700
 
11821
		return 0;
13701
		if (INTEL_INFO(dev)->gen >= 9)
11822
 
13702
			flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
11823
	BUG_ON(!plane->crtc);
13703
 
Line 11824... Line 13704...
11824
 
13704
		dev->mode_config.rotation_property =
11825
	return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
-
 
11826
}
-
 
11827
 
-
 
11828
static int
-
 
11829
intel_check_cursor_plane(struct drm_plane *plane,
-
 
11830
			 struct intel_plane_state *state)
13705
			drm_mode_create_rotation_property(dev, flags);
11831
{
13706
	}
11832
	struct drm_crtc *crtc = state->crtc;
13707
	if (dev->mode_config.rotation_property)
11833
	struct drm_device *dev = crtc->dev;
-
 
Line -... Line 13708...
-
 
13708
		drm_object_attach_property(&plane->base.base,
-
 
13709
				dev->mode_config.rotation_property,
-
 
13710
				plane->base.state->rotation);
-
 
13711
}
-
 
13712
 
-
 
13713
static int
-
 
13714
intel_check_cursor_plane(struct drm_plane *plane,
-
 
13715
			 struct intel_crtc_state *crtc_state,
-
 
13716
			 struct intel_plane_state *state)
-
 
13717
{
-
 
13718
	struct drm_crtc *crtc = crtc_state->base.crtc;
-
 
13719
	struct drm_framebuffer *fb = state->base.fb;
-
 
13720
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11834
	struct drm_framebuffer *fb = state->fb;
13721
	enum pipe pipe = to_intel_plane(plane)->pipe;
11835
	struct drm_rect *dest = &state->dst;
13722
	unsigned stride;
Line 11836... Line -...
11836
	struct drm_rect *src = &state->src;
-
 
11837
	const struct drm_rect *clip = &state->clip;
-
 
11838
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-
 
11839
	int crtc_w, crtc_h;
-
 
11840
	unsigned stride;
-
 
11841
	int ret;
-
 
11842
 
-
 
11843
	ret = drm_plane_helper_check_update(plane, crtc, fb,
-
 
11844
					    src, dest, clip,
-
 
11845
					    DRM_PLANE_HELPER_NO_SCALING,
-
 
11846
					    DRM_PLANE_HELPER_NO_SCALING,
-
 
11847
					    true, true, &state->visible);
-
 
11848
	if (ret)
-
 
11849
		return ret;
-
 
11850
 
-
 
11851
 
-
 
11852
	/* if we want to turn off the cursor ignore width and height */
-
 
11853
	if (!obj)
-
 
11854
		return 0;
-
 
11855
 
-
 
11856
	/* Check for which cursor types we support */
-
 
11857
	crtc_w = drm_rect_width(&state->orig_dst);
-
 
11858
	crtc_h = drm_rect_height(&state->orig_dst);
-
 
11859
	if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
-
 
11860
		DRM_DEBUG("Cursor dimension not supported\n");
-
 
11861
		return -EINVAL;
-
 
11862
	}
-
 
11863
 
-
 
11864
	stride = roundup_pow_of_two(crtc_w) * 4;
-
 
11865
	if (obj->base.size < stride * crtc_h) {
-
 
11866
		DRM_DEBUG_KMS("buffer is too small\n");
-
 
11867
		return -ENOMEM;
-
 
11868
	}
-
 
11869
 
13723
	int ret;
11870
	if (fb == crtc->cursor->fb)
13724
 
11871
		return 0;
-
 
Line 11872... Line 13725...
11872
 
13725
	ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
11873
	/* we only need to pin inside GTT if cursor is non-phy */
13726
					    &state->dst, &state->clip,
11874
	mutex_lock(&dev->struct_mutex);
-
 
11875
	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
-
 
11876
		DRM_DEBUG_KMS("cursor cannot be tiled\n");
-
 
11877
		ret = -EINVAL;
13727
					    DRM_PLANE_HELPER_NO_SCALING,
11878
	}
13728
					    DRM_PLANE_HELPER_NO_SCALING,
11879
	mutex_unlock(&dev->struct_mutex);
13729
					    true, true, &state->visible);
11880
 
-
 
11881
	return ret;
13730
	if (ret)
Line -... Line 13731...
-
 
13731
		return ret;
-
 
13732
 
-
 
13733
	/* if we want to turn off the cursor ignore width and height */
-
 
13734
	if (!obj)
-
 
13735
		return 0;
-
 
13736
 
11882
}
13737
	/* Check for which cursor types we support */
-
 
13738
	if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
11883
 
13739
		DRM_DEBUG("Cursor dimension %dx%d not supported\n",
Line 11884... Line -...
11884
static int
-
 
11885
intel_commit_cursor_plane(struct drm_plane *plane,
-
 
11886
			  struct intel_plane_state *state)
-
 
11887
{
-
 
11888
	struct drm_crtc *crtc = state->crtc;
-
 
11889
	struct drm_framebuffer *fb = state->fb;
-
 
11890
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
 
11891
	struct intel_plane *intel_plane = to_intel_plane(plane);
-
 
11892
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13740
			  state->base.crtc_w, state->base.crtc_h);
11893
	struct drm_i915_gem_object *obj = intel_fb->obj;
-
 
11894
	int crtc_w, crtc_h;
13741
		return -EINVAL;
11895
 
-
 
11896
	crtc->cursor_x = state->orig_dst.x1;
-
 
11897
	crtc->cursor_y = state->orig_dst.y1;
-
 
11898
 
-
 
11899
	intel_plane->crtc_x = state->orig_dst.x1;
-
 
Line -... Line 13742...
-
 
13742
	}
-
 
13743
 
-
 
13744
	stride = roundup_pow_of_two(state->base.crtc_w) * 4;
11900
	intel_plane->crtc_y = state->orig_dst.y1;
13745
	if (obj->base.size < stride * state->base.crtc_h) {
-
 
13746
		DRM_DEBUG_KMS("buffer is too small\n");
11901
	intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
13747
		return -ENOMEM;
Line 11902... Line 13748...
11902
	intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
13748
	}
11903
	intel_plane->src_x = state->orig_src.x1;
-
 
11904
	intel_plane->src_y = state->orig_src.y1;
-
 
Line -... Line 13749...
-
 
13749
 
11905
	intel_plane->src_w = drm_rect_width(&state->orig_src);
13750
	if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
11906
	intel_plane->src_h = drm_rect_height(&state->orig_src);
13751
		DRM_DEBUG_KMS("cursor cannot be tiled\n");
Line 11907... Line -...
11907
	intel_plane->obj = obj;
-
 
11908
 
-
 
11909
	if (fb != crtc->cursor->fb) {
-
 
11910
		crtc_w = drm_rect_width(&state->orig_dst);
-
 
11911
		crtc_h = drm_rect_height(&state->orig_dst);
-
 
11912
		return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
-
 
11913
	} else {
-
 
11914
		intel_crtc_update_cursor(crtc, state->visible);
13752
		return -EINVAL;
11915
 
13753
	}
11916
 
13754
 
11917
		return 0;
13755
	/*
-
 
13756
	 * There's something wrong with the cursor on CHV pipe C.
Line 11918... Line 13757...
11918
	}
13757
	 * If it straddles the left edge of the screen then
11919
}
13758
	 * moving it away from the edge or disabling it often
11920
 
13759
	 * results in a pipe underrun, and often that can lead to
Line -... Line 13760...
-
 
13760
	 * dead pipe (constant underrun reported, and it scans
-
 
13761
	 * out just a solid color). To recover from that, the
-
 
13762
	 * display power well must be turned off and on again.
-
 
13763
	 * Refuse the put the cursor into that compromised position.
-
 
13764
	 */
-
 
13765
	if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
-
 
13766
	    state->visible && state->base.crtc_x < 0) {
11921
static int
13767
		DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11922
intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
13768
		return -EINVAL;
11923
			  struct drm_framebuffer *fb, int crtc_x, int crtc_y,
13769
	}
11924
			  unsigned int crtc_w, unsigned int crtc_h,
13770
 
-
 
13771
	return 0;
-
 
13772
}
11925
			  uint32_t src_x, uint32_t src_y,
13773
 
-
 
13774
static void
Line 11926... Line 13775...
11926
			  uint32_t src_w, uint32_t src_h)
13775
intel_disable_cursor_plane(struct drm_plane *plane,
11927
{
13776
			   struct drm_crtc *crtc)
11928
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13777
{
11929
	struct intel_plane_state state;
13778
	intel_crtc_update_cursor(crtc, false);
11930
	int ret;
13779
}
Line 11931... Line 13780...
11931
 
13780
 
Line 11994... Line 13843...
11994
							BIT(DRM_ROTATE_0) |
13843
							BIT(DRM_ROTATE_0) |
11995
							BIT(DRM_ROTATE_180));
13844
							BIT(DRM_ROTATE_180));
11996
		if (dev->mode_config.rotation_property)
13845
		if (dev->mode_config.rotation_property)
11997
			drm_object_attach_property(&cursor->base.base,
13846
			drm_object_attach_property(&cursor->base.base,
11998
				dev->mode_config.rotation_property,
13847
				dev->mode_config.rotation_property,
11999
				cursor->rotation);
13848
				state->base.rotation);
12000
	}
13849
	}
Line -... Line 13850...
-
 
13850
 
-
 
13851
	if (INTEL_INFO(dev)->gen >=9)
-
 
13852
		state->scaler_id = -1;
-
 
13853
 
-
 
13854
	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12001
 
13855
 
12002
	return &cursor->base;
13856
	return &cursor->base;
Line -... Line 13857...
-
 
13857
}
-
 
13858
 
-
 
13859
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
-
 
13860
	struct intel_crtc_state *crtc_state)
-
 
13861
{
-
 
13862
	int i;
-
 
13863
	struct intel_scaler *intel_scaler;
-
 
13864
	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
-
 
13865
 
-
 
13866
	for (i = 0; i < intel_crtc->num_scalers; i++) {
-
 
13867
		intel_scaler = &scaler_state->scalers[i];
-
 
13868
		intel_scaler->in_use = 0;
-
 
13869
		intel_scaler->mode = PS_SCALER_MODE_DYN;
-
 
13870
	}
-
 
13871
 
-
 
13872
	scaler_state->scaler_id = -1;
12003
}
13873
}
12004
 
13874
 
12005
static void intel_crtc_init(struct drm_device *dev, int pipe)
13875
static void intel_crtc_init(struct drm_device *dev, int pipe)
12006
{
13876
{
-
 
13877
	struct drm_i915_private *dev_priv = dev->dev_private;
12007
	struct drm_i915_private *dev_priv = dev->dev_private;
13878
	struct intel_crtc *intel_crtc;
12008
	struct intel_crtc *intel_crtc;
13879
	struct intel_crtc_state *crtc_state = NULL;
12009
	struct drm_plane *primary = NULL;
13880
	struct drm_plane *primary = NULL;
Line 12010... Line 13881...
12010
	struct drm_plane *cursor = NULL;
13881
	struct drm_plane *cursor = NULL;
12011
	int i, ret;
13882
	int i, ret;
12012
 
13883
 
Line -... Line 13884...
-
 
13884
	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
-
 
13885
	if (intel_crtc == NULL)
-
 
13886
		return;
-
 
13887
 
-
 
13888
	crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
-
 
13889
	if (!crtc_state)
-
 
13890
		goto fail;
-
 
13891
	intel_crtc->config = crtc_state;
-
 
13892
	intel_crtc->base.state = &crtc_state->base;
-
 
13893
	crtc_state->base.crtc = &intel_crtc->base;
-
 
13894
 
-
 
13895
	/* initialize shared scalers */
-
 
13896
	if (INTEL_INFO(dev)->gen >= 9) {
-
 
13897
		if (pipe == PIPE_C)
-
 
13898
			intel_crtc->num_scalers = 1;
-
 
13899
		else
-
 
13900
			intel_crtc->num_scalers = SKL_NUM_SCALERS;
12013
	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13901
 
12014
	if (intel_crtc == NULL)
13902
		skl_init_scalers(dev, intel_crtc, crtc_state);
12015
		return;
13903
	}
Line 12016... Line 13904...
12016
 
13904
 
Line 12047... Line 13935...
12047
 
13935
 
12048
	intel_crtc->cursor_base = ~0;
13936
	intel_crtc->cursor_base = ~0;
12049
	intel_crtc->cursor_cntl = ~0;
13937
	intel_crtc->cursor_cntl = ~0;
Line -... Line 13938...
-
 
13938
	intel_crtc->cursor_size = ~0;
-
 
13939
 
12050
	intel_crtc->cursor_size = ~0;
13940
	intel_crtc->wm.cxsr_allowed = true;
12051
 
13941
 
12052
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13942
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12053
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13943
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
Line 12062... Line 13952...
12062
fail:
13952
fail:
12063
	if (primary)
13953
	if (primary)
12064
		drm_plane_cleanup(primary);
13954
		drm_plane_cleanup(primary);
12065
	if (cursor)
13955
	if (cursor)
12066
		drm_plane_cleanup(cursor);
13956
		drm_plane_cleanup(cursor);
-
 
13957
	kfree(crtc_state);
12067
	kfree(intel_crtc);
13958
	kfree(intel_crtc);
12068
}
13959
}
Line 12069... Line 13960...
12069
 
13960
 
12070
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13961
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
Line 12085... Line 13976...
12085
{
13976
{
12086
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13977
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12087
	struct drm_crtc *drmmode_crtc;
13978
	struct drm_crtc *drmmode_crtc;
12088
	struct intel_crtc *crtc;
13979
	struct intel_crtc *crtc;
Line 12089... Line -...
12089
 
-
 
12090
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-
 
12091
		return -ENODEV;
-
 
12092
 
13980
 
Line 12093... Line 13981...
12093
	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13981
	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12094
 
13982
 
12095
	if (!drmmode_crtc) {
13983
	if (!drmmode_crtc) {
Line 12134... Line 14022...
12134
		return false;
14022
		return false;
Line 12135... Line 14023...
12135
 
14023
 
12136
	return true;
14024
	return true;
Line 12137... Line -...
12137
}
-
 
12138
 
-
 
12139
const char *intel_output_name(int output)
-
 
12140
{
-
 
12141
	static const char *names[] = {
-
 
12142
		[INTEL_OUTPUT_UNUSED] = "Unused",
-
 
12143
		[INTEL_OUTPUT_ANALOG] = "Analog",
-
 
12144
		[INTEL_OUTPUT_DVO] = "DVO",
-
 
12145
		[INTEL_OUTPUT_SDVO] = "SDVO",
-
 
12146
		[INTEL_OUTPUT_LVDS] = "LVDS",
-
 
12147
		[INTEL_OUTPUT_TVOUT] = "TV",
-
 
12148
		[INTEL_OUTPUT_HDMI] = "HDMI",
-
 
12149
		[INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
-
 
12150
		[INTEL_OUTPUT_EDP] = "eDP",
-
 
12151
		[INTEL_OUTPUT_DSI] = "DSI",
-
 
12152
		[INTEL_OUTPUT_UNKNOWN] = "Unknown",
-
 
12153
	};
-
 
12154
 
-
 
12155
	if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
-
 
12156
		return "Invalid";
-
 
12157
 
-
 
12158
	return names[output];
-
 
12159
}
14025
}
12160
 
14026
 
12161
static bool intel_crt_present(struct drm_device *dev)
14027
static bool intel_crt_present(struct drm_device *dev)
Line 12162... Line 14028...
12162
{
14028
{
Line 12186... Line 14052...
12186
	intel_lvds_init(dev);
14052
	intel_lvds_init(dev);
Line 12187... Line 14053...
12187
 
14053
 
12188
	if (intel_crt_present(dev))
14054
	if (intel_crt_present(dev))
Line -... Line 14055...
-
 
14055
		intel_crt_init(dev);
-
 
14056
 
-
 
14057
	if (IS_BROXTON(dev)) {
-
 
14058
		/*
-
 
14059
		 * FIXME: Broxton doesn't support port detection via the
-
 
14060
		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
-
 
14061
		 * detect the ports.
-
 
14062
		 */
-
 
14063
		intel_ddi_init(dev, PORT_A);
12189
	intel_crt_init(dev);
14064
		intel_ddi_init(dev, PORT_B);
12190
 
14065
		intel_ddi_init(dev, PORT_C);
Line -... Line 14066...
-
 
14066
	} else if (HAS_DDI(dev)) {
12191
	if (HAS_DDI(dev)) {
14067
		int found;
-
 
14068
 
-
 
14069
		/*
-
 
14070
		 * Haswell uses DDI functions to detect digital outputs.
12192
		int found;
14071
		 * On SKL pre-D0 the strap isn't connected, so we assume
12193
 
14072
		 * it's there.
12194
		/* Haswell uses DDI functions to detect digital outputs */
14073
		 */
12195
		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14074
		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
Line 12196... Line 14075...
12196
		/* DDI A only supports eDP */
14075
		/* WaIgnoreDDIAStrap: skl */
12197
		if (found)
14076
		if (found || IS_SKYLAKE(dev))
12198
			intel_ddi_init(dev, PORT_A);
14077
			intel_ddi_init(dev, PORT_A);
Line 12205... Line 14084...
12205
			intel_ddi_init(dev, PORT_B);
14084
			intel_ddi_init(dev, PORT_B);
12206
		if (found & SFUSE_STRAP_DDIC_DETECTED)
14085
		if (found & SFUSE_STRAP_DDIC_DETECTED)
12207
			intel_ddi_init(dev, PORT_C);
14086
			intel_ddi_init(dev, PORT_C);
12208
		if (found & SFUSE_STRAP_DDID_DETECTED)
14087
		if (found & SFUSE_STRAP_DDID_DETECTED)
12209
			intel_ddi_init(dev, PORT_D);
14088
			intel_ddi_init(dev, PORT_D);
-
 
14089
		/*
-
 
14090
		 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
-
 
14091
		 */
-
 
14092
		if (IS_SKYLAKE(dev) &&
-
 
14093
		    (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
-
 
14094
		     dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
-
 
14095
		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
-
 
14096
			intel_ddi_init(dev, PORT_E);
-
 
14097
 
12210
	} else if (HAS_PCH_SPLIT(dev)) {
14098
	} else if (HAS_PCH_SPLIT(dev)) {
12211
		int found;
14099
		int found;
12212
		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14100
		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Line 12213... Line 14101...
12213
 
14101
 
Line 12242... Line 14130...
12242
		 * eDP ports may have been muxed to an alternate function.
14130
		 * eDP ports may have been muxed to an alternate function.
12243
		 * Thus we can't rely on the DP_DETECTED bit alone to detect
14131
		 * Thus we can't rely on the DP_DETECTED bit alone to detect
12244
		 * eDP ports. Consult the VBT as well as DP_DETECTED to
14132
		 * eDP ports. Consult the VBT as well as DP_DETECTED to
12245
		 * detect eDP ports.
14133
		 * detect eDP ports.
12246
		 */
14134
		 */
12247
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
14135
		if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
12248
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14136
		    !intel_dp_is_edp(dev, PORT_B))
12249
					PORT_B);
14137
			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
12250
		if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14138
		if (I915_READ(VLV_DP_B) & DP_DETECTED ||
12251
		    intel_dp_is_edp(dev, PORT_B))
14139
		    intel_dp_is_edp(dev, PORT_B))
12252
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14140
			intel_dp_init(dev, VLV_DP_B, PORT_B);
Line 12253... Line 14141...
12253
 
14141
 
12254
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
14142
		if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
12255
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14143
		    !intel_dp_is_edp(dev, PORT_C))
12256
					PORT_C);
14144
			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
12257
		if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14145
		if (I915_READ(VLV_DP_C) & DP_DETECTED ||
12258
		    intel_dp_is_edp(dev, PORT_C))
14146
		    intel_dp_is_edp(dev, PORT_C))
Line 12259... Line 14147...
12259
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14147
			intel_dp_init(dev, VLV_DP_C, PORT_C);
12260
 
-
 
12261
		if (IS_CHERRYVIEW(dev)) {
-
 
12262
			if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
-
 
12263
				intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14148
 
-
 
14149
		if (IS_CHERRYVIEW(dev)) {
-
 
14150
			/* eDP not supported on port D, so don't check VBT */
12264
						PORT_D);
14151
			if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
12265
			/* eDP not supported on port D, so don't check VBT */
14152
				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
12266
				if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14153
			if (I915_READ(CHV_DP_D) & DP_DETECTED)
Line 12267... Line 14154...
12267
					intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14154
				intel_dp_init(dev, CHV_DP_D, PORT_D);
12268
			}
14155
		}
12269
 
14156
 
Line 12270... Line 14157...
12270
		intel_dsi_init(dev);
14157
		intel_dsi_init(dev);
12271
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14158
	} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
12272
		bool found = false;
14159
		bool found = false;
12273
 
14160
 
12274
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14161
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12275
			DRM_DEBUG_KMS("probing SDVOB\n");
14162
			DRM_DEBUG_KMS("probing SDVOB\n");
12276
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14163
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Line 12277... Line 14164...
12277
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14164
			if (!found && IS_G4X(dev)) {
12278
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14165
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12279
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14166
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Line 12280... Line 14167...
12280
			}
14167
			}
Line 12290... Line 14177...
12290
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14177
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12291
		}
14178
		}
Line 12292... Line 14179...
12292
 
14179
 
Line 12293... Line 14180...
12293
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14180
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12294
 
14181
 
12295
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14182
			if (IS_G4X(dev)) {
12296
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14183
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12297
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14184
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12298
			}
14185
			}
12299
			if (SUPPORTS_INTEGRATED_DP(dev))
14186
			if (IS_G4X(dev))
Line 12300... Line 14187...
12300
				intel_dp_init(dev, DP_C, PORT_C);
14187
				intel_dp_init(dev, DP_C, PORT_C);
12301
			}
14188
		}
12302
 
14189
 
12303
		if (SUPPORTS_INTEGRATED_DP(dev) &&
14190
		if (IS_G4X(dev) &&
12304
		    (I915_READ(DP_D) & DP_DETECTED))
14191
		    (I915_READ(DP_D) & DP_DETECTED))
Line 12305... Line -...
12305
			intel_dp_init(dev, DP_D, PORT_D);
-
 
12306
	} else if (IS_GEN2(dev))
14192
			intel_dp_init(dev, DP_D, PORT_D);
Line 12307... Line 14193...
12307
		intel_dvo_init(dev);
14193
	} else if (IS_GEN2(dev))
12308
 
14194
		intel_dvo_init(dev);
12309
 
14195
 
Line 12318... Line 14204...
12318
	intel_init_pch_refclk(dev);
14204
	intel_init_pch_refclk(dev);
Line 12319... Line 14205...
12319
 
14205
 
12320
	drm_helper_move_panel_connectors_to_head(dev);
14206
	drm_helper_move_panel_connectors_to_head(dev);
Line -... Line 14207...
-
 
14207
}
-
 
14208
 
-
 
14209
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
-
 
14210
{
-
 
14211
	struct drm_device *dev = fb->dev;
-
 
14212
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-
 
14213
 
-
 
14214
	drm_framebuffer_cleanup(fb);
-
 
14215
	mutex_lock(&dev->struct_mutex);
-
 
14216
	WARN_ON(!intel_fb->obj->framebuffer_references--);
-
 
14217
	drm_gem_object_unreference(&intel_fb->obj->base);
-
 
14218
	mutex_unlock(&dev->struct_mutex);
-
 
14219
	kfree(intel_fb);
-
 
14220
}
-
 
14221
 
-
 
14222
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
-
 
14223
						struct drm_file *file,
-
 
14224
						unsigned int *handle)
-
 
14225
{
-
 
14226
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-
 
14227
	struct drm_i915_gem_object *obj = intel_fb->obj;
-
 
14228
 
-
 
14229
	if (obj->userptr.mm) {
-
 
14230
		DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
-
 
14231
		return -EINVAL;
-
 
14232
	}
-
 
14233
 
Line -... Line 14234...
-
 
14234
	return drm_gem_handle_create(file, &obj->base, handle);
-
 
14235
}
-
 
14236
 
-
 
14237
static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
-
 
14238
					struct drm_file *file,
-
 
14239
					unsigned flags, unsigned color,
-
 
14240
					struct drm_clip_rect *clips,
-
 
14241
					unsigned num_clips)
-
 
14242
{
-
 
14243
	struct drm_device *dev = fb->dev;
-
 
14244
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-
 
14245
	struct drm_i915_gem_object *obj = intel_fb->obj;
-
 
14246
 
-
 
14247
	mutex_lock(&dev->struct_mutex);
-
 
14248
	intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
-
 
14249
	mutex_unlock(&dev->struct_mutex);
Line 12321... Line 14250...
12321
}
14250
 
12322
 
14251
	return 0;
12323
 
14252
}
-
 
14253
 
12324
 
14254
static const struct drm_framebuffer_funcs intel_fb_funcs = {
Line -... Line 14255...
-
 
14255
	.destroy = intel_user_framebuffer_destroy,
-
 
14256
	.create_handle = intel_user_framebuffer_create_handle,
-
 
14257
	.dirty = intel_user_framebuffer_dirty,
-
 
14258
};
-
 
14259
 
-
 
14260
static
-
 
14261
u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
-
 
14262
			 uint32_t pixel_format)
-
 
14263
{
-
 
14264
	u32 gen = INTEL_INFO(dev)->gen;
-
 
14265
 
-
 
14266
	if (gen >= 9) {
-
 
14267
		/* "The stride in bytes must not exceed the of the size of 8K
-
 
14268
		 *  pixels and 32K bytes."
-
 
14269
		 */
-
 
14270
		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
-
 
14271
	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
-
 
14272
		return 32*1024;
-
 
14273
	} else if (gen >= 4) {
-
 
14274
		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
-
 
14275
			return 16*1024;
-
 
14276
		else
-
 
14277
			return 32*1024;
-
 
14278
	} else if (gen >= 3) {
-
 
14279
		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
-
 
14280
			return 8*1024;
-
 
14281
		else
-
 
14282
			return 16*1024;
-
 
14283
	} else {
12325
static const struct drm_framebuffer_funcs intel_fb_funcs = {
14284
		/* XXX DSPC is limited to 4k tiled */
12326
//	.destroy = intel_user_framebuffer_destroy,
14285
		return 8*1024;
12327
//	.create_handle = intel_user_framebuffer_create_handle,
14286
	}
12328
};
14287
}
12329
 
14288
 
12330
static int intel_framebuffer_init(struct drm_device *dev,
14289
static int intel_framebuffer_init(struct drm_device *dev,
12331
			   struct intel_framebuffer *intel_fb,
-
 
12332
			   struct drm_mode_fb_cmd2 *mode_cmd,
14290
				  struct intel_framebuffer *intel_fb,
-
 
14291
				  struct drm_mode_fb_cmd2 *mode_cmd,
Line 12333... Line 14292...
12333
			   struct drm_i915_gem_object *obj)
14292
				  struct drm_i915_gem_object *obj)
Line -... Line 14293...
-
 
14293
{
-
 
14294
	unsigned int aligned_height;
-
 
14295
	int ret;
12334
{
14296
	u32 pitch_limit, stride_alignment;
-
 
14297
 
12335
	int aligned_height;
14298
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12336
	int pitch_limit;
14299
 
12337
	int ret;
14300
	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
-
 
14301
		/* Enforce that fb modifier and tiling mode match, but only for
-
 
14302
		 * X-tiled. This is needed for FBC. */
-
 
14303
		if (!!(obj->tiling_mode == I915_TILING_X) !=
-
 
14304
		    !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
-
 
14305
			DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
-
 
14306
			return -EINVAL;
-
 
14307
		}
-
 
14308
	} else {
Line -... Line 14309...
-
 
14309
		if (obj->tiling_mode == I915_TILING_X)
12338
 
14310
			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
-
 
14311
		else if (obj->tiling_mode == I915_TILING_Y) {
-
 
14312
			DRM_DEBUG("No Y tiling for legacy addfb\n");
-
 
14313
			return -EINVAL;
-
 
14314
		}
-
 
14315
	}
-
 
14316
 
-
 
14317
	/* Passed in modifier sanity checking. */
-
 
14318
	switch (mode_cmd->modifier[0]) {
-
 
14319
	case I915_FORMAT_MOD_Y_TILED:
-
 
14320
	case I915_FORMAT_MOD_Yf_TILED:
-
 
14321
		if (INTEL_INFO(dev)->gen < 9) {
12339
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14322
			DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12340
 
14323
				  mode_cmd->modifier[0]);
12341
	if (obj->tiling_mode == I915_TILING_Y) {
14324
			return -EINVAL;
12342
		DRM_DEBUG("hardware does not support tiling Y\n");
14325
		}
Line 12343... Line 14326...
12343
		return -EINVAL;
14326
	case DRM_FORMAT_MOD_NONE:
12344
	}
14327
	case I915_FORMAT_MOD_X_TILED:
12345
 
14328
		break;
12346
	if (mode_cmd->pitches[0] & 63) {
-
 
12347
		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
-
 
12348
			  mode_cmd->pitches[0]);
-
 
12349
		return -EINVAL;
-
 
12350
	}
14329
	default:
12351
 
14330
		DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
12352
	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
14331
			  mode_cmd->modifier[0]);
12353
		pitch_limit = 32*1024;
-
 
12354
	} else if (INTEL_INFO(dev)->gen >= 4) {
-
 
12355
		if (obj->tiling_mode)
14332
		return -EINVAL;
12356
			pitch_limit = 16*1024;
-
 
12357
		else
-
 
Line -... Line 14333...
-
 
14333
	}
-
 
14334
 
12358
			pitch_limit = 32*1024;
14335
	stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12359
	} else if (INTEL_INFO(dev)->gen >= 3) {
14336
						     mode_cmd->pixel_format);
-
 
14337
	if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12360
		if (obj->tiling_mode)
14338
		DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12361
			pitch_limit = 8*1024;
14339
			  mode_cmd->pitches[0], stride_alignment);
12362
		else
14340
		return -EINVAL;
12363
			pitch_limit = 16*1024;
14341
	}
Line 12364... Line 14342...
12364
	} else
14342
 
12365
		/* XXX DSPC is limited to 4k tiled */
14343
	pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12366
		pitch_limit = 8*1024;
14344
					   mode_cmd->pixel_format);
12367
 
14345
	if (mode_cmd->pitches[0] > pitch_limit) {
12368
	if (mode_cmd->pitches[0] > pitch_limit) {
14346
		DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12369
		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
14347
			  mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
Line 12385... Line 14363...
12385
	case DRM_FORMAT_RGB565:
14363
	case DRM_FORMAT_RGB565:
12386
	case DRM_FORMAT_XRGB8888:
14364
	case DRM_FORMAT_XRGB8888:
12387
	case DRM_FORMAT_ARGB8888:
14365
	case DRM_FORMAT_ARGB8888:
12388
		break;
14366
		break;
12389
	case DRM_FORMAT_XRGB1555:
14367
	case DRM_FORMAT_XRGB1555:
12390
	case DRM_FORMAT_ARGB1555:
-
 
12391
		if (INTEL_INFO(dev)->gen > 3) {
14368
		if (INTEL_INFO(dev)->gen > 3) {
12392
			DRM_DEBUG("unsupported pixel format: %s\n",
14369
			DRM_DEBUG("unsupported pixel format: %s\n",
12393
				  drm_get_format_name(mode_cmd->pixel_format));
14370
				  drm_get_format_name(mode_cmd->pixel_format));
12394
			return -EINVAL;
14371
			return -EINVAL;
12395
		}
14372
		}
12396
		break;
14373
		break;
12397
	case DRM_FORMAT_XBGR8888:
-
 
12398
	case DRM_FORMAT_ABGR8888:
14374
	case DRM_FORMAT_ABGR8888:
-
 
14375
		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
-
 
14376
			DRM_DEBUG("unsupported pixel format: %s\n",
-
 
14377
				  drm_get_format_name(mode_cmd->pixel_format));
-
 
14378
			return -EINVAL;
-
 
14379
		}
-
 
14380
		break;
-
 
14381
	case DRM_FORMAT_XBGR8888:
12399
	case DRM_FORMAT_XRGB2101010:
14382
	case DRM_FORMAT_XRGB2101010:
12400
	case DRM_FORMAT_ARGB2101010:
-
 
12401
	case DRM_FORMAT_XBGR2101010:
14383
	case DRM_FORMAT_XBGR2101010:
12402
	case DRM_FORMAT_ABGR2101010:
-
 
12403
		if (INTEL_INFO(dev)->gen < 4) {
14384
		if (INTEL_INFO(dev)->gen < 4) {
12404
			DRM_DEBUG("unsupported pixel format: %s\n",
14385
			DRM_DEBUG("unsupported pixel format: %s\n",
12405
				  drm_get_format_name(mode_cmd->pixel_format));
14386
				  drm_get_format_name(mode_cmd->pixel_format));
12406
			return -EINVAL;
14387
			return -EINVAL;
12407
		}
14388
		}
12408
		break;
14389
		break;
-
 
14390
	case DRM_FORMAT_ABGR2101010:
-
 
14391
		if (!IS_VALLEYVIEW(dev)) {
-
 
14392
			DRM_DEBUG("unsupported pixel format: %s\n",
-
 
14393
				  drm_get_format_name(mode_cmd->pixel_format));
-
 
14394
			return -EINVAL;
-
 
14395
		}
-
 
14396
		break;
12409
	case DRM_FORMAT_YUYV:
14397
	case DRM_FORMAT_YUYV:
12410
	case DRM_FORMAT_UYVY:
14398
	case DRM_FORMAT_UYVY:
12411
	case DRM_FORMAT_YVYU:
14399
	case DRM_FORMAT_YVYU:
12412
	case DRM_FORMAT_VYUY:
14400
	case DRM_FORMAT_VYUY:
12413
		if (INTEL_INFO(dev)->gen < 5) {
14401
		if (INTEL_INFO(dev)->gen < 5) {
Line 12424... Line 14412...
12424
 
14412
 
12425
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14413
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12426
	if (mode_cmd->offsets[0] != 0)
14414
	if (mode_cmd->offsets[0] != 0)
Line 12427... Line 14415...
12427
		return -EINVAL;
14415
		return -EINVAL;
-
 
14416
 
12428
 
14417
	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12429
	aligned_height = intel_align_height(dev, mode_cmd->height,
14418
					       mode_cmd->pixel_format,
12430
					    obj->tiling_mode);
14419
					       mode_cmd->modifier[0]);
12431
	/* FIXME drm helper for size checks (especially planar formats)? */
14420
	/* FIXME drm helper for size checks (especially planar formats)? */
Line 12432... Line 14421...
12432
	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14421
	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
Line 12443... Line 14432...
12443
	}
14432
	}
Line 12444... Line 14433...
12444
 
14433
 
12445
	return 0;
14434
	return 0;
Line -... Line 14435...
-
 
14435
}
-
 
14436
 
-
 
14437
static struct drm_framebuffer *
-
 
14438
intel_user_framebuffer_create(struct drm_device *dev,
-
 
14439
			      struct drm_file *filp,
-
 
14440
			      struct drm_mode_fb_cmd2 *user_mode_cmd)
-
 
14441
{
-
 
14442
	struct drm_i915_gem_object *obj;
-
 
14443
	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
-
 
14444
 
-
 
14445
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
-
 
14446
						mode_cmd.handles[0]));
-
 
14447
	if (&obj->base == NULL)
-
 
14448
		return ERR_PTR(-ENOENT);
-
 
14449
 
-
 
14450
	return intel_framebuffer_create(dev, &mode_cmd, obj);
12446
}
14451
}
12447
 
14452
 
12448
#ifndef CONFIG_DRM_I915_FBDEV
14453
#ifndef CONFIG_DRM_FBDEV_EMULATION
12449
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14454
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12450
{
14455
{
Line 12451... Line 14456...
12451
}
14456
}
12452
#endif
14457
#endif
12453
 
14458
 
-
 
14459
static const struct drm_mode_config_funcs intel_mode_funcs = {
-
 
14460
	.fb_create = intel_user_framebuffer_create,
-
 
14461
	.output_poll_changed = intel_fbdev_output_poll_changed,
-
 
14462
	.atomic_check = intel_atomic_check,
12454
static const struct drm_mode_config_funcs intel_mode_funcs = {
14463
	.atomic_commit = intel_atomic_commit,
Line 12455... Line 14464...
12455
	.fb_create = NULL,
14464
	.atomic_state_alloc = intel_atomic_state_alloc,
12456
	.output_poll_changed = intel_fbdev_output_poll_changed,
14465
	.atomic_state_clear = intel_atomic_state_clear,
12457
};
14466
};
Line 12470... Line 14479...
12470
	else if (IS_PINEVIEW(dev))
14479
	else if (IS_PINEVIEW(dev))
12471
		dev_priv->display.find_dpll = pnv_find_best_dpll;
14480
		dev_priv->display.find_dpll = pnv_find_best_dpll;
12472
	else
14481
	else
12473
		dev_priv->display.find_dpll = i9xx_find_best_dpll;
14482
		dev_priv->display.find_dpll = i9xx_find_best_dpll;
Line 12474... Line 14483...
12474
 
14483
 
12475
	if (HAS_DDI(dev)) {
14484
	if (INTEL_INFO(dev)->gen >= 9) {
12476
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14485
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
-
 
14486
		dev_priv->display.get_initial_plane_config =
12477
		dev_priv->display.get_plane_config = ironlake_get_plane_config;
14487
			skylake_get_initial_plane_config;
12478
		dev_priv->display.crtc_compute_clock =
14488
		dev_priv->display.crtc_compute_clock =
12479
			haswell_crtc_compute_clock;
14489
			haswell_crtc_compute_clock;
12480
		dev_priv->display.crtc_enable = haswell_crtc_enable;
14490
		dev_priv->display.crtc_enable = haswell_crtc_enable;
12481
		dev_priv->display.crtc_disable = haswell_crtc_disable;
-
 
12482
		dev_priv->display.off = ironlake_crtc_off;
-
 
12483
		if (INTEL_INFO(dev)->gen >= 9)
14491
		dev_priv->display.crtc_disable = haswell_crtc_disable;
12484
			dev_priv->display.update_primary_plane =
14492
		dev_priv->display.update_primary_plane =
12485
				skylake_update_primary_plane;
14493
			skylake_update_primary_plane;
-
 
14494
	} else if (HAS_DDI(dev)) {
-
 
14495
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
-
 
14496
		dev_priv->display.get_initial_plane_config =
-
 
14497
			ironlake_get_initial_plane_config;
-
 
14498
		dev_priv->display.crtc_compute_clock =
-
 
14499
			haswell_crtc_compute_clock;
-
 
14500
		dev_priv->display.crtc_enable = haswell_crtc_enable;
12486
		else
14501
		dev_priv->display.crtc_disable = haswell_crtc_disable;
12487
		dev_priv->display.update_primary_plane =
14502
		dev_priv->display.update_primary_plane =
12488
			ironlake_update_primary_plane;
14503
			ironlake_update_primary_plane;
12489
	} else if (HAS_PCH_SPLIT(dev)) {
14504
	} else if (HAS_PCH_SPLIT(dev)) {
12490
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14505
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
-
 
14506
		dev_priv->display.get_initial_plane_config =
12491
		dev_priv->display.get_plane_config = ironlake_get_plane_config;
14507
			ironlake_get_initial_plane_config;
12492
		dev_priv->display.crtc_compute_clock =
14508
		dev_priv->display.crtc_compute_clock =
12493
			ironlake_crtc_compute_clock;
14509
			ironlake_crtc_compute_clock;
12494
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
14510
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
12495
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
-
 
12496
		dev_priv->display.off = ironlake_crtc_off;
14511
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
12497
		dev_priv->display.update_primary_plane =
14512
		dev_priv->display.update_primary_plane =
12498
			ironlake_update_primary_plane;
14513
			ironlake_update_primary_plane;
12499
	} else if (IS_VALLEYVIEW(dev)) {
14514
	} else if (IS_VALLEYVIEW(dev)) {
12500
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14515
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-
 
14516
		dev_priv->display.get_initial_plane_config =
12501
		dev_priv->display.get_plane_config = i9xx_get_plane_config;
14517
			i9xx_get_initial_plane_config;
12502
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14518
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12503
		dev_priv->display.crtc_enable = valleyview_crtc_enable;
14519
		dev_priv->display.crtc_enable = valleyview_crtc_enable;
12504
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
-
 
12505
		dev_priv->display.off = i9xx_crtc_off;
14520
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
12506
		dev_priv->display.update_primary_plane =
14521
		dev_priv->display.update_primary_plane =
12507
			i9xx_update_primary_plane;
14522
			i9xx_update_primary_plane;
12508
	} else {
14523
	} else {
12509
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14524
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-
 
14525
		dev_priv->display.get_initial_plane_config =
12510
		dev_priv->display.get_plane_config = i9xx_get_plane_config;
14526
			i9xx_get_initial_plane_config;
12511
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14527
		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12512
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
14528
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
12513
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
-
 
12514
		dev_priv->display.off = i9xx_crtc_off;
14529
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
12515
		dev_priv->display.update_primary_plane =
14530
		dev_priv->display.update_primary_plane =
12516
			i9xx_update_primary_plane;
14531
			i9xx_update_primary_plane;
Line 12517... Line 14532...
12517
	}
14532
	}
-
 
14533
 
-
 
14534
	/* Returns the core display clock speed */
-
 
14535
	if (IS_SKYLAKE(dev))
-
 
14536
		dev_priv->display.get_display_clock_speed =
-
 
14537
			skylake_get_display_clock_speed;
-
 
14538
	else if (IS_BROXTON(dev))
-
 
14539
		dev_priv->display.get_display_clock_speed =
-
 
14540
			broxton_get_display_clock_speed;
-
 
14541
	else if (IS_BROADWELL(dev))
-
 
14542
		dev_priv->display.get_display_clock_speed =
-
 
14543
			broadwell_get_display_clock_speed;
-
 
14544
	else if (IS_HASWELL(dev))
12518
 
14545
		dev_priv->display.get_display_clock_speed =
12519
	/* Returns the core display clock speed */
14546
			haswell_get_display_clock_speed;
12520
	if (IS_VALLEYVIEW(dev))
14547
	else if (IS_VALLEYVIEW(dev))
-
 
14548
		dev_priv->display.get_display_clock_speed =
-
 
14549
			valleyview_get_display_clock_speed;
-
 
14550
	else if (IS_GEN5(dev))
12521
		dev_priv->display.get_display_clock_speed =
14551
		dev_priv->display.get_display_clock_speed =
-
 
14552
			ilk_get_display_clock_speed;
12522
			valleyview_get_display_clock_speed;
14553
	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
12523
	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14554
		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
-
 
14555
		dev_priv->display.get_display_clock_speed =
-
 
14556
			i945_get_display_clock_speed;
-
 
14557
	else if (IS_GM45(dev))
-
 
14558
		dev_priv->display.get_display_clock_speed =
-
 
14559
			gm45_get_display_clock_speed;
-
 
14560
	else if (IS_CRESTLINE(dev))
-
 
14561
		dev_priv->display.get_display_clock_speed =
-
 
14562
			i965gm_get_display_clock_speed;
-
 
14563
	else if (IS_PINEVIEW(dev))
-
 
14564
		dev_priv->display.get_display_clock_speed =
-
 
14565
			pnv_get_display_clock_speed;
-
 
14566
	else if (IS_G33(dev) || IS_G4X(dev))
12524
		dev_priv->display.get_display_clock_speed =
14567
		dev_priv->display.get_display_clock_speed =
12525
			i945_get_display_clock_speed;
14568
			g33_get_display_clock_speed;
12526
	else if (IS_I915G(dev))
14569
	else if (IS_I915G(dev))
12527
		dev_priv->display.get_display_clock_speed =
14570
		dev_priv->display.get_display_clock_speed =
12528
			i915_get_display_clock_speed;
14571
			i915_get_display_clock_speed;
Line 12538... Line 14581...
12538
	else if (IS_I865G(dev))
14581
	else if (IS_I865G(dev))
12539
		dev_priv->display.get_display_clock_speed =
14582
		dev_priv->display.get_display_clock_speed =
12540
			i865_get_display_clock_speed;
14583
			i865_get_display_clock_speed;
12541
	else if (IS_I85X(dev))
14584
	else if (IS_I85X(dev))
12542
		dev_priv->display.get_display_clock_speed =
14585
		dev_priv->display.get_display_clock_speed =
12543
			i855_get_display_clock_speed;
14586
			i85x_get_display_clock_speed;
12544
	else /* 852, 830 */
14587
	else { /* 830 */
-
 
14588
		WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
12545
		dev_priv->display.get_display_clock_speed =
14589
		dev_priv->display.get_display_clock_speed =
12546
			i830_get_display_clock_speed;
14590
			i830_get_display_clock_speed;
-
 
14591
	}
Line 12547... Line 14592...
12547
 
14592
 
12548
		if (IS_GEN5(dev)) {
14593
	if (IS_GEN5(dev)) {
12549
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14594
		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12550
		} else if (IS_GEN6(dev)) {
14595
	} else if (IS_GEN6(dev)) {
12551
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14596
		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12552
		} else if (IS_IVYBRIDGE(dev)) {
14597
	} else if (IS_IVYBRIDGE(dev)) {
12553
			/* FIXME: detect B0+ stepping and use auto training */
14598
		/* FIXME: detect B0+ stepping and use auto training */
12554
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
-
 
12555
			dev_priv->display.modeset_global_resources =
-
 
12556
				ivb_modeset_global_resources;
14599
		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12557
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14600
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-
 
14601
		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
-
 
14602
		if (IS_BROADWELL(dev)) {
-
 
14603
			dev_priv->display.modeset_commit_cdclk =
-
 
14604
				broadwell_modeset_commit_cdclk;
-
 
14605
			dev_priv->display.modeset_calc_cdclk =
-
 
14606
				broadwell_modeset_calc_cdclk;
12558
			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14607
		}
-
 
14608
	} else if (IS_VALLEYVIEW(dev)) {
-
 
14609
		dev_priv->display.modeset_commit_cdclk =
12559
	} else if (IS_VALLEYVIEW(dev)) {
14610
			valleyview_modeset_commit_cdclk;
12560
		dev_priv->display.modeset_global_resources =
14611
		dev_priv->display.modeset_calc_cdclk =
-
 
14612
			valleyview_modeset_calc_cdclk;
-
 
14613
	} else if (IS_BROXTON(dev)) {
-
 
14614
		dev_priv->display.modeset_commit_cdclk =
-
 
14615
			broxton_modeset_commit_cdclk;
-
 
14616
		dev_priv->display.modeset_calc_cdclk =
12561
			valleyview_modeset_global_resources;
14617
			broxton_modeset_calc_cdclk;
Line 12562... Line -...
12562
	}
-
 
12563
 
-
 
Line 12564... Line -...
12564
	/* Default just returns -ENODEV to indicate unsupported */
-
 
Line 12565... Line 14618...
12565
//	dev_priv->display.queue_flip = intel_default_queue_flip;
14618
	}
12566
 
14619
 
Line 12567... Line 14620...
12567
 
14620
 
Line 12656... Line 14709...
12656
		.hook = quirk_invert_brightness,
14709
		.hook = quirk_invert_brightness,
12657
	},
14710
	},
12658
};
14711
};
Line 12659... Line 14712...
12659
 
14712
 
12660
static struct intel_quirk intel_quirks[] = {
-
 
12661
	/* HP Mini needs pipe A force quirk (LP: #322104) */
-
 
12662
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
-
 
12663
 
14713
static struct intel_quirk intel_quirks[] = {
12664
	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14714
	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
Line 12665... Line 14715...
12665
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14715
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12666
 
14716
 
Line 12704... Line 14754...
12704
	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14754
	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
Line 12705... Line 14755...
12705
 
14755
 
12706
	/* Apple Macbook 2,1 (Core 2 T7400) */
14756
	/* Apple Macbook 2,1 (Core 2 T7400) */
Line -... Line 14757...
-
 
14757
	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
-
 
14758
 
-
 
14759
	/* Apple Macbook 4,1 */
12707
	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14760
	{ 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
12708
 
14761
 
Line 12709... Line 14762...
12709
	/* Toshiba CB35 Chromebook (Celeron 2955U) */
14762
	/* Toshiba CB35 Chromebook (Celeron 2955U) */
12710
	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14763
	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
-
 
14764
 
-
 
14765
	/* HP Chromebook 14 (Celeron 2955U) */
-
 
14766
	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
-
 
14767
 
-
 
14768
	/* Dell Chromebook 11 */
-
 
14769
	{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
12711
 
14770
 
Line 12712... Line 14771...
12712
	/* HP Chromebook 14 (Celeron 2955U) */
14771
	/* Dell Chromebook 11 (2015 version) */
12713
	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14772
	{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
12714
};
14773
};
Line 12739... Line 14798...
12739
{
14798
{
12740
	struct drm_i915_private *dev_priv = dev->dev_private;
14799
	struct drm_i915_private *dev_priv = dev->dev_private;
12741
	u8 sr1;
14800
	u8 sr1;
12742
	u32 vga_reg = i915_vgacntrl_reg(dev);
14801
	u32 vga_reg = i915_vgacntrl_reg(dev);
Line -... Line 14802...
-
 
14802
 
12743
 
14803
	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12744
//	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14804
//	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12745
	outb(SR01, VGA_SR_INDEX);
14805
	outb(SR01, VGA_SR_INDEX);
12746
	sr1 = inb(VGA_SR_DATA);
14806
	sr1 = inb(VGA_SR_DATA);
12747
	outb(sr1 | 1<<5, VGA_SR_DATA);
14807
	outb(sr1 | 1<<5, VGA_SR_DATA);
12748
//	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14808
//	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
Line 12749... Line -...
12749
	udelay(300);
-
 
12750
 
-
 
12751
	/*
-
 
12752
	 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
-
 
12753
	 * from S3 without preserving (some of?) the other bits.
14809
	udelay(300);
12754
	 */
14810
 
12755
	I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
14811
	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
Line 12756... Line 14812...
12756
	POSTING_READ(vga_reg);
14812
	POSTING_READ(vga_reg);
12757
}
14813
}
-
 
14814
 
12758
 
14815
void intel_modeset_init_hw(struct drm_device *dev)
12759
void intel_modeset_init_hw(struct drm_device *dev)
-
 
12760
{
-
 
12761
	intel_prepare_ddi(dev);
-
 
12762
 
-
 
12763
	if (IS_VALLEYVIEW(dev))
14816
{
12764
		vlv_update_cdclk(dev);
-
 
12765
 
14817
	intel_update_cdclk(dev);
12766
	intel_init_clock_gating(dev);
14818
	intel_prepare_ddi(dev);
Line 12767... Line 14819...
12767
 
14819
	intel_init_clock_gating(dev);
12768
    intel_enable_gt_powersave(dev);
14820
	intel_enable_gt_powersave(dev);
12769
}
14821
}
12770
 
14822
 
12771
void intel_modeset_init(struct drm_device *dev)
14823
void intel_modeset_init(struct drm_device *dev)
12772
{
14824
{
12773
	struct drm_i915_private *dev_priv = dev->dev_private;
14825
	struct drm_i915_private *dev_priv = dev->dev_private;
12774
	int sprite, ret;
14826
	int sprite, ret;
Line 12775... Line 14827...
12775
	enum pipe pipe;
14827
	enum pipe pipe;
12776
	struct intel_crtc *crtc;
14828
	struct intel_crtc *crtc;
Line 12777... Line 14829...
12777
 
14829
ENTER();
12778
	drm_mode_config_init(dev);
14830
	drm_mode_config_init(dev);
Line -... Line 14831...
-
 
14831
 
-
 
14832
	dev->mode_config.min_width = 0;
12779
 
14833
	dev->mode_config.min_height = 0;
Line 12780... Line 14834...
12780
	dev->mode_config.min_width = 0;
14834
 
Line 12781... Line 14835...
12781
	dev->mode_config.min_height = 0;
14835
	dev->mode_config.preferred_depth = 24;
Line 12782... Line 14836...
12782
 
14836
	dev->mode_config.prefer_shadow = 1;
12783
	dev->mode_config.preferred_depth = 24;
14837
 
Line -... Line 14838...
-
 
14838
	dev->mode_config.allow_fb_modifiers = true;
-
 
14839
 
-
 
14840
	dev->mode_config.funcs = &intel_mode_funcs;
-
 
14841
 
-
 
14842
	intel_init_quirks(dev);
-
 
14843
 
-
 
14844
	intel_init_pm(dev);
-
 
14845
 
-
 
14846
	if (INTEL_INFO(dev)->num_pipes == 0)
-
 
14847
		return;
-
 
14848
 
-
 
14849
	/*
-
 
14850
	 * There may be no VBT; and if the BIOS enabled SSC we can
-
 
14851
	 * just keep using it to avoid unnecessary flicker.  Whereas if the
-
 
14852
	 * BIOS isn't using it, don't assume it will work even if the VBT
-
 
14853
	 * indicates as much.
-
 
14854
	 */
-
 
14855
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
12784
	dev->mode_config.prefer_shadow = 1;
14856
		bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
Line 12785... Line 14857...
12785
 
14857
					    DREF_SSC1_ENABLE);
12786
	dev->mode_config.funcs = &intel_mode_funcs;
14858
 
12787
 
14859
		if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
Line 12819... Line 14891...
12819
		      INTEL_INFO(dev)->num_pipes,
14891
		      INTEL_INFO(dev)->num_pipes,
12820
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14892
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Line 12821... Line 14893...
12821
 
14893
 
12822
	for_each_pipe(dev_priv, pipe) {
14894
	for_each_pipe(dev_priv, pipe) {
12823
		intel_crtc_init(dev, pipe);
14895
		intel_crtc_init(dev, pipe);
12824
		for_each_sprite(pipe, sprite) {
14896
		for_each_sprite(dev_priv, pipe, sprite) {
12825
			ret = intel_plane_init(dev, pipe, sprite);
14897
			ret = intel_plane_init(dev, pipe, sprite);
12826
		if (ret)
14898
			if (ret)
12827
				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14899
				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12828
					      pipe_name(pipe), sprite_name(pipe, sprite), ret);
14900
					      pipe_name(pipe), sprite_name(pipe, sprite), ret);
12829
		}
14901
		}
Line -... Line 14902...
-
 
14902
	}
12830
	}
14903
 
Line 12831... Line 14904...
12831
 
14904
	intel_update_czclk(dev_priv);
Line 12832... Line -...
12832
	intel_init_dpio(dev);
-
 
12833
 
-
 
12834
	intel_shared_dpll_init(dev);
14905
	intel_update_cdclk(dev);
12835
 
14906
 
12836
	/* save the BIOS value before clobbering it */
14907
	intel_shared_dpll_init(dev);
Line 12837... Line 14908...
12837
	dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
14908
 
12838
	/* Just disable it once at startup */
14909
	/* Just disable it once at startup */
Line 12839... Line 14910...
12839
	i915_disable_vga(dev);
14910
	i915_disable_vga(dev);
12840
	intel_setup_outputs(dev);
14911
	intel_setup_outputs(dev);
12841
 
14912
 
Line 12842... Line 14913...
12842
	/* Just in case the BIOS is doing something questionable. */
14913
	/* Just in case the BIOS is doing something questionable. */
-
 
14914
	intel_fbc_disable(dev_priv);
-
 
14915
 
12843
	intel_disable_fbc(dev);
14916
	drm_modeset_lock_all(dev);
12844
 
14917
	intel_modeset_setup_hw_state(dev);
Line 12845... Line 14918...
12845
	drm_modeset_lock_all(dev);
14918
	drm_modeset_unlock_all(dev);
12846
	intel_modeset_setup_hw_state(dev, false);
14919
 
12847
	drm_modeset_unlock_all(dev);
14920
	for_each_intel_crtc(dev, crtc) {
12848
 
14921
		struct intel_initial_plane_config plane_config = {};
12849
	for_each_intel_crtc(dev, crtc) {
14922
 
12850
		if (!crtc->active)
14923
		if (!crtc->active)
12851
			continue;
14924
			continue;
12852
 
-
 
12853
		/*
14925
 
12854
		 * Note that reserving the BIOS fb up front prevents us
14926
		/*
-
 
14927
		 * Note that reserving the BIOS fb up front prevents us
12855
		 * from stuffing other stolen allocations like the ring
14928
		 * from stuffing other stolen allocations like the ring
12856
		 * on top.  This prevents some ugliness at boot time, and
14929
		 * on top.  This prevents some ugliness at boot time, and
12857
		 * can even allow for smooth boot transitions if the BIOS
14930
		 * can even allow for smooth boot transitions if the BIOS
12858
		 * fb is large enough for the active pipe configuration.
14931
		 * fb is large enough for the active pipe configuration.
12859
		 */
14932
		 */
-
 
14933
		dev_priv->display.get_initial_plane_config(crtc,
-
 
14934
							   &plane_config);
-
 
14935
 
-
 
14936
		/*
-
 
14937
		 * If the fb is shared between multiple heads, we'll
12860
		if (dev_priv->display.get_plane_config) {
14938
		 * just get the first one.
-
 
14939
		 */
-
 
14940
		intel_find_initial_plane_obj(crtc, &plane_config);
12861
			dev_priv->display.get_plane_config(crtc,
14941
		if(!main_fb_obj)
-
 
14942
		{
12862
							   &crtc->plane_config);
14943
			struct drm_framebuffer *fb;
-
 
14944
 
-
 
14945
			fb = crtc->base.primary->fb;
-
 
14946
			main_fb_obj = intel_fb_obj(fb);
12863
			/*
14947
			main_fb_obj->map_and_fenceable=true;
Line 12864... Line 14948...
12864
			 * If the fb is shared between multiple heads, we'll
14948
			DRM_DEBUG_KMS("main_fb_obj %p gtt_offset 0x%08lx\n", main_fb_obj, i915_gem_obj_ggtt_offset(main_fb_obj));
12865
			 * just get the first one.
14949
		}
12866
			 */
14950
 
Line 12878... Line 14962...
12878
	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14962
	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Line 12879... Line 14963...
12879
 
14963
 
12880
	/* We can't just switch on the pipe A, we need to set things up with a
14964
	/* We can't just switch on the pipe A, we need to set things up with a
12881
	 * proper mode and output configuration. As a gross hack, enable pipe A
14965
	 * proper mode and output configuration. As a gross hack, enable pipe A
12882
	 * by enabling the load detect pipe once. */
14966
	 * by enabling the load detect pipe once. */
12883
	list_for_each_entry(connector,
-
 
12884
			    &dev->mode_config.connector_list,
-
 
12885
			    base.head) {
14967
	for_each_intel_connector(dev, connector) {
12886
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14968
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12887
			crt = &connector->base;
14969
			crt = &connector->base;
12888
			break;
14970
			break;
12889
		}
14971
		}
Line 12890... Line 14972...
12890
	}
14972
	}
12891
 
14973
 
Line 12892... Line 14974...
12892
	if (!crt)
14974
	if (!crt)
12893
		return;
14975
		return;
12894
 
14976
 
Line 12895... Line 14977...
12895
	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14977
	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12896
		intel_release_load_detect_pipe(crt, &load_detect_temp);
14978
		intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
12897
}
14979
}
12898
 
14980
 
12899
static bool
14981
static bool
12900
intel_check_plane_mapping(struct intel_crtc *crtc)
14982
intel_check_plane_mapping(struct intel_crtc *crtc)
Line 12901... Line 14983...
12901
{
14983
{
12902
	struct drm_device *dev = crtc->base.dev;
14984
	struct drm_device *dev = crtc->base.dev;
Line 12903... Line 14985...
12903
	struct drm_i915_private *dev_priv = dev->dev_private;
14985
	struct drm_i915_private *dev_priv = dev->dev_private;
12904
	u32 reg, val;
-
 
Line 12905... Line 14986...
12905
 
14986
	u32 val;
12906
	if (INTEL_INFO(dev)->num_pipes == 1)
14987
 
12907
		return true;
14988
	if (INTEL_INFO(dev)->num_pipes == 1)
Line 12908... Line 14989...
12908
 
14989
		return true;
12909
	reg = DSPCNTR(!crtc->plane);
14990
 
Line -... Line 14991...
-
 
14991
	val = I915_READ(DSPCNTR(!crtc->plane));
-
 
14992
 
-
 
14993
	if ((val & DISPLAY_PLANE_ENABLE) &&
-
 
14994
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
-
 
14995
		return false;
-
 
14996
 
-
 
14997
	return true;
-
 
14998
}
-
 
14999
 
-
 
15000
static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
-
 
15001
{
12910
	val = I915_READ(reg);
15002
	struct drm_device *dev = crtc->base.dev;
12911
 
15003
	struct intel_encoder *encoder;
12912
	if ((val & DISPLAY_PLANE_ENABLE) &&
15004
 
12913
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15005
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12914
		return false;
15006
		return true;
Line 12915... Line 15007...
12915
 
15007
 
12916
	return true;
15008
	return false;
12917
}
15009
}
Line 12918... Line 15010...
12918
 
15010
 
-
 
15011
static void intel_sanitize_crtc(struct intel_crtc *crtc)
12919
static void intel_sanitize_crtc(struct intel_crtc *crtc)
15012
{
12920
{
15013
	struct drm_device *dev = crtc->base.dev;
-
 
15014
	struct drm_i915_private *dev_priv = dev->dev_private;
12921
	struct drm_device *dev = crtc->base.dev;
15015
	u32 reg;
-
 
15016
 
-
 
15017
	/* Clear any frame start delays used for debugging left by the BIOS */
-
 
15018
	reg = PIPECONF(crtc->config->cpu_transcoder);
-
 
15019
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12922
	struct drm_i915_private *dev_priv = dev->dev_private;
15020
 
-
 
15021
	/* restore vblank interrupts to correct state */
12923
	u32 reg;
15022
	drm_crtc_vblank_reset(&crtc->base);
-
 
15023
	if (crtc->active) {
-
 
15024
		struct intel_plane *plane;
Line 12924... Line 15025...
12924
 
15025
 
12925
	/* Clear any frame start delays used for debugging left by the BIOS */
15026
		drm_crtc_vblank_on(&crtc->base);
12926
	reg = PIPECONF(crtc->config.cpu_transcoder);
15027
 
12927
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15028
		/* Disable everything but the primary plane */
12928
 
-
 
12929
	/* restore vblank interrupts to correct state */
15029
		for_each_intel_plane_on_crtc(dev, crtc, plane) {
Line 12930... Line 15030...
12930
	if (crtc->active) {
15030
			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
12931
		update_scanline_offset(crtc);
15031
				continue;
Line 12932... Line 15032...
12932
		drm_vblank_on(dev, crtc->pipe);
15032
 
12933
	} else
15033
			plane->disable_plane(&plane->base, &crtc->base);
12934
		drm_vblank_off(dev, crtc->pipe);
15034
		}
12935
 
15035
	}
-
 
15036
 
12936
	/* We need to sanitize the plane -> pipe mapping first because this will
15037
	/* We need to sanitize the plane -> pipe mapping first because this will
12937
	 * disable the crtc (and hence change the state) if it is wrong. Note
-
 
12938
	 * that gen4+ has a fixed plane -> pipe mapping.  */
15038
	 * disable the crtc (and hence change the state) if it is wrong. Note
12939
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15039
	 * that gen4+ has a fixed plane -> pipe mapping.  */
12940
		struct intel_connector *connector;
-
 
12941
		bool plane;
-
 
12942
 
-
 
12943
		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
-
 
12944
			      crtc->base.base.id);
-
 
12945
 
-
 
12946
		/* Pipe has the wrong plane attached and the plane is active.
-
 
12947
		 * Temporarily change the plane mapping and disable everything
-
 
12948
		 * ...  */
-
 
12949
		plane = crtc->plane;
-
 
12950
		crtc->plane = !plane;
-
 
12951
		crtc->primary_enabled = true;
-
 
12952
		dev_priv->display.crtc_disable(&crtc->base);
-
 
12953
		crtc->plane = plane;
-
 
12954
 
-
 
12955
		/* ... and break all links. */
-
 
12956
		list_for_each_entry(connector, &dev->mode_config.connector_list,
-
 
12957
				    base.head) {
-
 
12958
			if (connector->encoder->base.crtc != &crtc->base)
-
 
12959
				continue;
-
 
12960
 
-
 
12961
			connector->base.dpms = DRM_MODE_DPMS_OFF;
15040
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Line 12962... Line 15041...
12962
			connector->base.encoder = NULL;
15041
		bool plane;
12963
		}
15042
 
12964
		/* multiple connectors may have the same encoder:
15043
		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
Line 12983... Line 15062...
12983
		intel_enable_pipe_a(dev);
15062
		intel_enable_pipe_a(dev);
12984
	}
15063
	}
Line 12985... Line 15064...
12985
 
15064
 
12986
	/* Adjust the state of the output pipe according to whether we
15065
	/* Adjust the state of the output pipe according to whether we
-
 
15066
	 * have active connectors/encoders. */
12987
	 * have active connectors/encoders. */
15067
	if (!intel_crtc_has_encoders(crtc))
Line 12988... Line 15068...
12988
	intel_crtc_update_dpms(&crtc->base);
15068
		intel_crtc_disable_noatomic(&crtc->base);
12989
 
15069
 
Line 12990... Line 15070...
12990
	if (crtc->active != crtc->base.enabled) {
15070
	if (crtc->active != crtc->base.state->active) {
-
 
15071
		struct intel_encoder *encoder;
12991
		struct intel_encoder *encoder;
15072
 
12992
 
15073
		/* This can happen either due to bugs in the get_hw_state
12993
		/* This can happen either due to bugs in the get_hw_state
15074
		 * functions or because of calls to intel_crtc_disable_noatomic,
12994
		 * functions or because the pipe is force-enabled due to the
15075
		 * or because the pipe is force-enabled due to the
12995
		 * pipe A quirk. */
15076
		 * pipe A quirk. */
12996
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15077
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
Line -... Line 15078...
-
 
15078
			      crtc->base.base.id,
-
 
15079
			      crtc->base.state->enable ? "enabled" : "disabled",
12997
			      crtc->base.base.id,
15080
			      crtc->active ? "enabled" : "disabled");
Line 12998... Line 15081...
12998
			      crtc->base.enabled ? "enabled" : "disabled",
15081
 
12999
			      crtc->active ? "enabled" : "disabled");
15082
		WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
13000
 
15083
		crtc->base.state->active = crtc->active;
13001
		crtc->base.enabled = crtc->active;
15084
		crtc->base.enabled = crtc->active;
13002
 
15085
 
13003
		/* Because we only establish the connector -> encoder ->
15086
		/* Because we only establish the connector -> encoder ->
Line 13004... Line 15087...
13004
		 * crtc links if something is active, this means the
15087
		 * crtc links if something is active, this means the
13005
		 * crtc is now deactivated. Break the links. connector
-
 
13006
		 * -> encoder links are only establish when things are
15088
		 * crtc is now deactivated. Break the links. connector
13007
		 *  actually up, hence no need to break them. */
15089
		 * -> encoder links are only establish when things are
13008
		WARN_ON(crtc->active);
-
 
Line 13009... Line 15090...
13009
 
15090
		 *  actually up, hence no need to break them. */
13010
		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15091
		WARN_ON(crtc->active);
13011
			WARN_ON(encoder->connectors_active);
15092
 
13012
			encoder->base.crtc = NULL;
15093
		for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Line 13034... Line 15115...
13034
 
15115
 
13035
static void intel_sanitize_encoder(struct intel_encoder *encoder)
15116
static void intel_sanitize_encoder(struct intel_encoder *encoder)
13036
{
15117
{
13037
	struct intel_connector *connector;
15118
	struct intel_connector *connector;
-
 
15119
	struct drm_device *dev = encoder->base.dev;
Line 13038... Line 15120...
13038
	struct drm_device *dev = encoder->base.dev;
15120
	bool active = false;
13039
 
15121
 
13040
	/* We need to check both for a crtc link (meaning that the
15122
	/* We need to check both for a crtc link (meaning that the
13041
	 * encoder is active and trying to read from a pipe) and the
15123
	 * encoder is active and trying to read from a pipe) and the
13042
	 * pipe itself being active. */
15124
	 * pipe itself being active. */
Line -... Line 15125...
-
 
15125
	bool has_active_crtc = encoder->base.crtc &&
-
 
15126
		to_intel_crtc(encoder->base.crtc)->active;
-
 
15127
 
-
 
15128
	for_each_intel_connector(dev, connector) {
-
 
15129
		if (connector->base.encoder != &encoder->base)
-
 
15130
			continue;
-
 
15131
 
-
 
15132
		active = true;
13043
	bool has_active_crtc = encoder->base.crtc &&
15133
		break;
13044
		to_intel_crtc(encoder->base.crtc)->active;
15134
	}
13045
 
15135
 
13046
	if (encoder->connectors_active && !has_active_crtc) {
15136
	if (active && !has_active_crtc) {
Line 13047... Line 15137...
13047
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15137
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
Line 13058... Line 15148...
13058
			encoder->disable(encoder);
15148
			encoder->disable(encoder);
13059
			if (encoder->post_disable)
15149
			if (encoder->post_disable)
13060
				encoder->post_disable(encoder);
15150
				encoder->post_disable(encoder);
13061
		}
15151
		}
13062
		encoder->base.crtc = NULL;
15152
		encoder->base.crtc = NULL;
13063
		encoder->connectors_active = false;
-
 
Line 13064... Line 15153...
13064
 
15153
 
13065
		/* Inconsistent output/port/pipe state happens presumably due to
15154
		/* Inconsistent output/port/pipe state happens presumably due to
13066
		 * a bug in one of the get_hw_state functions. Or someplace else
15155
		 * a bug in one of the get_hw_state functions. Or someplace else
13067
		 * in our code, like the register restore mess on resume. Clamp
15156
		 * in our code, like the register restore mess on resume. Clamp
13068
		 * things to off as a safer default. */
15157
		 * things to off as a safer default. */
13069
		list_for_each_entry(connector,
-
 
13070
				    &dev->mode_config.connector_list,
-
 
13071
				    base.head) {
15158
		for_each_intel_connector(dev, connector) {
13072
			if (connector->encoder != encoder)
15159
			if (connector->encoder != encoder)
13073
				continue;
15160
				continue;
13074
			connector->base.dpms = DRM_MODE_DPMS_OFF;
15161
			connector->base.dpms = DRM_MODE_DPMS_OFF;
13075
			connector->base.encoder = NULL;
15162
			connector->base.encoder = NULL;
Line 13105... Line 15192...
13105
		return;
15192
		return;
Line 13106... Line 15193...
13106
 
15193
 
13107
	i915_redisable_vga_power_on(dev);
15194
	i915_redisable_vga_power_on(dev);
Line 13108... Line 15195...
13108
}
15195
}
13109
 
15196
 
13110
static bool primary_get_hw_state(struct intel_crtc *crtc)
15197
static bool primary_get_hw_state(struct intel_plane *plane)
Line -... Line 15198...
-
 
15198
{
-
 
15199
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
 
15200
 
-
 
15201
	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
-
 
15202
}
-
 
15203
 
-
 
15204
/* FIXME read out full plane state for all planes */
-
 
15205
static void readout_plane_state(struct intel_crtc *crtc)
13111
{
15206
{
-
 
15207
	struct drm_plane *primary = crtc->base.primary;
13112
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15208
	struct intel_plane_state *plane_state =
-
 
15209
		to_intel_plane_state(primary->state);
Line -... Line 15210...
-
 
15210
 
13113
 
15211
	plane_state->visible =
13114
	if (!crtc->active)
15212
		primary_get_hw_state(to_intel_plane(primary));
Line 13115... Line 15213...
13115
		return false;
15213
 
13116
 
15214
	if (plane_state->visible)
13117
	return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15215
		crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
Line 13125... Line 15223...
13125
	struct intel_encoder *encoder;
15223
	struct intel_encoder *encoder;
13126
	struct intel_connector *connector;
15224
	struct intel_connector *connector;
13127
	int i;
15225
	int i;
Line 13128... Line 15226...
13128
 
15226
 
-
 
15227
	for_each_intel_crtc(dev, crtc) {
13129
	for_each_intel_crtc(dev, crtc) {
15228
		__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
13130
		memset(&crtc->config, 0, sizeof(crtc->config));
-
 
13131
 
15229
		memset(crtc->config, 0, sizeof(*crtc->config));
Line 13132... Line 15230...
13132
		crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15230
		crtc->config->base.crtc = &crtc->base;
13133
 
15231
 
Line -... Line 15232...
-
 
15232
		crtc->active = dev_priv->display.get_pipe_config(crtc,
13134
		crtc->active = dev_priv->display.get_pipe_config(crtc,
15233
								 crtc->config);
-
 
15234
 
13135
								 &crtc->config);
15235
		crtc->base.state->active = crtc->active;
Line 13136... Line 15236...
13136
 
15236
		crtc->base.enabled = crtc->active;
13137
		crtc->base.enabled = crtc->active;
15237
 
13138
		crtc->primary_enabled = primary_get_hw_state(crtc);
15238
		readout_plane_state(crtc);
13139
 
15239
 
Line 13167... Line 15267...
13167
		pipe = 0;
15267
		pipe = 0;
Line 13168... Line 15268...
13168
 
15268
 
13169
		if (encoder->get_hw_state(encoder, &pipe)) {
15269
		if (encoder->get_hw_state(encoder, &pipe)) {
13170
			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15270
			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13171
			encoder->base.crtc = &crtc->base;
15271
			encoder->base.crtc = &crtc->base;
13172
				encoder->get_config(encoder, &crtc->config);
15272
			encoder->get_config(encoder, crtc->config);
13173
		} else {
15273
		} else {
13174
			encoder->base.crtc = NULL;
15274
			encoder->base.crtc = NULL;
Line 13175... Line -...
13175
		}
-
 
13176
 
15275
		}
13177
		encoder->connectors_active = false;
15276
 
13178
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15277
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13179
			      encoder->base.base.id,
15278
			      encoder->base.base.id,
13180
			      encoder->base.name,
15279
			      encoder->base.name,
13181
			      encoder->base.crtc ? "enabled" : "disabled",
15280
			      encoder->base.crtc ? "enabled" : "disabled",
Line 13182... Line 15281...
13182
			      pipe_name(pipe));
15281
			      pipe_name(pipe));
13183
	}
-
 
13184
 
15282
	}
13185
	list_for_each_entry(connector, &dev->mode_config.connector_list,
15283
 
13186
			    base.head) {
-
 
13187
		if (connector->get_hw_state(connector)) {
15284
	for_each_intel_connector(dev, connector) {
13188
			connector->base.dpms = DRM_MODE_DPMS_ON;
15285
		if (connector->get_hw_state(connector)) {
13189
			connector->encoder->connectors_active = true;
15286
			connector->base.dpms = DRM_MODE_DPMS_ON;
13190
			connector->base.encoder = &connector->encoder->base;
15287
			connector->base.encoder = &connector->encoder->base;
13191
		} else {
15288
		} else {
13192
			connector->base.dpms = DRM_MODE_DPMS_OFF;
15289
			connector->base.dpms = DRM_MODE_DPMS_OFF;
13193
			connector->base.encoder = NULL;
15290
			connector->base.encoder = NULL;
13194
		}
15291
		}
13195
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15292
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13196
			      connector->base.base.id,
15293
			      connector->base.base.id,
-
 
15294
			      connector->base.name,
-
 
15295
			      connector->base.encoder ? "enabled" : "disabled");
-
 
15296
	}
-
 
15297
 
-
 
15298
	for_each_intel_crtc(dev, crtc) {
-
 
15299
		crtc->base.hwmode = crtc->config->base.adjusted_mode;
-
 
15300
 
-
 
15301
		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
-
 
15302
		if (crtc->base.state->active) {
-
 
15303
			intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
-
 
15304
			intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
-
 
15305
			WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
-
 
15306
 
-
 
15307
			/*
-
 
15308
			 * The initial mode needs to be set in order to keep
-
 
15309
			 * the atomic core happy. It wants a valid mode if the
-
 
15310
			 * crtc's enabled, so we do the above call.
-
 
15311
			 *
-
 
15312
			 * At this point some state updated by the connectors
-
 
15313
			 * in their ->detect() callback has not run yet, so
-
 
15314
			 * no recalculation can be done yet.
-
 
15315
			 *
-
 
15316
			 * Even if we could do a recalculation and modeset
-
 
15317
			 * right now it would cause a double modeset if
-
 
15318
			 * fbdev or userspace chooses a different initial mode.
-
 
15319
			 *
-
 
15320
			 * If that happens, someone indicated they wanted a
-
 
15321
			 * mode change, which means it's safe to do a full
-
 
15322
			 * recalculation.
-
 
15323
			 */
-
 
15324
			crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
-
 
15325
 
-
 
15326
			drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
13197
			      connector->base.name,
15327
			update_scanline_offset(crtc);
Line 13198... Line 15328...
13198
			      connector->base.encoder ? "enabled" : "disabled");
15328
		}
13199
	}
15329
	}
-
 
15330
}
-
 
15331
 
13200
}
15332
/* Scan out the current hw modeset state,
13201
 
-
 
13202
/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15333
 * and sanitizes it to the current state
13203
 * and i915 state tracking structures. */
15334
 */
13204
void intel_modeset_setup_hw_state(struct drm_device *dev,
15335
static void
13205
				  bool force_restore)
15336
intel_modeset_setup_hw_state(struct drm_device *dev)
13206
{
15337
{
13207
	struct drm_i915_private *dev_priv = dev->dev_private;
15338
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 13208... Line 15339...
13208
	enum pipe pipe;
15339
	enum pipe pipe;
Line 13209... Line -...
13209
	struct intel_crtc *crtc;
-
 
13210
	struct intel_encoder *encoder;
-
 
13211
	int i;
-
 
13212
 
-
 
13213
	intel_modeset_readout_hw_state(dev);
-
 
13214
 
-
 
13215
	/*
-
 
13216
	 * Now that we have the config, copy it to each CRTC struct
-
 
13217
	 * Note that this could go away if we move to using crtc_config
-
 
13218
	 * checking everywhere.
-
 
13219
	 */
-
 
13220
	for_each_intel_crtc(dev, crtc) {
-
 
13221
		if (crtc->active && i915.fastboot) {
-
 
13222
			intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
-
 
13223
			DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15340
	struct intel_crtc *crtc;
13224
				      crtc->base.base.id);
15341
	struct intel_encoder *encoder;
13225
			drm_mode_debug_printmodeline(&crtc->base.mode);
15342
	int i;
13226
		}
15343
 
Line 13227... Line 15344...
13227
	}
15344
	intel_modeset_readout_hw_state(dev);
13228
 
15345
 
13229
	/* HW state is read out, now we need to sanitize this mess. */
15346
	/* HW state is read out, now we need to sanitize this mess. */
13230
	for_each_intel_encoder(dev, encoder) {
15347
	for_each_intel_encoder(dev, encoder) {
-
 
15348
		intel_sanitize_encoder(encoder);
13231
		intel_sanitize_encoder(encoder);
15349
	}
Line -... Line 15350...
-
 
15350
 
-
 
15351
	for_each_pipe(dev_priv, pipe) {
13232
	}
15352
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13233
 
15353
		intel_sanitize_crtc(crtc);
Line 13234... Line 15354...
13234
	for_each_pipe(dev_priv, pipe) {
15354
		intel_dump_pipe_config(crtc, crtc->config,
13235
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15355
				       "[setup_hw_state]");
Line 13247... Line 15367...
13247
 
15367
 
13248
		pll->disable(dev_priv, pll);
15368
		pll->disable(dev_priv, pll);
13249
		pll->on = false;
15369
		pll->on = false;
Line -... Line 15370...
-
 
15370
	}
-
 
15371
 
13250
	}
15372
	if (IS_VALLEYVIEW(dev))
13251
 
15373
		vlv_wm_get_hw_state(dev);
13252
	if (IS_GEN9(dev))
15374
	else if (IS_GEN9(dev))
13253
		skl_wm_get_hw_state(dev);
15375
		skl_wm_get_hw_state(dev);
Line 13254... Line 15376...
13254
	else if (HAS_PCH_SPLIT(dev))
15376
	else if (HAS_PCH_SPLIT(dev))
13255
		ilk_wm_get_hw_state(dev);
15377
		ilk_wm_get_hw_state(dev);
Line -... Line 15378...
-
 
15378
 
-
 
15379
	for_each_intel_crtc(dev, crtc) {
-
 
15380
		unsigned long put_domains;
13256
 
15381
 
-
 
15382
		put_domains = modeset_get_crtc_power_domains(&crtc->base);
-
 
15383
		if (WARN_ON(put_domains))
-
 
15384
			modeset_put_power_domains(dev_priv, put_domains);
-
 
15385
	}
-
 
15386
	intel_display_set_init_power(dev_priv, false);
13257
	if (force_restore) {
15387
}
-
 
15388
 
13258
		i915_redisable_vga(dev);
15389
void intel_display_resume(struct drm_device *dev)
-
 
15390
{
-
 
15391
	struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
-
 
15392
	struct intel_connector *conn;
-
 
15393
	struct intel_plane *plane;
13259
 
15394
	struct drm_crtc *crtc;
-
 
15395
	int ret;
-
 
15396
 
-
 
15397
	if (!state)
-
 
15398
		return;
-
 
15399
 
-
 
15400
	state->acquire_ctx = dev->mode_config.acquire_ctx;
13260
		/*
15401
 
13261
		 * We need to use raw interfaces for restoring state to avoid
15402
	/* preserve complete old state, including dpll */
13262
		 * checking (bogus) intermediate states.
15403
	intel_atomic_get_shared_dpll_state(state);
-
 
15404
 
-
 
15405
	for_each_crtc(dev, crtc) {
-
 
15406
		struct drm_crtc_state *crtc_state =
-
 
15407
			drm_atomic_get_crtc_state(state, crtc);
Line 13263... Line 15408...
13263
		 */
15408
 
13264
		for_each_pipe(dev_priv, pipe) {
15409
		ret = PTR_ERR_OR_ZERO(crtc_state);
13265
			struct drm_crtc *crtc =
15410
		if (ret)
-
 
15411
			goto err;
-
 
15412
 
-
 
15413
		/* force a restore */
13266
				dev_priv->pipe_to_crtc_mapping[pipe];
15414
		crtc_state->mode_changed = true;
13267
 
15415
	}
13268
			intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
15416
 
Line -... Line 15417...
-
 
15417
	for_each_intel_plane(dev, plane) {
-
 
15418
		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
-
 
15419
		if (ret)
-
 
15420
			goto err;
-
 
15421
	}
-
 
15422
 
13269
					 crtc->primary->fb);
15423
	for_each_intel_connector(dev, conn) {
-
 
15424
		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
-
 
15425
		if (ret)
-
 
15426
			goto err;
-
 
15427
	}
-
 
15428
 
-
 
15429
	intel_modeset_setup_hw_state(dev);
-
 
15430
 
-
 
15431
	i915_redisable_vga(dev);
-
 
15432
	ret = drm_atomic_commit(state);
13270
		}
15433
	if (!ret)
Line 13271... Line 15434...
13271
	} else {
15434
		return;
13272
	intel_modeset_update_staged_output_state(dev);
15435
 
13273
	}
-
 
13274
 
15436
err:
13275
	intel_modeset_check_state(dev);
15437
	DRM_ERROR("Restoring old state failed with %i\n", ret);
-
 
15438
	drm_atomic_state_free(state);
Line 13276... Line 15439...
13276
}
15439
}
13277
 
15440
 
13278
void intel_modeset_gem_init(struct drm_device *dev)
15441
void intel_modeset_gem_init(struct drm_device *dev)
Line 13279... Line -...
13279
{
-
 
13280
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
13281
	struct drm_crtc *c;
-
 
13282
	struct drm_i915_gem_object *obj;
-
 
13283
 
-
 
13284
	mutex_lock(&dev->struct_mutex);
-
 
13285
	intel_init_gt_powersave(dev);
-
 
13286
	mutex_unlock(&dev->struct_mutex);
-
 
13287
 
-
 
13288
	/*
-
 
13289
	 * There may be no VBT; and if the BIOS enabled SSC we can
15442
{
Line 13290... Line 15443...
13290
	 * just keep using it to avoid unnecessary flicker.  Whereas if the
15443
	struct drm_crtc *c;
Line 13291... Line 15444...
13291
	 * BIOS isn't using it, don't assume it will work even if the VBT
15444
	struct drm_i915_gem_object *obj;
13292
	 * indicates as much.
15445
	int ret;
13293
	 */
15446
 
13294
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15447
	mutex_lock(&dev->struct_mutex);
13295
		dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15448
	intel_init_gt_powersave(dev);
13296
						DREF_SSC1_ENABLE);
-
 
13297
 
15449
	mutex_unlock(&dev->struct_mutex);
13298
	intel_modeset_init_hw(dev);
15450
 
13299
 
15451
	intel_modeset_init_hw(dev);
13300
//   intel_setup_overlay(dev);
15452
 
Line -... Line 15453...
-
 
15453
//   intel_setup_overlay(dev);
13301
 
15454
 
13302
	/*
15455
	/*
-
 
15456
	 * Make sure any fbs we allocated at startup are properly
13303
	 * Make sure any fbs we allocated at startup are properly
15457
	 * pinned & fenced.  When we do the allocation it's too early
-
 
15458
	 * for this.
-
 
15459
	 */
13304
	 * pinned & fenced.  When we do the allocation it's too early
15460
	for_each_crtc(dev, c) {
13305
	 * for this.
15461
		obj = intel_fb_obj(c->primary->fb);
13306
	 */
15462
		if (obj == NULL)
13307
	mutex_lock(&dev->struct_mutex);
15463
			continue;
-
 
15464
 
-
 
15465
		mutex_lock(&dev->struct_mutex);
-
 
15466
		ret = intel_pin_and_fence_fb_obj(c->primary,
13308
	for_each_crtc(dev, c) {
15467
						 c->primary->fb,
13309
		obj = intel_fb_obj(c->primary->fb);
15468
						 c->primary->state,
-
 
15469
						 NULL, NULL);
13310
		if (obj == NULL)
15470
		mutex_unlock(&dev->struct_mutex);
13311
			continue;
15471
		if (ret) {
Line 13312... Line 15472...
13312
 
15472
			DRM_ERROR("failed to pin boot fb on pipe %d\n",
13313
		if (intel_pin_and_fence_fb_obj(c->primary,
15473
				  to_intel_crtc(c)->pipe);
13314
					       c->primary->fb,
15474
			drm_framebuffer_unreference(c->primary->fb);
Line 13351... Line 15511...
13351
	 * Due to the hpd irq storm handling the hotplug work can re-arm the
15511
	 * Due to the hpd irq storm handling the hotplug work can re-arm the
13352
	 * poll handlers. Hence disable polling after hpd handling is shut down.
15512
	 * poll handlers. Hence disable polling after hpd handling is shut down.
13353
	 */
15513
	 */
13354
	drm_kms_helper_poll_fini(dev);
15514
	drm_kms_helper_poll_fini(dev);
Line 13355... Line -...
13355
 
-
 
13356
	mutex_lock(&dev->struct_mutex);
-
 
13357
 
15515
 
Line 13358... Line 15516...
13358
	intel_unregister_dsm_handler();
15516
	intel_unregister_dsm_handler();
13359
 
-
 
13360
	intel_disable_fbc(dev);
-
 
13361
 
-
 
13362
	ironlake_teardown_rc6(dev);
-
 
Line 13363... Line 15517...
13363
 
15517
 
13364
	mutex_unlock(&dev->struct_mutex);
15518
	intel_fbc_disable(dev_priv);
Line 13365... Line 15519...
13365
 
15519