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1 | /* |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | */ |
25 | */ |
26 | 26 | ||
27 | //#include |
27 | //#include |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
- | 42 | #include |
|
- | 43 | #include |
|
42 | //#include |
44 | #include |
- | 45 | ||
- | 46 | static inline void ndelay(unsigned long x) |
|
- | 47 | { |
|
- | 48 | udelay(DIV_ROUND_UP(x, 1000)); |
|
- | 49 | } |
|
- | 50 | ||
- | 51 | /* Primary plane formats supported by all gen */ |
|
- | 52 | #define COMMON_PRIMARY_FORMATS \ |
|
- | 53 | DRM_FORMAT_C8, \ |
|
- | 54 | DRM_FORMAT_RGB565, \ |
|
- | 55 | DRM_FORMAT_XRGB8888, \ |
|
- | 56 | DRM_FORMAT_ARGB8888 |
|
- | 57 | ||
- | 58 | /* Primary plane formats for gen <= 3 */ |
|
- | 59 | static const uint32_t intel_primary_formats_gen2[] = { |
|
- | 60 | COMMON_PRIMARY_FORMATS, |
|
- | 61 | DRM_FORMAT_XRGB1555, |
|
- | 62 | DRM_FORMAT_ARGB1555, |
|
- | 63 | }; |
|
- | 64 | ||
- | 65 | /* Primary plane formats for gen >= 4 */ |
|
- | 66 | static const uint32_t intel_primary_formats_gen4[] = { |
|
- | 67 | COMMON_PRIMARY_FORMATS, \ |
|
- | 68 | DRM_FORMAT_XBGR8888, |
|
- | 69 | DRM_FORMAT_ABGR8888, |
|
- | 70 | DRM_FORMAT_XRGB2101010, |
|
- | 71 | DRM_FORMAT_ARGB2101010, |
|
- | 72 | DRM_FORMAT_XBGR2101010, |
|
- | 73 | DRM_FORMAT_ABGR2101010, |
|
- | 74 | }; |
|
- | 75 | ||
- | 76 | /* Cursor formats */ |
|
- | 77 | static const uint32_t intel_cursor_formats[] = { |
|
- | 78 | DRM_FORMAT_ARGB8888, |
|
- | 79 | }; |
|
- | 80 | ||
- | 81 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
|
- | 82 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
|
43 | 83 | ||
44 | #define MAX_ERRNO 4095 |
84 | #define MAX_ERRNO 4095 |
45 | phys_addr_t get_bus_addr(void); |
85 | phys_addr_t get_bus_addr(void); |
46 | 86 | ||
47 | static inline void outb(u8 v, u16 port) |
87 | static inline void outb(u8 v, u16 port) |
48 | { |
88 | { |
49 | asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); |
89 | asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); |
50 | } |
90 | } |
51 | static inline u8 inb(u16 port) |
91 | static inline u8 inb(u16 port) |
52 | { |
92 | { |
53 | u8 v; |
93 | u8 v; |
54 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
94 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
55 | return v; |
95 | return v; |
56 | } |
96 | } |
57 | 97 | ||
- | 98 | static void intel_increase_pllclock(struct drm_device *dev, |
|
58 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
99 | enum pipe pipe); |
59 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
100 | void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
60 | 101 | ||
61 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
102 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
62 | struct intel_crtc_config *pipe_config); |
103 | struct intel_crtc_config *pipe_config); |
63 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
104 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
64 | struct intel_crtc_config *pipe_config); |
105 | struct intel_crtc_config *pipe_config); |
65 | 106 | ||
66 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
107 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
67 | int x, int y, struct drm_framebuffer *old_fb); |
108 | int x, int y, struct drm_framebuffer *old_fb); |
- | 109 | static int intel_framebuffer_init(struct drm_device *dev, |
|
- | 110 | struct intel_framebuffer *ifb, |
|
- | 111 | struct drm_mode_fb_cmd2 *mode_cmd, |
|
- | 112 | struct drm_i915_gem_object *obj); |
|
- | 113 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
|
- | 114 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
|
- | 115 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
|
- | 116 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
|
- | 117 | struct intel_link_m_n *m_n); |
|
- | 118 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
|
- | 119 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
|
- | 120 | static void intel_set_pipe_csc(struct drm_crtc *crtc); |
|
- | 121 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
|
- | 122 | ||
- | 123 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
|
- | 124 | { |
|
- | 125 | if (!connector->mst_port) |
|
- | 126 | return connector->encoder; |
|
- | 127 | else |
|
- | 128 | return &connector->mst_port->mst_encoders[pipe]->base; |
|
68 | 129 | } |
|
69 | 130 | ||
70 | typedef struct { |
131 | typedef struct { |
71 | int min, max; |
132 | int min, max; |
72 | } intel_range_t; |
133 | } intel_range_t; |
73 | 134 | ||
74 | typedef struct { |
135 | typedef struct { |
75 | int dot_limit; |
136 | int dot_limit; |
76 | int p2_slow, p2_fast; |
137 | int p2_slow, p2_fast; |
77 | } intel_p2_t; |
138 | } intel_p2_t; |
78 | 139 | ||
79 | typedef struct intel_limit intel_limit_t; |
140 | typedef struct intel_limit intel_limit_t; |
80 | struct intel_limit { |
141 | struct intel_limit { |
81 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
142 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
82 | intel_p2_t p2; |
143 | intel_p2_t p2; |
83 | }; |
144 | }; |
84 | 145 | ||
85 | int |
146 | int |
86 | intel_pch_rawclk(struct drm_device *dev) |
147 | intel_pch_rawclk(struct drm_device *dev) |
87 | { |
148 | { |
88 | struct drm_i915_private *dev_priv = dev->dev_private; |
149 | struct drm_i915_private *dev_priv = dev->dev_private; |
89 | 150 | ||
90 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
151 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
91 | 152 | ||
92 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
153 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
93 | } |
154 | } |
94 | 155 | ||
95 | static inline u32 /* units of 100MHz */ |
156 | static inline u32 /* units of 100MHz */ |
96 | intel_fdi_link_freq(struct drm_device *dev) |
157 | intel_fdi_link_freq(struct drm_device *dev) |
97 | { |
158 | { |
98 | if (IS_GEN5(dev)) { |
159 | if (IS_GEN5(dev)) { |
99 | struct drm_i915_private *dev_priv = dev->dev_private; |
160 | struct drm_i915_private *dev_priv = dev->dev_private; |
100 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
161 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
101 | } else |
162 | } else |
102 | return 27; |
163 | return 27; |
103 | } |
164 | } |
104 | 165 | ||
105 | static const intel_limit_t intel_limits_i8xx_dac = { |
166 | static const intel_limit_t intel_limits_i8xx_dac = { |
106 | .dot = { .min = 25000, .max = 350000 }, |
167 | .dot = { .min = 25000, .max = 350000 }, |
107 | .vco = { .min = 908000, .max = 1512000 }, |
168 | .vco = { .min = 908000, .max = 1512000 }, |
108 | .n = { .min = 2, .max = 16 }, |
169 | .n = { .min = 2, .max = 16 }, |
109 | .m = { .min = 96, .max = 140 }, |
170 | .m = { .min = 96, .max = 140 }, |
110 | .m1 = { .min = 18, .max = 26 }, |
171 | .m1 = { .min = 18, .max = 26 }, |
111 | .m2 = { .min = 6, .max = 16 }, |
172 | .m2 = { .min = 6, .max = 16 }, |
112 | .p = { .min = 4, .max = 128 }, |
173 | .p = { .min = 4, .max = 128 }, |
113 | .p1 = { .min = 2, .max = 33 }, |
174 | .p1 = { .min = 2, .max = 33 }, |
114 | .p2 = { .dot_limit = 165000, |
175 | .p2 = { .dot_limit = 165000, |
115 | .p2_slow = 4, .p2_fast = 2 }, |
176 | .p2_slow = 4, .p2_fast = 2 }, |
116 | }; |
177 | }; |
117 | 178 | ||
118 | static const intel_limit_t intel_limits_i8xx_dvo = { |
179 | static const intel_limit_t intel_limits_i8xx_dvo = { |
119 | .dot = { .min = 25000, .max = 350000 }, |
180 | .dot = { .min = 25000, .max = 350000 }, |
120 | .vco = { .min = 908000, .max = 1512000 }, |
181 | .vco = { .min = 908000, .max = 1512000 }, |
121 | .n = { .min = 2, .max = 16 }, |
182 | .n = { .min = 2, .max = 16 }, |
122 | .m = { .min = 96, .max = 140 }, |
183 | .m = { .min = 96, .max = 140 }, |
123 | .m1 = { .min = 18, .max = 26 }, |
184 | .m1 = { .min = 18, .max = 26 }, |
124 | .m2 = { .min = 6, .max = 16 }, |
185 | .m2 = { .min = 6, .max = 16 }, |
125 | .p = { .min = 4, .max = 128 }, |
186 | .p = { .min = 4, .max = 128 }, |
126 | .p1 = { .min = 2, .max = 33 }, |
187 | .p1 = { .min = 2, .max = 33 }, |
127 | .p2 = { .dot_limit = 165000, |
188 | .p2 = { .dot_limit = 165000, |
128 | .p2_slow = 4, .p2_fast = 4 }, |
189 | .p2_slow = 4, .p2_fast = 4 }, |
129 | }; |
190 | }; |
130 | 191 | ||
131 | static const intel_limit_t intel_limits_i8xx_lvds = { |
192 | static const intel_limit_t intel_limits_i8xx_lvds = { |
132 | .dot = { .min = 25000, .max = 350000 }, |
193 | .dot = { .min = 25000, .max = 350000 }, |
133 | .vco = { .min = 908000, .max = 1512000 }, |
194 | .vco = { .min = 908000, .max = 1512000 }, |
134 | .n = { .min = 2, .max = 16 }, |
195 | .n = { .min = 2, .max = 16 }, |
135 | .m = { .min = 96, .max = 140 }, |
196 | .m = { .min = 96, .max = 140 }, |
136 | .m1 = { .min = 18, .max = 26 }, |
197 | .m1 = { .min = 18, .max = 26 }, |
137 | .m2 = { .min = 6, .max = 16 }, |
198 | .m2 = { .min = 6, .max = 16 }, |
138 | .p = { .min = 4, .max = 128 }, |
199 | .p = { .min = 4, .max = 128 }, |
139 | .p1 = { .min = 1, .max = 6 }, |
200 | .p1 = { .min = 1, .max = 6 }, |
140 | .p2 = { .dot_limit = 165000, |
201 | .p2 = { .dot_limit = 165000, |
141 | .p2_slow = 14, .p2_fast = 7 }, |
202 | .p2_slow = 14, .p2_fast = 7 }, |
142 | }; |
203 | }; |
143 | 204 | ||
144 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
205 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
145 | .dot = { .min = 20000, .max = 400000 }, |
206 | .dot = { .min = 20000, .max = 400000 }, |
146 | .vco = { .min = 1400000, .max = 2800000 }, |
207 | .vco = { .min = 1400000, .max = 2800000 }, |
147 | .n = { .min = 1, .max = 6 }, |
208 | .n = { .min = 1, .max = 6 }, |
148 | .m = { .min = 70, .max = 120 }, |
209 | .m = { .min = 70, .max = 120 }, |
149 | .m1 = { .min = 8, .max = 18 }, |
210 | .m1 = { .min = 8, .max = 18 }, |
150 | .m2 = { .min = 3, .max = 7 }, |
211 | .m2 = { .min = 3, .max = 7 }, |
151 | .p = { .min = 5, .max = 80 }, |
212 | .p = { .min = 5, .max = 80 }, |
152 | .p1 = { .min = 1, .max = 8 }, |
213 | .p1 = { .min = 1, .max = 8 }, |
153 | .p2 = { .dot_limit = 200000, |
214 | .p2 = { .dot_limit = 200000, |
154 | .p2_slow = 10, .p2_fast = 5 }, |
215 | .p2_slow = 10, .p2_fast = 5 }, |
155 | }; |
216 | }; |
156 | 217 | ||
157 | static const intel_limit_t intel_limits_i9xx_lvds = { |
218 | static const intel_limit_t intel_limits_i9xx_lvds = { |
158 | .dot = { .min = 20000, .max = 400000 }, |
219 | .dot = { .min = 20000, .max = 400000 }, |
159 | .vco = { .min = 1400000, .max = 2800000 }, |
220 | .vco = { .min = 1400000, .max = 2800000 }, |
160 | .n = { .min = 1, .max = 6 }, |
221 | .n = { .min = 1, .max = 6 }, |
161 | .m = { .min = 70, .max = 120 }, |
222 | .m = { .min = 70, .max = 120 }, |
162 | .m1 = { .min = 8, .max = 18 }, |
223 | .m1 = { .min = 8, .max = 18 }, |
163 | .m2 = { .min = 3, .max = 7 }, |
224 | .m2 = { .min = 3, .max = 7 }, |
164 | .p = { .min = 7, .max = 98 }, |
225 | .p = { .min = 7, .max = 98 }, |
165 | .p1 = { .min = 1, .max = 8 }, |
226 | .p1 = { .min = 1, .max = 8 }, |
166 | .p2 = { .dot_limit = 112000, |
227 | .p2 = { .dot_limit = 112000, |
167 | .p2_slow = 14, .p2_fast = 7 }, |
228 | .p2_slow = 14, .p2_fast = 7 }, |
168 | }; |
229 | }; |
169 | 230 | ||
170 | 231 | ||
171 | static const intel_limit_t intel_limits_g4x_sdvo = { |
232 | static const intel_limit_t intel_limits_g4x_sdvo = { |
172 | .dot = { .min = 25000, .max = 270000 }, |
233 | .dot = { .min = 25000, .max = 270000 }, |
173 | .vco = { .min = 1750000, .max = 3500000}, |
234 | .vco = { .min = 1750000, .max = 3500000}, |
174 | .n = { .min = 1, .max = 4 }, |
235 | .n = { .min = 1, .max = 4 }, |
175 | .m = { .min = 104, .max = 138 }, |
236 | .m = { .min = 104, .max = 138 }, |
176 | .m1 = { .min = 17, .max = 23 }, |
237 | .m1 = { .min = 17, .max = 23 }, |
177 | .m2 = { .min = 5, .max = 11 }, |
238 | .m2 = { .min = 5, .max = 11 }, |
178 | .p = { .min = 10, .max = 30 }, |
239 | .p = { .min = 10, .max = 30 }, |
179 | .p1 = { .min = 1, .max = 3}, |
240 | .p1 = { .min = 1, .max = 3}, |
180 | .p2 = { .dot_limit = 270000, |
241 | .p2 = { .dot_limit = 270000, |
181 | .p2_slow = 10, |
242 | .p2_slow = 10, |
182 | .p2_fast = 10 |
243 | .p2_fast = 10 |
183 | }, |
244 | }, |
184 | }; |
245 | }; |
185 | 246 | ||
186 | static const intel_limit_t intel_limits_g4x_hdmi = { |
247 | static const intel_limit_t intel_limits_g4x_hdmi = { |
187 | .dot = { .min = 22000, .max = 400000 }, |
248 | .dot = { .min = 22000, .max = 400000 }, |
188 | .vco = { .min = 1750000, .max = 3500000}, |
249 | .vco = { .min = 1750000, .max = 3500000}, |
189 | .n = { .min = 1, .max = 4 }, |
250 | .n = { .min = 1, .max = 4 }, |
190 | .m = { .min = 104, .max = 138 }, |
251 | .m = { .min = 104, .max = 138 }, |
191 | .m1 = { .min = 16, .max = 23 }, |
252 | .m1 = { .min = 16, .max = 23 }, |
192 | .m2 = { .min = 5, .max = 11 }, |
253 | .m2 = { .min = 5, .max = 11 }, |
193 | .p = { .min = 5, .max = 80 }, |
254 | .p = { .min = 5, .max = 80 }, |
194 | .p1 = { .min = 1, .max = 8}, |
255 | .p1 = { .min = 1, .max = 8}, |
195 | .p2 = { .dot_limit = 165000, |
256 | .p2 = { .dot_limit = 165000, |
196 | .p2_slow = 10, .p2_fast = 5 }, |
257 | .p2_slow = 10, .p2_fast = 5 }, |
197 | }; |
258 | }; |
198 | 259 | ||
199 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
260 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
200 | .dot = { .min = 20000, .max = 115000 }, |
261 | .dot = { .min = 20000, .max = 115000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, |
262 | .vco = { .min = 1750000, .max = 3500000 }, |
202 | .n = { .min = 1, .max = 3 }, |
263 | .n = { .min = 1, .max = 3 }, |
203 | .m = { .min = 104, .max = 138 }, |
264 | .m = { .min = 104, .max = 138 }, |
204 | .m1 = { .min = 17, .max = 23 }, |
265 | .m1 = { .min = 17, .max = 23 }, |
205 | .m2 = { .min = 5, .max = 11 }, |
266 | .m2 = { .min = 5, .max = 11 }, |
206 | .p = { .min = 28, .max = 112 }, |
267 | .p = { .min = 28, .max = 112 }, |
207 | .p1 = { .min = 2, .max = 8 }, |
268 | .p1 = { .min = 2, .max = 8 }, |
208 | .p2 = { .dot_limit = 0, |
269 | .p2 = { .dot_limit = 0, |
209 | .p2_slow = 14, .p2_fast = 14 |
270 | .p2_slow = 14, .p2_fast = 14 |
210 | }, |
271 | }, |
211 | }; |
272 | }; |
212 | 273 | ||
213 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
274 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
214 | .dot = { .min = 80000, .max = 224000 }, |
275 | .dot = { .min = 80000, .max = 224000 }, |
215 | .vco = { .min = 1750000, .max = 3500000 }, |
276 | .vco = { .min = 1750000, .max = 3500000 }, |
216 | .n = { .min = 1, .max = 3 }, |
277 | .n = { .min = 1, .max = 3 }, |
217 | .m = { .min = 104, .max = 138 }, |
278 | .m = { .min = 104, .max = 138 }, |
218 | .m1 = { .min = 17, .max = 23 }, |
279 | .m1 = { .min = 17, .max = 23 }, |
219 | .m2 = { .min = 5, .max = 11 }, |
280 | .m2 = { .min = 5, .max = 11 }, |
220 | .p = { .min = 14, .max = 42 }, |
281 | .p = { .min = 14, .max = 42 }, |
221 | .p1 = { .min = 2, .max = 6 }, |
282 | .p1 = { .min = 2, .max = 6 }, |
222 | .p2 = { .dot_limit = 0, |
283 | .p2 = { .dot_limit = 0, |
223 | .p2_slow = 7, .p2_fast = 7 |
284 | .p2_slow = 7, .p2_fast = 7 |
224 | }, |
285 | }, |
225 | }; |
286 | }; |
226 | 287 | ||
227 | static const intel_limit_t intel_limits_pineview_sdvo = { |
288 | static const intel_limit_t intel_limits_pineview_sdvo = { |
228 | .dot = { .min = 20000, .max = 400000}, |
289 | .dot = { .min = 20000, .max = 400000}, |
229 | .vco = { .min = 1700000, .max = 3500000 }, |
290 | .vco = { .min = 1700000, .max = 3500000 }, |
230 | /* Pineview's Ncounter is a ring counter */ |
291 | /* Pineview's Ncounter is a ring counter */ |
231 | .n = { .min = 3, .max = 6 }, |
292 | .n = { .min = 3, .max = 6 }, |
232 | .m = { .min = 2, .max = 256 }, |
293 | .m = { .min = 2, .max = 256 }, |
233 | /* Pineview only has one combined m divider, which we treat as m2. */ |
294 | /* Pineview only has one combined m divider, which we treat as m2. */ |
234 | .m1 = { .min = 0, .max = 0 }, |
295 | .m1 = { .min = 0, .max = 0 }, |
235 | .m2 = { .min = 0, .max = 254 }, |
296 | .m2 = { .min = 0, .max = 254 }, |
236 | .p = { .min = 5, .max = 80 }, |
297 | .p = { .min = 5, .max = 80 }, |
237 | .p1 = { .min = 1, .max = 8 }, |
298 | .p1 = { .min = 1, .max = 8 }, |
238 | .p2 = { .dot_limit = 200000, |
299 | .p2 = { .dot_limit = 200000, |
239 | .p2_slow = 10, .p2_fast = 5 }, |
300 | .p2_slow = 10, .p2_fast = 5 }, |
240 | }; |
301 | }; |
241 | 302 | ||
242 | static const intel_limit_t intel_limits_pineview_lvds = { |
303 | static const intel_limit_t intel_limits_pineview_lvds = { |
243 | .dot = { .min = 20000, .max = 400000 }, |
304 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1700000, .max = 3500000 }, |
305 | .vco = { .min = 1700000, .max = 3500000 }, |
245 | .n = { .min = 3, .max = 6 }, |
306 | .n = { .min = 3, .max = 6 }, |
246 | .m = { .min = 2, .max = 256 }, |
307 | .m = { .min = 2, .max = 256 }, |
247 | .m1 = { .min = 0, .max = 0 }, |
308 | .m1 = { .min = 0, .max = 0 }, |
248 | .m2 = { .min = 0, .max = 254 }, |
309 | .m2 = { .min = 0, .max = 254 }, |
249 | .p = { .min = 7, .max = 112 }, |
310 | .p = { .min = 7, .max = 112 }, |
250 | .p1 = { .min = 1, .max = 8 }, |
311 | .p1 = { .min = 1, .max = 8 }, |
251 | .p2 = { .dot_limit = 112000, |
312 | .p2 = { .dot_limit = 112000, |
252 | .p2_slow = 14, .p2_fast = 14 }, |
313 | .p2_slow = 14, .p2_fast = 14 }, |
253 | }; |
314 | }; |
254 | 315 | ||
255 | /* Ironlake / Sandybridge |
316 | /* Ironlake / Sandybridge |
256 | * |
317 | * |
257 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
318 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
258 | * the range value for them is (actual_value - 2). |
319 | * the range value for them is (actual_value - 2). |
259 | */ |
320 | */ |
260 | static const intel_limit_t intel_limits_ironlake_dac = { |
321 | static const intel_limit_t intel_limits_ironlake_dac = { |
261 | .dot = { .min = 25000, .max = 350000 }, |
322 | .dot = { .min = 25000, .max = 350000 }, |
262 | .vco = { .min = 1760000, .max = 3510000 }, |
323 | .vco = { .min = 1760000, .max = 3510000 }, |
263 | .n = { .min = 1, .max = 5 }, |
324 | .n = { .min = 1, .max = 5 }, |
264 | .m = { .min = 79, .max = 127 }, |
325 | .m = { .min = 79, .max = 127 }, |
265 | .m1 = { .min = 12, .max = 22 }, |
326 | .m1 = { .min = 12, .max = 22 }, |
266 | .m2 = { .min = 5, .max = 9 }, |
327 | .m2 = { .min = 5, .max = 9 }, |
267 | .p = { .min = 5, .max = 80 }, |
328 | .p = { .min = 5, .max = 80 }, |
268 | .p1 = { .min = 1, .max = 8 }, |
329 | .p1 = { .min = 1, .max = 8 }, |
269 | .p2 = { .dot_limit = 225000, |
330 | .p2 = { .dot_limit = 225000, |
270 | .p2_slow = 10, .p2_fast = 5 }, |
331 | .p2_slow = 10, .p2_fast = 5 }, |
271 | }; |
332 | }; |
272 | 333 | ||
273 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
334 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
274 | .dot = { .min = 25000, .max = 350000 }, |
335 | .dot = { .min = 25000, .max = 350000 }, |
275 | .vco = { .min = 1760000, .max = 3510000 }, |
336 | .vco = { .min = 1760000, .max = 3510000 }, |
276 | .n = { .min = 1, .max = 3 }, |
337 | .n = { .min = 1, .max = 3 }, |
277 | .m = { .min = 79, .max = 118 }, |
338 | .m = { .min = 79, .max = 118 }, |
278 | .m1 = { .min = 12, .max = 22 }, |
339 | .m1 = { .min = 12, .max = 22 }, |
279 | .m2 = { .min = 5, .max = 9 }, |
340 | .m2 = { .min = 5, .max = 9 }, |
280 | .p = { .min = 28, .max = 112 }, |
341 | .p = { .min = 28, .max = 112 }, |
281 | .p1 = { .min = 2, .max = 8 }, |
342 | .p1 = { .min = 2, .max = 8 }, |
282 | .p2 = { .dot_limit = 225000, |
343 | .p2 = { .dot_limit = 225000, |
283 | .p2_slow = 14, .p2_fast = 14 }, |
344 | .p2_slow = 14, .p2_fast = 14 }, |
284 | }; |
345 | }; |
285 | 346 | ||
286 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
287 | .dot = { .min = 25000, .max = 350000 }, |
348 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, |
289 | .n = { .min = 1, .max = 3 }, |
350 | .n = { .min = 1, .max = 3 }, |
290 | .m = { .min = 79, .max = 127 }, |
351 | .m = { .min = 79, .max = 127 }, |
291 | .m1 = { .min = 12, .max = 22 }, |
352 | .m1 = { .min = 12, .max = 22 }, |
292 | .m2 = { .min = 5, .max = 9 }, |
353 | .m2 = { .min = 5, .max = 9 }, |
293 | .p = { .min = 14, .max = 56 }, |
354 | .p = { .min = 14, .max = 56 }, |
294 | .p1 = { .min = 2, .max = 8 }, |
355 | .p1 = { .min = 2, .max = 8 }, |
295 | .p2 = { .dot_limit = 225000, |
356 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 7, .p2_fast = 7 }, |
357 | .p2_slow = 7, .p2_fast = 7 }, |
297 | }; |
358 | }; |
298 | 359 | ||
299 | /* LVDS 100mhz refclk limits. */ |
360 | /* LVDS 100mhz refclk limits. */ |
300 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
361 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
301 | .dot = { .min = 25000, .max = 350000 }, |
362 | .dot = { .min = 25000, .max = 350000 }, |
302 | .vco = { .min = 1760000, .max = 3510000 }, |
363 | .vco = { .min = 1760000, .max = 3510000 }, |
303 | .n = { .min = 1, .max = 2 }, |
364 | .n = { .min = 1, .max = 2 }, |
304 | .m = { .min = 79, .max = 126 }, |
365 | .m = { .min = 79, .max = 126 }, |
305 | .m1 = { .min = 12, .max = 22 }, |
366 | .m1 = { .min = 12, .max = 22 }, |
306 | .m2 = { .min = 5, .max = 9 }, |
367 | .m2 = { .min = 5, .max = 9 }, |
307 | .p = { .min = 28, .max = 112 }, |
368 | .p = { .min = 28, .max = 112 }, |
308 | .p1 = { .min = 2, .max = 8 }, |
369 | .p1 = { .min = 2, .max = 8 }, |
309 | .p2 = { .dot_limit = 225000, |
370 | .p2 = { .dot_limit = 225000, |
310 | .p2_slow = 14, .p2_fast = 14 }, |
371 | .p2_slow = 14, .p2_fast = 14 }, |
311 | }; |
372 | }; |
312 | 373 | ||
313 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
374 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
314 | .dot = { .min = 25000, .max = 350000 }, |
375 | .dot = { .min = 25000, .max = 350000 }, |
315 | .vco = { .min = 1760000, .max = 3510000 }, |
376 | .vco = { .min = 1760000, .max = 3510000 }, |
316 | .n = { .min = 1, .max = 3 }, |
377 | .n = { .min = 1, .max = 3 }, |
317 | .m = { .min = 79, .max = 126 }, |
378 | .m = { .min = 79, .max = 126 }, |
318 | .m1 = { .min = 12, .max = 22 }, |
379 | .m1 = { .min = 12, .max = 22 }, |
319 | .m2 = { .min = 5, .max = 9 }, |
380 | .m2 = { .min = 5, .max = 9 }, |
320 | .p = { .min = 14, .max = 42 }, |
381 | .p = { .min = 14, .max = 42 }, |
321 | .p1 = { .min = 2, .max = 6 }, |
382 | .p1 = { .min = 2, .max = 6 }, |
322 | .p2 = { .dot_limit = 225000, |
383 | .p2 = { .dot_limit = 225000, |
323 | .p2_slow = 7, .p2_fast = 7 }, |
384 | .p2_slow = 7, .p2_fast = 7 }, |
324 | }; |
385 | }; |
325 | 386 | ||
326 | static const intel_limit_t intel_limits_vlv = { |
387 | static const intel_limit_t intel_limits_vlv = { |
327 | /* |
388 | /* |
328 | * These are the data rate limits (measured in fast clocks) |
389 | * These are the data rate limits (measured in fast clocks) |
329 | * since those are the strictest limits we have. The fast |
390 | * since those are the strictest limits we have. The fast |
330 | * clock and actual rate limits are more relaxed, so checking |
391 | * clock and actual rate limits are more relaxed, so checking |
331 | * them would make no difference. |
392 | * them would make no difference. |
332 | */ |
393 | */ |
333 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
394 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
395 | .vco = { .min = 4000000, .max = 6000000 }, |
335 | .n = { .min = 1, .max = 7 }, |
396 | .n = { .min = 1, .max = 7 }, |
336 | .m1 = { .min = 2, .max = 3 }, |
397 | .m1 = { .min = 2, .max = 3 }, |
337 | .m2 = { .min = 11, .max = 156 }, |
398 | .m2 = { .min = 11, .max = 156 }, |
338 | .p1 = { .min = 2, .max = 3 }, |
399 | .p1 = { .min = 2, .max = 3 }, |
339 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
400 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
340 | }; |
401 | }; |
- | 402 | ||
- | 403 | static const intel_limit_t intel_limits_chv = { |
|
- | 404 | /* |
|
- | 405 | * These are the data rate limits (measured in fast clocks) |
|
- | 406 | * since those are the strictest limits we have. The fast |
|
- | 407 | * clock and actual rate limits are more relaxed, so checking |
|
- | 408 | * them would make no difference. |
|
- | 409 | */ |
|
- | 410 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
|
- | 411 | .vco = { .min = 4860000, .max = 6700000 }, |
|
- | 412 | .n = { .min = 1, .max = 1 }, |
|
- | 413 | .m1 = { .min = 2, .max = 2 }, |
|
- | 414 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
|
- | 415 | .p1 = { .min = 2, .max = 4 }, |
|
- | 416 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
|
- | 417 | }; |
|
341 | 418 | ||
342 | static void vlv_clock(int refclk, intel_clock_t *clock) |
419 | static void vlv_clock(int refclk, intel_clock_t *clock) |
343 | { |
420 | { |
344 | clock->m = clock->m1 * clock->m2; |
421 | clock->m = clock->m1 * clock->m2; |
345 | clock->p = clock->p1 * clock->p2; |
422 | clock->p = clock->p1 * clock->p2; |
346 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
423 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
347 | return; |
424 | return; |
348 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
425 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
349 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
426 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
350 | } |
427 | } |
351 | 428 | ||
352 | /** |
429 | /** |
353 | * Returns whether any output on the specified pipe is of the specified type |
430 | * Returns whether any output on the specified pipe is of the specified type |
354 | */ |
431 | */ |
355 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
432 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
356 | { |
433 | { |
357 | struct drm_device *dev = crtc->dev; |
434 | struct drm_device *dev = crtc->dev; |
358 | struct intel_encoder *encoder; |
435 | struct intel_encoder *encoder; |
359 | 436 | ||
360 | for_each_encoder_on_crtc(dev, crtc, encoder) |
437 | for_each_encoder_on_crtc(dev, crtc, encoder) |
361 | if (encoder->type == type) |
438 | if (encoder->type == type) |
362 | return true; |
439 | return true; |
363 | 440 | ||
364 | return false; |
441 | return false; |
365 | } |
442 | } |
366 | 443 | ||
367 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
444 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
368 | int refclk) |
445 | int refclk) |
369 | { |
446 | { |
370 | struct drm_device *dev = crtc->dev; |
447 | struct drm_device *dev = crtc->dev; |
371 | const intel_limit_t *limit; |
448 | const intel_limit_t *limit; |
372 | 449 | ||
373 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
450 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
374 | if (intel_is_dual_link_lvds(dev)) { |
451 | if (intel_is_dual_link_lvds(dev)) { |
375 | if (refclk == 100000) |
452 | if (refclk == 100000) |
376 | limit = &intel_limits_ironlake_dual_lvds_100m; |
453 | limit = &intel_limits_ironlake_dual_lvds_100m; |
377 | else |
454 | else |
378 | limit = &intel_limits_ironlake_dual_lvds; |
455 | limit = &intel_limits_ironlake_dual_lvds; |
379 | } else { |
456 | } else { |
380 | if (refclk == 100000) |
457 | if (refclk == 100000) |
381 | limit = &intel_limits_ironlake_single_lvds_100m; |
458 | limit = &intel_limits_ironlake_single_lvds_100m; |
382 | else |
459 | else |
383 | limit = &intel_limits_ironlake_single_lvds; |
460 | limit = &intel_limits_ironlake_single_lvds; |
384 | } |
461 | } |
385 | } else |
462 | } else |
386 | limit = &intel_limits_ironlake_dac; |
463 | limit = &intel_limits_ironlake_dac; |
387 | 464 | ||
388 | return limit; |
465 | return limit; |
389 | } |
466 | } |
390 | 467 | ||
391 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
468 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
392 | { |
469 | { |
393 | struct drm_device *dev = crtc->dev; |
470 | struct drm_device *dev = crtc->dev; |
394 | const intel_limit_t *limit; |
471 | const intel_limit_t *limit; |
395 | 472 | ||
396 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
473 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
397 | if (intel_is_dual_link_lvds(dev)) |
474 | if (intel_is_dual_link_lvds(dev)) |
398 | limit = &intel_limits_g4x_dual_channel_lvds; |
475 | limit = &intel_limits_g4x_dual_channel_lvds; |
399 | else |
476 | else |
400 | limit = &intel_limits_g4x_single_channel_lvds; |
477 | limit = &intel_limits_g4x_single_channel_lvds; |
401 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
478 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
402 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
479 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
403 | limit = &intel_limits_g4x_hdmi; |
480 | limit = &intel_limits_g4x_hdmi; |
404 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
481 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
405 | limit = &intel_limits_g4x_sdvo; |
482 | limit = &intel_limits_g4x_sdvo; |
406 | } else /* The option is for other outputs */ |
483 | } else /* The option is for other outputs */ |
407 | limit = &intel_limits_i9xx_sdvo; |
484 | limit = &intel_limits_i9xx_sdvo; |
408 | 485 | ||
409 | return limit; |
486 | return limit; |
410 | } |
487 | } |
411 | 488 | ||
412 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
489 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
413 | { |
490 | { |
414 | struct drm_device *dev = crtc->dev; |
491 | struct drm_device *dev = crtc->dev; |
415 | const intel_limit_t *limit; |
492 | const intel_limit_t *limit; |
416 | 493 | ||
417 | if (HAS_PCH_SPLIT(dev)) |
494 | if (HAS_PCH_SPLIT(dev)) |
418 | limit = intel_ironlake_limit(crtc, refclk); |
495 | limit = intel_ironlake_limit(crtc, refclk); |
419 | else if (IS_G4X(dev)) { |
496 | else if (IS_G4X(dev)) { |
420 | limit = intel_g4x_limit(crtc); |
497 | limit = intel_g4x_limit(crtc); |
421 | } else if (IS_PINEVIEW(dev)) { |
498 | } else if (IS_PINEVIEW(dev)) { |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
499 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
423 | limit = &intel_limits_pineview_lvds; |
500 | limit = &intel_limits_pineview_lvds; |
424 | else |
501 | else |
425 | limit = &intel_limits_pineview_sdvo; |
502 | limit = &intel_limits_pineview_sdvo; |
- | 503 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 504 | limit = &intel_limits_chv; |
|
426 | } else if (IS_VALLEYVIEW(dev)) { |
505 | } else if (IS_VALLEYVIEW(dev)) { |
427 | limit = &intel_limits_vlv; |
506 | limit = &intel_limits_vlv; |
428 | } else if (!IS_GEN2(dev)) { |
507 | } else if (!IS_GEN2(dev)) { |
429 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
508 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
430 | limit = &intel_limits_i9xx_lvds; |
509 | limit = &intel_limits_i9xx_lvds; |
431 | else |
510 | else |
432 | limit = &intel_limits_i9xx_sdvo; |
511 | limit = &intel_limits_i9xx_sdvo; |
433 | } else { |
512 | } else { |
434 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
513 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
435 | limit = &intel_limits_i8xx_lvds; |
514 | limit = &intel_limits_i8xx_lvds; |
436 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
515 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
437 | limit = &intel_limits_i8xx_dvo; |
516 | limit = &intel_limits_i8xx_dvo; |
438 | else |
517 | else |
439 | limit = &intel_limits_i8xx_dac; |
518 | limit = &intel_limits_i8xx_dac; |
440 | } |
519 | } |
441 | return limit; |
520 | return limit; |
442 | } |
521 | } |
443 | 522 | ||
444 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
523 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
445 | static void pineview_clock(int refclk, intel_clock_t *clock) |
524 | static void pineview_clock(int refclk, intel_clock_t *clock) |
446 | { |
525 | { |
447 | clock->m = clock->m2 + 2; |
526 | clock->m = clock->m2 + 2; |
448 | clock->p = clock->p1 * clock->p2; |
527 | clock->p = clock->p1 * clock->p2; |
449 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
450 | return; |
529 | return; |
451 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
530 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
452 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
531 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
453 | } |
532 | } |
454 | 533 | ||
455 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
534 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
456 | { |
535 | { |
457 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
536 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
458 | } |
537 | } |
459 | 538 | ||
460 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
539 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
461 | { |
540 | { |
462 | clock->m = i9xx_dpll_compute_m(clock); |
541 | clock->m = i9xx_dpll_compute_m(clock); |
463 | clock->p = clock->p1 * clock->p2; |
542 | clock->p = clock->p1 * clock->p2; |
464 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
543 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
465 | return; |
544 | return; |
466 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
545 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
467 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
546 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
468 | } |
547 | } |
- | 548 | ||
- | 549 | static void chv_clock(int refclk, intel_clock_t *clock) |
|
- | 550 | { |
|
- | 551 | clock->m = clock->m1 * clock->m2; |
|
- | 552 | clock->p = clock->p1 * clock->p2; |
|
- | 553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
|
- | 554 | return; |
|
- | 555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
|
- | 556 | clock->n << 22); |
|
- | 557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
- | 558 | } |
|
469 | 559 | ||
470 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
560 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
471 | /** |
561 | /** |
472 | * Returns whether the given set of divisors are valid for a given refclk with |
562 | * Returns whether the given set of divisors are valid for a given refclk with |
473 | * the given connectors. |
563 | * the given connectors. |
474 | */ |
564 | */ |
475 | 565 | ||
476 | static bool intel_PLL_is_valid(struct drm_device *dev, |
566 | static bool intel_PLL_is_valid(struct drm_device *dev, |
477 | const intel_limit_t *limit, |
567 | const intel_limit_t *limit, |
478 | const intel_clock_t *clock) |
568 | const intel_clock_t *clock) |
479 | { |
569 | { |
480 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
570 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
481 | INTELPllInvalid("n out of range\n"); |
571 | INTELPllInvalid("n out of range\n"); |
482 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
572 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
483 | INTELPllInvalid("p1 out of range\n"); |
573 | INTELPllInvalid("p1 out of range\n"); |
484 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
574 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
485 | INTELPllInvalid("m2 out of range\n"); |
575 | INTELPllInvalid("m2 out of range\n"); |
486 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
576 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
487 | INTELPllInvalid("m1 out of range\n"); |
577 | INTELPllInvalid("m1 out of range\n"); |
488 | 578 | ||
489 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
579 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
490 | if (clock->m1 <= clock->m2) |
580 | if (clock->m1 <= clock->m2) |
491 | INTELPllInvalid("m1 <= m2\n"); |
581 | INTELPllInvalid("m1 <= m2\n"); |
492 | 582 | ||
493 | if (!IS_VALLEYVIEW(dev)) { |
583 | if (!IS_VALLEYVIEW(dev)) { |
494 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
584 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
495 | INTELPllInvalid("p out of range\n"); |
585 | INTELPllInvalid("p out of range\n"); |
496 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
586 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
497 | INTELPllInvalid("m out of range\n"); |
587 | INTELPllInvalid("m out of range\n"); |
498 | } |
588 | } |
499 | 589 | ||
500 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
590 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
501 | INTELPllInvalid("vco out of range\n"); |
591 | INTELPllInvalid("vco out of range\n"); |
502 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
592 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
503 | * connector, etc., rather than just a single range. |
593 | * connector, etc., rather than just a single range. |
504 | */ |
594 | */ |
505 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
595 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
506 | INTELPllInvalid("dot out of range\n"); |
596 | INTELPllInvalid("dot out of range\n"); |
507 | 597 | ||
508 | return true; |
598 | return true; |
509 | } |
599 | } |
510 | 600 | ||
511 | static bool |
601 | static bool |
512 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
602 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
513 | int target, int refclk, intel_clock_t *match_clock, |
603 | int target, int refclk, intel_clock_t *match_clock, |
514 | intel_clock_t *best_clock) |
604 | intel_clock_t *best_clock) |
515 | { |
605 | { |
516 | struct drm_device *dev = crtc->dev; |
606 | struct drm_device *dev = crtc->dev; |
517 | intel_clock_t clock; |
607 | intel_clock_t clock; |
518 | int err = target; |
608 | int err = target; |
519 | 609 | ||
520 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
610 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
521 | /* |
611 | /* |
522 | * For LVDS just rely on its current settings for dual-channel. |
612 | * For LVDS just rely on its current settings for dual-channel. |
523 | * We haven't figured out how to reliably set up different |
613 | * We haven't figured out how to reliably set up different |
524 | * single/dual channel state, if we even can. |
614 | * single/dual channel state, if we even can. |
525 | */ |
615 | */ |
526 | if (intel_is_dual_link_lvds(dev)) |
616 | if (intel_is_dual_link_lvds(dev)) |
527 | clock.p2 = limit->p2.p2_fast; |
617 | clock.p2 = limit->p2.p2_fast; |
528 | else |
618 | else |
529 | clock.p2 = limit->p2.p2_slow; |
619 | clock.p2 = limit->p2.p2_slow; |
530 | } else { |
620 | } else { |
531 | if (target < limit->p2.dot_limit) |
621 | if (target < limit->p2.dot_limit) |
532 | clock.p2 = limit->p2.p2_slow; |
622 | clock.p2 = limit->p2.p2_slow; |
533 | else |
623 | else |
534 | clock.p2 = limit->p2.p2_fast; |
624 | clock.p2 = limit->p2.p2_fast; |
535 | } |
625 | } |
536 | 626 | ||
537 | memset(best_clock, 0, sizeof(*best_clock)); |
627 | memset(best_clock, 0, sizeof(*best_clock)); |
538 | 628 | ||
539 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
540 | clock.m1++) { |
630 | clock.m1++) { |
541 | for (clock.m2 = limit->m2.min; |
631 | for (clock.m2 = limit->m2.min; |
542 | clock.m2 <= limit->m2.max; clock.m2++) { |
632 | clock.m2 <= limit->m2.max; clock.m2++) { |
543 | if (clock.m2 >= clock.m1) |
633 | if (clock.m2 >= clock.m1) |
544 | break; |
634 | break; |
545 | for (clock.n = limit->n.min; |
635 | for (clock.n = limit->n.min; |
546 | clock.n <= limit->n.max; clock.n++) { |
636 | clock.n <= limit->n.max; clock.n++) { |
547 | for (clock.p1 = limit->p1.min; |
637 | for (clock.p1 = limit->p1.min; |
548 | clock.p1 <= limit->p1.max; clock.p1++) { |
638 | clock.p1 <= limit->p1.max; clock.p1++) { |
549 | int this_err; |
639 | int this_err; |
550 | 640 | ||
551 | i9xx_clock(refclk, &clock); |
641 | i9xx_clock(refclk, &clock); |
552 | if (!intel_PLL_is_valid(dev, limit, |
642 | if (!intel_PLL_is_valid(dev, limit, |
553 | &clock)) |
643 | &clock)) |
554 | continue; |
644 | continue; |
555 | if (match_clock && |
645 | if (match_clock && |
556 | clock.p != match_clock->p) |
646 | clock.p != match_clock->p) |
557 | continue; |
647 | continue; |
558 | 648 | ||
559 | this_err = abs(clock.dot - target); |
649 | this_err = abs(clock.dot - target); |
560 | if (this_err < err) { |
650 | if (this_err < err) { |
561 | *best_clock = clock; |
651 | *best_clock = clock; |
562 | err = this_err; |
652 | err = this_err; |
563 | } |
653 | } |
564 | } |
654 | } |
565 | } |
655 | } |
566 | } |
656 | } |
567 | } |
657 | } |
568 | 658 | ||
569 | return (err != target); |
659 | return (err != target); |
570 | } |
660 | } |
571 | 661 | ||
572 | static bool |
662 | static bool |
573 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
663 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
574 | int target, int refclk, intel_clock_t *match_clock, |
664 | int target, int refclk, intel_clock_t *match_clock, |
575 | intel_clock_t *best_clock) |
665 | intel_clock_t *best_clock) |
576 | { |
666 | { |
577 | struct drm_device *dev = crtc->dev; |
667 | struct drm_device *dev = crtc->dev; |
578 | intel_clock_t clock; |
668 | intel_clock_t clock; |
579 | int err = target; |
669 | int err = target; |
580 | 670 | ||
581 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
671 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
582 | /* |
672 | /* |
583 | * For LVDS just rely on its current settings for dual-channel. |
673 | * For LVDS just rely on its current settings for dual-channel. |
584 | * We haven't figured out how to reliably set up different |
674 | * We haven't figured out how to reliably set up different |
585 | * single/dual channel state, if we even can. |
675 | * single/dual channel state, if we even can. |
586 | */ |
676 | */ |
587 | if (intel_is_dual_link_lvds(dev)) |
677 | if (intel_is_dual_link_lvds(dev)) |
588 | clock.p2 = limit->p2.p2_fast; |
678 | clock.p2 = limit->p2.p2_fast; |
589 | else |
679 | else |
590 | clock.p2 = limit->p2.p2_slow; |
680 | clock.p2 = limit->p2.p2_slow; |
591 | } else { |
681 | } else { |
592 | if (target < limit->p2.dot_limit) |
682 | if (target < limit->p2.dot_limit) |
593 | clock.p2 = limit->p2.p2_slow; |
683 | clock.p2 = limit->p2.p2_slow; |
594 | else |
684 | else |
595 | clock.p2 = limit->p2.p2_fast; |
685 | clock.p2 = limit->p2.p2_fast; |
596 | } |
686 | } |
597 | 687 | ||
598 | memset(best_clock, 0, sizeof(*best_clock)); |
688 | memset(best_clock, 0, sizeof(*best_clock)); |
599 | 689 | ||
600 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
690 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
601 | clock.m1++) { |
691 | clock.m1++) { |
602 | for (clock.m2 = limit->m2.min; |
692 | for (clock.m2 = limit->m2.min; |
603 | clock.m2 <= limit->m2.max; clock.m2++) { |
693 | clock.m2 <= limit->m2.max; clock.m2++) { |
604 | for (clock.n = limit->n.min; |
694 | for (clock.n = limit->n.min; |
605 | clock.n <= limit->n.max; clock.n++) { |
695 | clock.n <= limit->n.max; clock.n++) { |
606 | for (clock.p1 = limit->p1.min; |
696 | for (clock.p1 = limit->p1.min; |
607 | clock.p1 <= limit->p1.max; clock.p1++) { |
697 | clock.p1 <= limit->p1.max; clock.p1++) { |
608 | int this_err; |
698 | int this_err; |
609 | 699 | ||
610 | pineview_clock(refclk, &clock); |
700 | pineview_clock(refclk, &clock); |
611 | if (!intel_PLL_is_valid(dev, limit, |
701 | if (!intel_PLL_is_valid(dev, limit, |
612 | &clock)) |
702 | &clock)) |
613 | continue; |
703 | continue; |
614 | if (match_clock && |
704 | if (match_clock && |
615 | clock.p != match_clock->p) |
705 | clock.p != match_clock->p) |
616 | continue; |
706 | continue; |
617 | 707 | ||
618 | this_err = abs(clock.dot - target); |
708 | this_err = abs(clock.dot - target); |
619 | if (this_err < err) { |
709 | if (this_err < err) { |
620 | *best_clock = clock; |
710 | *best_clock = clock; |
621 | err = this_err; |
711 | err = this_err; |
622 | } |
712 | } |
623 | } |
713 | } |
624 | } |
714 | } |
625 | } |
715 | } |
626 | } |
716 | } |
627 | 717 | ||
628 | return (err != target); |
718 | return (err != target); |
629 | } |
719 | } |
630 | 720 | ||
631 | static bool |
721 | static bool |
632 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
722 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
633 | int target, int refclk, intel_clock_t *match_clock, |
723 | int target, int refclk, intel_clock_t *match_clock, |
634 | intel_clock_t *best_clock) |
724 | intel_clock_t *best_clock) |
635 | { |
725 | { |
636 | struct drm_device *dev = crtc->dev; |
726 | struct drm_device *dev = crtc->dev; |
637 | intel_clock_t clock; |
727 | intel_clock_t clock; |
638 | int max_n; |
728 | int max_n; |
639 | bool found; |
729 | bool found; |
640 | /* approximately equals target * 0.00585 */ |
730 | /* approximately equals target * 0.00585 */ |
641 | int err_most = (target >> 8) + (target >> 9); |
731 | int err_most = (target >> 8) + (target >> 9); |
642 | found = false; |
732 | found = false; |
643 | 733 | ||
644 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
734 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
645 | if (intel_is_dual_link_lvds(dev)) |
735 | if (intel_is_dual_link_lvds(dev)) |
646 | clock.p2 = limit->p2.p2_fast; |
736 | clock.p2 = limit->p2.p2_fast; |
647 | else |
737 | else |
648 | clock.p2 = limit->p2.p2_slow; |
738 | clock.p2 = limit->p2.p2_slow; |
649 | } else { |
739 | } else { |
650 | if (target < limit->p2.dot_limit) |
740 | if (target < limit->p2.dot_limit) |
651 | clock.p2 = limit->p2.p2_slow; |
741 | clock.p2 = limit->p2.p2_slow; |
652 | else |
742 | else |
653 | clock.p2 = limit->p2.p2_fast; |
743 | clock.p2 = limit->p2.p2_fast; |
654 | } |
744 | } |
655 | 745 | ||
656 | memset(best_clock, 0, sizeof(*best_clock)); |
746 | memset(best_clock, 0, sizeof(*best_clock)); |
657 | max_n = limit->n.max; |
747 | max_n = limit->n.max; |
658 | /* based on hardware requirement, prefer smaller n to precision */ |
748 | /* based on hardware requirement, prefer smaller n to precision */ |
659 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
749 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
660 | /* based on hardware requirement, prefere larger m1,m2 */ |
750 | /* based on hardware requirement, prefere larger m1,m2 */ |
661 | for (clock.m1 = limit->m1.max; |
751 | for (clock.m1 = limit->m1.max; |
662 | clock.m1 >= limit->m1.min; clock.m1--) { |
752 | clock.m1 >= limit->m1.min; clock.m1--) { |
663 | for (clock.m2 = limit->m2.max; |
753 | for (clock.m2 = limit->m2.max; |
664 | clock.m2 >= limit->m2.min; clock.m2--) { |
754 | clock.m2 >= limit->m2.min; clock.m2--) { |
665 | for (clock.p1 = limit->p1.max; |
755 | for (clock.p1 = limit->p1.max; |
666 | clock.p1 >= limit->p1.min; clock.p1--) { |
756 | clock.p1 >= limit->p1.min; clock.p1--) { |
667 | int this_err; |
757 | int this_err; |
668 | 758 | ||
669 | i9xx_clock(refclk, &clock); |
759 | i9xx_clock(refclk, &clock); |
670 | if (!intel_PLL_is_valid(dev, limit, |
760 | if (!intel_PLL_is_valid(dev, limit, |
671 | &clock)) |
761 | &clock)) |
672 | continue; |
762 | continue; |
673 | 763 | ||
674 | this_err = abs(clock.dot - target); |
764 | this_err = abs(clock.dot - target); |
675 | if (this_err < err_most) { |
765 | if (this_err < err_most) { |
676 | *best_clock = clock; |
766 | *best_clock = clock; |
677 | err_most = this_err; |
767 | err_most = this_err; |
678 | max_n = clock.n; |
768 | max_n = clock.n; |
679 | found = true; |
769 | found = true; |
680 | } |
770 | } |
681 | } |
771 | } |
682 | } |
772 | } |
683 | } |
773 | } |
684 | } |
774 | } |
685 | return found; |
775 | return found; |
686 | } |
776 | } |
687 | 777 | ||
688 | static bool |
778 | static bool |
689 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
779 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
690 | int target, int refclk, intel_clock_t *match_clock, |
780 | int target, int refclk, intel_clock_t *match_clock, |
691 | intel_clock_t *best_clock) |
781 | intel_clock_t *best_clock) |
692 | { |
782 | { |
693 | struct drm_device *dev = crtc->dev; |
783 | struct drm_device *dev = crtc->dev; |
694 | intel_clock_t clock; |
784 | intel_clock_t clock; |
695 | unsigned int bestppm = 1000000; |
785 | unsigned int bestppm = 1000000; |
696 | /* min update 19.2 MHz */ |
786 | /* min update 19.2 MHz */ |
697 | int max_n = min(limit->n.max, refclk / 19200); |
787 | int max_n = min(limit->n.max, refclk / 19200); |
698 | bool found = false; |
788 | bool found = false; |
699 | 789 | ||
700 | target *= 5; /* fast clock */ |
790 | target *= 5; /* fast clock */ |
701 | 791 | ||
702 | memset(best_clock, 0, sizeof(*best_clock)); |
792 | memset(best_clock, 0, sizeof(*best_clock)); |
703 | 793 | ||
704 | /* based on hardware requirement, prefer smaller n to precision */ |
794 | /* based on hardware requirement, prefer smaller n to precision */ |
705 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
795 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
706 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
796 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
707 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
797 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
708 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
798 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
709 | clock.p = clock.p1 * clock.p2; |
799 | clock.p = clock.p1 * clock.p2; |
710 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
800 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
711 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
801 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
712 | unsigned int ppm, diff; |
802 | unsigned int ppm, diff; |
713 | 803 | ||
714 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
804 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
715 | refclk * clock.m1); |
805 | refclk * clock.m1); |
716 | 806 | ||
717 | vlv_clock(refclk, &clock); |
807 | vlv_clock(refclk, &clock); |
718 | 808 | ||
719 | if (!intel_PLL_is_valid(dev, limit, |
809 | if (!intel_PLL_is_valid(dev, limit, |
720 | &clock)) |
810 | &clock)) |
721 | continue; |
811 | continue; |
722 | 812 | ||
723 | diff = abs(clock.dot - target); |
813 | diff = abs(clock.dot - target); |
724 | ppm = div_u64(1000000ULL * diff, target); |
814 | ppm = div_u64(1000000ULL * diff, target); |
725 | 815 | ||
726 | if (ppm < 100 && clock.p > best_clock->p) { |
816 | if (ppm < 100 && clock.p > best_clock->p) { |
727 | bestppm = 0; |
817 | bestppm = 0; |
728 | *best_clock = clock; |
818 | *best_clock = clock; |
729 | found = true; |
819 | found = true; |
730 | } |
820 | } |
731 | 821 | ||
732 | if (bestppm >= 10 && ppm < bestppm - 10) { |
822 | if (bestppm >= 10 && ppm < bestppm - 10) { |
733 | bestppm = ppm; |
823 | bestppm = ppm; |
734 | *best_clock = clock; |
824 | *best_clock = clock; |
735 | found = true; |
825 | found = true; |
736 | } |
826 | } |
737 | } |
827 | } |
738 | } |
828 | } |
739 | } |
829 | } |
740 | } |
830 | } |
741 | 831 | ||
742 | return found; |
832 | return found; |
743 | } |
833 | } |
- | 834 | ||
- | 835 | static bool |
|
- | 836 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
|
- | 837 | int target, int refclk, intel_clock_t *match_clock, |
|
- | 838 | intel_clock_t *best_clock) |
|
- | 839 | { |
|
- | 840 | struct drm_device *dev = crtc->dev; |
|
- | 841 | intel_clock_t clock; |
|
- | 842 | uint64_t m2; |
|
- | 843 | int found = false; |
|
- | 844 | ||
- | 845 | memset(best_clock, 0, sizeof(*best_clock)); |
|
- | 846 | ||
- | 847 | /* |
|
- | 848 | * Based on hardware doc, the n always set to 1, and m1 always |
|
- | 849 | * set to 2. If requires to support 200Mhz refclk, we need to |
|
- | 850 | * revisit this because n may not 1 anymore. |
|
- | 851 | */ |
|
- | 852 | clock.n = 1, clock.m1 = 2; |
|
- | 853 | target *= 5; /* fast clock */ |
|
- | 854 | ||
- | 855 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
|
- | 856 | for (clock.p2 = limit->p2.p2_fast; |
|
- | 857 | clock.p2 >= limit->p2.p2_slow; |
|
- | 858 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
|
- | 859 | ||
- | 860 | clock.p = clock.p1 * clock.p2; |
|
- | 861 | ||
- | 862 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
|
- | 863 | clock.n) << 22, refclk * clock.m1); |
|
- | 864 | ||
- | 865 | if (m2 > INT_MAX/clock.m1) |
|
- | 866 | continue; |
|
- | 867 | ||
- | 868 | clock.m2 = m2; |
|
- | 869 | ||
- | 870 | chv_clock(refclk, &clock); |
|
- | 871 | ||
- | 872 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
|
- | 873 | continue; |
|
- | 874 | ||
- | 875 | /* based on hardware requirement, prefer bigger p |
|
- | 876 | */ |
|
- | 877 | if (clock.p > best_clock->p) { |
|
- | 878 | *best_clock = clock; |
|
- | 879 | found = true; |
|
- | 880 | } |
|
- | 881 | } |
|
- | 882 | } |
|
- | 883 | ||
- | 884 | return found; |
|
- | 885 | } |
|
744 | 886 | ||
745 | bool intel_crtc_active(struct drm_crtc *crtc) |
887 | bool intel_crtc_active(struct drm_crtc *crtc) |
746 | { |
888 | { |
747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
748 | 890 | ||
749 | /* Be paranoid as we can arrive here with only partial |
891 | /* Be paranoid as we can arrive here with only partial |
750 | * state retrieved from the hardware during setup. |
892 | * state retrieved from the hardware during setup. |
751 | * |
893 | * |
752 | * We can ditch the adjusted_mode.crtc_clock check as soon |
894 | * We can ditch the adjusted_mode.crtc_clock check as soon |
753 | * as Haswell has gained clock readout/fastboot support. |
895 | * as Haswell has gained clock readout/fastboot support. |
754 | * |
896 | * |
755 | * We can ditch the crtc->fb check as soon as we can |
897 | * We can ditch the crtc->primary->fb check as soon as we can |
756 | * properly reconstruct framebuffers. |
898 | * properly reconstruct framebuffers. |
757 | */ |
899 | */ |
758 | return intel_crtc->active && crtc->fb && |
900 | return intel_crtc->active && crtc->primary->fb && |
759 | intel_crtc->config.adjusted_mode.crtc_clock; |
901 | intel_crtc->config.adjusted_mode.crtc_clock; |
760 | } |
902 | } |
761 | 903 | ||
762 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
904 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
763 | enum pipe pipe) |
905 | enum pipe pipe) |
764 | { |
906 | { |
765 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
907 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
767 | 909 | ||
768 | return intel_crtc->config.cpu_transcoder; |
910 | return intel_crtc->config.cpu_transcoder; |
769 | } |
911 | } |
770 | 912 | ||
771 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
913 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
772 | { |
914 | { |
773 | struct drm_i915_private *dev_priv = dev->dev_private; |
915 | struct drm_i915_private *dev_priv = dev->dev_private; |
774 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
916 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
775 | 917 | ||
776 | frame = I915_READ(frame_reg); |
918 | frame = I915_READ(frame_reg); |
777 | 919 | ||
778 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
920 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
779 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
921 | WARN(1, "vblank wait timed out\n"); |
780 | } |
922 | } |
781 | 923 | ||
782 | /** |
924 | /** |
783 | * intel_wait_for_vblank - wait for vblank on a given pipe |
925 | * intel_wait_for_vblank - wait for vblank on a given pipe |
784 | * @dev: drm device |
926 | * @dev: drm device |
785 | * @pipe: pipe to wait for |
927 | * @pipe: pipe to wait for |
786 | * |
928 | * |
787 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
929 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
788 | * mode setting code. |
930 | * mode setting code. |
789 | */ |
931 | */ |
790 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
932 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
791 | { |
933 | { |
792 | struct drm_i915_private *dev_priv = dev->dev_private; |
934 | struct drm_i915_private *dev_priv = dev->dev_private; |
793 | int pipestat_reg = PIPESTAT(pipe); |
935 | int pipestat_reg = PIPESTAT(pipe); |
794 | 936 | ||
795 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
937 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
796 | g4x_wait_for_vblank(dev, pipe); |
938 | g4x_wait_for_vblank(dev, pipe); |
797 | return; |
939 | return; |
798 | } |
940 | } |
799 | 941 | ||
800 | /* Clear existing vblank status. Note this will clear any other |
942 | /* Clear existing vblank status. Note this will clear any other |
801 | * sticky status fields as well. |
943 | * sticky status fields as well. |
802 | * |
944 | * |
803 | * This races with i915_driver_irq_handler() with the result |
945 | * This races with i915_driver_irq_handler() with the result |
804 | * that either function could miss a vblank event. Here it is not |
946 | * that either function could miss a vblank event. Here it is not |
805 | * fatal, as we will either wait upon the next vblank interrupt or |
947 | * fatal, as we will either wait upon the next vblank interrupt or |
806 | * timeout. Generally speaking intel_wait_for_vblank() is only |
948 | * timeout. Generally speaking intel_wait_for_vblank() is only |
807 | * called during modeset at which time the GPU should be idle and |
949 | * called during modeset at which time the GPU should be idle and |
808 | * should *not* be performing page flips and thus not waiting on |
950 | * should *not* be performing page flips and thus not waiting on |
809 | * vblanks... |
951 | * vblanks... |
810 | * Currently, the result of us stealing a vblank from the irq |
952 | * Currently, the result of us stealing a vblank from the irq |
811 | * handler is that a single frame will be skipped during swapbuffers. |
953 | * handler is that a single frame will be skipped during swapbuffers. |
812 | */ |
954 | */ |
813 | I915_WRITE(pipestat_reg, |
955 | I915_WRITE(pipestat_reg, |
814 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
956 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
815 | 957 | ||
816 | /* Wait for vblank interrupt bit to set */ |
958 | /* Wait for vblank interrupt bit to set */ |
817 | if (wait_for(I915_READ(pipestat_reg) & |
959 | if (wait_for(I915_READ(pipestat_reg) & |
818 | PIPE_VBLANK_INTERRUPT_STATUS, |
960 | PIPE_VBLANK_INTERRUPT_STATUS, |
819 | 50)) |
961 | 50)) |
820 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
962 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
821 | } |
963 | } |
822 | 964 | ||
823 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
965 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
824 | { |
966 | { |
825 | struct drm_i915_private *dev_priv = dev->dev_private; |
967 | struct drm_i915_private *dev_priv = dev->dev_private; |
826 | u32 reg = PIPEDSL(pipe); |
968 | u32 reg = PIPEDSL(pipe); |
827 | u32 line1, line2; |
969 | u32 line1, line2; |
828 | u32 line_mask; |
970 | u32 line_mask; |
829 | 971 | ||
830 | if (IS_GEN2(dev)) |
972 | if (IS_GEN2(dev)) |
831 | line_mask = DSL_LINEMASK_GEN2; |
973 | line_mask = DSL_LINEMASK_GEN2; |
832 | else |
974 | else |
833 | line_mask = DSL_LINEMASK_GEN3; |
975 | line_mask = DSL_LINEMASK_GEN3; |
834 | 976 | ||
835 | line1 = I915_READ(reg) & line_mask; |
977 | line1 = I915_READ(reg) & line_mask; |
836 | mdelay(5); |
978 | mdelay(5); |
837 | line2 = I915_READ(reg) & line_mask; |
979 | line2 = I915_READ(reg) & line_mask; |
838 | 980 | ||
839 | return line1 == line2; |
981 | return line1 == line2; |
840 | } |
982 | } |
841 | 983 | ||
842 | /* |
984 | /* |
843 | * intel_wait_for_pipe_off - wait for pipe to turn off |
985 | * intel_wait_for_pipe_off - wait for pipe to turn off |
844 | * @dev: drm device |
986 | * @dev: drm device |
845 | * @pipe: pipe to wait for |
987 | * @pipe: pipe to wait for |
846 | * |
988 | * |
847 | * After disabling a pipe, we can't wait for vblank in the usual way, |
989 | * After disabling a pipe, we can't wait for vblank in the usual way, |
848 | * spinning on the vblank interrupt status bit, since we won't actually |
990 | * spinning on the vblank interrupt status bit, since we won't actually |
849 | * see an interrupt when the pipe is disabled. |
991 | * see an interrupt when the pipe is disabled. |
850 | * |
992 | * |
851 | * On Gen4 and above: |
993 | * On Gen4 and above: |
852 | * wait for the pipe register state bit to turn off |
994 | * wait for the pipe register state bit to turn off |
853 | * |
995 | * |
854 | * Otherwise: |
996 | * Otherwise: |
855 | * wait for the display line value to settle (it usually |
997 | * wait for the display line value to settle (it usually |
856 | * ends up stopping at the start of the next frame). |
998 | * ends up stopping at the start of the next frame). |
857 | * |
999 | * |
858 | */ |
1000 | */ |
859 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
1001 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
860 | { |
1002 | { |
861 | struct drm_i915_private *dev_priv = dev->dev_private; |
1003 | struct drm_i915_private *dev_priv = dev->dev_private; |
862 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1004 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
863 | pipe); |
1005 | pipe); |
864 | 1006 | ||
865 | if (INTEL_INFO(dev)->gen >= 4) { |
1007 | if (INTEL_INFO(dev)->gen >= 4) { |
866 | int reg = PIPECONF(cpu_transcoder); |
1008 | int reg = PIPECONF(cpu_transcoder); |
867 | 1009 | ||
868 | /* Wait for the Pipe State to go off */ |
1010 | /* Wait for the Pipe State to go off */ |
869 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1011 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
870 | 100)) |
1012 | 100)) |
871 | WARN(1, "pipe_off wait timed out\n"); |
1013 | WARN(1, "pipe_off wait timed out\n"); |
872 | } else { |
1014 | } else { |
873 | /* Wait for the display line to settle */ |
1015 | /* Wait for the display line to settle */ |
874 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
1016 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
875 | WARN(1, "pipe_off wait timed out\n"); |
1017 | WARN(1, "pipe_off wait timed out\n"); |
876 | } |
1018 | } |
877 | } |
1019 | } |
878 | 1020 | ||
879 | /* |
1021 | /* |
880 | * ibx_digital_port_connected - is the specified port connected? |
1022 | * ibx_digital_port_connected - is the specified port connected? |
881 | * @dev_priv: i915 private structure |
1023 | * @dev_priv: i915 private structure |
882 | * @port: the port to test |
1024 | * @port: the port to test |
883 | * |
1025 | * |
884 | * Returns true if @port is connected, false otherwise. |
1026 | * Returns true if @port is connected, false otherwise. |
885 | */ |
1027 | */ |
886 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
1028 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
887 | struct intel_digital_port *port) |
1029 | struct intel_digital_port *port) |
888 | { |
1030 | { |
889 | u32 bit; |
1031 | u32 bit; |
890 | 1032 | ||
891 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1033 | if (HAS_PCH_IBX(dev_priv->dev)) { |
892 | switch(port->port) { |
1034 | switch (port->port) { |
893 | case PORT_B: |
1035 | case PORT_B: |
894 | bit = SDE_PORTB_HOTPLUG; |
1036 | bit = SDE_PORTB_HOTPLUG; |
895 | break; |
1037 | break; |
896 | case PORT_C: |
1038 | case PORT_C: |
897 | bit = SDE_PORTC_HOTPLUG; |
1039 | bit = SDE_PORTC_HOTPLUG; |
898 | break; |
1040 | break; |
899 | case PORT_D: |
1041 | case PORT_D: |
900 | bit = SDE_PORTD_HOTPLUG; |
1042 | bit = SDE_PORTD_HOTPLUG; |
901 | break; |
1043 | break; |
902 | default: |
1044 | default: |
903 | return true; |
1045 | return true; |
904 | } |
1046 | } |
905 | } else { |
1047 | } else { |
906 | switch(port->port) { |
1048 | switch (port->port) { |
907 | case PORT_B: |
1049 | case PORT_B: |
908 | bit = SDE_PORTB_HOTPLUG_CPT; |
1050 | bit = SDE_PORTB_HOTPLUG_CPT; |
909 | break; |
1051 | break; |
910 | case PORT_C: |
1052 | case PORT_C: |
911 | bit = SDE_PORTC_HOTPLUG_CPT; |
1053 | bit = SDE_PORTC_HOTPLUG_CPT; |
912 | break; |
1054 | break; |
913 | case PORT_D: |
1055 | case PORT_D: |
914 | bit = SDE_PORTD_HOTPLUG_CPT; |
1056 | bit = SDE_PORTD_HOTPLUG_CPT; |
915 | break; |
1057 | break; |
916 | default: |
1058 | default: |
917 | return true; |
1059 | return true; |
918 | } |
1060 | } |
919 | } |
1061 | } |
920 | 1062 | ||
921 | return I915_READ(SDEISR) & bit; |
1063 | return I915_READ(SDEISR) & bit; |
922 | } |
1064 | } |
923 | 1065 | ||
924 | static const char *state_string(bool enabled) |
1066 | static const char *state_string(bool enabled) |
925 | { |
1067 | { |
926 | return enabled ? "on" : "off"; |
1068 | return enabled ? "on" : "off"; |
927 | } |
1069 | } |
928 | 1070 | ||
929 | /* Only for pre-ILK configs */ |
1071 | /* Only for pre-ILK configs */ |
930 | void assert_pll(struct drm_i915_private *dev_priv, |
1072 | void assert_pll(struct drm_i915_private *dev_priv, |
931 | enum pipe pipe, bool state) |
1073 | enum pipe pipe, bool state) |
932 | { |
1074 | { |
933 | int reg; |
1075 | int reg; |
934 | u32 val; |
1076 | u32 val; |
935 | bool cur_state; |
1077 | bool cur_state; |
936 | 1078 | ||
937 | reg = DPLL(pipe); |
1079 | reg = DPLL(pipe); |
938 | val = I915_READ(reg); |
1080 | val = I915_READ(reg); |
939 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1081 | cur_state = !!(val & DPLL_VCO_ENABLE); |
940 | WARN(cur_state != state, |
1082 | WARN(cur_state != state, |
941 | "PLL state assertion failure (expected %s, current %s)\n", |
1083 | "PLL state assertion failure (expected %s, current %s)\n", |
942 | state_string(state), state_string(cur_state)); |
1084 | state_string(state), state_string(cur_state)); |
943 | } |
1085 | } |
944 | 1086 | ||
945 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1087 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
946 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
1088 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
947 | { |
1089 | { |
948 | u32 val; |
1090 | u32 val; |
949 | bool cur_state; |
1091 | bool cur_state; |
950 | 1092 | ||
951 | mutex_lock(&dev_priv->dpio_lock); |
1093 | mutex_lock(&dev_priv->dpio_lock); |
952 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
1094 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
953 | mutex_unlock(&dev_priv->dpio_lock); |
1095 | mutex_unlock(&dev_priv->dpio_lock); |
954 | 1096 | ||
955 | cur_state = val & DSI_PLL_VCO_EN; |
1097 | cur_state = val & DSI_PLL_VCO_EN; |
956 | WARN(cur_state != state, |
1098 | WARN(cur_state != state, |
957 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1099 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
958 | state_string(state), state_string(cur_state)); |
1100 | state_string(state), state_string(cur_state)); |
959 | } |
1101 | } |
960 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
1102 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
961 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
1103 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
962 | 1104 | ||
963 | struct intel_shared_dpll * |
1105 | struct intel_shared_dpll * |
964 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1106 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
965 | { |
1107 | { |
966 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1108 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
967 | 1109 | ||
968 | if (crtc->config.shared_dpll < 0) |
1110 | if (crtc->config.shared_dpll < 0) |
969 | return NULL; |
1111 | return NULL; |
970 | 1112 | ||
971 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
1113 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
972 | } |
1114 | } |
973 | 1115 | ||
974 | /* For ILK+ */ |
1116 | /* For ILK+ */ |
975 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1117 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
976 | struct intel_shared_dpll *pll, |
1118 | struct intel_shared_dpll *pll, |
977 | bool state) |
1119 | bool state) |
978 | { |
1120 | { |
979 | bool cur_state; |
1121 | bool cur_state; |
980 | struct intel_dpll_hw_state hw_state; |
1122 | struct intel_dpll_hw_state hw_state; |
981 | - | ||
982 | if (HAS_PCH_LPT(dev_priv->dev)) { |
- | |
983 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
- | |
984 | return; |
- | |
985 | } |
- | |
986 | 1123 | ||
987 | if (WARN (!pll, |
1124 | if (WARN (!pll, |
988 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
1125 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
989 | return; |
1126 | return; |
990 | 1127 | ||
991 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
1128 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
992 | WARN(cur_state != state, |
1129 | WARN(cur_state != state, |
993 | "%s assertion failure (expected %s, current %s)\n", |
1130 | "%s assertion failure (expected %s, current %s)\n", |
994 | pll->name, state_string(state), state_string(cur_state)); |
1131 | pll->name, state_string(state), state_string(cur_state)); |
995 | } |
1132 | } |
996 | 1133 | ||
997 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1134 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
998 | enum pipe pipe, bool state) |
1135 | enum pipe pipe, bool state) |
999 | { |
1136 | { |
1000 | int reg; |
1137 | int reg; |
1001 | u32 val; |
1138 | u32 val; |
1002 | bool cur_state; |
1139 | bool cur_state; |
1003 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1140 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1004 | pipe); |
1141 | pipe); |
1005 | 1142 | ||
1006 | if (HAS_DDI(dev_priv->dev)) { |
1143 | if (HAS_DDI(dev_priv->dev)) { |
1007 | /* DDI does not have a specific FDI_TX register */ |
1144 | /* DDI does not have a specific FDI_TX register */ |
1008 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1145 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1009 | val = I915_READ(reg); |
1146 | val = I915_READ(reg); |
1010 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
1147 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
1011 | } else { |
1148 | } else { |
1012 | reg = FDI_TX_CTL(pipe); |
1149 | reg = FDI_TX_CTL(pipe); |
1013 | val = I915_READ(reg); |
1150 | val = I915_READ(reg); |
1014 | cur_state = !!(val & FDI_TX_ENABLE); |
1151 | cur_state = !!(val & FDI_TX_ENABLE); |
1015 | } |
1152 | } |
1016 | WARN(cur_state != state, |
1153 | WARN(cur_state != state, |
1017 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1154 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1018 | state_string(state), state_string(cur_state)); |
1155 | state_string(state), state_string(cur_state)); |
1019 | } |
1156 | } |
1020 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1157 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1021 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1158 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1022 | 1159 | ||
1023 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
1160 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
1024 | enum pipe pipe, bool state) |
1161 | enum pipe pipe, bool state) |
1025 | { |
1162 | { |
1026 | int reg; |
1163 | int reg; |
1027 | u32 val; |
1164 | u32 val; |
1028 | bool cur_state; |
1165 | bool cur_state; |
1029 | 1166 | ||
1030 | reg = FDI_RX_CTL(pipe); |
1167 | reg = FDI_RX_CTL(pipe); |
1031 | val = I915_READ(reg); |
1168 | val = I915_READ(reg); |
1032 | cur_state = !!(val & FDI_RX_ENABLE); |
1169 | cur_state = !!(val & FDI_RX_ENABLE); |
1033 | WARN(cur_state != state, |
1170 | WARN(cur_state != state, |
1034 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1171 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1035 | state_string(state), state_string(cur_state)); |
1172 | state_string(state), state_string(cur_state)); |
1036 | } |
1173 | } |
1037 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1174 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1038 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1175 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1039 | 1176 | ||
1040 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1177 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1041 | enum pipe pipe) |
1178 | enum pipe pipe) |
1042 | { |
1179 | { |
1043 | int reg; |
1180 | int reg; |
1044 | u32 val; |
1181 | u32 val; |
1045 | 1182 | ||
1046 | /* ILK FDI PLL is always enabled */ |
1183 | /* ILK FDI PLL is always enabled */ |
1047 | if (dev_priv->info->gen == 5) |
1184 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
1048 | return; |
1185 | return; |
1049 | 1186 | ||
1050 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1187 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1051 | if (HAS_DDI(dev_priv->dev)) |
1188 | if (HAS_DDI(dev_priv->dev)) |
1052 | return; |
1189 | return; |
1053 | 1190 | ||
1054 | reg = FDI_TX_CTL(pipe); |
1191 | reg = FDI_TX_CTL(pipe); |
1055 | val = I915_READ(reg); |
1192 | val = I915_READ(reg); |
1056 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1193 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1057 | } |
1194 | } |
1058 | 1195 | ||
1059 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1196 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) |
1197 | enum pipe pipe, bool state) |
1061 | { |
1198 | { |
1062 | int reg; |
1199 | int reg; |
1063 | u32 val; |
1200 | u32 val; |
1064 | bool cur_state; |
1201 | bool cur_state; |
1065 | 1202 | ||
1066 | reg = FDI_RX_CTL(pipe); |
1203 | reg = FDI_RX_CTL(pipe); |
1067 | val = I915_READ(reg); |
1204 | val = I915_READ(reg); |
1068 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1205 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1069 | WARN(cur_state != state, |
1206 | WARN(cur_state != state, |
1070 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1207 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1071 | state_string(state), state_string(cur_state)); |
1208 | state_string(state), state_string(cur_state)); |
1072 | } |
1209 | } |
1073 | 1210 | ||
1074 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1211 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1075 | enum pipe pipe) |
1212 | enum pipe pipe) |
1076 | { |
1213 | { |
1077 | int pp_reg, lvds_reg; |
1214 | int pp_reg, lvds_reg; |
1078 | u32 val; |
1215 | u32 val; |
1079 | enum pipe panel_pipe = PIPE_A; |
1216 | enum pipe panel_pipe = PIPE_A; |
1080 | bool locked = true; |
1217 | bool locked = true; |
1081 | 1218 | ||
1082 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1219 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1083 | pp_reg = PCH_PP_CONTROL; |
1220 | pp_reg = PCH_PP_CONTROL; |
1084 | lvds_reg = PCH_LVDS; |
1221 | lvds_reg = PCH_LVDS; |
1085 | } else { |
1222 | } else { |
1086 | pp_reg = PP_CONTROL; |
1223 | pp_reg = PP_CONTROL; |
1087 | lvds_reg = LVDS; |
1224 | lvds_reg = LVDS; |
1088 | } |
1225 | } |
1089 | 1226 | ||
1090 | val = I915_READ(pp_reg); |
1227 | val = I915_READ(pp_reg); |
1091 | if (!(val & PANEL_POWER_ON) || |
1228 | if (!(val & PANEL_POWER_ON) || |
1092 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1229 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1093 | locked = false; |
1230 | locked = false; |
1094 | 1231 | ||
1095 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1232 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1096 | panel_pipe = PIPE_B; |
1233 | panel_pipe = PIPE_B; |
1097 | 1234 | ||
1098 | WARN(panel_pipe == pipe && locked, |
1235 | WARN(panel_pipe == pipe && locked, |
1099 | "panel assertion failure, pipe %c regs locked\n", |
1236 | "panel assertion failure, pipe %c regs locked\n", |
1100 | pipe_name(pipe)); |
1237 | pipe_name(pipe)); |
1101 | } |
1238 | } |
1102 | 1239 | ||
1103 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1240 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1104 | enum pipe pipe, bool state) |
1241 | enum pipe pipe, bool state) |
1105 | { |
1242 | { |
1106 | struct drm_device *dev = dev_priv->dev; |
1243 | struct drm_device *dev = dev_priv->dev; |
1107 | bool cur_state; |
1244 | bool cur_state; |
1108 | - | ||
1109 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
- | |
1110 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; |
1245 | |
1111 | else if (IS_845G(dev) || IS_I865G(dev)) |
1246 | if (IS_845G(dev) || IS_I865G(dev)) |
1112 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
1247 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
1113 | else |
1248 | else |
1114 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
1249 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
1115 | 1250 | ||
1116 | WARN(cur_state != state, |
1251 | WARN(cur_state != state, |
1117 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1252 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1118 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1253 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1119 | } |
1254 | } |
1120 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
1255 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
1121 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
1256 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
1122 | 1257 | ||
1123 | void assert_pipe(struct drm_i915_private *dev_priv, |
1258 | void assert_pipe(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) |
1259 | enum pipe pipe, bool state) |
1125 | { |
1260 | { |
1126 | int reg; |
1261 | int reg; |
1127 | u32 val; |
1262 | u32 val; |
1128 | bool cur_state; |
1263 | bool cur_state; |
1129 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1264 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1130 | pipe); |
1265 | pipe); |
1131 | 1266 | ||
1132 | /* if we need the pipe A quirk it must be always on */ |
1267 | /* if we need the pipe A quirk it must be always on */ |
1133 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1268 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1134 | state = true; |
1269 | state = true; |
1135 | 1270 | ||
1136 | if (!intel_display_power_enabled(dev_priv->dev, |
1271 | if (!intel_display_power_enabled(dev_priv, |
1137 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1272 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1138 | cur_state = false; |
1273 | cur_state = false; |
1139 | } else { |
1274 | } else { |
1140 | reg = PIPECONF(cpu_transcoder); |
1275 | reg = PIPECONF(cpu_transcoder); |
1141 | val = I915_READ(reg); |
1276 | val = I915_READ(reg); |
1142 | cur_state = !!(val & PIPECONF_ENABLE); |
1277 | cur_state = !!(val & PIPECONF_ENABLE); |
1143 | } |
1278 | } |
1144 | 1279 | ||
1145 | WARN(cur_state != state, |
1280 | WARN(cur_state != state, |
1146 | "pipe %c assertion failure (expected %s, current %s)\n", |
1281 | "pipe %c assertion failure (expected %s, current %s)\n", |
1147 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1282 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1148 | } |
1283 | } |
1149 | 1284 | ||
1150 | static void assert_plane(struct drm_i915_private *dev_priv, |
1285 | static void assert_plane(struct drm_i915_private *dev_priv, |
1151 | enum plane plane, bool state) |
1286 | enum plane plane, bool state) |
1152 | { |
1287 | { |
1153 | int reg; |
1288 | int reg; |
1154 | u32 val; |
1289 | u32 val; |
1155 | bool cur_state; |
1290 | bool cur_state; |
1156 | 1291 | ||
1157 | reg = DSPCNTR(plane); |
1292 | reg = DSPCNTR(plane); |
1158 | val = I915_READ(reg); |
1293 | val = I915_READ(reg); |
1159 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1294 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1160 | WARN(cur_state != state, |
1295 | WARN(cur_state != state, |
1161 | "plane %c assertion failure (expected %s, current %s)\n", |
1296 | "plane %c assertion failure (expected %s, current %s)\n", |
1162 | plane_name(plane), state_string(state), state_string(cur_state)); |
1297 | plane_name(plane), state_string(state), state_string(cur_state)); |
1163 | } |
1298 | } |
1164 | 1299 | ||
1165 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1300 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1166 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1301 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1167 | 1302 | ||
1168 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1303 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1169 | enum pipe pipe) |
1304 | enum pipe pipe) |
1170 | { |
1305 | { |
1171 | struct drm_device *dev = dev_priv->dev; |
1306 | struct drm_device *dev = dev_priv->dev; |
1172 | int reg, i; |
1307 | int reg, i; |
1173 | u32 val; |
1308 | u32 val; |
1174 | int cur_pipe; |
1309 | int cur_pipe; |
1175 | 1310 | ||
1176 | /* Primary planes are fixed to pipes on gen4+ */ |
1311 | /* Primary planes are fixed to pipes on gen4+ */ |
1177 | if (INTEL_INFO(dev)->gen >= 4) { |
1312 | if (INTEL_INFO(dev)->gen >= 4) { |
1178 | reg = DSPCNTR(pipe); |
1313 | reg = DSPCNTR(pipe); |
1179 | val = I915_READ(reg); |
1314 | val = I915_READ(reg); |
1180 | WARN((val & DISPLAY_PLANE_ENABLE), |
1315 | WARN(val & DISPLAY_PLANE_ENABLE, |
1181 | "plane %c assertion failure, should be disabled but not\n", |
1316 | "plane %c assertion failure, should be disabled but not\n", |
1182 | plane_name(pipe)); |
1317 | plane_name(pipe)); |
1183 | return; |
1318 | return; |
1184 | } |
1319 | } |
1185 | 1320 | ||
1186 | /* Need to check both planes against the pipe */ |
1321 | /* Need to check both planes against the pipe */ |
1187 | for_each_pipe(i) { |
1322 | for_each_pipe(i) { |
1188 | reg = DSPCNTR(i); |
1323 | reg = DSPCNTR(i); |
1189 | val = I915_READ(reg); |
1324 | val = I915_READ(reg); |
1190 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1325 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1191 | DISPPLANE_SEL_PIPE_SHIFT; |
1326 | DISPPLANE_SEL_PIPE_SHIFT; |
1192 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1327 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1193 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1328 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1194 | plane_name(i), pipe_name(pipe)); |
1329 | plane_name(i), pipe_name(pipe)); |
1195 | } |
1330 | } |
1196 | } |
1331 | } |
1197 | 1332 | ||
1198 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1333 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1199 | enum pipe pipe) |
1334 | enum pipe pipe) |
1200 | { |
1335 | { |
1201 | struct drm_device *dev = dev_priv->dev; |
1336 | struct drm_device *dev = dev_priv->dev; |
1202 | int reg, i; |
1337 | int reg, sprite; |
1203 | u32 val; |
1338 | u32 val; |
1204 | 1339 | ||
1205 | if (IS_VALLEYVIEW(dev)) { |
1340 | if (IS_VALLEYVIEW(dev)) { |
1206 | for (i = 0; i < dev_priv->num_plane; i++) { |
1341 | for_each_sprite(pipe, sprite) { |
1207 | reg = SPCNTR(pipe, i); |
1342 | reg = SPCNTR(pipe, sprite); |
1208 | val = I915_READ(reg); |
1343 | val = I915_READ(reg); |
1209 | WARN((val & SP_ENABLE), |
1344 | WARN(val & SP_ENABLE, |
1210 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1345 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1211 | sprite_name(pipe, i), pipe_name(pipe)); |
1346 | sprite_name(pipe, sprite), pipe_name(pipe)); |
1212 | } |
1347 | } |
1213 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1348 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1214 | reg = SPRCTL(pipe); |
1349 | reg = SPRCTL(pipe); |
1215 | val = I915_READ(reg); |
1350 | val = I915_READ(reg); |
1216 | WARN((val & SPRITE_ENABLE), |
1351 | WARN(val & SPRITE_ENABLE, |
1217 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1352 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1218 | plane_name(pipe), pipe_name(pipe)); |
1353 | plane_name(pipe), pipe_name(pipe)); |
1219 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1354 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1220 | reg = DVSCNTR(pipe); |
1355 | reg = DVSCNTR(pipe); |
1221 | val = I915_READ(reg); |
1356 | val = I915_READ(reg); |
1222 | WARN((val & DVS_ENABLE), |
1357 | WARN(val & DVS_ENABLE, |
1223 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1358 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1224 | plane_name(pipe), pipe_name(pipe)); |
1359 | plane_name(pipe), pipe_name(pipe)); |
1225 | } |
1360 | } |
1226 | } |
1361 | } |
1227 | 1362 | ||
1228 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1363 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1229 | { |
1364 | { |
1230 | u32 val; |
1365 | u32 val; |
1231 | bool enabled; |
1366 | bool enabled; |
1232 | 1367 | ||
1233 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
1368 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
1234 | 1369 | ||
1235 | val = I915_READ(PCH_DREF_CONTROL); |
1370 | val = I915_READ(PCH_DREF_CONTROL); |
1236 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1371 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1237 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1372 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1238 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1373 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1239 | } |
1374 | } |
1240 | 1375 | ||
1241 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1376 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1242 | enum pipe pipe) |
1377 | enum pipe pipe) |
1243 | { |
1378 | { |
1244 | int reg; |
1379 | int reg; |
1245 | u32 val; |
1380 | u32 val; |
1246 | bool enabled; |
1381 | bool enabled; |
1247 | 1382 | ||
1248 | reg = PCH_TRANSCONF(pipe); |
1383 | reg = PCH_TRANSCONF(pipe); |
1249 | val = I915_READ(reg); |
1384 | val = I915_READ(reg); |
1250 | enabled = !!(val & TRANS_ENABLE); |
1385 | enabled = !!(val & TRANS_ENABLE); |
1251 | WARN(enabled, |
1386 | WARN(enabled, |
1252 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1387 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1253 | pipe_name(pipe)); |
1388 | pipe_name(pipe)); |
1254 | } |
1389 | } |
1255 | 1390 | ||
1256 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1391 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe, u32 port_sel, u32 val) |
1392 | enum pipe pipe, u32 port_sel, u32 val) |
1258 | { |
1393 | { |
1259 | if ((val & DP_PORT_EN) == 0) |
1394 | if ((val & DP_PORT_EN) == 0) |
1260 | return false; |
1395 | return false; |
1261 | 1396 | ||
1262 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1397 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1263 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1398 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1264 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1399 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1265 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1400 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1266 | return false; |
1401 | return false; |
- | 1402 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
|
- | 1403 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
|
- | 1404 | return false; |
|
1267 | } else { |
1405 | } else { |
1268 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1406 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1269 | return false; |
1407 | return false; |
1270 | } |
1408 | } |
1271 | return true; |
1409 | return true; |
1272 | } |
1410 | } |
1273 | 1411 | ||
1274 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1412 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1275 | enum pipe pipe, u32 val) |
1413 | enum pipe pipe, u32 val) |
1276 | { |
1414 | { |
1277 | if ((val & SDVO_ENABLE) == 0) |
1415 | if ((val & SDVO_ENABLE) == 0) |
1278 | return false; |
1416 | return false; |
1279 | 1417 | ||
1280 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1418 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1281 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1419 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1282 | return false; |
1420 | return false; |
- | 1421 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
|
- | 1422 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
|
- | 1423 | return false; |
|
1283 | } else { |
1424 | } else { |
1284 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1425 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1285 | return false; |
1426 | return false; |
1286 | } |
1427 | } |
1287 | return true; |
1428 | return true; |
1288 | } |
1429 | } |
1289 | 1430 | ||
1290 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1431 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1291 | enum pipe pipe, u32 val) |
1432 | enum pipe pipe, u32 val) |
1292 | { |
1433 | { |
1293 | if ((val & LVDS_PORT_EN) == 0) |
1434 | if ((val & LVDS_PORT_EN) == 0) |
1294 | return false; |
1435 | return false; |
1295 | 1436 | ||
1296 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1437 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1297 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1438 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1298 | return false; |
1439 | return false; |
1299 | } else { |
1440 | } else { |
1300 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1441 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1301 | return false; |
1442 | return false; |
1302 | } |
1443 | } |
1303 | return true; |
1444 | return true; |
1304 | } |
1445 | } |
1305 | 1446 | ||
1306 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1447 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1307 | enum pipe pipe, u32 val) |
1448 | enum pipe pipe, u32 val) |
1308 | { |
1449 | { |
1309 | if ((val & ADPA_DAC_ENABLE) == 0) |
1450 | if ((val & ADPA_DAC_ENABLE) == 0) |
1310 | return false; |
1451 | return false; |
1311 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1452 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1312 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1453 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1313 | return false; |
1454 | return false; |
1314 | } else { |
1455 | } else { |
1315 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1456 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1316 | return false; |
1457 | return false; |
1317 | } |
1458 | } |
1318 | return true; |
1459 | return true; |
1319 | } |
1460 | } |
1320 | 1461 | ||
1321 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1462 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe, int reg, u32 port_sel) |
1463 | enum pipe pipe, int reg, u32 port_sel) |
1323 | { |
1464 | { |
1324 | u32 val = I915_READ(reg); |
1465 | u32 val = I915_READ(reg); |
1325 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1466 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1326 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1467 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1327 | reg, pipe_name(pipe)); |
1468 | reg, pipe_name(pipe)); |
1328 | 1469 | ||
1329 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1470 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1330 | && (val & DP_PIPEB_SELECT), |
1471 | && (val & DP_PIPEB_SELECT), |
1331 | "IBX PCH dp port still using transcoder B\n"); |
1472 | "IBX PCH dp port still using transcoder B\n"); |
1332 | } |
1473 | } |
1333 | 1474 | ||
1334 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1475 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1335 | enum pipe pipe, int reg) |
1476 | enum pipe pipe, int reg) |
1336 | { |
1477 | { |
1337 | u32 val = I915_READ(reg); |
1478 | u32 val = I915_READ(reg); |
1338 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1479 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1339 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1480 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1340 | reg, pipe_name(pipe)); |
1481 | reg, pipe_name(pipe)); |
1341 | 1482 | ||
1342 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1483 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1343 | && (val & SDVO_PIPE_B_SELECT), |
1484 | && (val & SDVO_PIPE_B_SELECT), |
1344 | "IBX PCH hdmi port still using transcoder B\n"); |
1485 | "IBX PCH hdmi port still using transcoder B\n"); |
1345 | } |
1486 | } |
1346 | 1487 | ||
1347 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1488 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1348 | enum pipe pipe) |
1489 | enum pipe pipe) |
1349 | { |
1490 | { |
1350 | int reg; |
1491 | int reg; |
1351 | u32 val; |
1492 | u32 val; |
1352 | 1493 | ||
1353 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1494 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1354 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1495 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1355 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1496 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1356 | 1497 | ||
1357 | reg = PCH_ADPA; |
1498 | reg = PCH_ADPA; |
1358 | val = I915_READ(reg); |
1499 | val = I915_READ(reg); |
1359 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1500 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1360 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1501 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1361 | pipe_name(pipe)); |
1502 | pipe_name(pipe)); |
1362 | 1503 | ||
1363 | reg = PCH_LVDS; |
1504 | reg = PCH_LVDS; |
1364 | val = I915_READ(reg); |
1505 | val = I915_READ(reg); |
1365 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1506 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1366 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1507 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1367 | pipe_name(pipe)); |
1508 | pipe_name(pipe)); |
1368 | 1509 | ||
1369 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1510 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1370 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1511 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1371 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1512 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1372 | } |
1513 | } |
1373 | 1514 | ||
1374 | static void intel_init_dpio(struct drm_device *dev) |
1515 | static void intel_init_dpio(struct drm_device *dev) |
1375 | { |
1516 | { |
1376 | struct drm_i915_private *dev_priv = dev->dev_private; |
1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
1377 | 1518 | ||
1378 | if (!IS_VALLEYVIEW(dev)) |
1519 | if (!IS_VALLEYVIEW(dev)) |
1379 | return; |
1520 | return; |
- | 1521 | ||
- | 1522 | /* |
|
- | 1523 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), |
|
- | 1524 | * CHV x1 PHY (DP/HDMI D) |
|
- | 1525 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) |
|
- | 1526 | */ |
|
- | 1527 | if (IS_CHERRYVIEW(dev)) { |
|
- | 1528 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; |
|
- | 1529 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; |
|
1380 | 1530 | } else { |
|
1381 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
1531 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
- | 1532 | } |
|
1382 | } |
1533 | } |
1383 | 1534 | ||
1384 | static void intel_reset_dpio(struct drm_device *dev) |
1535 | static void intel_reset_dpio(struct drm_device *dev) |
1385 | { |
1536 | { |
1386 | struct drm_i915_private *dev_priv = dev->dev_private; |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
1387 | 1538 | ||
- | 1539 | if (IS_CHERRYVIEW(dev)) { |
|
1388 | if (!IS_VALLEYVIEW(dev)) |
1540 | enum dpio_phy phy; |
1389 | return; |
- | |
1390 | 1541 | u32 val; |
|
1391 | /* |
1542 | |
1392 | * Enable the CRI clock source so we can get at the display and the |
- | |
1393 | * reference clock for VGA hotplug / manual detection. |
1543 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { |
1394 | */ |
1544 | /* Poll for phypwrgood signal */ |
1395 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
1545 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & |
1396 | DPLL_REFA_CLK_ENABLE_VLV | |
1546 | PHY_POWERGOOD(phy), 1)) |
1397 | DPLL_INTEGRATED_CRI_CLK_VLV); |
- | |
1398 | 1547 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
|
1399 | /* |
- | |
1400 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
- | |
1401 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
- | |
1402 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
1548 | |
1403 | * b. The other bits such as sfr settings / modesel may all be set |
1549 | /* |
1404 | * to 0. |
1550 | * Deassert common lane reset for PHY. |
- | 1551 | * |
|
1405 | * |
1552 | * This should only be done on init and resume from S3 |
1406 | * This should only be done on init and resume from S3 with both |
1553 | * with both PLLs disabled, or we risk losing DPIO and |
- | 1554 | * PLL synchronization. |
|
- | 1555 | */ |
|
- | 1556 | val = I915_READ(DISPLAY_PHY_CONTROL); |
|
- | 1557 | I915_WRITE(DISPLAY_PHY_CONTROL, |
|
1407 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. |
1558 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); |
1408 | */ |
1559 | } |
1409 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
1560 | } |
1410 | } |
1561 | } |
1411 | 1562 | ||
1412 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1563 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1413 | { |
1564 | { |
1414 | struct drm_device *dev = crtc->base.dev; |
1565 | struct drm_device *dev = crtc->base.dev; |
1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
1416 | int reg = DPLL(crtc->pipe); |
1567 | int reg = DPLL(crtc->pipe); |
1417 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1568 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1418 | 1569 | ||
1419 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1570 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1420 | 1571 | ||
1421 | /* No really, not for ILK+ */ |
1572 | /* No really, not for ILK+ */ |
1422 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1573 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1423 | 1574 | ||
1424 | /* PLL is protected by panel, make sure we can write it */ |
1575 | /* PLL is protected by panel, make sure we can write it */ |
1425 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1576 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1426 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1577 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1427 | 1578 | ||
1428 | I915_WRITE(reg, dpll); |
1579 | I915_WRITE(reg, dpll); |
1429 | POSTING_READ(reg); |
1580 | POSTING_READ(reg); |
1430 | udelay(150); |
1581 | udelay(150); |
1431 | 1582 | ||
1432 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1583 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1433 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1584 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1434 | 1585 | ||
1435 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1586 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1436 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1587 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1437 | 1588 | ||
1438 | /* We do this three times for luck */ |
1589 | /* We do this three times for luck */ |
1439 | I915_WRITE(reg, dpll); |
1590 | I915_WRITE(reg, dpll); |
1440 | POSTING_READ(reg); |
1591 | POSTING_READ(reg); |
1441 | udelay(150); /* wait for warmup */ |
1592 | udelay(150); /* wait for warmup */ |
1442 | I915_WRITE(reg, dpll); |
1593 | I915_WRITE(reg, dpll); |
1443 | POSTING_READ(reg); |
1594 | POSTING_READ(reg); |
1444 | udelay(150); /* wait for warmup */ |
1595 | udelay(150); /* wait for warmup */ |
1445 | I915_WRITE(reg, dpll); |
1596 | I915_WRITE(reg, dpll); |
1446 | POSTING_READ(reg); |
1597 | POSTING_READ(reg); |
1447 | udelay(150); /* wait for warmup */ |
1598 | udelay(150); /* wait for warmup */ |
1448 | } |
1599 | } |
- | 1600 | ||
- | 1601 | static void chv_enable_pll(struct intel_crtc *crtc) |
|
- | 1602 | { |
|
- | 1603 | struct drm_device *dev = crtc->base.dev; |
|
- | 1604 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1605 | int pipe = crtc->pipe; |
|
- | 1606 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 1607 | u32 tmp; |
|
- | 1608 | ||
- | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
|
- | 1610 | ||
- | 1611 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); |
|
- | 1612 | ||
- | 1613 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1614 | ||
- | 1615 | /* Enable back the 10bit clock to display controller */ |
|
- | 1616 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
|
- | 1617 | tmp |= DPIO_DCLKP_EN; |
|
- | 1618 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
|
- | 1619 | ||
- | 1620 | /* |
|
- | 1621 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
|
- | 1622 | */ |
|
- | 1623 | udelay(1); |
|
- | 1624 | ||
- | 1625 | /* Enable PLL */ |
|
- | 1626 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
|
- | 1627 | ||
- | 1628 | /* Check PLL is locked */ |
|
- | 1629 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
|
- | 1630 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
|
- | 1631 | ||
- | 1632 | /* not sure when this should be written */ |
|
- | 1633 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); |
|
- | 1634 | POSTING_READ(DPLL_MD(pipe)); |
|
- | 1635 | ||
- | 1636 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 1637 | } |
|
1449 | 1638 | ||
1450 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1639 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1451 | { |
1640 | { |
1452 | struct drm_device *dev = crtc->base.dev; |
1641 | struct drm_device *dev = crtc->base.dev; |
1453 | struct drm_i915_private *dev_priv = dev->dev_private; |
1642 | struct drm_i915_private *dev_priv = dev->dev_private; |
1454 | int reg = DPLL(crtc->pipe); |
1643 | int reg = DPLL(crtc->pipe); |
1455 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1644 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1456 | 1645 | ||
1457 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1458 | 1647 | ||
1459 | /* No really, not for ILK+ */ |
1648 | /* No really, not for ILK+ */ |
1460 | BUG_ON(dev_priv->info->gen >= 5); |
1649 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
1461 | 1650 | ||
1462 | /* PLL is protected by panel, make sure we can write it */ |
1651 | /* PLL is protected by panel, make sure we can write it */ |
1463 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1652 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1464 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1653 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1465 | 1654 | ||
1466 | I915_WRITE(reg, dpll); |
1655 | I915_WRITE(reg, dpll); |
1467 | 1656 | ||
1468 | /* Wait for the clocks to stabilize. */ |
1657 | /* Wait for the clocks to stabilize. */ |
1469 | POSTING_READ(reg); |
1658 | POSTING_READ(reg); |
1470 | udelay(150); |
1659 | udelay(150); |
1471 | 1660 | ||
1472 | if (INTEL_INFO(dev)->gen >= 4) { |
1661 | if (INTEL_INFO(dev)->gen >= 4) { |
1473 | I915_WRITE(DPLL_MD(crtc->pipe), |
1662 | I915_WRITE(DPLL_MD(crtc->pipe), |
1474 | crtc->config.dpll_hw_state.dpll_md); |
1663 | crtc->config.dpll_hw_state.dpll_md); |
1475 | } else { |
1664 | } else { |
1476 | /* The pixel multiplier can only be updated once the |
1665 | /* The pixel multiplier can only be updated once the |
1477 | * DPLL is enabled and the clocks are stable. |
1666 | * DPLL is enabled and the clocks are stable. |
1478 | * |
1667 | * |
1479 | * So write it again. |
1668 | * So write it again. |
1480 | */ |
1669 | */ |
1481 | I915_WRITE(reg, dpll); |
1670 | I915_WRITE(reg, dpll); |
1482 | } |
1671 | } |
1483 | 1672 | ||
1484 | /* We do this three times for luck */ |
1673 | /* We do this three times for luck */ |
1485 | I915_WRITE(reg, dpll); |
1674 | I915_WRITE(reg, dpll); |
1486 | POSTING_READ(reg); |
1675 | POSTING_READ(reg); |
1487 | udelay(150); /* wait for warmup */ |
1676 | udelay(150); /* wait for warmup */ |
1488 | I915_WRITE(reg, dpll); |
1677 | I915_WRITE(reg, dpll); |
1489 | POSTING_READ(reg); |
1678 | POSTING_READ(reg); |
1490 | udelay(150); /* wait for warmup */ |
1679 | udelay(150); /* wait for warmup */ |
1491 | I915_WRITE(reg, dpll); |
1680 | I915_WRITE(reg, dpll); |
1492 | POSTING_READ(reg); |
1681 | POSTING_READ(reg); |
1493 | udelay(150); /* wait for warmup */ |
1682 | udelay(150); /* wait for warmup */ |
1494 | } |
1683 | } |
1495 | 1684 | ||
1496 | /** |
1685 | /** |
1497 | * i9xx_disable_pll - disable a PLL |
1686 | * i9xx_disable_pll - disable a PLL |
1498 | * @dev_priv: i915 private structure |
1687 | * @dev_priv: i915 private structure |
1499 | * @pipe: pipe PLL to disable |
1688 | * @pipe: pipe PLL to disable |
1500 | * |
1689 | * |
1501 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1690 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1502 | * |
1691 | * |
1503 | * Note! This is for pre-ILK only. |
1692 | * Note! This is for pre-ILK only. |
1504 | */ |
1693 | */ |
1505 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1694 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1506 | { |
1695 | { |
1507 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1696 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1508 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1697 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1509 | return; |
1698 | return; |
1510 | 1699 | ||
1511 | /* Make sure the pipe isn't still relying on us */ |
1700 | /* Make sure the pipe isn't still relying on us */ |
1512 | assert_pipe_disabled(dev_priv, pipe); |
1701 | assert_pipe_disabled(dev_priv, pipe); |
1513 | 1702 | ||
1514 | I915_WRITE(DPLL(pipe), 0); |
1703 | I915_WRITE(DPLL(pipe), 0); |
1515 | POSTING_READ(DPLL(pipe)); |
1704 | POSTING_READ(DPLL(pipe)); |
1516 | } |
1705 | } |
1517 | 1706 | ||
1518 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1707 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1519 | { |
1708 | { |
1520 | u32 val = 0; |
1709 | u32 val = 0; |
1521 | 1710 | ||
1522 | /* Make sure the pipe isn't still relying on us */ |
1711 | /* Make sure the pipe isn't still relying on us */ |
1523 | assert_pipe_disabled(dev_priv, pipe); |
1712 | assert_pipe_disabled(dev_priv, pipe); |
1524 | 1713 | ||
1525 | /* |
1714 | /* |
1526 | * Leave integrated clock source and reference clock enabled for pipe B. |
1715 | * Leave integrated clock source and reference clock enabled for pipe B. |
1527 | * The latter is needed for VGA hotplug / manual detection. |
1716 | * The latter is needed for VGA hotplug / manual detection. |
1528 | */ |
1717 | */ |
1529 | if (pipe == PIPE_B) |
1718 | if (pipe == PIPE_B) |
1530 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1719 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1531 | I915_WRITE(DPLL(pipe), val); |
1720 | I915_WRITE(DPLL(pipe), val); |
1532 | POSTING_READ(DPLL(pipe)); |
1721 | POSTING_READ(DPLL(pipe)); |
- | 1722 | ||
- | 1723 | } |
|
- | 1724 | ||
- | 1725 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
|
- | 1726 | { |
|
- | 1727 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 1728 | u32 val; |
|
- | 1729 | ||
- | 1730 | /* Make sure the pipe isn't still relying on us */ |
|
- | 1731 | assert_pipe_disabled(dev_priv, pipe); |
|
- | 1732 | ||
- | 1733 | /* Set PLL en = 0 */ |
|
- | 1734 | val = DPLL_SSC_REF_CLOCK_CHV; |
|
- | 1735 | if (pipe != PIPE_A) |
|
- | 1736 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 1737 | I915_WRITE(DPLL(pipe), val); |
|
- | 1738 | POSTING_READ(DPLL(pipe)); |
|
- | 1739 | ||
- | 1740 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1741 | ||
- | 1742 | /* Disable 10bit clock to display controller */ |
|
- | 1743 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
|
- | 1744 | val &= ~DPIO_DCLKP_EN; |
|
- | 1745 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
|
- | 1746 | ||
- | 1747 | /* disable left/right clock distribution */ |
|
- | 1748 | if (pipe != PIPE_B) { |
|
- | 1749 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
|
- | 1750 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
|
- | 1751 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
|
- | 1752 | } else { |
|
- | 1753 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
|
- | 1754 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
|
- | 1755 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
|
- | 1756 | } |
|
- | 1757 | ||
- | 1758 | mutex_unlock(&dev_priv->dpio_lock); |
|
1533 | } |
1759 | } |
1534 | 1760 | ||
1535 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1761 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1536 | struct intel_digital_port *dport) |
1762 | struct intel_digital_port *dport) |
1537 | { |
1763 | { |
1538 | u32 port_mask; |
1764 | u32 port_mask; |
- | 1765 | int dpll_reg; |
|
1539 | 1766 | ||
1540 | switch (dport->port) { |
1767 | switch (dport->port) { |
1541 | case PORT_B: |
1768 | case PORT_B: |
1542 | port_mask = DPLL_PORTB_READY_MASK; |
1769 | port_mask = DPLL_PORTB_READY_MASK; |
- | 1770 | dpll_reg = DPLL(0); |
|
1543 | break; |
1771 | break; |
1544 | case PORT_C: |
1772 | case PORT_C: |
1545 | port_mask = DPLL_PORTC_READY_MASK; |
1773 | port_mask = DPLL_PORTC_READY_MASK; |
- | 1774 | dpll_reg = DPLL(0); |
|
- | 1775 | break; |
|
- | 1776 | case PORT_D: |
|
- | 1777 | port_mask = DPLL_PORTD_READY_MASK; |
|
- | 1778 | dpll_reg = DPIO_PHY_STATUS; |
|
1546 | break; |
1779 | break; |
1547 | default: |
1780 | default: |
1548 | BUG(); |
1781 | BUG(); |
1549 | } |
1782 | } |
1550 | 1783 | ||
1551 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1784 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
1552 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1785 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
- | 1786 | port_name(dport->port), I915_READ(dpll_reg)); |
|
- | 1787 | } |
|
- | 1788 | ||
- | 1789 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
|
- | 1790 | { |
|
- | 1791 | struct drm_device *dev = crtc->base.dev; |
|
- | 1792 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1793 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
|
- | 1794 | ||
- | 1795 | if (WARN_ON(pll == NULL)) |
|
- | 1796 | return; |
|
- | 1797 | ||
- | 1798 | WARN_ON(!pll->refcount); |
|
- | 1799 | if (pll->active == 0) { |
|
- | 1800 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
|
- | 1801 | WARN_ON(pll->on); |
|
- | 1802 | assert_shared_dpll_disabled(dev_priv, pll); |
|
- | 1803 | ||
- | 1804 | pll->mode_set(dev_priv, pll); |
|
1553 | port_name(dport->port), I915_READ(DPLL(0))); |
1805 | } |
1554 | } |
1806 | } |
1555 | 1807 | ||
1556 | /** |
1808 | /** |
1557 | * ironlake_enable_shared_dpll - enable PCH PLL |
1809 | * intel_enable_shared_dpll - enable PCH PLL |
1558 | * @dev_priv: i915 private structure |
1810 | * @dev_priv: i915 private structure |
1559 | * @pipe: pipe PLL to enable |
1811 | * @pipe: pipe PLL to enable |
1560 | * |
1812 | * |
1561 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1813 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1562 | * drives the transcoder clock. |
1814 | * drives the transcoder clock. |
1563 | */ |
1815 | */ |
1564 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1816 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
1565 | { |
1817 | { |
- | 1818 | struct drm_device *dev = crtc->base.dev; |
|
1566 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1819 | struct drm_i915_private *dev_priv = dev->dev_private; |
1567 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1820 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1568 | - | ||
1569 | /* PCH PLLs only available on ILK, SNB and IVB */ |
- | |
1570 | BUG_ON(dev_priv->info->gen < 5); |
1821 | |
1571 | if (WARN_ON(pll == NULL)) |
1822 | if (WARN_ON(pll == NULL)) |
1572 | return; |
1823 | return; |
1573 | 1824 | ||
1574 | if (WARN_ON(pll->refcount == 0)) |
1825 | if (WARN_ON(pll->refcount == 0)) |
1575 | return; |
1826 | return; |
1576 | 1827 | ||
1577 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1828 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1578 | pll->name, pll->active, pll->on, |
1829 | pll->name, pll->active, pll->on, |
1579 | crtc->base.base.id); |
1830 | crtc->base.base.id); |
1580 | 1831 | ||
1581 | if (pll->active++) { |
1832 | if (pll->active++) { |
1582 | WARN_ON(!pll->on); |
1833 | WARN_ON(!pll->on); |
1583 | assert_shared_dpll_enabled(dev_priv, pll); |
1834 | assert_shared_dpll_enabled(dev_priv, pll); |
1584 | return; |
1835 | return; |
1585 | } |
1836 | } |
1586 | WARN_ON(pll->on); |
1837 | WARN_ON(pll->on); |
- | 1838 | ||
- | 1839 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
|
1587 | 1840 | ||
1588 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1841 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1589 | pll->enable(dev_priv, pll); |
1842 | pll->enable(dev_priv, pll); |
1590 | pll->on = true; |
1843 | pll->on = true; |
1591 | } |
1844 | } |
1592 | 1845 | ||
1593 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1846 | void intel_disable_shared_dpll(struct intel_crtc *crtc) |
- | 1847 | { |
|
1594 | { |
1848 | struct drm_device *dev = crtc->base.dev; |
1595 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1849 | struct drm_i915_private *dev_priv = dev->dev_private; |
1596 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1850 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1597 | 1851 | ||
1598 | /* PCH only available on ILK+ */ |
1852 | /* PCH only available on ILK+ */ |
1599 | BUG_ON(dev_priv->info->gen < 5); |
1853 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1600 | if (WARN_ON(pll == NULL)) |
1854 | if (WARN_ON(pll == NULL)) |
1601 | return; |
1855 | return; |
1602 | 1856 | ||
1603 | if (WARN_ON(pll->refcount == 0)) |
1857 | if (WARN_ON(pll->refcount == 0)) |
1604 | return; |
1858 | return; |
1605 | 1859 | ||
1606 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1860 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1607 | pll->name, pll->active, pll->on, |
1861 | pll->name, pll->active, pll->on, |
1608 | crtc->base.base.id); |
1862 | crtc->base.base.id); |
1609 | 1863 | ||
1610 | if (WARN_ON(pll->active == 0)) { |
1864 | if (WARN_ON(pll->active == 0)) { |
1611 | assert_shared_dpll_disabled(dev_priv, pll); |
1865 | assert_shared_dpll_disabled(dev_priv, pll); |
1612 | return; |
1866 | return; |
1613 | } |
1867 | } |
1614 | 1868 | ||
1615 | assert_shared_dpll_enabled(dev_priv, pll); |
1869 | assert_shared_dpll_enabled(dev_priv, pll); |
1616 | WARN_ON(!pll->on); |
1870 | WARN_ON(!pll->on); |
1617 | if (--pll->active) |
1871 | if (--pll->active) |
1618 | return; |
1872 | return; |
1619 | 1873 | ||
1620 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1874 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1621 | pll->disable(dev_priv, pll); |
1875 | pll->disable(dev_priv, pll); |
1622 | pll->on = false; |
1876 | pll->on = false; |
- | 1877 | ||
- | 1878 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
|
1623 | } |
1879 | } |
1624 | 1880 | ||
1625 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1881 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1626 | enum pipe pipe) |
1882 | enum pipe pipe) |
1627 | { |
1883 | { |
1628 | struct drm_device *dev = dev_priv->dev; |
1884 | struct drm_device *dev = dev_priv->dev; |
1629 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1885 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1631 | uint32_t reg, val, pipeconf_val; |
1887 | uint32_t reg, val, pipeconf_val; |
1632 | 1888 | ||
1633 | /* PCH only available on ILK+ */ |
1889 | /* PCH only available on ILK+ */ |
1634 | BUG_ON(dev_priv->info->gen < 5); |
1890 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1635 | 1891 | ||
1636 | /* Make sure PCH DPLL is enabled */ |
1892 | /* Make sure PCH DPLL is enabled */ |
1637 | assert_shared_dpll_enabled(dev_priv, |
1893 | assert_shared_dpll_enabled(dev_priv, |
1638 | intel_crtc_to_shared_dpll(intel_crtc)); |
1894 | intel_crtc_to_shared_dpll(intel_crtc)); |
1639 | 1895 | ||
1640 | /* FDI must be feeding us bits for PCH ports */ |
1896 | /* FDI must be feeding us bits for PCH ports */ |
1641 | assert_fdi_tx_enabled(dev_priv, pipe); |
1897 | assert_fdi_tx_enabled(dev_priv, pipe); |
1642 | assert_fdi_rx_enabled(dev_priv, pipe); |
1898 | assert_fdi_rx_enabled(dev_priv, pipe); |
1643 | 1899 | ||
1644 | if (HAS_PCH_CPT(dev)) { |
1900 | if (HAS_PCH_CPT(dev)) { |
1645 | /* Workaround: Set the timing override bit before enabling the |
1901 | /* Workaround: Set the timing override bit before enabling the |
1646 | * pch transcoder. */ |
1902 | * pch transcoder. */ |
1647 | reg = TRANS_CHICKEN2(pipe); |
1903 | reg = TRANS_CHICKEN2(pipe); |
1648 | val = I915_READ(reg); |
1904 | val = I915_READ(reg); |
1649 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1905 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1650 | I915_WRITE(reg, val); |
1906 | I915_WRITE(reg, val); |
1651 | } |
1907 | } |
1652 | 1908 | ||
1653 | reg = PCH_TRANSCONF(pipe); |
1909 | reg = PCH_TRANSCONF(pipe); |
1654 | val = I915_READ(reg); |
1910 | val = I915_READ(reg); |
1655 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1911 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1656 | 1912 | ||
1657 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1913 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1658 | /* |
1914 | /* |
1659 | * make the BPC in transcoder be consistent with |
1915 | * make the BPC in transcoder be consistent with |
1660 | * that in pipeconf reg. |
1916 | * that in pipeconf reg. |
1661 | */ |
1917 | */ |
1662 | val &= ~PIPECONF_BPC_MASK; |
1918 | val &= ~PIPECONF_BPC_MASK; |
1663 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1919 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1664 | } |
1920 | } |
1665 | 1921 | ||
1666 | val &= ~TRANS_INTERLACE_MASK; |
1922 | val &= ~TRANS_INTERLACE_MASK; |
1667 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1923 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1668 | if (HAS_PCH_IBX(dev_priv->dev) && |
1924 | if (HAS_PCH_IBX(dev_priv->dev) && |
1669 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1925 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1670 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1926 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1671 | else |
1927 | else |
1672 | val |= TRANS_INTERLACED; |
1928 | val |= TRANS_INTERLACED; |
1673 | else |
1929 | else |
1674 | val |= TRANS_PROGRESSIVE; |
1930 | val |= TRANS_PROGRESSIVE; |
1675 | 1931 | ||
1676 | I915_WRITE(reg, val | TRANS_ENABLE); |
1932 | I915_WRITE(reg, val | TRANS_ENABLE); |
1677 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1933 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1678 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1934 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1679 | } |
1935 | } |
1680 | 1936 | ||
1681 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1937 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1682 | enum transcoder cpu_transcoder) |
1938 | enum transcoder cpu_transcoder) |
1683 | { |
1939 | { |
1684 | u32 val, pipeconf_val; |
1940 | u32 val, pipeconf_val; |
1685 | 1941 | ||
1686 | /* PCH only available on ILK+ */ |
1942 | /* PCH only available on ILK+ */ |
1687 | BUG_ON(dev_priv->info->gen < 5); |
1943 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
1688 | 1944 | ||
1689 | /* FDI must be feeding us bits for PCH ports */ |
1945 | /* FDI must be feeding us bits for PCH ports */ |
1690 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1946 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1691 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1947 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1692 | 1948 | ||
1693 | /* Workaround: set timing override bit. */ |
1949 | /* Workaround: set timing override bit. */ |
1694 | val = I915_READ(_TRANSA_CHICKEN2); |
1950 | val = I915_READ(_TRANSA_CHICKEN2); |
1695 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1951 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1696 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1952 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1697 | 1953 | ||
1698 | val = TRANS_ENABLE; |
1954 | val = TRANS_ENABLE; |
1699 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1955 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1700 | 1956 | ||
1701 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1957 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1702 | PIPECONF_INTERLACED_ILK) |
1958 | PIPECONF_INTERLACED_ILK) |
1703 | val |= TRANS_INTERLACED; |
1959 | val |= TRANS_INTERLACED; |
1704 | else |
1960 | else |
1705 | val |= TRANS_PROGRESSIVE; |
1961 | val |= TRANS_PROGRESSIVE; |
1706 | 1962 | ||
1707 | I915_WRITE(LPT_TRANSCONF, val); |
1963 | I915_WRITE(LPT_TRANSCONF, val); |
1708 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1964 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1709 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1965 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1710 | } |
1966 | } |
1711 | 1967 | ||
1712 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1968 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1713 | enum pipe pipe) |
1969 | enum pipe pipe) |
1714 | { |
1970 | { |
1715 | struct drm_device *dev = dev_priv->dev; |
1971 | struct drm_device *dev = dev_priv->dev; |
1716 | uint32_t reg, val; |
1972 | uint32_t reg, val; |
1717 | 1973 | ||
1718 | /* FDI relies on the transcoder */ |
1974 | /* FDI relies on the transcoder */ |
1719 | assert_fdi_tx_disabled(dev_priv, pipe); |
1975 | assert_fdi_tx_disabled(dev_priv, pipe); |
1720 | assert_fdi_rx_disabled(dev_priv, pipe); |
1976 | assert_fdi_rx_disabled(dev_priv, pipe); |
1721 | 1977 | ||
1722 | /* Ports must be off as well */ |
1978 | /* Ports must be off as well */ |
1723 | assert_pch_ports_disabled(dev_priv, pipe); |
1979 | assert_pch_ports_disabled(dev_priv, pipe); |
1724 | 1980 | ||
1725 | reg = PCH_TRANSCONF(pipe); |
1981 | reg = PCH_TRANSCONF(pipe); |
1726 | val = I915_READ(reg); |
1982 | val = I915_READ(reg); |
1727 | val &= ~TRANS_ENABLE; |
1983 | val &= ~TRANS_ENABLE; |
1728 | I915_WRITE(reg, val); |
1984 | I915_WRITE(reg, val); |
1729 | /* wait for PCH transcoder off, transcoder state */ |
1985 | /* wait for PCH transcoder off, transcoder state */ |
1730 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1986 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1731 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1987 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1732 | 1988 | ||
1733 | if (!HAS_PCH_IBX(dev)) { |
1989 | if (!HAS_PCH_IBX(dev)) { |
1734 | /* Workaround: Clear the timing override chicken bit again. */ |
1990 | /* Workaround: Clear the timing override chicken bit again. */ |
1735 | reg = TRANS_CHICKEN2(pipe); |
1991 | reg = TRANS_CHICKEN2(pipe); |
1736 | val = I915_READ(reg); |
1992 | val = I915_READ(reg); |
1737 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1993 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1738 | I915_WRITE(reg, val); |
1994 | I915_WRITE(reg, val); |
1739 | } |
1995 | } |
1740 | } |
1996 | } |
1741 | 1997 | ||
1742 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1998 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1743 | { |
1999 | { |
1744 | u32 val; |
2000 | u32 val; |
1745 | 2001 | ||
1746 | val = I915_READ(LPT_TRANSCONF); |
2002 | val = I915_READ(LPT_TRANSCONF); |
1747 | val &= ~TRANS_ENABLE; |
2003 | val &= ~TRANS_ENABLE; |
1748 | I915_WRITE(LPT_TRANSCONF, val); |
2004 | I915_WRITE(LPT_TRANSCONF, val); |
1749 | /* wait for PCH transcoder off, transcoder state */ |
2005 | /* wait for PCH transcoder off, transcoder state */ |
1750 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
2006 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1751 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
2007 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1752 | 2008 | ||
1753 | /* Workaround: clear timing override bit. */ |
2009 | /* Workaround: clear timing override bit. */ |
1754 | val = I915_READ(_TRANSA_CHICKEN2); |
2010 | val = I915_READ(_TRANSA_CHICKEN2); |
1755 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
2011 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1756 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2012 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1757 | } |
2013 | } |
1758 | 2014 | ||
1759 | /** |
2015 | /** |
1760 | * intel_enable_pipe - enable a pipe, asserting requirements |
2016 | * intel_enable_pipe - enable a pipe, asserting requirements |
1761 | * @dev_priv: i915 private structure |
- | |
1762 | * @pipe: pipe to enable |
2017 | * @crtc: crtc responsible for the pipe |
1763 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
- | |
1764 | * |
2018 | * |
1765 | * Enable @pipe, making sure that various hardware specific requirements |
2019 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
1766 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
2020 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1767 | * |
- | |
1768 | * @pipe should be %PIPE_A or %PIPE_B. |
- | |
1769 | * |
- | |
1770 | * Will wait until the pipe is actually running (i.e. first vblank) before |
- | |
1771 | * returning. |
- | |
1772 | */ |
2021 | */ |
1773 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
2022 | static void intel_enable_pipe(struct intel_crtc *crtc) |
1774 | bool pch_port, bool dsi) |
- | |
1775 | { |
2023 | { |
- | 2024 | struct drm_device *dev = crtc->base.dev; |
|
- | 2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2026 | enum pipe pipe = crtc->pipe; |
|
1776 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2027 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1777 | pipe); |
2028 | pipe); |
1778 | enum pipe pch_transcoder; |
2029 | enum pipe pch_transcoder; |
1779 | int reg; |
2030 | int reg; |
1780 | u32 val; |
2031 | u32 val; |
1781 | 2032 | ||
1782 | assert_planes_disabled(dev_priv, pipe); |
2033 | assert_planes_disabled(dev_priv, pipe); |
1783 | assert_cursor_disabled(dev_priv, pipe); |
2034 | assert_cursor_disabled(dev_priv, pipe); |
1784 | assert_sprites_disabled(dev_priv, pipe); |
2035 | assert_sprites_disabled(dev_priv, pipe); |
1785 | 2036 | ||
1786 | if (HAS_PCH_LPT(dev_priv->dev)) |
2037 | if (HAS_PCH_LPT(dev_priv->dev)) |
1787 | pch_transcoder = TRANSCODER_A; |
2038 | pch_transcoder = TRANSCODER_A; |
1788 | else |
2039 | else |
1789 | pch_transcoder = pipe; |
2040 | pch_transcoder = pipe; |
1790 | 2041 | ||
1791 | /* |
2042 | /* |
1792 | * A pipe without a PLL won't actually be able to drive bits from |
2043 | * A pipe without a PLL won't actually be able to drive bits from |
1793 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
2044 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1794 | * need the check. |
2045 | * need the check. |
1795 | */ |
2046 | */ |
1796 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
2047 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1797 | if (dsi) |
2048 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
1798 | assert_dsi_pll_enabled(dev_priv); |
2049 | assert_dsi_pll_enabled(dev_priv); |
1799 | else |
2050 | else |
1800 | assert_pll_enabled(dev_priv, pipe); |
2051 | assert_pll_enabled(dev_priv, pipe); |
1801 | else { |
2052 | else { |
1802 | if (pch_port) { |
2053 | if (crtc->config.has_pch_encoder) { |
1803 | /* if driving the PCH, we need FDI enabled */ |
2054 | /* if driving the PCH, we need FDI enabled */ |
1804 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
2055 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1805 | assert_fdi_tx_pll_enabled(dev_priv, |
2056 | assert_fdi_tx_pll_enabled(dev_priv, |
1806 | (enum pipe) cpu_transcoder); |
2057 | (enum pipe) cpu_transcoder); |
1807 | } |
2058 | } |
1808 | /* FIXME: assert CPU port conditions for SNB+ */ |
2059 | /* FIXME: assert CPU port conditions for SNB+ */ |
1809 | } |
2060 | } |
1810 | 2061 | ||
1811 | reg = PIPECONF(cpu_transcoder); |
2062 | reg = PIPECONF(cpu_transcoder); |
1812 | val = I915_READ(reg); |
2063 | val = I915_READ(reg); |
1813 | if (val & PIPECONF_ENABLE) |
2064 | if (val & PIPECONF_ENABLE) { |
- | 2065 | WARN_ON(!(pipe == PIPE_A && |
|
- | 2066 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
|
1814 | return; |
2067 | return; |
- | 2068 | } |
|
1815 | 2069 | ||
1816 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
2070 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1817 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2071 | POSTING_READ(reg); |
1818 | } |
2072 | } |
1819 | 2073 | ||
1820 | /** |
2074 | /** |
1821 | * intel_disable_pipe - disable a pipe, asserting requirements |
2075 | * intel_disable_pipe - disable a pipe, asserting requirements |
1822 | * @dev_priv: i915 private structure |
2076 | * @dev_priv: i915 private structure |
1823 | * @pipe: pipe to disable |
2077 | * @pipe: pipe to disable |
1824 | * |
2078 | * |
1825 | * Disable @pipe, making sure that various hardware specific requirements |
2079 | * Disable @pipe, making sure that various hardware specific requirements |
1826 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
2080 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1827 | * |
2081 | * |
1828 | * @pipe should be %PIPE_A or %PIPE_B. |
2082 | * @pipe should be %PIPE_A or %PIPE_B. |
1829 | * |
2083 | * |
1830 | * Will wait until the pipe has shut down before returning. |
2084 | * Will wait until the pipe has shut down before returning. |
1831 | */ |
2085 | */ |
1832 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
2086 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1833 | enum pipe pipe) |
2087 | enum pipe pipe) |
1834 | { |
2088 | { |
1835 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2089 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1836 | pipe); |
2090 | pipe); |
1837 | int reg; |
2091 | int reg; |
1838 | u32 val; |
2092 | u32 val; |
1839 | 2093 | ||
1840 | /* |
2094 | /* |
1841 | * Make sure planes won't keep trying to pump pixels to us, |
2095 | * Make sure planes won't keep trying to pump pixels to us, |
1842 | * or we might hang the display. |
2096 | * or we might hang the display. |
1843 | */ |
2097 | */ |
1844 | assert_planes_disabled(dev_priv, pipe); |
2098 | assert_planes_disabled(dev_priv, pipe); |
1845 | assert_cursor_disabled(dev_priv, pipe); |
2099 | assert_cursor_disabled(dev_priv, pipe); |
1846 | assert_sprites_disabled(dev_priv, pipe); |
2100 | assert_sprites_disabled(dev_priv, pipe); |
1847 | 2101 | ||
1848 | /* Don't disable pipe A or pipe A PLLs if needed */ |
2102 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1849 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
2103 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1850 | return; |
2104 | return; |
1851 | 2105 | ||
1852 | reg = PIPECONF(cpu_transcoder); |
2106 | reg = PIPECONF(cpu_transcoder); |
1853 | val = I915_READ(reg); |
2107 | val = I915_READ(reg); |
1854 | if ((val & PIPECONF_ENABLE) == 0) |
2108 | if ((val & PIPECONF_ENABLE) == 0) |
1855 | return; |
2109 | return; |
1856 | 2110 | ||
1857 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
2111 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1858 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2112 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1859 | } |
2113 | } |
1860 | 2114 | ||
1861 | /* |
2115 | /* |
1862 | * Plane regs are double buffered, going from enabled->disabled needs a |
2116 | * Plane regs are double buffered, going from enabled->disabled needs a |
1863 | * trigger in order to latch. The display address reg provides this. |
2117 | * trigger in order to latch. The display address reg provides this. |
1864 | */ |
2118 | */ |
1865 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2119 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1866 | enum plane plane) |
2120 | enum plane plane) |
1867 | { |
2121 | { |
- | 2122 | struct drm_device *dev = dev_priv->dev; |
|
1868 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
2123 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1869 | 2124 | ||
1870 | I915_WRITE(reg, I915_READ(reg)); |
2125 | I915_WRITE(reg, I915_READ(reg)); |
1871 | POSTING_READ(reg); |
2126 | POSTING_READ(reg); |
1872 | } |
2127 | } |
1873 | 2128 | ||
1874 | /** |
2129 | /** |
1875 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
2130 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
1876 | * @dev_priv: i915 private structure |
2131 | * @dev_priv: i915 private structure |
1877 | * @plane: plane to enable |
2132 | * @plane: plane to enable |
1878 | * @pipe: pipe being fed |
2133 | * @pipe: pipe being fed |
1879 | * |
2134 | * |
1880 | * Enable @plane on @pipe, making sure that @pipe is running first. |
2135 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1881 | */ |
2136 | */ |
1882 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
2137 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
1883 | enum plane plane, enum pipe pipe) |
2138 | enum plane plane, enum pipe pipe) |
1884 | { |
2139 | { |
- | 2140 | struct drm_device *dev = dev_priv->dev; |
|
1885 | struct intel_crtc *intel_crtc = |
2141 | struct intel_crtc *intel_crtc = |
1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
2142 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
1887 | int reg; |
2143 | int reg; |
1888 | u32 val; |
2144 | u32 val; |
1889 | 2145 | ||
1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
2146 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1891 | assert_pipe_enabled(dev_priv, pipe); |
2147 | assert_pipe_enabled(dev_priv, pipe); |
1892 | 2148 | ||
- | 2149 | if (intel_crtc->primary_enabled) |
|
1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
2150 | return; |
1894 | 2151 | ||
1895 | intel_crtc->primary_enabled = true; |
2152 | intel_crtc->primary_enabled = true; |
1896 | 2153 | ||
1897 | reg = DSPCNTR(plane); |
2154 | reg = DSPCNTR(plane); |
1898 | val = I915_READ(reg); |
2155 | val = I915_READ(reg); |
1899 | if (val & DISPLAY_PLANE_ENABLE) |
2156 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
1900 | return; |
- | |
1901 | 2157 | ||
1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
2158 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1903 | intel_flush_primary_plane(dev_priv, plane); |
2159 | intel_flush_primary_plane(dev_priv, plane); |
1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
- | |
1905 | } |
2160 | } |
1906 | 2161 | ||
1907 | /** |
2162 | /** |
1908 | * intel_disable_primary_plane - disable the primary plane |
2163 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
1909 | * @dev_priv: i915 private structure |
2164 | * @dev_priv: i915 private structure |
1910 | * @plane: plane to disable |
2165 | * @plane: plane to disable |
1911 | * @pipe: pipe consuming the data |
2166 | * @pipe: pipe consuming the data |
1912 | * |
2167 | * |
1913 | * Disable @plane; should be an independent operation. |
2168 | * Disable @plane; should be an independent operation. |
1914 | */ |
2169 | */ |
1915 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
2170 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
1916 | enum plane plane, enum pipe pipe) |
2171 | enum plane plane, enum pipe pipe) |
1917 | { |
2172 | { |
1918 | struct intel_crtc *intel_crtc = |
2173 | struct intel_crtc *intel_crtc = |
1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
2174 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
1920 | int reg; |
2175 | int reg; |
1921 | u32 val; |
2176 | u32 val; |
1922 | 2177 | ||
- | 2178 | if (!intel_crtc->primary_enabled) |
|
1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
2179 | return; |
1924 | 2180 | ||
1925 | intel_crtc->primary_enabled = false; |
2181 | intel_crtc->primary_enabled = false; |
1926 | 2182 | ||
1927 | reg = DSPCNTR(plane); |
2183 | reg = DSPCNTR(plane); |
1928 | val = I915_READ(reg); |
2184 | val = I915_READ(reg); |
1929 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
2185 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
1930 | return; |
- | |
1931 | 2186 | ||
1932 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
2187 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1933 | intel_flush_primary_plane(dev_priv, plane); |
2188 | intel_flush_primary_plane(dev_priv, plane); |
1934 | intel_wait_for_vblank(dev_priv->dev, pipe); |
- | |
1935 | } |
2189 | } |
1936 | 2190 | ||
1937 | static bool need_vtd_wa(struct drm_device *dev) |
2191 | static bool need_vtd_wa(struct drm_device *dev) |
1938 | { |
2192 | { |
1939 | #ifdef CONFIG_INTEL_IOMMU |
2193 | #ifdef CONFIG_INTEL_IOMMU |
1940 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
2194 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1941 | return true; |
2195 | return true; |
1942 | #endif |
2196 | #endif |
1943 | return false; |
2197 | return false; |
1944 | } |
2198 | } |
- | 2199 | ||
- | 2200 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
|
- | 2201 | { |
|
- | 2202 | int tile_height; |
|
- | 2203 | ||
- | 2204 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
|
- | 2205 | return ALIGN(height, tile_height); |
|
- | 2206 | } |
|
1945 | 2207 | ||
1946 | int |
2208 | int |
1947 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
2209 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1948 | struct drm_i915_gem_object *obj, |
2210 | struct drm_i915_gem_object *obj, |
1949 | struct intel_ring_buffer *pipelined) |
2211 | struct intel_engine_cs *pipelined) |
1950 | { |
2212 | { |
1951 | struct drm_i915_private *dev_priv = dev->dev_private; |
2213 | struct drm_i915_private *dev_priv = dev->dev_private; |
1952 | u32 alignment; |
2214 | u32 alignment; |
1953 | int ret; |
2215 | int ret; |
- | 2216 | ||
- | 2217 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
1954 | 2218 | ||
1955 | switch (obj->tiling_mode) { |
2219 | switch (obj->tiling_mode) { |
1956 | case I915_TILING_NONE: |
2220 | case I915_TILING_NONE: |
1957 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2221 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1958 | alignment = 128 * 1024; |
2222 | alignment = 128 * 1024; |
1959 | else if (INTEL_INFO(dev)->gen >= 4) |
2223 | else if (INTEL_INFO(dev)->gen >= 4) |
1960 | alignment = 4 * 1024; |
2224 | alignment = 4 * 1024; |
1961 | else |
2225 | else |
1962 | alignment = 64 * 1024; |
2226 | alignment = 64 * 1024; |
1963 | break; |
2227 | break; |
1964 | case I915_TILING_X: |
2228 | case I915_TILING_X: |
1965 | /* pin() will align the object as required by fence */ |
2229 | /* pin() will align the object as required by fence */ |
1966 | alignment = 0; |
2230 | alignment = 0; |
1967 | break; |
2231 | break; |
1968 | case I915_TILING_Y: |
2232 | case I915_TILING_Y: |
1969 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
2233 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
1970 | return -EINVAL; |
2234 | return -EINVAL; |
1971 | default: |
2235 | default: |
1972 | BUG(); |
2236 | BUG(); |
1973 | } |
2237 | } |
1974 | 2238 | ||
1975 | /* Note that the w/a also requires 64 PTE of padding following the |
2239 | /* Note that the w/a also requires 64 PTE of padding following the |
1976 | * bo. We currently fill all unused PTE with the shadow page and so |
2240 | * bo. We currently fill all unused PTE with the shadow page and so |
1977 | * we should always have valid PTE following the scanout preventing |
2241 | * we should always have valid PTE following the scanout preventing |
1978 | * the VT-d warning. |
2242 | * the VT-d warning. |
1979 | */ |
2243 | */ |
1980 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
2244 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1981 | alignment = 256 * 1024; |
2245 | alignment = 256 * 1024; |
1982 | 2246 | ||
1983 | dev_priv->mm.interruptible = false; |
2247 | dev_priv->mm.interruptible = false; |
1984 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
2248 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1985 | if (ret) |
2249 | if (ret) |
1986 | goto err_interruptible; |
2250 | goto err_interruptible; |
1987 | 2251 | ||
1988 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2252 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1989 | * fence, whereas 965+ only requires a fence if using |
2253 | * fence, whereas 965+ only requires a fence if using |
1990 | * framebuffer compression. For simplicity, we always install |
2254 | * framebuffer compression. For simplicity, we always install |
1991 | * a fence as the cost is not that onerous. |
2255 | * a fence as the cost is not that onerous. |
1992 | */ |
2256 | */ |
1993 | ret = i915_gem_object_get_fence(obj); |
2257 | ret = i915_gem_object_get_fence(obj); |
1994 | if (ret) |
2258 | if (ret) |
1995 | goto err_unpin; |
2259 | goto err_unpin; |
1996 | 2260 | ||
1997 | i915_gem_object_pin_fence(obj); |
2261 | i915_gem_object_pin_fence(obj); |
1998 | 2262 | ||
1999 | dev_priv->mm.interruptible = true; |
2263 | dev_priv->mm.interruptible = true; |
2000 | return 0; |
2264 | return 0; |
2001 | 2265 | ||
2002 | err_unpin: |
2266 | err_unpin: |
2003 | i915_gem_object_unpin_from_display_plane(obj); |
2267 | i915_gem_object_unpin_from_display_plane(obj); |
2004 | err_interruptible: |
2268 | err_interruptible: |
2005 | dev_priv->mm.interruptible = true; |
2269 | dev_priv->mm.interruptible = true; |
2006 | return ret; |
2270 | return ret; |
2007 | } |
2271 | } |
2008 | 2272 | ||
2009 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2273 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2010 | { |
2274 | { |
- | 2275 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
|
- | 2276 | ||
2011 | // i915_gem_object_unpin_fence(obj); |
2277 | i915_gem_object_unpin_fence(obj); |
2012 | // i915_gem_object_unpin(obj); |
2278 | // i915_gem_object_unpin_from_display_plane(obj); |
2013 | } |
2279 | } |
2014 | 2280 | ||
2015 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2281 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2016 | * is assumed to be a power-of-two. */ |
2282 | * is assumed to be a power-of-two. */ |
2017 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2283 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2018 | unsigned int tiling_mode, |
2284 | unsigned int tiling_mode, |
2019 | unsigned int cpp, |
2285 | unsigned int cpp, |
2020 | unsigned int pitch) |
2286 | unsigned int pitch) |
2021 | { |
2287 | { |
2022 | if (tiling_mode != I915_TILING_NONE) { |
2288 | if (tiling_mode != I915_TILING_NONE) { |
2023 | unsigned int tile_rows, tiles; |
2289 | unsigned int tile_rows, tiles; |
2024 | 2290 | ||
2025 | tile_rows = *y / 8; |
2291 | tile_rows = *y / 8; |
2026 | *y %= 8; |
2292 | *y %= 8; |
2027 | 2293 | ||
2028 | tiles = *x / (512/cpp); |
2294 | tiles = *x / (512/cpp); |
2029 | *x %= 512/cpp; |
2295 | *x %= 512/cpp; |
2030 | 2296 | ||
2031 | return tile_rows * pitch * 8 + tiles * 4096; |
2297 | return tile_rows * pitch * 8 + tiles * 4096; |
2032 | } else { |
2298 | } else { |
2033 | unsigned int offset; |
2299 | unsigned int offset; |
2034 | 2300 | ||
2035 | offset = *y * pitch + *x * cpp; |
2301 | offset = *y * pitch + *x * cpp; |
2036 | *y = 0; |
2302 | *y = 0; |
2037 | *x = (offset & 4095) / cpp; |
2303 | *x = (offset & 4095) / cpp; |
2038 | return offset & -4096; |
2304 | return offset & -4096; |
2039 | } |
2305 | } |
2040 | } |
2306 | } |
- | 2307 | ||
- | 2308 | int intel_format_to_fourcc(int format) |
|
- | 2309 | { |
|
- | 2310 | switch (format) { |
|
- | 2311 | case DISPPLANE_8BPP: |
|
- | 2312 | return DRM_FORMAT_C8; |
|
- | 2313 | case DISPPLANE_BGRX555: |
|
- | 2314 | return DRM_FORMAT_XRGB1555; |
|
- | 2315 | case DISPPLANE_BGRX565: |
|
- | 2316 | return DRM_FORMAT_RGB565; |
|
- | 2317 | default: |
|
- | 2318 | case DISPPLANE_BGRX888: |
|
- | 2319 | return DRM_FORMAT_XRGB8888; |
|
- | 2320 | case DISPPLANE_RGBX888: |
|
- | 2321 | return DRM_FORMAT_XBGR8888; |
|
- | 2322 | case DISPPLANE_BGRX101010: |
|
- | 2323 | return DRM_FORMAT_XRGB2101010; |
|
- | 2324 | case DISPPLANE_RGBX101010: |
|
- | 2325 | return DRM_FORMAT_XBGR2101010; |
|
- | 2326 | } |
|
- | 2327 | } |
|
- | 2328 | ||
- | 2329 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
|
- | 2330 | struct intel_plane_config *plane_config) |
|
- | 2331 | { |
|
- | 2332 | struct drm_device *dev = crtc->base.dev; |
|
- | 2333 | struct drm_i915_gem_object *obj = NULL; |
|
- | 2334 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
|
- | 2335 | u32 base = plane_config->base; |
|
- | 2336 | ||
- | 2337 | if (plane_config->size == 0) |
|
- | 2338 | return false; |
|
- | 2339 | ||
- | 2340 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
|
- | 2341 | plane_config->size); |
|
- | 2342 | if (!obj) |
|
- | 2343 | return false; |
|
- | 2344 | ||
- | 2345 | main_fb_obj = obj; |
|
- | 2346 | ||
- | 2347 | if (plane_config->tiled) { |
|
- | 2348 | obj->tiling_mode = I915_TILING_X; |
|
- | 2349 | obj->stride = crtc->base.primary->fb->pitches[0]; |
|
- | 2350 | } |
|
- | 2351 | ||
- | 2352 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
|
- | 2353 | mode_cmd.width = crtc->base.primary->fb->width; |
|
- | 2354 | mode_cmd.height = crtc->base.primary->fb->height; |
|
- | 2355 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; |
|
- | 2356 | ||
- | 2357 | mutex_lock(&dev->struct_mutex); |
|
- | 2358 | ||
- | 2359 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
|
- | 2360 | &mode_cmd, obj)) { |
|
- | 2361 | DRM_DEBUG_KMS("intel fb init failed\n"); |
|
- | 2362 | goto out_unref_obj; |
|
- | 2363 | } |
|
- | 2364 | ||
- | 2365 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
|
- | 2366 | mutex_unlock(&dev->struct_mutex); |
|
- | 2367 | ||
- | 2368 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); |
|
- | 2369 | return true; |
|
- | 2370 | ||
- | 2371 | out_unref_obj: |
|
- | 2372 | drm_gem_object_unreference(&obj->base); |
|
- | 2373 | mutex_unlock(&dev->struct_mutex); |
|
- | 2374 | return false; |
|
- | 2375 | } |
|
- | 2376 | ||
- | 2377 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
|
- | 2378 | struct intel_plane_config *plane_config) |
|
- | 2379 | { |
|
- | 2380 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 2381 | struct drm_crtc *c; |
|
- | 2382 | struct intel_crtc *i; |
|
- | 2383 | struct drm_i915_gem_object *obj; |
|
- | 2384 | ||
- | 2385 | if (!intel_crtc->base.primary->fb) |
|
- | 2386 | return; |
|
- | 2387 | ||
- | 2388 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
|
- | 2389 | return; |
|
- | 2390 | ||
- | 2391 | kfree(intel_crtc->base.primary->fb); |
|
- | 2392 | intel_crtc->base.primary->fb = NULL; |
|
- | 2393 | ||
- | 2394 | /* |
|
- | 2395 | * Failed to alloc the obj, check to see if we should share |
|
- | 2396 | * an fb with another CRTC instead |
|
- | 2397 | */ |
|
- | 2398 | for_each_crtc(dev, c) { |
|
- | 2399 | i = to_intel_crtc(c); |
|
- | 2400 | ||
- | 2401 | if (c == &intel_crtc->base) |
|
- | 2402 | continue; |
|
- | 2403 | ||
- | 2404 | if (!i->active) |
|
- | 2405 | continue; |
|
- | 2406 | ||
- | 2407 | obj = intel_fb_obj(c->primary->fb); |
|
- | 2408 | if (obj == NULL) |
|
- | 2409 | continue; |
|
- | 2410 | ||
- | 2411 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
|
- | 2412 | drm_framebuffer_reference(c->primary->fb); |
|
- | 2413 | intel_crtc->base.primary->fb = c->primary->fb; |
|
- | 2414 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
|
- | 2415 | break; |
|
- | 2416 | } |
|
- | 2417 | } |
|
- | 2418 | } |
|
2041 | 2419 | ||
- | 2420 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
|
2042 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2421 | struct drm_framebuffer *fb, |
2043 | int x, int y) |
2422 | int x, int y) |
2044 | { |
2423 | { |
2045 | struct drm_device *dev = crtc->dev; |
2424 | struct drm_device *dev = crtc->dev; |
2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
2425 | struct drm_i915_private *dev_priv = dev->dev_private; |
2047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2048 | struct intel_framebuffer *intel_fb; |
- | |
2049 | struct drm_i915_gem_object *obj; |
2427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2050 | int plane = intel_crtc->plane; |
2428 | int plane = intel_crtc->plane; |
2051 | unsigned long linear_offset; |
2429 | unsigned long linear_offset; |
2052 | u32 dspcntr; |
2430 | u32 dspcntr; |
2053 | u32 reg; |
2431 | u32 reg; |
2054 | - | ||
2055 | switch (plane) { |
- | |
2056 | case 0: |
- | |
2057 | case 1: |
- | |
2058 | break; |
- | |
2059 | default: |
- | |
2060 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
- | |
2061 | return -EINVAL; |
- | |
2062 | } |
- | |
2063 | - | ||
2064 | intel_fb = to_intel_framebuffer(fb); |
- | |
2065 | obj = intel_fb->obj; |
- | |
2066 | 2432 | ||
2067 | reg = DSPCNTR(plane); |
2433 | reg = DSPCNTR(plane); |
2068 | dspcntr = I915_READ(reg); |
2434 | dspcntr = I915_READ(reg); |
2069 | /* Mask out pixel format bits in case we change it */ |
2435 | /* Mask out pixel format bits in case we change it */ |
2070 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2436 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2071 | switch (fb->pixel_format) { |
2437 | switch (fb->pixel_format) { |
2072 | case DRM_FORMAT_C8: |
2438 | case DRM_FORMAT_C8: |
2073 | dspcntr |= DISPPLANE_8BPP; |
2439 | dspcntr |= DISPPLANE_8BPP; |
2074 | break; |
2440 | break; |
2075 | case DRM_FORMAT_XRGB1555: |
2441 | case DRM_FORMAT_XRGB1555: |
2076 | case DRM_FORMAT_ARGB1555: |
2442 | case DRM_FORMAT_ARGB1555: |
2077 | dspcntr |= DISPPLANE_BGRX555; |
2443 | dspcntr |= DISPPLANE_BGRX555; |
2078 | break; |
2444 | break; |
2079 | case DRM_FORMAT_RGB565: |
2445 | case DRM_FORMAT_RGB565: |
2080 | dspcntr |= DISPPLANE_BGRX565; |
2446 | dspcntr |= DISPPLANE_BGRX565; |
2081 | break; |
2447 | break; |
2082 | case DRM_FORMAT_XRGB8888: |
2448 | case DRM_FORMAT_XRGB8888: |
2083 | case DRM_FORMAT_ARGB8888: |
2449 | case DRM_FORMAT_ARGB8888: |
2084 | dspcntr |= DISPPLANE_BGRX888; |
2450 | dspcntr |= DISPPLANE_BGRX888; |
2085 | break; |
2451 | break; |
2086 | case DRM_FORMAT_XBGR8888: |
2452 | case DRM_FORMAT_XBGR8888: |
2087 | case DRM_FORMAT_ABGR8888: |
2453 | case DRM_FORMAT_ABGR8888: |
2088 | dspcntr |= DISPPLANE_RGBX888; |
2454 | dspcntr |= DISPPLANE_RGBX888; |
2089 | break; |
2455 | break; |
2090 | case DRM_FORMAT_XRGB2101010: |
2456 | case DRM_FORMAT_XRGB2101010: |
2091 | case DRM_FORMAT_ARGB2101010: |
2457 | case DRM_FORMAT_ARGB2101010: |
2092 | dspcntr |= DISPPLANE_BGRX101010; |
2458 | dspcntr |= DISPPLANE_BGRX101010; |
2093 | break; |
2459 | break; |
2094 | case DRM_FORMAT_XBGR2101010: |
2460 | case DRM_FORMAT_XBGR2101010: |
2095 | case DRM_FORMAT_ABGR2101010: |
2461 | case DRM_FORMAT_ABGR2101010: |
2096 | dspcntr |= DISPPLANE_RGBX101010; |
2462 | dspcntr |= DISPPLANE_RGBX101010; |
2097 | break; |
2463 | break; |
2098 | default: |
2464 | default: |
2099 | BUG(); |
2465 | BUG(); |
2100 | } |
2466 | } |
2101 | 2467 | ||
2102 | if (INTEL_INFO(dev)->gen >= 4) { |
2468 | if (INTEL_INFO(dev)->gen >= 4) { |
2103 | if (obj->tiling_mode != I915_TILING_NONE) |
2469 | if (obj->tiling_mode != I915_TILING_NONE) |
2104 | dspcntr |= DISPPLANE_TILED; |
2470 | dspcntr |= DISPPLANE_TILED; |
2105 | else |
2471 | else |
2106 | dspcntr &= ~DISPPLANE_TILED; |
2472 | dspcntr &= ~DISPPLANE_TILED; |
2107 | } |
2473 | } |
2108 | 2474 | ||
2109 | if (IS_G4X(dev)) |
2475 | if (IS_G4X(dev)) |
2110 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2476 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2111 | 2477 | ||
2112 | I915_WRITE(reg, dspcntr); |
2478 | I915_WRITE(reg, dspcntr); |
2113 | 2479 | ||
2114 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2480 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2115 | 2481 | ||
2116 | if (INTEL_INFO(dev)->gen >= 4) { |
2482 | if (INTEL_INFO(dev)->gen >= 4) { |
2117 | intel_crtc->dspaddr_offset = |
2483 | intel_crtc->dspaddr_offset = |
2118 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2484 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2119 | fb->bits_per_pixel / 8, |
2485 | fb->bits_per_pixel / 8, |
2120 | fb->pitches[0]); |
2486 | fb->pitches[0]); |
2121 | linear_offset -= intel_crtc->dspaddr_offset; |
2487 | linear_offset -= intel_crtc->dspaddr_offset; |
2122 | } else { |
2488 | } else { |
2123 | intel_crtc->dspaddr_offset = linear_offset; |
2489 | intel_crtc->dspaddr_offset = linear_offset; |
2124 | } |
2490 | } |
2125 | 2491 | ||
2126 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2492 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2127 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2493 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2128 | fb->pitches[0]); |
2494 | fb->pitches[0]); |
2129 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2495 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2130 | if (INTEL_INFO(dev)->gen >= 4) { |
2496 | if (INTEL_INFO(dev)->gen >= 4) { |
2131 | I915_WRITE(DSPSURF(plane), |
2497 | I915_WRITE(DSPSURF(plane), |
2132 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2498 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2133 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2499 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2134 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2500 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2135 | } else |
2501 | } else |
2136 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2502 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2137 | POSTING_READ(reg); |
2503 | POSTING_READ(reg); |
2138 | - | ||
2139 | return 0; |
- | |
2140 | } |
2504 | } |
2141 | 2505 | ||
2142 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2506 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
- | 2507 | struct drm_framebuffer *fb, |
|
2143 | struct drm_framebuffer *fb, int x, int y) |
2508 | int x, int y) |
2144 | { |
2509 | { |
2145 | struct drm_device *dev = crtc->dev; |
2510 | struct drm_device *dev = crtc->dev; |
2146 | struct drm_i915_private *dev_priv = dev->dev_private; |
2511 | struct drm_i915_private *dev_priv = dev->dev_private; |
2147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2148 | struct intel_framebuffer *intel_fb; |
- | |
2149 | struct drm_i915_gem_object *obj; |
2513 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2150 | int plane = intel_crtc->plane; |
2514 | int plane = intel_crtc->plane; |
2151 | unsigned long linear_offset; |
2515 | unsigned long linear_offset; |
2152 | u32 dspcntr; |
2516 | u32 dspcntr; |
2153 | u32 reg; |
2517 | u32 reg; |
2154 | - | ||
2155 | switch (plane) { |
- | |
2156 | case 0: |
- | |
2157 | case 1: |
- | |
2158 | case 2: |
- | |
2159 | break; |
- | |
2160 | default: |
- | |
2161 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
- | |
2162 | return -EINVAL; |
- | |
2163 | } |
- | |
2164 | - | ||
2165 | intel_fb = to_intel_framebuffer(fb); |
- | |
2166 | obj = intel_fb->obj; |
- | |
2167 | 2518 | ||
2168 | reg = DSPCNTR(plane); |
2519 | reg = DSPCNTR(plane); |
2169 | dspcntr = I915_READ(reg); |
2520 | dspcntr = I915_READ(reg); |
2170 | /* Mask out pixel format bits in case we change it */ |
2521 | /* Mask out pixel format bits in case we change it */ |
2171 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2522 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2172 | switch (fb->pixel_format) { |
2523 | switch (fb->pixel_format) { |
2173 | case DRM_FORMAT_C8: |
2524 | case DRM_FORMAT_C8: |
2174 | dspcntr |= DISPPLANE_8BPP; |
2525 | dspcntr |= DISPPLANE_8BPP; |
2175 | break; |
2526 | break; |
2176 | case DRM_FORMAT_RGB565: |
2527 | case DRM_FORMAT_RGB565: |
2177 | dspcntr |= DISPPLANE_BGRX565; |
2528 | dspcntr |= DISPPLANE_BGRX565; |
2178 | break; |
2529 | break; |
2179 | case DRM_FORMAT_XRGB8888: |
2530 | case DRM_FORMAT_XRGB8888: |
2180 | case DRM_FORMAT_ARGB8888: |
2531 | case DRM_FORMAT_ARGB8888: |
2181 | dspcntr |= DISPPLANE_BGRX888; |
2532 | dspcntr |= DISPPLANE_BGRX888; |
2182 | break; |
2533 | break; |
2183 | case DRM_FORMAT_XBGR8888: |
2534 | case DRM_FORMAT_XBGR8888: |
2184 | case DRM_FORMAT_ABGR8888: |
2535 | case DRM_FORMAT_ABGR8888: |
2185 | dspcntr |= DISPPLANE_RGBX888; |
2536 | dspcntr |= DISPPLANE_RGBX888; |
2186 | break; |
2537 | break; |
2187 | case DRM_FORMAT_XRGB2101010: |
2538 | case DRM_FORMAT_XRGB2101010: |
2188 | case DRM_FORMAT_ARGB2101010: |
2539 | case DRM_FORMAT_ARGB2101010: |
2189 | dspcntr |= DISPPLANE_BGRX101010; |
2540 | dspcntr |= DISPPLANE_BGRX101010; |
2190 | break; |
2541 | break; |
2191 | case DRM_FORMAT_XBGR2101010: |
2542 | case DRM_FORMAT_XBGR2101010: |
2192 | case DRM_FORMAT_ABGR2101010: |
2543 | case DRM_FORMAT_ABGR2101010: |
2193 | dspcntr |= DISPPLANE_RGBX101010; |
2544 | dspcntr |= DISPPLANE_RGBX101010; |
2194 | break; |
2545 | break; |
2195 | default: |
2546 | default: |
2196 | BUG(); |
2547 | BUG(); |
2197 | } |
2548 | } |
2198 | 2549 | ||
2199 | if (obj->tiling_mode != I915_TILING_NONE) |
2550 | if (obj->tiling_mode != I915_TILING_NONE) |
2200 | dspcntr |= DISPPLANE_TILED; |
2551 | dspcntr |= DISPPLANE_TILED; |
2201 | else |
2552 | else |
2202 | dspcntr &= ~DISPPLANE_TILED; |
2553 | dspcntr &= ~DISPPLANE_TILED; |
2203 | 2554 | ||
2204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2555 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2205 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2556 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2206 | else |
2557 | else |
2207 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2558 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2208 | 2559 | ||
2209 | I915_WRITE(reg, dspcntr); |
2560 | I915_WRITE(reg, dspcntr); |
2210 | 2561 | ||
2211 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2562 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2212 | intel_crtc->dspaddr_offset = |
2563 | intel_crtc->dspaddr_offset = |
2213 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2564 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2214 | fb->bits_per_pixel / 8, |
2565 | fb->bits_per_pixel / 8, |
2215 | fb->pitches[0]); |
2566 | fb->pitches[0]); |
2216 | linear_offset -= intel_crtc->dspaddr_offset; |
2567 | linear_offset -= intel_crtc->dspaddr_offset; |
2217 | 2568 | ||
2218 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2569 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2219 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2570 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2220 | fb->pitches[0]); |
2571 | fb->pitches[0]); |
2221 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2572 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2222 | I915_WRITE(DSPSURF(plane), |
2573 | I915_WRITE(DSPSURF(plane), |
2223 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2574 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2224 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2575 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2225 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2576 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2226 | } else { |
2577 | } else { |
2227 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2578 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2228 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2579 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2229 | } |
2580 | } |
2230 | POSTING_READ(reg); |
2581 | POSTING_READ(reg); |
2231 | - | ||
2232 | return 0; |
- | |
2233 | } |
2582 | } |
2234 | 2583 | ||
2235 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2584 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2236 | static int |
2585 | static int |
2237 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2586 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2238 | int x, int y, enum mode_set_atomic state) |
2587 | int x, int y, enum mode_set_atomic state) |
2239 | { |
2588 | { |
2240 | struct drm_device *dev = crtc->dev; |
2589 | struct drm_device *dev = crtc->dev; |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; |
2590 | struct drm_i915_private *dev_priv = dev->dev_private; |
2242 | 2591 | ||
2243 | if (dev_priv->display.disable_fbc) |
2592 | if (dev_priv->display.disable_fbc) |
2244 | dev_priv->display.disable_fbc(dev); |
2593 | dev_priv->display.disable_fbc(dev); |
2245 | intel_increase_pllclock(crtc); |
2594 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
- | 2595 | ||
- | 2596 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
|
2246 | 2597 | ||
2247 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2598 | return 0; |
2248 | } |
2599 | } |
2249 | 2600 | ||
2250 | #if 0 |
2601 | #if 0 |
2251 | void intel_display_handle_reset(struct drm_device *dev) |
2602 | void intel_display_handle_reset(struct drm_device *dev) |
2252 | { |
2603 | { |
2253 | struct drm_i915_private *dev_priv = dev->dev_private; |
2604 | struct drm_i915_private *dev_priv = dev->dev_private; |
2254 | struct drm_crtc *crtc; |
2605 | struct drm_crtc *crtc; |
2255 | 2606 | ||
2256 | /* |
2607 | /* |
2257 | * Flips in the rings have been nuked by the reset, |
2608 | * Flips in the rings have been nuked by the reset, |
2258 | * so complete all pending flips so that user space |
2609 | * so complete all pending flips so that user space |
2259 | * will get its events and not get stuck. |
2610 | * will get its events and not get stuck. |
2260 | * |
2611 | * |
2261 | * Also update the base address of all primary |
2612 | * Also update the base address of all primary |
2262 | * planes to the the last fb to make sure we're |
2613 | * planes to the the last fb to make sure we're |
2263 | * showing the correct fb after a reset. |
2614 | * showing the correct fb after a reset. |
2264 | * |
2615 | * |
2265 | * Need to make two loops over the crtcs so that we |
2616 | * Need to make two loops over the crtcs so that we |
2266 | * don't try to grab a crtc mutex before the |
2617 | * don't try to grab a crtc mutex before the |
2267 | * pending_flip_queue really got woken up. |
2618 | * pending_flip_queue really got woken up. |
2268 | */ |
2619 | */ |
2269 | 2620 | ||
2270 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2621 | for_each_crtc(dev, crtc) { |
2271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2272 | enum plane plane = intel_crtc->plane; |
2623 | enum plane plane = intel_crtc->plane; |
2273 | 2624 | ||
2274 | intel_prepare_page_flip(dev, plane); |
2625 | intel_prepare_page_flip(dev, plane); |
2275 | intel_finish_page_flip_plane(dev, plane); |
2626 | intel_finish_page_flip_plane(dev, plane); |
2276 | } |
2627 | } |
2277 | 2628 | ||
2278 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2629 | for_each_crtc(dev, crtc) { |
2279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2280 | 2631 | ||
2281 | mutex_lock(&crtc->mutex); |
2632 | drm_modeset_lock(&crtc->mutex, NULL); |
2282 | /* |
2633 | /* |
2283 | * FIXME: Once we have proper support for primary planes (and |
2634 | * FIXME: Once we have proper support for primary planes (and |
2284 | * disabling them without disabling the entire crtc) allow again |
2635 | * disabling them without disabling the entire crtc) allow again |
2285 | * a NULL crtc->fb. |
2636 | * a NULL crtc->primary->fb. |
2286 | */ |
2637 | */ |
2287 | if (intel_crtc->active && crtc->fb) |
2638 | if (intel_crtc->active && crtc->primary->fb) |
2288 | dev_priv->display.update_plane(crtc, crtc->fb, |
2639 | dev_priv->display.update_primary_plane(crtc, |
- | 2640 | crtc->primary->fb, |
|
- | 2641 | crtc->x, |
|
2289 | crtc->x, crtc->y); |
2642 | crtc->y); |
2290 | mutex_unlock(&crtc->mutex); |
2643 | drm_modeset_unlock(&crtc->mutex); |
2291 | } |
2644 | } |
2292 | } |
2645 | } |
2293 | 2646 | ||
2294 | static int |
2647 | static int |
2295 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2648 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2296 | { |
2649 | { |
2297 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2650 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2298 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2651 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2299 | bool was_interruptible = dev_priv->mm.interruptible; |
2652 | bool was_interruptible = dev_priv->mm.interruptible; |
2300 | int ret; |
2653 | int ret; |
2301 | 2654 | ||
2302 | /* Big Hammer, we also need to ensure that any pending |
2655 | /* Big Hammer, we also need to ensure that any pending |
2303 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2656 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2304 | * current scanout is retired before unpinning the old |
2657 | * current scanout is retired before unpinning the old |
2305 | * framebuffer. |
2658 | * framebuffer. |
2306 | * |
2659 | * |
2307 | * This should only fail upon a hung GPU, in which case we |
2660 | * This should only fail upon a hung GPU, in which case we |
2308 | * can safely continue. |
2661 | * can safely continue. |
2309 | */ |
2662 | */ |
2310 | dev_priv->mm.interruptible = false; |
2663 | dev_priv->mm.interruptible = false; |
2311 | ret = i915_gem_object_finish_gpu(obj); |
2664 | ret = i915_gem_object_finish_gpu(obj); |
2312 | dev_priv->mm.interruptible = was_interruptible; |
2665 | dev_priv->mm.interruptible = was_interruptible; |
2313 | 2666 | ||
2314 | return ret; |
2667 | return ret; |
2315 | } |
2668 | } |
2316 | 2669 | ||
2317 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2670 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2318 | { |
2671 | { |
2319 | struct drm_device *dev = crtc->dev; |
2672 | struct drm_device *dev = crtc->dev; |
2320 | struct drm_i915_master_private *master_priv; |
2673 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 2674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 2675 | unsigned long flags; |
|
2321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2676 | bool pending; |
- | 2677 | ||
2322 | 2678 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
|
2323 | if (!dev->primary->master) |
2679 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2324 | return; |
2680 | return false; |
2325 | 2681 | ||
2326 | master_priv = dev->primary->master->driver_priv; |
- | |
2327 | if (!master_priv->sarea_priv) |
- | |
2328 | return; |
- | |
2329 | - | ||
2330 | switch (intel_crtc->pipe) { |
2682 | spin_lock_irqsave(&dev->event_lock, flags); |
2331 | case 0: |
- | |
2332 | master_priv->sarea_priv->pipeA_x = x; |
- | |
2333 | master_priv->sarea_priv->pipeA_y = y; |
- | |
2334 | break; |
- | |
2335 | case 1: |
- | |
2336 | master_priv->sarea_priv->pipeB_x = x; |
- | |
2337 | master_priv->sarea_priv->pipeB_y = y; |
- | |
2338 | break; |
2683 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2339 | default: |
2684 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2340 | break; |
2685 | |
2341 | } |
2686 | return pending; |
2342 | } |
2687 | } |
2343 | #endif |
2688 | #endif |
2344 | 2689 | ||
2345 | static int |
2690 | static int |
2346 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2691 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2347 | struct drm_framebuffer *fb) |
2692 | struct drm_framebuffer *fb) |
2348 | { |
2693 | { |
2349 | struct drm_device *dev = crtc->dev; |
2694 | struct drm_device *dev = crtc->dev; |
2350 | struct drm_i915_private *dev_priv = dev->dev_private; |
2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
2351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 2697 | enum pipe pipe = intel_crtc->pipe; |
|
2352 | struct drm_framebuffer *old_fb; |
2698 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
- | 2699 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
- | 2700 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
|
2353 | int ret; |
2701 | int ret; |
- | 2702 | ||
2354 | 2703 | ||
2355 | /* no fb bound */ |
2704 | /* no fb bound */ |
2356 | if (!fb) { |
2705 | if (!fb) { |
2357 | DRM_ERROR("No FB bound\n"); |
2706 | DRM_ERROR("No FB bound\n"); |
2358 | return 0; |
2707 | return 0; |
2359 | } |
2708 | } |
2360 | 2709 | ||
2361 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2710 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2362 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2711 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2363 | plane_name(intel_crtc->plane), |
2712 | plane_name(intel_crtc->plane), |
2364 | INTEL_INFO(dev)->num_pipes); |
2713 | INTEL_INFO(dev)->num_pipes); |
2365 | return -EINVAL; |
2714 | return -EINVAL; |
2366 | } |
2715 | } |
2367 | 2716 | ||
2368 | mutex_lock(&dev->struct_mutex); |
2717 | mutex_lock(&dev->struct_mutex); |
2369 | ret = intel_pin_and_fence_fb_obj(dev, |
2718 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
- | 2719 | if (ret == 0) |
|
2370 | to_intel_framebuffer(fb)->obj, |
2720 | i915_gem_track_fb(old_obj, obj, |
2371 | NULL); |
2721 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
2372 | if (ret != 0) { |
- | |
2373 | mutex_unlock(&dev->struct_mutex); |
2722 | mutex_unlock(&dev->struct_mutex); |
- | 2723 | if (ret != 0) { |
|
2374 | DRM_ERROR("pin & fence failed\n"); |
2724 | DRM_ERROR("pin & fence failed\n"); |
2375 | return ret; |
2725 | return ret; |
2376 | } |
2726 | } |
2377 | 2727 | ||
2378 | /* |
2728 | /* |
2379 | * Update pipe size and adjust fitter if needed: the reason for this is |
2729 | * Update pipe size and adjust fitter if needed: the reason for this is |
2380 | * that in compute_mode_changes we check the native mode (not the pfit |
2730 | * that in compute_mode_changes we check the native mode (not the pfit |
2381 | * mode) to see if we can flip rather than do a full mode set. In the |
2731 | * mode) to see if we can flip rather than do a full mode set. In the |
2382 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
2732 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
2383 | * pfit state, we'll end up with a big fb scanned out into the wrong |
2733 | * pfit state, we'll end up with a big fb scanned out into the wrong |
2384 | * sized surface. |
2734 | * sized surface. |
2385 | * |
2735 | * |
2386 | * To fix this properly, we need to hoist the checks up into |
2736 | * To fix this properly, we need to hoist the checks up into |
2387 | * compute_mode_changes (or above), check the actual pfit state and |
2737 | * compute_mode_changes (or above), check the actual pfit state and |
2388 | * whether the platform allows pfit disable with pipe active, and only |
2738 | * whether the platform allows pfit disable with pipe active, and only |
2389 | * then update the pipesrc and pfit state, even on the flip path. |
2739 | * then update the pipesrc and pfit state, even on the flip path. |
2390 | */ |
2740 | */ |
2391 | if (i915_fastboot) { |
2741 | if (i915.fastboot) { |
2392 | const struct drm_display_mode *adjusted_mode = |
2742 | const struct drm_display_mode *adjusted_mode = |
2393 | &intel_crtc->config.adjusted_mode; |
2743 | &intel_crtc->config.adjusted_mode; |
2394 | 2744 | ||
2395 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2745 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2396 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2746 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2397 | (adjusted_mode->crtc_vdisplay - 1)); |
2747 | (adjusted_mode->crtc_vdisplay - 1)); |
2398 | if (!intel_crtc->config.pch_pfit.enabled && |
2748 | if (!intel_crtc->config.pch_pfit.enabled && |
2399 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2749 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2400 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2750 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2401 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2751 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2402 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2752 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2403 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2753 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2404 | } |
2754 | } |
2405 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2755 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2406 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
2756 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
2407 | } |
2757 | } |
2408 | 2758 | ||
2409 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2759 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2410 | if (ret) { |
- | |
2411 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2760 | |
2412 | mutex_unlock(&dev->struct_mutex); |
2761 | if (intel_crtc->active) |
2413 | DRM_ERROR("failed to update base address\n"); |
- | |
2414 | return ret; |
- | |
2415 | } |
- | |
2416 | 2762 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
2417 | old_fb = crtc->fb; |
2763 | |
2418 | crtc->fb = fb; |
2764 | crtc->primary->fb = fb; |
2419 | crtc->x = x; |
2765 | crtc->x = x; |
2420 | crtc->y = y; |
2766 | crtc->y = y; |
2421 | 2767 | ||
2422 | if (old_fb) { |
2768 | if (old_fb) { |
2423 | if (intel_crtc->active && old_fb != fb) |
2769 | if (intel_crtc->active && old_fb != fb) |
2424 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2770 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
- | 2771 | mutex_lock(&dev->struct_mutex); |
|
2425 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2772 | intel_unpin_fb_obj(old_obj); |
- | 2773 | mutex_unlock(&dev->struct_mutex); |
|
2426 | } |
2774 | } |
- | 2775 | ||
2427 | 2776 | mutex_lock(&dev->struct_mutex); |
|
2428 | intel_update_fbc(dev); |
- | |
2429 | intel_edp_psr_update(dev); |
2777 | intel_update_fbc(dev); |
2430 | mutex_unlock(&dev->struct_mutex); |
2778 | mutex_unlock(&dev->struct_mutex); |
2431 | 2779 | ||
2432 | return 0; |
2780 | return 0; |
2433 | } |
2781 | } |
2434 | 2782 | ||
2435 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2783 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2436 | { |
2784 | { |
2437 | struct drm_device *dev = crtc->dev; |
2785 | struct drm_device *dev = crtc->dev; |
2438 | struct drm_i915_private *dev_priv = dev->dev_private; |
2786 | struct drm_i915_private *dev_priv = dev->dev_private; |
2439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2440 | int pipe = intel_crtc->pipe; |
2788 | int pipe = intel_crtc->pipe; |
2441 | u32 reg, temp; |
2789 | u32 reg, temp; |
2442 | 2790 | ||
2443 | /* enable normal train */ |
2791 | /* enable normal train */ |
2444 | reg = FDI_TX_CTL(pipe); |
2792 | reg = FDI_TX_CTL(pipe); |
2445 | temp = I915_READ(reg); |
2793 | temp = I915_READ(reg); |
2446 | if (IS_IVYBRIDGE(dev)) { |
2794 | if (IS_IVYBRIDGE(dev)) { |
2447 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2795 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2448 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2796 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2449 | } else { |
2797 | } else { |
2450 | temp &= ~FDI_LINK_TRAIN_NONE; |
2798 | temp &= ~FDI_LINK_TRAIN_NONE; |
2451 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2799 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2452 | } |
2800 | } |
2453 | I915_WRITE(reg, temp); |
2801 | I915_WRITE(reg, temp); |
2454 | 2802 | ||
2455 | reg = FDI_RX_CTL(pipe); |
2803 | reg = FDI_RX_CTL(pipe); |
2456 | temp = I915_READ(reg); |
2804 | temp = I915_READ(reg); |
2457 | if (HAS_PCH_CPT(dev)) { |
2805 | if (HAS_PCH_CPT(dev)) { |
2458 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2806 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2459 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2807 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2460 | } else { |
2808 | } else { |
2461 | temp &= ~FDI_LINK_TRAIN_NONE; |
2809 | temp &= ~FDI_LINK_TRAIN_NONE; |
2462 | temp |= FDI_LINK_TRAIN_NONE; |
2810 | temp |= FDI_LINK_TRAIN_NONE; |
2463 | } |
2811 | } |
2464 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2812 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2465 | 2813 | ||
2466 | /* wait one idle pattern time */ |
2814 | /* wait one idle pattern time */ |
2467 | POSTING_READ(reg); |
2815 | POSTING_READ(reg); |
2468 | udelay(1000); |
2816 | udelay(1000); |
2469 | 2817 | ||
2470 | /* IVB wants error correction enabled */ |
2818 | /* IVB wants error correction enabled */ |
2471 | if (IS_IVYBRIDGE(dev)) |
2819 | if (IS_IVYBRIDGE(dev)) |
2472 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2820 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2473 | FDI_FE_ERRC_ENABLE); |
2821 | FDI_FE_ERRC_ENABLE); |
2474 | } |
2822 | } |
2475 | 2823 | ||
2476 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2824 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2477 | { |
2825 | { |
2478 | return crtc->base.enabled && crtc->active && |
2826 | return crtc->base.enabled && crtc->active && |
2479 | crtc->config.has_pch_encoder; |
2827 | crtc->config.has_pch_encoder; |
2480 | } |
2828 | } |
2481 | 2829 | ||
2482 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2830 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2483 | { |
2831 | { |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; |
2832 | struct drm_i915_private *dev_priv = dev->dev_private; |
2485 | struct intel_crtc *pipe_B_crtc = |
2833 | struct intel_crtc *pipe_B_crtc = |
2486 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2834 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2487 | struct intel_crtc *pipe_C_crtc = |
2835 | struct intel_crtc *pipe_C_crtc = |
2488 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2836 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2489 | uint32_t temp; |
2837 | uint32_t temp; |
2490 | 2838 | ||
2491 | /* |
2839 | /* |
2492 | * When everything is off disable fdi C so that we could enable fdi B |
2840 | * When everything is off disable fdi C so that we could enable fdi B |
2493 | * with all lanes. Note that we don't care about enabled pipes without |
2841 | * with all lanes. Note that we don't care about enabled pipes without |
2494 | * an enabled pch encoder. |
2842 | * an enabled pch encoder. |
2495 | */ |
2843 | */ |
2496 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2844 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2497 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2845 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2498 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2846 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2499 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2847 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2500 | 2848 | ||
2501 | temp = I915_READ(SOUTH_CHICKEN1); |
2849 | temp = I915_READ(SOUTH_CHICKEN1); |
2502 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2850 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2503 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2851 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2504 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2852 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2505 | } |
2853 | } |
2506 | } |
2854 | } |
2507 | 2855 | ||
2508 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2856 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2509 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2857 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2510 | { |
2858 | { |
2511 | struct drm_device *dev = crtc->dev; |
2859 | struct drm_device *dev = crtc->dev; |
2512 | struct drm_i915_private *dev_priv = dev->dev_private; |
2860 | struct drm_i915_private *dev_priv = dev->dev_private; |
2513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2514 | int pipe = intel_crtc->pipe; |
2862 | int pipe = intel_crtc->pipe; |
2515 | int plane = intel_crtc->plane; |
- | |
2516 | u32 reg, temp, tries; |
2863 | u32 reg, temp, tries; |
2517 | 2864 | ||
2518 | /* FDI needs bits from pipe & plane first */ |
2865 | /* FDI needs bits from pipe first */ |
2519 | assert_pipe_enabled(dev_priv, pipe); |
- | |
2520 | assert_plane_enabled(dev_priv, plane); |
2866 | assert_pipe_enabled(dev_priv, pipe); |
2521 | 2867 | ||
2522 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2868 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2523 | for train result */ |
2869 | for train result */ |
2524 | reg = FDI_RX_IMR(pipe); |
2870 | reg = FDI_RX_IMR(pipe); |
2525 | temp = I915_READ(reg); |
2871 | temp = I915_READ(reg); |
2526 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2872 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2527 | temp &= ~FDI_RX_BIT_LOCK; |
2873 | temp &= ~FDI_RX_BIT_LOCK; |
2528 | I915_WRITE(reg, temp); |
2874 | I915_WRITE(reg, temp); |
2529 | I915_READ(reg); |
2875 | I915_READ(reg); |
2530 | udelay(150); |
2876 | udelay(150); |
2531 | 2877 | ||
2532 | /* enable CPU FDI TX and PCH FDI RX */ |
2878 | /* enable CPU FDI TX and PCH FDI RX */ |
2533 | reg = FDI_TX_CTL(pipe); |
2879 | reg = FDI_TX_CTL(pipe); |
2534 | temp = I915_READ(reg); |
2880 | temp = I915_READ(reg); |
2535 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2881 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2536 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2882 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2537 | temp &= ~FDI_LINK_TRAIN_NONE; |
2883 | temp &= ~FDI_LINK_TRAIN_NONE; |
2538 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2884 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2539 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2885 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2540 | 2886 | ||
2541 | reg = FDI_RX_CTL(pipe); |
2887 | reg = FDI_RX_CTL(pipe); |
2542 | temp = I915_READ(reg); |
2888 | temp = I915_READ(reg); |
2543 | temp &= ~FDI_LINK_TRAIN_NONE; |
2889 | temp &= ~FDI_LINK_TRAIN_NONE; |
2544 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2890 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2545 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2891 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2546 | 2892 | ||
2547 | POSTING_READ(reg); |
2893 | POSTING_READ(reg); |
2548 | udelay(150); |
2894 | udelay(150); |
2549 | 2895 | ||
2550 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2896 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2551 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2897 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2552 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2898 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2553 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2899 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2554 | 2900 | ||
2555 | reg = FDI_RX_IIR(pipe); |
2901 | reg = FDI_RX_IIR(pipe); |
2556 | for (tries = 0; tries < 5; tries++) { |
2902 | for (tries = 0; tries < 5; tries++) { |
2557 | temp = I915_READ(reg); |
2903 | temp = I915_READ(reg); |
2558 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2904 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2559 | 2905 | ||
2560 | if ((temp & FDI_RX_BIT_LOCK)) { |
2906 | if ((temp & FDI_RX_BIT_LOCK)) { |
2561 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2907 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2562 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2908 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2563 | break; |
2909 | break; |
2564 | } |
2910 | } |
2565 | } |
2911 | } |
2566 | if (tries == 5) |
2912 | if (tries == 5) |
2567 | DRM_ERROR("FDI train 1 fail!\n"); |
2913 | DRM_ERROR("FDI train 1 fail!\n"); |
2568 | 2914 | ||
2569 | /* Train 2 */ |
2915 | /* Train 2 */ |
2570 | reg = FDI_TX_CTL(pipe); |
2916 | reg = FDI_TX_CTL(pipe); |
2571 | temp = I915_READ(reg); |
2917 | temp = I915_READ(reg); |
2572 | temp &= ~FDI_LINK_TRAIN_NONE; |
2918 | temp &= ~FDI_LINK_TRAIN_NONE; |
2573 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2919 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2574 | I915_WRITE(reg, temp); |
2920 | I915_WRITE(reg, temp); |
2575 | 2921 | ||
2576 | reg = FDI_RX_CTL(pipe); |
2922 | reg = FDI_RX_CTL(pipe); |
2577 | temp = I915_READ(reg); |
2923 | temp = I915_READ(reg); |
2578 | temp &= ~FDI_LINK_TRAIN_NONE; |
2924 | temp &= ~FDI_LINK_TRAIN_NONE; |
2579 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2925 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2580 | I915_WRITE(reg, temp); |
2926 | I915_WRITE(reg, temp); |
2581 | 2927 | ||
2582 | POSTING_READ(reg); |
2928 | POSTING_READ(reg); |
2583 | udelay(150); |
2929 | udelay(150); |
2584 | 2930 | ||
2585 | reg = FDI_RX_IIR(pipe); |
2931 | reg = FDI_RX_IIR(pipe); |
2586 | for (tries = 0; tries < 5; tries++) { |
2932 | for (tries = 0; tries < 5; tries++) { |
2587 | temp = I915_READ(reg); |
2933 | temp = I915_READ(reg); |
2588 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2934 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2589 | 2935 | ||
2590 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2936 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2591 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2937 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2592 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2938 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2593 | break; |
2939 | break; |
2594 | } |
2940 | } |
2595 | } |
2941 | } |
2596 | if (tries == 5) |
2942 | if (tries == 5) |
2597 | DRM_ERROR("FDI train 2 fail!\n"); |
2943 | DRM_ERROR("FDI train 2 fail!\n"); |
2598 | 2944 | ||
2599 | DRM_DEBUG_KMS("FDI train done\n"); |
2945 | DRM_DEBUG_KMS("FDI train done\n"); |
2600 | 2946 | ||
2601 | } |
2947 | } |
2602 | 2948 | ||
2603 | static const int snb_b_fdi_train_param[] = { |
2949 | static const int snb_b_fdi_train_param[] = { |
2604 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2950 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2605 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2951 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2606 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2952 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2607 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2953 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2608 | }; |
2954 | }; |
2609 | 2955 | ||
2610 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2956 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2611 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2957 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2612 | { |
2958 | { |
2613 | struct drm_device *dev = crtc->dev; |
2959 | struct drm_device *dev = crtc->dev; |
2614 | struct drm_i915_private *dev_priv = dev->dev_private; |
2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
2615 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2616 | int pipe = intel_crtc->pipe; |
2962 | int pipe = intel_crtc->pipe; |
2617 | u32 reg, temp, i, retry; |
2963 | u32 reg, temp, i, retry; |
2618 | 2964 | ||
2619 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2965 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2620 | for train result */ |
2966 | for train result */ |
2621 | reg = FDI_RX_IMR(pipe); |
2967 | reg = FDI_RX_IMR(pipe); |
2622 | temp = I915_READ(reg); |
2968 | temp = I915_READ(reg); |
2623 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2969 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2624 | temp &= ~FDI_RX_BIT_LOCK; |
2970 | temp &= ~FDI_RX_BIT_LOCK; |
2625 | I915_WRITE(reg, temp); |
2971 | I915_WRITE(reg, temp); |
2626 | 2972 | ||
2627 | POSTING_READ(reg); |
2973 | POSTING_READ(reg); |
2628 | udelay(150); |
2974 | udelay(150); |
2629 | 2975 | ||
2630 | /* enable CPU FDI TX and PCH FDI RX */ |
2976 | /* enable CPU FDI TX and PCH FDI RX */ |
2631 | reg = FDI_TX_CTL(pipe); |
2977 | reg = FDI_TX_CTL(pipe); |
2632 | temp = I915_READ(reg); |
2978 | temp = I915_READ(reg); |
2633 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2979 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2634 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2980 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2635 | temp &= ~FDI_LINK_TRAIN_NONE; |
2981 | temp &= ~FDI_LINK_TRAIN_NONE; |
2636 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2982 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2637 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2983 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2638 | /* SNB-B */ |
2984 | /* SNB-B */ |
2639 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2985 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2640 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2986 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2641 | 2987 | ||
2642 | I915_WRITE(FDI_RX_MISC(pipe), |
2988 | I915_WRITE(FDI_RX_MISC(pipe), |
2643 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2989 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2644 | 2990 | ||
2645 | reg = FDI_RX_CTL(pipe); |
2991 | reg = FDI_RX_CTL(pipe); |
2646 | temp = I915_READ(reg); |
2992 | temp = I915_READ(reg); |
2647 | if (HAS_PCH_CPT(dev)) { |
2993 | if (HAS_PCH_CPT(dev)) { |
2648 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2994 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2649 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2995 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2650 | } else { |
2996 | } else { |
2651 | temp &= ~FDI_LINK_TRAIN_NONE; |
2997 | temp &= ~FDI_LINK_TRAIN_NONE; |
2652 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2998 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2653 | } |
2999 | } |
2654 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3000 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2655 | 3001 | ||
2656 | POSTING_READ(reg); |
3002 | POSTING_READ(reg); |
2657 | udelay(150); |
3003 | udelay(150); |
2658 | 3004 | ||
2659 | for (i = 0; i < 4; i++) { |
3005 | for (i = 0; i < 4; i++) { |
2660 | reg = FDI_TX_CTL(pipe); |
3006 | reg = FDI_TX_CTL(pipe); |
2661 | temp = I915_READ(reg); |
3007 | temp = I915_READ(reg); |
2662 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3008 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2663 | temp |= snb_b_fdi_train_param[i]; |
3009 | temp |= snb_b_fdi_train_param[i]; |
2664 | I915_WRITE(reg, temp); |
3010 | I915_WRITE(reg, temp); |
2665 | 3011 | ||
2666 | POSTING_READ(reg); |
3012 | POSTING_READ(reg); |
2667 | udelay(500); |
3013 | udelay(500); |
2668 | 3014 | ||
2669 | for (retry = 0; retry < 5; retry++) { |
3015 | for (retry = 0; retry < 5; retry++) { |
2670 | reg = FDI_RX_IIR(pipe); |
3016 | reg = FDI_RX_IIR(pipe); |
2671 | temp = I915_READ(reg); |
3017 | temp = I915_READ(reg); |
2672 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3018 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2673 | if (temp & FDI_RX_BIT_LOCK) { |
3019 | if (temp & FDI_RX_BIT_LOCK) { |
2674 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
3020 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2675 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
3021 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2676 | break; |
3022 | break; |
2677 | } |
3023 | } |
2678 | udelay(50); |
3024 | udelay(50); |
2679 | } |
3025 | } |
2680 | if (retry < 5) |
3026 | if (retry < 5) |
2681 | break; |
3027 | break; |
2682 | } |
3028 | } |
2683 | if (i == 4) |
3029 | if (i == 4) |
2684 | DRM_ERROR("FDI train 1 fail!\n"); |
3030 | DRM_ERROR("FDI train 1 fail!\n"); |
2685 | 3031 | ||
2686 | /* Train 2 */ |
3032 | /* Train 2 */ |
2687 | reg = FDI_TX_CTL(pipe); |
3033 | reg = FDI_TX_CTL(pipe); |
2688 | temp = I915_READ(reg); |
3034 | temp = I915_READ(reg); |
2689 | temp &= ~FDI_LINK_TRAIN_NONE; |
3035 | temp &= ~FDI_LINK_TRAIN_NONE; |
2690 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
3036 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2691 | if (IS_GEN6(dev)) { |
3037 | if (IS_GEN6(dev)) { |
2692 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3038 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2693 | /* SNB-B */ |
3039 | /* SNB-B */ |
2694 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
3040 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2695 | } |
3041 | } |
2696 | I915_WRITE(reg, temp); |
3042 | I915_WRITE(reg, temp); |
2697 | 3043 | ||
2698 | reg = FDI_RX_CTL(pipe); |
3044 | reg = FDI_RX_CTL(pipe); |
2699 | temp = I915_READ(reg); |
3045 | temp = I915_READ(reg); |
2700 | if (HAS_PCH_CPT(dev)) { |
3046 | if (HAS_PCH_CPT(dev)) { |
2701 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3047 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2702 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
3048 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2703 | } else { |
3049 | } else { |
2704 | temp &= ~FDI_LINK_TRAIN_NONE; |
3050 | temp &= ~FDI_LINK_TRAIN_NONE; |
2705 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
3051 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2706 | } |
3052 | } |
2707 | I915_WRITE(reg, temp); |
3053 | I915_WRITE(reg, temp); |
2708 | 3054 | ||
2709 | POSTING_READ(reg); |
3055 | POSTING_READ(reg); |
2710 | udelay(150); |
3056 | udelay(150); |
2711 | 3057 | ||
2712 | for (i = 0; i < 4; i++) { |
3058 | for (i = 0; i < 4; i++) { |
2713 | reg = FDI_TX_CTL(pipe); |
3059 | reg = FDI_TX_CTL(pipe); |
2714 | temp = I915_READ(reg); |
3060 | temp = I915_READ(reg); |
2715 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3061 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2716 | temp |= snb_b_fdi_train_param[i]; |
3062 | temp |= snb_b_fdi_train_param[i]; |
2717 | I915_WRITE(reg, temp); |
3063 | I915_WRITE(reg, temp); |
2718 | 3064 | ||
2719 | POSTING_READ(reg); |
3065 | POSTING_READ(reg); |
2720 | udelay(500); |
3066 | udelay(500); |
2721 | 3067 | ||
2722 | for (retry = 0; retry < 5; retry++) { |
3068 | for (retry = 0; retry < 5; retry++) { |
2723 | reg = FDI_RX_IIR(pipe); |
3069 | reg = FDI_RX_IIR(pipe); |
2724 | temp = I915_READ(reg); |
3070 | temp = I915_READ(reg); |
2725 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3071 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2726 | if (temp & FDI_RX_SYMBOL_LOCK) { |
3072 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2727 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
3073 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2728 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3074 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2729 | break; |
3075 | break; |
2730 | } |
3076 | } |
2731 | udelay(50); |
3077 | udelay(50); |
2732 | } |
3078 | } |
2733 | if (retry < 5) |
3079 | if (retry < 5) |
2734 | break; |
3080 | break; |
2735 | } |
3081 | } |
2736 | if (i == 4) |
3082 | if (i == 4) |
2737 | DRM_ERROR("FDI train 2 fail!\n"); |
3083 | DRM_ERROR("FDI train 2 fail!\n"); |
2738 | 3084 | ||
2739 | DRM_DEBUG_KMS("FDI train done.\n"); |
3085 | DRM_DEBUG_KMS("FDI train done.\n"); |
2740 | } |
3086 | } |
2741 | 3087 | ||
2742 | /* Manual link training for Ivy Bridge A0 parts */ |
3088 | /* Manual link training for Ivy Bridge A0 parts */ |
2743 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
3089 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2744 | { |
3090 | { |
2745 | struct drm_device *dev = crtc->dev; |
3091 | struct drm_device *dev = crtc->dev; |
2746 | struct drm_i915_private *dev_priv = dev->dev_private; |
3092 | struct drm_i915_private *dev_priv = dev->dev_private; |
2747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2748 | int pipe = intel_crtc->pipe; |
3094 | int pipe = intel_crtc->pipe; |
2749 | u32 reg, temp, i, j; |
3095 | u32 reg, temp, i, j; |
2750 | 3096 | ||
2751 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3097 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2752 | for train result */ |
3098 | for train result */ |
2753 | reg = FDI_RX_IMR(pipe); |
3099 | reg = FDI_RX_IMR(pipe); |
2754 | temp = I915_READ(reg); |
3100 | temp = I915_READ(reg); |
2755 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3101 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2756 | temp &= ~FDI_RX_BIT_LOCK; |
3102 | temp &= ~FDI_RX_BIT_LOCK; |
2757 | I915_WRITE(reg, temp); |
3103 | I915_WRITE(reg, temp); |
2758 | 3104 | ||
2759 | POSTING_READ(reg); |
3105 | POSTING_READ(reg); |
2760 | udelay(150); |
3106 | udelay(150); |
2761 | 3107 | ||
2762 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3108 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2763 | I915_READ(FDI_RX_IIR(pipe))); |
3109 | I915_READ(FDI_RX_IIR(pipe))); |
2764 | 3110 | ||
2765 | /* Try each vswing and preemphasis setting twice before moving on */ |
3111 | /* Try each vswing and preemphasis setting twice before moving on */ |
2766 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
3112 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2767 | /* disable first in case we need to retry */ |
3113 | /* disable first in case we need to retry */ |
2768 | reg = FDI_TX_CTL(pipe); |
3114 | reg = FDI_TX_CTL(pipe); |
2769 | temp = I915_READ(reg); |
3115 | temp = I915_READ(reg); |
2770 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
3116 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2771 | temp &= ~FDI_TX_ENABLE; |
3117 | temp &= ~FDI_TX_ENABLE; |
2772 | I915_WRITE(reg, temp); |
3118 | I915_WRITE(reg, temp); |
2773 | 3119 | ||
2774 | reg = FDI_RX_CTL(pipe); |
3120 | reg = FDI_RX_CTL(pipe); |
2775 | temp = I915_READ(reg); |
3121 | temp = I915_READ(reg); |
2776 | temp &= ~FDI_LINK_TRAIN_AUTO; |
3122 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2777 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3123 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2778 | temp &= ~FDI_RX_ENABLE; |
3124 | temp &= ~FDI_RX_ENABLE; |
2779 | I915_WRITE(reg, temp); |
3125 | I915_WRITE(reg, temp); |
2780 | 3126 | ||
2781 | /* enable CPU FDI TX and PCH FDI RX */ |
3127 | /* enable CPU FDI TX and PCH FDI RX */ |
2782 | reg = FDI_TX_CTL(pipe); |
3128 | reg = FDI_TX_CTL(pipe); |
2783 | temp = I915_READ(reg); |
3129 | temp = I915_READ(reg); |
2784 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3130 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2785 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
3131 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2786 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
3132 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2787 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3133 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2788 | temp |= snb_b_fdi_train_param[j/2]; |
3134 | temp |= snb_b_fdi_train_param[j/2]; |
2789 | temp |= FDI_COMPOSITE_SYNC; |
3135 | temp |= FDI_COMPOSITE_SYNC; |
2790 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
3136 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2791 | 3137 | ||
2792 | I915_WRITE(FDI_RX_MISC(pipe), |
3138 | I915_WRITE(FDI_RX_MISC(pipe), |
2793 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
3139 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2794 | 3140 | ||
2795 | reg = FDI_RX_CTL(pipe); |
3141 | reg = FDI_RX_CTL(pipe); |
2796 | temp = I915_READ(reg); |
3142 | temp = I915_READ(reg); |
2797 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3143 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2798 | temp |= FDI_COMPOSITE_SYNC; |
3144 | temp |= FDI_COMPOSITE_SYNC; |
2799 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3145 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2800 | 3146 | ||
2801 | POSTING_READ(reg); |
3147 | POSTING_READ(reg); |
2802 | udelay(1); /* should be 0.5us */ |
3148 | udelay(1); /* should be 0.5us */ |
2803 | 3149 | ||
2804 | for (i = 0; i < 4; i++) { |
3150 | for (i = 0; i < 4; i++) { |
2805 | reg = FDI_RX_IIR(pipe); |
3151 | reg = FDI_RX_IIR(pipe); |
2806 | temp = I915_READ(reg); |
3152 | temp = I915_READ(reg); |
2807 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3153 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2808 | 3154 | ||
2809 | if (temp & FDI_RX_BIT_LOCK || |
3155 | if (temp & FDI_RX_BIT_LOCK || |
2810 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
3156 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2811 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
3157 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2812 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
3158 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2813 | i); |
3159 | i); |
2814 | break; |
3160 | break; |
2815 | } |
3161 | } |
2816 | udelay(1); /* should be 0.5us */ |
3162 | udelay(1); /* should be 0.5us */ |
2817 | } |
3163 | } |
2818 | if (i == 4) { |
3164 | if (i == 4) { |
2819 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
3165 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
2820 | continue; |
3166 | continue; |
2821 | } |
3167 | } |
2822 | 3168 | ||
2823 | /* Train 2 */ |
3169 | /* Train 2 */ |
2824 | reg = FDI_TX_CTL(pipe); |
3170 | reg = FDI_TX_CTL(pipe); |
2825 | temp = I915_READ(reg); |
3171 | temp = I915_READ(reg); |
2826 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3172 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2827 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
3173 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2828 | I915_WRITE(reg, temp); |
3174 | I915_WRITE(reg, temp); |
2829 | 3175 | ||
2830 | reg = FDI_RX_CTL(pipe); |
3176 | reg = FDI_RX_CTL(pipe); |
2831 | temp = I915_READ(reg); |
3177 | temp = I915_READ(reg); |
2832 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3178 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2833 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
3179 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2834 | I915_WRITE(reg, temp); |
3180 | I915_WRITE(reg, temp); |
2835 | 3181 | ||
2836 | POSTING_READ(reg); |
3182 | POSTING_READ(reg); |
2837 | udelay(2); /* should be 1.5us */ |
3183 | udelay(2); /* should be 1.5us */ |
2838 | 3184 | ||
2839 | for (i = 0; i < 4; i++) { |
3185 | for (i = 0; i < 4; i++) { |
2840 | reg = FDI_RX_IIR(pipe); |
3186 | reg = FDI_RX_IIR(pipe); |
2841 | temp = I915_READ(reg); |
3187 | temp = I915_READ(reg); |
2842 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3188 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2843 | 3189 | ||
2844 | if (temp & FDI_RX_SYMBOL_LOCK || |
3190 | if (temp & FDI_RX_SYMBOL_LOCK || |
2845 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
3191 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2846 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
3192 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2847 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
3193 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2848 | i); |
3194 | i); |
2849 | goto train_done; |
3195 | goto train_done; |
2850 | } |
3196 | } |
2851 | udelay(2); /* should be 1.5us */ |
3197 | udelay(2); /* should be 1.5us */ |
2852 | } |
3198 | } |
2853 | if (i == 4) |
3199 | if (i == 4) |
2854 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
3200 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2855 | } |
3201 | } |
2856 | 3202 | ||
2857 | train_done: |
3203 | train_done: |
2858 | DRM_DEBUG_KMS("FDI train done.\n"); |
3204 | DRM_DEBUG_KMS("FDI train done.\n"); |
2859 | } |
3205 | } |
2860 | 3206 | ||
2861 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
3207 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2862 | { |
3208 | { |
2863 | struct drm_device *dev = intel_crtc->base.dev; |
3209 | struct drm_device *dev = intel_crtc->base.dev; |
2864 | struct drm_i915_private *dev_priv = dev->dev_private; |
3210 | struct drm_i915_private *dev_priv = dev->dev_private; |
2865 | int pipe = intel_crtc->pipe; |
3211 | int pipe = intel_crtc->pipe; |
2866 | u32 reg, temp; |
3212 | u32 reg, temp; |
2867 | 3213 | ||
2868 | 3214 | ||
2869 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
3215 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2870 | reg = FDI_RX_CTL(pipe); |
3216 | reg = FDI_RX_CTL(pipe); |
2871 | temp = I915_READ(reg); |
3217 | temp = I915_READ(reg); |
2872 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3218 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2873 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
3219 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2874 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3220 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2875 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3221 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2876 | 3222 | ||
2877 | POSTING_READ(reg); |
3223 | POSTING_READ(reg); |
2878 | udelay(200); |
3224 | udelay(200); |
2879 | 3225 | ||
2880 | /* Switch from Rawclk to PCDclk */ |
3226 | /* Switch from Rawclk to PCDclk */ |
2881 | temp = I915_READ(reg); |
3227 | temp = I915_READ(reg); |
2882 | I915_WRITE(reg, temp | FDI_PCDCLK); |
3228 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2883 | 3229 | ||
2884 | POSTING_READ(reg); |
3230 | POSTING_READ(reg); |
2885 | udelay(200); |
3231 | udelay(200); |
2886 | 3232 | ||
2887 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3233 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2888 | reg = FDI_TX_CTL(pipe); |
3234 | reg = FDI_TX_CTL(pipe); |
2889 | temp = I915_READ(reg); |
3235 | temp = I915_READ(reg); |
2890 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
3236 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2891 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
3237 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2892 | 3238 | ||
2893 | POSTING_READ(reg); |
3239 | POSTING_READ(reg); |
2894 | udelay(100); |
3240 | udelay(100); |
2895 | } |
3241 | } |
2896 | } |
3242 | } |
2897 | 3243 | ||
2898 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3244 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2899 | { |
3245 | { |
2900 | struct drm_device *dev = intel_crtc->base.dev; |
3246 | struct drm_device *dev = intel_crtc->base.dev; |
2901 | struct drm_i915_private *dev_priv = dev->dev_private; |
3247 | struct drm_i915_private *dev_priv = dev->dev_private; |
2902 | int pipe = intel_crtc->pipe; |
3248 | int pipe = intel_crtc->pipe; |
2903 | u32 reg, temp; |
3249 | u32 reg, temp; |
2904 | 3250 | ||
2905 | /* Switch from PCDclk to Rawclk */ |
3251 | /* Switch from PCDclk to Rawclk */ |
2906 | reg = FDI_RX_CTL(pipe); |
3252 | reg = FDI_RX_CTL(pipe); |
2907 | temp = I915_READ(reg); |
3253 | temp = I915_READ(reg); |
2908 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
3254 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2909 | 3255 | ||
2910 | /* Disable CPU FDI TX PLL */ |
3256 | /* Disable CPU FDI TX PLL */ |
2911 | reg = FDI_TX_CTL(pipe); |
3257 | reg = FDI_TX_CTL(pipe); |
2912 | temp = I915_READ(reg); |
3258 | temp = I915_READ(reg); |
2913 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
3259 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2914 | 3260 | ||
2915 | POSTING_READ(reg); |
3261 | POSTING_READ(reg); |
2916 | udelay(100); |
3262 | udelay(100); |
2917 | 3263 | ||
2918 | reg = FDI_RX_CTL(pipe); |
3264 | reg = FDI_RX_CTL(pipe); |
2919 | temp = I915_READ(reg); |
3265 | temp = I915_READ(reg); |
2920 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
3266 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2921 | 3267 | ||
2922 | /* Wait for the clocks to turn off. */ |
3268 | /* Wait for the clocks to turn off. */ |
2923 | POSTING_READ(reg); |
3269 | POSTING_READ(reg); |
2924 | udelay(100); |
3270 | udelay(100); |
2925 | } |
3271 | } |
2926 | 3272 | ||
2927 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3273 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2928 | { |
3274 | { |
2929 | struct drm_device *dev = crtc->dev; |
3275 | struct drm_device *dev = crtc->dev; |
2930 | struct drm_i915_private *dev_priv = dev->dev_private; |
3276 | struct drm_i915_private *dev_priv = dev->dev_private; |
2931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2932 | int pipe = intel_crtc->pipe; |
3278 | int pipe = intel_crtc->pipe; |
2933 | u32 reg, temp; |
3279 | u32 reg, temp; |
2934 | 3280 | ||
2935 | /* disable CPU FDI tx and PCH FDI rx */ |
3281 | /* disable CPU FDI tx and PCH FDI rx */ |
2936 | reg = FDI_TX_CTL(pipe); |
3282 | reg = FDI_TX_CTL(pipe); |
2937 | temp = I915_READ(reg); |
3283 | temp = I915_READ(reg); |
2938 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
3284 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2939 | POSTING_READ(reg); |
3285 | POSTING_READ(reg); |
2940 | 3286 | ||
2941 | reg = FDI_RX_CTL(pipe); |
3287 | reg = FDI_RX_CTL(pipe); |
2942 | temp = I915_READ(reg); |
3288 | temp = I915_READ(reg); |
2943 | temp &= ~(0x7 << 16); |
3289 | temp &= ~(0x7 << 16); |
2944 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3290 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2945 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3291 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2946 | 3292 | ||
2947 | POSTING_READ(reg); |
3293 | POSTING_READ(reg); |
2948 | udelay(100); |
3294 | udelay(100); |
2949 | 3295 | ||
2950 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
3296 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2951 | if (HAS_PCH_IBX(dev)) { |
3297 | if (HAS_PCH_IBX(dev)) |
2952 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3298 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2953 | } |
- | |
2954 | 3299 | ||
2955 | /* still set train pattern 1 */ |
3300 | /* still set train pattern 1 */ |
2956 | reg = FDI_TX_CTL(pipe); |
3301 | reg = FDI_TX_CTL(pipe); |
2957 | temp = I915_READ(reg); |
3302 | temp = I915_READ(reg); |
2958 | temp &= ~FDI_LINK_TRAIN_NONE; |
3303 | temp &= ~FDI_LINK_TRAIN_NONE; |
2959 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
3304 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2960 | I915_WRITE(reg, temp); |
3305 | I915_WRITE(reg, temp); |
2961 | 3306 | ||
2962 | reg = FDI_RX_CTL(pipe); |
3307 | reg = FDI_RX_CTL(pipe); |
2963 | temp = I915_READ(reg); |
3308 | temp = I915_READ(reg); |
2964 | if (HAS_PCH_CPT(dev)) { |
3309 | if (HAS_PCH_CPT(dev)) { |
2965 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3310 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2966 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3311 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2967 | } else { |
3312 | } else { |
2968 | temp &= ~FDI_LINK_TRAIN_NONE; |
3313 | temp &= ~FDI_LINK_TRAIN_NONE; |
2969 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
3314 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2970 | } |
3315 | } |
2971 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
3316 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2972 | temp &= ~(0x07 << 16); |
3317 | temp &= ~(0x07 << 16); |
2973 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3318 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2974 | I915_WRITE(reg, temp); |
3319 | I915_WRITE(reg, temp); |
2975 | 3320 | ||
2976 | POSTING_READ(reg); |
3321 | POSTING_READ(reg); |
2977 | udelay(100); |
3322 | udelay(100); |
2978 | } |
3323 | } |
2979 | 3324 | ||
2980 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3325 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2981 | { |
3326 | { |
2982 | struct drm_device *dev = crtc->dev; |
- | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
2984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
2985 | unsigned long flags; |
- | |
- | 3327 | struct intel_crtc *crtc; |
|
- | 3328 | ||
- | 3329 | /* Note that we don't need to be called with mode_config.lock here |
|
- | 3330 | * as our list of CRTC objects is static for the lifetime of the |
|
- | 3331 | * device and so cannot disappear as we iterate. Similarly, we can |
|
- | 3332 | * happily treat the predicates as racy, atomic checks as userspace |
|
- | 3333 | * cannot claim and pin a new fb without at least acquring the |
|
2986 | bool pending; |
3334 | * struct_mutex and so serialising with us. |
2987 | 3335 | */ |
|
2988 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
3336 | for_each_intel_crtc(dev, crtc) { |
2989 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
- | |
2990 | return false; |
3337 | if (atomic_read(&crtc->unpin_work_count) == 0) |
2991 | 3338 | continue; |
|
- | 3339 | ||
- | 3340 | if (crtc->unpin_work) |
|
- | 3341 | intel_wait_for_vblank(dev, crtc->pipe); |
|
2992 | spin_lock_irqsave(&dev->event_lock, flags); |
3342 | |
2993 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
3343 | return true; |
2994 | spin_unlock_irqrestore(&dev->event_lock, flags); |
3344 | } |
2995 | 3345 | ||
2996 | return pending; |
3346 | return false; |
2997 | } |
3347 | } |
2998 | 3348 | ||
2999 | #if 0 |
3349 | #if 0 |
3000 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3350 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3001 | { |
3351 | { |
3002 | struct drm_device *dev = crtc->dev; |
3352 | struct drm_device *dev = crtc->dev; |
3003 | struct drm_i915_private *dev_priv = dev->dev_private; |
3353 | struct drm_i915_private *dev_priv = dev->dev_private; |
3004 | 3354 | ||
3005 | if (crtc->fb == NULL) |
3355 | if (crtc->primary->fb == NULL) |
3006 | return; |
3356 | return; |
3007 | 3357 | ||
3008 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3358 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3009 | 3359 | ||
3010 | wait_event(dev_priv->pending_flip_queue, |
3360 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
- | 3361 | !intel_crtc_has_pending_flip(crtc), |
|
3011 | !intel_crtc_has_pending_flip(crtc)); |
3362 | 60*HZ) == 0); |
3012 | 3363 | ||
3013 | mutex_lock(&dev->struct_mutex); |
3364 | mutex_lock(&dev->struct_mutex); |
3014 | intel_finish_fb(crtc->fb); |
3365 | intel_finish_fb(crtc->primary->fb); |
3015 | mutex_unlock(&dev->struct_mutex); |
3366 | mutex_unlock(&dev->struct_mutex); |
3016 | } |
3367 | } |
3017 | #endif |
3368 | #endif |
3018 | 3369 | ||
3019 | /* Program iCLKIP clock to the desired frequency */ |
3370 | /* Program iCLKIP clock to the desired frequency */ |
3020 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
3371 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
3021 | { |
3372 | { |
3022 | struct drm_device *dev = crtc->dev; |
3373 | struct drm_device *dev = crtc->dev; |
3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
3374 | struct drm_i915_private *dev_priv = dev->dev_private; |
3024 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
3375 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
3025 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3376 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3026 | u32 temp; |
3377 | u32 temp; |
3027 | 3378 | ||
3028 | mutex_lock(&dev_priv->dpio_lock); |
3379 | mutex_lock(&dev_priv->dpio_lock); |
3029 | 3380 | ||
3030 | /* It is necessary to ungate the pixclk gate prior to programming |
3381 | /* It is necessary to ungate the pixclk gate prior to programming |
3031 | * the divisors, and gate it back when it is done. |
3382 | * the divisors, and gate it back when it is done. |
3032 | */ |
3383 | */ |
3033 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
3384 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
3034 | 3385 | ||
3035 | /* Disable SSCCTL */ |
3386 | /* Disable SSCCTL */ |
3036 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
3387 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
3037 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3388 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3038 | SBI_SSCCTL_DISABLE, |
3389 | SBI_SSCCTL_DISABLE, |
3039 | SBI_ICLK); |
3390 | SBI_ICLK); |
3040 | 3391 | ||
3041 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
3392 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
3042 | if (clock == 20000) { |
3393 | if (clock == 20000) { |
3043 | auxdiv = 1; |
3394 | auxdiv = 1; |
3044 | divsel = 0x41; |
3395 | divsel = 0x41; |
3045 | phaseinc = 0x20; |
3396 | phaseinc = 0x20; |
3046 | } else { |
3397 | } else { |
3047 | /* The iCLK virtual clock root frequency is in MHz, |
3398 | /* The iCLK virtual clock root frequency is in MHz, |
3048 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3399 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3049 | * divisors, it is necessary to divide one by another, so we |
3400 | * divisors, it is necessary to divide one by another, so we |
3050 | * convert the virtual clock precision to KHz here for higher |
3401 | * convert the virtual clock precision to KHz here for higher |
3051 | * precision. |
3402 | * precision. |
3052 | */ |
3403 | */ |
3053 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3404 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3054 | u32 iclk_pi_range = 64; |
3405 | u32 iclk_pi_range = 64; |
3055 | u32 desired_divisor, msb_divisor_value, pi_value; |
3406 | u32 desired_divisor, msb_divisor_value, pi_value; |
3056 | 3407 | ||
3057 | desired_divisor = (iclk_virtual_root_freq / clock); |
3408 | desired_divisor = (iclk_virtual_root_freq / clock); |
3058 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3409 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3059 | pi_value = desired_divisor % iclk_pi_range; |
3410 | pi_value = desired_divisor % iclk_pi_range; |
3060 | 3411 | ||
3061 | auxdiv = 0; |
3412 | auxdiv = 0; |
3062 | divsel = msb_divisor_value - 2; |
3413 | divsel = msb_divisor_value - 2; |
3063 | phaseinc = pi_value; |
3414 | phaseinc = pi_value; |
3064 | } |
3415 | } |
3065 | 3416 | ||
3066 | /* This should not happen with any sane values */ |
3417 | /* This should not happen with any sane values */ |
3067 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
3418 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
3068 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
3419 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
3069 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
3420 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
3070 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
3421 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
3071 | 3422 | ||
3072 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
3423 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
3073 | clock, |
3424 | clock, |
3074 | auxdiv, |
3425 | auxdiv, |
3075 | divsel, |
3426 | divsel, |
3076 | phasedir, |
3427 | phasedir, |
3077 | phaseinc); |
3428 | phaseinc); |
3078 | 3429 | ||
3079 | /* Program SSCDIVINTPHASE6 */ |
3430 | /* Program SSCDIVINTPHASE6 */ |
3080 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
3431 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
3081 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3432 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3082 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
3433 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
3083 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
3434 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
3084 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
3435 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
3085 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
3436 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
3086 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
3437 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
3087 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
3438 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
3088 | 3439 | ||
3089 | /* Program SSCAUXDIV */ |
3440 | /* Program SSCAUXDIV */ |
3090 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
3441 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
3091 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3442 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3092 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
3443 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
3093 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
3444 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
3094 | 3445 | ||
3095 | /* Enable modulator and associated divider */ |
3446 | /* Enable modulator and associated divider */ |
3096 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
3447 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
3097 | temp &= ~SBI_SSCCTL_DISABLE; |
3448 | temp &= ~SBI_SSCCTL_DISABLE; |
3098 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
3449 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
3099 | 3450 | ||
3100 | /* Wait for initialization time */ |
3451 | /* Wait for initialization time */ |
3101 | udelay(24); |
3452 | udelay(24); |
3102 | 3453 | ||
3103 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
3454 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
3104 | 3455 | ||
3105 | mutex_unlock(&dev_priv->dpio_lock); |
3456 | mutex_unlock(&dev_priv->dpio_lock); |
3106 | } |
3457 | } |
3107 | 3458 | ||
3108 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3459 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3109 | enum pipe pch_transcoder) |
3460 | enum pipe pch_transcoder) |
3110 | { |
3461 | { |
3111 | struct drm_device *dev = crtc->base.dev; |
3462 | struct drm_device *dev = crtc->base.dev; |
3112 | struct drm_i915_private *dev_priv = dev->dev_private; |
3463 | struct drm_i915_private *dev_priv = dev->dev_private; |
3113 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
3464 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
3114 | 3465 | ||
3115 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
3466 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
3116 | I915_READ(HTOTAL(cpu_transcoder))); |
3467 | I915_READ(HTOTAL(cpu_transcoder))); |
3117 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
3468 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
3118 | I915_READ(HBLANK(cpu_transcoder))); |
3469 | I915_READ(HBLANK(cpu_transcoder))); |
3119 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
3470 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
3120 | I915_READ(HSYNC(cpu_transcoder))); |
3471 | I915_READ(HSYNC(cpu_transcoder))); |
3121 | 3472 | ||
3122 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
3473 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
3123 | I915_READ(VTOTAL(cpu_transcoder))); |
3474 | I915_READ(VTOTAL(cpu_transcoder))); |
3124 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
3475 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
3125 | I915_READ(VBLANK(cpu_transcoder))); |
3476 | I915_READ(VBLANK(cpu_transcoder))); |
3126 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
3477 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
3127 | I915_READ(VSYNC(cpu_transcoder))); |
3478 | I915_READ(VSYNC(cpu_transcoder))); |
3128 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
3479 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
3129 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
3480 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
3130 | } |
3481 | } |
3131 | 3482 | ||
3132 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3483 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3133 | { |
3484 | { |
3134 | struct drm_i915_private *dev_priv = dev->dev_private; |
3485 | struct drm_i915_private *dev_priv = dev->dev_private; |
3135 | uint32_t temp; |
3486 | uint32_t temp; |
3136 | 3487 | ||
3137 | temp = I915_READ(SOUTH_CHICKEN1); |
3488 | temp = I915_READ(SOUTH_CHICKEN1); |
3138 | if (temp & FDI_BC_BIFURCATION_SELECT) |
3489 | if (temp & FDI_BC_BIFURCATION_SELECT) |
3139 | return; |
3490 | return; |
3140 | 3491 | ||
3141 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3492 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3142 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
3493 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
3143 | 3494 | ||
3144 | temp |= FDI_BC_BIFURCATION_SELECT; |
3495 | temp |= FDI_BC_BIFURCATION_SELECT; |
3145 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
3496 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
3146 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3497 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3147 | POSTING_READ(SOUTH_CHICKEN1); |
3498 | POSTING_READ(SOUTH_CHICKEN1); |
3148 | } |
3499 | } |
3149 | 3500 | ||
3150 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
3501 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
3151 | { |
3502 | { |
3152 | struct drm_device *dev = intel_crtc->base.dev; |
3503 | struct drm_device *dev = intel_crtc->base.dev; |
3153 | struct drm_i915_private *dev_priv = dev->dev_private; |
3504 | struct drm_i915_private *dev_priv = dev->dev_private; |
3154 | 3505 | ||
3155 | switch (intel_crtc->pipe) { |
3506 | switch (intel_crtc->pipe) { |
3156 | case PIPE_A: |
3507 | case PIPE_A: |
3157 | break; |
3508 | break; |
3158 | case PIPE_B: |
3509 | case PIPE_B: |
3159 | if (intel_crtc->config.fdi_lanes > 2) |
3510 | if (intel_crtc->config.fdi_lanes > 2) |
3160 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3511 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3161 | else |
3512 | else |
3162 | cpt_enable_fdi_bc_bifurcation(dev); |
3513 | cpt_enable_fdi_bc_bifurcation(dev); |
3163 | 3514 | ||
3164 | break; |
3515 | break; |
3165 | case PIPE_C: |
3516 | case PIPE_C: |
3166 | cpt_enable_fdi_bc_bifurcation(dev); |
3517 | cpt_enable_fdi_bc_bifurcation(dev); |
3167 | 3518 | ||
3168 | break; |
3519 | break; |
3169 | default: |
3520 | default: |
3170 | BUG(); |
3521 | BUG(); |
3171 | } |
3522 | } |
3172 | } |
3523 | } |
3173 | 3524 | ||
3174 | /* |
3525 | /* |
3175 | * Enable PCH resources required for PCH ports: |
3526 | * Enable PCH resources required for PCH ports: |
3176 | * - PCH PLLs |
3527 | * - PCH PLLs |
3177 | * - FDI training & RX/TX |
3528 | * - FDI training & RX/TX |
3178 | * - update transcoder timings |
3529 | * - update transcoder timings |
3179 | * - DP transcoding bits |
3530 | * - DP transcoding bits |
3180 | * - transcoder |
3531 | * - transcoder |
3181 | */ |
3532 | */ |
3182 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3533 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3183 | { |
3534 | { |
3184 | struct drm_device *dev = crtc->dev; |
3535 | struct drm_device *dev = crtc->dev; |
3185 | struct drm_i915_private *dev_priv = dev->dev_private; |
3536 | struct drm_i915_private *dev_priv = dev->dev_private; |
3186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3187 | int pipe = intel_crtc->pipe; |
3538 | int pipe = intel_crtc->pipe; |
3188 | u32 reg, temp; |
3539 | u32 reg, temp; |
3189 | 3540 | ||
3190 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3541 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3191 | 3542 | ||
3192 | if (IS_IVYBRIDGE(dev)) |
3543 | if (IS_IVYBRIDGE(dev)) |
3193 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
3544 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
3194 | 3545 | ||
3195 | /* Write the TU size bits before fdi link training, so that error |
3546 | /* Write the TU size bits before fdi link training, so that error |
3196 | * detection works. */ |
3547 | * detection works. */ |
3197 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3548 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3198 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3549 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3199 | 3550 | ||
3200 | /* For PCH output, training FDI link */ |
3551 | /* For PCH output, training FDI link */ |
3201 | dev_priv->display.fdi_link_train(crtc); |
3552 | dev_priv->display.fdi_link_train(crtc); |
3202 | 3553 | ||
3203 | /* We need to program the right clock selection before writing the pixel |
3554 | /* We need to program the right clock selection before writing the pixel |
3204 | * mutliplier into the DPLL. */ |
3555 | * mutliplier into the DPLL. */ |
3205 | if (HAS_PCH_CPT(dev)) { |
3556 | if (HAS_PCH_CPT(dev)) { |
3206 | u32 sel; |
3557 | u32 sel; |
3207 | 3558 | ||
3208 | temp = I915_READ(PCH_DPLL_SEL); |
3559 | temp = I915_READ(PCH_DPLL_SEL); |
3209 | temp |= TRANS_DPLL_ENABLE(pipe); |
3560 | temp |= TRANS_DPLL_ENABLE(pipe); |
3210 | sel = TRANS_DPLLB_SEL(pipe); |
3561 | sel = TRANS_DPLLB_SEL(pipe); |
3211 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3562 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3212 | temp |= sel; |
3563 | temp |= sel; |
3213 | else |
3564 | else |
3214 | temp &= ~sel; |
3565 | temp &= ~sel; |
3215 | I915_WRITE(PCH_DPLL_SEL, temp); |
3566 | I915_WRITE(PCH_DPLL_SEL, temp); |
3216 | } |
3567 | } |
3217 | 3568 | ||
3218 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3569 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3219 | * transcoder, and we actually should do this to not upset any PCH |
3570 | * transcoder, and we actually should do this to not upset any PCH |
3220 | * transcoder that already use the clock when we share it. |
3571 | * transcoder that already use the clock when we share it. |
3221 | * |
3572 | * |
3222 | * Note that enable_shared_dpll tries to do the right thing, but |
3573 | * Note that enable_shared_dpll tries to do the right thing, but |
3223 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3574 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3224 | * the right LVDS enable sequence. */ |
3575 | * the right LVDS enable sequence. */ |
3225 | ironlake_enable_shared_dpll(intel_crtc); |
3576 | intel_enable_shared_dpll(intel_crtc); |
3226 | 3577 | ||
3227 | /* set transcoder timing, panel must allow it */ |
3578 | /* set transcoder timing, panel must allow it */ |
3228 | assert_panel_unlocked(dev_priv, pipe); |
3579 | assert_panel_unlocked(dev_priv, pipe); |
3229 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3580 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3230 | 3581 | ||
3231 | intel_fdi_normal_train(crtc); |
3582 | intel_fdi_normal_train(crtc); |
3232 | 3583 | ||
3233 | /* For PCH DP, enable TRANS_DP_CTL */ |
3584 | /* For PCH DP, enable TRANS_DP_CTL */ |
3234 | if (HAS_PCH_CPT(dev) && |
3585 | if (HAS_PCH_CPT(dev) && |
3235 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3586 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3236 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3587 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3237 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3588 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3238 | reg = TRANS_DP_CTL(pipe); |
3589 | reg = TRANS_DP_CTL(pipe); |
3239 | temp = I915_READ(reg); |
3590 | temp = I915_READ(reg); |
3240 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3591 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3241 | TRANS_DP_SYNC_MASK | |
3592 | TRANS_DP_SYNC_MASK | |
3242 | TRANS_DP_BPC_MASK); |
3593 | TRANS_DP_BPC_MASK); |
3243 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3594 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3244 | TRANS_DP_ENH_FRAMING); |
3595 | TRANS_DP_ENH_FRAMING); |
3245 | temp |= bpc << 9; /* same format but at 11:9 */ |
3596 | temp |= bpc << 9; /* same format but at 11:9 */ |
3246 | 3597 | ||
3247 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3598 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3248 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3599 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3249 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3600 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3250 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3601 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3251 | 3602 | ||
3252 | switch (intel_trans_dp_port_sel(crtc)) { |
3603 | switch (intel_trans_dp_port_sel(crtc)) { |
3253 | case PCH_DP_B: |
3604 | case PCH_DP_B: |
3254 | temp |= TRANS_DP_PORT_SEL_B; |
3605 | temp |= TRANS_DP_PORT_SEL_B; |
3255 | break; |
3606 | break; |
3256 | case PCH_DP_C: |
3607 | case PCH_DP_C: |
3257 | temp |= TRANS_DP_PORT_SEL_C; |
3608 | temp |= TRANS_DP_PORT_SEL_C; |
3258 | break; |
3609 | break; |
3259 | case PCH_DP_D: |
3610 | case PCH_DP_D: |
3260 | temp |= TRANS_DP_PORT_SEL_D; |
3611 | temp |= TRANS_DP_PORT_SEL_D; |
3261 | break; |
3612 | break; |
3262 | default: |
3613 | default: |
3263 | BUG(); |
3614 | BUG(); |
3264 | } |
3615 | } |
3265 | 3616 | ||
3266 | I915_WRITE(reg, temp); |
3617 | I915_WRITE(reg, temp); |
3267 | } |
3618 | } |
3268 | 3619 | ||
3269 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3620 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3270 | } |
3621 | } |
3271 | 3622 | ||
3272 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3623 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3273 | { |
3624 | { |
3274 | struct drm_device *dev = crtc->dev; |
3625 | struct drm_device *dev = crtc->dev; |
3275 | struct drm_i915_private *dev_priv = dev->dev_private; |
3626 | struct drm_i915_private *dev_priv = dev->dev_private; |
3276 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3277 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3628 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3278 | 3629 | ||
3279 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3630 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3280 | 3631 | ||
3281 | lpt_program_iclkip(crtc); |
3632 | lpt_program_iclkip(crtc); |
3282 | 3633 | ||
3283 | /* Set transcoder timing. */ |
3634 | /* Set transcoder timing. */ |
3284 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3635 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3285 | 3636 | ||
3286 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3637 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3287 | } |
3638 | } |
3288 | 3639 | ||
3289 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3640 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
3290 | { |
3641 | { |
3291 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3642 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3292 | 3643 | ||
3293 | if (pll == NULL) |
3644 | if (pll == NULL) |
3294 | return; |
3645 | return; |
3295 | 3646 | ||
3296 | if (pll->refcount == 0) { |
3647 | if (pll->refcount == 0) { |
3297 | WARN(1, "bad %s refcount\n", pll->name); |
3648 | WARN(1, "bad %s refcount\n", pll->name); |
3298 | return; |
3649 | return; |
3299 | } |
3650 | } |
3300 | 3651 | ||
3301 | if (--pll->refcount == 0) { |
3652 | if (--pll->refcount == 0) { |
3302 | WARN_ON(pll->on); |
3653 | WARN_ON(pll->on); |
3303 | WARN_ON(pll->active); |
3654 | WARN_ON(pll->active); |
3304 | } |
3655 | } |
3305 | 3656 | ||
3306 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3657 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3307 | } |
3658 | } |
3308 | 3659 | ||
3309 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3660 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3310 | { |
3661 | { |
3311 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3662 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3312 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3663 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3313 | enum intel_dpll_id i; |
3664 | enum intel_dpll_id i; |
3314 | 3665 | ||
3315 | if (pll) { |
3666 | if (pll) { |
3316 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3667 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3317 | crtc->base.base.id, pll->name); |
3668 | crtc->base.base.id, pll->name); |
3318 | intel_put_shared_dpll(crtc); |
3669 | intel_put_shared_dpll(crtc); |
3319 | } |
3670 | } |
3320 | 3671 | ||
3321 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3672 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3322 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3673 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3323 | i = (enum intel_dpll_id) crtc->pipe; |
3674 | i = (enum intel_dpll_id) crtc->pipe; |
3324 | pll = &dev_priv->shared_dplls[i]; |
3675 | pll = &dev_priv->shared_dplls[i]; |
3325 | 3676 | ||
3326 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3677 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3327 | crtc->base.base.id, pll->name); |
3678 | crtc->base.base.id, pll->name); |
- | 3679 | ||
- | 3680 | WARN_ON(pll->refcount); |
|
3328 | 3681 | ||
3329 | goto found; |
3682 | goto found; |
3330 | } |
3683 | } |
3331 | 3684 | ||
3332 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3685 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3333 | pll = &dev_priv->shared_dplls[i]; |
3686 | pll = &dev_priv->shared_dplls[i]; |
3334 | 3687 | ||
3335 | /* Only want to check enabled timings first */ |
3688 | /* Only want to check enabled timings first */ |
3336 | if (pll->refcount == 0) |
3689 | if (pll->refcount == 0) |
3337 | continue; |
3690 | continue; |
3338 | 3691 | ||
3339 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3692 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3340 | sizeof(pll->hw_state)) == 0) { |
3693 | sizeof(pll->hw_state)) == 0) { |
3341 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3694 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3342 | crtc->base.base.id, |
3695 | crtc->base.base.id, |
3343 | pll->name, pll->refcount, pll->active); |
3696 | pll->name, pll->refcount, pll->active); |
3344 | 3697 | ||
3345 | goto found; |
3698 | goto found; |
3346 | } |
3699 | } |
3347 | } |
3700 | } |
3348 | 3701 | ||
3349 | /* Ok no matching timings, maybe there's a free one? */ |
3702 | /* Ok no matching timings, maybe there's a free one? */ |
3350 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3703 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3351 | pll = &dev_priv->shared_dplls[i]; |
3704 | pll = &dev_priv->shared_dplls[i]; |
3352 | if (pll->refcount == 0) { |
3705 | if (pll->refcount == 0) { |
3353 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3706 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3354 | crtc->base.base.id, pll->name); |
3707 | crtc->base.base.id, pll->name); |
3355 | goto found; |
3708 | goto found; |
3356 | } |
3709 | } |
3357 | } |
3710 | } |
3358 | 3711 | ||
3359 | return NULL; |
3712 | return NULL; |
3360 | 3713 | ||
3361 | found: |
3714 | found: |
- | 3715 | if (pll->refcount == 0) |
|
- | 3716 | pll->hw_state = crtc->config.dpll_hw_state; |
|
- | 3717 | ||
3362 | crtc->config.shared_dpll = i; |
3718 | crtc->config.shared_dpll = i; |
3363 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3719 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3364 | pipe_name(crtc->pipe)); |
3720 | pipe_name(crtc->pipe)); |
3365 | - | ||
3366 | if (pll->active == 0) { |
- | |
3367 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
- | |
3368 | sizeof(pll->hw_state)); |
- | |
3369 | - | ||
3370 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
- | |
3371 | WARN_ON(pll->on); |
- | |
3372 | assert_shared_dpll_disabled(dev_priv, pll); |
- | |
3373 | - | ||
3374 | pll->mode_set(dev_priv, pll); |
- | |
3375 | } |
3721 | |
3376 | pll->refcount++; |
3722 | pll->refcount++; |
3377 | 3723 | ||
3378 | return pll; |
3724 | return pll; |
3379 | } |
3725 | } |
3380 | 3726 | ||
3381 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3727 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3382 | { |
3728 | { |
3383 | struct drm_i915_private *dev_priv = dev->dev_private; |
3729 | struct drm_i915_private *dev_priv = dev->dev_private; |
3384 | int dslreg = PIPEDSL(pipe); |
3730 | int dslreg = PIPEDSL(pipe); |
3385 | u32 temp; |
3731 | u32 temp; |
3386 | 3732 | ||
3387 | temp = I915_READ(dslreg); |
3733 | temp = I915_READ(dslreg); |
3388 | udelay(500); |
3734 | udelay(500); |
3389 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3735 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3390 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3736 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3391 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3737 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3392 | } |
3738 | } |
3393 | } |
3739 | } |
3394 | 3740 | ||
3395 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3741 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3396 | { |
3742 | { |
3397 | struct drm_device *dev = crtc->base.dev; |
3743 | struct drm_device *dev = crtc->base.dev; |
3398 | struct drm_i915_private *dev_priv = dev->dev_private; |
3744 | struct drm_i915_private *dev_priv = dev->dev_private; |
3399 | int pipe = crtc->pipe; |
3745 | int pipe = crtc->pipe; |
3400 | 3746 | ||
3401 | if (crtc->config.pch_pfit.enabled) { |
3747 | if (crtc->config.pch_pfit.enabled) { |
3402 | /* Force use of hard-coded filter coefficients |
3748 | /* Force use of hard-coded filter coefficients |
3403 | * as some pre-programmed values are broken, |
3749 | * as some pre-programmed values are broken, |
3404 | * e.g. x201. |
3750 | * e.g. x201. |
3405 | */ |
3751 | */ |
3406 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3752 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3407 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3753 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3408 | PF_PIPE_SEL_IVB(pipe)); |
3754 | PF_PIPE_SEL_IVB(pipe)); |
3409 | else |
3755 | else |
3410 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3756 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3411 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3757 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3412 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3758 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3413 | } |
3759 | } |
3414 | } |
3760 | } |
3415 | 3761 | ||
3416 | static void intel_enable_planes(struct drm_crtc *crtc) |
3762 | static void intel_enable_planes(struct drm_crtc *crtc) |
3417 | { |
3763 | { |
3418 | struct drm_device *dev = crtc->dev; |
3764 | struct drm_device *dev = crtc->dev; |
3419 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3765 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
- | 3766 | struct drm_plane *plane; |
|
3420 | struct intel_plane *intel_plane; |
3767 | struct intel_plane *intel_plane; |
3421 | 3768 | ||
- | 3769 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
|
3422 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3770 | intel_plane = to_intel_plane(plane); |
3423 | if (intel_plane->pipe == pipe) |
3771 | if (intel_plane->pipe == pipe) |
3424 | intel_plane_restore(&intel_plane->base); |
3772 | intel_plane_restore(&intel_plane->base); |
3425 | } |
3773 | } |
- | 3774 | } |
|
3426 | 3775 | ||
3427 | static void intel_disable_planes(struct drm_crtc *crtc) |
3776 | static void intel_disable_planes(struct drm_crtc *crtc) |
3428 | { |
3777 | { |
3429 | struct drm_device *dev = crtc->dev; |
3778 | struct drm_device *dev = crtc->dev; |
3430 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3779 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
- | 3780 | struct drm_plane *plane; |
|
3431 | struct intel_plane *intel_plane; |
3781 | struct intel_plane *intel_plane; |
3432 | 3782 | ||
- | 3783 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
|
3433 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3784 | intel_plane = to_intel_plane(plane); |
3434 | if (intel_plane->pipe == pipe) |
3785 | if (intel_plane->pipe == pipe) |
3435 | intel_plane_disable(&intel_plane->base); |
3786 | intel_plane_disable(&intel_plane->base); |
3436 | } |
3787 | } |
- | 3788 | } |
|
3437 | 3789 | ||
3438 | void hsw_enable_ips(struct intel_crtc *crtc) |
3790 | void hsw_enable_ips(struct intel_crtc *crtc) |
3439 | { |
3791 | { |
- | 3792 | struct drm_device *dev = crtc->base.dev; |
|
3440 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3793 | struct drm_i915_private *dev_priv = dev->dev_private; |
3441 | 3794 | ||
3442 | if (!crtc->config.ips_enabled) |
3795 | if (!crtc->config.ips_enabled) |
3443 | return; |
3796 | return; |
3444 | 3797 | ||
3445 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
- | |
3446 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3798 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3447 | * only after intel_enable_plane. And intel_enable_plane already waits |
- | |
- | 3799 | intel_wait_for_vblank(dev, crtc->pipe); |
|
3448 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3800 | |
3449 | assert_plane_enabled(dev_priv, crtc->plane); |
3801 | assert_plane_enabled(dev_priv, crtc->plane); |
3450 | if (IS_BROADWELL(crtc->base.dev)) { |
3802 | if (IS_BROADWELL(dev)) { |
3451 | mutex_lock(&dev_priv->rps.hw_lock); |
3803 | mutex_lock(&dev_priv->rps.hw_lock); |
3452 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
3804 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
3453 | mutex_unlock(&dev_priv->rps.hw_lock); |
3805 | mutex_unlock(&dev_priv->rps.hw_lock); |
3454 | /* Quoting Art Runyan: "its not safe to expect any particular |
3806 | /* Quoting Art Runyan: "its not safe to expect any particular |
3455 | * value in IPS_CTL bit 31 after enabling IPS through the |
3807 | * value in IPS_CTL bit 31 after enabling IPS through the |
3456 | * mailbox." Moreover, the mailbox may return a bogus state, |
3808 | * mailbox." Moreover, the mailbox may return a bogus state, |
3457 | * so we need to just enable it and continue on. |
3809 | * so we need to just enable it and continue on. |
3458 | */ |
3810 | */ |
3459 | } else { |
3811 | } else { |
3460 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3812 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3461 | /* The bit only becomes 1 in the next vblank, so this wait here |
3813 | /* The bit only becomes 1 in the next vblank, so this wait here |
3462 | * is essentially intel_wait_for_vblank. If we don't have this |
3814 | * is essentially intel_wait_for_vblank. If we don't have this |
3463 | * and don't wait for vblanks until the end of crtc_enable, then |
3815 | * and don't wait for vblanks until the end of crtc_enable, then |
3464 | * the HW state readout code will complain that the expected |
3816 | * the HW state readout code will complain that the expected |
3465 | * IPS_CTL value is not the one we read. */ |
3817 | * IPS_CTL value is not the one we read. */ |
3466 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
3818 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
3467 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
3819 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
3468 | } |
3820 | } |
3469 | } |
3821 | } |
3470 | 3822 | ||
3471 | void hsw_disable_ips(struct intel_crtc *crtc) |
3823 | void hsw_disable_ips(struct intel_crtc *crtc) |
3472 | { |
3824 | { |
3473 | struct drm_device *dev = crtc->base.dev; |
3825 | struct drm_device *dev = crtc->base.dev; |
3474 | struct drm_i915_private *dev_priv = dev->dev_private; |
3826 | struct drm_i915_private *dev_priv = dev->dev_private; |
3475 | 3827 | ||
3476 | if (!crtc->config.ips_enabled) |
3828 | if (!crtc->config.ips_enabled) |
3477 | return; |
3829 | return; |
3478 | 3830 | ||
3479 | assert_plane_enabled(dev_priv, crtc->plane); |
3831 | assert_plane_enabled(dev_priv, crtc->plane); |
3480 | if (IS_BROADWELL(crtc->base.dev)) { |
3832 | if (IS_BROADWELL(dev)) { |
3481 | mutex_lock(&dev_priv->rps.hw_lock); |
3833 | mutex_lock(&dev_priv->rps.hw_lock); |
3482 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
3834 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
3483 | mutex_unlock(&dev_priv->rps.hw_lock); |
3835 | mutex_unlock(&dev_priv->rps.hw_lock); |
- | 3836 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
|
- | 3837 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) |
|
- | 3838 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
|
3484 | } else { |
3839 | } else { |
3485 | I915_WRITE(IPS_CTL, 0); |
3840 | I915_WRITE(IPS_CTL, 0); |
3486 | POSTING_READ(IPS_CTL); |
3841 | POSTING_READ(IPS_CTL); |
3487 | } |
3842 | } |
3488 | 3843 | ||
3489 | /* We need to wait for a vblank before we can disable the plane. */ |
3844 | /* We need to wait for a vblank before we can disable the plane. */ |
3490 | intel_wait_for_vblank(dev, crtc->pipe); |
3845 | intel_wait_for_vblank(dev, crtc->pipe); |
3491 | } |
3846 | } |
3492 | 3847 | ||
3493 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
3848 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
3494 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
3849 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
3495 | { |
3850 | { |
3496 | struct drm_device *dev = crtc->dev; |
3851 | struct drm_device *dev = crtc->dev; |
3497 | struct drm_i915_private *dev_priv = dev->dev_private; |
3852 | struct drm_i915_private *dev_priv = dev->dev_private; |
3498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3499 | enum pipe pipe = intel_crtc->pipe; |
3854 | enum pipe pipe = intel_crtc->pipe; |
3500 | int palreg = PALETTE(pipe); |
3855 | int palreg = PALETTE(pipe); |
3501 | int i; |
3856 | int i; |
3502 | bool reenable_ips = false; |
3857 | bool reenable_ips = false; |
3503 | 3858 | ||
3504 | /* The clocks have to be on to load the palette. */ |
3859 | /* The clocks have to be on to load the palette. */ |
3505 | if (!crtc->enabled || !intel_crtc->active) |
3860 | if (!crtc->enabled || !intel_crtc->active) |
3506 | return; |
3861 | return; |
3507 | 3862 | ||
3508 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
3863 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
3509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
3864 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
3510 | assert_dsi_pll_enabled(dev_priv); |
3865 | assert_dsi_pll_enabled(dev_priv); |
3511 | else |
3866 | else |
3512 | assert_pll_enabled(dev_priv, pipe); |
3867 | assert_pll_enabled(dev_priv, pipe); |
3513 | } |
3868 | } |
3514 | 3869 | ||
3515 | /* use legacy palette for Ironlake */ |
3870 | /* use legacy palette for Ironlake */ |
3516 | if (HAS_PCH_SPLIT(dev)) |
3871 | if (!HAS_GMCH_DISPLAY(dev)) |
3517 | palreg = LGC_PALETTE(pipe); |
3872 | palreg = LGC_PALETTE(pipe); |
3518 | 3873 | ||
3519 | /* Workaround : Do not read or write the pipe palette/gamma data while |
3874 | /* Workaround : Do not read or write the pipe palette/gamma data while |
3520 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
3875 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
3521 | */ |
3876 | */ |
3522 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
3877 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
3523 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3878 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3524 | GAMMA_MODE_MODE_SPLIT)) { |
3879 | GAMMA_MODE_MODE_SPLIT)) { |
3525 | hsw_disable_ips(intel_crtc); |
3880 | hsw_disable_ips(intel_crtc); |
3526 | reenable_ips = true; |
3881 | reenable_ips = true; |
3527 | } |
3882 | } |
3528 | 3883 | ||
3529 | for (i = 0; i < 256; i++) { |
3884 | for (i = 0; i < 256; i++) { |
3530 | I915_WRITE(palreg + 4 * i, |
3885 | I915_WRITE(palreg + 4 * i, |
3531 | (intel_crtc->lut_r[i] << 16) | |
3886 | (intel_crtc->lut_r[i] << 16) | |
3532 | (intel_crtc->lut_g[i] << 8) | |
3887 | (intel_crtc->lut_g[i] << 8) | |
3533 | intel_crtc->lut_b[i]); |
3888 | intel_crtc->lut_b[i]); |
3534 | } |
3889 | } |
3535 | 3890 | ||
3536 | if (reenable_ips) |
3891 | if (reenable_ips) |
3537 | hsw_enable_ips(intel_crtc); |
3892 | hsw_enable_ips(intel_crtc); |
3538 | } |
3893 | } |
- | 3894 | ||
- | 3895 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
|
- | 3896 | { |
|
- | 3897 | if (!enable && intel_crtc->overlay) { |
|
- | 3898 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 3899 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3900 | ||
- | 3901 | mutex_lock(&dev->struct_mutex); |
|
- | 3902 | dev_priv->mm.interruptible = false; |
|
- | 3903 | dev_priv->mm.interruptible = true; |
|
- | 3904 | mutex_unlock(&dev->struct_mutex); |
|
- | 3905 | } |
|
- | 3906 | ||
- | 3907 | /* Let userspace switch the overlay on again. In most cases userspace |
|
- | 3908 | * has to recompute where to put it anyway. |
|
- | 3909 | */ |
|
- | 3910 | } |
|
- | 3911 | ||
- | 3912 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
|
- | 3913 | { |
|
- | 3914 | struct drm_device *dev = crtc->dev; |
|
- | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3916 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3917 | int pipe = intel_crtc->pipe; |
|
- | 3918 | int plane = intel_crtc->plane; |
|
- | 3919 | ||
- | 3920 | drm_vblank_on(dev, pipe); |
|
- | 3921 | ||
- | 3922 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
|
- | 3923 | intel_enable_planes(crtc); |
|
- | 3924 | intel_crtc_update_cursor(crtc, true); |
|
- | 3925 | intel_crtc_dpms_overlay(intel_crtc, true); |
|
- | 3926 | ||
- | 3927 | hsw_enable_ips(intel_crtc); |
|
- | 3928 | ||
- | 3929 | mutex_lock(&dev->struct_mutex); |
|
- | 3930 | intel_update_fbc(dev); |
|
- | 3931 | mutex_unlock(&dev->struct_mutex); |
|
- | 3932 | } |
|
- | 3933 | ||
- | 3934 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
|
- | 3935 | { |
|
- | 3936 | struct drm_device *dev = crtc->dev; |
|
- | 3937 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3939 | int pipe = intel_crtc->pipe; |
|
- | 3940 | int plane = intel_crtc->plane; |
|
- | 3941 | ||
- | 3942 | ||
- | 3943 | if (dev_priv->fbc.plane == plane) |
|
- | 3944 | intel_disable_fbc(dev); |
|
- | 3945 | ||
- | 3946 | hsw_disable_ips(intel_crtc); |
|
- | 3947 | ||
- | 3948 | intel_crtc_dpms_overlay(intel_crtc, false); |
|
- | 3949 | intel_crtc_update_cursor(crtc, false); |
|
- | 3950 | intel_disable_planes(crtc); |
|
- | 3951 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
|
- | 3952 | drm_vblank_off(dev, pipe); |
|
- | 3953 | } |
|
3539 | 3954 | ||
3540 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3955 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3541 | { |
3956 | { |
3542 | struct drm_device *dev = crtc->dev; |
3957 | struct drm_device *dev = crtc->dev; |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; |
3958 | struct drm_i915_private *dev_priv = dev->dev_private; |
3544 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3959 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3545 | struct intel_encoder *encoder; |
3960 | struct intel_encoder *encoder; |
3546 | int pipe = intel_crtc->pipe; |
3961 | int pipe = intel_crtc->pipe; |
3547 | int plane = intel_crtc->plane; |
3962 | enum plane plane = intel_crtc->plane; |
3548 | 3963 | ||
3549 | WARN_ON(!crtc->enabled); |
3964 | WARN_ON(!crtc->enabled); |
3550 | 3965 | ||
3551 | if (intel_crtc->active) |
3966 | if (intel_crtc->active) |
3552 | return; |
3967 | return; |
- | 3968 | ||
- | 3969 | if (intel_crtc->config.has_pch_encoder) |
|
- | 3970 | intel_prepare_shared_dpll(intel_crtc); |
|
- | 3971 | ||
- | 3972 | if (intel_crtc->config.has_dp_encoder) |
|
- | 3973 | intel_dp_set_m_n(intel_crtc); |
|
- | 3974 | ||
- | 3975 | intel_set_pipe_timings(intel_crtc); |
|
- | 3976 | ||
- | 3977 | if (intel_crtc->config.has_pch_encoder) { |
|
- | 3978 | intel_cpu_transcoder_set_m_n(intel_crtc, |
|
- | 3979 | &intel_crtc->config.fdi_m_n); |
|
- | 3980 | } |
|
- | 3981 | ||
- | 3982 | ironlake_set_pipeconf(crtc); |
|
- | 3983 | ||
- | 3984 | /* Set up the display plane register */ |
|
- | 3985 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
|
- | 3986 | POSTING_READ(DSPCNTR(plane)); |
|
- | 3987 | ||
- | 3988 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
|
- | 3989 | crtc->x, crtc->y); |
|
3553 | 3990 | ||
3554 | intel_crtc->active = true; |
3991 | intel_crtc->active = true; |
3555 | 3992 | ||
3556 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3993 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3557 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3994 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3558 | 3995 | ||
3559 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3996 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3560 | if (encoder->pre_enable) |
3997 | if (encoder->pre_enable) |
3561 | encoder->pre_enable(encoder); |
3998 | encoder->pre_enable(encoder); |
3562 | 3999 | ||
3563 | if (intel_crtc->config.has_pch_encoder) { |
4000 | if (intel_crtc->config.has_pch_encoder) { |
3564 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4001 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3565 | * cpu pipes, hence this is separate from all the other fdi/pch |
4002 | * cpu pipes, hence this is separate from all the other fdi/pch |
3566 | * enabling. */ |
4003 | * enabling. */ |
3567 | ironlake_fdi_pll_enable(intel_crtc); |
4004 | ironlake_fdi_pll_enable(intel_crtc); |
3568 | } else { |
4005 | } else { |
3569 | assert_fdi_tx_disabled(dev_priv, pipe); |
4006 | assert_fdi_tx_disabled(dev_priv, pipe); |
3570 | assert_fdi_rx_disabled(dev_priv, pipe); |
4007 | assert_fdi_rx_disabled(dev_priv, pipe); |
3571 | } |
4008 | } |
3572 | 4009 | ||
3573 | ironlake_pfit_enable(intel_crtc); |
4010 | ironlake_pfit_enable(intel_crtc); |
3574 | 4011 | ||
3575 | /* |
4012 | /* |
3576 | * On ILK+ LUT must be loaded before the pipe is running but with |
4013 | * On ILK+ LUT must be loaded before the pipe is running but with |
3577 | * clocks enabled |
4014 | * clocks enabled |
3578 | */ |
4015 | */ |
3579 | intel_crtc_load_lut(crtc); |
4016 | intel_crtc_load_lut(crtc); |
3580 | 4017 | ||
3581 | intel_update_watermarks(crtc); |
4018 | intel_update_watermarks(crtc); |
3582 | intel_enable_pipe(dev_priv, pipe, |
- | |
3583 | intel_crtc->config.has_pch_encoder, false); |
- | |
3584 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
3585 | intel_enable_planes(crtc); |
4019 | intel_enable_pipe(intel_crtc); |
3586 | intel_crtc_update_cursor(crtc, true); |
- | |
3587 | 4020 | ||
3588 | if (intel_crtc->config.has_pch_encoder) |
4021 | if (intel_crtc->config.has_pch_encoder) |
3589 | ironlake_pch_enable(crtc); |
4022 | ironlake_pch_enable(crtc); |
3590 | - | ||
3591 | mutex_lock(&dev->struct_mutex); |
- | |
3592 | intel_update_fbc(dev); |
- | |
3593 | mutex_unlock(&dev->struct_mutex); |
- | |
3594 | 4023 | ||
3595 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4024 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3596 | encoder->enable(encoder); |
4025 | encoder->enable(encoder); |
3597 | 4026 | ||
3598 | if (HAS_PCH_CPT(dev)) |
4027 | if (HAS_PCH_CPT(dev)) |
3599 | cpt_verify_modeset(dev, intel_crtc->pipe); |
4028 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3600 | - | ||
3601 | /* |
- | |
3602 | * There seems to be a race in PCH platform hw (at least on some |
- | |
3603 | * outputs) where an enabled pipe still completes any pageflip right |
- | |
3604 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
- | |
3605 | * as the first vblank happend, everything works as expected. Hence just |
- | |
3606 | * wait for one vblank before returning to avoid strange things |
- | |
3607 | * happening. |
- | |
3608 | */ |
4029 | |
3609 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4030 | intel_crtc_enable_planes(crtc); |
3610 | } |
4031 | } |
3611 | 4032 | ||
3612 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4033 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3613 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
4034 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3614 | { |
4035 | { |
3615 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
4036 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3616 | } |
4037 | } |
3617 | - | ||
3618 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
- | |
3619 | { |
- | |
3620 | struct drm_device *dev = crtc->dev; |
- | |
3621 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3623 | int pipe = intel_crtc->pipe; |
- | |
3624 | int plane = intel_crtc->plane; |
- | |
3625 | - | ||
3626 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
3627 | intel_enable_planes(crtc); |
- | |
3628 | intel_crtc_update_cursor(crtc, true); |
- | |
3629 | - | ||
3630 | hsw_enable_ips(intel_crtc); |
- | |
3631 | - | ||
3632 | mutex_lock(&dev->struct_mutex); |
- | |
3633 | intel_update_fbc(dev); |
- | |
3634 | mutex_unlock(&dev->struct_mutex); |
- | |
3635 | } |
- | |
3636 | - | ||
3637 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) |
- | |
3638 | { |
- | |
3639 | struct drm_device *dev = crtc->dev; |
- | |
3640 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3642 | int pipe = intel_crtc->pipe; |
- | |
3643 | int plane = intel_crtc->plane; |
- | |
3644 | - | ||
3645 | // intel_crtc_wait_for_pending_flips(crtc); |
- | |
3646 | // drm_vblank_off(dev, pipe); |
- | |
3647 | - | ||
3648 | /* FBC must be disabled before disabling the plane on HSW. */ |
- | |
3649 | if (dev_priv->fbc.plane == plane) |
- | |
3650 | intel_disable_fbc(dev); |
- | |
3651 | - | ||
3652 | hsw_disable_ips(intel_crtc); |
- | |
3653 | - | ||
3654 | intel_crtc_update_cursor(crtc, false); |
- | |
3655 | intel_disable_planes(crtc); |
- | |
3656 | intel_disable_primary_plane(dev_priv, plane, pipe); |
- | |
3657 | } |
- | |
3658 | 4038 | ||
3659 | /* |
4039 | /* |
3660 | * This implements the workaround described in the "notes" section of the mode |
4040 | * This implements the workaround described in the "notes" section of the mode |
3661 | * set sequence documentation. When going from no pipes or single pipe to |
4041 | * set sequence documentation. When going from no pipes or single pipe to |
3662 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
4042 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
3663 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
4043 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
3664 | */ |
4044 | */ |
3665 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
4045 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
3666 | { |
4046 | { |
3667 | struct drm_device *dev = crtc->base.dev; |
4047 | struct drm_device *dev = crtc->base.dev; |
3668 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
4048 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
3669 | 4049 | ||
3670 | /* We want to get the other_active_crtc only if there's only 1 other |
4050 | /* We want to get the other_active_crtc only if there's only 1 other |
3671 | * active crtc. */ |
4051 | * active crtc. */ |
3672 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { |
4052 | for_each_intel_crtc(dev, crtc_it) { |
3673 | if (!crtc_it->active || crtc_it == crtc) |
4053 | if (!crtc_it->active || crtc_it == crtc) |
3674 | continue; |
4054 | continue; |
3675 | 4055 | ||
3676 | if (other_active_crtc) |
4056 | if (other_active_crtc) |
3677 | return; |
4057 | return; |
3678 | 4058 | ||
3679 | other_active_crtc = crtc_it; |
4059 | other_active_crtc = crtc_it; |
3680 | } |
4060 | } |
3681 | if (!other_active_crtc) |
4061 | if (!other_active_crtc) |
3682 | return; |
4062 | return; |
3683 | 4063 | ||
3684 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
4064 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3685 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
4065 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3686 | } |
4066 | } |
3687 | 4067 | ||
3688 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4068 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3689 | { |
4069 | { |
3690 | struct drm_device *dev = crtc->dev; |
4070 | struct drm_device *dev = crtc->dev; |
3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
4071 | struct drm_i915_private *dev_priv = dev->dev_private; |
3692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3693 | struct intel_encoder *encoder; |
4073 | struct intel_encoder *encoder; |
3694 | int pipe = intel_crtc->pipe; |
4074 | int pipe = intel_crtc->pipe; |
- | 4075 | enum plane plane = intel_crtc->plane; |
|
3695 | 4076 | ||
3696 | WARN_ON(!crtc->enabled); |
4077 | WARN_ON(!crtc->enabled); |
3697 | 4078 | ||
3698 | if (intel_crtc->active) |
4079 | if (intel_crtc->active) |
3699 | return; |
4080 | return; |
3700 | 4081 | ||
- | 4082 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
|
3701 | intel_crtc->active = true; |
- | |
3702 | 4083 | intel_enable_shared_dpll(intel_crtc); |
|
3703 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4084 | |
- | 4085 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4086 | intel_dp_set_m_n(intel_crtc); |
|
3704 | if (intel_crtc->config.has_pch_encoder) |
4087 | |
- | 4088 | intel_set_pipe_timings(intel_crtc); |
|
- | 4089 | ||
- | 4090 | if (intel_crtc->config.has_pch_encoder) { |
|
- | 4091 | intel_cpu_transcoder_set_m_n(intel_crtc, |
|
- | 4092 | &intel_crtc->config.fdi_m_n); |
|
- | 4093 | } |
|
- | 4094 | ||
- | 4095 | haswell_set_pipeconf(crtc); |
|
- | 4096 | ||
- | 4097 | intel_set_pipe_csc(crtc); |
|
- | 4098 | ||
- | 4099 | /* Set up the display plane register */ |
|
3705 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
4100 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
- | 4101 | POSTING_READ(DSPCNTR(plane)); |
|
- | 4102 | ||
- | 4103 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
|
- | 4104 | crtc->x, crtc->y); |
|
3706 | 4105 | ||
3707 | if (intel_crtc->config.has_pch_encoder) |
4106 | intel_crtc->active = true; |
3708 | dev_priv->display.fdi_link_train(crtc); |
4107 | |
3709 | 4108 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
|
3710 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4109 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3711 | if (encoder->pre_enable) |
4110 | if (encoder->pre_enable) |
3712 | encoder->pre_enable(encoder); |
4111 | encoder->pre_enable(encoder); |
- | 4112 | ||
- | 4113 | if (intel_crtc->config.has_pch_encoder) { |
|
- | 4114 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
|
- | 4115 | dev_priv->display.fdi_link_train(crtc); |
|
- | 4116 | } |
|
3713 | 4117 | ||
3714 | intel_ddi_enable_pipe_clock(intel_crtc); |
4118 | intel_ddi_enable_pipe_clock(intel_crtc); |
3715 | 4119 | ||
3716 | ironlake_pfit_enable(intel_crtc); |
4120 | ironlake_pfit_enable(intel_crtc); |
3717 | 4121 | ||
3718 | /* |
4122 | /* |
3719 | * On ILK+ LUT must be loaded before the pipe is running but with |
4123 | * On ILK+ LUT must be loaded before the pipe is running but with |
3720 | * clocks enabled |
4124 | * clocks enabled |
3721 | */ |
4125 | */ |
3722 | intel_crtc_load_lut(crtc); |
4126 | intel_crtc_load_lut(crtc); |
3723 | 4127 | ||
3724 | intel_ddi_set_pipe_settings(crtc); |
4128 | intel_ddi_set_pipe_settings(crtc); |
3725 | intel_ddi_enable_transcoder_func(crtc); |
4129 | intel_ddi_enable_transcoder_func(crtc); |
3726 | 4130 | ||
3727 | intel_update_watermarks(crtc); |
4131 | intel_update_watermarks(crtc); |
3728 | intel_enable_pipe(dev_priv, pipe, |
4132 | intel_enable_pipe(intel_crtc); |
3729 | intel_crtc->config.has_pch_encoder, false); |
- | |
3730 | 4133 | ||
3731 | if (intel_crtc->config.has_pch_encoder) |
4134 | if (intel_crtc->config.has_pch_encoder) |
3732 | lpt_pch_enable(crtc); |
4135 | lpt_pch_enable(crtc); |
- | 4136 | ||
- | 4137 | if (intel_crtc->config.dp_encoder_is_mst) |
|
- | 4138 | intel_ddi_set_vc_payload_alloc(crtc, true); |
|
3733 | 4139 | ||
3734 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4140 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3735 | encoder->enable(encoder); |
4141 | encoder->enable(encoder); |
3736 | intel_opregion_notify_encoder(encoder, true); |
4142 | intel_opregion_notify_encoder(encoder, true); |
3737 | } |
4143 | } |
3738 | 4144 | ||
3739 | /* If we change the relative order between pipe/planes enabling, we need |
4145 | /* If we change the relative order between pipe/planes enabling, we need |
3740 | * to change the workaround. */ |
4146 | * to change the workaround. */ |
3741 | haswell_mode_set_planes_workaround(intel_crtc); |
4147 | haswell_mode_set_planes_workaround(intel_crtc); |
3742 | haswell_crtc_enable_planes(crtc); |
4148 | intel_crtc_enable_planes(crtc); |
3743 | - | ||
3744 | /* |
- | |
3745 | * There seems to be a race in PCH platform hw (at least on some |
- | |
3746 | * outputs) where an enabled pipe still completes any pageflip right |
- | |
3747 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
- | |
3748 | * as the first vblank happend, everything works as expected. Hence just |
- | |
3749 | * wait for one vblank before returning to avoid strange things |
- | |
3750 | * happening. |
- | |
3751 | */ |
- | |
3752 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
- | |
3753 | } |
4149 | } |
3754 | 4150 | ||
3755 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4151 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3756 | { |
4152 | { |
3757 | struct drm_device *dev = crtc->base.dev; |
4153 | struct drm_device *dev = crtc->base.dev; |
3758 | struct drm_i915_private *dev_priv = dev->dev_private; |
4154 | struct drm_i915_private *dev_priv = dev->dev_private; |
3759 | int pipe = crtc->pipe; |
4155 | int pipe = crtc->pipe; |
3760 | 4156 | ||
3761 | /* To avoid upsetting the power well on haswell only disable the pfit if |
4157 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3762 | * it's in use. The hw state code will make sure we get this right. */ |
4158 | * it's in use. The hw state code will make sure we get this right. */ |
3763 | if (crtc->config.pch_pfit.enabled) { |
4159 | if (crtc->config.pch_pfit.enabled) { |
3764 | I915_WRITE(PF_CTL(pipe), 0); |
4160 | I915_WRITE(PF_CTL(pipe), 0); |
3765 | I915_WRITE(PF_WIN_POS(pipe), 0); |
4161 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3766 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
4162 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3767 | } |
4163 | } |
3768 | } |
4164 | } |
3769 | 4165 | ||
3770 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4166 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3771 | { |
4167 | { |
3772 | struct drm_device *dev = crtc->dev; |
4168 | struct drm_device *dev = crtc->dev; |
3773 | struct drm_i915_private *dev_priv = dev->dev_private; |
4169 | struct drm_i915_private *dev_priv = dev->dev_private; |
3774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3775 | struct intel_encoder *encoder; |
4171 | struct intel_encoder *encoder; |
3776 | int pipe = intel_crtc->pipe; |
4172 | int pipe = intel_crtc->pipe; |
3777 | int plane = intel_crtc->plane; |
- | |
3778 | u32 reg, temp; |
4173 | u32 reg, temp; |
3779 | - | ||
3780 | 4174 | ||
3781 | if (!intel_crtc->active) |
4175 | if (!intel_crtc->active) |
3782 | return; |
4176 | return; |
- | 4177 | ||
- | 4178 | intel_crtc_disable_planes(crtc); |
|
3783 | 4179 | ||
3784 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4180 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3785 | encoder->disable(encoder); |
4181 | encoder->disable(encoder); |
3786 | - | ||
3787 | // intel_crtc_wait_for_pending_flips(crtc); |
- | |
3788 | // drm_vblank_off(dev, pipe); |
- | |
3789 | - | ||
3790 | if (dev_priv->fbc.plane == plane) |
- | |
3791 | intel_disable_fbc(dev); |
- | |
3792 | - | ||
3793 | intel_crtc_update_cursor(crtc, false); |
- | |
3794 | intel_disable_planes(crtc); |
- | |
3795 | intel_disable_primary_plane(dev_priv, plane, pipe); |
- | |
3796 | 4182 | ||
3797 | if (intel_crtc->config.has_pch_encoder) |
4183 | if (intel_crtc->config.has_pch_encoder) |
3798 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
4184 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3799 | 4185 | ||
3800 | intel_disable_pipe(dev_priv, pipe); |
4186 | intel_disable_pipe(dev_priv, pipe); |
- | 4187 | ||
- | 4188 | if (intel_crtc->config.dp_encoder_is_mst) |
|
- | 4189 | intel_ddi_set_vc_payload_alloc(crtc, false); |
|
3801 | 4190 | ||
3802 | ironlake_pfit_disable(intel_crtc); |
4191 | ironlake_pfit_disable(intel_crtc); |
3803 | 4192 | ||
3804 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4193 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3805 | if (encoder->post_disable) |
4194 | if (encoder->post_disable) |
3806 | encoder->post_disable(encoder); |
4195 | encoder->post_disable(encoder); |
3807 | 4196 | ||
3808 | if (intel_crtc->config.has_pch_encoder) { |
4197 | if (intel_crtc->config.has_pch_encoder) { |
3809 | ironlake_fdi_disable(crtc); |
4198 | ironlake_fdi_disable(crtc); |
3810 | 4199 | ||
3811 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4200 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3812 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
4201 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3813 | 4202 | ||
3814 | if (HAS_PCH_CPT(dev)) { |
4203 | if (HAS_PCH_CPT(dev)) { |
3815 | /* disable TRANS_DP_CTL */ |
4204 | /* disable TRANS_DP_CTL */ |
3816 | reg = TRANS_DP_CTL(pipe); |
4205 | reg = TRANS_DP_CTL(pipe); |
3817 | temp = I915_READ(reg); |
4206 | temp = I915_READ(reg); |
3818 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
4207 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3819 | TRANS_DP_PORT_SEL_MASK); |
4208 | TRANS_DP_PORT_SEL_MASK); |
3820 | temp |= TRANS_DP_PORT_SEL_NONE; |
4209 | temp |= TRANS_DP_PORT_SEL_NONE; |
3821 | I915_WRITE(reg, temp); |
4210 | I915_WRITE(reg, temp); |
3822 | 4211 | ||
3823 | /* disable DPLL_SEL */ |
4212 | /* disable DPLL_SEL */ |
3824 | temp = I915_READ(PCH_DPLL_SEL); |
4213 | temp = I915_READ(PCH_DPLL_SEL); |
3825 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
4214 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3826 | I915_WRITE(PCH_DPLL_SEL, temp); |
4215 | I915_WRITE(PCH_DPLL_SEL, temp); |
3827 | } |
4216 | } |
3828 | 4217 | ||
3829 | /* disable PCH DPLL */ |
4218 | /* disable PCH DPLL */ |
3830 | intel_disable_shared_dpll(intel_crtc); |
4219 | intel_disable_shared_dpll(intel_crtc); |
3831 | 4220 | ||
3832 | ironlake_fdi_pll_disable(intel_crtc); |
4221 | ironlake_fdi_pll_disable(intel_crtc); |
3833 | } |
4222 | } |
3834 | 4223 | ||
3835 | intel_crtc->active = false; |
4224 | intel_crtc->active = false; |
3836 | intel_update_watermarks(crtc); |
4225 | intel_update_watermarks(crtc); |
3837 | 4226 | ||
3838 | mutex_lock(&dev->struct_mutex); |
4227 | mutex_lock(&dev->struct_mutex); |
3839 | intel_update_fbc(dev); |
4228 | intel_update_fbc(dev); |
3840 | mutex_unlock(&dev->struct_mutex); |
4229 | mutex_unlock(&dev->struct_mutex); |
3841 | } |
4230 | } |
3842 | 4231 | ||
3843 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
4232 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3844 | { |
4233 | { |
3845 | struct drm_device *dev = crtc->dev; |
4234 | struct drm_device *dev = crtc->dev; |
3846 | struct drm_i915_private *dev_priv = dev->dev_private; |
4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
3847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3848 | struct intel_encoder *encoder; |
4237 | struct intel_encoder *encoder; |
3849 | int pipe = intel_crtc->pipe; |
4238 | int pipe = intel_crtc->pipe; |
3850 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4239 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3851 | 4240 | ||
3852 | if (!intel_crtc->active) |
4241 | if (!intel_crtc->active) |
3853 | return; |
4242 | return; |
3854 | 4243 | ||
3855 | haswell_crtc_disable_planes(crtc); |
4244 | intel_crtc_disable_planes(crtc); |
3856 | 4245 | ||
3857 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4246 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3858 | intel_opregion_notify_encoder(encoder, false); |
4247 | intel_opregion_notify_encoder(encoder, false); |
3859 | encoder->disable(encoder); |
4248 | encoder->disable(encoder); |
3860 | } |
4249 | } |
3861 | 4250 | ||
3862 | if (intel_crtc->config.has_pch_encoder) |
4251 | if (intel_crtc->config.has_pch_encoder) |
3863 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
4252 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3864 | intel_disable_pipe(dev_priv, pipe); |
4253 | intel_disable_pipe(dev_priv, pipe); |
3865 | 4254 | ||
3866 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4255 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
3867 | 4256 | ||
3868 | ironlake_pfit_disable(intel_crtc); |
4257 | ironlake_pfit_disable(intel_crtc); |
3869 | 4258 | ||
3870 | intel_ddi_disable_pipe_clock(intel_crtc); |
4259 | intel_ddi_disable_pipe_clock(intel_crtc); |
3871 | - | ||
3872 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
3873 | if (encoder->post_disable) |
- | |
3874 | encoder->post_disable(encoder); |
- | |
3875 | 4260 | ||
3876 | if (intel_crtc->config.has_pch_encoder) { |
4261 | if (intel_crtc->config.has_pch_encoder) { |
3877 | lpt_disable_pch_transcoder(dev_priv); |
4262 | lpt_disable_pch_transcoder(dev_priv); |
3878 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
4263 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3879 | intel_ddi_fdi_disable(crtc); |
4264 | intel_ddi_fdi_disable(crtc); |
3880 | } |
4265 | } |
- | 4266 | ||
- | 4267 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 4268 | if (encoder->post_disable) |
|
- | 4269 | encoder->post_disable(encoder); |
|
3881 | 4270 | ||
3882 | intel_crtc->active = false; |
4271 | intel_crtc->active = false; |
3883 | intel_update_watermarks(crtc); |
4272 | intel_update_watermarks(crtc); |
3884 | 4273 | ||
3885 | mutex_lock(&dev->struct_mutex); |
4274 | mutex_lock(&dev->struct_mutex); |
3886 | intel_update_fbc(dev); |
4275 | intel_update_fbc(dev); |
3887 | mutex_unlock(&dev->struct_mutex); |
4276 | mutex_unlock(&dev->struct_mutex); |
- | 4277 | ||
- | 4278 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
|
- | 4279 | intel_disable_shared_dpll(intel_crtc); |
|
3888 | } |
4280 | } |
3889 | 4281 | ||
3890 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4282 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3891 | { |
4283 | { |
3892 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3893 | intel_put_shared_dpll(intel_crtc); |
4285 | intel_put_shared_dpll(intel_crtc); |
3894 | } |
4286 | } |
3895 | - | ||
3896 | static void haswell_crtc_off(struct drm_crtc *crtc) |
- | |
3897 | { |
- | |
3898 | intel_ddi_put_crtc_pll(crtc); |
- | |
3899 | } |
- | |
3900 | - | ||
3901 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
- | |
3902 | { |
- | |
3903 | if (!enable && intel_crtc->overlay) { |
- | |
3904 | struct drm_device *dev = intel_crtc->base.dev; |
- | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3906 | - | ||
3907 | mutex_lock(&dev->struct_mutex); |
- | |
3908 | dev_priv->mm.interruptible = false; |
- | |
3909 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
- | |
3910 | dev_priv->mm.interruptible = true; |
- | |
3911 | mutex_unlock(&dev->struct_mutex); |
- | |
3912 | } |
- | |
3913 | - | ||
3914 | /* Let userspace switch the overlay on again. In most cases userspace |
- | |
3915 | * has to recompute where to put it anyway. |
- | |
3916 | */ |
- | |
3917 | } |
- | |
3918 | - | ||
3919 | /** |
- | |
3920 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
- | |
3921 | * cursor plane briefly if not already running after enabling the display |
- | |
3922 | * plane. |
- | |
3923 | * This workaround avoids occasional blank screens when self refresh is |
- | |
3924 | * enabled. |
- | |
3925 | */ |
- | |
3926 | static void |
- | |
3927 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
- | |
3928 | { |
- | |
3929 | u32 cntl = I915_READ(CURCNTR(pipe)); |
- | |
3930 | - | ||
3931 | if ((cntl & CURSOR_MODE) == 0) { |
- | |
3932 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
- | |
3933 | - | ||
3934 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
- | |
3935 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
- | |
3936 | intel_wait_for_vblank(dev_priv->dev, pipe); |
- | |
3937 | I915_WRITE(CURCNTR(pipe), cntl); |
- | |
3938 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
- | |
3939 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
- | |
3940 | } |
- | |
3941 | } |
4287 | |
3942 | 4288 | ||
3943 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4289 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3944 | { |
4290 | { |
3945 | struct drm_device *dev = crtc->base.dev; |
4291 | struct drm_device *dev = crtc->base.dev; |
3946 | struct drm_i915_private *dev_priv = dev->dev_private; |
4292 | struct drm_i915_private *dev_priv = dev->dev_private; |
3947 | struct intel_crtc_config *pipe_config = &crtc->config; |
4293 | struct intel_crtc_config *pipe_config = &crtc->config; |
3948 | 4294 | ||
3949 | if (!crtc->config.gmch_pfit.control) |
4295 | if (!crtc->config.gmch_pfit.control) |
3950 | return; |
4296 | return; |
3951 | 4297 | ||
3952 | /* |
4298 | /* |
3953 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4299 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3954 | * according to register description and PRM. |
4300 | * according to register description and PRM. |
3955 | */ |
4301 | */ |
3956 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4302 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3957 | assert_pipe_disabled(dev_priv, crtc->pipe); |
4303 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3958 | 4304 | ||
3959 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4305 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3960 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
4306 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
3961 | 4307 | ||
3962 | /* Border color in case we don't scale up to the full screen. Black by |
4308 | /* Border color in case we don't scale up to the full screen. Black by |
3963 | * default, change to something else for debugging. */ |
4309 | * default, change to something else for debugging. */ |
3964 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
4310 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3965 | } |
4311 | } |
- | 4312 | ||
- | 4313 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
|
- | 4314 | { |
|
- | 4315 | switch (port) { |
|
- | 4316 | case PORT_A: |
|
- | 4317 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
|
- | 4318 | case PORT_B: |
|
- | 4319 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
|
- | 4320 | case PORT_C: |
|
- | 4321 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
|
- | 4322 | case PORT_D: |
|
- | 4323 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
|
- | 4324 | default: |
|
- | 4325 | WARN_ON_ONCE(1); |
|
- | 4326 | return POWER_DOMAIN_PORT_OTHER; |
|
- | 4327 | } |
|
- | 4328 | } |
|
- | 4329 | ||
- | 4330 | #define for_each_power_domain(domain, mask) \ |
|
- | 4331 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
|
- | 4332 | if ((1 << (domain)) & (mask)) |
|
- | 4333 | ||
- | 4334 | enum intel_display_power_domain |
|
- | 4335 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
|
- | 4336 | { |
|
- | 4337 | struct drm_device *dev = intel_encoder->base.dev; |
|
- | 4338 | struct intel_digital_port *intel_dig_port; |
|
- | 4339 | ||
- | 4340 | switch (intel_encoder->type) { |
|
- | 4341 | case INTEL_OUTPUT_UNKNOWN: |
|
- | 4342 | /* Only DDI platforms should ever use this output type */ |
|
- | 4343 | WARN_ON_ONCE(!HAS_DDI(dev)); |
|
- | 4344 | case INTEL_OUTPUT_DISPLAYPORT: |
|
- | 4345 | case INTEL_OUTPUT_HDMI: |
|
- | 4346 | case INTEL_OUTPUT_EDP: |
|
- | 4347 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
|
- | 4348 | return port_to_power_domain(intel_dig_port->port); |
|
- | 4349 | case INTEL_OUTPUT_DP_MST: |
|
- | 4350 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
|
- | 4351 | return port_to_power_domain(intel_dig_port->port); |
|
- | 4352 | case INTEL_OUTPUT_ANALOG: |
|
- | 4353 | return POWER_DOMAIN_PORT_CRT; |
|
- | 4354 | case INTEL_OUTPUT_DSI: |
|
- | 4355 | return POWER_DOMAIN_PORT_DSI; |
|
- | 4356 | default: |
|
- | 4357 | return POWER_DOMAIN_PORT_OTHER; |
|
- | 4358 | } |
|
- | 4359 | } |
|
- | 4360 | ||
- | 4361 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
|
- | 4362 | { |
|
- | 4363 | struct drm_device *dev = crtc->dev; |
|
- | 4364 | struct intel_encoder *intel_encoder; |
|
- | 4365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 4366 | enum pipe pipe = intel_crtc->pipe; |
|
- | 4367 | unsigned long mask; |
|
- | 4368 | enum transcoder transcoder; |
|
- | 4369 | ||
- | 4370 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
|
- | 4371 | ||
- | 4372 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
|
- | 4373 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
|
- | 4374 | if (intel_crtc->config.pch_pfit.enabled || |
|
- | 4375 | intel_crtc->config.pch_pfit.force_thru) |
|
- | 4376 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
|
- | 4377 | ||
- | 4378 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
|
- | 4379 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
|
- | 4380 | ||
- | 4381 | return mask; |
|
- | 4382 | } |
|
- | 4383 | ||
- | 4384 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
|
- | 4385 | bool enable) |
|
- | 4386 | { |
|
- | 4387 | if (dev_priv->power_domains.init_power_on == enable) |
|
- | 4388 | return; |
|
- | 4389 | ||
- | 4390 | if (enable) |
|
- | 4391 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
|
- | 4392 | else |
|
- | 4393 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
|
- | 4394 | ||
- | 4395 | dev_priv->power_domains.init_power_on = enable; |
|
- | 4396 | } |
|
- | 4397 | ||
- | 4398 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
|
- | 4399 | { |
|
- | 4400 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4401 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
|
- | 4402 | struct intel_crtc *crtc; |
|
- | 4403 | ||
- | 4404 | /* |
|
- | 4405 | * First get all needed power domains, then put all unneeded, to avoid |
|
- | 4406 | * any unnecessary toggling of the power wells. |
|
- | 4407 | */ |
|
- | 4408 | for_each_intel_crtc(dev, crtc) { |
|
- | 4409 | enum intel_display_power_domain domain; |
|
- | 4410 | ||
- | 4411 | if (!crtc->base.enabled) |
|
- | 4412 | continue; |
|
- | 4413 | ||
- | 4414 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
|
- | 4415 | ||
- | 4416 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
|
- | 4417 | intel_display_power_get(dev_priv, domain); |
|
- | 4418 | } |
|
- | 4419 | ||
- | 4420 | for_each_intel_crtc(dev, crtc) { |
|
- | 4421 | enum intel_display_power_domain domain; |
|
- | 4422 | ||
- | 4423 | for_each_power_domain(domain, crtc->enabled_power_domains) |
|
- | 4424 | intel_display_power_put(dev_priv, domain); |
|
- | 4425 | ||
- | 4426 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
|
- | 4427 | } |
|
- | 4428 | ||
- | 4429 | intel_display_set_init_power(dev_priv, false); |
|
- | 4430 | } |
|
- | 4431 | ||
3966 | 4432 | /* returns HPLL frequency in kHz */ |
|
3967 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
4433 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
3968 | { |
4434 | { |
3969 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
4435 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
3970 | 4436 | ||
3971 | /* Obtain SKU information */ |
4437 | /* Obtain SKU information */ |
3972 | mutex_lock(&dev_priv->dpio_lock); |
4438 | mutex_lock(&dev_priv->dpio_lock); |
3973 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
4439 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
3974 | CCK_FUSE_HPLL_FREQ_MASK; |
4440 | CCK_FUSE_HPLL_FREQ_MASK; |
3975 | mutex_unlock(&dev_priv->dpio_lock); |
4441 | mutex_unlock(&dev_priv->dpio_lock); |
3976 | 4442 | ||
- | 4443 | return vco_freq[hpll_freq] * 1000; |
|
- | 4444 | } |
|
- | 4445 | ||
- | 4446 | static void vlv_update_cdclk(struct drm_device *dev) |
|
- | 4447 | { |
|
- | 4448 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4449 | ||
- | 4450 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
|
- | 4451 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", |
|
- | 4452 | dev_priv->vlv_cdclk_freq); |
|
- | 4453 | ||
- | 4454 | /* |
|
- | 4455 | * Program the gmbus_freq based on the cdclk frequency. |
|
- | 4456 | * BSpec erroneously claims we should aim for 4MHz, but |
|
- | 4457 | * in fact 1MHz is the correct frequency. |
|
- | 4458 | */ |
|
3977 | return vco_freq[hpll_freq]; |
4459 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); |
3978 | } |
4460 | } |
3979 | 4461 | ||
3980 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4462 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
3981 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
4463 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
3982 | { |
4464 | { |
3983 | struct drm_i915_private *dev_priv = dev->dev_private; |
4465 | struct drm_i915_private *dev_priv = dev->dev_private; |
3984 | u32 val, cmd; |
4466 | u32 val, cmd; |
- | 4467 | ||
- | 4468 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
|
3985 | 4469 | ||
3986 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4470 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
3987 | cmd = 2; |
4471 | cmd = 2; |
3988 | else if (cdclk == 266) |
4472 | else if (cdclk == 266667) |
3989 | cmd = 1; |
4473 | cmd = 1; |
3990 | else |
4474 | else |
3991 | cmd = 0; |
4475 | cmd = 0; |
3992 | 4476 | ||
3993 | mutex_lock(&dev_priv->rps.hw_lock); |
4477 | mutex_lock(&dev_priv->rps.hw_lock); |
3994 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
4478 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
3995 | val &= ~DSPFREQGUAR_MASK; |
4479 | val &= ~DSPFREQGUAR_MASK; |
3996 | val |= (cmd << DSPFREQGUAR_SHIFT); |
4480 | val |= (cmd << DSPFREQGUAR_SHIFT); |
3997 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
4481 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
3998 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
4482 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
3999 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
4483 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
4000 | 50)) { |
4484 | 50)) { |
4001 | DRM_ERROR("timed out waiting for CDclk change\n"); |
4485 | DRM_ERROR("timed out waiting for CDclk change\n"); |
4002 | } |
4486 | } |
4003 | mutex_unlock(&dev_priv->rps.hw_lock); |
4487 | mutex_unlock(&dev_priv->rps.hw_lock); |
4004 | 4488 | ||
4005 | if (cdclk == 400) { |
4489 | if (cdclk == 400000) { |
4006 | u32 divider, vco; |
4490 | u32 divider, vco; |
4007 | 4491 | ||
4008 | vco = valleyview_get_vco(dev_priv); |
4492 | vco = valleyview_get_vco(dev_priv); |
4009 | divider = ((vco << 1) / cdclk) - 1; |
4493 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
4010 | 4494 | ||
4011 | mutex_lock(&dev_priv->dpio_lock); |
4495 | mutex_lock(&dev_priv->dpio_lock); |
4012 | /* adjust cdclk divider */ |
4496 | /* adjust cdclk divider */ |
4013 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
4497 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
4014 | val &= ~0xf; |
4498 | val &= ~DISPLAY_FREQUENCY_VALUES; |
4015 | val |= divider; |
4499 | val |= divider; |
4016 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
4500 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
- | 4501 | ||
- | 4502 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
|
- | 4503 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
|
- | 4504 | 50)) |
|
- | 4505 | DRM_ERROR("timed out waiting for CDclk change\n"); |
|
4017 | mutex_unlock(&dev_priv->dpio_lock); |
4506 | mutex_unlock(&dev_priv->dpio_lock); |
4018 | } |
4507 | } |
4019 | 4508 | ||
4020 | mutex_lock(&dev_priv->dpio_lock); |
4509 | mutex_lock(&dev_priv->dpio_lock); |
4021 | /* adjust self-refresh exit latency value */ |
4510 | /* adjust self-refresh exit latency value */ |
4022 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
4511 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
4023 | val &= ~0x7f; |
4512 | val &= ~0x7f; |
4024 | 4513 | ||
4025 | /* |
4514 | /* |
4026 | * For high bandwidth configs, we set a higher latency in the bunit |
4515 | * For high bandwidth configs, we set a higher latency in the bunit |
4027 | * so that the core display fetch happens in time to avoid underruns. |
4516 | * so that the core display fetch happens in time to avoid underruns. |
4028 | */ |
4517 | */ |
4029 | if (cdclk == 400) |
4518 | if (cdclk == 400000) |
4030 | val |= 4500 / 250; /* 4.5 usec */ |
4519 | val |= 4500 / 250; /* 4.5 usec */ |
4031 | else |
4520 | else |
4032 | val |= 3000 / 250; /* 3.0 usec */ |
4521 | val |= 3000 / 250; /* 3.0 usec */ |
4033 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
4522 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
4034 | mutex_unlock(&dev_priv->dpio_lock); |
4523 | mutex_unlock(&dev_priv->dpio_lock); |
4035 | - | ||
4036 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ |
4524 | |
4037 | intel_i2c_reset(dev); |
- | |
4038 | } |
- | |
4039 | - | ||
4040 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
- | |
4041 | { |
- | |
4042 | int cur_cdclk, vco; |
- | |
4043 | int divider; |
- | |
4044 | - | ||
4045 | vco = valleyview_get_vco(dev_priv); |
- | |
4046 | - | ||
4047 | mutex_lock(&dev_priv->dpio_lock); |
- | |
4048 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
- | |
4049 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
4050 | - | ||
4051 | divider &= 0xf; |
- | |
4052 | - | ||
4053 | cur_cdclk = (vco << 1) / (divider + 1); |
- | |
4054 | - | ||
4055 | return cur_cdclk; |
4525 | vlv_update_cdclk(dev); |
4056 | } |
4526 | } |
4057 | 4527 | ||
4058 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4528 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4059 | int max_pixclk) |
4529 | int max_pixclk) |
4060 | { |
4530 | { |
4061 | int cur_cdclk; |
- | |
4062 | - | ||
4063 | cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4531 | int vco = valleyview_get_vco(dev_priv); |
- | 4532 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; |
|
4064 | 4533 | ||
4065 | /* |
4534 | /* |
4066 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
4535 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
4067 | * 200MHz |
4536 | * 200MHz |
4068 | * 267MHz |
4537 | * 267MHz |
4069 | * 320MHz |
4538 | * 320/333MHz (depends on HPLL freq) |
4070 | * 400MHz |
4539 | * 400MHz |
4071 | * So we check to see whether we're above 90% of the lower bin and |
4540 | * So we check to see whether we're above 90% of the lower bin and |
4072 | * adjust if needed. |
4541 | * adjust if needed. |
- | 4542 | * |
|
- | 4543 | * We seem to get an unstable or solid color picture at 200MHz. |
|
- | 4544 | * Not sure what's wrong. For now use 200MHz only when all pipes |
|
- | 4545 | * are off. |
|
4073 | */ |
4546 | */ |
4074 | if (max_pixclk > 288000) { |
4547 | if (max_pixclk > freq_320*9/10) |
4075 | return 400; |
4548 | return 400000; |
4076 | } else if (max_pixclk > 240000) { |
4549 | else if (max_pixclk > 266667*9/10) |
4077 | return 320; |
4550 | return freq_320; |
- | 4551 | else if (max_pixclk > 0) |
|
- | 4552 | return 266667; |
|
4078 | } else |
4553 | else |
4079 | return 266; |
4554 | return 200000; |
4080 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
- | |
4081 | } |
4555 | } |
- | 4556 | ||
4082 | 4557 | /* compute the max pixel clock for new configuration */ |
|
4083 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, |
- | |
4084 | unsigned modeset_pipes, |
- | |
4085 | struct intel_crtc_config *pipe_config) |
4558 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
4086 | { |
4559 | { |
4087 | struct drm_device *dev = dev_priv->dev; |
4560 | struct drm_device *dev = dev_priv->dev; |
4088 | struct intel_crtc *intel_crtc; |
4561 | struct intel_crtc *intel_crtc; |
4089 | int max_pixclk = 0; |
4562 | int max_pixclk = 0; |
4090 | 4563 | ||
4091 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
- | |
4092 | base.head) { |
- | |
4093 | if (modeset_pipes & (1 << intel_crtc->pipe)) |
- | |
4094 | max_pixclk = max(max_pixclk, |
- | |
4095 | pipe_config->adjusted_mode.crtc_clock); |
4564 | for_each_intel_crtc(dev, intel_crtc) { |
4096 | else if (intel_crtc->base.enabled) |
4565 | if (intel_crtc->new_enabled) |
4097 | max_pixclk = max(max_pixclk, |
4566 | max_pixclk = max(max_pixclk, |
4098 | intel_crtc->config.adjusted_mode.crtc_clock); |
4567 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
4099 | } |
4568 | } |
4100 | 4569 | ||
4101 | return max_pixclk; |
4570 | return max_pixclk; |
4102 | } |
4571 | } |
4103 | 4572 | ||
4104 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
4573 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
4105 | unsigned *prepare_pipes, |
4574 | unsigned *prepare_pipes) |
4106 | unsigned modeset_pipes, |
- | |
4107 | struct intel_crtc_config *pipe_config) |
- | |
4108 | { |
4575 | { |
4109 | struct drm_i915_private *dev_priv = dev->dev_private; |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; |
4110 | struct intel_crtc *intel_crtc; |
4577 | struct intel_crtc *intel_crtc; |
4111 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, |
4578 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
4112 | pipe_config); |
- | |
4113 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
- | |
4114 | 4579 | ||
- | 4580 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
|
4115 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) |
4581 | dev_priv->vlv_cdclk_freq) |
4116 | return; |
4582 | return; |
4117 | 4583 | ||
4118 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4584 | /* disable/enable all currently active pipes while we change cdclk */ |
4119 | base.head) |
4585 | for_each_intel_crtc(dev, intel_crtc) |
4120 | if (intel_crtc->base.enabled) |
4586 | if (intel_crtc->base.enabled) |
4121 | *prepare_pipes |= (1 << intel_crtc->pipe); |
4587 | *prepare_pipes |= (1 << intel_crtc->pipe); |
4122 | } |
4588 | } |
4123 | 4589 | ||
4124 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
4590 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
4125 | { |
4591 | { |
4126 | struct drm_i915_private *dev_priv = dev->dev_private; |
4592 | struct drm_i915_private *dev_priv = dev->dev_private; |
4127 | int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL); |
4593 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
4128 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
- | |
4129 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4594 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4130 | 4595 | ||
4131 | if (req_cdclk != cur_cdclk) |
4596 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
- | 4597 | valleyview_set_cdclk(dev, req_cdclk); |
|
4132 | valleyview_set_cdclk(dev, req_cdclk); |
4598 | modeset_update_crtc_power_domains(dev); |
4133 | } |
4599 | } |
4134 | 4600 | ||
4135 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4601 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4136 | { |
4602 | { |
4137 | struct drm_device *dev = crtc->dev; |
4603 | struct drm_device *dev = crtc->dev; |
4138 | struct drm_i915_private *dev_priv = dev->dev_private; |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; |
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4140 | struct intel_encoder *encoder; |
4606 | struct intel_encoder *encoder; |
4141 | int pipe = intel_crtc->pipe; |
4607 | int pipe = intel_crtc->pipe; |
4142 | int plane = intel_crtc->plane; |
4608 | int plane = intel_crtc->plane; |
4143 | bool is_dsi; |
4609 | bool is_dsi; |
- | 4610 | u32 dspcntr; |
|
4144 | 4611 | ||
4145 | WARN_ON(!crtc->enabled); |
4612 | WARN_ON(!crtc->enabled); |
4146 | 4613 | ||
4147 | if (intel_crtc->active) |
4614 | if (intel_crtc->active) |
4148 | return; |
4615 | return; |
- | 4616 | ||
- | 4617 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
|
- | 4618 | ||
- | 4619 | if (!is_dsi && !IS_CHERRYVIEW(dev)) |
|
- | 4620 | vlv_prepare_pll(intel_crtc); |
|
- | 4621 | ||
- | 4622 | /* Set up the display plane register */ |
|
- | 4623 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
|
- | 4624 | ||
- | 4625 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4626 | intel_dp_set_m_n(intel_crtc); |
|
- | 4627 | ||
- | 4628 | intel_set_pipe_timings(intel_crtc); |
|
- | 4629 | ||
- | 4630 | /* pipesrc and dspsize control the size that is scaled from, |
|
- | 4631 | * which should always be the user's requested size. |
|
- | 4632 | */ |
|
- | 4633 | I915_WRITE(DSPSIZE(plane), |
|
- | 4634 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
|
- | 4635 | (intel_crtc->config.pipe_src_w - 1)); |
|
- | 4636 | I915_WRITE(DSPPOS(plane), 0); |
|
- | 4637 | ||
- | 4638 | i9xx_set_pipeconf(intel_crtc); |
|
- | 4639 | ||
- | 4640 | I915_WRITE(DSPCNTR(plane), dspcntr); |
|
- | 4641 | POSTING_READ(DSPCNTR(plane)); |
|
- | 4642 | ||
- | 4643 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
|
- | 4644 | crtc->x, crtc->y); |
|
4149 | 4645 | ||
- | 4646 | intel_crtc->active = true; |
|
- | 4647 | ||
4150 | intel_crtc->active = true; |
4648 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4151 | 4649 | ||
4152 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4650 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4153 | if (encoder->pre_pll_enable) |
4651 | if (encoder->pre_pll_enable) |
4154 | encoder->pre_pll_enable(encoder); |
4652 | encoder->pre_pll_enable(encoder); |
4155 | - | ||
4156 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
- | |
4157 | 4653 | ||
- | 4654 | if (!is_dsi) { |
|
- | 4655 | if (IS_CHERRYVIEW(dev)) |
|
- | 4656 | chv_enable_pll(intel_crtc); |
|
4158 | if (!is_dsi) |
4657 | else |
- | 4658 | vlv_enable_pll(intel_crtc); |
|
4159 | vlv_enable_pll(intel_crtc); |
4659 | } |
4160 | 4660 | ||
4161 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4661 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4162 | if (encoder->pre_enable) |
4662 | if (encoder->pre_enable) |
4163 | encoder->pre_enable(encoder); |
4663 | encoder->pre_enable(encoder); |
4164 | 4664 | ||
4165 | i9xx_pfit_enable(intel_crtc); |
4665 | i9xx_pfit_enable(intel_crtc); |
4166 | 4666 | ||
4167 | intel_crtc_load_lut(crtc); |
4667 | intel_crtc_load_lut(crtc); |
4168 | 4668 | ||
4169 | intel_update_watermarks(crtc); |
4669 | intel_update_watermarks(crtc); |
4170 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
- | |
4171 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
4172 | intel_enable_planes(crtc); |
4670 | intel_enable_pipe(intel_crtc); |
4173 | intel_crtc_update_cursor(crtc, true); |
- | |
4174 | - | ||
4175 | intel_update_fbc(dev); |
- | |
4176 | 4671 | ||
4177 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4672 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4178 | encoder->enable(encoder); |
4673 | encoder->enable(encoder); |
- | 4674 | ||
- | 4675 | intel_crtc_enable_planes(crtc); |
|
- | 4676 | ||
- | 4677 | /* Underruns don't raise interrupts, so check manually. */ |
|
- | 4678 | i9xx_check_fifo_underruns(dev); |
|
- | 4679 | } |
|
- | 4680 | ||
- | 4681 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
|
- | 4682 | { |
|
- | 4683 | struct drm_device *dev = crtc->base.dev; |
|
- | 4684 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4685 | ||
- | 4686 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); |
|
- | 4687 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); |
|
4179 | } |
4688 | } |
4180 | 4689 | ||
4181 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
4690 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
4182 | { |
4691 | { |
4183 | struct drm_device *dev = crtc->dev; |
4692 | struct drm_device *dev = crtc->dev; |
4184 | struct drm_i915_private *dev_priv = dev->dev_private; |
4693 | struct drm_i915_private *dev_priv = dev->dev_private; |
4185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4186 | struct intel_encoder *encoder; |
4695 | struct intel_encoder *encoder; |
4187 | int pipe = intel_crtc->pipe; |
4696 | int pipe = intel_crtc->pipe; |
4188 | int plane = intel_crtc->plane; |
4697 | int plane = intel_crtc->plane; |
- | 4698 | u32 dspcntr; |
|
4189 | 4699 | ||
4190 | WARN_ON(!crtc->enabled); |
4700 | WARN_ON(!crtc->enabled); |
4191 | 4701 | ||
4192 | if (intel_crtc->active) |
4702 | if (intel_crtc->active) |
4193 | return; |
4703 | return; |
- | 4704 | ||
- | 4705 | i9xx_set_pll_dividers(intel_crtc); |
|
- | 4706 | ||
- | 4707 | /* Set up the display plane register */ |
|
- | 4708 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
|
- | 4709 | ||
- | 4710 | if (pipe == 0) |
|
- | 4711 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
|
- | 4712 | else |
|
- | 4713 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
|
- | 4714 | ||
- | 4715 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4716 | intel_dp_set_m_n(intel_crtc); |
|
- | 4717 | ||
- | 4718 | intel_set_pipe_timings(intel_crtc); |
|
- | 4719 | ||
- | 4720 | /* pipesrc and dspsize control the size that is scaled from, |
|
- | 4721 | * which should always be the user's requested size. |
|
- | 4722 | */ |
|
- | 4723 | I915_WRITE(DSPSIZE(plane), |
|
- | 4724 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
|
- | 4725 | (intel_crtc->config.pipe_src_w - 1)); |
|
- | 4726 | I915_WRITE(DSPPOS(plane), 0); |
|
- | 4727 | ||
- | 4728 | i9xx_set_pipeconf(intel_crtc); |
|
- | 4729 | ||
- | 4730 | I915_WRITE(DSPCNTR(plane), dspcntr); |
|
- | 4731 | POSTING_READ(DSPCNTR(plane)); |
|
- | 4732 | ||
- | 4733 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
|
- | 4734 | crtc->x, crtc->y); |
|
4194 | 4735 | ||
- | 4736 | intel_crtc->active = true; |
|
- | 4737 | ||
- | 4738 | if (!IS_GEN2(dev)) |
|
4195 | intel_crtc->active = true; |
4739 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4196 | 4740 | ||
4197 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4741 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4198 | if (encoder->pre_enable) |
4742 | if (encoder->pre_enable) |
4199 | encoder->pre_enable(encoder); |
4743 | encoder->pre_enable(encoder); |
4200 | 4744 | ||
4201 | i9xx_enable_pll(intel_crtc); |
4745 | i9xx_enable_pll(intel_crtc); |
4202 | 4746 | ||
4203 | i9xx_pfit_enable(intel_crtc); |
4747 | i9xx_pfit_enable(intel_crtc); |
4204 | 4748 | ||
4205 | intel_crtc_load_lut(crtc); |
4749 | intel_crtc_load_lut(crtc); |
4206 | 4750 | ||
4207 | intel_update_watermarks(crtc); |
4751 | intel_update_watermarks(crtc); |
4208 | intel_enable_pipe(dev_priv, pipe, false, false); |
- | |
4209 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
4210 | intel_enable_planes(crtc); |
4752 | intel_enable_pipe(intel_crtc); |
4211 | /* The fixup needs to happen before cursor is enabled */ |
- | |
4212 | if (IS_G4X(dev)) |
- | |
4213 | g4x_fixup_plane(dev_priv, pipe); |
- | |
4214 | intel_crtc_update_cursor(crtc, true); |
- | |
4215 | - | ||
4216 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
- | |
4217 | intel_crtc_dpms_overlay(intel_crtc, true); |
- | |
4218 | - | ||
4219 | intel_update_fbc(dev); |
- | |
4220 | 4753 | ||
4221 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4754 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4222 | encoder->enable(encoder); |
4755 | encoder->enable(encoder); |
- | 4756 | ||
- | 4757 | intel_crtc_enable_planes(crtc); |
|
- | 4758 | ||
- | 4759 | /* |
|
- | 4760 | * Gen2 reports pipe underruns whenever all planes are disabled. |
|
- | 4761 | * So don't enable underrun reporting before at least some planes |
|
- | 4762 | * are enabled. |
|
- | 4763 | * FIXME: Need to fix the logic to work when we turn off all planes |
|
- | 4764 | * but leave the pipe running. |
|
- | 4765 | */ |
|
- | 4766 | if (IS_GEN2(dev)) |
|
- | 4767 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
|
- | 4768 | ||
- | 4769 | /* Underruns don't raise interrupts, so check manually. */ |
|
- | 4770 | i9xx_check_fifo_underruns(dev); |
|
4223 | } |
4771 | } |
4224 | 4772 | ||
4225 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4773 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4226 | { |
4774 | { |
4227 | struct drm_device *dev = crtc->base.dev; |
4775 | struct drm_device *dev = crtc->base.dev; |
4228 | struct drm_i915_private *dev_priv = dev->dev_private; |
4776 | struct drm_i915_private *dev_priv = dev->dev_private; |
4229 | 4777 | ||
4230 | if (!crtc->config.gmch_pfit.control) |
4778 | if (!crtc->config.gmch_pfit.control) |
4231 | return; |
4779 | return; |
4232 | 4780 | ||
4233 | assert_pipe_disabled(dev_priv, crtc->pipe); |
4781 | assert_pipe_disabled(dev_priv, crtc->pipe); |
4234 | 4782 | ||
4235 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4783 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4236 | I915_READ(PFIT_CONTROL)); |
4784 | I915_READ(PFIT_CONTROL)); |
4237 | I915_WRITE(PFIT_CONTROL, 0); |
4785 | I915_WRITE(PFIT_CONTROL, 0); |
4238 | } |
4786 | } |
4239 | 4787 | ||
4240 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4788 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4241 | { |
4789 | { |
4242 | struct drm_device *dev = crtc->dev; |
4790 | struct drm_device *dev = crtc->dev; |
4243 | struct drm_i915_private *dev_priv = dev->dev_private; |
4791 | struct drm_i915_private *dev_priv = dev->dev_private; |
4244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4245 | struct intel_encoder *encoder; |
4793 | struct intel_encoder *encoder; |
4246 | int pipe = intel_crtc->pipe; |
4794 | int pipe = intel_crtc->pipe; |
4247 | int plane = intel_crtc->plane; |
- | |
4248 | 4795 | ||
4249 | if (!intel_crtc->active) |
4796 | if (!intel_crtc->active) |
4250 | return; |
4797 | return; |
- | 4798 | ||
- | 4799 | /* |
|
4251 | 4800 | * Gen2 reports pipe underruns whenever all planes are disabled. |
|
- | 4801 | * So diasble underrun reporting before all the planes get disabled. |
|
4252 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4802 | * FIXME: Need to fix the logic to work when we turn off all planes |
- | 4803 | * but leave the pipe running. |
|
- | 4804 | */ |
|
- | 4805 | if (IS_GEN2(dev)) |
|
- | 4806 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
|
- | 4807 | ||
- | 4808 | /* |
|
- | 4809 | * Vblank time updates from the shadow to live plane control register |
|
- | 4810 | * are blocked if the memory self-refresh mode is active at that |
|
- | 4811 | * moment. So to make sure the plane gets truly disabled, disable |
|
- | 4812 | * first the self-refresh mode. The self-refresh enable bit in turn |
|
4253 | encoder->disable(encoder); |
4813 | * will be checked/applied by the HW only at the next frame start |
- | 4814 | * event which is after the vblank start event, so we need to have a |
|
4254 | 4815 | * wait-for-vblank between disabling the plane and the pipe. |
|
4255 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
4816 | */ |
4256 | // intel_crtc_wait_for_pending_flips(crtc); |
4817 | intel_set_memory_cxsr(dev_priv, false); |
4257 | // drm_vblank_off(dev, pipe); |
4818 | intel_crtc_disable_planes(crtc); |
- | 4819 | ||
- | 4820 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
4258 | 4821 | encoder->disable(encoder); |
|
4259 | if (dev_priv->fbc.plane == plane) |
4822 | |
4260 | intel_disable_fbc(dev); |
4823 | /* |
- | 4824 | * On gen2 planes are double buffered but the pipe isn't, so we must |
|
4261 | 4825 | * wait for planes to fully turn off before disabling the pipe. |
|
4262 | intel_crtc_dpms_overlay(intel_crtc, false); |
4826 | * We also need to wait on all gmch platforms because of the |
4263 | intel_crtc_update_cursor(crtc, false); |
4827 | * self-refresh mode constraint explained above. |
4264 | intel_disable_planes(crtc); |
4828 | */ |
4265 | intel_disable_primary_plane(dev_priv, plane, pipe); |
4829 | intel_wait_for_vblank(dev, pipe); |
4266 | 4830 | ||
4267 | intel_disable_pipe(dev_priv, pipe); |
4831 | intel_disable_pipe(dev_priv, pipe); |
4268 | 4832 | ||
4269 | i9xx_pfit_disable(intel_crtc); |
4833 | i9xx_pfit_disable(intel_crtc); |
4270 | 4834 | ||
4271 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4835 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4272 | if (encoder->post_disable) |
4836 | if (encoder->post_disable) |
4273 | encoder->post_disable(encoder); |
4837 | encoder->post_disable(encoder); |
4274 | 4838 | ||
- | 4839 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
|
- | 4840 | if (IS_CHERRYVIEW(dev)) |
|
- | 4841 | chv_disable_pll(dev_priv, pipe); |
|
4275 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4842 | else if (IS_VALLEYVIEW(dev)) |
4276 | vlv_disable_pll(dev_priv, pipe); |
4843 | vlv_disable_pll(dev_priv, pipe); |
4277 | else if (!IS_VALLEYVIEW(dev)) |
4844 | else |
- | 4845 | i9xx_disable_pll(dev_priv, pipe); |
|
- | 4846 | } |
|
- | 4847 | ||
- | 4848 | if (!IS_GEN2(dev)) |
|
4278 | i9xx_disable_pll(dev_priv, pipe); |
4849 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
4279 | 4850 | ||
4280 | intel_crtc->active = false; |
4851 | intel_crtc->active = false; |
4281 | intel_update_watermarks(crtc); |
4852 | intel_update_watermarks(crtc); |
- | 4853 | ||
4282 | 4854 | mutex_lock(&dev->struct_mutex); |
|
- | 4855 | intel_update_fbc(dev); |
|
4283 | intel_update_fbc(dev); |
4856 | mutex_unlock(&dev->struct_mutex); |
4284 | } |
4857 | } |
4285 | 4858 | ||
4286 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4859 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4287 | { |
4860 | { |
4288 | } |
4861 | } |
4289 | 4862 | ||
4290 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4863 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4291 | bool enabled) |
4864 | bool enabled) |
4292 | { |
4865 | { |
4293 | struct drm_device *dev = crtc->dev; |
4866 | struct drm_device *dev = crtc->dev; |
4294 | struct drm_i915_master_private *master_priv; |
4867 | struct drm_i915_master_private *master_priv; |
4295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4296 | int pipe = intel_crtc->pipe; |
4869 | int pipe = intel_crtc->pipe; |
4297 | 4870 | ||
4298 | 4871 | ||
4299 | #if 0 |
4872 | #if 0 |
4300 | if (!dev->primary->master) |
4873 | if (!dev->primary->master) |
4301 | return; |
4874 | return; |
4302 | 4875 | ||
4303 | master_priv = dev->primary->master->driver_priv; |
4876 | master_priv = dev->primary->master->driver_priv; |
4304 | if (!master_priv->sarea_priv) |
4877 | if (!master_priv->sarea_priv) |
4305 | return; |
4878 | return; |
4306 | 4879 | ||
4307 | switch (pipe) { |
4880 | switch (pipe) { |
4308 | case 0: |
4881 | case 0: |
4309 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
4882 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
4310 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
4883 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
4311 | break; |
4884 | break; |
4312 | case 1: |
4885 | case 1: |
4313 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
4886 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
4314 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
4887 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
4315 | break; |
4888 | break; |
4316 | default: |
4889 | default: |
4317 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
4890 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
4318 | break; |
4891 | break; |
4319 | } |
4892 | } |
4320 | #endif |
4893 | #endif |
- | 4894 | } |
|
- | 4895 | ||
- | 4896 | /* Master function to enable/disable CRTC and corresponding power wells */ |
|
- | 4897 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) |
|
- | 4898 | { |
|
- | 4899 | struct drm_device *dev = crtc->dev; |
|
- | 4900 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 4902 | enum intel_display_power_domain domain; |
|
- | 4903 | unsigned long domains; |
|
- | 4904 | ||
- | 4905 | if (enable) { |
|
- | 4906 | if (!intel_crtc->active) { |
|
- | 4907 | domains = get_crtc_power_domains(crtc); |
|
- | 4908 | for_each_power_domain(domain, domains) |
|
- | 4909 | intel_display_power_get(dev_priv, domain); |
|
- | 4910 | intel_crtc->enabled_power_domains = domains; |
|
- | 4911 | ||
- | 4912 | dev_priv->display.crtc_enable(crtc); |
|
- | 4913 | } |
|
- | 4914 | } else { |
|
- | 4915 | if (intel_crtc->active) { |
|
- | 4916 | dev_priv->display.crtc_disable(crtc); |
|
- | 4917 | ||
- | 4918 | domains = intel_crtc->enabled_power_domains; |
|
- | 4919 | for_each_power_domain(domain, domains) |
|
- | 4920 | intel_display_power_put(dev_priv, domain); |
|
- | 4921 | intel_crtc->enabled_power_domains = 0; |
|
- | 4922 | } |
|
4321 | 4923 | } |
|
4322 | } |
4924 | } |
4323 | 4925 | ||
4324 | /** |
4926 | /** |
4325 | * Sets the power management mode of the pipe and plane. |
4927 | * Sets the power management mode of the pipe and plane. |
4326 | */ |
4928 | */ |
4327 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
4929 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
4328 | { |
4930 | { |
4329 | struct drm_device *dev = crtc->dev; |
4931 | struct drm_device *dev = crtc->dev; |
4330 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4331 | struct intel_encoder *intel_encoder; |
4932 | struct intel_encoder *intel_encoder; |
4332 | bool enable = false; |
4933 | bool enable = false; |
4333 | 4934 | ||
4334 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4935 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4335 | enable |= intel_encoder->connectors_active; |
4936 | enable |= intel_encoder->connectors_active; |
4336 | - | ||
4337 | if (enable) |
4937 | |
4338 | dev_priv->display.crtc_enable(crtc); |
- | |
4339 | else |
- | |
4340 | dev_priv->display.crtc_disable(crtc); |
4938 | intel_crtc_control(crtc, enable); |
4341 | 4939 | ||
4342 | intel_crtc_update_sarea(crtc, enable); |
4940 | intel_crtc_update_sarea(crtc, enable); |
4343 | } |
4941 | } |
4344 | 4942 | ||
4345 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4943 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4346 | { |
4944 | { |
4347 | struct drm_device *dev = crtc->dev; |
4945 | struct drm_device *dev = crtc->dev; |
4348 | struct drm_connector *connector; |
4946 | struct drm_connector *connector; |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4947 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 4948 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
|
4350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4949 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
4351 | 4950 | ||
4352 | /* crtc should still be enabled when we disable it. */ |
4951 | /* crtc should still be enabled when we disable it. */ |
4353 | WARN_ON(!crtc->enabled); |
4952 | WARN_ON(!crtc->enabled); |
4354 | 4953 | ||
4355 | dev_priv->display.crtc_disable(crtc); |
4954 | dev_priv->display.crtc_disable(crtc); |
4356 | intel_crtc->eld_vld = false; |
- | |
4357 | intel_crtc_update_sarea(crtc, false); |
4955 | intel_crtc_update_sarea(crtc, false); |
4358 | dev_priv->display.off(crtc); |
4956 | dev_priv->display.off(crtc); |
4359 | - | ||
4360 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
- | |
4361 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
- | |
4362 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
- | |
4363 | 4957 | ||
4364 | if (crtc->fb) { |
4958 | if (crtc->primary->fb) { |
4365 | mutex_lock(&dev->struct_mutex); |
4959 | mutex_lock(&dev->struct_mutex); |
- | 4960 | intel_unpin_fb_obj(old_obj); |
|
- | 4961 | i915_gem_track_fb(old_obj, NULL, |
|
4366 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
4962 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
4367 | mutex_unlock(&dev->struct_mutex); |
4963 | mutex_unlock(&dev->struct_mutex); |
4368 | crtc->fb = NULL; |
4964 | crtc->primary->fb = NULL; |
4369 | } |
4965 | } |
4370 | 4966 | ||
4371 | /* Update computed state. */ |
4967 | /* Update computed state. */ |
4372 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
4968 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
4373 | if (!connector->encoder || !connector->encoder->crtc) |
4969 | if (!connector->encoder || !connector->encoder->crtc) |
4374 | continue; |
4970 | continue; |
4375 | 4971 | ||
4376 | if (connector->encoder->crtc != crtc) |
4972 | if (connector->encoder->crtc != crtc) |
4377 | continue; |
4973 | continue; |
4378 | 4974 | ||
4379 | connector->dpms = DRM_MODE_DPMS_OFF; |
4975 | connector->dpms = DRM_MODE_DPMS_OFF; |
4380 | to_intel_encoder(connector->encoder)->connectors_active = false; |
4976 | to_intel_encoder(connector->encoder)->connectors_active = false; |
4381 | } |
4977 | } |
4382 | } |
4978 | } |
4383 | 4979 | ||
4384 | void intel_encoder_destroy(struct drm_encoder *encoder) |
4980 | void intel_encoder_destroy(struct drm_encoder *encoder) |
4385 | { |
4981 | { |
4386 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
4982 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
4387 | 4983 | ||
4388 | drm_encoder_cleanup(encoder); |
4984 | drm_encoder_cleanup(encoder); |
4389 | kfree(intel_encoder); |
4985 | kfree(intel_encoder); |
4390 | } |
4986 | } |
4391 | 4987 | ||
4392 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
4988 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
4393 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4989 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4394 | * state of the entire output pipe. */ |
4990 | * state of the entire output pipe. */ |
4395 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
4991 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
4396 | { |
4992 | { |
4397 | if (mode == DRM_MODE_DPMS_ON) { |
4993 | if (mode == DRM_MODE_DPMS_ON) { |
4398 | encoder->connectors_active = true; |
4994 | encoder->connectors_active = true; |
4399 | 4995 | ||
4400 | intel_crtc_update_dpms(encoder->base.crtc); |
4996 | intel_crtc_update_dpms(encoder->base.crtc); |
4401 | } else { |
4997 | } else { |
4402 | encoder->connectors_active = false; |
4998 | encoder->connectors_active = false; |
4403 | 4999 | ||
4404 | intel_crtc_update_dpms(encoder->base.crtc); |
5000 | intel_crtc_update_dpms(encoder->base.crtc); |
4405 | } |
5001 | } |
4406 | } |
5002 | } |
4407 | 5003 | ||
4408 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5004 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4409 | * internal consistency). */ |
5005 | * internal consistency). */ |
4410 | static void intel_connector_check_state(struct intel_connector *connector) |
5006 | static void intel_connector_check_state(struct intel_connector *connector) |
4411 | { |
5007 | { |
4412 | if (connector->get_hw_state(connector)) { |
5008 | if (connector->get_hw_state(connector)) { |
4413 | struct intel_encoder *encoder = connector->encoder; |
5009 | struct intel_encoder *encoder = connector->encoder; |
4414 | struct drm_crtc *crtc; |
5010 | struct drm_crtc *crtc; |
4415 | bool encoder_enabled; |
5011 | bool encoder_enabled; |
4416 | enum pipe pipe; |
5012 | enum pipe pipe; |
4417 | 5013 | ||
4418 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5014 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4419 | connector->base.base.id, |
5015 | connector->base.base.id, |
4420 | drm_get_connector_name(&connector->base)); |
5016 | connector->base.name); |
- | 5017 | ||
- | 5018 | /* there is no real hw state for MST connectors */ |
|
- | 5019 | if (connector->mst_port) |
|
- | 5020 | return; |
|
4421 | 5021 | ||
4422 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5022 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
4423 | "wrong connector dpms state\n"); |
5023 | "wrong connector dpms state\n"); |
4424 | WARN(connector->base.encoder != &encoder->base, |
5024 | WARN(connector->base.encoder != &encoder->base, |
4425 | "active connector not linked to encoder\n"); |
5025 | "active connector not linked to encoder\n"); |
- | 5026 | ||
- | 5027 | if (encoder) { |
|
4426 | WARN(!encoder->connectors_active, |
5028 | WARN(!encoder->connectors_active, |
4427 | "encoder->connectors_active not set\n"); |
5029 | "encoder->connectors_active not set\n"); |
4428 | 5030 | ||
4429 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
5031 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
4430 | WARN(!encoder_enabled, "encoder not enabled\n"); |
5032 | WARN(!encoder_enabled, "encoder not enabled\n"); |
4431 | if (WARN_ON(!encoder->base.crtc)) |
5033 | if (WARN_ON(!encoder->base.crtc)) |
4432 | return; |
5034 | return; |
4433 | 5035 | ||
4434 | crtc = encoder->base.crtc; |
5036 | crtc = encoder->base.crtc; |
4435 | 5037 | ||
4436 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5038 | WARN(!crtc->enabled, "crtc not enabled\n"); |
4437 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5039 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
4438 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
5040 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
4439 | "encoder active on the wrong pipe\n"); |
5041 | "encoder active on the wrong pipe\n"); |
4440 | } |
5042 | } |
4441 | } |
5043 | } |
- | 5044 | } |
|
4442 | 5045 | ||
4443 | /* Even simpler default implementation, if there's really no special case to |
5046 | /* Even simpler default implementation, if there's really no special case to |
4444 | * consider. */ |
5047 | * consider. */ |
4445 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
5048 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
4446 | { |
5049 | { |
4447 | /* All the simple cases only support two dpms states. */ |
5050 | /* All the simple cases only support two dpms states. */ |
4448 | if (mode != DRM_MODE_DPMS_ON) |
5051 | if (mode != DRM_MODE_DPMS_ON) |
4449 | mode = DRM_MODE_DPMS_OFF; |
5052 | mode = DRM_MODE_DPMS_OFF; |
4450 | 5053 | ||
4451 | if (mode == connector->dpms) |
5054 | if (mode == connector->dpms) |
4452 | return; |
5055 | return; |
4453 | 5056 | ||
4454 | connector->dpms = mode; |
5057 | connector->dpms = mode; |
4455 | 5058 | ||
4456 | /* Only need to change hw state when actually enabled */ |
5059 | /* Only need to change hw state when actually enabled */ |
4457 | if (connector->encoder) |
5060 | if (connector->encoder) |
4458 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
5061 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
4459 | 5062 | ||
4460 | intel_modeset_check_state(connector->dev); |
5063 | intel_modeset_check_state(connector->dev); |
4461 | } |
5064 | } |
4462 | 5065 | ||
4463 | /* Simple connector->get_hw_state implementation for encoders that support only |
5066 | /* Simple connector->get_hw_state implementation for encoders that support only |
4464 | * one connector and no cloning and hence the encoder state determines the state |
5067 | * one connector and no cloning and hence the encoder state determines the state |
4465 | * of the connector. */ |
5068 | * of the connector. */ |
4466 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
5069 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
4467 | { |
5070 | { |
4468 | enum pipe pipe = 0; |
5071 | enum pipe pipe = 0; |
4469 | struct intel_encoder *encoder = connector->encoder; |
5072 | struct intel_encoder *encoder = connector->encoder; |
4470 | 5073 | ||
4471 | return encoder->get_hw_state(encoder, &pipe); |
5074 | return encoder->get_hw_state(encoder, &pipe); |
4472 | } |
5075 | } |
4473 | 5076 | ||
4474 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5077 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4475 | struct intel_crtc_config *pipe_config) |
5078 | struct intel_crtc_config *pipe_config) |
4476 | { |
5079 | { |
4477 | struct drm_i915_private *dev_priv = dev->dev_private; |
5080 | struct drm_i915_private *dev_priv = dev->dev_private; |
4478 | struct intel_crtc *pipe_B_crtc = |
5081 | struct intel_crtc *pipe_B_crtc = |
4479 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
5082 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
4480 | 5083 | ||
4481 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5084 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
4482 | pipe_name(pipe), pipe_config->fdi_lanes); |
5085 | pipe_name(pipe), pipe_config->fdi_lanes); |
4483 | if (pipe_config->fdi_lanes > 4) { |
5086 | if (pipe_config->fdi_lanes > 4) { |
4484 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
5087 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4485 | pipe_name(pipe), pipe_config->fdi_lanes); |
5088 | pipe_name(pipe), pipe_config->fdi_lanes); |
4486 | return false; |
5089 | return false; |
4487 | } |
5090 | } |
4488 | 5091 | ||
4489 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
5092 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
4490 | if (pipe_config->fdi_lanes > 2) { |
5093 | if (pipe_config->fdi_lanes > 2) { |
4491 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
5094 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4492 | pipe_config->fdi_lanes); |
5095 | pipe_config->fdi_lanes); |
4493 | return false; |
5096 | return false; |
4494 | } else { |
5097 | } else { |
4495 | return true; |
5098 | return true; |
4496 | } |
5099 | } |
4497 | } |
5100 | } |
4498 | 5101 | ||
4499 | if (INTEL_INFO(dev)->num_pipes == 2) |
5102 | if (INTEL_INFO(dev)->num_pipes == 2) |
4500 | return true; |
5103 | return true; |
4501 | 5104 | ||
4502 | /* Ivybridge 3 pipe is really complicated */ |
5105 | /* Ivybridge 3 pipe is really complicated */ |
4503 | switch (pipe) { |
5106 | switch (pipe) { |
4504 | case PIPE_A: |
5107 | case PIPE_A: |
4505 | return true; |
5108 | return true; |
4506 | case PIPE_B: |
5109 | case PIPE_B: |
4507 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
5110 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
4508 | pipe_config->fdi_lanes > 2) { |
5111 | pipe_config->fdi_lanes > 2) { |
4509 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5112 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4510 | pipe_name(pipe), pipe_config->fdi_lanes); |
5113 | pipe_name(pipe), pipe_config->fdi_lanes); |
4511 | return false; |
5114 | return false; |
4512 | } |
5115 | } |
4513 | return true; |
5116 | return true; |
4514 | case PIPE_C: |
5117 | case PIPE_C: |
4515 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
5118 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4516 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5119 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4517 | if (pipe_config->fdi_lanes > 2) { |
5120 | if (pipe_config->fdi_lanes > 2) { |
4518 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5121 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4519 | pipe_name(pipe), pipe_config->fdi_lanes); |
5122 | pipe_name(pipe), pipe_config->fdi_lanes); |
4520 | return false; |
5123 | return false; |
4521 | } |
5124 | } |
4522 | } else { |
5125 | } else { |
4523 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
5126 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
4524 | return false; |
5127 | return false; |
4525 | } |
5128 | } |
4526 | return true; |
5129 | return true; |
4527 | default: |
5130 | default: |
4528 | BUG(); |
5131 | BUG(); |
4529 | } |
5132 | } |
4530 | } |
5133 | } |
4531 | 5134 | ||
4532 | #define RETRY 1 |
5135 | #define RETRY 1 |
4533 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
5136 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4534 | struct intel_crtc_config *pipe_config) |
5137 | struct intel_crtc_config *pipe_config) |
4535 | { |
5138 | { |
4536 | struct drm_device *dev = intel_crtc->base.dev; |
5139 | struct drm_device *dev = intel_crtc->base.dev; |
4537 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5140 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4538 | int lane, link_bw, fdi_dotclock; |
5141 | int lane, link_bw, fdi_dotclock; |
4539 | bool setup_ok, needs_recompute = false; |
5142 | bool setup_ok, needs_recompute = false; |
4540 | 5143 | ||
4541 | retry: |
5144 | retry: |
4542 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5145 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4543 | * each output octet as 10 bits. The actual frequency |
5146 | * each output octet as 10 bits. The actual frequency |
4544 | * is stored as a divider into a 100MHz clock, and the |
5147 | * is stored as a divider into a 100MHz clock, and the |
4545 | * mode pixel clock is stored in units of 1KHz. |
5148 | * mode pixel clock is stored in units of 1KHz. |
4546 | * Hence the bw of each lane in terms of the mode signal |
5149 | * Hence the bw of each lane in terms of the mode signal |
4547 | * is: |
5150 | * is: |
4548 | */ |
5151 | */ |
4549 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
5152 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4550 | 5153 | ||
4551 | fdi_dotclock = adjusted_mode->crtc_clock; |
5154 | fdi_dotclock = adjusted_mode->crtc_clock; |
4552 | 5155 | ||
4553 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
5156 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4554 | pipe_config->pipe_bpp); |
5157 | pipe_config->pipe_bpp); |
4555 | 5158 | ||
4556 | pipe_config->fdi_lanes = lane; |
5159 | pipe_config->fdi_lanes = lane; |
4557 | 5160 | ||
4558 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
5161 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4559 | link_bw, &pipe_config->fdi_m_n); |
5162 | link_bw, &pipe_config->fdi_m_n); |
4560 | 5163 | ||
4561 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5164 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4562 | intel_crtc->pipe, pipe_config); |
5165 | intel_crtc->pipe, pipe_config); |
4563 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
5166 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4564 | pipe_config->pipe_bpp -= 2*3; |
5167 | pipe_config->pipe_bpp -= 2*3; |
4565 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
5168 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
4566 | pipe_config->pipe_bpp); |
5169 | pipe_config->pipe_bpp); |
4567 | needs_recompute = true; |
5170 | needs_recompute = true; |
4568 | pipe_config->bw_constrained = true; |
5171 | pipe_config->bw_constrained = true; |
4569 | 5172 | ||
4570 | goto retry; |
5173 | goto retry; |
4571 | } |
5174 | } |
4572 | 5175 | ||
4573 | if (needs_recompute) |
5176 | if (needs_recompute) |
4574 | return RETRY; |
5177 | return RETRY; |
4575 | 5178 | ||
4576 | return setup_ok ? 0 : -EINVAL; |
5179 | return setup_ok ? 0 : -EINVAL; |
4577 | } |
5180 | } |
4578 | 5181 | ||
4579 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5182 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4580 | struct intel_crtc_config *pipe_config) |
5183 | struct intel_crtc_config *pipe_config) |
4581 | { |
5184 | { |
4582 | pipe_config->ips_enabled = i915_enable_ips && |
5185 | pipe_config->ips_enabled = i915.enable_ips && |
4583 | hsw_crtc_supports_ips(crtc) && |
5186 | hsw_crtc_supports_ips(crtc) && |
4584 | pipe_config->pipe_bpp <= 24; |
5187 | pipe_config->pipe_bpp <= 24; |
4585 | } |
5188 | } |
4586 | 5189 | ||
4587 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5190 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4588 | struct intel_crtc_config *pipe_config) |
5191 | struct intel_crtc_config *pipe_config) |
4589 | { |
5192 | { |
4590 | struct drm_device *dev = crtc->base.dev; |
5193 | struct drm_device *dev = crtc->base.dev; |
4591 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5194 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4592 | 5195 | ||
4593 | /* FIXME should check pixel clock limits on all platforms */ |
5196 | /* FIXME should check pixel clock limits on all platforms */ |
4594 | if (INTEL_INFO(dev)->gen < 4) { |
5197 | if (INTEL_INFO(dev)->gen < 4) { |
4595 | struct drm_i915_private *dev_priv = dev->dev_private; |
5198 | struct drm_i915_private *dev_priv = dev->dev_private; |
4596 | int clock_limit = |
5199 | int clock_limit = |
4597 | dev_priv->display.get_display_clock_speed(dev); |
5200 | dev_priv->display.get_display_clock_speed(dev); |
4598 | 5201 | ||
4599 | /* |
5202 | /* |
4600 | * Enable pixel doubling when the dot clock |
5203 | * Enable pixel doubling when the dot clock |
4601 | * is > 90% of the (display) core speed. |
5204 | * is > 90% of the (display) core speed. |
4602 | * |
5205 | * |
4603 | * GDG double wide on either pipe, |
5206 | * GDG double wide on either pipe, |
4604 | * otherwise pipe A only. |
5207 | * otherwise pipe A only. |
4605 | */ |
5208 | */ |
4606 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
5209 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
4607 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
5210 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
4608 | clock_limit *= 2; |
5211 | clock_limit *= 2; |
4609 | pipe_config->double_wide = true; |
5212 | pipe_config->double_wide = true; |
4610 | } |
5213 | } |
4611 | 5214 | ||
4612 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
5215 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
4613 | return -EINVAL; |
5216 | return -EINVAL; |
4614 | } |
5217 | } |
4615 | 5218 | ||
4616 | /* |
5219 | /* |
4617 | * Pipe horizontal size must be even in: |
5220 | * Pipe horizontal size must be even in: |
4618 | * - DVO ganged mode |
5221 | * - DVO ganged mode |
4619 | * - LVDS dual channel mode |
5222 | * - LVDS dual channel mode |
4620 | * - Double wide pipe |
5223 | * - Double wide pipe |
4621 | */ |
5224 | */ |
4622 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5225 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4623 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5226 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
4624 | pipe_config->pipe_src_w &= ~1; |
5227 | pipe_config->pipe_src_w &= ~1; |
4625 | 5228 | ||
4626 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5229 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4627 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
5230 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4628 | */ |
5231 | */ |
4629 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
5232 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4630 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
5233 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4631 | return -EINVAL; |
5234 | return -EINVAL; |
4632 | 5235 | ||
4633 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5236 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4634 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
5237 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4635 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5238 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4636 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5239 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4637 | * for lvds. */ |
5240 | * for lvds. */ |
4638 | pipe_config->pipe_bpp = 8*3; |
5241 | pipe_config->pipe_bpp = 8*3; |
4639 | } |
5242 | } |
4640 | 5243 | ||
4641 | if (HAS_IPS(dev)) |
5244 | if (HAS_IPS(dev)) |
4642 | hsw_compute_ips_config(crtc, pipe_config); |
5245 | hsw_compute_ips_config(crtc, pipe_config); |
- | 5246 | ||
4643 | 5247 | /* |
|
4644 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
5248 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the |
- | 5249 | * old clock survives for now. |
|
4645 | * clock survives for now. */ |
5250 | */ |
4646 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5251 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) |
4647 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
5252 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4648 | 5253 | ||
4649 | if (pipe_config->has_pch_encoder) |
5254 | if (pipe_config->has_pch_encoder) |
4650 | return ironlake_fdi_compute_config(crtc, pipe_config); |
5255 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4651 | 5256 | ||
4652 | return 0; |
5257 | return 0; |
4653 | } |
5258 | } |
4654 | 5259 | ||
4655 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5260 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4656 | { |
5261 | { |
- | 5262 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5263 | int vco = valleyview_get_vco(dev_priv); |
|
- | 5264 | u32 val; |
|
- | 5265 | int divider; |
|
- | 5266 | ||
- | 5267 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 5268 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
|
- | 5269 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 5270 | ||
- | 5271 | divider = val & DISPLAY_FREQUENCY_VALUES; |
|
- | 5272 | ||
- | 5273 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
|
- | 5274 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
|
- | 5275 | "cdclk change in progress\n"); |
|
- | 5276 | ||
4657 | return 400000; /* FIXME */ |
5277 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
4658 | } |
5278 | } |
4659 | 5279 | ||
4660 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5280 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4661 | { |
5281 | { |
4662 | return 400000; |
5282 | return 400000; |
4663 | } |
5283 | } |
4664 | 5284 | ||
4665 | static int i915_get_display_clock_speed(struct drm_device *dev) |
5285 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4666 | { |
5286 | { |
4667 | return 333000; |
5287 | return 333000; |
4668 | } |
5288 | } |
4669 | 5289 | ||
4670 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5290 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4671 | { |
5291 | { |
4672 | return 200000; |
5292 | return 200000; |
4673 | } |
5293 | } |
4674 | 5294 | ||
4675 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5295 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4676 | { |
5296 | { |
4677 | u16 gcfgc = 0; |
5297 | u16 gcfgc = 0; |
4678 | 5298 | ||
4679 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5299 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4680 | 5300 | ||
4681 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
5301 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4682 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
5302 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4683 | return 267000; |
5303 | return 267000; |
4684 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
5304 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4685 | return 333000; |
5305 | return 333000; |
4686 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
5306 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4687 | return 444000; |
5307 | return 444000; |
4688 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
5308 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4689 | return 200000; |
5309 | return 200000; |
4690 | default: |
5310 | default: |
4691 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
5311 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
4692 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
5312 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4693 | return 133000; |
5313 | return 133000; |
4694 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
5314 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4695 | return 167000; |
5315 | return 167000; |
4696 | } |
5316 | } |
4697 | } |
5317 | } |
4698 | 5318 | ||
4699 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5319 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4700 | { |
5320 | { |
4701 | u16 gcfgc = 0; |
5321 | u16 gcfgc = 0; |
4702 | 5322 | ||
4703 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5323 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4704 | 5324 | ||
4705 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
5325 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4706 | return 133000; |
5326 | return 133000; |
4707 | else { |
5327 | else { |
4708 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
5328 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4709 | case GC_DISPLAY_CLOCK_333_MHZ: |
5329 | case GC_DISPLAY_CLOCK_333_MHZ: |
4710 | return 333000; |
5330 | return 333000; |
4711 | default: |
5331 | default: |
4712 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
5332 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4713 | return 190000; |
5333 | return 190000; |
4714 | } |
5334 | } |
4715 | } |
5335 | } |
4716 | } |
5336 | } |
4717 | 5337 | ||
4718 | static int i865_get_display_clock_speed(struct drm_device *dev) |
5338 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4719 | { |
5339 | { |
4720 | return 266000; |
5340 | return 266000; |
4721 | } |
5341 | } |
4722 | 5342 | ||
4723 | static int i855_get_display_clock_speed(struct drm_device *dev) |
5343 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4724 | { |
5344 | { |
4725 | u16 hpllcc = 0; |
5345 | u16 hpllcc = 0; |
4726 | /* Assume that the hardware is in the high speed state. This |
5346 | /* Assume that the hardware is in the high speed state. This |
4727 | * should be the default. |
5347 | * should be the default. |
4728 | */ |
5348 | */ |
4729 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
5349 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4730 | case GC_CLOCK_133_200: |
5350 | case GC_CLOCK_133_200: |
4731 | case GC_CLOCK_100_200: |
5351 | case GC_CLOCK_100_200: |
4732 | return 200000; |
5352 | return 200000; |
4733 | case GC_CLOCK_166_250: |
5353 | case GC_CLOCK_166_250: |
4734 | return 250000; |
5354 | return 250000; |
4735 | case GC_CLOCK_100_133: |
5355 | case GC_CLOCK_100_133: |
4736 | return 133000; |
5356 | return 133000; |
4737 | } |
5357 | } |
4738 | 5358 | ||
4739 | /* Shouldn't happen */ |
5359 | /* Shouldn't happen */ |
4740 | return 0; |
5360 | return 0; |
4741 | } |
5361 | } |
4742 | 5362 | ||
4743 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5363 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4744 | { |
5364 | { |
4745 | return 133000; |
5365 | return 133000; |
4746 | } |
5366 | } |
4747 | 5367 | ||
4748 | static void |
5368 | static void |
4749 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
5369 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4750 | { |
5370 | { |
4751 | while (*num > DATA_LINK_M_N_MASK || |
5371 | while (*num > DATA_LINK_M_N_MASK || |
4752 | *den > DATA_LINK_M_N_MASK) { |
5372 | *den > DATA_LINK_M_N_MASK) { |
4753 | *num >>= 1; |
5373 | *num >>= 1; |
4754 | *den >>= 1; |
5374 | *den >>= 1; |
4755 | } |
5375 | } |
4756 | } |
5376 | } |
4757 | 5377 | ||
4758 | static void compute_m_n(unsigned int m, unsigned int n, |
5378 | static void compute_m_n(unsigned int m, unsigned int n, |
4759 | uint32_t *ret_m, uint32_t *ret_n) |
5379 | uint32_t *ret_m, uint32_t *ret_n) |
4760 | { |
5380 | { |
4761 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
5381 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
4762 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
5382 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
4763 | intel_reduce_m_n_ratio(ret_m, ret_n); |
5383 | intel_reduce_m_n_ratio(ret_m, ret_n); |
4764 | } |
5384 | } |
4765 | 5385 | ||
4766 | void |
5386 | void |
4767 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
5387 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
4768 | int pixel_clock, int link_clock, |
5388 | int pixel_clock, int link_clock, |
4769 | struct intel_link_m_n *m_n) |
5389 | struct intel_link_m_n *m_n) |
4770 | { |
5390 | { |
4771 | m_n->tu = 64; |
5391 | m_n->tu = 64; |
4772 | 5392 | ||
4773 | compute_m_n(bits_per_pixel * pixel_clock, |
5393 | compute_m_n(bits_per_pixel * pixel_clock, |
4774 | link_clock * nlanes * 8, |
5394 | link_clock * nlanes * 8, |
4775 | &m_n->gmch_m, &m_n->gmch_n); |
5395 | &m_n->gmch_m, &m_n->gmch_n); |
4776 | 5396 | ||
4777 | compute_m_n(pixel_clock, link_clock, |
5397 | compute_m_n(pixel_clock, link_clock, |
4778 | &m_n->link_m, &m_n->link_n); |
5398 | &m_n->link_m, &m_n->link_n); |
4779 | } |
5399 | } |
4780 | 5400 | ||
4781 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5401 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4782 | { |
5402 | { |
4783 | if (i915_panel_use_ssc >= 0) |
5403 | if (i915.panel_use_ssc >= 0) |
4784 | return i915_panel_use_ssc != 0; |
5404 | return i915.panel_use_ssc != 0; |
4785 | return dev_priv->vbt.lvds_use_ssc |
5405 | return dev_priv->vbt.lvds_use_ssc |
4786 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
5406 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4787 | } |
5407 | } |
4788 | 5408 | ||
4789 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5409 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4790 | { |
5410 | { |
4791 | struct drm_device *dev = crtc->dev; |
5411 | struct drm_device *dev = crtc->dev; |
4792 | struct drm_i915_private *dev_priv = dev->dev_private; |
5412 | struct drm_i915_private *dev_priv = dev->dev_private; |
4793 | int refclk; |
5413 | int refclk; |
4794 | 5414 | ||
4795 | if (IS_VALLEYVIEW(dev)) { |
5415 | if (IS_VALLEYVIEW(dev)) { |
4796 | refclk = 100000; |
5416 | refclk = 100000; |
4797 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
5417 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4798 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5418 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4799 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5419 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4800 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
5420 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
4801 | } else if (!IS_GEN2(dev)) { |
5421 | } else if (!IS_GEN2(dev)) { |
4802 | refclk = 96000; |
5422 | refclk = 96000; |
4803 | } else { |
5423 | } else { |
4804 | refclk = 48000; |
5424 | refclk = 48000; |
4805 | } |
5425 | } |
4806 | 5426 | ||
4807 | return refclk; |
5427 | return refclk; |
4808 | } |
5428 | } |
4809 | 5429 | ||
4810 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
5430 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4811 | { |
5431 | { |
4812 | return (1 << dpll->n) << 16 | dpll->m2; |
5432 | return (1 << dpll->n) << 16 | dpll->m2; |
4813 | } |
5433 | } |
4814 | 5434 | ||
4815 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5435 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4816 | { |
5436 | { |
4817 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
5437 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
4818 | } |
5438 | } |
4819 | 5439 | ||
4820 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
5440 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4821 | intel_clock_t *reduced_clock) |
5441 | intel_clock_t *reduced_clock) |
4822 | { |
5442 | { |
4823 | struct drm_device *dev = crtc->base.dev; |
5443 | struct drm_device *dev = crtc->base.dev; |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4825 | int pipe = crtc->pipe; |
- | |
4826 | u32 fp, fp2 = 0; |
5444 | u32 fp, fp2 = 0; |
4827 | 5445 | ||
4828 | if (IS_PINEVIEW(dev)) { |
5446 | if (IS_PINEVIEW(dev)) { |
4829 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
5447 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
4830 | if (reduced_clock) |
5448 | if (reduced_clock) |
4831 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
5449 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
4832 | } else { |
5450 | } else { |
4833 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
5451 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4834 | if (reduced_clock) |
5452 | if (reduced_clock) |
4835 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
5453 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4836 | } |
5454 | } |
4837 | - | ||
4838 | I915_WRITE(FP0(pipe), fp); |
5455 | |
4839 | crtc->config.dpll_hw_state.fp0 = fp; |
5456 | crtc->config.dpll_hw_state.fp0 = fp; |
4840 | 5457 | ||
4841 | crtc->lowfreq_avail = false; |
5458 | crtc->lowfreq_avail = false; |
4842 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5459 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4843 | reduced_clock && i915_powersave) { |
5460 | reduced_clock && i915.powersave) { |
4844 | I915_WRITE(FP1(pipe), fp2); |
- | |
4845 | crtc->config.dpll_hw_state.fp1 = fp2; |
5461 | crtc->config.dpll_hw_state.fp1 = fp2; |
4846 | crtc->lowfreq_avail = true; |
5462 | crtc->lowfreq_avail = true; |
4847 | } else { |
5463 | } else { |
4848 | I915_WRITE(FP1(pipe), fp); |
- | |
4849 | crtc->config.dpll_hw_state.fp1 = fp; |
5464 | crtc->config.dpll_hw_state.fp1 = fp; |
4850 | } |
5465 | } |
4851 | } |
5466 | } |
4852 | 5467 | ||
4853 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5468 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4854 | pipe) |
5469 | pipe) |
4855 | { |
5470 | { |
4856 | u32 reg_val; |
5471 | u32 reg_val; |
4857 | 5472 | ||
4858 | /* |
5473 | /* |
4859 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
5474 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4860 | * and set it to a reasonable value instead. |
5475 | * and set it to a reasonable value instead. |
4861 | */ |
5476 | */ |
4862 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
5477 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
4863 | reg_val &= 0xffffff00; |
5478 | reg_val &= 0xffffff00; |
4864 | reg_val |= 0x00000030; |
5479 | reg_val |= 0x00000030; |
4865 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
5480 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
4866 | 5481 | ||
4867 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
5482 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
4868 | reg_val &= 0x8cffffff; |
5483 | reg_val &= 0x8cffffff; |
4869 | reg_val = 0x8c000000; |
5484 | reg_val = 0x8c000000; |
4870 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
5485 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
4871 | 5486 | ||
4872 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
5487 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
4873 | reg_val &= 0xffffff00; |
5488 | reg_val &= 0xffffff00; |
4874 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
5489 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
4875 | 5490 | ||
4876 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
5491 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
4877 | reg_val &= 0x00ffffff; |
5492 | reg_val &= 0x00ffffff; |
4878 | reg_val |= 0xb0000000; |
5493 | reg_val |= 0xb0000000; |
4879 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
5494 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
4880 | } |
5495 | } |
4881 | 5496 | ||
4882 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5497 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4883 | struct intel_link_m_n *m_n) |
5498 | struct intel_link_m_n *m_n) |
4884 | { |
5499 | { |
4885 | struct drm_device *dev = crtc->base.dev; |
5500 | struct drm_device *dev = crtc->base.dev; |
4886 | struct drm_i915_private *dev_priv = dev->dev_private; |
5501 | struct drm_i915_private *dev_priv = dev->dev_private; |
4887 | int pipe = crtc->pipe; |
5502 | int pipe = crtc->pipe; |
4888 | 5503 | ||
4889 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5504 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4890 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
5505 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
4891 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
5506 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
4892 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
5507 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
4893 | } |
5508 | } |
4894 | 5509 | ||
4895 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
5510 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
4896 | struct intel_link_m_n *m_n) |
5511 | struct intel_link_m_n *m_n) |
4897 | { |
5512 | { |
4898 | struct drm_device *dev = crtc->base.dev; |
5513 | struct drm_device *dev = crtc->base.dev; |
4899 | struct drm_i915_private *dev_priv = dev->dev_private; |
5514 | struct drm_i915_private *dev_priv = dev->dev_private; |
4900 | int pipe = crtc->pipe; |
5515 | int pipe = crtc->pipe; |
4901 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
5516 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
4902 | 5517 | ||
4903 | if (INTEL_INFO(dev)->gen >= 5) { |
5518 | if (INTEL_INFO(dev)->gen >= 5) { |
4904 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5519 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4905 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
5520 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
4906 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
5521 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
4907 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
5522 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
4908 | } else { |
5523 | } else { |
4909 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5524 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4910 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
5525 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
4911 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
5526 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
4912 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
5527 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
4913 | } |
5528 | } |
4914 | } |
5529 | } |
4915 | 5530 | ||
4916 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5531 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4917 | { |
5532 | { |
4918 | if (crtc->config.has_pch_encoder) |
5533 | if (crtc->config.has_pch_encoder) |
4919 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
5534 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4920 | else |
5535 | else |
4921 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
5536 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4922 | } |
5537 | } |
4923 | 5538 | ||
4924 | static void vlv_update_pll(struct intel_crtc *crtc) |
5539 | static void vlv_update_pll(struct intel_crtc *crtc) |
4925 | { |
5540 | { |
- | 5541 | u32 dpll, dpll_md; |
|
- | 5542 | ||
- | 5543 | /* |
|
- | 5544 | * Enable DPIO clock input. We should never disable the reference |
|
- | 5545 | * clock for pipe B, since VGA hotplug / manual detection depends |
|
- | 5546 | * on it. |
|
- | 5547 | */ |
|
- | 5548 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
|
- | 5549 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
|
- | 5550 | /* We should never disable this, set it here for state tracking */ |
|
- | 5551 | if (crtc->pipe == PIPE_B) |
|
- | 5552 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 5553 | dpll |= DPLL_VCO_ENABLE; |
|
- | 5554 | crtc->config.dpll_hw_state.dpll = dpll; |
|
- | 5555 | ||
- | 5556 | dpll_md = (crtc->config.pixel_multiplier - 1) |
|
- | 5557 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
|
- | 5558 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
|
- | 5559 | } |
|
- | 5560 | ||
- | 5561 | static void vlv_prepare_pll(struct intel_crtc *crtc) |
|
- | 5562 | { |
|
4926 | struct drm_device *dev = crtc->base.dev; |
5563 | struct drm_device *dev = crtc->base.dev; |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; |
5564 | struct drm_i915_private *dev_priv = dev->dev_private; |
4928 | int pipe = crtc->pipe; |
5565 | int pipe = crtc->pipe; |
4929 | u32 dpll, mdiv; |
5566 | u32 mdiv; |
4930 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
5567 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4931 | u32 coreclk, reg_val, dpll_md; |
5568 | u32 coreclk, reg_val; |
4932 | 5569 | ||
4933 | mutex_lock(&dev_priv->dpio_lock); |
5570 | mutex_lock(&dev_priv->dpio_lock); |
4934 | 5571 | ||
4935 | bestn = crtc->config.dpll.n; |
5572 | bestn = crtc->config.dpll.n; |
4936 | bestm1 = crtc->config.dpll.m1; |
5573 | bestm1 = crtc->config.dpll.m1; |
4937 | bestm2 = crtc->config.dpll.m2; |
5574 | bestm2 = crtc->config.dpll.m2; |
4938 | bestp1 = crtc->config.dpll.p1; |
5575 | bestp1 = crtc->config.dpll.p1; |
4939 | bestp2 = crtc->config.dpll.p2; |
5576 | bestp2 = crtc->config.dpll.p2; |
4940 | 5577 | ||
4941 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5578 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4942 | 5579 | ||
4943 | /* PLL B needs special handling */ |
5580 | /* PLL B needs special handling */ |
4944 | if (pipe) |
5581 | if (pipe == PIPE_B) |
4945 | vlv_pllb_recal_opamp(dev_priv, pipe); |
5582 | vlv_pllb_recal_opamp(dev_priv, pipe); |
4946 | 5583 | ||
4947 | /* Set up Tx target for periodic Rcomp update */ |
5584 | /* Set up Tx target for periodic Rcomp update */ |
4948 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
5585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
4949 | 5586 | ||
4950 | /* Disable target IRef on PLL */ |
5587 | /* Disable target IRef on PLL */ |
4951 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
5588 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
4952 | reg_val &= 0x00ffffff; |
5589 | reg_val &= 0x00ffffff; |
4953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
5590 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
4954 | 5591 | ||
4955 | /* Disable fast lock */ |
5592 | /* Disable fast lock */ |
4956 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
5593 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
4957 | 5594 | ||
4958 | /* Set idtafcrecal before PLL is enabled */ |
5595 | /* Set idtafcrecal before PLL is enabled */ |
4959 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5596 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4960 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
5597 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4961 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
5598 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4962 | mdiv |= (1 << DPIO_K_SHIFT); |
5599 | mdiv |= (1 << DPIO_K_SHIFT); |
4963 | 5600 | ||
4964 | /* |
5601 | /* |
4965 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
5602 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4966 | * but we don't support that). |
5603 | * but we don't support that). |
4967 | * Note: don't use the DAC post divider as it seems unstable. |
5604 | * Note: don't use the DAC post divider as it seems unstable. |
4968 | */ |
5605 | */ |
4969 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
5606 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4970 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
5607 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
4971 | 5608 | ||
4972 | mdiv |= DPIO_ENABLE_CALIBRATION; |
5609 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
5610 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
4974 | 5611 | ||
4975 | /* Set HBR and RBR LPF coefficients */ |
5612 | /* Set HBR and RBR LPF coefficients */ |
4976 | if (crtc->config.port_clock == 162000 || |
5613 | if (crtc->config.port_clock == 162000 || |
4977 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
5614 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4978 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
5615 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4979 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
5616 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
4980 | 0x009f0003); |
5617 | 0x009f0003); |
4981 | else |
5618 | else |
4982 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
5619 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
4983 | 0x00d0000f); |
5620 | 0x00d0000f); |
4984 | 5621 | ||
4985 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
5622 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4986 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
5623 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4987 | /* Use SSC source */ |
5624 | /* Use SSC source */ |
4988 | if (!pipe) |
5625 | if (pipe == PIPE_A) |
4989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5626 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4990 | 0x0df40000); |
5627 | 0x0df40000); |
4991 | else |
5628 | else |
4992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5629 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4993 | 0x0df70000); |
5630 | 0x0df70000); |
4994 | } else { /* HDMI or VGA */ |
5631 | } else { /* HDMI or VGA */ |
4995 | /* Use bend source */ |
5632 | /* Use bend source */ |
4996 | if (!pipe) |
5633 | if (pipe == PIPE_A) |
4997 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5634 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4998 | 0x0df70000); |
5635 | 0x0df70000); |
4999 | else |
5636 | else |
5000 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5637 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5001 | 0x0df40000); |
5638 | 0x0df40000); |
5002 | } |
5639 | } |
5003 | 5640 | ||
5004 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
5641 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
5005 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5642 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5006 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
5643 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
5007 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5644 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5008 | coreclk |= 0x01000000; |
5645 | coreclk |= 0x01000000; |
5009 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
5646 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
5010 | 5647 | ||
5011 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
5648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
- | 5649 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 5650 | } |
|
- | 5651 | ||
- | 5652 | static void chv_update_pll(struct intel_crtc *crtc) |
|
- | 5653 | { |
|
- | 5654 | struct drm_device *dev = crtc->base.dev; |
|
- | 5655 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5656 | int pipe = crtc->pipe; |
|
- | 5657 | int dpll_reg = DPLL(crtc->pipe); |
|
- | 5658 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 5659 | u32 loopfilter, intcoeff; |
|
- | 5660 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
|
- | 5661 | int refclk; |
|
- | 5662 | ||
- | 5663 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
|
- | 5664 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
|
- | 5665 | DPLL_VCO_ENABLE; |
|
- | 5666 | if (pipe != PIPE_A) |
|
- | 5667 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 5668 | ||
- | 5669 | crtc->config.dpll_hw_state.dpll_md = |
|
- | 5670 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
|
- | 5671 | ||
- | 5672 | bestn = crtc->config.dpll.n; |
|
- | 5673 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; |
|
- | 5674 | bestm1 = crtc->config.dpll.m1; |
|
- | 5675 | bestm2 = crtc->config.dpll.m2 >> 22; |
|
- | 5676 | bestp1 = crtc->config.dpll.p1; |
|
- | 5677 | bestp2 = crtc->config.dpll.p2; |
|
5012 | 5678 | ||
5013 | /* |
- | |
5014 | * Enable DPIO clock input. We should never disable the reference |
- | |
5015 | * clock for pipe B, since VGA hotplug / manual detection depends |
5679 | /* |
5016 | * on it. |
5680 | * Enable Refclk and SSC |
5017 | */ |
- | |
5018 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
- | |
5019 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
- | |
5020 | /* We should never disable this, set it here for state tracking */ |
5681 | */ |
5021 | if (pipe == PIPE_B) |
- | |
5022 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
- | |
5023 | dpll |= DPLL_VCO_ENABLE; |
5682 | I915_WRITE(dpll_reg, |
5024 | crtc->config.dpll_hw_state.dpll = dpll; |
- | |
5025 | 5683 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
|
5026 | dpll_md = (crtc->config.pixel_multiplier - 1) |
- | |
- | 5684 | ||
- | 5685 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 5686 | ||
- | 5687 | /* p1 and p2 divider */ |
|
- | 5688 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
|
- | 5689 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
|
- | 5690 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
|
- | 5691 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
|
- | 5692 | 1 << DPIO_CHV_K_DIV_SHIFT); |
|
- | 5693 | ||
- | 5694 | /* Feedback post-divider - m2 */ |
|
- | 5695 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
|
- | 5696 | ||
- | 5697 | /* Feedback refclk divider - n and m1 */ |
|
- | 5698 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
|
- | 5699 | DPIO_CHV_M1_DIV_BY_2 | |
|
- | 5700 | 1 << DPIO_CHV_N_DIV_SHIFT); |
|
- | 5701 | ||
5027 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5702 | /* M2 fraction division */ |
- | 5703 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
|
- | 5704 | ||
- | 5705 | /* M2 fraction division enable */ |
|
- | 5706 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), |
|
- | 5707 | DPIO_CHV_FRAC_DIV_EN | |
|
- | 5708 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); |
|
- | 5709 | ||
- | 5710 | /* Loop filter */ |
|
- | 5711 | refclk = i9xx_get_refclk(&crtc->base, 0); |
|
- | 5712 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
|
- | 5713 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; |
|
- | 5714 | if (refclk == 100000) |
|
- | 5715 | intcoeff = 11; |
|
- | 5716 | else if (refclk == 38400) |
|
- | 5717 | intcoeff = 10; |
|
- | 5718 | else |
|
- | 5719 | intcoeff = 9; |
|
- | 5720 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; |
|
- | 5721 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
|
- | 5722 | ||
5028 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5723 | /* AFC Recal */ |
5029 | 5724 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
|
5030 | if (crtc->config.has_dp_encoder) |
5725 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
5031 | intel_dp_set_m_n(crtc); |
5726 | DPIO_AFC_RECAL); |
5032 | 5727 | ||
5033 | mutex_unlock(&dev_priv->dpio_lock); |
5728 | mutex_unlock(&dev_priv->dpio_lock); |
5034 | } |
5729 | } |
5035 | 5730 | ||
5036 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5731 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5037 | intel_clock_t *reduced_clock, |
5732 | intel_clock_t *reduced_clock, |
5038 | int num_connectors) |
5733 | int num_connectors) |
5039 | { |
5734 | { |
5040 | struct drm_device *dev = crtc->base.dev; |
5735 | struct drm_device *dev = crtc->base.dev; |
5041 | struct drm_i915_private *dev_priv = dev->dev_private; |
5736 | struct drm_i915_private *dev_priv = dev->dev_private; |
5042 | u32 dpll; |
5737 | u32 dpll; |
5043 | bool is_sdvo; |
5738 | bool is_sdvo; |
5044 | struct dpll *clock = &crtc->config.dpll; |
5739 | struct dpll *clock = &crtc->config.dpll; |
5045 | 5740 | ||
5046 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5741 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5047 | 5742 | ||
5048 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5743 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5049 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
5744 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
5050 | 5745 | ||
5051 | dpll = DPLL_VGA_MODE_DIS; |
5746 | dpll = DPLL_VGA_MODE_DIS; |
5052 | 5747 | ||
5053 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
5748 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
5054 | dpll |= DPLLB_MODE_LVDS; |
5749 | dpll |= DPLLB_MODE_LVDS; |
5055 | else |
5750 | else |
5056 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5751 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5057 | 5752 | ||
5058 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5753 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5059 | dpll |= (crtc->config.pixel_multiplier - 1) |
5754 | dpll |= (crtc->config.pixel_multiplier - 1) |
5060 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
5755 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
5061 | } |
5756 | } |
5062 | 5757 | ||
5063 | if (is_sdvo) |
5758 | if (is_sdvo) |
5064 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5759 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5065 | 5760 | ||
5066 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
5761 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
5067 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5762 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5068 | 5763 | ||
5069 | /* compute bitmask from p1 value */ |
5764 | /* compute bitmask from p1 value */ |
5070 | if (IS_PINEVIEW(dev)) |
5765 | if (IS_PINEVIEW(dev)) |
5071 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
5766 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
5072 | else { |
5767 | else { |
5073 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5768 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5074 | if (IS_G4X(dev) && reduced_clock) |
5769 | if (IS_G4X(dev) && reduced_clock) |
5075 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5770 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5076 | } |
5771 | } |
5077 | switch (clock->p2) { |
5772 | switch (clock->p2) { |
5078 | case 5: |
5773 | case 5: |
5079 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5774 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5080 | break; |
5775 | break; |
5081 | case 7: |
5776 | case 7: |
5082 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5777 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5083 | break; |
5778 | break; |
5084 | case 10: |
5779 | case 10: |
5085 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5780 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5086 | break; |
5781 | break; |
5087 | case 14: |
5782 | case 14: |
5088 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5783 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5089 | break; |
5784 | break; |
5090 | } |
5785 | } |
5091 | if (INTEL_INFO(dev)->gen >= 4) |
5786 | if (INTEL_INFO(dev)->gen >= 4) |
5092 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5787 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5093 | 5788 | ||
5094 | if (crtc->config.sdvo_tv_clock) |
5789 | if (crtc->config.sdvo_tv_clock) |
5095 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
5790 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
5096 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5791 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5097 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5792 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5098 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5793 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5099 | else |
5794 | else |
5100 | dpll |= PLL_REF_INPUT_DREFCLK; |
5795 | dpll |= PLL_REF_INPUT_DREFCLK; |
5101 | 5796 | ||
5102 | dpll |= DPLL_VCO_ENABLE; |
5797 | dpll |= DPLL_VCO_ENABLE; |
5103 | crtc->config.dpll_hw_state.dpll = dpll; |
5798 | crtc->config.dpll_hw_state.dpll = dpll; |
5104 | 5799 | ||
5105 | if (INTEL_INFO(dev)->gen >= 4) { |
5800 | if (INTEL_INFO(dev)->gen >= 4) { |
5106 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5801 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5107 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5802 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5108 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5803 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5109 | } |
5804 | } |
5110 | - | ||
5111 | if (crtc->config.has_dp_encoder) |
- | |
5112 | intel_dp_set_m_n(crtc); |
- | |
5113 | } |
5805 | } |
5114 | 5806 | ||
5115 | static void i8xx_update_pll(struct intel_crtc *crtc, |
5807 | static void i8xx_update_pll(struct intel_crtc *crtc, |
5116 | intel_clock_t *reduced_clock, |
5808 | intel_clock_t *reduced_clock, |
5117 | int num_connectors) |
5809 | int num_connectors) |
5118 | { |
5810 | { |
5119 | struct drm_device *dev = crtc->base.dev; |
5811 | struct drm_device *dev = crtc->base.dev; |
5120 | struct drm_i915_private *dev_priv = dev->dev_private; |
5812 | struct drm_i915_private *dev_priv = dev->dev_private; |
5121 | u32 dpll; |
5813 | u32 dpll; |
5122 | struct dpll *clock = &crtc->config.dpll; |
5814 | struct dpll *clock = &crtc->config.dpll; |
5123 | 5815 | ||
5124 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5816 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5125 | 5817 | ||
5126 | dpll = DPLL_VGA_MODE_DIS; |
5818 | dpll = DPLL_VGA_MODE_DIS; |
5127 | 5819 | ||
5128 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
5820 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
5129 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5821 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5130 | } else { |
5822 | } else { |
5131 | if (clock->p1 == 2) |
5823 | if (clock->p1 == 2) |
5132 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
5824 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
5133 | else |
5825 | else |
5134 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5826 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5135 | if (clock->p2 == 4) |
5827 | if (clock->p2 == 4) |
5136 | dpll |= PLL_P2_DIVIDE_BY_4; |
5828 | dpll |= PLL_P2_DIVIDE_BY_4; |
5137 | } |
5829 | } |
5138 | 5830 | ||
5139 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5831 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5140 | dpll |= DPLL_DVO_2X_MODE; |
5832 | dpll |= DPLL_DVO_2X_MODE; |
5141 | 5833 | ||
5142 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5834 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5143 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5835 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5144 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5836 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5145 | else |
5837 | else |
5146 | dpll |= PLL_REF_INPUT_DREFCLK; |
5838 | dpll |= PLL_REF_INPUT_DREFCLK; |
5147 | 5839 | ||
5148 | dpll |= DPLL_VCO_ENABLE; |
5840 | dpll |= DPLL_VCO_ENABLE; |
5149 | crtc->config.dpll_hw_state.dpll = dpll; |
5841 | crtc->config.dpll_hw_state.dpll = dpll; |
5150 | } |
5842 | } |
5151 | 5843 | ||
5152 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
5844 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
5153 | { |
5845 | { |
5154 | struct drm_device *dev = intel_crtc->base.dev; |
5846 | struct drm_device *dev = intel_crtc->base.dev; |
5155 | struct drm_i915_private *dev_priv = dev->dev_private; |
5847 | struct drm_i915_private *dev_priv = dev->dev_private; |
5156 | enum pipe pipe = intel_crtc->pipe; |
5848 | enum pipe pipe = intel_crtc->pipe; |
5157 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5849 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5158 | struct drm_display_mode *adjusted_mode = |
5850 | struct drm_display_mode *adjusted_mode = |
5159 | &intel_crtc->config.adjusted_mode; |
5851 | &intel_crtc->config.adjusted_mode; |
5160 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5852 | uint32_t crtc_vtotal, crtc_vblank_end; |
- | 5853 | int vsyncshift = 0; |
|
5161 | 5854 | ||
5162 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5855 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5163 | * the hw state checker will get angry at the mismatch. */ |
5856 | * the hw state checker will get angry at the mismatch. */ |
5164 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
5857 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
5165 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
5858 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
5166 | 5859 | ||
5167 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5860 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5168 | /* the chip adds 2 halflines automatically */ |
5861 | /* the chip adds 2 halflines automatically */ |
5169 | crtc_vtotal -= 1; |
5862 | crtc_vtotal -= 1; |
5170 | crtc_vblank_end -= 1; |
5863 | crtc_vblank_end -= 1; |
- | 5864 | ||
5171 | vsyncshift = adjusted_mode->crtc_hsync_start |
5865 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
5172 | - adjusted_mode->crtc_htotal / 2; |
5866 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
5173 | } else { |
5867 | else |
- | 5868 | vsyncshift = adjusted_mode->crtc_hsync_start - |
|
- | 5869 | adjusted_mode->crtc_htotal / 2; |
|
5174 | vsyncshift = 0; |
5870 | if (vsyncshift < 0) |
- | 5871 | vsyncshift += adjusted_mode->crtc_htotal; |
|
5175 | } |
5872 | } |
5176 | 5873 | ||
5177 | if (INTEL_INFO(dev)->gen > 3) |
5874 | if (INTEL_INFO(dev)->gen > 3) |
5178 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
5875 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
5179 | 5876 | ||
5180 | I915_WRITE(HTOTAL(cpu_transcoder), |
5877 | I915_WRITE(HTOTAL(cpu_transcoder), |
5181 | (adjusted_mode->crtc_hdisplay - 1) | |
5878 | (adjusted_mode->crtc_hdisplay - 1) | |
5182 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5879 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5183 | I915_WRITE(HBLANK(cpu_transcoder), |
5880 | I915_WRITE(HBLANK(cpu_transcoder), |
5184 | (adjusted_mode->crtc_hblank_start - 1) | |
5881 | (adjusted_mode->crtc_hblank_start - 1) | |
5185 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5882 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5186 | I915_WRITE(HSYNC(cpu_transcoder), |
5883 | I915_WRITE(HSYNC(cpu_transcoder), |
5187 | (adjusted_mode->crtc_hsync_start - 1) | |
5884 | (adjusted_mode->crtc_hsync_start - 1) | |
5188 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5885 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5189 | 5886 | ||
5190 | I915_WRITE(VTOTAL(cpu_transcoder), |
5887 | I915_WRITE(VTOTAL(cpu_transcoder), |
5191 | (adjusted_mode->crtc_vdisplay - 1) | |
5888 | (adjusted_mode->crtc_vdisplay - 1) | |
5192 | ((crtc_vtotal - 1) << 16)); |
5889 | ((crtc_vtotal - 1) << 16)); |
5193 | I915_WRITE(VBLANK(cpu_transcoder), |
5890 | I915_WRITE(VBLANK(cpu_transcoder), |
5194 | (adjusted_mode->crtc_vblank_start - 1) | |
5891 | (adjusted_mode->crtc_vblank_start - 1) | |
5195 | ((crtc_vblank_end - 1) << 16)); |
5892 | ((crtc_vblank_end - 1) << 16)); |
5196 | I915_WRITE(VSYNC(cpu_transcoder), |
5893 | I915_WRITE(VSYNC(cpu_transcoder), |
5197 | (adjusted_mode->crtc_vsync_start - 1) | |
5894 | (adjusted_mode->crtc_vsync_start - 1) | |
5198 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5895 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5199 | 5896 | ||
5200 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5897 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5201 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
5898 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
5202 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
5899 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
5203 | * bits. */ |
5900 | * bits. */ |
5204 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
5901 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
5205 | (pipe == PIPE_B || pipe == PIPE_C)) |
5902 | (pipe == PIPE_B || pipe == PIPE_C)) |
5206 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
5903 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
5207 | 5904 | ||
5208 | /* pipesrc controls the size that is scaled from, which should |
5905 | /* pipesrc controls the size that is scaled from, which should |
5209 | * always be the user's requested size. |
5906 | * always be the user's requested size. |
5210 | */ |
5907 | */ |
5211 | I915_WRITE(PIPESRC(pipe), |
5908 | I915_WRITE(PIPESRC(pipe), |
5212 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5909 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5213 | (intel_crtc->config.pipe_src_h - 1)); |
5910 | (intel_crtc->config.pipe_src_h - 1)); |
5214 | } |
5911 | } |
5215 | 5912 | ||
5216 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5913 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5217 | struct intel_crtc_config *pipe_config) |
5914 | struct intel_crtc_config *pipe_config) |
5218 | { |
5915 | { |
5219 | struct drm_device *dev = crtc->base.dev; |
5916 | struct drm_device *dev = crtc->base.dev; |
5220 | struct drm_i915_private *dev_priv = dev->dev_private; |
5917 | struct drm_i915_private *dev_priv = dev->dev_private; |
5221 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
5918 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
5222 | uint32_t tmp; |
5919 | uint32_t tmp; |
5223 | 5920 | ||
5224 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
5921 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
5225 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
5922 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
5226 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
5923 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
5227 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
5924 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
5228 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
5925 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
5229 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
5926 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
5230 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
5927 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
5231 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
5928 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
5232 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
5929 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
5233 | 5930 | ||
5234 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
5931 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
5235 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
5932 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
5236 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
5933 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
5237 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
5934 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
5238 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
5935 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
5239 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
5936 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
5240 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
5937 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
5241 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
5938 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
5242 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
5939 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
5243 | 5940 | ||
5244 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
5941 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
5245 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
5942 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
5246 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
5943 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
5247 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
5944 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
5248 | } |
5945 | } |
5249 | 5946 | ||
5250 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
5947 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
5251 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5948 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5252 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
5949 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
5253 | 5950 | ||
5254 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
5951 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
5255 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
5952 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
5256 | } |
5953 | } |
5257 | 5954 | ||
5258 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5955 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5259 | struct intel_crtc_config *pipe_config) |
5956 | struct intel_crtc_config *pipe_config) |
- | 5957 | { |
|
- | 5958 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
|
- | 5959 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
|
- | 5960 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
|
- | 5961 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
|
- | 5962 | ||
5260 | { |
5963 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
- | 5964 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
|
- | 5965 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
|
5261 | struct drm_crtc *crtc = &intel_crtc->base; |
- | |
5262 | 5966 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
|
5263 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
- | |
5264 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
- | |
5265 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
- | |
5266 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
- | |
5267 | - | ||
5268 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
- | |
5269 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
- | |
5270 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
- | |
5271 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
- | |
5272 | 5967 | ||
5273 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
5968 | mode->flags = pipe_config->adjusted_mode.flags; |
5274 | 5969 | ||
5275 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
5970 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5276 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5971 | mode->flags |= pipe_config->adjusted_mode.flags; |
5277 | } |
5972 | } |
5278 | 5973 | ||
5279 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5974 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5280 | { |
5975 | { |
5281 | struct drm_device *dev = intel_crtc->base.dev; |
5976 | struct drm_device *dev = intel_crtc->base.dev; |
5282 | struct drm_i915_private *dev_priv = dev->dev_private; |
5977 | struct drm_i915_private *dev_priv = dev->dev_private; |
5283 | uint32_t pipeconf; |
5978 | uint32_t pipeconf; |
5284 | 5979 | ||
5285 | pipeconf = 0; |
5980 | pipeconf = 0; |
5286 | 5981 | ||
5287 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5982 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5288 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
5983 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
5289 | pipeconf |= PIPECONF_ENABLE; |
5984 | pipeconf |= PIPECONF_ENABLE; |
5290 | 5985 | ||
5291 | if (intel_crtc->config.double_wide) |
5986 | if (intel_crtc->config.double_wide) |
5292 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
5987 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
5293 | 5988 | ||
5294 | /* only g4x and later have fancy bpc/dither controls */ |
5989 | /* only g4x and later have fancy bpc/dither controls */ |
5295 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5990 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5296 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5991 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5297 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
5992 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
5298 | pipeconf |= PIPECONF_DITHER_EN | |
5993 | pipeconf |= PIPECONF_DITHER_EN | |
5299 | PIPECONF_DITHER_TYPE_SP; |
5994 | PIPECONF_DITHER_TYPE_SP; |
5300 | 5995 | ||
5301 | switch (intel_crtc->config.pipe_bpp) { |
5996 | switch (intel_crtc->config.pipe_bpp) { |
5302 | case 18: |
5997 | case 18: |
5303 | pipeconf |= PIPECONF_6BPC; |
5998 | pipeconf |= PIPECONF_6BPC; |
5304 | break; |
5999 | break; |
5305 | case 24: |
6000 | case 24: |
5306 | pipeconf |= PIPECONF_8BPC; |
6001 | pipeconf |= PIPECONF_8BPC; |
5307 | break; |
6002 | break; |
5308 | case 30: |
6003 | case 30: |
5309 | pipeconf |= PIPECONF_10BPC; |
6004 | pipeconf |= PIPECONF_10BPC; |
5310 | break; |
6005 | break; |
5311 | default: |
6006 | default: |
5312 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6007 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5313 | BUG(); |
6008 | BUG(); |
5314 | } |
6009 | } |
5315 | } |
6010 | } |
5316 | 6011 | ||
5317 | if (HAS_PIPE_CXSR(dev)) { |
6012 | if (HAS_PIPE_CXSR(dev)) { |
5318 | if (intel_crtc->lowfreq_avail) { |
6013 | if (intel_crtc->lowfreq_avail) { |
5319 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
6014 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
5320 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
6015 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5321 | } else { |
6016 | } else { |
5322 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
6017 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
5323 | } |
6018 | } |
5324 | } |
6019 | } |
- | 6020 | ||
5325 | 6021 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
|
5326 | if (!IS_GEN2(dev) && |
6022 | if (INTEL_INFO(dev)->gen < 4 || |
5327 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6023 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
5328 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6024 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
- | 6025 | else |
|
- | 6026 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
|
5329 | else |
6027 | } else |
5330 | pipeconf |= PIPECONF_PROGRESSIVE; |
6028 | pipeconf |= PIPECONF_PROGRESSIVE; |
5331 | 6029 | ||
5332 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6030 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5333 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
6031 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
5334 | 6032 | ||
5335 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6033 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5336 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
6034 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
5337 | } |
6035 | } |
5338 | 6036 | ||
5339 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
6037 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5340 | int x, int y, |
6038 | int x, int y, |
5341 | struct drm_framebuffer *fb) |
6039 | struct drm_framebuffer *fb) |
5342 | { |
6040 | { |
5343 | struct drm_device *dev = crtc->dev; |
6041 | struct drm_device *dev = crtc->dev; |
5344 | struct drm_i915_private *dev_priv = dev->dev_private; |
6042 | struct drm_i915_private *dev_priv = dev->dev_private; |
5345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5346 | int pipe = intel_crtc->pipe; |
- | |
5347 | int plane = intel_crtc->plane; |
- | |
5348 | int refclk, num_connectors = 0; |
6044 | int refclk, num_connectors = 0; |
5349 | intel_clock_t clock, reduced_clock; |
6045 | intel_clock_t clock, reduced_clock; |
5350 | u32 dspcntr; |
- | |
5351 | bool ok, has_reduced_clock = false; |
6046 | bool ok, has_reduced_clock = false; |
5352 | bool is_lvds = false, is_dsi = false; |
6047 | bool is_lvds = false, is_dsi = false; |
5353 | struct intel_encoder *encoder; |
6048 | struct intel_encoder *encoder; |
5354 | const intel_limit_t *limit; |
6049 | const intel_limit_t *limit; |
5355 | int ret; |
- | |
5356 | 6050 | ||
5357 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6051 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5358 | switch (encoder->type) { |
6052 | switch (encoder->type) { |
5359 | case INTEL_OUTPUT_LVDS: |
6053 | case INTEL_OUTPUT_LVDS: |
5360 | is_lvds = true; |
6054 | is_lvds = true; |
5361 | break; |
6055 | break; |
5362 | case INTEL_OUTPUT_DSI: |
6056 | case INTEL_OUTPUT_DSI: |
5363 | is_dsi = true; |
6057 | is_dsi = true; |
5364 | break; |
6058 | break; |
5365 | } |
6059 | } |
5366 | 6060 | ||
5367 | num_connectors++; |
6061 | num_connectors++; |
5368 | } |
6062 | } |
5369 | 6063 | ||
5370 | if (is_dsi) |
6064 | if (is_dsi) |
5371 | goto skip_dpll; |
6065 | return 0; |
5372 | 6066 | ||
5373 | if (!intel_crtc->config.clock_set) { |
6067 | if (!intel_crtc->config.clock_set) { |
5374 | refclk = i9xx_get_refclk(crtc, num_connectors); |
6068 | refclk = i9xx_get_refclk(crtc, num_connectors); |
5375 | 6069 | ||
5376 | /* |
6070 | /* |
5377 | * Returns a set of divisors for the desired target clock with |
6071 | * Returns a set of divisors for the desired target clock with |
5378 | * the given refclk, or FALSE. The returned values represent |
6072 | * the given refclk, or FALSE. The returned values represent |
5379 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
6073 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
5380 | * 2) / p1 / p2. |
6074 | * 2) / p1 / p2. |
5381 | */ |
6075 | */ |
5382 | limit = intel_limit(crtc, refclk); |
6076 | limit = intel_limit(crtc, refclk); |
5383 | ok = dev_priv->display.find_dpll(limit, crtc, |
6077 | ok = dev_priv->display.find_dpll(limit, crtc, |
5384 | intel_crtc->config.port_clock, |
6078 | intel_crtc->config.port_clock, |
5385 | refclk, NULL, &clock); |
6079 | refclk, NULL, &clock); |
5386 | if (!ok) { |
6080 | if (!ok) { |
5387 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6081 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5388 | return -EINVAL; |
6082 | return -EINVAL; |
5389 | } |
6083 | } |
5390 | 6084 | ||
5391 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6085 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5392 | /* |
6086 | /* |
5393 | * Ensure we match the reduced clock's P to the target |
6087 | * Ensure we match the reduced clock's P to the target |
5394 | * clock. If the clocks don't match, we can't switch |
6088 | * clock. If the clocks don't match, we can't switch |
5395 | * the display clock by using the FP0/FP1. In such case |
6089 | * the display clock by using the FP0/FP1. In such case |
5396 | * we will disable the LVDS downclock feature. |
6090 | * we will disable the LVDS downclock feature. |
5397 | */ |
6091 | */ |
5398 | has_reduced_clock = |
6092 | has_reduced_clock = |
5399 | dev_priv->display.find_dpll(limit, crtc, |
6093 | dev_priv->display.find_dpll(limit, crtc, |
5400 | dev_priv->lvds_downclock, |
6094 | dev_priv->lvds_downclock, |
5401 | refclk, &clock, |
6095 | refclk, &clock, |
5402 | &reduced_clock); |
6096 | &reduced_clock); |
5403 | } |
6097 | } |
5404 | /* Compat-code for transition, will disappear. */ |
6098 | /* Compat-code for transition, will disappear. */ |
5405 | intel_crtc->config.dpll.n = clock.n; |
6099 | intel_crtc->config.dpll.n = clock.n; |
5406 | intel_crtc->config.dpll.m1 = clock.m1; |
6100 | intel_crtc->config.dpll.m1 = clock.m1; |
5407 | intel_crtc->config.dpll.m2 = clock.m2; |
6101 | intel_crtc->config.dpll.m2 = clock.m2; |
5408 | intel_crtc->config.dpll.p1 = clock.p1; |
6102 | intel_crtc->config.dpll.p1 = clock.p1; |
5409 | intel_crtc->config.dpll.p2 = clock.p2; |
6103 | intel_crtc->config.dpll.p2 = clock.p2; |
5410 | } |
6104 | } |
5411 | 6105 | ||
5412 | if (IS_GEN2(dev)) { |
6106 | if (IS_GEN2(dev)) { |
5413 | i8xx_update_pll(intel_crtc, |
6107 | i8xx_update_pll(intel_crtc, |
5414 | has_reduced_clock ? &reduced_clock : NULL, |
6108 | has_reduced_clock ? &reduced_clock : NULL, |
5415 | num_connectors); |
6109 | num_connectors); |
- | 6110 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 6111 | chv_update_pll(intel_crtc); |
|
5416 | } else if (IS_VALLEYVIEW(dev)) { |
6112 | } else if (IS_VALLEYVIEW(dev)) { |
5417 | vlv_update_pll(intel_crtc); |
6113 | vlv_update_pll(intel_crtc); |
5418 | } else { |
6114 | } else { |
5419 | i9xx_update_pll(intel_crtc, |
6115 | i9xx_update_pll(intel_crtc, |
5420 | has_reduced_clock ? &reduced_clock : NULL, |
6116 | has_reduced_clock ? &reduced_clock : NULL, |
5421 | num_connectors); |
6117 | num_connectors); |
5422 | } |
6118 | } |
5423 | - | ||
5424 | skip_dpll: |
- | |
5425 | /* Set up the display plane register */ |
- | |
5426 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
- | |
5427 | - | ||
5428 | if (!IS_VALLEYVIEW(dev)) { |
- | |
5429 | if (pipe == 0) |
- | |
5430 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
- | |
5431 | else |
- | |
5432 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
- | |
5433 | } |
- | |
5434 | - | ||
5435 | intel_set_pipe_timings(intel_crtc); |
- | |
5436 | - | ||
5437 | /* pipesrc and dspsize control the size that is scaled from, |
- | |
5438 | * which should always be the user's requested size. |
- | |
5439 | */ |
- | |
5440 | I915_WRITE(DSPSIZE(plane), |
- | |
5441 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
- | |
5442 | (intel_crtc->config.pipe_src_w - 1)); |
- | |
5443 | I915_WRITE(DSPPOS(plane), 0); |
- | |
5444 | - | ||
5445 | i9xx_set_pipeconf(intel_crtc); |
- | |
5446 | - | ||
5447 | I915_WRITE(DSPCNTR(plane), dspcntr); |
- | |
5448 | POSTING_READ(DSPCNTR(plane)); |
- | |
5449 | - | ||
5450 | ret = intel_pipe_set_base(crtc, x, y, fb); |
- | |
5451 | 6119 | ||
5452 | return ret; |
6120 | return 0; |
5453 | } |
6121 | } |
5454 | 6122 | ||
5455 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6123 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5456 | struct intel_crtc_config *pipe_config) |
6124 | struct intel_crtc_config *pipe_config) |
5457 | { |
6125 | { |
5458 | struct drm_device *dev = crtc->base.dev; |
6126 | struct drm_device *dev = crtc->base.dev; |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; |
6127 | struct drm_i915_private *dev_priv = dev->dev_private; |
5460 | uint32_t tmp; |
6128 | uint32_t tmp; |
5461 | 6129 | ||
5462 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6130 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5463 | return; |
6131 | return; |
5464 | 6132 | ||
5465 | tmp = I915_READ(PFIT_CONTROL); |
6133 | tmp = I915_READ(PFIT_CONTROL); |
5466 | if (!(tmp & PFIT_ENABLE)) |
6134 | if (!(tmp & PFIT_ENABLE)) |
5467 | return; |
6135 | return; |
5468 | 6136 | ||
5469 | /* Check whether the pfit is attached to our pipe. */ |
6137 | /* Check whether the pfit is attached to our pipe. */ |
5470 | if (INTEL_INFO(dev)->gen < 4) { |
6138 | if (INTEL_INFO(dev)->gen < 4) { |
5471 | if (crtc->pipe != PIPE_B) |
6139 | if (crtc->pipe != PIPE_B) |
5472 | return; |
6140 | return; |
5473 | } else { |
6141 | } else { |
5474 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
6142 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
5475 | return; |
6143 | return; |
5476 | } |
6144 | } |
5477 | 6145 | ||
5478 | pipe_config->gmch_pfit.control = tmp; |
6146 | pipe_config->gmch_pfit.control = tmp; |
5479 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6147 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5480 | if (INTEL_INFO(dev)->gen < 5) |
6148 | if (INTEL_INFO(dev)->gen < 5) |
5481 | pipe_config->gmch_pfit.lvds_border_bits = |
6149 | pipe_config->gmch_pfit.lvds_border_bits = |
5482 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
6150 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5483 | } |
6151 | } |
5484 | 6152 | ||
5485 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6153 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5486 | struct intel_crtc_config *pipe_config) |
6154 | struct intel_crtc_config *pipe_config) |
5487 | { |
6155 | { |
5488 | struct drm_device *dev = crtc->base.dev; |
6156 | struct drm_device *dev = crtc->base.dev; |
5489 | struct drm_i915_private *dev_priv = dev->dev_private; |
6157 | struct drm_i915_private *dev_priv = dev->dev_private; |
5490 | int pipe = pipe_config->cpu_transcoder; |
6158 | int pipe = pipe_config->cpu_transcoder; |
5491 | intel_clock_t clock; |
6159 | intel_clock_t clock; |
5492 | u32 mdiv; |
6160 | u32 mdiv; |
5493 | int refclk = 100000; |
6161 | int refclk = 100000; |
- | 6162 | ||
- | 6163 | /* In case of MIPI DPLL will not even be used */ |
|
- | 6164 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
|
- | 6165 | return; |
|
5494 | 6166 | ||
5495 | mutex_lock(&dev_priv->dpio_lock); |
6167 | mutex_lock(&dev_priv->dpio_lock); |
5496 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
6168 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
5497 | mutex_unlock(&dev_priv->dpio_lock); |
6169 | mutex_unlock(&dev_priv->dpio_lock); |
5498 | 6170 | ||
5499 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
6171 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5500 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
6172 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5501 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
6173 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
5502 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
6174 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
5503 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
6175 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
5504 | 6176 | ||
5505 | vlv_clock(refclk, &clock); |
6177 | vlv_clock(refclk, &clock); |
5506 | 6178 | ||
5507 | /* clock.dot is the fast clock */ |
6179 | /* clock.dot is the fast clock */ |
5508 | pipe_config->port_clock = clock.dot / 5; |
6180 | pipe_config->port_clock = clock.dot / 5; |
5509 | } |
6181 | } |
- | 6182 | ||
- | 6183 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
|
- | 6184 | struct intel_plane_config *plane_config) |
|
- | 6185 | { |
|
- | 6186 | struct drm_device *dev = crtc->base.dev; |
|
- | 6187 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6188 | u32 val, base, offset; |
|
- | 6189 | int pipe = crtc->pipe, plane = crtc->plane; |
|
- | 6190 | int fourcc, pixel_format; |
|
- | 6191 | int aligned_height; |
|
- | 6192 | ||
- | 6193 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
|
- | 6194 | if (!crtc->base.primary->fb) { |
|
- | 6195 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
|
- | 6196 | return; |
|
- | 6197 | } |
|
- | 6198 | ||
- | 6199 | val = I915_READ(DSPCNTR(plane)); |
|
- | 6200 | ||
- | 6201 | if (INTEL_INFO(dev)->gen >= 4) |
|
- | 6202 | if (val & DISPPLANE_TILED) |
|
- | 6203 | plane_config->tiled = true; |
|
- | 6204 | ||
- | 6205 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
|
- | 6206 | fourcc = intel_format_to_fourcc(pixel_format); |
|
- | 6207 | crtc->base.primary->fb->pixel_format = fourcc; |
|
- | 6208 | crtc->base.primary->fb->bits_per_pixel = |
|
- | 6209 | drm_format_plane_cpp(fourcc, 0) * 8; |
|
- | 6210 | ||
- | 6211 | if (INTEL_INFO(dev)->gen >= 4) { |
|
- | 6212 | if (plane_config->tiled) |
|
- | 6213 | offset = I915_READ(DSPTILEOFF(plane)); |
|
- | 6214 | else |
|
- | 6215 | offset = I915_READ(DSPLINOFF(plane)); |
|
- | 6216 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
|
- | 6217 | } else { |
|
- | 6218 | base = I915_READ(DSPADDR(plane)); |
|
- | 6219 | } |
|
- | 6220 | plane_config->base = base; |
|
- | 6221 | ||
- | 6222 | val = I915_READ(PIPESRC(pipe)); |
|
- | 6223 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
|
- | 6224 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
|
- | 6225 | ||
- | 6226 | val = I915_READ(DSPSTRIDE(pipe)); |
|
- | 6227 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
|
- | 6228 | ||
- | 6229 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
|
- | 6230 | plane_config->tiled); |
|
- | 6231 | ||
- | 6232 | plane_config->size = 16*1024*1024; |
|
- | 6233 | ||
- | 6234 | ||
- | 6235 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
|
- | 6236 | pipe, plane, crtc->base.primary->fb->width, |
|
- | 6237 | crtc->base.primary->fb->height, |
|
- | 6238 | crtc->base.primary->fb->bits_per_pixel, base, |
|
- | 6239 | crtc->base.primary->fb->pitches[0], |
|
- | 6240 | plane_config->size); |
|
- | 6241 | ||
- | 6242 | } |
|
- | 6243 | ||
- | 6244 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
|
- | 6245 | struct intel_crtc_config *pipe_config) |
|
- | 6246 | { |
|
- | 6247 | struct drm_device *dev = crtc->base.dev; |
|
- | 6248 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6249 | int pipe = pipe_config->cpu_transcoder; |
|
- | 6250 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 6251 | intel_clock_t clock; |
|
- | 6252 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; |
|
- | 6253 | int refclk = 100000; |
|
- | 6254 | ||
- | 6255 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 6256 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
|
- | 6257 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
|
- | 6258 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
|
- | 6259 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
|
- | 6260 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 6261 | ||
- | 6262 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
|
- | 6263 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); |
|
- | 6264 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
|
- | 6265 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
|
- | 6266 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
|
- | 6267 | ||
- | 6268 | chv_clock(refclk, &clock); |
|
- | 6269 | ||
- | 6270 | /* clock.dot is the fast clock */ |
|
- | 6271 | pipe_config->port_clock = clock.dot / 5; |
|
- | 6272 | } |
|
5510 | 6273 | ||
5511 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6274 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5512 | struct intel_crtc_config *pipe_config) |
6275 | struct intel_crtc_config *pipe_config) |
5513 | { |
6276 | { |
5514 | struct drm_device *dev = crtc->base.dev; |
6277 | struct drm_device *dev = crtc->base.dev; |
5515 | struct drm_i915_private *dev_priv = dev->dev_private; |
6278 | struct drm_i915_private *dev_priv = dev->dev_private; |
5516 | uint32_t tmp; |
6279 | uint32_t tmp; |
- | 6280 | ||
- | 6281 | if (!intel_display_power_enabled(dev_priv, |
|
- | 6282 | POWER_DOMAIN_PIPE(crtc->pipe))) |
|
- | 6283 | return false; |
|
5517 | 6284 | ||
5518 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6285 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5519 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6286 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5520 | 6287 | ||
5521 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6288 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5522 | if (!(tmp & PIPECONF_ENABLE)) |
6289 | if (!(tmp & PIPECONF_ENABLE)) |
5523 | return false; |
6290 | return false; |
5524 | 6291 | ||
5525 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6292 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5526 | switch (tmp & PIPECONF_BPC_MASK) { |
6293 | switch (tmp & PIPECONF_BPC_MASK) { |
5527 | case PIPECONF_6BPC: |
6294 | case PIPECONF_6BPC: |
5528 | pipe_config->pipe_bpp = 18; |
6295 | pipe_config->pipe_bpp = 18; |
5529 | break; |
6296 | break; |
5530 | case PIPECONF_8BPC: |
6297 | case PIPECONF_8BPC: |
5531 | pipe_config->pipe_bpp = 24; |
6298 | pipe_config->pipe_bpp = 24; |
5532 | break; |
6299 | break; |
5533 | case PIPECONF_10BPC: |
6300 | case PIPECONF_10BPC: |
5534 | pipe_config->pipe_bpp = 30; |
6301 | pipe_config->pipe_bpp = 30; |
5535 | break; |
6302 | break; |
5536 | default: |
6303 | default: |
5537 | break; |
6304 | break; |
5538 | } |
6305 | } |
5539 | } |
6306 | } |
- | 6307 | ||
- | 6308 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
|
- | 6309 | pipe_config->limited_color_range = true; |
|
5540 | 6310 | ||
5541 | if (INTEL_INFO(dev)->gen < 4) |
6311 | if (INTEL_INFO(dev)->gen < 4) |
5542 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
6312 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
5543 | 6313 | ||
5544 | intel_get_pipe_timings(crtc, pipe_config); |
6314 | intel_get_pipe_timings(crtc, pipe_config); |
5545 | 6315 | ||
5546 | i9xx_get_pfit_config(crtc, pipe_config); |
6316 | i9xx_get_pfit_config(crtc, pipe_config); |
5547 | 6317 | ||
5548 | if (INTEL_INFO(dev)->gen >= 4) { |
6318 | if (INTEL_INFO(dev)->gen >= 4) { |
5549 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
6319 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
5550 | pipe_config->pixel_multiplier = |
6320 | pipe_config->pixel_multiplier = |
5551 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
6321 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
5552 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
6322 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
5553 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6323 | pipe_config->dpll_hw_state.dpll_md = tmp; |
5554 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6324 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5555 | tmp = I915_READ(DPLL(crtc->pipe)); |
6325 | tmp = I915_READ(DPLL(crtc->pipe)); |
5556 | pipe_config->pixel_multiplier = |
6326 | pipe_config->pixel_multiplier = |
5557 | ((tmp & SDVO_MULTIPLIER_MASK) |
6327 | ((tmp & SDVO_MULTIPLIER_MASK) |
5558 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
6328 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
5559 | } else { |
6329 | } else { |
5560 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
6330 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
5561 | * port and will be fixed up in the encoder->get_config |
6331 | * port and will be fixed up in the encoder->get_config |
5562 | * function. */ |
6332 | * function. */ |
5563 | pipe_config->pixel_multiplier = 1; |
6333 | pipe_config->pixel_multiplier = 1; |
5564 | } |
6334 | } |
5565 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6335 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5566 | if (!IS_VALLEYVIEW(dev)) { |
6336 | if (!IS_VALLEYVIEW(dev)) { |
5567 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6337 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5568 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
6338 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5569 | } else { |
6339 | } else { |
5570 | /* Mask out read-only status bits. */ |
6340 | /* Mask out read-only status bits. */ |
5571 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
6341 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5572 | DPLL_PORTC_READY_MASK | |
6342 | DPLL_PORTC_READY_MASK | |
5573 | DPLL_PORTB_READY_MASK); |
6343 | DPLL_PORTB_READY_MASK); |
5574 | } |
6344 | } |
- | 6345 | ||
- | 6346 | if (IS_CHERRYVIEW(dev)) |
|
5575 | 6347 | chv_crtc_clock_get(crtc, pipe_config); |
|
5576 | if (IS_VALLEYVIEW(dev)) |
6348 | else if (IS_VALLEYVIEW(dev)) |
5577 | vlv_crtc_clock_get(crtc, pipe_config); |
6349 | vlv_crtc_clock_get(crtc, pipe_config); |
5578 | else |
6350 | else |
5579 | i9xx_crtc_clock_get(crtc, pipe_config); |
6351 | i9xx_crtc_clock_get(crtc, pipe_config); |
5580 | 6352 | ||
5581 | return true; |
6353 | return true; |
5582 | } |
6354 | } |
5583 | 6355 | ||
5584 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
6356 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5585 | { |
6357 | { |
5586 | struct drm_i915_private *dev_priv = dev->dev_private; |
6358 | struct drm_i915_private *dev_priv = dev->dev_private; |
5587 | struct drm_mode_config *mode_config = &dev->mode_config; |
6359 | struct drm_mode_config *mode_config = &dev->mode_config; |
5588 | struct intel_encoder *encoder; |
6360 | struct intel_encoder *encoder; |
5589 | u32 val, final; |
6361 | u32 val, final; |
5590 | bool has_lvds = false; |
6362 | bool has_lvds = false; |
5591 | bool has_cpu_edp = false; |
6363 | bool has_cpu_edp = false; |
5592 | bool has_panel = false; |
6364 | bool has_panel = false; |
5593 | bool has_ck505 = false; |
6365 | bool has_ck505 = false; |
5594 | bool can_ssc = false; |
6366 | bool can_ssc = false; |
5595 | 6367 | ||
5596 | /* We need to take the global config into account */ |
6368 | /* We need to take the global config into account */ |
5597 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6369 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5598 | base.head) { |
6370 | base.head) { |
5599 | switch (encoder->type) { |
6371 | switch (encoder->type) { |
5600 | case INTEL_OUTPUT_LVDS: |
6372 | case INTEL_OUTPUT_LVDS: |
5601 | has_panel = true; |
6373 | has_panel = true; |
5602 | has_lvds = true; |
6374 | has_lvds = true; |
5603 | break; |
6375 | break; |
5604 | case INTEL_OUTPUT_EDP: |
6376 | case INTEL_OUTPUT_EDP: |
5605 | has_panel = true; |
6377 | has_panel = true; |
5606 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
6378 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5607 | has_cpu_edp = true; |
6379 | has_cpu_edp = true; |
5608 | break; |
6380 | break; |
5609 | } |
6381 | } |
5610 | } |
6382 | } |
5611 | 6383 | ||
5612 | if (HAS_PCH_IBX(dev)) { |
6384 | if (HAS_PCH_IBX(dev)) { |
5613 | has_ck505 = dev_priv->vbt.display_clock_mode; |
6385 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5614 | can_ssc = has_ck505; |
6386 | can_ssc = has_ck505; |
5615 | } else { |
6387 | } else { |
5616 | has_ck505 = false; |
6388 | has_ck505 = false; |
5617 | can_ssc = true; |
6389 | can_ssc = true; |
5618 | } |
6390 | } |
5619 | 6391 | ||
5620 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6392 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5621 | has_panel, has_lvds, has_ck505); |
6393 | has_panel, has_lvds, has_ck505); |
5622 | 6394 | ||
5623 | /* Ironlake: try to setup display ref clock before DPLL |
6395 | /* Ironlake: try to setup display ref clock before DPLL |
5624 | * enabling. This is only under driver's control after |
6396 | * enabling. This is only under driver's control after |
5625 | * PCH B stepping, previous chipset stepping should be |
6397 | * PCH B stepping, previous chipset stepping should be |
5626 | * ignoring this setting. |
6398 | * ignoring this setting. |
5627 | */ |
6399 | */ |
5628 | val = I915_READ(PCH_DREF_CONTROL); |
6400 | val = I915_READ(PCH_DREF_CONTROL); |
5629 | 6401 | ||
5630 | /* As we must carefully and slowly disable/enable each source in turn, |
6402 | /* As we must carefully and slowly disable/enable each source in turn, |
5631 | * compute the final state we want first and check if we need to |
6403 | * compute the final state we want first and check if we need to |
5632 | * make any changes at all. |
6404 | * make any changes at all. |
5633 | */ |
6405 | */ |
5634 | final = val; |
6406 | final = val; |
5635 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
6407 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5636 | if (has_ck505) |
6408 | if (has_ck505) |
5637 | final |= DREF_NONSPREAD_CK505_ENABLE; |
6409 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5638 | else |
6410 | else |
5639 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
6411 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5640 | 6412 | ||
5641 | final &= ~DREF_SSC_SOURCE_MASK; |
6413 | final &= ~DREF_SSC_SOURCE_MASK; |
5642 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
6414 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5643 | final &= ~DREF_SSC1_ENABLE; |
6415 | final &= ~DREF_SSC1_ENABLE; |
5644 | 6416 | ||
5645 | if (has_panel) { |
6417 | if (has_panel) { |
5646 | final |= DREF_SSC_SOURCE_ENABLE; |
6418 | final |= DREF_SSC_SOURCE_ENABLE; |
5647 | 6419 | ||
5648 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
6420 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5649 | final |= DREF_SSC1_ENABLE; |
6421 | final |= DREF_SSC1_ENABLE; |
5650 | 6422 | ||
5651 | if (has_cpu_edp) { |
6423 | if (has_cpu_edp) { |
5652 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
6424 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5653 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
6425 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5654 | else |
6426 | else |
5655 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
6427 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5656 | } else |
6428 | } else |
5657 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6429 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5658 | } else { |
6430 | } else { |
5659 | final |= DREF_SSC_SOURCE_DISABLE; |
6431 | final |= DREF_SSC_SOURCE_DISABLE; |
5660 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6432 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5661 | } |
6433 | } |
5662 | 6434 | ||
5663 | if (final == val) |
6435 | if (final == val) |
5664 | return; |
6436 | return; |
5665 | 6437 | ||
5666 | /* Always enable nonspread source */ |
6438 | /* Always enable nonspread source */ |
5667 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
6439 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5668 | 6440 | ||
5669 | if (has_ck505) |
6441 | if (has_ck505) |
5670 | val |= DREF_NONSPREAD_CK505_ENABLE; |
6442 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5671 | else |
6443 | else |
5672 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
6444 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5673 | 6445 | ||
5674 | if (has_panel) { |
6446 | if (has_panel) { |
5675 | val &= ~DREF_SSC_SOURCE_MASK; |
6447 | val &= ~DREF_SSC_SOURCE_MASK; |
5676 | val |= DREF_SSC_SOURCE_ENABLE; |
6448 | val |= DREF_SSC_SOURCE_ENABLE; |
5677 | 6449 | ||
5678 | /* SSC must be turned on before enabling the CPU output */ |
6450 | /* SSC must be turned on before enabling the CPU output */ |
5679 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
6451 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5680 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
6452 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5681 | val |= DREF_SSC1_ENABLE; |
6453 | val |= DREF_SSC1_ENABLE; |
5682 | } else |
6454 | } else |
5683 | val &= ~DREF_SSC1_ENABLE; |
6455 | val &= ~DREF_SSC1_ENABLE; |
5684 | 6456 | ||
5685 | /* Get SSC going before enabling the outputs */ |
6457 | /* Get SSC going before enabling the outputs */ |
5686 | I915_WRITE(PCH_DREF_CONTROL, val); |
6458 | I915_WRITE(PCH_DREF_CONTROL, val); |
5687 | POSTING_READ(PCH_DREF_CONTROL); |
6459 | POSTING_READ(PCH_DREF_CONTROL); |
5688 | udelay(200); |
6460 | udelay(200); |
5689 | 6461 | ||
5690 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
6462 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5691 | 6463 | ||
5692 | /* Enable CPU source on CPU attached eDP */ |
6464 | /* Enable CPU source on CPU attached eDP */ |
5693 | if (has_cpu_edp) { |
6465 | if (has_cpu_edp) { |
5694 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
6466 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5695 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
6467 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5696 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
6468 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5697 | } |
- | |
5698 | else |
6469 | } else |
5699 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
6470 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5700 | } else |
6471 | } else |
5701 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6472 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5702 | 6473 | ||
5703 | I915_WRITE(PCH_DREF_CONTROL, val); |
6474 | I915_WRITE(PCH_DREF_CONTROL, val); |
5704 | POSTING_READ(PCH_DREF_CONTROL); |
6475 | POSTING_READ(PCH_DREF_CONTROL); |
5705 | udelay(200); |
6476 | udelay(200); |
5706 | } else { |
6477 | } else { |
5707 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
6478 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5708 | 6479 | ||
5709 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
6480 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5710 | 6481 | ||
5711 | /* Turn off CPU output */ |
6482 | /* Turn off CPU output */ |
5712 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6483 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5713 | 6484 | ||
5714 | I915_WRITE(PCH_DREF_CONTROL, val); |
6485 | I915_WRITE(PCH_DREF_CONTROL, val); |
5715 | POSTING_READ(PCH_DREF_CONTROL); |
6486 | POSTING_READ(PCH_DREF_CONTROL); |
5716 | udelay(200); |
6487 | udelay(200); |
5717 | 6488 | ||
5718 | /* Turn off the SSC source */ |
6489 | /* Turn off the SSC source */ |
5719 | val &= ~DREF_SSC_SOURCE_MASK; |
6490 | val &= ~DREF_SSC_SOURCE_MASK; |
5720 | val |= DREF_SSC_SOURCE_DISABLE; |
6491 | val |= DREF_SSC_SOURCE_DISABLE; |
5721 | 6492 | ||
5722 | /* Turn off SSC1 */ |
6493 | /* Turn off SSC1 */ |
5723 | val &= ~DREF_SSC1_ENABLE; |
6494 | val &= ~DREF_SSC1_ENABLE; |
5724 | 6495 | ||
5725 | I915_WRITE(PCH_DREF_CONTROL, val); |
6496 | I915_WRITE(PCH_DREF_CONTROL, val); |
5726 | POSTING_READ(PCH_DREF_CONTROL); |
6497 | POSTING_READ(PCH_DREF_CONTROL); |
5727 | udelay(200); |
6498 | udelay(200); |
5728 | } |
6499 | } |
5729 | 6500 | ||
5730 | BUG_ON(val != final); |
6501 | BUG_ON(val != final); |
5731 | } |
6502 | } |
5732 | 6503 | ||
5733 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
6504 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
5734 | { |
6505 | { |
5735 | uint32_t tmp; |
6506 | uint32_t tmp; |
5736 | 6507 | ||
5737 | tmp = I915_READ(SOUTH_CHICKEN2); |
6508 | tmp = I915_READ(SOUTH_CHICKEN2); |
5738 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
6509 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
5739 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
6510 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5740 | 6511 | ||
5741 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6512 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5742 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
6513 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
5743 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
6514 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
5744 | 6515 | ||
5745 | tmp = I915_READ(SOUTH_CHICKEN2); |
6516 | tmp = I915_READ(SOUTH_CHICKEN2); |
5746 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
6517 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
5747 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
6518 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5748 | 6519 | ||
5749 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6520 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5750 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
6521 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
5751 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
6522 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5752 | } |
6523 | } |
5753 | 6524 | ||
5754 | /* WaMPhyProgramming:hsw */ |
6525 | /* WaMPhyProgramming:hsw */ |
5755 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
6526 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
5756 | { |
6527 | { |
5757 | uint32_t tmp; |
6528 | uint32_t tmp; |
5758 | 6529 | ||
5759 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
6530 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5760 | tmp &= ~(0xFF << 24); |
6531 | tmp &= ~(0xFF << 24); |
5761 | tmp |= (0x12 << 24); |
6532 | tmp |= (0x12 << 24); |
5762 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
6533 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
5763 | 6534 | ||
5764 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6535 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5765 | tmp |= (1 << 11); |
6536 | tmp |= (1 << 11); |
5766 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
6537 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
5767 | 6538 | ||
5768 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
6539 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
5769 | tmp |= (1 << 11); |
6540 | tmp |= (1 << 11); |
5770 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
6541 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
5771 | 6542 | ||
5772 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6543 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5773 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
6544 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5774 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
6545 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
5775 | 6546 | ||
5776 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
6547 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
5777 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
6548 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5778 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
6549 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
5779 | 6550 | ||
5780 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6551 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5781 | tmp &= ~(7 << 13); |
6552 | tmp &= ~(7 << 13); |
5782 | tmp |= (5 << 13); |
6553 | tmp |= (5 << 13); |
5783 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
6554 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
5784 | 6555 | ||
5785 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6556 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5786 | tmp &= ~(7 << 13); |
6557 | tmp &= ~(7 << 13); |
5787 | tmp |= (5 << 13); |
6558 | tmp |= (5 << 13); |
5788 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
6559 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
5789 | 6560 | ||
5790 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
6561 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
5791 | tmp &= ~0xFF; |
6562 | tmp &= ~0xFF; |
5792 | tmp |= 0x1C; |
6563 | tmp |= 0x1C; |
5793 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
6564 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
5794 | 6565 | ||
5795 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
6566 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
5796 | tmp &= ~0xFF; |
6567 | tmp &= ~0xFF; |
5797 | tmp |= 0x1C; |
6568 | tmp |= 0x1C; |
5798 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
6569 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
5799 | 6570 | ||
5800 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
6571 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
5801 | tmp &= ~(0xFF << 16); |
6572 | tmp &= ~(0xFF << 16); |
5802 | tmp |= (0x1C << 16); |
6573 | tmp |= (0x1C << 16); |
5803 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
6574 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
5804 | 6575 | ||
5805 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
6576 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
5806 | tmp &= ~(0xFF << 16); |
6577 | tmp &= ~(0xFF << 16); |
5807 | tmp |= (0x1C << 16); |
6578 | tmp |= (0x1C << 16); |
5808 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
6579 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
5809 | 6580 | ||
5810 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6581 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5811 | tmp |= (1 << 27); |
6582 | tmp |= (1 << 27); |
5812 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
6583 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
5813 | 6584 | ||
5814 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6585 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5815 | tmp |= (1 << 27); |
6586 | tmp |= (1 << 27); |
5816 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
6587 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
5817 | 6588 | ||
5818 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6589 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5819 | tmp &= ~(0xF << 28); |
6590 | tmp &= ~(0xF << 28); |
5820 | tmp |= (4 << 28); |
6591 | tmp |= (4 << 28); |
5821 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
6592 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
5822 | 6593 | ||
5823 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6594 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5824 | tmp &= ~(0xF << 28); |
6595 | tmp &= ~(0xF << 28); |
5825 | tmp |= (4 << 28); |
6596 | tmp |= (4 << 28); |
5826 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
6597 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
5827 | } |
6598 | } |
5828 | 6599 | ||
5829 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6600 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5830 | * Programming" based on the parameters passed: |
6601 | * Programming" based on the parameters passed: |
5831 | * - Sequence to enable CLKOUT_DP |
6602 | * - Sequence to enable CLKOUT_DP |
5832 | * - Sequence to enable CLKOUT_DP without spread |
6603 | * - Sequence to enable CLKOUT_DP without spread |
5833 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
6604 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
5834 | */ |
6605 | */ |
5835 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
6606 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
5836 | bool with_fdi) |
6607 | bool with_fdi) |
5837 | { |
6608 | { |
5838 | struct drm_i915_private *dev_priv = dev->dev_private; |
6609 | struct drm_i915_private *dev_priv = dev->dev_private; |
5839 | uint32_t reg, tmp; |
6610 | uint32_t reg, tmp; |
5840 | 6611 | ||
5841 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
6612 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5842 | with_spread = true; |
6613 | with_spread = true; |
5843 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
6614 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
5844 | with_fdi, "LP PCH doesn't have FDI\n")) |
6615 | with_fdi, "LP PCH doesn't have FDI\n")) |
5845 | with_fdi = false; |
6616 | with_fdi = false; |
5846 | 6617 | ||
5847 | mutex_lock(&dev_priv->dpio_lock); |
6618 | mutex_lock(&dev_priv->dpio_lock); |
5848 | 6619 | ||
5849 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6620 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5850 | tmp &= ~SBI_SSCCTL_DISABLE; |
6621 | tmp &= ~SBI_SSCCTL_DISABLE; |
5851 | tmp |= SBI_SSCCTL_PATHALT; |
6622 | tmp |= SBI_SSCCTL_PATHALT; |
5852 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6623 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5853 | 6624 | ||
5854 | udelay(24); |
6625 | udelay(24); |
5855 | 6626 | ||
5856 | if (with_spread) { |
6627 | if (with_spread) { |
5857 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6628 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5858 | tmp &= ~SBI_SSCCTL_PATHALT; |
6629 | tmp &= ~SBI_SSCCTL_PATHALT; |
5859 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6630 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5860 | 6631 | ||
5861 | if (with_fdi) { |
6632 | if (with_fdi) { |
5862 | lpt_reset_fdi_mphy(dev_priv); |
6633 | lpt_reset_fdi_mphy(dev_priv); |
5863 | lpt_program_fdi_mphy(dev_priv); |
6634 | lpt_program_fdi_mphy(dev_priv); |
5864 | } |
6635 | } |
5865 | } |
6636 | } |
5866 | 6637 | ||
5867 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6638 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5868 | SBI_GEN0 : SBI_DBUFF0; |
6639 | SBI_GEN0 : SBI_DBUFF0; |
5869 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
6640 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5870 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
6641 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5871 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
6642 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5872 | 6643 | ||
5873 | mutex_unlock(&dev_priv->dpio_lock); |
6644 | mutex_unlock(&dev_priv->dpio_lock); |
5874 | } |
6645 | } |
5875 | 6646 | ||
5876 | /* Sequence to disable CLKOUT_DP */ |
6647 | /* Sequence to disable CLKOUT_DP */ |
5877 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
6648 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
5878 | { |
6649 | { |
5879 | struct drm_i915_private *dev_priv = dev->dev_private; |
6650 | struct drm_i915_private *dev_priv = dev->dev_private; |
5880 | uint32_t reg, tmp; |
6651 | uint32_t reg, tmp; |
5881 | 6652 | ||
5882 | mutex_lock(&dev_priv->dpio_lock); |
6653 | mutex_lock(&dev_priv->dpio_lock); |
5883 | 6654 | ||
5884 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6655 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5885 | SBI_GEN0 : SBI_DBUFF0; |
6656 | SBI_GEN0 : SBI_DBUFF0; |
5886 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
6657 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5887 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
6658 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5888 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
6659 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5889 | 6660 | ||
5890 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6661 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5891 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
6662 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
5892 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
6663 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
5893 | tmp |= SBI_SSCCTL_PATHALT; |
6664 | tmp |= SBI_SSCCTL_PATHALT; |
5894 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6665 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5895 | udelay(32); |
6666 | udelay(32); |
5896 | } |
6667 | } |
5897 | tmp |= SBI_SSCCTL_DISABLE; |
6668 | tmp |= SBI_SSCCTL_DISABLE; |
5898 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6669 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5899 | } |
6670 | } |
5900 | 6671 | ||
5901 | mutex_unlock(&dev_priv->dpio_lock); |
6672 | mutex_unlock(&dev_priv->dpio_lock); |
5902 | } |
6673 | } |
5903 | 6674 | ||
5904 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6675 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5905 | { |
6676 | { |
5906 | struct drm_mode_config *mode_config = &dev->mode_config; |
6677 | struct drm_mode_config *mode_config = &dev->mode_config; |
5907 | struct intel_encoder *encoder; |
6678 | struct intel_encoder *encoder; |
5908 | bool has_vga = false; |
6679 | bool has_vga = false; |
5909 | 6680 | ||
5910 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
6681 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5911 | switch (encoder->type) { |
6682 | switch (encoder->type) { |
5912 | case INTEL_OUTPUT_ANALOG: |
6683 | case INTEL_OUTPUT_ANALOG: |
5913 | has_vga = true; |
6684 | has_vga = true; |
5914 | break; |
6685 | break; |
5915 | } |
6686 | } |
5916 | } |
6687 | } |
5917 | 6688 | ||
5918 | if (has_vga) |
6689 | if (has_vga) |
5919 | lpt_enable_clkout_dp(dev, true, true); |
6690 | lpt_enable_clkout_dp(dev, true, true); |
5920 | else |
6691 | else |
5921 | lpt_disable_clkout_dp(dev); |
6692 | lpt_disable_clkout_dp(dev); |
5922 | } |
6693 | } |
5923 | 6694 | ||
5924 | /* |
6695 | /* |
5925 | * Initialize reference clocks when the driver loads |
6696 | * Initialize reference clocks when the driver loads |
5926 | */ |
6697 | */ |
5927 | void intel_init_pch_refclk(struct drm_device *dev) |
6698 | void intel_init_pch_refclk(struct drm_device *dev) |
5928 | { |
6699 | { |
5929 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
6700 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5930 | ironlake_init_pch_refclk(dev); |
6701 | ironlake_init_pch_refclk(dev); |
5931 | else if (HAS_PCH_LPT(dev)) |
6702 | else if (HAS_PCH_LPT(dev)) |
5932 | lpt_init_pch_refclk(dev); |
6703 | lpt_init_pch_refclk(dev); |
5933 | } |
6704 | } |
5934 | 6705 | ||
5935 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6706 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5936 | { |
6707 | { |
5937 | struct drm_device *dev = crtc->dev; |
6708 | struct drm_device *dev = crtc->dev; |
5938 | struct drm_i915_private *dev_priv = dev->dev_private; |
6709 | struct drm_i915_private *dev_priv = dev->dev_private; |
5939 | struct intel_encoder *encoder; |
6710 | struct intel_encoder *encoder; |
5940 | int num_connectors = 0; |
6711 | int num_connectors = 0; |
5941 | bool is_lvds = false; |
6712 | bool is_lvds = false; |
5942 | 6713 | ||
5943 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6714 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5944 | switch (encoder->type) { |
6715 | switch (encoder->type) { |
5945 | case INTEL_OUTPUT_LVDS: |
6716 | case INTEL_OUTPUT_LVDS: |
5946 | is_lvds = true; |
6717 | is_lvds = true; |
5947 | break; |
6718 | break; |
5948 | } |
6719 | } |
5949 | num_connectors++; |
6720 | num_connectors++; |
5950 | } |
6721 | } |
5951 | 6722 | ||
5952 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
6723 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5953 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
6724 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
5954 | dev_priv->vbt.lvds_ssc_freq); |
6725 | dev_priv->vbt.lvds_ssc_freq); |
5955 | return dev_priv->vbt.lvds_ssc_freq; |
6726 | return dev_priv->vbt.lvds_ssc_freq; |
5956 | } |
6727 | } |
5957 | 6728 | ||
5958 | return 120000; |
6729 | return 120000; |
5959 | } |
6730 | } |
5960 | 6731 | ||
5961 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
6732 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
5962 | { |
6733 | { |
5963 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
6734 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5965 | int pipe = intel_crtc->pipe; |
6736 | int pipe = intel_crtc->pipe; |
5966 | uint32_t val; |
6737 | uint32_t val; |
5967 | 6738 | ||
5968 | val = 0; |
6739 | val = 0; |
5969 | 6740 | ||
5970 | switch (intel_crtc->config.pipe_bpp) { |
6741 | switch (intel_crtc->config.pipe_bpp) { |
5971 | case 18: |
6742 | case 18: |
5972 | val |= PIPECONF_6BPC; |
6743 | val |= PIPECONF_6BPC; |
5973 | break; |
6744 | break; |
5974 | case 24: |
6745 | case 24: |
5975 | val |= PIPECONF_8BPC; |
6746 | val |= PIPECONF_8BPC; |
5976 | break; |
6747 | break; |
5977 | case 30: |
6748 | case 30: |
5978 | val |= PIPECONF_10BPC; |
6749 | val |= PIPECONF_10BPC; |
5979 | break; |
6750 | break; |
5980 | case 36: |
6751 | case 36: |
5981 | val |= PIPECONF_12BPC; |
6752 | val |= PIPECONF_12BPC; |
5982 | break; |
6753 | break; |
5983 | default: |
6754 | default: |
5984 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6755 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5985 | BUG(); |
6756 | BUG(); |
5986 | } |
6757 | } |
5987 | 6758 | ||
5988 | if (intel_crtc->config.dither) |
6759 | if (intel_crtc->config.dither) |
5989 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6760 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5990 | 6761 | ||
5991 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6762 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5992 | val |= PIPECONF_INTERLACED_ILK; |
6763 | val |= PIPECONF_INTERLACED_ILK; |
5993 | else |
6764 | else |
5994 | val |= PIPECONF_PROGRESSIVE; |
6765 | val |= PIPECONF_PROGRESSIVE; |
5995 | 6766 | ||
5996 | if (intel_crtc->config.limited_color_range) |
6767 | if (intel_crtc->config.limited_color_range) |
5997 | val |= PIPECONF_COLOR_RANGE_SELECT; |
6768 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5998 | 6769 | ||
5999 | I915_WRITE(PIPECONF(pipe), val); |
6770 | I915_WRITE(PIPECONF(pipe), val); |
6000 | POSTING_READ(PIPECONF(pipe)); |
6771 | POSTING_READ(PIPECONF(pipe)); |
6001 | } |
6772 | } |
6002 | 6773 | ||
6003 | /* |
6774 | /* |
6004 | * Set up the pipe CSC unit. |
6775 | * Set up the pipe CSC unit. |
6005 | * |
6776 | * |
6006 | * Currently only full range RGB to limited range RGB conversion |
6777 | * Currently only full range RGB to limited range RGB conversion |
6007 | * is supported, but eventually this should handle various |
6778 | * is supported, but eventually this should handle various |
6008 | * RGB<->YCbCr scenarios as well. |
6779 | * RGB<->YCbCr scenarios as well. |
6009 | */ |
6780 | */ |
6010 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
6781 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
6011 | { |
6782 | { |
6012 | struct drm_device *dev = crtc->dev; |
6783 | struct drm_device *dev = crtc->dev; |
6013 | struct drm_i915_private *dev_priv = dev->dev_private; |
6784 | struct drm_i915_private *dev_priv = dev->dev_private; |
6014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6015 | int pipe = intel_crtc->pipe; |
6786 | int pipe = intel_crtc->pipe; |
6016 | uint16_t coeff = 0x7800; /* 1.0 */ |
6787 | uint16_t coeff = 0x7800; /* 1.0 */ |
6017 | 6788 | ||
6018 | /* |
6789 | /* |
6019 | * TODO: Check what kind of values actually come out of the pipe |
6790 | * TODO: Check what kind of values actually come out of the pipe |
6020 | * with these coeff/postoff values and adjust to get the best |
6791 | * with these coeff/postoff values and adjust to get the best |
6021 | * accuracy. Perhaps we even need to take the bpc value into |
6792 | * accuracy. Perhaps we even need to take the bpc value into |
6022 | * consideration. |
6793 | * consideration. |
6023 | */ |
6794 | */ |
6024 | 6795 | ||
6025 | if (intel_crtc->config.limited_color_range) |
6796 | if (intel_crtc->config.limited_color_range) |
6026 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6797 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6027 | 6798 | ||
6028 | /* |
6799 | /* |
6029 | * GY/GU and RY/RU should be the other way around according |
6800 | * GY/GU and RY/RU should be the other way around according |
6030 | * to BSpec, but reality doesn't agree. Just set them up in |
6801 | * to BSpec, but reality doesn't agree. Just set them up in |
6031 | * a way that results in the correct picture. |
6802 | * a way that results in the correct picture. |
6032 | */ |
6803 | */ |
6033 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
6804 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
6034 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
6805 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
6035 | 6806 | ||
6036 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
6807 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
6037 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
6808 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
6038 | 6809 | ||
6039 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
6810 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
6040 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
6811 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
6041 | 6812 | ||
6042 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
6813 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
6043 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
6814 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
6044 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
6815 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
6045 | 6816 | ||
6046 | if (INTEL_INFO(dev)->gen > 6) { |
6817 | if (INTEL_INFO(dev)->gen > 6) { |
6047 | uint16_t postoff = 0; |
6818 | uint16_t postoff = 0; |
6048 | 6819 | ||
6049 | if (intel_crtc->config.limited_color_range) |
6820 | if (intel_crtc->config.limited_color_range) |
6050 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
6821 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
6051 | 6822 | ||
6052 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
6823 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
6053 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
6824 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
6054 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
6825 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
6055 | 6826 | ||
6056 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
6827 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
6057 | } else { |
6828 | } else { |
6058 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
6829 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
6059 | 6830 | ||
6060 | if (intel_crtc->config.limited_color_range) |
6831 | if (intel_crtc->config.limited_color_range) |
6061 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6832 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6062 | 6833 | ||
6063 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
6834 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
6064 | } |
6835 | } |
6065 | } |
6836 | } |
6066 | 6837 | ||
6067 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
6838 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
6068 | { |
6839 | { |
6069 | struct drm_device *dev = crtc->dev; |
6840 | struct drm_device *dev = crtc->dev; |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; |
6841 | struct drm_i915_private *dev_priv = dev->dev_private; |
6071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6072 | enum pipe pipe = intel_crtc->pipe; |
6843 | enum pipe pipe = intel_crtc->pipe; |
6073 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
6844 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
6074 | uint32_t val; |
6845 | uint32_t val; |
6075 | 6846 | ||
6076 | val = 0; |
6847 | val = 0; |
6077 | 6848 | ||
6078 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
6849 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
6079 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6850 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6080 | 6851 | ||
6081 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6852 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6082 | val |= PIPECONF_INTERLACED_ILK; |
6853 | val |= PIPECONF_INTERLACED_ILK; |
6083 | else |
6854 | else |
6084 | val |= PIPECONF_PROGRESSIVE; |
6855 | val |= PIPECONF_PROGRESSIVE; |
6085 | 6856 | ||
6086 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6857 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6087 | POSTING_READ(PIPECONF(cpu_transcoder)); |
6858 | POSTING_READ(PIPECONF(cpu_transcoder)); |
6088 | 6859 | ||
6089 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
6860 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
6090 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
6861 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
6091 | 6862 | ||
6092 | if (IS_BROADWELL(dev)) { |
6863 | if (IS_BROADWELL(dev)) { |
6093 | val = 0; |
6864 | val = 0; |
6094 | 6865 | ||
6095 | switch (intel_crtc->config.pipe_bpp) { |
6866 | switch (intel_crtc->config.pipe_bpp) { |
6096 | case 18: |
6867 | case 18: |
6097 | val |= PIPEMISC_DITHER_6_BPC; |
6868 | val |= PIPEMISC_DITHER_6_BPC; |
6098 | break; |
6869 | break; |
6099 | case 24: |
6870 | case 24: |
6100 | val |= PIPEMISC_DITHER_8_BPC; |
6871 | val |= PIPEMISC_DITHER_8_BPC; |
6101 | break; |
6872 | break; |
6102 | case 30: |
6873 | case 30: |
6103 | val |= PIPEMISC_DITHER_10_BPC; |
6874 | val |= PIPEMISC_DITHER_10_BPC; |
6104 | break; |
6875 | break; |
6105 | case 36: |
6876 | case 36: |
6106 | val |= PIPEMISC_DITHER_12_BPC; |
6877 | val |= PIPEMISC_DITHER_12_BPC; |
6107 | break; |
6878 | break; |
6108 | default: |
6879 | default: |
6109 | /* Case prevented by pipe_config_set_bpp. */ |
6880 | /* Case prevented by pipe_config_set_bpp. */ |
6110 | BUG(); |
6881 | BUG(); |
6111 | } |
6882 | } |
6112 | 6883 | ||
6113 | if (intel_crtc->config.dither) |
6884 | if (intel_crtc->config.dither) |
6114 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
6885 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
6115 | 6886 | ||
6116 | I915_WRITE(PIPEMISC(pipe), val); |
6887 | I915_WRITE(PIPEMISC(pipe), val); |
6117 | } |
6888 | } |
6118 | } |
6889 | } |
6119 | 6890 | ||
6120 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6891 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6121 | intel_clock_t *clock, |
6892 | intel_clock_t *clock, |
6122 | bool *has_reduced_clock, |
6893 | bool *has_reduced_clock, |
6123 | intel_clock_t *reduced_clock) |
6894 | intel_clock_t *reduced_clock) |
6124 | { |
6895 | { |
6125 | struct drm_device *dev = crtc->dev; |
6896 | struct drm_device *dev = crtc->dev; |
6126 | struct drm_i915_private *dev_priv = dev->dev_private; |
6897 | struct drm_i915_private *dev_priv = dev->dev_private; |
6127 | struct intel_encoder *intel_encoder; |
6898 | struct intel_encoder *intel_encoder; |
6128 | int refclk; |
6899 | int refclk; |
6129 | const intel_limit_t *limit; |
6900 | const intel_limit_t *limit; |
6130 | bool ret, is_lvds = false; |
6901 | bool ret, is_lvds = false; |
6131 | 6902 | ||
6132 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6903 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6133 | switch (intel_encoder->type) { |
6904 | switch (intel_encoder->type) { |
6134 | case INTEL_OUTPUT_LVDS: |
6905 | case INTEL_OUTPUT_LVDS: |
6135 | is_lvds = true; |
6906 | is_lvds = true; |
6136 | break; |
6907 | break; |
6137 | } |
6908 | } |
6138 | } |
6909 | } |
6139 | 6910 | ||
6140 | refclk = ironlake_get_refclk(crtc); |
6911 | refclk = ironlake_get_refclk(crtc); |
6141 | 6912 | ||
6142 | /* |
6913 | /* |
6143 | * Returns a set of divisors for the desired target clock with the given |
6914 | * Returns a set of divisors for the desired target clock with the given |
6144 | * refclk, or FALSE. The returned values represent the clock equation: |
6915 | * refclk, or FALSE. The returned values represent the clock equation: |
6145 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
6916 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
6146 | */ |
6917 | */ |
6147 | limit = intel_limit(crtc, refclk); |
6918 | limit = intel_limit(crtc, refclk); |
6148 | ret = dev_priv->display.find_dpll(limit, crtc, |
6919 | ret = dev_priv->display.find_dpll(limit, crtc, |
6149 | to_intel_crtc(crtc)->config.port_clock, |
6920 | to_intel_crtc(crtc)->config.port_clock, |
6150 | refclk, NULL, clock); |
6921 | refclk, NULL, clock); |
6151 | if (!ret) |
6922 | if (!ret) |
6152 | return false; |
6923 | return false; |
6153 | 6924 | ||
6154 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6925 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6155 | /* |
6926 | /* |
6156 | * Ensure we match the reduced clock's P to the target clock. |
6927 | * Ensure we match the reduced clock's P to the target clock. |
6157 | * If the clocks don't match, we can't switch the display clock |
6928 | * If the clocks don't match, we can't switch the display clock |
6158 | * by using the FP0/FP1. In such case we will disable the LVDS |
6929 | * by using the FP0/FP1. In such case we will disable the LVDS |
6159 | * downclock feature. |
6930 | * downclock feature. |
6160 | */ |
6931 | */ |
6161 | *has_reduced_clock = |
6932 | *has_reduced_clock = |
6162 | dev_priv->display.find_dpll(limit, crtc, |
6933 | dev_priv->display.find_dpll(limit, crtc, |
6163 | dev_priv->lvds_downclock, |
6934 | dev_priv->lvds_downclock, |
6164 | refclk, clock, |
6935 | refclk, clock, |
6165 | reduced_clock); |
6936 | reduced_clock); |
6166 | } |
6937 | } |
6167 | 6938 | ||
6168 | return true; |
6939 | return true; |
6169 | } |
6940 | } |
6170 | 6941 | ||
6171 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6942 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6172 | { |
6943 | { |
6173 | /* |
6944 | /* |
6174 | * Account for spread spectrum to avoid |
6945 | * Account for spread spectrum to avoid |
6175 | * oversubscribing the link. Max center spread |
6946 | * oversubscribing the link. Max center spread |
6176 | * is 2.5%; use 5% for safety's sake. |
6947 | * is 2.5%; use 5% for safety's sake. |
6177 | */ |
6948 | */ |
6178 | u32 bps = target_clock * bpp * 21 / 20; |
6949 | u32 bps = target_clock * bpp * 21 / 20; |
6179 | return bps / (link_bw * 8) + 1; |
6950 | return DIV_ROUND_UP(bps, link_bw * 8); |
6180 | } |
6951 | } |
6181 | 6952 | ||
6182 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6953 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6183 | { |
6954 | { |
6184 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
6955 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
6185 | } |
6956 | } |
6186 | 6957 | ||
6187 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
6958 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
6188 | u32 *fp, |
6959 | u32 *fp, |
6189 | intel_clock_t *reduced_clock, u32 *fp2) |
6960 | intel_clock_t *reduced_clock, u32 *fp2) |
6190 | { |
6961 | { |
6191 | struct drm_crtc *crtc = &intel_crtc->base; |
6962 | struct drm_crtc *crtc = &intel_crtc->base; |
6192 | struct drm_device *dev = crtc->dev; |
6963 | struct drm_device *dev = crtc->dev; |
6193 | struct drm_i915_private *dev_priv = dev->dev_private; |
6964 | struct drm_i915_private *dev_priv = dev->dev_private; |
6194 | struct intel_encoder *intel_encoder; |
6965 | struct intel_encoder *intel_encoder; |
6195 | uint32_t dpll; |
6966 | uint32_t dpll; |
6196 | int factor, num_connectors = 0; |
6967 | int factor, num_connectors = 0; |
6197 | bool is_lvds = false, is_sdvo = false; |
6968 | bool is_lvds = false, is_sdvo = false; |
6198 | 6969 | ||
6199 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6970 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6200 | switch (intel_encoder->type) { |
6971 | switch (intel_encoder->type) { |
6201 | case INTEL_OUTPUT_LVDS: |
6972 | case INTEL_OUTPUT_LVDS: |
6202 | is_lvds = true; |
6973 | is_lvds = true; |
6203 | break; |
6974 | break; |
6204 | case INTEL_OUTPUT_SDVO: |
6975 | case INTEL_OUTPUT_SDVO: |
6205 | case INTEL_OUTPUT_HDMI: |
6976 | case INTEL_OUTPUT_HDMI: |
6206 | is_sdvo = true; |
6977 | is_sdvo = true; |
6207 | break; |
6978 | break; |
6208 | } |
6979 | } |
6209 | 6980 | ||
6210 | num_connectors++; |
6981 | num_connectors++; |
6211 | } |
6982 | } |
6212 | 6983 | ||
6213 | /* Enable autotuning of the PLL clock (if permissible) */ |
6984 | /* Enable autotuning of the PLL clock (if permissible) */ |
6214 | factor = 21; |
6985 | factor = 21; |
6215 | if (is_lvds) { |
6986 | if (is_lvds) { |
6216 | if ((intel_panel_use_ssc(dev_priv) && |
6987 | if ((intel_panel_use_ssc(dev_priv) && |
6217 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6988 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6218 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
6989 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
6219 | factor = 25; |
6990 | factor = 25; |
6220 | } else if (intel_crtc->config.sdvo_tv_clock) |
6991 | } else if (intel_crtc->config.sdvo_tv_clock) |
6221 | factor = 20; |
6992 | factor = 20; |
6222 | 6993 | ||
6223 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
6994 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
6224 | *fp |= FP_CB_TUNE; |
6995 | *fp |= FP_CB_TUNE; |
6225 | 6996 | ||
6226 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6997 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6227 | *fp2 |= FP_CB_TUNE; |
6998 | *fp2 |= FP_CB_TUNE; |
6228 | 6999 | ||
6229 | dpll = 0; |
7000 | dpll = 0; |
6230 | 7001 | ||
6231 | if (is_lvds) |
7002 | if (is_lvds) |
6232 | dpll |= DPLLB_MODE_LVDS; |
7003 | dpll |= DPLLB_MODE_LVDS; |
6233 | else |
7004 | else |
6234 | dpll |= DPLLB_MODE_DAC_SERIAL; |
7005 | dpll |= DPLLB_MODE_DAC_SERIAL; |
6235 | 7006 | ||
6236 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
7007 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6237 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
7008 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
6238 | 7009 | ||
6239 | if (is_sdvo) |
7010 | if (is_sdvo) |
6240 | dpll |= DPLL_SDVO_HIGH_SPEED; |
7011 | dpll |= DPLL_SDVO_HIGH_SPEED; |
6241 | if (intel_crtc->config.has_dp_encoder) |
7012 | if (intel_crtc->config.has_dp_encoder) |
6242 | dpll |= DPLL_SDVO_HIGH_SPEED; |
7013 | dpll |= DPLL_SDVO_HIGH_SPEED; |
6243 | 7014 | ||
6244 | /* compute bitmask from p1 value */ |
7015 | /* compute bitmask from p1 value */ |
6245 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7016 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6246 | /* also FPA1 */ |
7017 | /* also FPA1 */ |
6247 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
7018 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6248 | 7019 | ||
6249 | switch (intel_crtc->config.dpll.p2) { |
7020 | switch (intel_crtc->config.dpll.p2) { |
6250 | case 5: |
7021 | case 5: |
6251 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
7022 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
6252 | break; |
7023 | break; |
6253 | case 7: |
7024 | case 7: |
6254 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
7025 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
6255 | break; |
7026 | break; |
6256 | case 10: |
7027 | case 10: |
6257 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
7028 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
6258 | break; |
7029 | break; |
6259 | case 14: |
7030 | case 14: |
6260 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
7031 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
6261 | break; |
7032 | break; |
6262 | } |
7033 | } |
6263 | 7034 | ||
6264 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7035 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6265 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7036 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6266 | else |
7037 | else |
6267 | dpll |= PLL_REF_INPUT_DREFCLK; |
7038 | dpll |= PLL_REF_INPUT_DREFCLK; |
6268 | 7039 | ||
6269 | return dpll | DPLL_VCO_ENABLE; |
7040 | return dpll | DPLL_VCO_ENABLE; |
6270 | } |
7041 | } |
6271 | 7042 | ||
6272 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
7043 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
6273 | int x, int y, |
7044 | int x, int y, |
6274 | struct drm_framebuffer *fb) |
7045 | struct drm_framebuffer *fb) |
6275 | { |
7046 | { |
6276 | struct drm_device *dev = crtc->dev; |
7047 | struct drm_device *dev = crtc->dev; |
6277 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6279 | int pipe = intel_crtc->pipe; |
- | |
6280 | int plane = intel_crtc->plane; |
- | |
6281 | int num_connectors = 0; |
7049 | int num_connectors = 0; |
6282 | intel_clock_t clock, reduced_clock; |
7050 | intel_clock_t clock, reduced_clock; |
6283 | u32 dpll = 0, fp = 0, fp2 = 0; |
7051 | u32 dpll = 0, fp = 0, fp2 = 0; |
6284 | bool ok, has_reduced_clock = false; |
7052 | bool ok, has_reduced_clock = false; |
6285 | bool is_lvds = false; |
7053 | bool is_lvds = false; |
6286 | struct intel_encoder *encoder; |
7054 | struct intel_encoder *encoder; |
6287 | struct intel_shared_dpll *pll; |
7055 | struct intel_shared_dpll *pll; |
6288 | int ret; |
- | |
6289 | 7056 | ||
6290 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
7057 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6291 | switch (encoder->type) { |
7058 | switch (encoder->type) { |
6292 | case INTEL_OUTPUT_LVDS: |
7059 | case INTEL_OUTPUT_LVDS: |
6293 | is_lvds = true; |
7060 | is_lvds = true; |
6294 | break; |
7061 | break; |
6295 | } |
7062 | } |
6296 | 7063 | ||
6297 | num_connectors++; |
7064 | num_connectors++; |
6298 | } |
7065 | } |
6299 | 7066 | ||
6300 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7067 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6301 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
7068 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
6302 | 7069 | ||
6303 | ok = ironlake_compute_clocks(crtc, &clock, |
7070 | ok = ironlake_compute_clocks(crtc, &clock, |
6304 | &has_reduced_clock, &reduced_clock); |
7071 | &has_reduced_clock, &reduced_clock); |
6305 | if (!ok && !intel_crtc->config.clock_set) { |
7072 | if (!ok && !intel_crtc->config.clock_set) { |
6306 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7073 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6307 | return -EINVAL; |
7074 | return -EINVAL; |
6308 | } |
7075 | } |
6309 | /* Compat-code for transition, will disappear. */ |
7076 | /* Compat-code for transition, will disappear. */ |
6310 | if (!intel_crtc->config.clock_set) { |
7077 | if (!intel_crtc->config.clock_set) { |
6311 | intel_crtc->config.dpll.n = clock.n; |
7078 | intel_crtc->config.dpll.n = clock.n; |
6312 | intel_crtc->config.dpll.m1 = clock.m1; |
7079 | intel_crtc->config.dpll.m1 = clock.m1; |
6313 | intel_crtc->config.dpll.m2 = clock.m2; |
7080 | intel_crtc->config.dpll.m2 = clock.m2; |
6314 | intel_crtc->config.dpll.p1 = clock.p1; |
7081 | intel_crtc->config.dpll.p1 = clock.p1; |
6315 | intel_crtc->config.dpll.p2 = clock.p2; |
7082 | intel_crtc->config.dpll.p2 = clock.p2; |
6316 | } |
7083 | } |
6317 | 7084 | ||
6318 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
7085 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
6319 | if (intel_crtc->config.has_pch_encoder) { |
7086 | if (intel_crtc->config.has_pch_encoder) { |
6320 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
7087 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
6321 | if (has_reduced_clock) |
7088 | if (has_reduced_clock) |
6322 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
7089 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
6323 | 7090 | ||
6324 | dpll = ironlake_compute_dpll(intel_crtc, |
7091 | dpll = ironlake_compute_dpll(intel_crtc, |
6325 | &fp, &reduced_clock, |
7092 | &fp, &reduced_clock, |
6326 | has_reduced_clock ? &fp2 : NULL); |
7093 | has_reduced_clock ? &fp2 : NULL); |
6327 | 7094 | ||
6328 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
7095 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
6329 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7096 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6330 | if (has_reduced_clock) |
7097 | if (has_reduced_clock) |
6331 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
7098 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
6332 | else |
7099 | else |
6333 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
7100 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
6334 | 7101 | ||
6335 | pll = intel_get_shared_dpll(intel_crtc); |
7102 | pll = intel_get_shared_dpll(intel_crtc); |
6336 | if (pll == NULL) { |
7103 | if (pll == NULL) { |
6337 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
7104 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6338 | pipe_name(pipe)); |
7105 | pipe_name(intel_crtc->pipe)); |
6339 | return -EINVAL; |
7106 | return -EINVAL; |
6340 | } |
7107 | } |
6341 | } else |
7108 | } else |
6342 | intel_put_shared_dpll(intel_crtc); |
7109 | intel_put_shared_dpll(intel_crtc); |
6343 | - | ||
6344 | if (intel_crtc->config.has_dp_encoder) |
- | |
6345 | intel_dp_set_m_n(intel_crtc); |
- | |
6346 | 7110 | ||
6347 | if (is_lvds && has_reduced_clock && i915_powersave) |
7111 | if (is_lvds && has_reduced_clock && i915.powersave) |
6348 | intel_crtc->lowfreq_avail = true; |
7112 | intel_crtc->lowfreq_avail = true; |
6349 | else |
7113 | else |
6350 | intel_crtc->lowfreq_avail = false; |
7114 | intel_crtc->lowfreq_avail = false; |
6351 | - | ||
6352 | intel_set_pipe_timings(intel_crtc); |
- | |
6353 | - | ||
6354 | if (intel_crtc->config.has_pch_encoder) { |
- | |
6355 | intel_cpu_transcoder_set_m_n(intel_crtc, |
- | |
6356 | &intel_crtc->config.fdi_m_n); |
- | |
6357 | } |
- | |
6358 | - | ||
6359 | ironlake_set_pipeconf(crtc); |
- | |
6360 | - | ||
6361 | /* Set up the display plane register */ |
- | |
6362 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
- | |
6363 | POSTING_READ(DSPCNTR(plane)); |
- | |
6364 | - | ||
6365 | ret = intel_pipe_set_base(crtc, x, y, fb); |
- | |
6366 | 7115 | ||
6367 | return ret; |
7116 | return 0; |
6368 | } |
7117 | } |
6369 | 7118 | ||
6370 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7119 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6371 | struct intel_link_m_n *m_n) |
7120 | struct intel_link_m_n *m_n) |
6372 | { |
7121 | { |
6373 | struct drm_device *dev = crtc->base.dev; |
7122 | struct drm_device *dev = crtc->base.dev; |
6374 | struct drm_i915_private *dev_priv = dev->dev_private; |
7123 | struct drm_i915_private *dev_priv = dev->dev_private; |
6375 | enum pipe pipe = crtc->pipe; |
7124 | enum pipe pipe = crtc->pipe; |
6376 | 7125 | ||
6377 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
7126 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
6378 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
7127 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
6379 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
7128 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
6380 | & ~TU_SIZE_MASK; |
7129 | & ~TU_SIZE_MASK; |
6381 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
7130 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
6382 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
7131 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
6383 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
7132 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6384 | } |
7133 | } |
6385 | 7134 | ||
6386 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
7135 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
6387 | enum transcoder transcoder, |
7136 | enum transcoder transcoder, |
6388 | struct intel_link_m_n *m_n) |
7137 | struct intel_link_m_n *m_n) |
6389 | { |
7138 | { |
6390 | struct drm_device *dev = crtc->base.dev; |
7139 | struct drm_device *dev = crtc->base.dev; |
6391 | struct drm_i915_private *dev_priv = dev->dev_private; |
7140 | struct drm_i915_private *dev_priv = dev->dev_private; |
6392 | enum pipe pipe = crtc->pipe; |
7141 | enum pipe pipe = crtc->pipe; |
6393 | 7142 | ||
6394 | if (INTEL_INFO(dev)->gen >= 5) { |
7143 | if (INTEL_INFO(dev)->gen >= 5) { |
6395 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
7144 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
6396 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
7145 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
6397 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
7146 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
6398 | & ~TU_SIZE_MASK; |
7147 | & ~TU_SIZE_MASK; |
6399 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
7148 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
6400 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
7149 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
6401 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
7150 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6402 | } else { |
7151 | } else { |
6403 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
7152 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
6404 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
7153 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
6405 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
7154 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
6406 | & ~TU_SIZE_MASK; |
7155 | & ~TU_SIZE_MASK; |
6407 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
7156 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
6408 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
7157 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
6409 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
7158 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6410 | } |
7159 | } |
6411 | } |
7160 | } |
6412 | 7161 | ||
6413 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
7162 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
6414 | struct intel_crtc_config *pipe_config) |
7163 | struct intel_crtc_config *pipe_config) |
6415 | { |
7164 | { |
6416 | if (crtc->config.has_pch_encoder) |
7165 | if (crtc->config.has_pch_encoder) |
6417 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
7166 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
6418 | else |
7167 | else |
6419 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
7168 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
6420 | &pipe_config->dp_m_n); |
7169 | &pipe_config->dp_m_n); |
6421 | } |
7170 | } |
6422 | 7171 | ||
6423 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7172 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6424 | struct intel_crtc_config *pipe_config) |
7173 | struct intel_crtc_config *pipe_config) |
6425 | { |
7174 | { |
6426 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
7175 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
6427 | &pipe_config->fdi_m_n); |
7176 | &pipe_config->fdi_m_n); |
6428 | } |
7177 | } |
6429 | 7178 | ||
6430 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7179 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6431 | struct intel_crtc_config *pipe_config) |
7180 | struct intel_crtc_config *pipe_config) |
6432 | { |
7181 | { |
6433 | struct drm_device *dev = crtc->base.dev; |
7182 | struct drm_device *dev = crtc->base.dev; |
6434 | struct drm_i915_private *dev_priv = dev->dev_private; |
7183 | struct drm_i915_private *dev_priv = dev->dev_private; |
6435 | uint32_t tmp; |
7184 | uint32_t tmp; |
6436 | 7185 | ||
6437 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
7186 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
6438 | 7187 | ||
6439 | if (tmp & PF_ENABLE) { |
7188 | if (tmp & PF_ENABLE) { |
6440 | pipe_config->pch_pfit.enabled = true; |
7189 | pipe_config->pch_pfit.enabled = true; |
6441 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7190 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6442 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
7191 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
6443 | 7192 | ||
6444 | /* We currently do not free assignements of panel fitters on |
7193 | /* We currently do not free assignements of panel fitters on |
6445 | * ivb/hsw (since we don't use the higher upscaling modes which |
7194 | * ivb/hsw (since we don't use the higher upscaling modes which |
6446 | * differentiates them) so just WARN about this case for now. */ |
7195 | * differentiates them) so just WARN about this case for now. */ |
6447 | if (IS_GEN7(dev)) { |
7196 | if (IS_GEN7(dev)) { |
6448 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
7197 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
6449 | PF_PIPE_SEL_IVB(crtc->pipe)); |
7198 | PF_PIPE_SEL_IVB(crtc->pipe)); |
6450 | } |
7199 | } |
6451 | } |
7200 | } |
6452 | } |
7201 | } |
- | 7202 | ||
- | 7203 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
|
- | 7204 | struct intel_plane_config *plane_config) |
|
- | 7205 | { |
|
- | 7206 | struct drm_device *dev = crtc->base.dev; |
|
- | 7207 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7208 | u32 val, base, offset; |
|
- | 7209 | int pipe = crtc->pipe, plane = crtc->plane; |
|
- | 7210 | int fourcc, pixel_format; |
|
- | 7211 | int aligned_height; |
|
- | 7212 | ||
- | 7213 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
|
- | 7214 | if (!crtc->base.primary->fb) { |
|
- | 7215 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
|
- | 7216 | return; |
|
- | 7217 | } |
|
- | 7218 | ||
- | 7219 | val = I915_READ(DSPCNTR(plane)); |
|
- | 7220 | ||
- | 7221 | if (INTEL_INFO(dev)->gen >= 4) |
|
- | 7222 | if (val & DISPPLANE_TILED) |
|
- | 7223 | plane_config->tiled = true; |
|
- | 7224 | ||
- | 7225 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
|
- | 7226 | fourcc = intel_format_to_fourcc(pixel_format); |
|
- | 7227 | crtc->base.primary->fb->pixel_format = fourcc; |
|
- | 7228 | crtc->base.primary->fb->bits_per_pixel = |
|
- | 7229 | drm_format_plane_cpp(fourcc, 0) * 8; |
|
- | 7230 | ||
- | 7231 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
|
- | 7232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
|
- | 7233 | offset = I915_READ(DSPOFFSET(plane)); |
|
- | 7234 | } else { |
|
- | 7235 | if (plane_config->tiled) |
|
- | 7236 | offset = I915_READ(DSPTILEOFF(plane)); |
|
- | 7237 | else |
|
- | 7238 | offset = I915_READ(DSPLINOFF(plane)); |
|
- | 7239 | } |
|
- | 7240 | plane_config->base = base; |
|
- | 7241 | ||
- | 7242 | val = I915_READ(PIPESRC(pipe)); |
|
- | 7243 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
|
- | 7244 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
|
- | 7245 | ||
- | 7246 | val = I915_READ(DSPSTRIDE(pipe)); |
|
- | 7247 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
|
- | 7248 | ||
- | 7249 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
|
- | 7250 | plane_config->tiled); |
|
- | 7251 | ||
- | 7252 | plane_config->size = 16*1024*1024; |
|
- | 7253 | ||
- | 7254 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
|
- | 7255 | pipe, plane, crtc->base.primary->fb->width, |
|
- | 7256 | crtc->base.primary->fb->height, |
|
- | 7257 | crtc->base.primary->fb->bits_per_pixel, base, |
|
- | 7258 | crtc->base.primary->fb->pitches[0], |
|
- | 7259 | plane_config->size); |
|
- | 7260 | } |
|
6453 | 7261 | ||
6454 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7262 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6455 | struct intel_crtc_config *pipe_config) |
7263 | struct intel_crtc_config *pipe_config) |
6456 | { |
7264 | { |
6457 | struct drm_device *dev = crtc->base.dev; |
7265 | struct drm_device *dev = crtc->base.dev; |
6458 | struct drm_i915_private *dev_priv = dev->dev_private; |
7266 | struct drm_i915_private *dev_priv = dev->dev_private; |
6459 | uint32_t tmp; |
7267 | uint32_t tmp; |
- | 7268 | ||
- | 7269 | if (!intel_display_power_enabled(dev_priv, |
|
- | 7270 | POWER_DOMAIN_PIPE(crtc->pipe))) |
|
- | 7271 | return false; |
|
6460 | 7272 | ||
6461 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
7273 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6462 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7274 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6463 | 7275 | ||
6464 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7276 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6465 | if (!(tmp & PIPECONF_ENABLE)) |
7277 | if (!(tmp & PIPECONF_ENABLE)) |
6466 | return false; |
7278 | return false; |
6467 | 7279 | ||
6468 | switch (tmp & PIPECONF_BPC_MASK) { |
7280 | switch (tmp & PIPECONF_BPC_MASK) { |
6469 | case PIPECONF_6BPC: |
7281 | case PIPECONF_6BPC: |
6470 | pipe_config->pipe_bpp = 18; |
7282 | pipe_config->pipe_bpp = 18; |
6471 | break; |
7283 | break; |
6472 | case PIPECONF_8BPC: |
7284 | case PIPECONF_8BPC: |
6473 | pipe_config->pipe_bpp = 24; |
7285 | pipe_config->pipe_bpp = 24; |
6474 | break; |
7286 | break; |
6475 | case PIPECONF_10BPC: |
7287 | case PIPECONF_10BPC: |
6476 | pipe_config->pipe_bpp = 30; |
7288 | pipe_config->pipe_bpp = 30; |
6477 | break; |
7289 | break; |
6478 | case PIPECONF_12BPC: |
7290 | case PIPECONF_12BPC: |
6479 | pipe_config->pipe_bpp = 36; |
7291 | pipe_config->pipe_bpp = 36; |
6480 | break; |
7292 | break; |
6481 | default: |
7293 | default: |
6482 | break; |
7294 | break; |
6483 | } |
7295 | } |
- | 7296 | ||
- | 7297 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
|
- | 7298 | pipe_config->limited_color_range = true; |
|
6484 | 7299 | ||
6485 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
7300 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
6486 | struct intel_shared_dpll *pll; |
7301 | struct intel_shared_dpll *pll; |
6487 | 7302 | ||
6488 | pipe_config->has_pch_encoder = true; |
7303 | pipe_config->has_pch_encoder = true; |
6489 | 7304 | ||
6490 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7305 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6491 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
7306 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6492 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
7307 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6493 | 7308 | ||
6494 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
7309 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6495 | 7310 | ||
6496 | if (HAS_PCH_IBX(dev_priv->dev)) { |
7311 | if (HAS_PCH_IBX(dev_priv->dev)) { |
6497 | pipe_config->shared_dpll = |
7312 | pipe_config->shared_dpll = |
6498 | (enum intel_dpll_id) crtc->pipe; |
7313 | (enum intel_dpll_id) crtc->pipe; |
6499 | } else { |
7314 | } else { |
6500 | tmp = I915_READ(PCH_DPLL_SEL); |
7315 | tmp = I915_READ(PCH_DPLL_SEL); |
6501 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
7316 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
6502 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
7317 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
6503 | else |
7318 | else |
6504 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
7319 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
6505 | } |
7320 | } |
6506 | 7321 | ||
6507 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
7322 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
6508 | 7323 | ||
6509 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
7324 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
6510 | &pipe_config->dpll_hw_state)); |
7325 | &pipe_config->dpll_hw_state)); |
6511 | 7326 | ||
6512 | tmp = pipe_config->dpll_hw_state.dpll; |
7327 | tmp = pipe_config->dpll_hw_state.dpll; |
6513 | pipe_config->pixel_multiplier = |
7328 | pipe_config->pixel_multiplier = |
6514 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
7329 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
6515 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
7330 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
6516 | 7331 | ||
6517 | ironlake_pch_clock_get(crtc, pipe_config); |
7332 | ironlake_pch_clock_get(crtc, pipe_config); |
6518 | } else { |
7333 | } else { |
6519 | pipe_config->pixel_multiplier = 1; |
7334 | pipe_config->pixel_multiplier = 1; |
6520 | } |
7335 | } |
6521 | 7336 | ||
6522 | intel_get_pipe_timings(crtc, pipe_config); |
7337 | intel_get_pipe_timings(crtc, pipe_config); |
6523 | 7338 | ||
6524 | ironlake_get_pfit_config(crtc, pipe_config); |
7339 | ironlake_get_pfit_config(crtc, pipe_config); |
6525 | 7340 | ||
6526 | return true; |
7341 | return true; |
6527 | } |
7342 | } |
6528 | 7343 | ||
6529 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7344 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6530 | { |
7345 | { |
6531 | struct drm_device *dev = dev_priv->dev; |
7346 | struct drm_device *dev = dev_priv->dev; |
6532 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
- | |
6533 | struct intel_crtc *crtc; |
7347 | struct intel_crtc *crtc; |
6534 | unsigned long irqflags; |
- | |
6535 | uint32_t val; |
- | |
6536 | 7348 | ||
6537 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
7349 | for_each_intel_crtc(dev, crtc) |
6538 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
7350 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
6539 | pipe_name(crtc->pipe)); |
7351 | pipe_name(crtc->pipe)); |
6540 | 7352 | ||
6541 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
7353 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
6542 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
7354 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
6543 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
7355 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
6544 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
7356 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
6545 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7357 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
6546 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
7358 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
6547 | "CPU PWM1 enabled\n"); |
7359 | "CPU PWM1 enabled\n"); |
- | 7360 | if (IS_HASWELL(dev)) |
|
6548 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
7361 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
6549 | "CPU PWM2 enabled\n"); |
7362 | "CPU PWM2 enabled\n"); |
6550 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7363 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
6551 | "PCH PWM1 enabled\n"); |
7364 | "PCH PWM1 enabled\n"); |
6552 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
7365 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
6553 | "Utility pin enabled\n"); |
7366 | "Utility pin enabled\n"); |
6554 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
7367 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
- | 7368 | ||
- | 7369 | /* |
|
- | 7370 | * In theory we can still leave IRQs enabled, as long as only the HPD |
|
- | 7371 | * interrupts remain enabled. We used to check for that, but since it's |
|
- | 7372 | * gen-specific and since we only disable LCPLL after we fully disable |
|
- | 7373 | * the interrupts, the check below should be enough. |
|
6555 | 7374 | */ |
|
- | 7375 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
|
- | 7376 | } |
|
- | 7377 | ||
- | 7378 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
|
- | 7379 | { |
|
- | 7380 | struct drm_device *dev = dev_priv->dev; |
|
- | 7381 | ||
6556 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7382 | if (IS_HASWELL(dev)) |
- | 7383 | return I915_READ(D_COMP_HSW); |
|
6557 | val = I915_READ(DEIMR); |
7384 | else |
- | 7385 | return I915_READ(D_COMP_BDW); |
|
- | 7386 | } |
|
6558 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
7387 | |
- | 7388 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
|
- | 7389 | { |
|
- | 7390 | struct drm_device *dev = dev_priv->dev; |
|
6559 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
7391 | |
- | 7392 | if (IS_HASWELL(dev)) { |
|
6560 | val = I915_READ(SDEIMR); |
7393 | mutex_lock(&dev_priv->rps.hw_lock); |
- | 7394 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
|
6561 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
7395 | val)) |
6562 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
7396 | DRM_ERROR("Failed to write to D_COMP\n"); |
- | 7397 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 7398 | } else { |
|
- | 7399 | I915_WRITE(D_COMP_BDW, val); |
|
- | 7400 | POSTING_READ(D_COMP_BDW); |
|
6563 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
7401 | } |
6564 | } |
7402 | } |
6565 | 7403 | ||
6566 | /* |
7404 | /* |
6567 | * This function implements pieces of two sequences from BSpec: |
7405 | * This function implements pieces of two sequences from BSpec: |
6568 | * - Sequence for display software to disable LCPLL |
7406 | * - Sequence for display software to disable LCPLL |
6569 | * - Sequence for display software to allow package C8+ |
7407 | * - Sequence for display software to allow package C8+ |
6570 | * The steps implemented here are just the steps that actually touch the LCPLL |
7408 | * The steps implemented here are just the steps that actually touch the LCPLL |
6571 | * register. Callers should take care of disabling all the display engine |
7409 | * register. Callers should take care of disabling all the display engine |
6572 | * functions, doing the mode unset, fixing interrupts, etc. |
7410 | * functions, doing the mode unset, fixing interrupts, etc. |
6573 | */ |
7411 | */ |
6574 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7412 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6575 | bool switch_to_fclk, bool allow_power_down) |
7413 | bool switch_to_fclk, bool allow_power_down) |
6576 | { |
7414 | { |
6577 | uint32_t val; |
7415 | uint32_t val; |
6578 | 7416 | ||
6579 | assert_can_disable_lcpll(dev_priv); |
7417 | assert_can_disable_lcpll(dev_priv); |
6580 | 7418 | ||
6581 | val = I915_READ(LCPLL_CTL); |
7419 | val = I915_READ(LCPLL_CTL); |
6582 | 7420 | ||
6583 | if (switch_to_fclk) { |
7421 | if (switch_to_fclk) { |
6584 | val |= LCPLL_CD_SOURCE_FCLK; |
7422 | val |= LCPLL_CD_SOURCE_FCLK; |
6585 | I915_WRITE(LCPLL_CTL, val); |
7423 | I915_WRITE(LCPLL_CTL, val); |
6586 | 7424 | ||
6587 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
7425 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
6588 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
7426 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
6589 | DRM_ERROR("Switching to FCLK failed\n"); |
7427 | DRM_ERROR("Switching to FCLK failed\n"); |
6590 | 7428 | ||
6591 | val = I915_READ(LCPLL_CTL); |
7429 | val = I915_READ(LCPLL_CTL); |
6592 | } |
7430 | } |
6593 | 7431 | ||
6594 | val |= LCPLL_PLL_DISABLE; |
7432 | val |= LCPLL_PLL_DISABLE; |
6595 | I915_WRITE(LCPLL_CTL, val); |
7433 | I915_WRITE(LCPLL_CTL, val); |
6596 | POSTING_READ(LCPLL_CTL); |
7434 | POSTING_READ(LCPLL_CTL); |
6597 | 7435 | ||
6598 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
7436 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6599 | DRM_ERROR("LCPLL still locked\n"); |
7437 | DRM_ERROR("LCPLL still locked\n"); |
6600 | 7438 | ||
6601 | val = I915_READ(D_COMP); |
7439 | val = hsw_read_dcomp(dev_priv); |
6602 | val |= D_COMP_COMP_DISABLE; |
7440 | val |= D_COMP_COMP_DISABLE; |
6603 | mutex_lock(&dev_priv->rps.hw_lock); |
- | |
6604 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
- | |
6605 | DRM_ERROR("Failed to disable D_COMP\n"); |
- | |
6606 | mutex_unlock(&dev_priv->rps.hw_lock); |
- | |
6607 | POSTING_READ(D_COMP); |
7441 | hsw_write_dcomp(dev_priv, val); |
6608 | delay(1); |
7442 | ndelay(100); |
- | 7443 | ||
6609 | 7444 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
|
6610 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
7445 | 1)) |
6611 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7446 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
6612 | 7447 | ||
6613 | if (allow_power_down) { |
7448 | if (allow_power_down) { |
6614 | val = I915_READ(LCPLL_CTL); |
7449 | val = I915_READ(LCPLL_CTL); |
6615 | val |= LCPLL_POWER_DOWN_ALLOW; |
7450 | val |= LCPLL_POWER_DOWN_ALLOW; |
6616 | I915_WRITE(LCPLL_CTL, val); |
7451 | I915_WRITE(LCPLL_CTL, val); |
6617 | POSTING_READ(LCPLL_CTL); |
7452 | POSTING_READ(LCPLL_CTL); |
6618 | } |
7453 | } |
6619 | } |
7454 | } |
6620 | 7455 | ||
6621 | /* |
7456 | /* |
6622 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
7457 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6623 | * source. |
7458 | * source. |
6624 | */ |
7459 | */ |
6625 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
7460 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6626 | { |
7461 | { |
6627 | uint32_t val; |
7462 | uint32_t val; |
- | 7463 | unsigned long irqflags; |
|
6628 | 7464 | ||
6629 | val = I915_READ(LCPLL_CTL); |
7465 | val = I915_READ(LCPLL_CTL); |
6630 | 7466 | ||
6631 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
7467 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
6632 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
7468 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6633 | return; |
7469 | return; |
- | 7470 | ||
6634 | 7471 | /* |
|
- | 7472 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
|
- | 7473 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
|
- | 7474 | * |
|
- | 7475 | * The other problem is that hsw_restore_lcpll() is called as part of |
|
- | 7476 | * the runtime PM resume sequence, so we can't just call |
|
- | 7477 | * gen6_gt_force_wake_get() because that function calls |
|
- | 7478 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount |
|
- | 7479 | * while we are on the resume sequence. So to solve this problem we have |
|
6635 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
7480 | * to call special forcewake code that doesn't touch runtime PM and |
- | 7481 | * doesn't enable the forcewake delayed work. |
|
- | 7482 | */ |
|
- | 7483 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
6636 | * we'll hang the machine! */ |
7484 | if (dev_priv->uncore.forcewake_count++ == 0) |
- | 7485 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
|
6637 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
7486 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
6638 | 7487 | ||
6639 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7488 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6640 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
7489 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6641 | I915_WRITE(LCPLL_CTL, val); |
7490 | I915_WRITE(LCPLL_CTL, val); |
6642 | POSTING_READ(LCPLL_CTL); |
7491 | POSTING_READ(LCPLL_CTL); |
6643 | } |
7492 | } |
6644 | 7493 | ||
6645 | val = I915_READ(D_COMP); |
7494 | val = hsw_read_dcomp(dev_priv); |
6646 | val |= D_COMP_COMP_FORCE; |
7495 | val |= D_COMP_COMP_FORCE; |
6647 | val &= ~D_COMP_COMP_DISABLE; |
7496 | val &= ~D_COMP_COMP_DISABLE; |
6648 | mutex_lock(&dev_priv->rps.hw_lock); |
- | |
6649 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
- | |
6650 | DRM_ERROR("Failed to enable D_COMP\n"); |
- | |
6651 | mutex_unlock(&dev_priv->rps.hw_lock); |
- | |
6652 | POSTING_READ(D_COMP); |
7497 | hsw_write_dcomp(dev_priv, val); |
6653 | 7498 | ||
6654 | val = I915_READ(LCPLL_CTL); |
7499 | val = I915_READ(LCPLL_CTL); |
6655 | val &= ~LCPLL_PLL_DISABLE; |
7500 | val &= ~LCPLL_PLL_DISABLE; |
6656 | I915_WRITE(LCPLL_CTL, val); |
7501 | I915_WRITE(LCPLL_CTL, val); |
6657 | 7502 | ||
6658 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
7503 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
6659 | DRM_ERROR("LCPLL not locked yet\n"); |
7504 | DRM_ERROR("LCPLL not locked yet\n"); |
6660 | 7505 | ||
6661 | if (val & LCPLL_CD_SOURCE_FCLK) { |
7506 | if (val & LCPLL_CD_SOURCE_FCLK) { |
6662 | val = I915_READ(LCPLL_CTL); |
7507 | val = I915_READ(LCPLL_CTL); |
6663 | val &= ~LCPLL_CD_SOURCE_FCLK; |
7508 | val &= ~LCPLL_CD_SOURCE_FCLK; |
6664 | I915_WRITE(LCPLL_CTL, val); |
7509 | I915_WRITE(LCPLL_CTL, val); |
6665 | 7510 | ||
6666 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
7511 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6667 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
7512 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6668 | DRM_ERROR("Switching back to LCPLL failed\n"); |
7513 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6669 | } |
7514 | } |
- | 7515 | ||
- | 7516 | /* See the big comment above. */ |
|
- | 7517 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
6670 | 7518 | if (--dev_priv->uncore.forcewake_count == 0) |
|
- | 7519 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
|
6671 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
7520 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
- | 7521 | } |
|
- | 7522 | ||
- | 7523 | /* |
|
- | 7524 | * Package states C8 and deeper are really deep PC states that can only be |
|
- | 7525 | * reached when all the devices on the system allow it, so even if the graphics |
|
- | 7526 | * device allows PC8+, it doesn't mean the system will actually get to these |
|
- | 7527 | * states. Our driver only allows PC8+ when going into runtime PM. |
|
- | 7528 | * |
|
- | 7529 | * The requirements for PC8+ are that all the outputs are disabled, the power |
|
- | 7530 | * well is disabled and most interrupts are disabled, and these are also |
|
- | 7531 | * requirements for runtime PM. When these conditions are met, we manually do |
|
- | 7532 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
|
- | 7533 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
|
- | 7534 | * hang the machine. |
|
- | 7535 | * |
|
- | 7536 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
|
- | 7537 | * the state of some registers, so when we come back from PC8+ we need to |
|
- | 7538 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
|
- | 7539 | * need to take care of the registers kept by RC6. Notice that this happens even |
|
- | 7540 | * if we don't put the device in PCI D3 state (which is what currently happens |
|
- | 7541 | * because of the runtime PM support). |
|
- | 7542 | * |
|
- | 7543 | * For more, read "Display Sequences for Package C8" on the hardware |
|
6672 | } |
7544 | * documentation. |
6673 | 7545 | */ |
|
6674 | void hsw_enable_pc8_work(struct work_struct *__work) |
- | |
6675 | { |
- | |
6676 | struct drm_i915_private *dev_priv = |
- | |
6677 | container_of(to_delayed_work(__work), struct drm_i915_private, |
7546 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
6678 | pc8.enable_work); |
7547 | { |
6679 | struct drm_device *dev = dev_priv->dev; |
7548 | struct drm_device *dev = dev_priv->dev; |
6680 | uint32_t val; |
7549 | uint32_t val; |
6681 | - | ||
6682 | WARN_ON(!HAS_PC8(dev)); |
- | |
6683 | - | ||
6684 | if (dev_priv->pc8.enabled) |
- | |
6685 | return; |
- | |
6686 | 7550 | ||
6687 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
- | |
6688 | - | ||
6689 | dev_priv->pc8.enabled = true; |
7551 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6690 | 7552 | ||
6691 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7553 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6692 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7554 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6693 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
7555 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6694 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7556 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6695 | } |
7557 | } |
6696 | 7558 | ||
6697 | lpt_disable_clkout_dp(dev); |
7559 | lpt_disable_clkout_dp(dev); |
6698 | hsw_pc8_disable_interrupts(dev); |
- | |
6699 | hsw_disable_lcpll(dev_priv, true, true); |
7560 | hsw_disable_lcpll(dev_priv, true, true); |
6700 | - | ||
6701 | intel_runtime_pm_put(dev_priv); |
- | |
6702 | } |
7561 | } |
6703 | - | ||
6704 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6705 | { |
- | |
6706 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
- | |
6707 | WARN(dev_priv->pc8.disable_count < 1, |
- | |
6708 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
- | |
6709 | - | ||
6710 | dev_priv->pc8.disable_count--; |
- | |
6711 | if (dev_priv->pc8.disable_count != 0) |
- | |
6712 | return; |
- | |
6713 | - | ||
6714 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
- | |
6715 | msecs_to_jiffies(i915_pc8_timeout)); |
- | |
6716 | } |
- | |
6717 | 7562 | ||
6718 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
7563 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
6719 | { |
7564 | { |
6720 | struct drm_device *dev = dev_priv->dev; |
7565 | struct drm_device *dev = dev_priv->dev; |
6721 | uint32_t val; |
7566 | uint32_t val; |
6722 | - | ||
6723 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
- | |
6724 | WARN(dev_priv->pc8.disable_count < 0, |
- | |
6725 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
- | |
6726 | - | ||
6727 | dev_priv->pc8.disable_count++; |
- | |
6728 | if (dev_priv->pc8.disable_count != 1) |
- | |
6729 | return; |
- | |
6730 | - | ||
6731 | WARN_ON(!HAS_PC8(dev)); |
- | |
6732 | - | ||
6733 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
- | |
6734 | if (!dev_priv->pc8.enabled) |
- | |
6735 | return; |
- | |
6736 | 7567 | ||
6737 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
- | |
6738 | - | ||
6739 | intel_runtime_pm_get(dev_priv); |
7568 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6740 | - | ||
6741 | hsw_restore_lcpll(dev_priv); |
7569 | |
6742 | hsw_pc8_restore_interrupts(dev); |
7570 | hsw_restore_lcpll(dev_priv); |
6743 | lpt_init_pch_refclk(dev); |
7571 | lpt_init_pch_refclk(dev); |
6744 | 7572 | ||
6745 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7573 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6746 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7574 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6747 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
7575 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6748 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7576 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6749 | } |
7577 | } |
6750 | 7578 | ||
6751 | intel_prepare_ddi(dev); |
7579 | intel_prepare_ddi(dev); |
6752 | i915_gem_init_swizzling(dev); |
- | |
6753 | mutex_lock(&dev_priv->rps.hw_lock); |
- | |
6754 | gen6_update_ring_freq(dev); |
- | |
6755 | mutex_unlock(&dev_priv->rps.hw_lock); |
- | |
6756 | dev_priv->pc8.enabled = false; |
- | |
6757 | } |
7580 | } |
6758 | 7581 | ||
6759 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
7582 | static void snb_modeset_global_resources(struct drm_device *dev) |
6760 | { |
- | |
6761 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6762 | return; |
- | |
6763 | - | ||
6764 | mutex_lock(&dev_priv->pc8.lock); |
7583 | { |
6765 | __hsw_enable_package_c8(dev_priv); |
- | |
6766 | mutex_unlock(&dev_priv->pc8.lock); |
7584 | modeset_update_crtc_power_domains(dev); |
6767 | } |
7585 | } |
6768 | 7586 | ||
6769 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6770 | { |
- | |
6771 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6772 | return; |
- | |
6773 | 7587 | static void haswell_modeset_global_resources(struct drm_device *dev) |
|
6774 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6775 | __hsw_disable_package_c8(dev_priv); |
7588 | { |
6776 | mutex_unlock(&dev_priv->pc8.lock); |
7589 | modeset_update_crtc_power_domains(dev); |
- | 7590 | } |
|
- | 7591 | ||
6777 | } |
7592 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6778 | - | ||
6779 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
7593 | int x, int y, |
6780 | { |
- | |
6781 | struct drm_device *dev = dev_priv->dev; |
- | |
6782 | struct intel_crtc *crtc; |
7594 | struct drm_framebuffer *fb) |
6783 | uint32_t val; |
7595 | { |
6784 | - | ||
6785 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
- | |
6786 | if (crtc->base.enabled) |
- | |
6787 | return false; |
- | |
6788 | - | ||
6789 | /* This case is still possible since we have the i915.disable_power_well |
- | |
6790 | * parameter and also the KVMr or something else might be requesting the |
7596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6791 | * power well. */ |
- | |
6792 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
7597 | |
6793 | if (val != 0) { |
7598 | if (!intel_ddi_pll_select(intel_crtc)) |
6794 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
- | |
6795 | return false; |
7599 | return -EINVAL; |
6796 | } |
- | |
6797 | - | ||
6798 | return true; |
- | |
6799 | } |
7600 | |
6800 | 7601 | intel_crtc->lowfreq_avail = false; |
|
- | 7602 | ||
6801 | /* Since we're called from modeset_global_resources there's no way to |
7603 | return 0; |
6802 | * symmetrically increase and decrease the refcount, so we use |
- | |
6803 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
- | |
6804 | * or not. |
- | |
6805 | */ |
- | |
6806 | static void hsw_update_package_c8(struct drm_device *dev) |
- | |
6807 | { |
- | |
6808 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6809 | bool allow; |
- | |
6810 | 7604 | } |
|
6811 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6812 | return; |
- | |
6813 | - | ||
6814 | if (!i915_enable_pc8) |
- | |
6815 | return; |
7605 | |
6816 | - | ||
6817 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6818 | - | ||
6819 | allow = hsw_can_enable_package_c8(dev_priv); |
- | |
6820 | - | ||
6821 | if (allow == dev_priv->pc8.requirements_met) |
- | |
6822 | goto done; |
- | |
6823 | - | ||
6824 | dev_priv->pc8.requirements_met = allow; |
- | |
6825 | - | ||
6826 | if (allow) |
- | |
6827 | __hsw_enable_package_c8(dev_priv); |
- | |
6828 | else |
- | |
6829 | __hsw_disable_package_c8(dev_priv); |
- | |
6830 | - | ||
6831 | done: |
- | |
6832 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6833 | } |
- | |
6834 | - | ||
6835 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
- | |
6836 | { |
- | |
6837 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6838 | return; |
- | |
6839 | - | ||
6840 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6841 | if (!dev_priv->pc8.gpu_idle) { |
- | |
6842 | dev_priv->pc8.gpu_idle = true; |
- | |
6843 | __hsw_enable_package_c8(dev_priv); |
- | |
6844 | } |
7606 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
6845 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6846 | } |
- | |
6847 | - | ||
6848 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
- | |
6849 | { |
- | |
6850 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6851 | return; |
- | |
6852 | - | ||
6853 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6854 | if (dev_priv->pc8.gpu_idle) { |
- | |
6855 | dev_priv->pc8.gpu_idle = false; |
- | |
6856 | __hsw_disable_package_c8(dev_priv); |
- | |
6857 | } |
7607 | struct intel_crtc_config *pipe_config) |
6858 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6859 | } |
- | |
6860 | - | ||
6861 | #define for_each_power_domain(domain, mask) \ |
- | |
6862 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
7608 | { |
6863 | if ((1 << (domain)) & (mask)) |
- | |
6864 | - | ||
6865 | static unsigned long get_pipe_power_domains(struct drm_device *dev, |
- | |
6866 | enum pipe pipe, bool pfit_enabled) |
7609 | struct drm_device *dev = crtc->base.dev; |
- | 7610 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7611 | struct intel_shared_dpll *pll; |
|
- | 7612 | enum port port; |
|
6867 | { |
7613 | uint32_t tmp; |
- | 7614 | ||
- | 7615 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
|
- | 7616 | ||
6868 | unsigned long mask; |
7617 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
6869 | enum transcoder transcoder; |
- | |
6870 | - | ||
6871 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
- | |
6872 | - | ||
6873 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
7618 | |
6874 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
- | |
6875 | if (pfit_enabled) |
- | |
6876 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
- | |
6877 | - | ||
6878 | return mask; |
- | |
6879 | } |
7619 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
- | 7620 | ||
6880 | 7621 | switch (pipe_config->ddi_pll_sel) { |
|
6881 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
7622 | case PORT_CLK_SEL_WRPLL1: |
6882 | { |
- | |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6884 | - | ||
6885 | if (dev_priv->power_domains.init_power_on == enable) |
- | |
6886 | return; |
- | |
6887 | 7623 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; |
|
6888 | if (enable) |
7624 | break; |
6889 | intel_display_power_get(dev, POWER_DOMAIN_INIT); |
7625 | case PORT_CLK_SEL_WRPLL2: |
- | 7626 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
|
6890 | else |
7627 | break; |
6891 | intel_display_power_put(dev, POWER_DOMAIN_INIT); |
7628 | } |
6892 | - | ||
6893 | dev_priv->power_domains.init_power_on = enable; |
- | |
6894 | } |
- | |
6895 | - | ||
6896 | static void modeset_update_power_wells(struct drm_device *dev) |
- | |
6897 | { |
- | |
6898 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
- | |
6899 | struct intel_crtc *crtc; |
- | |
6900 | - | ||
6901 | /* |
- | |
6902 | * First get all needed power domains, then put all unneeded, to avoid |
- | |
6903 | * any unnecessary toggling of the power wells. |
- | |
6904 | */ |
- | |
6905 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
- | |
6906 | enum intel_display_power_domain domain; |
- | |
6907 | - | ||
6908 | if (!crtc->base.enabled) |
- | |
6909 | continue; |
- | |
6910 | - | ||
6911 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
- | |
6912 | crtc->pipe, |
- | |
6913 | crtc->config.pch_pfit.enabled); |
- | |
6914 | - | ||
6915 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
- | |
6916 | intel_display_power_get(dev, domain); |
- | |
6917 | } |
- | |
6918 | - | ||
6919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
- | |
6920 | enum intel_display_power_domain domain; |
- | |
6921 | - | ||
6922 | for_each_power_domain(domain, crtc->enabled_power_domains) |
- | |
6923 | intel_display_power_put(dev, domain); |
- | |
6924 | - | ||
6925 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
- | |
6926 | } |
- | |
6927 | - | ||
6928 | intel_display_set_init_power(dev, false); |
- | |
6929 | } |
- | |
6930 | - | ||
6931 | static void haswell_modeset_global_resources(struct drm_device *dev) |
- | |
6932 | { |
- | |
6933 | modeset_update_power_wells(dev); |
- | |
6934 | hsw_update_package_c8(dev); |
- | |
6935 | } |
- | |
6936 | - | ||
6937 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
7629 | |
6938 | int x, int y, |
- | |
6939 | struct drm_framebuffer *fb) |
- | |
6940 | { |
- | |
- | 7630 | if (pipe_config->shared_dpll >= 0) { |
|
- | 7631 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
|
6941 | struct drm_device *dev = crtc->dev; |
7632 | |
6942 | struct drm_i915_private *dev_priv = dev->dev_private; |
7633 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
6943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
6944 | int plane = intel_crtc->plane; |
- | |
6945 | int ret; |
7634 | &pipe_config->dpll_hw_state)); |
6946 | - | ||
6947 | if (!intel_ddi_pll_select(intel_crtc)) |
- | |
6948 | return -EINVAL; |
- | |
6949 | intel_ddi_pll_enable(intel_crtc); |
- | |
6950 | - | ||
6951 | if (intel_crtc->config.has_dp_encoder) |
- | |
6952 | intel_dp_set_m_n(intel_crtc); |
- | |
6953 | - | ||
6954 | intel_crtc->lowfreq_avail = false; |
- | |
6955 | - | ||
6956 | intel_set_pipe_timings(intel_crtc); |
- | |
6957 | - | ||
6958 | if (intel_crtc->config.has_pch_encoder) { |
7635 | } |
6959 | intel_cpu_transcoder_set_m_n(intel_crtc, |
7636 | |
6960 | &intel_crtc->config.fdi_m_n); |
7637 | /* |
6961 | } |
7638 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
6962 | 7639 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
|
6963 | haswell_set_pipeconf(crtc); |
7640 | * the PCH transcoder is on. |
6964 | 7641 | */ |
|
6965 | intel_set_pipe_csc(crtc); |
7642 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
6966 | 7643 | pipe_config->has_pch_encoder = true; |
|
6967 | /* Set up the display plane register */ |
7644 | |
6968 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
7645 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6969 | POSTING_READ(DSPCNTR(plane)); |
7646 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6970 | 7647 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
|
6971 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7648 | |
6972 | 7649 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
|
6973 | return ret; |
7650 | } |
6974 | } |
7651 | } |
6975 | 7652 | ||
6976 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7653 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6977 | struct intel_crtc_config *pipe_config) |
7654 | struct intel_crtc_config *pipe_config) |
6978 | { |
7655 | { |
6979 | struct drm_device *dev = crtc->base.dev; |
7656 | struct drm_device *dev = crtc->base.dev; |
6980 | struct drm_i915_private *dev_priv = dev->dev_private; |
7657 | struct drm_i915_private *dev_priv = dev->dev_private; |
6981 | enum intel_display_power_domain pfit_domain; |
7658 | enum intel_display_power_domain pfit_domain; |
6982 | uint32_t tmp; |
7659 | uint32_t tmp; |
- | 7660 | ||
- | 7661 | if (!intel_display_power_enabled(dev_priv, |
|
- | 7662 | POWER_DOMAIN_PIPE(crtc->pipe))) |
|
- | 7663 | return false; |
|
6983 | 7664 | ||
6984 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
7665 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6985 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7666 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6986 | 7667 | ||
6987 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7668 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6988 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
7669 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
6989 | enum pipe trans_edp_pipe; |
7670 | enum pipe trans_edp_pipe; |
6990 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
7671 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
6991 | default: |
7672 | default: |
6992 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
7673 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
6993 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
7674 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
6994 | case TRANS_DDI_EDP_INPUT_A_ON: |
7675 | case TRANS_DDI_EDP_INPUT_A_ON: |
6995 | trans_edp_pipe = PIPE_A; |
7676 | trans_edp_pipe = PIPE_A; |
6996 | break; |
7677 | break; |
6997 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
7678 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
6998 | trans_edp_pipe = PIPE_B; |
7679 | trans_edp_pipe = PIPE_B; |
6999 | break; |
7680 | break; |
7000 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
7681 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
7001 | trans_edp_pipe = PIPE_C; |
7682 | trans_edp_pipe = PIPE_C; |
7002 | break; |
7683 | break; |
7003 | } |
7684 | } |
7004 | 7685 | ||
7005 | if (trans_edp_pipe == crtc->pipe) |
7686 | if (trans_edp_pipe == crtc->pipe) |
7006 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
7687 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
7007 | } |
7688 | } |
7008 | 7689 | ||
7009 | if (!intel_display_power_enabled(dev, |
7690 | if (!intel_display_power_enabled(dev_priv, |
7010 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
7691 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
7011 | return false; |
7692 | return false; |
7012 | 7693 | ||
7013 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
7694 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
7014 | if (!(tmp & PIPECONF_ENABLE)) |
7695 | if (!(tmp & PIPECONF_ENABLE)) |
7015 | return false; |
7696 | return false; |
7016 | - | ||
7017 | /* |
- | |
7018 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
- | |
7019 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
- | |
7020 | * the PCH transcoder is on. |
- | |
7021 | */ |
- | |
7022 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
- | |
7023 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
- | |
7024 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
- | |
7025 | pipe_config->has_pch_encoder = true; |
- | |
7026 | - | ||
7027 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
- | |
7028 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
- | |
7029 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
- | |
7030 | 7697 | ||
7031 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
- | |
7032 | } |
7698 | haswell_get_ddi_port_state(crtc, pipe_config); |
7033 | 7699 | ||
7034 | intel_get_pipe_timings(crtc, pipe_config); |
7700 | intel_get_pipe_timings(crtc, pipe_config); |
7035 | 7701 | ||
7036 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7702 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7037 | if (intel_display_power_enabled(dev, pfit_domain)) |
7703 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
7038 | ironlake_get_pfit_config(crtc, pipe_config); |
7704 | ironlake_get_pfit_config(crtc, pipe_config); |
7039 | 7705 | ||
7040 | if (IS_HASWELL(dev)) |
7706 | if (IS_HASWELL(dev)) |
7041 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
7707 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
7042 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
7708 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
7043 | 7709 | ||
7044 | pipe_config->pixel_multiplier = 1; |
7710 | pipe_config->pixel_multiplier = 1; |
7045 | 7711 | ||
7046 | return true; |
7712 | return true; |
7047 | } |
7713 | } |
7048 | - | ||
7049 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
- | |
7050 | int x, int y, |
- | |
7051 | struct drm_framebuffer *fb) |
- | |
7052 | { |
- | |
7053 | struct drm_device *dev = crtc->dev; |
- | |
7054 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
7055 | struct intel_encoder *encoder; |
- | |
7056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7057 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
- | |
7058 | int pipe = intel_crtc->pipe; |
- | |
7059 | int ret; |
- | |
7060 | - | ||
7061 | drm_vblank_pre_modeset(dev, pipe); |
- | |
7062 | - | ||
7063 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
- | |
7064 | - | ||
7065 | drm_vblank_post_modeset(dev, pipe); |
- | |
7066 | - | ||
7067 | if (ret != 0) |
- | |
7068 | return ret; |
- | |
7069 | - | ||
7070 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
- | |
7071 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
- | |
7072 | encoder->base.base.id, |
- | |
7073 | drm_get_encoder_name(&encoder->base), |
- | |
7074 | mode->base.id, mode->name); |
- | |
7075 | encoder->mode_set(encoder); |
- | |
7076 | } |
- | |
7077 | - | ||
7078 | return 0; |
- | |
7079 | } |
- | |
7080 | 7714 | ||
7081 | static struct { |
7715 | static struct { |
7082 | int clock; |
7716 | int clock; |
7083 | u32 config; |
7717 | u32 config; |
7084 | } hdmi_audio_clock[] = { |
7718 | } hdmi_audio_clock[] = { |
7085 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7719 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7086 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
7720 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
7087 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
7721 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
7088 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7722 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7089 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
7723 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
7090 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
7724 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
7091 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
7725 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
7092 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
7726 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
7093 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7727 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7094 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
7728 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
7095 | }; |
7729 | }; |
7096 | 7730 | ||
7097 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
7731 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
7098 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
7732 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
7099 | { |
7733 | { |
7100 | int i; |
7734 | int i; |
7101 | 7735 | ||
7102 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
7736 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
7103 | if (mode->clock == hdmi_audio_clock[i].clock) |
7737 | if (mode->clock == hdmi_audio_clock[i].clock) |
7104 | break; |
7738 | break; |
7105 | } |
7739 | } |
7106 | 7740 | ||
7107 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
7741 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
7108 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
7742 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
7109 | i = 1; |
7743 | i = 1; |
7110 | } |
7744 | } |
7111 | 7745 | ||
7112 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
7746 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
7113 | hdmi_audio_clock[i].clock, |
7747 | hdmi_audio_clock[i].clock, |
7114 | hdmi_audio_clock[i].config); |
7748 | hdmi_audio_clock[i].config); |
7115 | 7749 | ||
7116 | return hdmi_audio_clock[i].config; |
7750 | return hdmi_audio_clock[i].config; |
7117 | } |
7751 | } |
7118 | 7752 | ||
7119 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7753 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7120 | int reg_eldv, uint32_t bits_eldv, |
7754 | int reg_eldv, uint32_t bits_eldv, |
7121 | int reg_elda, uint32_t bits_elda, |
7755 | int reg_elda, uint32_t bits_elda, |
7122 | int reg_edid) |
7756 | int reg_edid) |
7123 | { |
7757 | { |
7124 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7758 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7125 | uint8_t *eld = connector->eld; |
7759 | uint8_t *eld = connector->eld; |
7126 | uint32_t i; |
7760 | uint32_t i; |
7127 | 7761 | ||
7128 | i = I915_READ(reg_eldv); |
7762 | i = I915_READ(reg_eldv); |
7129 | i &= bits_eldv; |
7763 | i &= bits_eldv; |
7130 | 7764 | ||
7131 | if (!eld[0]) |
7765 | if (!eld[0]) |
7132 | return !i; |
7766 | return !i; |
7133 | 7767 | ||
7134 | if (!i) |
7768 | if (!i) |
7135 | return false; |
7769 | return false; |
7136 | 7770 | ||
7137 | i = I915_READ(reg_elda); |
7771 | i = I915_READ(reg_elda); |
7138 | i &= ~bits_elda; |
7772 | i &= ~bits_elda; |
7139 | I915_WRITE(reg_elda, i); |
7773 | I915_WRITE(reg_elda, i); |
7140 | 7774 | ||
7141 | for (i = 0; i < eld[2]; i++) |
7775 | for (i = 0; i < eld[2]; i++) |
7142 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
7776 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
7143 | return false; |
7777 | return false; |
7144 | 7778 | ||
7145 | return true; |
7779 | return true; |
7146 | } |
7780 | } |
7147 | 7781 | ||
7148 | static void g4x_write_eld(struct drm_connector *connector, |
7782 | static void g4x_write_eld(struct drm_connector *connector, |
7149 | struct drm_crtc *crtc, |
7783 | struct drm_crtc *crtc, |
7150 | struct drm_display_mode *mode) |
7784 | struct drm_display_mode *mode) |
7151 | { |
7785 | { |
7152 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7786 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7153 | uint8_t *eld = connector->eld; |
7787 | uint8_t *eld = connector->eld; |
7154 | uint32_t eldv; |
7788 | uint32_t eldv; |
7155 | uint32_t len; |
7789 | uint32_t len; |
7156 | uint32_t i; |
7790 | uint32_t i; |
7157 | 7791 | ||
7158 | i = I915_READ(G4X_AUD_VID_DID); |
7792 | i = I915_READ(G4X_AUD_VID_DID); |
7159 | 7793 | ||
7160 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
7794 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
7161 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
7795 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
7162 | else |
7796 | else |
7163 | eldv = G4X_ELDV_DEVCTG; |
7797 | eldv = G4X_ELDV_DEVCTG; |
7164 | 7798 | ||
7165 | if (intel_eld_uptodate(connector, |
7799 | if (intel_eld_uptodate(connector, |
7166 | G4X_AUD_CNTL_ST, eldv, |
7800 | G4X_AUD_CNTL_ST, eldv, |
7167 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
7801 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
7168 | G4X_HDMIW_HDMIEDID)) |
7802 | G4X_HDMIW_HDMIEDID)) |
7169 | return; |
7803 | return; |
7170 | 7804 | ||
7171 | i = I915_READ(G4X_AUD_CNTL_ST); |
7805 | i = I915_READ(G4X_AUD_CNTL_ST); |
7172 | i &= ~(eldv | G4X_ELD_ADDR); |
7806 | i &= ~(eldv | G4X_ELD_ADDR); |
7173 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
7807 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
7174 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7808 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7175 | 7809 | ||
7176 | if (!eld[0]) |
7810 | if (!eld[0]) |
7177 | return; |
7811 | return; |
7178 | 7812 | ||
7179 | len = min_t(uint8_t, eld[2], len); |
7813 | len = min_t(uint8_t, eld[2], len); |
7180 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7814 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7181 | for (i = 0; i < len; i++) |
7815 | for (i = 0; i < len; i++) |
7182 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
7816 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
7183 | 7817 | ||
7184 | i = I915_READ(G4X_AUD_CNTL_ST); |
7818 | i = I915_READ(G4X_AUD_CNTL_ST); |
7185 | i |= eldv; |
7819 | i |= eldv; |
7186 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7820 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7187 | } |
7821 | } |
7188 | 7822 | ||
7189 | static void haswell_write_eld(struct drm_connector *connector, |
7823 | static void haswell_write_eld(struct drm_connector *connector, |
7190 | struct drm_crtc *crtc, |
7824 | struct drm_crtc *crtc, |
7191 | struct drm_display_mode *mode) |
7825 | struct drm_display_mode *mode) |
7192 | { |
7826 | { |
7193 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7827 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7194 | uint8_t *eld = connector->eld; |
7828 | uint8_t *eld = connector->eld; |
7195 | struct drm_device *dev = crtc->dev; |
- | |
7196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7197 | uint32_t eldv; |
7829 | uint32_t eldv; |
7198 | uint32_t i; |
7830 | uint32_t i; |
7199 | int len; |
7831 | int len; |
7200 | int pipe = to_intel_crtc(crtc)->pipe; |
7832 | int pipe = to_intel_crtc(crtc)->pipe; |
7201 | int tmp; |
7833 | int tmp; |
7202 | 7834 | ||
7203 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
7835 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
7204 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
7836 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
7205 | int aud_config = HSW_AUD_CFG(pipe); |
7837 | int aud_config = HSW_AUD_CFG(pipe); |
7206 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
7838 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
7207 | - | ||
7208 | - | ||
7209 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
- | |
7210 | 7839 | ||
7211 | /* Audio output enable */ |
7840 | /* Audio output enable */ |
7212 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
7841 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
7213 | tmp = I915_READ(aud_cntrl_st2); |
7842 | tmp = I915_READ(aud_cntrl_st2); |
7214 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
7843 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
7215 | I915_WRITE(aud_cntrl_st2, tmp); |
7844 | I915_WRITE(aud_cntrl_st2, tmp); |
- | 7845 | POSTING_READ(aud_cntrl_st2); |
|
7216 | - | ||
7217 | /* Wait for 1 vertical blank */ |
7846 | |
7218 | intel_wait_for_vblank(dev, pipe); |
7847 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
7219 | 7848 | ||
7220 | /* Set ELD valid state */ |
7849 | /* Set ELD valid state */ |
7221 | tmp = I915_READ(aud_cntrl_st2); |
7850 | tmp = I915_READ(aud_cntrl_st2); |
7222 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
7851 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
7223 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7852 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7224 | I915_WRITE(aud_cntrl_st2, tmp); |
7853 | I915_WRITE(aud_cntrl_st2, tmp); |
7225 | tmp = I915_READ(aud_cntrl_st2); |
7854 | tmp = I915_READ(aud_cntrl_st2); |
7226 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
7855 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
7227 | 7856 | ||
7228 | /* Enable HDMI mode */ |
7857 | /* Enable HDMI mode */ |
7229 | tmp = I915_READ(aud_config); |
7858 | tmp = I915_READ(aud_config); |
7230 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
7859 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
7231 | /* clear N_programing_enable and N_value_index */ |
7860 | /* clear N_programing_enable and N_value_index */ |
7232 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
7861 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
7233 | I915_WRITE(aud_config, tmp); |
7862 | I915_WRITE(aud_config, tmp); |
7234 | 7863 | ||
7235 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7864 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7236 | 7865 | ||
7237 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
7866 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
7238 | intel_crtc->eld_vld = true; |
- | |
7239 | 7867 | ||
7240 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7868 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7241 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7869 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7242 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7870 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7243 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7871 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7244 | } else { |
7872 | } else { |
7245 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7873 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7246 | } |
7874 | } |
7247 | 7875 | ||
7248 | if (intel_eld_uptodate(connector, |
7876 | if (intel_eld_uptodate(connector, |
7249 | aud_cntrl_st2, eldv, |
7877 | aud_cntrl_st2, eldv, |
7250 | aud_cntl_st, IBX_ELD_ADDRESS, |
7878 | aud_cntl_st, IBX_ELD_ADDRESS, |
7251 | hdmiw_hdmiedid)) |
7879 | hdmiw_hdmiedid)) |
7252 | return; |
7880 | return; |
7253 | 7881 | ||
7254 | i = I915_READ(aud_cntrl_st2); |
7882 | i = I915_READ(aud_cntrl_st2); |
7255 | i &= ~eldv; |
7883 | i &= ~eldv; |
7256 | I915_WRITE(aud_cntrl_st2, i); |
7884 | I915_WRITE(aud_cntrl_st2, i); |
7257 | 7885 | ||
7258 | if (!eld[0]) |
7886 | if (!eld[0]) |
7259 | return; |
7887 | return; |
7260 | 7888 | ||
7261 | i = I915_READ(aud_cntl_st); |
7889 | i = I915_READ(aud_cntl_st); |
7262 | i &= ~IBX_ELD_ADDRESS; |
7890 | i &= ~IBX_ELD_ADDRESS; |
7263 | I915_WRITE(aud_cntl_st, i); |
7891 | I915_WRITE(aud_cntl_st, i); |
7264 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
7892 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
7265 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
7893 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
7266 | 7894 | ||
7267 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7895 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7268 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7896 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7269 | for (i = 0; i < len; i++) |
7897 | for (i = 0; i < len; i++) |
7270 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7898 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7271 | 7899 | ||
7272 | i = I915_READ(aud_cntrl_st2); |
7900 | i = I915_READ(aud_cntrl_st2); |
7273 | i |= eldv; |
7901 | i |= eldv; |
7274 | I915_WRITE(aud_cntrl_st2, i); |
7902 | I915_WRITE(aud_cntrl_st2, i); |
7275 | 7903 | ||
7276 | } |
7904 | } |
7277 | 7905 | ||
7278 | static void ironlake_write_eld(struct drm_connector *connector, |
7906 | static void ironlake_write_eld(struct drm_connector *connector, |
7279 | struct drm_crtc *crtc, |
7907 | struct drm_crtc *crtc, |
7280 | struct drm_display_mode *mode) |
7908 | struct drm_display_mode *mode) |
7281 | { |
7909 | { |
7282 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7910 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7283 | uint8_t *eld = connector->eld; |
7911 | uint8_t *eld = connector->eld; |
7284 | uint32_t eldv; |
7912 | uint32_t eldv; |
7285 | uint32_t i; |
7913 | uint32_t i; |
7286 | int len; |
7914 | int len; |
7287 | int hdmiw_hdmiedid; |
7915 | int hdmiw_hdmiedid; |
7288 | int aud_config; |
7916 | int aud_config; |
7289 | int aud_cntl_st; |
7917 | int aud_cntl_st; |
7290 | int aud_cntrl_st2; |
7918 | int aud_cntrl_st2; |
7291 | int pipe = to_intel_crtc(crtc)->pipe; |
7919 | int pipe = to_intel_crtc(crtc)->pipe; |
7292 | 7920 | ||
7293 | if (HAS_PCH_IBX(connector->dev)) { |
7921 | if (HAS_PCH_IBX(connector->dev)) { |
7294 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7922 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7295 | aud_config = IBX_AUD_CFG(pipe); |
7923 | aud_config = IBX_AUD_CFG(pipe); |
7296 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
7924 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
7297 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
7925 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
7298 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7926 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7299 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
7927 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
7300 | aud_config = VLV_AUD_CFG(pipe); |
7928 | aud_config = VLV_AUD_CFG(pipe); |
7301 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
7929 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
7302 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
7930 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
7303 | } else { |
7931 | } else { |
7304 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7932 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7305 | aud_config = CPT_AUD_CFG(pipe); |
7933 | aud_config = CPT_AUD_CFG(pipe); |
7306 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
7934 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
7307 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
7935 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
7308 | } |
7936 | } |
7309 | 7937 | ||
7310 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7938 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7311 | 7939 | ||
7312 | if (IS_VALLEYVIEW(connector->dev)) { |
7940 | if (IS_VALLEYVIEW(connector->dev)) { |
7313 | struct intel_encoder *intel_encoder; |
7941 | struct intel_encoder *intel_encoder; |
7314 | struct intel_digital_port *intel_dig_port; |
7942 | struct intel_digital_port *intel_dig_port; |
7315 | 7943 | ||
7316 | intel_encoder = intel_attached_encoder(connector); |
7944 | intel_encoder = intel_attached_encoder(connector); |
7317 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
7945 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
7318 | i = intel_dig_port->port; |
7946 | i = intel_dig_port->port; |
7319 | } else { |
7947 | } else { |
7320 | i = I915_READ(aud_cntl_st); |
7948 | i = I915_READ(aud_cntl_st); |
7321 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
7949 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
7322 | /* DIP_Port_Select, 0x1 = PortB */ |
7950 | /* DIP_Port_Select, 0x1 = PortB */ |
7323 | } |
7951 | } |
7324 | 7952 | ||
7325 | if (!i) { |
7953 | if (!i) { |
7326 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
7954 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
7327 | /* operate blindly on all ports */ |
7955 | /* operate blindly on all ports */ |
7328 | eldv = IBX_ELD_VALIDB; |
7956 | eldv = IBX_ELD_VALIDB; |
7329 | eldv |= IBX_ELD_VALIDB << 4; |
7957 | eldv |= IBX_ELD_VALIDB << 4; |
7330 | eldv |= IBX_ELD_VALIDB << 8; |
7958 | eldv |= IBX_ELD_VALIDB << 8; |
7331 | } else { |
7959 | } else { |
7332 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
7960 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
7333 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
7961 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
7334 | } |
7962 | } |
7335 | 7963 | ||
7336 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7964 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7337 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7965 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7338 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7966 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7339 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7967 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7340 | } else { |
7968 | } else { |
7341 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7969 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7342 | } |
7970 | } |
7343 | 7971 | ||
7344 | if (intel_eld_uptodate(connector, |
7972 | if (intel_eld_uptodate(connector, |
7345 | aud_cntrl_st2, eldv, |
7973 | aud_cntrl_st2, eldv, |
7346 | aud_cntl_st, IBX_ELD_ADDRESS, |
7974 | aud_cntl_st, IBX_ELD_ADDRESS, |
7347 | hdmiw_hdmiedid)) |
7975 | hdmiw_hdmiedid)) |
7348 | return; |
7976 | return; |
7349 | 7977 | ||
7350 | i = I915_READ(aud_cntrl_st2); |
7978 | i = I915_READ(aud_cntrl_st2); |
7351 | i &= ~eldv; |
7979 | i &= ~eldv; |
7352 | I915_WRITE(aud_cntrl_st2, i); |
7980 | I915_WRITE(aud_cntrl_st2, i); |
7353 | 7981 | ||
7354 | if (!eld[0]) |
7982 | if (!eld[0]) |
7355 | return; |
7983 | return; |
7356 | 7984 | ||
7357 | i = I915_READ(aud_cntl_st); |
7985 | i = I915_READ(aud_cntl_st); |
7358 | i &= ~IBX_ELD_ADDRESS; |
7986 | i &= ~IBX_ELD_ADDRESS; |
7359 | I915_WRITE(aud_cntl_st, i); |
7987 | I915_WRITE(aud_cntl_st, i); |
7360 | 7988 | ||
7361 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7989 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7362 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7990 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
7363 | for (i = 0; i < len; i++) |
7991 | for (i = 0; i < len; i++) |
7364 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7992 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7365 | 7993 | ||
7366 | i = I915_READ(aud_cntrl_st2); |
7994 | i = I915_READ(aud_cntrl_st2); |
7367 | i |= eldv; |
7995 | i |= eldv; |
7368 | I915_WRITE(aud_cntrl_st2, i); |
7996 | I915_WRITE(aud_cntrl_st2, i); |
7369 | } |
7997 | } |
7370 | 7998 | ||
7371 | void intel_write_eld(struct drm_encoder *encoder, |
7999 | void intel_write_eld(struct drm_encoder *encoder, |
7372 | struct drm_display_mode *mode) |
8000 | struct drm_display_mode *mode) |
7373 | { |
8001 | { |
7374 | struct drm_crtc *crtc = encoder->crtc; |
8002 | struct drm_crtc *crtc = encoder->crtc; |
7375 | struct drm_connector *connector; |
8003 | struct drm_connector *connector; |
7376 | struct drm_device *dev = encoder->dev; |
8004 | struct drm_device *dev = encoder->dev; |
7377 | struct drm_i915_private *dev_priv = dev->dev_private; |
8005 | struct drm_i915_private *dev_priv = dev->dev_private; |
7378 | 8006 | ||
7379 | connector = drm_select_eld(encoder, mode); |
8007 | connector = drm_select_eld(encoder, mode); |
7380 | if (!connector) |
8008 | if (!connector) |
7381 | return; |
8009 | return; |
7382 | 8010 | ||
7383 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8011 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7384 | connector->base.id, |
8012 | connector->base.id, |
7385 | drm_get_connector_name(connector), |
8013 | connector->name, |
7386 | connector->encoder->base.id, |
8014 | connector->encoder->base.id, |
7387 | drm_get_encoder_name(connector->encoder)); |
8015 | connector->encoder->name); |
7388 | 8016 | ||
7389 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
8017 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
7390 | 8018 | ||
7391 | if (dev_priv->display.write_eld) |
8019 | if (dev_priv->display.write_eld) |
7392 | dev_priv->display.write_eld(connector, crtc, mode); |
8020 | dev_priv->display.write_eld(connector, crtc, mode); |
7393 | } |
8021 | } |
7394 | 8022 | ||
7395 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8023 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7396 | { |
8024 | { |
7397 | struct drm_device *dev = crtc->dev; |
8025 | struct drm_device *dev = crtc->dev; |
7398 | struct drm_i915_private *dev_priv = dev->dev_private; |
8026 | struct drm_i915_private *dev_priv = dev->dev_private; |
7399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7400 | bool visible = base != 0; |
- | |
7401 | u32 cntl; |
8028 | uint32_t cntl; |
7402 | 8029 | ||
7403 | if (intel_crtc->cursor_visible == visible) |
- | |
7404 | return; |
- | |
7405 | - | ||
7406 | cntl = I915_READ(_CURACNTR); |
- | |
7407 | if (visible) { |
8030 | if (base != intel_crtc->cursor_base) { |
7408 | /* On these chipsets we can only modify the base whilst |
8031 | /* On these chipsets we can only modify the base whilst |
7409 | * the cursor is disabled. |
8032 | * the cursor is disabled. |
7410 | */ |
8033 | */ |
- | 8034 | if (intel_crtc->cursor_cntl) { |
|
- | 8035 | I915_WRITE(_CURACNTR, 0); |
|
- | 8036 | POSTING_READ(_CURACNTR); |
|
- | 8037 | intel_crtc->cursor_cntl = 0; |
|
- | 8038 | } |
|
- | 8039 | ||
7411 | I915_WRITE(_CURABASE, base); |
8040 | I915_WRITE(_CURABASE, base); |
- | 8041 | POSTING_READ(_CURABASE); |
|
- | 8042 | } |
|
7412 | - | ||
7413 | cntl &= ~(CURSOR_FORMAT_MASK); |
8043 | |
- | 8044 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
|
- | 8045 | cntl = 0; |
|
7414 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
8046 | if (base) |
7415 | cntl |= CURSOR_ENABLE | |
8047 | cntl = (CURSOR_ENABLE | |
7416 | CURSOR_GAMMA_ENABLE | |
8048 | CURSOR_GAMMA_ENABLE | |
7417 | CURSOR_FORMAT_ARGB; |
- | |
7418 | } else |
8049 | CURSOR_FORMAT_ARGB); |
7419 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
8050 | if (intel_crtc->cursor_cntl != cntl) { |
7420 | I915_WRITE(_CURACNTR, cntl); |
- | |
- | 8051 | I915_WRITE(_CURACNTR, cntl); |
|
7421 | 8052 | POSTING_READ(_CURACNTR); |
|
- | 8053 | intel_crtc->cursor_cntl = cntl; |
|
7422 | intel_crtc->cursor_visible = visible; |
8054 | } |
7423 | } |
8055 | } |
7424 | 8056 | ||
7425 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
8057 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
7426 | { |
8058 | { |
7427 | struct drm_device *dev = crtc->dev; |
8059 | struct drm_device *dev = crtc->dev; |
7428 | struct drm_i915_private *dev_priv = dev->dev_private; |
8060 | struct drm_i915_private *dev_priv = dev->dev_private; |
7429 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7430 | int pipe = intel_crtc->pipe; |
8062 | int pipe = intel_crtc->pipe; |
7431 | bool visible = base != 0; |
8063 | uint32_t cntl; |
7432 | - | ||
7433 | if (intel_crtc->cursor_visible != visible) { |
8064 | |
7434 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
8065 | cntl = 0; |
- | 8066 | if (base) { |
|
- | 8067 | cntl = MCURSOR_GAMMA_ENABLE; |
|
- | 8068 | switch (intel_crtc->cursor_width) { |
|
- | 8069 | case 64: |
|
- | 8070 | cntl |= CURSOR_MODE_64_ARGB_AX; |
|
- | 8071 | break; |
|
7435 | if (base) { |
8072 | case 128: |
- | 8073 | cntl |= CURSOR_MODE_128_ARGB_AX; |
|
- | 8074 | break; |
|
7436 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
8075 | case 256: |
- | 8076 | cntl |= CURSOR_MODE_256_ARGB_AX; |
|
- | 8077 | break; |
|
- | 8078 | default: |
|
- | 8079 | WARN_ON(1); |
|
- | 8080 | return; |
|
7437 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
8081 | } |
7438 | cntl |= pipe << 28; /* Connect to correct pipe */ |
- | |
7439 | } else { |
- | |
7440 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
- | |
7441 | cntl |= CURSOR_MODE_DISABLE; |
8082 | cntl |= pipe << 28; /* Connect to correct pipe */ |
- | 8083 | } |
|
7442 | } |
8084 | if (intel_crtc->cursor_cntl != cntl) { |
7443 | I915_WRITE(CURCNTR(pipe), cntl); |
- | |
- | 8085 | I915_WRITE(CURCNTR(pipe), cntl); |
|
7444 | 8086 | POSTING_READ(CURCNTR(pipe)); |
|
7445 | intel_crtc->cursor_visible = visible; |
8087 | intel_crtc->cursor_cntl = cntl; |
- | 8088 | } |
|
7446 | } |
8089 | |
7447 | /* and commit changes on next vblank */ |
- | |
7448 | POSTING_READ(CURCNTR(pipe)); |
8090 | /* and commit changes on next vblank */ |
7449 | I915_WRITE(CURBASE(pipe), base); |
8091 | I915_WRITE(CURBASE(pipe), base); |
7450 | POSTING_READ(CURBASE(pipe)); |
8092 | POSTING_READ(CURBASE(pipe)); |
7451 | } |
8093 | } |
7452 | 8094 | ||
7453 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8095 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7454 | { |
8096 | { |
7455 | struct drm_device *dev = crtc->dev; |
8097 | struct drm_device *dev = crtc->dev; |
7456 | struct drm_i915_private *dev_priv = dev->dev_private; |
8098 | struct drm_i915_private *dev_priv = dev->dev_private; |
7457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7458 | int pipe = intel_crtc->pipe; |
8100 | int pipe = intel_crtc->pipe; |
7459 | bool visible = base != 0; |
8101 | uint32_t cntl; |
7460 | - | ||
7461 | if (intel_crtc->cursor_visible != visible) { |
8102 | |
7462 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
8103 | cntl = 0; |
7463 | if (base) { |
8104 | if (base) { |
- | 8105 | cntl = MCURSOR_GAMMA_ENABLE; |
|
- | 8106 | switch (intel_crtc->cursor_width) { |
|
7464 | cntl &= ~CURSOR_MODE; |
8107 | case 64: |
- | 8108 | cntl |= CURSOR_MODE_64_ARGB_AX; |
|
7465 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
8109 | break; |
7466 | } else { |
8110 | case 128: |
- | 8111 | cntl |= CURSOR_MODE_128_ARGB_AX; |
|
- | 8112 | break; |
|
7467 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
8113 | case 256: |
- | 8114 | cntl |= CURSOR_MODE_256_ARGB_AX; |
|
- | 8115 | break; |
|
- | 8116 | default: |
|
- | 8117 | WARN_ON(1); |
|
7468 | cntl |= CURSOR_MODE_DISABLE; |
8118 | return; |
7469 | } |
- | |
7470 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
- | |
7471 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
- | |
7472 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
8119 | } |
- | 8120 | } |
|
7473 | } |
8121 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
- | 8122 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
|
- | 8123 | ||
- | 8124 | if (intel_crtc->cursor_cntl != cntl) { |
|
7474 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
8125 | I915_WRITE(CURCNTR(pipe), cntl); |
7475 | 8126 | POSTING_READ(CURCNTR(pipe)); |
|
- | 8127 | intel_crtc->cursor_cntl = cntl; |
|
7476 | intel_crtc->cursor_visible = visible; |
8128 | } |
7477 | } |
- | |
7478 | /* and commit changes on next vblank */ |
8129 | |
7479 | POSTING_READ(CURCNTR_IVB(pipe)); |
8130 | /* and commit changes on next vblank */ |
7480 | I915_WRITE(CURBASE_IVB(pipe), base); |
8131 | I915_WRITE(CURBASE(pipe), base); |
7481 | POSTING_READ(CURBASE_IVB(pipe)); |
8132 | POSTING_READ(CURBASE(pipe)); |
7482 | } |
8133 | } |
7483 | 8134 | ||
7484 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
8135 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
7485 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8136 | void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7486 | bool on) |
8137 | bool on) |
7487 | { |
8138 | { |
7488 | struct drm_device *dev = crtc->dev; |
8139 | struct drm_device *dev = crtc->dev; |
7489 | struct drm_i915_private *dev_priv = dev->dev_private; |
8140 | struct drm_i915_private *dev_priv = dev->dev_private; |
7490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7491 | int pipe = intel_crtc->pipe; |
8142 | int pipe = intel_crtc->pipe; |
7492 | int x = intel_crtc->cursor_x; |
8143 | int x = crtc->cursor_x; |
7493 | int y = intel_crtc->cursor_y; |
8144 | int y = crtc->cursor_y; |
7494 | u32 base = 0, pos = 0; |
8145 | u32 base = 0, pos = 0; |
7495 | bool visible; |
- | |
7496 | 8146 | ||
7497 | if (on) |
8147 | if (on) |
7498 | base = intel_crtc->cursor_addr; |
8148 | base = intel_crtc->cursor_addr; |
7499 | 8149 | ||
7500 | if (x >= intel_crtc->config.pipe_src_w) |
8150 | if (x >= intel_crtc->config.pipe_src_w) |
7501 | base = 0; |
8151 | base = 0; |
7502 | 8152 | ||
7503 | if (y >= intel_crtc->config.pipe_src_h) |
8153 | if (y >= intel_crtc->config.pipe_src_h) |
7504 | base = 0; |
8154 | base = 0; |
7505 | 8155 | ||
7506 | if (x < 0) { |
8156 | if (x < 0) { |
7507 | if (x + intel_crtc->cursor_width <= 0) |
8157 | if (x + intel_crtc->cursor_width <= 0) |
7508 | base = 0; |
8158 | base = 0; |
7509 | 8159 | ||
7510 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
8160 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
7511 | x = -x; |
8161 | x = -x; |
7512 | } |
8162 | } |
7513 | pos |= x << CURSOR_X_SHIFT; |
8163 | pos |= x << CURSOR_X_SHIFT; |
7514 | 8164 | ||
7515 | if (y < 0) { |
8165 | if (y < 0) { |
7516 | if (y + intel_crtc->cursor_height <= 0) |
8166 | if (y + intel_crtc->cursor_height <= 0) |
7517 | base = 0; |
8167 | base = 0; |
7518 | 8168 | ||
7519 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
8169 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
7520 | y = -y; |
8170 | y = -y; |
7521 | } |
8171 | } |
7522 | pos |= y << CURSOR_Y_SHIFT; |
8172 | pos |= y << CURSOR_Y_SHIFT; |
7523 | - | ||
7524 | visible = base != 0; |
8173 | |
7525 | if (!visible && !intel_crtc->cursor_visible) |
8174 | if (base == 0 && intel_crtc->cursor_base == 0) |
7526 | return; |
- | |
7527 | - | ||
7528 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
- | |
7529 | I915_WRITE(CURPOS_IVB(pipe), pos); |
- | |
7530 | ivb_update_cursor(crtc, base); |
8175 | return; |
- | 8176 | ||
- | 8177 | I915_WRITE(CURPOS(pipe), pos); |
|
- | 8178 | ||
- | 8179 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
- | 8180 | ivb_update_cursor(crtc, base); |
|
- | 8181 | else if (IS_845G(dev) || IS_I865G(dev)) |
|
7531 | } else { |
8182 | i845_update_cursor(crtc, base); |
7532 | I915_WRITE(CURPOS(pipe), pos); |
- | |
- | 8183 | else |
|
7533 | i9xx_update_cursor(crtc, base); |
8184 | i9xx_update_cursor(crtc, base); |
- | 8185 | intel_crtc->cursor_base = base; |
|
- | 8186 | } |
|
7534 | } |
8187 | |
- | 8188 | /* |
|
- | 8189 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object |
|
- | 8190 | * |
|
- | 8191 | * Note that the object's reference will be consumed if the update fails. If |
|
7535 | } |
8192 | * the update succeeds, the reference of the old object (if any) will be |
7536 | 8193 | * consumed. |
|
7537 | #if 0 |
- | |
7538 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
8194 | */ |
7539 | struct drm_file *file, |
8195 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, |
7540 | uint32_t handle, |
8196 | struct drm_i915_gem_object *obj, |
7541 | uint32_t width, uint32_t height) |
8197 | uint32_t width, uint32_t height) |
7542 | { |
8198 | { |
7543 | struct drm_device *dev = crtc->dev; |
8199 | struct drm_device *dev = crtc->dev; |
7544 | struct drm_i915_private *dev_priv = dev->dev_private; |
8200 | struct drm_i915_private *dev_priv = dev->dev_private; |
7545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7546 | struct drm_i915_gem_object *obj; |
8202 | enum pipe pipe = intel_crtc->pipe; |
- | 8203 | unsigned old_width; |
|
7547 | uint32_t addr; |
8204 | uint32_t addr; |
7548 | int ret; |
8205 | int ret; |
7549 | 8206 | ||
7550 | /* if we want to turn off the cursor ignore width and height */ |
8207 | /* if we want to turn off the cursor ignore width and height */ |
7551 | if (!handle) { |
8208 | if (!obj) { |
7552 | DRM_DEBUG_KMS("cursor off\n"); |
8209 | DRM_DEBUG_KMS("cursor off\n"); |
7553 | addr = 0; |
8210 | addr = 0; |
7554 | obj = NULL; |
8211 | obj = NULL; |
7555 | mutex_lock(&dev->struct_mutex); |
8212 | mutex_lock(&dev->struct_mutex); |
7556 | goto finish; |
8213 | goto finish; |
7557 | } |
8214 | } |
7558 | 8215 | ||
7559 | /* Currently we only support 64x64 cursors */ |
8216 | /* Check for which cursor types we support */ |
- | 8217 | if (!((width == 64 && height == 64) || |
|
- | 8218 | (width == 128 && height == 128 && !IS_GEN2(dev)) || |
|
7560 | if (width != 64 || height != 64) { |
8219 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { |
7561 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
8220 | DRM_DEBUG("Cursor dimension not supported\n"); |
7562 | return -EINVAL; |
8221 | return -EINVAL; |
7563 | } |
8222 | } |
7564 | - | ||
7565 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
- | |
7566 | if (&obj->base == NULL) |
- | |
7567 | return -ENOENT; |
- | |
7568 | 8223 | ||
7569 | if (obj->base.size < width * height * 4) { |
8224 | if (obj->base.size < width * height * 4) { |
7570 | DRM_ERROR("buffer is to small\n"); |
8225 | DRM_DEBUG_KMS("buffer is too small\n"); |
7571 | ret = -ENOMEM; |
8226 | ret = -ENOMEM; |
7572 | goto fail; |
8227 | goto fail; |
7573 | } |
8228 | } |
7574 | 8229 | ||
7575 | /* we only need to pin inside GTT if cursor is non-phy */ |
8230 | /* we only need to pin inside GTT if cursor is non-phy */ |
7576 | mutex_lock(&dev->struct_mutex); |
8231 | mutex_lock(&dev->struct_mutex); |
7577 | if (!dev_priv->info->cursor_needs_physical) { |
8232 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
7578 | unsigned alignment; |
8233 | unsigned alignment; |
7579 | 8234 | ||
7580 | if (obj->tiling_mode) { |
8235 | if (obj->tiling_mode) { |
7581 | DRM_ERROR("cursor cannot be tiled\n"); |
8236 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
7582 | ret = -EINVAL; |
8237 | ret = -EINVAL; |
7583 | goto fail_locked; |
8238 | goto fail_locked; |
7584 | } |
8239 | } |
7585 | 8240 | ||
7586 | /* Note that the w/a also requires 2 PTE of padding following |
8241 | /* Note that the w/a also requires 2 PTE of padding following |
7587 | * the bo. We currently fill all unused PTE with the shadow |
8242 | * the bo. We currently fill all unused PTE with the shadow |
7588 | * page and so we should always have valid PTE following the |
8243 | * page and so we should always have valid PTE following the |
7589 | * cursor preventing the VT-d warning. |
8244 | * cursor preventing the VT-d warning. |
7590 | */ |
8245 | */ |
7591 | alignment = 0; |
8246 | alignment = 0; |
7592 | if (need_vtd_wa(dev)) |
8247 | if (need_vtd_wa(dev)) |
7593 | alignment = 64*1024; |
8248 | alignment = 64*1024; |
7594 | 8249 | ||
7595 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
8250 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
7596 | if (ret) { |
8251 | if (ret) { |
7597 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
8252 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
7598 | goto fail_locked; |
8253 | goto fail_locked; |
7599 | } |
8254 | } |
7600 | 8255 | ||
7601 | ret = i915_gem_object_put_fence(obj); |
8256 | ret = i915_gem_object_put_fence(obj); |
7602 | if (ret) { |
8257 | if (ret) { |
7603 | DRM_ERROR("failed to release fence for cursor"); |
8258 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
7604 | goto fail_unpin; |
8259 | goto fail_unpin; |
7605 | } |
8260 | } |
7606 | 8261 | ||
7607 | addr = i915_gem_obj_ggtt_offset(obj); |
8262 | addr = i915_gem_obj_ggtt_offset(obj); |
7608 | } else { |
8263 | } else { |
7609 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
8264 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
7610 | ret = i915_gem_attach_phys_object(dev, obj, |
8265 | // ret = i915_gem_object_attach_phys(obj, align); |
7611 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
- | |
7612 | align); |
- | |
7613 | if (ret) { |
8266 | // if (ret) { |
7614 | DRM_ERROR("failed to attach phys object\n"); |
8267 | // DRM_DEBUG_KMS("failed to attach phys object\n"); |
7615 | goto fail_locked; |
8268 | // goto fail_locked; |
7616 | } |
8269 | // } |
7617 | addr = obj->phys_obj->handle->busaddr; |
8270 | // addr = obj->phys_handle->busaddr; |
7618 | } |
8271 | } |
7619 | 8272 | ||
7620 | if (IS_GEN2(dev)) |
8273 | if (IS_GEN2(dev)) |
7621 | I915_WRITE(CURSIZE, (height << 12) | width); |
8274 | I915_WRITE(CURSIZE, (height << 12) | width); |
7622 | 8275 | ||
7623 | finish: |
8276 | finish: |
7624 | if (intel_crtc->cursor_bo) { |
8277 | if (intel_crtc->cursor_bo) { |
7625 | if (dev_priv->info->cursor_needs_physical) { |
8278 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
7626 | if (intel_crtc->cursor_bo != obj) |
- | |
7627 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
- | |
7628 | } else |
- | |
7629 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
8279 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
7630 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
- | |
7631 | } |
8280 | } |
- | 8281 | ||
- | 8282 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
|
7632 | 8283 | INTEL_FRONTBUFFER_CURSOR(pipe)); |
|
- | 8284 | mutex_unlock(&dev->struct_mutex); |
|
- | 8285 | ||
7633 | mutex_unlock(&dev->struct_mutex); |
8286 | old_width = intel_crtc->cursor_width; |
7634 | 8287 | ||
7635 | intel_crtc->cursor_addr = addr; |
8288 | intel_crtc->cursor_addr = addr; |
7636 | intel_crtc->cursor_bo = obj; |
8289 | intel_crtc->cursor_bo = obj; |
7637 | intel_crtc->cursor_width = width; |
8290 | intel_crtc->cursor_width = width; |
7638 | intel_crtc->cursor_height = height; |
8291 | intel_crtc->cursor_height = height; |
7639 | 8292 | ||
- | 8293 | if (intel_crtc->active) { |
|
- | 8294 | if (old_width != width) |
|
7640 | if (intel_crtc->active) |
8295 | intel_update_watermarks(crtc); |
- | 8296 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
|
7641 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
8297 | } |
7642 | 8298 | ||
7643 | return 0; |
8299 | return 0; |
7644 | fail_unpin: |
8300 | fail_unpin: |
7645 | i915_gem_object_unpin_from_display_plane(obj); |
8301 | i915_gem_object_unpin_from_display_plane(obj); |
7646 | fail_locked: |
8302 | fail_locked: |
7647 | mutex_unlock(&dev->struct_mutex); |
8303 | mutex_unlock(&dev->struct_mutex); |
7648 | fail: |
8304 | fail: |
7649 | drm_gem_object_unreference_unlocked(&obj->base); |
8305 | drm_gem_object_unreference_unlocked(&obj->base); |
7650 | return ret; |
8306 | return ret; |
7651 | } |
8307 | } |
7652 | #endif |
- | |
7653 | - | ||
7654 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
- | |
7655 | { |
- | |
7656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7657 | - | ||
7658 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
- | |
7659 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); |
- | |
7660 | - | ||
7661 | if (intel_crtc->active) |
- | |
7662 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
- | |
7663 | - | ||
7664 | return 0; |
- | |
7665 | } |
- | |
7666 | 8308 | ||
7667 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
8309 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7668 | u16 *blue, uint32_t start, uint32_t size) |
8310 | u16 *blue, uint32_t start, uint32_t size) |
7669 | { |
8311 | { |
7670 | int end = (start + size > 256) ? 256 : start + size, i; |
8312 | int end = (start + size > 256) ? 256 : start + size, i; |
7671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7672 | 8314 | ||
7673 | for (i = start; i < end; i++) { |
8315 | for (i = start; i < end; i++) { |
7674 | intel_crtc->lut_r[i] = red[i] >> 8; |
8316 | intel_crtc->lut_r[i] = red[i] >> 8; |
7675 | intel_crtc->lut_g[i] = green[i] >> 8; |
8317 | intel_crtc->lut_g[i] = green[i] >> 8; |
7676 | intel_crtc->lut_b[i] = blue[i] >> 8; |
8318 | intel_crtc->lut_b[i] = blue[i] >> 8; |
7677 | } |
8319 | } |
7678 | 8320 | ||
7679 | intel_crtc_load_lut(crtc); |
8321 | intel_crtc_load_lut(crtc); |
7680 | } |
8322 | } |
7681 | 8323 | ||
7682 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8324 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7683 | static struct drm_display_mode load_detect_mode = { |
8325 | static struct drm_display_mode load_detect_mode = { |
7684 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
8326 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7685 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
8327 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7686 | }; |
8328 | }; |
7687 | 8329 | ||
7688 | struct drm_framebuffer * |
8330 | struct drm_framebuffer * |
7689 | intel_framebuffer_create(struct drm_device *dev, |
8331 | __intel_framebuffer_create(struct drm_device *dev, |
7690 | struct drm_mode_fb_cmd2 *mode_cmd, |
8332 | struct drm_mode_fb_cmd2 *mode_cmd, |
7691 | struct drm_i915_gem_object *obj) |
8333 | struct drm_i915_gem_object *obj) |
7692 | { |
8334 | { |
7693 | struct intel_framebuffer *intel_fb; |
8335 | struct intel_framebuffer *intel_fb; |
7694 | int ret; |
8336 | int ret; |
7695 | 8337 | ||
7696 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
8338 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7697 | if (!intel_fb) { |
8339 | if (!intel_fb) { |
7698 | drm_gem_object_unreference_unlocked(&obj->base); |
8340 | drm_gem_object_unreference_unlocked(&obj->base); |
7699 | return ERR_PTR(-ENOMEM); |
8341 | return ERR_PTR(-ENOMEM); |
7700 | } |
8342 | } |
7701 | - | ||
7702 | ret = i915_mutex_lock_interruptible(dev); |
- | |
7703 | if (ret) |
- | |
7704 | goto err; |
- | |
7705 | 8343 | ||
7706 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
- | |
7707 | mutex_unlock(&dev->struct_mutex); |
8344 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7708 | if (ret) |
8345 | if (ret) |
7709 | goto err; |
8346 | goto err; |
7710 | 8347 | ||
7711 | return &intel_fb->base; |
8348 | return &intel_fb->base; |
7712 | err: |
8349 | err: |
7713 | drm_gem_object_unreference_unlocked(&obj->base); |
8350 | drm_gem_object_unreference_unlocked(&obj->base); |
7714 | kfree(intel_fb); |
8351 | kfree(intel_fb); |
7715 | 8352 | ||
7716 | return ERR_PTR(ret); |
8353 | return ERR_PTR(ret); |
7717 | } |
8354 | } |
- | 8355 | ||
- | 8356 | static struct drm_framebuffer * |
|
- | 8357 | intel_framebuffer_create(struct drm_device *dev, |
|
- | 8358 | struct drm_mode_fb_cmd2 *mode_cmd, |
|
- | 8359 | struct drm_i915_gem_object *obj) |
|
- | 8360 | { |
|
- | 8361 | struct drm_framebuffer *fb; |
|
- | 8362 | int ret; |
|
- | 8363 | ||
- | 8364 | ret = i915_mutex_lock_interruptible(dev); |
|
- | 8365 | if (ret) |
|
- | 8366 | return ERR_PTR(ret); |
|
- | 8367 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
|
- | 8368 | mutex_unlock(&dev->struct_mutex); |
|
- | 8369 | ||
- | 8370 | return fb; |
|
- | 8371 | } |
|
7718 | 8372 | ||
7719 | static u32 |
8373 | static u32 |
7720 | intel_framebuffer_pitch_for_width(int width, int bpp) |
8374 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7721 | { |
8375 | { |
7722 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
8376 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7723 | return ALIGN(pitch, 64); |
8377 | return ALIGN(pitch, 64); |
7724 | } |
8378 | } |
7725 | 8379 | ||
7726 | static u32 |
8380 | static u32 |
7727 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
8381 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7728 | { |
8382 | { |
7729 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
8383 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7730 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
8384 | return PAGE_ALIGN(pitch * mode->vdisplay); |
7731 | } |
8385 | } |
7732 | 8386 | ||
7733 | static struct drm_framebuffer * |
8387 | static struct drm_framebuffer * |
7734 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
8388 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7735 | struct drm_display_mode *mode, |
8389 | struct drm_display_mode *mode, |
7736 | int depth, int bpp) |
8390 | int depth, int bpp) |
7737 | { |
8391 | { |
7738 | struct drm_i915_gem_object *obj; |
8392 | struct drm_i915_gem_object *obj; |
7739 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
8393 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
- | 8394 | ||
- | 8395 | obj = i915_gem_alloc_object(dev, |
|
7740 | 8396 | intel_framebuffer_size_for_mode(mode, bpp)); |
|
- | 8397 | if (obj == NULL) |
|
- | 8398 | return ERR_PTR(-ENOMEM); |
|
- | 8399 | ||
- | 8400 | mode_cmd.width = mode->hdisplay; |
|
- | 8401 | mode_cmd.height = mode->vdisplay; |
|
- | 8402 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
|
- | 8403 | bpp); |
|
- | 8404 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
|
- | 8405 | ||
7741 | return NULL; |
8406 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
7742 | } |
8407 | } |
7743 | 8408 | ||
7744 | static struct drm_framebuffer * |
8409 | static struct drm_framebuffer * |
7745 | mode_fits_in_fbdev(struct drm_device *dev, |
8410 | mode_fits_in_fbdev(struct drm_device *dev, |
7746 | struct drm_display_mode *mode) |
8411 | struct drm_display_mode *mode) |
7747 | { |
8412 | { |
7748 | #ifdef CONFIG_DRM_I915_FBDEV |
8413 | #ifdef CONFIG_DRM_I915_FBDEV |
7749 | struct drm_i915_private *dev_priv = dev->dev_private; |
8414 | struct drm_i915_private *dev_priv = dev->dev_private; |
7750 | struct drm_i915_gem_object *obj; |
8415 | struct drm_i915_gem_object *obj; |
7751 | struct drm_framebuffer *fb; |
8416 | struct drm_framebuffer *fb; |
7752 | 8417 | ||
7753 | if (dev_priv->fbdev == NULL) |
8418 | if (!dev_priv->fbdev) |
7754 | return NULL; |
8419 | return NULL; |
7755 | - | ||
7756 | obj = dev_priv->fbdev->ifb.obj; |
8420 | |
- | 8421 | if (!dev_priv->fbdev->fb) |
|
- | 8422 | return NULL; |
|
- | 8423 | ||
7757 | if (obj == NULL) |
8424 | obj = dev_priv->fbdev->fb->obj; |
7758 | return NULL; |
8425 | BUG_ON(!obj); |
7759 | 8426 | ||
7760 | fb = &dev_priv->fbdev->ifb.base; |
8427 | fb = &dev_priv->fbdev->fb->base; |
7761 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8428 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7762 | fb->bits_per_pixel)) |
8429 | fb->bits_per_pixel)) |
7763 | return NULL; |
8430 | return NULL; |
7764 | 8431 | ||
7765 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
8432 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7766 | return NULL; |
8433 | return NULL; |
7767 | 8434 | ||
7768 | return fb; |
8435 | return fb; |
7769 | #else |
8436 | #else |
7770 | return NULL; |
8437 | return NULL; |
7771 | #endif |
8438 | #endif |
7772 | } |
8439 | } |
7773 | 8440 | ||
7774 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
8441 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7775 | struct drm_display_mode *mode, |
8442 | struct drm_display_mode *mode, |
7776 | struct intel_load_detect_pipe *old) |
8443 | struct intel_load_detect_pipe *old, |
- | 8444 | struct drm_modeset_acquire_ctx *ctx) |
|
7777 | { |
8445 | { |
7778 | struct intel_crtc *intel_crtc; |
8446 | struct intel_crtc *intel_crtc; |
7779 | struct intel_encoder *intel_encoder = |
8447 | struct intel_encoder *intel_encoder = |
7780 | intel_attached_encoder(connector); |
8448 | intel_attached_encoder(connector); |
7781 | struct drm_crtc *possible_crtc; |
8449 | struct drm_crtc *possible_crtc; |
7782 | struct drm_encoder *encoder = &intel_encoder->base; |
8450 | struct drm_encoder *encoder = &intel_encoder->base; |
7783 | struct drm_crtc *crtc = NULL; |
8451 | struct drm_crtc *crtc = NULL; |
7784 | struct drm_device *dev = encoder->dev; |
8452 | struct drm_device *dev = encoder->dev; |
7785 | struct drm_framebuffer *fb; |
8453 | struct drm_framebuffer *fb; |
- | 8454 | struct drm_mode_config *config = &dev->mode_config; |
|
7786 | int i = -1; |
8455 | int ret, i = -1; |
7787 | 8456 | ||
7788 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8457 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7789 | connector->base.id, drm_get_connector_name(connector), |
8458 | connector->base.id, connector->name, |
- | 8459 | encoder->base.id, encoder->name); |
|
- | 8460 | ||
- | 8461 | retry: |
|
- | 8462 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
|
- | 8463 | if (ret) |
|
7790 | encoder->base.id, drm_get_encoder_name(encoder)); |
8464 | goto fail_unlock; |
7791 | 8465 | ||
7792 | /* |
8466 | /* |
7793 | * Algorithm gets a little messy: |
8467 | * Algorithm gets a little messy: |
7794 | * |
8468 | * |
7795 | * - if the connector already has an assigned crtc, use it (but make |
8469 | * - if the connector already has an assigned crtc, use it (but make |
7796 | * sure it's on first) |
8470 | * sure it's on first) |
7797 | * |
8471 | * |
7798 | * - try to find the first unused crtc that can drive this connector, |
8472 | * - try to find the first unused crtc that can drive this connector, |
7799 | * and use that if we find one |
8473 | * and use that if we find one |
7800 | */ |
8474 | */ |
7801 | 8475 | ||
7802 | /* See if we already have a CRTC for this connector */ |
8476 | /* See if we already have a CRTC for this connector */ |
7803 | if (encoder->crtc) { |
8477 | if (encoder->crtc) { |
7804 | crtc = encoder->crtc; |
8478 | crtc = encoder->crtc; |
7805 | 8479 | ||
- | 8480 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
|
- | 8481 | if (ret) |
|
7806 | mutex_lock(&crtc->mutex); |
8482 | goto fail_unlock; |
7807 | 8483 | ||
7808 | old->dpms_mode = connector->dpms; |
8484 | old->dpms_mode = connector->dpms; |
7809 | old->load_detect_temp = false; |
8485 | old->load_detect_temp = false; |
7810 | 8486 | ||
7811 | /* Make sure the crtc and connector are running */ |
8487 | /* Make sure the crtc and connector are running */ |
7812 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8488 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7813 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
8489 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
7814 | 8490 | ||
7815 | return true; |
8491 | return true; |
7816 | } |
8492 | } |
7817 | 8493 | ||
7818 | /* Find an unused one (if possible) */ |
8494 | /* Find an unused one (if possible) */ |
7819 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
8495 | for_each_crtc(dev, possible_crtc) { |
7820 | i++; |
8496 | i++; |
7821 | if (!(encoder->possible_crtcs & (1 << i))) |
8497 | if (!(encoder->possible_crtcs & (1 << i))) |
7822 | continue; |
8498 | continue; |
7823 | if (!possible_crtc->enabled) { |
8499 | if (possible_crtc->enabled) |
- | 8500 | continue; |
|
- | 8501 | /* This can occur when applying the pipe A quirk on resume. */ |
|
- | 8502 | if (to_intel_crtc(possible_crtc)->new_enabled) |
|
- | 8503 | continue; |
|
- | 8504 | ||
7824 | crtc = possible_crtc; |
8505 | crtc = possible_crtc; |
7825 | break; |
8506 | break; |
7826 | } |
8507 | } |
7827 | } |
- | |
7828 | 8508 | ||
7829 | /* |
8509 | /* |
7830 | * If we didn't find an unused CRTC, don't use any. |
8510 | * If we didn't find an unused CRTC, don't use any. |
7831 | */ |
8511 | */ |
7832 | if (!crtc) { |
8512 | if (!crtc) { |
7833 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8513 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7834 | return false; |
8514 | goto fail_unlock; |
7835 | } |
8515 | } |
7836 | 8516 | ||
- | 8517 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
|
- | 8518 | if (ret) |
|
7837 | mutex_lock(&crtc->mutex); |
8519 | goto fail_unlock; |
7838 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8520 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7839 | to_intel_connector(connector)->new_encoder = intel_encoder; |
8521 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7840 | 8522 | ||
7841 | intel_crtc = to_intel_crtc(crtc); |
8523 | intel_crtc = to_intel_crtc(crtc); |
- | 8524 | intel_crtc->new_enabled = true; |
|
- | 8525 | intel_crtc->new_config = &intel_crtc->config; |
|
7842 | old->dpms_mode = connector->dpms; |
8526 | old->dpms_mode = connector->dpms; |
7843 | old->load_detect_temp = true; |
8527 | old->load_detect_temp = true; |
7844 | old->release_fb = NULL; |
8528 | old->release_fb = NULL; |
7845 | 8529 | ||
7846 | if (!mode) |
8530 | if (!mode) |
7847 | mode = &load_detect_mode; |
8531 | mode = &load_detect_mode; |
7848 | 8532 | ||
7849 | /* We need a framebuffer large enough to accommodate all accesses |
8533 | /* We need a framebuffer large enough to accommodate all accesses |
7850 | * that the plane may generate whilst we perform load detection. |
8534 | * that the plane may generate whilst we perform load detection. |
7851 | * We can not rely on the fbcon either being present (we get called |
8535 | * We can not rely on the fbcon either being present (we get called |
7852 | * during its initialisation to detect all boot displays, or it may |
8536 | * during its initialisation to detect all boot displays, or it may |
7853 | * not even exist) or that it is large enough to satisfy the |
8537 | * not even exist) or that it is large enough to satisfy the |
7854 | * requested mode. |
8538 | * requested mode. |
7855 | */ |
8539 | */ |
7856 | fb = mode_fits_in_fbdev(dev, mode); |
8540 | fb = mode_fits_in_fbdev(dev, mode); |
7857 | if (fb == NULL) { |
8541 | if (fb == NULL) { |
7858 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
8542 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
7859 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8543 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7860 | old->release_fb = fb; |
8544 | old->release_fb = fb; |
7861 | } else |
8545 | } else |
7862 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
8546 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7863 | if (IS_ERR(fb)) { |
8547 | if (IS_ERR(fb)) { |
7864 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
8548 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7865 | mutex_unlock(&crtc->mutex); |
- | |
7866 | return false; |
8549 | goto fail; |
7867 | } |
8550 | } |
7868 | 8551 | ||
7869 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
8552 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7870 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
8553 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7871 | if (old->release_fb) |
8554 | if (old->release_fb) |
7872 | old->release_fb->funcs->destroy(old->release_fb); |
8555 | old->release_fb->funcs->destroy(old->release_fb); |
7873 | mutex_unlock(&crtc->mutex); |
- | |
7874 | return false; |
8556 | goto fail; |
7875 | } |
8557 | } |
7876 | 8558 | ||
7877 | /* let the connector get through one full cycle before testing */ |
8559 | /* let the connector get through one full cycle before testing */ |
7878 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
8560 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7879 | return true; |
8561 | return true; |
- | 8562 | ||
- | 8563 | fail: |
|
- | 8564 | intel_crtc->new_enabled = crtc->enabled; |
|
- | 8565 | if (intel_crtc->new_enabled) |
|
- | 8566 | intel_crtc->new_config = &intel_crtc->config; |
|
- | 8567 | else |
|
- | 8568 | intel_crtc->new_config = NULL; |
|
- | 8569 | fail_unlock: |
|
- | 8570 | if (ret == -EDEADLK) { |
|
- | 8571 | drm_modeset_backoff(ctx); |
|
- | 8572 | goto retry; |
|
- | 8573 | } |
|
- | 8574 | ||
- | 8575 | return false; |
|
7880 | } |
8576 | } |
7881 | 8577 | ||
7882 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8578 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7883 | struct intel_load_detect_pipe *old) |
8579 | struct intel_load_detect_pipe *old) |
7884 | { |
8580 | { |
7885 | struct intel_encoder *intel_encoder = |
8581 | struct intel_encoder *intel_encoder = |
7886 | intel_attached_encoder(connector); |
8582 | intel_attached_encoder(connector); |
7887 | struct drm_encoder *encoder = &intel_encoder->base; |
8583 | struct drm_encoder *encoder = &intel_encoder->base; |
7888 | struct drm_crtc *crtc = encoder->crtc; |
8584 | struct drm_crtc *crtc = encoder->crtc; |
- | 8585 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
7889 | 8586 | ||
7890 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8587 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7891 | connector->base.id, drm_get_connector_name(connector), |
8588 | connector->base.id, connector->name, |
7892 | encoder->base.id, drm_get_encoder_name(encoder)); |
8589 | encoder->base.id, encoder->name); |
7893 | 8590 | ||
7894 | if (old->load_detect_temp) { |
8591 | if (old->load_detect_temp) { |
7895 | to_intel_connector(connector)->new_encoder = NULL; |
8592 | to_intel_connector(connector)->new_encoder = NULL; |
7896 | intel_encoder->new_crtc = NULL; |
8593 | intel_encoder->new_crtc = NULL; |
- | 8594 | intel_crtc->new_enabled = false; |
|
- | 8595 | intel_crtc->new_config = NULL; |
|
7897 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
8596 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
7898 | 8597 | ||
7899 | if (old->release_fb) { |
8598 | if (old->release_fb) { |
7900 | drm_framebuffer_unregister_private(old->release_fb); |
8599 | drm_framebuffer_unregister_private(old->release_fb); |
7901 | drm_framebuffer_unreference(old->release_fb); |
8600 | drm_framebuffer_unreference(old->release_fb); |
7902 | } |
8601 | } |
7903 | - | ||
7904 | mutex_unlock(&crtc->mutex); |
8602 | |
7905 | return; |
8603 | return; |
7906 | } |
8604 | } |
7907 | 8605 | ||
7908 | /* Switch crtc and encoder back off if necessary */ |
8606 | /* Switch crtc and encoder back off if necessary */ |
7909 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8607 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7910 | connector->funcs->dpms(connector, old->dpms_mode); |
8608 | connector->funcs->dpms(connector, old->dpms_mode); |
7911 | - | ||
7912 | mutex_unlock(&crtc->mutex); |
- | |
7913 | } |
8609 | } |
7914 | 8610 | ||
7915 | static int i9xx_pll_refclk(struct drm_device *dev, |
8611 | static int i9xx_pll_refclk(struct drm_device *dev, |
7916 | const struct intel_crtc_config *pipe_config) |
8612 | const struct intel_crtc_config *pipe_config) |
7917 | { |
8613 | { |
7918 | struct drm_i915_private *dev_priv = dev->dev_private; |
8614 | struct drm_i915_private *dev_priv = dev->dev_private; |
7919 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
8615 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
7920 | 8616 | ||
7921 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
8617 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
7922 | return dev_priv->vbt.lvds_ssc_freq; |
8618 | return dev_priv->vbt.lvds_ssc_freq; |
7923 | else if (HAS_PCH_SPLIT(dev)) |
8619 | else if (HAS_PCH_SPLIT(dev)) |
7924 | return 120000; |
8620 | return 120000; |
7925 | else if (!IS_GEN2(dev)) |
8621 | else if (!IS_GEN2(dev)) |
7926 | return 96000; |
8622 | return 96000; |
7927 | else |
8623 | else |
7928 | return 48000; |
8624 | return 48000; |
7929 | } |
8625 | } |
7930 | 8626 | ||
7931 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
8627 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7932 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8628 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7933 | struct intel_crtc_config *pipe_config) |
8629 | struct intel_crtc_config *pipe_config) |
7934 | { |
8630 | { |
7935 | struct drm_device *dev = crtc->base.dev; |
8631 | struct drm_device *dev = crtc->base.dev; |
7936 | struct drm_i915_private *dev_priv = dev->dev_private; |
8632 | struct drm_i915_private *dev_priv = dev->dev_private; |
7937 | int pipe = pipe_config->cpu_transcoder; |
8633 | int pipe = pipe_config->cpu_transcoder; |
7938 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
8634 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
7939 | u32 fp; |
8635 | u32 fp; |
7940 | intel_clock_t clock; |
8636 | intel_clock_t clock; |
7941 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
8637 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
7942 | 8638 | ||
7943 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
8639 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7944 | fp = pipe_config->dpll_hw_state.fp0; |
8640 | fp = pipe_config->dpll_hw_state.fp0; |
7945 | else |
8641 | else |
7946 | fp = pipe_config->dpll_hw_state.fp1; |
8642 | fp = pipe_config->dpll_hw_state.fp1; |
7947 | 8643 | ||
7948 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
8644 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7949 | if (IS_PINEVIEW(dev)) { |
8645 | if (IS_PINEVIEW(dev)) { |
7950 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
8646 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
7951 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
8647 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7952 | } else { |
8648 | } else { |
7953 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
8649 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
7954 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
8650 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7955 | } |
8651 | } |
7956 | 8652 | ||
7957 | if (!IS_GEN2(dev)) { |
8653 | if (!IS_GEN2(dev)) { |
7958 | if (IS_PINEVIEW(dev)) |
8654 | if (IS_PINEVIEW(dev)) |
7959 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
8655 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
7960 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
8656 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
7961 | else |
8657 | else |
7962 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
8658 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
7963 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8659 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7964 | 8660 | ||
7965 | switch (dpll & DPLL_MODE_MASK) { |
8661 | switch (dpll & DPLL_MODE_MASK) { |
7966 | case DPLLB_MODE_DAC_SERIAL: |
8662 | case DPLLB_MODE_DAC_SERIAL: |
7967 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
8663 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
7968 | 5 : 10; |
8664 | 5 : 10; |
7969 | break; |
8665 | break; |
7970 | case DPLLB_MODE_LVDS: |
8666 | case DPLLB_MODE_LVDS: |
7971 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
8667 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
7972 | 7 : 14; |
8668 | 7 : 14; |
7973 | break; |
8669 | break; |
7974 | default: |
8670 | default: |
7975 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
8671 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7976 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
8672 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7977 | return; |
8673 | return; |
7978 | } |
8674 | } |
7979 | 8675 | ||
7980 | if (IS_PINEVIEW(dev)) |
8676 | if (IS_PINEVIEW(dev)) |
7981 | pineview_clock(refclk, &clock); |
8677 | pineview_clock(refclk, &clock); |
7982 | else |
8678 | else |
7983 | i9xx_clock(refclk, &clock); |
8679 | i9xx_clock(refclk, &clock); |
7984 | } else { |
8680 | } else { |
7985 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
8681 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
7986 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
8682 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
7987 | 8683 | ||
7988 | if (is_lvds) { |
8684 | if (is_lvds) { |
7989 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
8685 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7990 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8686 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7991 | 8687 | ||
7992 | if (lvds & LVDS_CLKB_POWER_UP) |
8688 | if (lvds & LVDS_CLKB_POWER_UP) |
7993 | clock.p2 = 7; |
8689 | clock.p2 = 7; |
7994 | else |
8690 | else |
7995 | clock.p2 = 14; |
8691 | clock.p2 = 14; |
7996 | } else { |
8692 | } else { |
7997 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
8693 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7998 | clock.p1 = 2; |
8694 | clock.p1 = 2; |
7999 | else { |
8695 | else { |
8000 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
8696 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
8001 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
8697 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
8002 | } |
8698 | } |
8003 | if (dpll & PLL_P2_DIVIDE_BY_4) |
8699 | if (dpll & PLL_P2_DIVIDE_BY_4) |
8004 | clock.p2 = 4; |
8700 | clock.p2 = 4; |
8005 | else |
8701 | else |
8006 | clock.p2 = 2; |
8702 | clock.p2 = 2; |
8007 | } |
8703 | } |
8008 | 8704 | ||
8009 | i9xx_clock(refclk, &clock); |
8705 | i9xx_clock(refclk, &clock); |
8010 | } |
8706 | } |
8011 | 8707 | ||
8012 | /* |
8708 | /* |
8013 | * This value includes pixel_multiplier. We will use |
8709 | * This value includes pixel_multiplier. We will use |
8014 | * port_clock to compute adjusted_mode.crtc_clock in the |
8710 | * port_clock to compute adjusted_mode.crtc_clock in the |
8015 | * encoder's get_config() function. |
8711 | * encoder's get_config() function. |
8016 | */ |
8712 | */ |
8017 | pipe_config->port_clock = clock.dot; |
8713 | pipe_config->port_clock = clock.dot; |
8018 | } |
8714 | } |
8019 | 8715 | ||
8020 | int intel_dotclock_calculate(int link_freq, |
8716 | int intel_dotclock_calculate(int link_freq, |
8021 | const struct intel_link_m_n *m_n) |
8717 | const struct intel_link_m_n *m_n) |
8022 | { |
8718 | { |
8023 | /* |
8719 | /* |
8024 | * The calculation for the data clock is: |
8720 | * The calculation for the data clock is: |
8025 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
8721 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
8026 | * But we want to avoid losing precison if possible, so: |
8722 | * But we want to avoid losing precison if possible, so: |
8027 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
8723 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
8028 | * |
8724 | * |
8029 | * and the link clock is simpler: |
8725 | * and the link clock is simpler: |
8030 | * link_clock = (m * link_clock) / n |
8726 | * link_clock = (m * link_clock) / n |
8031 | */ |
8727 | */ |
8032 | 8728 | ||
8033 | if (!m_n->link_n) |
8729 | if (!m_n->link_n) |
8034 | return 0; |
8730 | return 0; |
8035 | 8731 | ||
8036 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8732 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8037 | } |
8733 | } |
8038 | 8734 | ||
8039 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8735 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8040 | struct intel_crtc_config *pipe_config) |
8736 | struct intel_crtc_config *pipe_config) |
8041 | { |
8737 | { |
8042 | struct drm_device *dev = crtc->base.dev; |
8738 | struct drm_device *dev = crtc->base.dev; |
8043 | 8739 | ||
8044 | /* read out port_clock from the DPLL */ |
8740 | /* read out port_clock from the DPLL */ |
8045 | i9xx_crtc_clock_get(crtc, pipe_config); |
8741 | i9xx_crtc_clock_get(crtc, pipe_config); |
8046 | 8742 | ||
8047 | /* |
8743 | /* |
8048 | * This value does not include pixel_multiplier. |
8744 | * This value does not include pixel_multiplier. |
8049 | * We will check that port_clock and adjusted_mode.crtc_clock |
8745 | * We will check that port_clock and adjusted_mode.crtc_clock |
8050 | * agree once we know their relationship in the encoder's |
8746 | * agree once we know their relationship in the encoder's |
8051 | * get_config() function. |
8747 | * get_config() function. |
8052 | */ |
8748 | */ |
8053 | pipe_config->adjusted_mode.crtc_clock = |
8749 | pipe_config->adjusted_mode.crtc_clock = |
8054 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8750 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8055 | &pipe_config->fdi_m_n); |
8751 | &pipe_config->fdi_m_n); |
8056 | } |
8752 | } |
8057 | 8753 | ||
8058 | /** Returns the currently programmed mode of the given pipe. */ |
8754 | /** Returns the currently programmed mode of the given pipe. */ |
8059 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
8755 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
8060 | struct drm_crtc *crtc) |
8756 | struct drm_crtc *crtc) |
8061 | { |
8757 | { |
8062 | struct drm_i915_private *dev_priv = dev->dev_private; |
8758 | struct drm_i915_private *dev_priv = dev->dev_private; |
8063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8064 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8760 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8065 | struct drm_display_mode *mode; |
8761 | struct drm_display_mode *mode; |
8066 | struct intel_crtc_config pipe_config; |
8762 | struct intel_crtc_config pipe_config; |
8067 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8763 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8068 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
8764 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
8069 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
8765 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
8070 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
8766 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
8071 | enum pipe pipe = intel_crtc->pipe; |
8767 | enum pipe pipe = intel_crtc->pipe; |
8072 | 8768 | ||
8073 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
8769 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
8074 | if (!mode) |
8770 | if (!mode) |
8075 | return NULL; |
8771 | return NULL; |
8076 | 8772 | ||
8077 | /* |
8773 | /* |
8078 | * Construct a pipe_config sufficient for getting the clock info |
8774 | * Construct a pipe_config sufficient for getting the clock info |
8079 | * back out of crtc_clock_get. |
8775 | * back out of crtc_clock_get. |
8080 | * |
8776 | * |
8081 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
8777 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
8082 | * to use a real value here instead. |
8778 | * to use a real value here instead. |
8083 | */ |
8779 | */ |
8084 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
8780 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
8085 | pipe_config.pixel_multiplier = 1; |
8781 | pipe_config.pixel_multiplier = 1; |
8086 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8782 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8087 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
8783 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
8088 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
8784 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
8089 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8785 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8090 | 8786 | ||
8091 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
8787 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
8092 | mode->hdisplay = (htot & 0xffff) + 1; |
8788 | mode->hdisplay = (htot & 0xffff) + 1; |
8093 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
8789 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
8094 | mode->hsync_start = (hsync & 0xffff) + 1; |
8790 | mode->hsync_start = (hsync & 0xffff) + 1; |
8095 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
8791 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
8096 | mode->vdisplay = (vtot & 0xffff) + 1; |
8792 | mode->vdisplay = (vtot & 0xffff) + 1; |
8097 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
8793 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
8098 | mode->vsync_start = (vsync & 0xffff) + 1; |
8794 | mode->vsync_start = (vsync & 0xffff) + 1; |
8099 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
8795 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
8100 | 8796 | ||
8101 | drm_mode_set_name(mode); |
8797 | drm_mode_set_name(mode); |
8102 | 8798 | ||
8103 | return mode; |
8799 | return mode; |
8104 | } |
8800 | } |
8105 | 8801 | ||
- | 8802 | static void intel_increase_pllclock(struct drm_device *dev, |
|
8106 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
8803 | enum pipe pipe) |
8107 | { |
- | |
8108 | struct drm_device *dev = crtc->dev; |
8804 | { |
8109 | drm_i915_private_t *dev_priv = dev->dev_private; |
- | |
8110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
8111 | int pipe = intel_crtc->pipe; |
8805 | struct drm_i915_private *dev_priv = dev->dev_private; |
8112 | int dpll_reg = DPLL(pipe); |
8806 | int dpll_reg = DPLL(pipe); |
8113 | int dpll; |
8807 | int dpll; |
8114 | 8808 | ||
8115 | if (HAS_PCH_SPLIT(dev)) |
8809 | if (!HAS_GMCH_DISPLAY(dev)) |
8116 | return; |
8810 | return; |
8117 | 8811 | ||
8118 | if (!dev_priv->lvds_downclock_avail) |
8812 | if (!dev_priv->lvds_downclock_avail) |
8119 | return; |
8813 | return; |
8120 | 8814 | ||
8121 | dpll = I915_READ(dpll_reg); |
8815 | dpll = I915_READ(dpll_reg); |
8122 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
8816 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
8123 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
8817 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
8124 | 8818 | ||
8125 | assert_panel_unlocked(dev_priv, pipe); |
8819 | assert_panel_unlocked(dev_priv, pipe); |
8126 | 8820 | ||
8127 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
8821 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
8128 | I915_WRITE(dpll_reg, dpll); |
8822 | I915_WRITE(dpll_reg, dpll); |
8129 | intel_wait_for_vblank(dev, pipe); |
8823 | intel_wait_for_vblank(dev, pipe); |
8130 | 8824 | ||
8131 | dpll = I915_READ(dpll_reg); |
8825 | dpll = I915_READ(dpll_reg); |
8132 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
8826 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
8133 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
8827 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
8134 | } |
8828 | } |
8135 | } |
8829 | } |
8136 | 8830 | ||
8137 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8831 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8138 | { |
8832 | { |
8139 | struct drm_device *dev = crtc->dev; |
8833 | struct drm_device *dev = crtc->dev; |
8140 | drm_i915_private_t *dev_priv = dev->dev_private; |
8834 | struct drm_i915_private *dev_priv = dev->dev_private; |
8141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8142 | 8836 | ||
8143 | if (HAS_PCH_SPLIT(dev)) |
8837 | if (!HAS_GMCH_DISPLAY(dev)) |
8144 | return; |
8838 | return; |
8145 | 8839 | ||
8146 | if (!dev_priv->lvds_downclock_avail) |
8840 | if (!dev_priv->lvds_downclock_avail) |
8147 | return; |
8841 | return; |
8148 | 8842 | ||
8149 | /* |
8843 | /* |
8150 | * Since this is called by a timer, we should never get here in |
8844 | * Since this is called by a timer, we should never get here in |
8151 | * the manual case. |
8845 | * the manual case. |
8152 | */ |
8846 | */ |
8153 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
8847 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
8154 | int pipe = intel_crtc->pipe; |
8848 | int pipe = intel_crtc->pipe; |
8155 | int dpll_reg = DPLL(pipe); |
8849 | int dpll_reg = DPLL(pipe); |
8156 | int dpll; |
8850 | int dpll; |
8157 | 8851 | ||
8158 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
8852 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
8159 | 8853 | ||
8160 | assert_panel_unlocked(dev_priv, pipe); |
8854 | assert_panel_unlocked(dev_priv, pipe); |
8161 | 8855 | ||
8162 | dpll = I915_READ(dpll_reg); |
8856 | dpll = I915_READ(dpll_reg); |
8163 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8857 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8164 | I915_WRITE(dpll_reg, dpll); |
8858 | I915_WRITE(dpll_reg, dpll); |
8165 | intel_wait_for_vblank(dev, pipe); |
8859 | intel_wait_for_vblank(dev, pipe); |
8166 | dpll = I915_READ(dpll_reg); |
8860 | dpll = I915_READ(dpll_reg); |
8167 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
8861 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
8168 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
8862 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
8169 | } |
8863 | } |
8170 | 8864 | ||
8171 | } |
8865 | } |
8172 | 8866 | ||
8173 | void intel_mark_busy(struct drm_device *dev) |
8867 | void intel_mark_busy(struct drm_device *dev) |
8174 | { |
8868 | { |
8175 | struct drm_i915_private *dev_priv = dev->dev_private; |
8869 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 8870 | ||
- | 8871 | if (dev_priv->mm.busy) |
|
- | 8872 | return; |
|
8176 | 8873 | ||
8177 | hsw_package_c8_gpu_busy(dev_priv); |
8874 | intel_runtime_pm_get(dev_priv); |
- | 8875 | i915_update_gfx_val(dev_priv); |
|
8178 | i915_update_gfx_val(dev_priv); |
8876 | dev_priv->mm.busy = true; |
8179 | } |
8877 | } |
8180 | 8878 | ||
8181 | void intel_mark_idle(struct drm_device *dev) |
8879 | void intel_mark_idle(struct drm_device *dev) |
8182 | { |
8880 | { |
8183 | struct drm_i915_private *dev_priv = dev->dev_private; |
8881 | struct drm_i915_private *dev_priv = dev->dev_private; |
8184 | struct drm_crtc *crtc; |
8882 | struct drm_crtc *crtc; |
8185 | - | ||
8186 | hsw_package_c8_gpu_idle(dev_priv); |
- | |
8187 | 8883 | ||
8188 | if (!i915_powersave) |
8884 | if (!dev_priv->mm.busy) |
- | 8885 | return; |
|
- | 8886 | ||
- | 8887 | dev_priv->mm.busy = false; |
|
- | 8888 | ||
- | 8889 | if (!i915.powersave) |
|
8189 | return; |
8890 | goto out; |
8190 | 8891 | ||
8191 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8892 | for_each_crtc(dev, crtc) { |
8192 | if (!crtc->fb) |
8893 | if (!crtc->primary->fb) |
8193 | continue; |
8894 | continue; |
8194 | 8895 | ||
8195 | intel_decrease_pllclock(crtc); |
8896 | intel_decrease_pllclock(crtc); |
8196 | } |
8897 | } |
8197 | 8898 | ||
8198 | if (dev_priv->info->gen >= 6) |
8899 | if (INTEL_INFO(dev)->gen >= 6) |
- | 8900 | gen6_rps_idle(dev->dev_private); |
|
- | 8901 | ||
- | 8902 | out: |
|
8199 | gen6_rps_idle(dev->dev_private); |
8903 | intel_runtime_pm_put(dev_priv); |
- | 8904 | } |
|
- | 8905 | ||
- | 8906 | ||
- | 8907 | /** |
|
- | 8908 | * intel_mark_fb_busy - mark given planes as busy |
|
- | 8909 | * @dev: DRM device |
|
- | 8910 | * @frontbuffer_bits: bits for the affected planes |
|
- | 8911 | * @ring: optional ring for asynchronous commands |
|
- | 8912 | * |
|
- | 8913 | * This function gets called every time the screen contents change. It can be |
|
8200 | } |
8914 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. |
- | 8915 | */ |
|
8201 | 8916 | static void intel_mark_fb_busy(struct drm_device *dev, |
|
8202 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8917 | unsigned frontbuffer_bits, |
8203 | struct intel_ring_buffer *ring) |
- | |
8204 | { |
8918 | struct intel_engine_cs *ring) |
8205 | struct drm_device *dev = obj->base.dev; |
8919 | { |
8206 | struct drm_crtc *crtc; |
8920 | enum pipe pipe; |
8207 | - | ||
8208 | if (!i915_powersave) |
8921 | |
8209 | return; |
- | |
8210 | - | ||
8211 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8922 | if (!i915.powersave) |
8212 | if (!crtc->fb) |
8923 | return; |
8213 | continue; |
8924 | |
8214 | 8925 | for_each_pipe(pipe) { |
|
8215 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8926 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
8216 | continue; |
8927 | continue; |
8217 | 8928 | ||
8218 | intel_increase_pllclock(crtc); |
8929 | intel_increase_pllclock(dev, pipe); |
8219 | if (ring && intel_fbc_enabled(dev)) |
8930 | if (ring && intel_fbc_enabled(dev)) |
8220 | ring->fbc_dirty = true; |
8931 | ring->fbc_dirty = true; |
8221 | } |
8932 | } |
8222 | } |
8933 | } |
- | 8934 | ||
- | 8935 | /** |
|
- | 8936 | * intel_fb_obj_invalidate - invalidate frontbuffer object |
|
- | 8937 | * @obj: GEM object to invalidate |
|
- | 8938 | * @ring: set for asynchronous rendering |
|
- | 8939 | * |
|
- | 8940 | * This function gets called every time rendering on the given object starts and |
|
- | 8941 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must |
|
- | 8942 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed |
|
- | 8943 | * until the rendering completes or a flip on this frontbuffer plane is |
|
- | 8944 | * scheduled. |
|
- | 8945 | */ |
|
- | 8946 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
|
- | 8947 | struct intel_engine_cs *ring) |
|
- | 8948 | { |
|
- | 8949 | struct drm_device *dev = obj->base.dev; |
|
- | 8950 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 8951 | ||
- | 8952 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
- | 8953 | ||
- | 8954 | if (!obj->frontbuffer_bits) |
|
- | 8955 | return; |
|
- | 8956 | ||
- | 8957 | if (ring) { |
|
- | 8958 | mutex_lock(&dev_priv->fb_tracking.lock); |
|
- | 8959 | dev_priv->fb_tracking.busy_bits |
|
- | 8960 | |= obj->frontbuffer_bits; |
|
- | 8961 | dev_priv->fb_tracking.flip_bits |
|
- | 8962 | &= ~obj->frontbuffer_bits; |
|
- | 8963 | mutex_unlock(&dev_priv->fb_tracking.lock); |
|
- | 8964 | } |
|
- | 8965 | ||
- | 8966 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); |
|
- | 8967 | ||
- | 8968 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
|
- | 8969 | } |
|
- | 8970 | ||
- | 8971 | /** |
|
- | 8972 | * intel_frontbuffer_flush - flush frontbuffer |
|
- | 8973 | * @dev: DRM device |
|
- | 8974 | * @frontbuffer_bits: frontbuffer plane tracking bits |
|
- | 8975 | * |
|
- | 8976 | * This function gets called every time rendering on the given planes has |
|
- | 8977 | * completed and frontbuffer caching can be started again. Flushes will get |
|
- | 8978 | * delayed if they're blocked by some oustanding asynchronous rendering. |
|
- | 8979 | * |
|
- | 8980 | * Can be called without any locks held. |
|
- | 8981 | */ |
|
- | 8982 | void intel_frontbuffer_flush(struct drm_device *dev, |
|
- | 8983 | unsigned frontbuffer_bits) |
|
- | 8984 | { |
|
- | 8985 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 8986 | ||
- | 8987 | /* Delay flushing when rings are still busy.*/ |
|
- | 8988 | mutex_lock(&dev_priv->fb_tracking.lock); |
|
- | 8989 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; |
|
- | 8990 | mutex_unlock(&dev_priv->fb_tracking.lock); |
|
- | 8991 | ||
- | 8992 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); |
|
- | 8993 | ||
- | 8994 | intel_edp_psr_flush(dev, frontbuffer_bits); |
|
8223 | 8995 | } |
|
8224 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8996 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8225 | { |
8997 | { |
8226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8227 | struct drm_device *dev = crtc->dev; |
8999 | struct drm_device *dev = crtc->dev; |
8228 | struct intel_unpin_work *work; |
9000 | struct intel_unpin_work *work; |
8229 | unsigned long flags; |
9001 | unsigned long flags; |
8230 | 9002 | ||
8231 | spin_lock_irqsave(&dev->event_lock, flags); |
9003 | spin_lock_irqsave(&dev->event_lock, flags); |
8232 | work = intel_crtc->unpin_work; |
9004 | work = intel_crtc->unpin_work; |
8233 | intel_crtc->unpin_work = NULL; |
9005 | intel_crtc->unpin_work = NULL; |
8234 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9006 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8235 | 9007 | ||
8236 | if (work) { |
9008 | if (work) { |
8237 | cancel_work_sync(&work->work); |
9009 | cancel_work_sync(&work->work); |
8238 | kfree(work); |
9010 | kfree(work); |
8239 | } |
9011 | } |
8240 | 9012 | ||
8241 | drm_crtc_cleanup(crtc); |
9013 | drm_crtc_cleanup(crtc); |
8242 | 9014 | ||
8243 | kfree(intel_crtc); |
9015 | kfree(intel_crtc); |
8244 | } |
9016 | } |
8245 | 9017 | ||
8246 | #if 0 |
9018 | #if 0 |
8247 | static void intel_unpin_work_fn(struct work_struct *__work) |
9019 | static void intel_unpin_work_fn(struct work_struct *__work) |
8248 | { |
9020 | { |
8249 | struct intel_unpin_work *work = |
9021 | struct intel_unpin_work *work = |
8250 | container_of(__work, struct intel_unpin_work, work); |
9022 | container_of(__work, struct intel_unpin_work, work); |
8251 | struct drm_device *dev = work->crtc->dev; |
9023 | struct drm_device *dev = work->crtc->dev; |
- | 9024 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
|
8252 | 9025 | ||
8253 | mutex_lock(&dev->struct_mutex); |
9026 | mutex_lock(&dev->struct_mutex); |
8254 | intel_unpin_fb_obj(work->old_fb_obj); |
9027 | intel_unpin_fb_obj(work->old_fb_obj); |
8255 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9028 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8256 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9029 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8257 | 9030 | ||
8258 | intel_update_fbc(dev); |
9031 | intel_update_fbc(dev); |
8259 | mutex_unlock(&dev->struct_mutex); |
9032 | mutex_unlock(&dev->struct_mutex); |
8260 | 9033 | ||
8261 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9034 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
8262 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
9035 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
8263 | 9036 | ||
8264 | kfree(work); |
9037 | kfree(work); |
8265 | } |
9038 | } |
8266 | 9039 | ||
8267 | static void do_intel_finish_page_flip(struct drm_device *dev, |
9040 | static void do_intel_finish_page_flip(struct drm_device *dev, |
8268 | struct drm_crtc *crtc) |
9041 | struct drm_crtc *crtc) |
8269 | { |
9042 | { |
8270 | drm_i915_private_t *dev_priv = dev->dev_private; |
9043 | struct drm_i915_private *dev_priv = dev->dev_private; |
8271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8272 | struct intel_unpin_work *work; |
9045 | struct intel_unpin_work *work; |
8273 | unsigned long flags; |
9046 | unsigned long flags; |
8274 | 9047 | ||
8275 | /* Ignore early vblank irqs */ |
9048 | /* Ignore early vblank irqs */ |
8276 | if (intel_crtc == NULL) |
9049 | if (intel_crtc == NULL) |
8277 | return; |
9050 | return; |
8278 | 9051 | ||
8279 | spin_lock_irqsave(&dev->event_lock, flags); |
9052 | spin_lock_irqsave(&dev->event_lock, flags); |
8280 | work = intel_crtc->unpin_work; |
9053 | work = intel_crtc->unpin_work; |
8281 | 9054 | ||
8282 | /* Ensure we don't miss a work->pending update ... */ |
9055 | /* Ensure we don't miss a work->pending update ... */ |
8283 | smp_rmb(); |
9056 | smp_rmb(); |
8284 | 9057 | ||
8285 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9058 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
8286 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9059 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8287 | return; |
9060 | return; |
8288 | } |
9061 | } |
8289 | 9062 | ||
8290 | /* and that the unpin work is consistent wrt ->pending. */ |
9063 | /* and that the unpin work is consistent wrt ->pending. */ |
8291 | smp_rmb(); |
9064 | smp_rmb(); |
8292 | 9065 | ||
8293 | intel_crtc->unpin_work = NULL; |
9066 | intel_crtc->unpin_work = NULL; |
8294 | 9067 | ||
8295 | if (work->event) |
9068 | if (work->event) |
8296 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
9069 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
8297 | 9070 | ||
8298 | drm_vblank_put(dev, intel_crtc->pipe); |
9071 | drm_crtc_vblank_put(crtc); |
8299 | 9072 | ||
8300 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9073 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8301 | 9074 | ||
8302 | wake_up_all(&dev_priv->pending_flip_queue); |
9075 | wake_up_all(&dev_priv->pending_flip_queue); |
8303 | 9076 | ||
8304 | queue_work(dev_priv->wq, &work->work); |
9077 | queue_work(dev_priv->wq, &work->work); |
8305 | 9078 | ||
8306 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
9079 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
8307 | } |
9080 | } |
8308 | 9081 | ||
8309 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9082 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8310 | { |
9083 | { |
8311 | drm_i915_private_t *dev_priv = dev->dev_private; |
9084 | struct drm_i915_private *dev_priv = dev->dev_private; |
8312 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9085 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8313 | 9086 | ||
8314 | do_intel_finish_page_flip(dev, crtc); |
9087 | do_intel_finish_page_flip(dev, crtc); |
8315 | } |
9088 | } |
8316 | 9089 | ||
8317 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
9090 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
8318 | { |
9091 | { |
8319 | drm_i915_private_t *dev_priv = dev->dev_private; |
9092 | struct drm_i915_private *dev_priv = dev->dev_private; |
8320 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9093 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8321 | 9094 | ||
8322 | do_intel_finish_page_flip(dev, crtc); |
9095 | do_intel_finish_page_flip(dev, crtc); |
8323 | } |
9096 | } |
- | 9097 | ||
- | 9098 | /* Is 'a' after or equal to 'b'? */ |
|
- | 9099 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
|
- | 9100 | { |
|
- | 9101 | return !((a - b) & 0x80000000); |
|
- | 9102 | } |
|
- | 9103 | ||
- | 9104 | static bool page_flip_finished(struct intel_crtc *crtc) |
|
- | 9105 | { |
|
- | 9106 | struct drm_device *dev = crtc->base.dev; |
|
- | 9107 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 9108 | ||
- | 9109 | /* |
|
- | 9110 | * The relevant registers doen't exist on pre-ctg. |
|
- | 9111 | * As the flip done interrupt doesn't trigger for mmio |
|
- | 9112 | * flips on gmch platforms, a flip count check isn't |
|
- | 9113 | * really needed there. But since ctg has the registers, |
|
- | 9114 | * include it in the check anyway. |
|
- | 9115 | */ |
|
- | 9116 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
|
- | 9117 | return true; |
|
- | 9118 | ||
- | 9119 | /* |
|
- | 9120 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
|
- | 9121 | * used the same base address. In that case the mmio flip might |
|
- | 9122 | * have completed, but the CS hasn't even executed the flip yet. |
|
- | 9123 | * |
|
- | 9124 | * A flip count check isn't enough as the CS might have updated |
|
- | 9125 | * the base address just after start of vblank, but before we |
|
- | 9126 | * managed to process the interrupt. This means we'd complete the |
|
- | 9127 | * CS flip too soon. |
|
- | 9128 | * |
|
- | 9129 | * Combining both checks should get us a good enough result. It may |
|
- | 9130 | * still happen that the CS flip has been executed, but has not |
|
- | 9131 | * yet actually completed. But in case the base address is the same |
|
- | 9132 | * anyway, we don't really care. |
|
- | 9133 | */ |
|
- | 9134 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
|
- | 9135 | crtc->unpin_work->gtt_offset && |
|
- | 9136 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), |
|
- | 9137 | crtc->unpin_work->flip_count); |
|
- | 9138 | } |
|
8324 | 9139 | ||
8325 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9140 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8326 | { |
9141 | { |
8327 | drm_i915_private_t *dev_priv = dev->dev_private; |
9142 | struct drm_i915_private *dev_priv = dev->dev_private; |
8328 | struct intel_crtc *intel_crtc = |
9143 | struct intel_crtc *intel_crtc = |
8329 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
9144 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
8330 | unsigned long flags; |
9145 | unsigned long flags; |
8331 | 9146 | ||
8332 | /* NB: An MMIO update of the plane base pointer will also |
9147 | /* NB: An MMIO update of the plane base pointer will also |
8333 | * generate a page-flip completion irq, i.e. every modeset |
9148 | * generate a page-flip completion irq, i.e. every modeset |
8334 | * is also accompanied by a spurious intel_prepare_page_flip(). |
9149 | * is also accompanied by a spurious intel_prepare_page_flip(). |
8335 | */ |
9150 | */ |
8336 | spin_lock_irqsave(&dev->event_lock, flags); |
9151 | spin_lock_irqsave(&dev->event_lock, flags); |
8337 | if (intel_crtc->unpin_work) |
9152 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
8338 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
9153 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
8339 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9154 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8340 | } |
9155 | } |
8341 | 9156 | ||
8342 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
9157 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8343 | { |
9158 | { |
8344 | /* Ensure that the work item is consistent when activating it ... */ |
9159 | /* Ensure that the work item is consistent when activating it ... */ |
8345 | smp_wmb(); |
9160 | smp_wmb(); |
8346 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
9161 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
8347 | /* and that it is marked active as soon as the irq could fire. */ |
9162 | /* and that it is marked active as soon as the irq could fire. */ |
8348 | smp_wmb(); |
9163 | smp_wmb(); |
8349 | } |
9164 | } |
8350 | 9165 | ||
8351 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9166 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8352 | struct drm_crtc *crtc, |
9167 | struct drm_crtc *crtc, |
8353 | struct drm_framebuffer *fb, |
9168 | struct drm_framebuffer *fb, |
8354 | struct drm_i915_gem_object *obj, |
9169 | struct drm_i915_gem_object *obj, |
- | 9170 | struct intel_engine_cs *ring, |
|
8355 | uint32_t flags) |
9171 | uint32_t flags) |
8356 | { |
9172 | { |
8357 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8359 | u32 flip_mask; |
9174 | u32 flip_mask; |
8360 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | |
8361 | int ret; |
9175 | int ret; |
8362 | - | ||
8363 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8364 | if (ret) |
- | |
8365 | goto err; |
- | |
8366 | 9176 | ||
8367 | ret = intel_ring_begin(ring, 6); |
9177 | ret = intel_ring_begin(ring, 6); |
8368 | if (ret) |
9178 | if (ret) |
8369 | goto err_unpin; |
9179 | return ret; |
8370 | 9180 | ||
8371 | /* Can't queue multiple flips, so wait for the previous |
9181 | /* Can't queue multiple flips, so wait for the previous |
8372 | * one to finish before executing the next. |
9182 | * one to finish before executing the next. |
8373 | */ |
9183 | */ |
8374 | if (intel_crtc->plane) |
9184 | if (intel_crtc->plane) |
8375 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
9185 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
8376 | else |
9186 | else |
8377 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
9187 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
8378 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9188 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8379 | intel_ring_emit(ring, MI_NOOP); |
9189 | intel_ring_emit(ring, MI_NOOP); |
8380 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9190 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8381 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9191 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8382 | intel_ring_emit(ring, fb->pitches[0]); |
9192 | intel_ring_emit(ring, fb->pitches[0]); |
8383 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9193 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8384 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
9194 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
8385 | 9195 | ||
8386 | intel_mark_page_flip_active(intel_crtc); |
9196 | intel_mark_page_flip_active(intel_crtc); |
8387 | __intel_ring_advance(ring); |
9197 | __intel_ring_advance(ring); |
8388 | return 0; |
9198 | return 0; |
8389 | - | ||
8390 | err_unpin: |
- | |
8391 | intel_unpin_fb_obj(obj); |
- | |
8392 | err: |
- | |
8393 | return ret; |
- | |
8394 | } |
9199 | } |
8395 | 9200 | ||
8396 | static int intel_gen3_queue_flip(struct drm_device *dev, |
9201 | static int intel_gen3_queue_flip(struct drm_device *dev, |
8397 | struct drm_crtc *crtc, |
9202 | struct drm_crtc *crtc, |
8398 | struct drm_framebuffer *fb, |
9203 | struct drm_framebuffer *fb, |
8399 | struct drm_i915_gem_object *obj, |
9204 | struct drm_i915_gem_object *obj, |
- | 9205 | struct intel_engine_cs *ring, |
|
8400 | uint32_t flags) |
9206 | uint32_t flags) |
8401 | { |
9207 | { |
8402 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8404 | u32 flip_mask; |
9209 | u32 flip_mask; |
8405 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | |
8406 | int ret; |
9210 | int ret; |
8407 | - | ||
8408 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8409 | if (ret) |
- | |
8410 | goto err; |
- | |
8411 | 9211 | ||
8412 | ret = intel_ring_begin(ring, 6); |
9212 | ret = intel_ring_begin(ring, 6); |
8413 | if (ret) |
9213 | if (ret) |
8414 | goto err_unpin; |
9214 | return ret; |
8415 | 9215 | ||
8416 | if (intel_crtc->plane) |
9216 | if (intel_crtc->plane) |
8417 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
9217 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
8418 | else |
9218 | else |
8419 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
9219 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
8420 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9220 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8421 | intel_ring_emit(ring, MI_NOOP); |
9221 | intel_ring_emit(ring, MI_NOOP); |
8422 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
9222 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
8423 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9223 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8424 | intel_ring_emit(ring, fb->pitches[0]); |
9224 | intel_ring_emit(ring, fb->pitches[0]); |
8425 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9225 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8426 | intel_ring_emit(ring, MI_NOOP); |
9226 | intel_ring_emit(ring, MI_NOOP); |
8427 | 9227 | ||
8428 | intel_mark_page_flip_active(intel_crtc); |
9228 | intel_mark_page_flip_active(intel_crtc); |
8429 | __intel_ring_advance(ring); |
9229 | __intel_ring_advance(ring); |
8430 | return 0; |
9230 | return 0; |
8431 | - | ||
8432 | err_unpin: |
- | |
8433 | intel_unpin_fb_obj(obj); |
- | |
8434 | err: |
- | |
8435 | return ret; |
- | |
8436 | } |
9231 | } |
8437 | 9232 | ||
8438 | static int intel_gen4_queue_flip(struct drm_device *dev, |
9233 | static int intel_gen4_queue_flip(struct drm_device *dev, |
8439 | struct drm_crtc *crtc, |
9234 | struct drm_crtc *crtc, |
8440 | struct drm_framebuffer *fb, |
9235 | struct drm_framebuffer *fb, |
8441 | struct drm_i915_gem_object *obj, |
9236 | struct drm_i915_gem_object *obj, |
- | 9237 | struct intel_engine_cs *ring, |
|
8442 | uint32_t flags) |
9238 | uint32_t flags) |
8443 | { |
9239 | { |
8444 | struct drm_i915_private *dev_priv = dev->dev_private; |
9240 | struct drm_i915_private *dev_priv = dev->dev_private; |
8445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8446 | uint32_t pf, pipesrc; |
9242 | uint32_t pf, pipesrc; |
8447 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | |
8448 | int ret; |
9243 | int ret; |
8449 | - | ||
8450 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8451 | if (ret) |
- | |
8452 | goto err; |
- | |
8453 | 9244 | ||
8454 | ret = intel_ring_begin(ring, 4); |
9245 | ret = intel_ring_begin(ring, 4); |
8455 | if (ret) |
9246 | if (ret) |
8456 | goto err_unpin; |
9247 | return ret; |
8457 | 9248 | ||
8458 | /* i965+ uses the linear or tiled offsets from the |
9249 | /* i965+ uses the linear or tiled offsets from the |
8459 | * Display Registers (which do not change across a page-flip) |
9250 | * Display Registers (which do not change across a page-flip) |
8460 | * so we need only reprogram the base address. |
9251 | * so we need only reprogram the base address. |
8461 | */ |
9252 | */ |
8462 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9253 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8463 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9254 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8464 | intel_ring_emit(ring, fb->pitches[0]); |
9255 | intel_ring_emit(ring, fb->pitches[0]); |
8465 | intel_ring_emit(ring, |
- | |
8466 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
9256 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
8467 | obj->tiling_mode); |
9257 | obj->tiling_mode); |
8468 | 9258 | ||
8469 | /* XXX Enabling the panel-fitter across page-flip is so far |
9259 | /* XXX Enabling the panel-fitter across page-flip is so far |
8470 | * untested on non-native modes, so ignore it for now. |
9260 | * untested on non-native modes, so ignore it for now. |
8471 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
9261 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
8472 | */ |
9262 | */ |
8473 | pf = 0; |
9263 | pf = 0; |
8474 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
9264 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8475 | intel_ring_emit(ring, pf | pipesrc); |
9265 | intel_ring_emit(ring, pf | pipesrc); |
8476 | 9266 | ||
8477 | intel_mark_page_flip_active(intel_crtc); |
9267 | intel_mark_page_flip_active(intel_crtc); |
8478 | __intel_ring_advance(ring); |
9268 | __intel_ring_advance(ring); |
8479 | return 0; |
9269 | return 0; |
8480 | - | ||
8481 | err_unpin: |
- | |
8482 | intel_unpin_fb_obj(obj); |
- | |
8483 | err: |
- | |
8484 | return ret; |
- | |
8485 | } |
9270 | } |
8486 | 9271 | ||
8487 | static int intel_gen6_queue_flip(struct drm_device *dev, |
9272 | static int intel_gen6_queue_flip(struct drm_device *dev, |
8488 | struct drm_crtc *crtc, |
9273 | struct drm_crtc *crtc, |
8489 | struct drm_framebuffer *fb, |
9274 | struct drm_framebuffer *fb, |
8490 | struct drm_i915_gem_object *obj, |
9275 | struct drm_i915_gem_object *obj, |
- | 9276 | struct intel_engine_cs *ring, |
|
8491 | uint32_t flags) |
9277 | uint32_t flags) |
8492 | { |
9278 | { |
8493 | struct drm_i915_private *dev_priv = dev->dev_private; |
9279 | struct drm_i915_private *dev_priv = dev->dev_private; |
8494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8495 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | |
8496 | uint32_t pf, pipesrc; |
9281 | uint32_t pf, pipesrc; |
8497 | int ret; |
9282 | int ret; |
8498 | - | ||
8499 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8500 | if (ret) |
- | |
8501 | goto err; |
- | |
8502 | 9283 | ||
8503 | ret = intel_ring_begin(ring, 4); |
9284 | ret = intel_ring_begin(ring, 4); |
8504 | if (ret) |
9285 | if (ret) |
8505 | goto err_unpin; |
9286 | return ret; |
8506 | 9287 | ||
8507 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9288 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8508 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9289 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8509 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
9290 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
8510 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9291 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8511 | 9292 | ||
8512 | /* Contrary to the suggestions in the documentation, |
9293 | /* Contrary to the suggestions in the documentation, |
8513 | * "Enable Panel Fitter" does not seem to be required when page |
9294 | * "Enable Panel Fitter" does not seem to be required when page |
8514 | * flipping with a non-native mode, and worse causes a normal |
9295 | * flipping with a non-native mode, and worse causes a normal |
8515 | * modeset to fail. |
9296 | * modeset to fail. |
8516 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
9297 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
8517 | */ |
9298 | */ |
8518 | pf = 0; |
9299 | pf = 0; |
8519 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
9300 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8520 | intel_ring_emit(ring, pf | pipesrc); |
9301 | intel_ring_emit(ring, pf | pipesrc); |
8521 | 9302 | ||
8522 | intel_mark_page_flip_active(intel_crtc); |
9303 | intel_mark_page_flip_active(intel_crtc); |
8523 | __intel_ring_advance(ring); |
9304 | __intel_ring_advance(ring); |
8524 | return 0; |
9305 | return 0; |
8525 | - | ||
8526 | err_unpin: |
- | |
8527 | intel_unpin_fb_obj(obj); |
- | |
8528 | err: |
- | |
8529 | return ret; |
- | |
8530 | } |
9306 | } |
8531 | 9307 | ||
8532 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9308 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8533 | struct drm_crtc *crtc, |
9309 | struct drm_crtc *crtc, |
8534 | struct drm_framebuffer *fb, |
9310 | struct drm_framebuffer *fb, |
8535 | struct drm_i915_gem_object *obj, |
9311 | struct drm_i915_gem_object *obj, |
- | 9312 | struct intel_engine_cs *ring, |
|
8536 | uint32_t flags) |
9313 | uint32_t flags) |
8537 | { |
9314 | { |
8538 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8540 | struct intel_ring_buffer *ring; |
- | |
8541 | uint32_t plane_bit = 0; |
9316 | uint32_t plane_bit = 0; |
8542 | int len, ret; |
9317 | int len, ret; |
8543 | - | ||
8544 | ring = obj->ring; |
- | |
8545 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
- | |
8546 | ring = &dev_priv->ring[BCS]; |
- | |
8547 | - | ||
8548 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8549 | if (ret) |
- | |
8550 | goto err; |
- | |
8551 | 9318 | ||
8552 | switch(intel_crtc->plane) { |
9319 | switch (intel_crtc->plane) { |
8553 | case PLANE_A: |
9320 | case PLANE_A: |
8554 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
9321 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
8555 | break; |
9322 | break; |
8556 | case PLANE_B: |
9323 | case PLANE_B: |
8557 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
9324 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
8558 | break; |
9325 | break; |
8559 | case PLANE_C: |
9326 | case PLANE_C: |
8560 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
9327 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
8561 | break; |
9328 | break; |
8562 | default: |
9329 | default: |
8563 | WARN_ONCE(1, "unknown plane in flip command\n"); |
9330 | WARN_ONCE(1, "unknown plane in flip command\n"); |
8564 | ret = -ENODEV; |
9331 | return -ENODEV; |
8565 | goto err_unpin; |
- | |
8566 | } |
9332 | } |
8567 | 9333 | ||
8568 | len = 4; |
9334 | len = 4; |
8569 | if (ring->id == RCS) |
9335 | if (ring->id == RCS) { |
8570 | len += 6; |
9336 | len += 6; |
- | 9337 | /* |
|
- | 9338 | * On Gen 8, SRM is now taking an extra dword to accommodate |
|
- | 9339 | * 48bits addresses, and we need a NOOP for the batch size to |
|
- | 9340 | * stay even. |
|
- | 9341 | */ |
|
- | 9342 | if (IS_GEN8(dev)) |
|
- | 9343 | len += 2; |
|
- | 9344 | } |
|
- | 9345 | ||
- | 9346 | /* |
|
- | 9347 | * BSpec MI_DISPLAY_FLIP for IVB: |
|
- | 9348 | * "The full packet must be contained within the same cache line." |
|
- | 9349 | * |
|
- | 9350 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
|
- | 9351 | * cacheline, if we ever start emitting more commands before |
|
- | 9352 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
|
- | 9353 | * then do the cacheline alignment, and finally emit the |
|
- | 9354 | * MI_DISPLAY_FLIP. |
|
- | 9355 | */ |
|
- | 9356 | ret = intel_ring_cacheline_align(ring); |
|
- | 9357 | if (ret) |
|
- | 9358 | return ret; |
|
8571 | 9359 | ||
8572 | ret = intel_ring_begin(ring, len); |
9360 | ret = intel_ring_begin(ring, len); |
8573 | if (ret) |
9361 | if (ret) |
8574 | goto err_unpin; |
9362 | return ret; |
8575 | 9363 | ||
8576 | /* Unmask the flip-done completion message. Note that the bspec says that |
9364 | /* Unmask the flip-done completion message. Note that the bspec says that |
8577 | * we should do this for both the BCS and RCS, and that we must not unmask |
9365 | * we should do this for both the BCS and RCS, and that we must not unmask |
8578 | * more than one flip event at any time (or ensure that one flip message |
9366 | * more than one flip event at any time (or ensure that one flip message |
8579 | * can be sent by waiting for flip-done prior to queueing new flips). |
9367 | * can be sent by waiting for flip-done prior to queueing new flips). |
8580 | * Experimentation says that BCS works despite DERRMR masking all |
9368 | * Experimentation says that BCS works despite DERRMR masking all |
8581 | * flip-done completion events and that unmasking all planes at once |
9369 | * flip-done completion events and that unmasking all planes at once |
8582 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
9370 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
8583 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
9371 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
8584 | */ |
9372 | */ |
8585 | if (ring->id == RCS) { |
9373 | if (ring->id == RCS) { |
8586 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
9374 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
8587 | intel_ring_emit(ring, DERRMR); |
9375 | intel_ring_emit(ring, DERRMR); |
8588 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
9376 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8589 | DERRMR_PIPEB_PRI_FLIP_DONE | |
9377 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8590 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
9378 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
- | 9379 | if (IS_GEN8(dev)) |
|
- | 9380 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | |
|
- | 9381 | MI_SRM_LRM_GLOBAL_GTT); |
|
- | 9382 | else |
|
8591 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
9383 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8592 | MI_SRM_LRM_GLOBAL_GTT); |
9384 | MI_SRM_LRM_GLOBAL_GTT); |
8593 | intel_ring_emit(ring, DERRMR); |
9385 | intel_ring_emit(ring, DERRMR); |
8594 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
9386 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
- | 9387 | if (IS_GEN8(dev)) { |
|
- | 9388 | intel_ring_emit(ring, 0); |
|
- | 9389 | intel_ring_emit(ring, MI_NOOP); |
|
- | 9390 | } |
|
8595 | } |
9391 | } |
8596 | 9392 | ||
8597 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
9393 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
8598 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
9394 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
8599 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9395 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8600 | intel_ring_emit(ring, (MI_NOOP)); |
9396 | intel_ring_emit(ring, (MI_NOOP)); |
8601 | 9397 | ||
8602 | intel_mark_page_flip_active(intel_crtc); |
9398 | intel_mark_page_flip_active(intel_crtc); |
8603 | __intel_ring_advance(ring); |
9399 | __intel_ring_advance(ring); |
8604 | return 0; |
9400 | return 0; |
8605 | - | ||
8606 | err_unpin: |
- | |
8607 | intel_unpin_fb_obj(obj); |
- | |
8608 | err: |
- | |
8609 | return ret; |
- | |
8610 | } |
9401 | } |
8611 | 9402 | ||
8612 | static int intel_default_queue_flip(struct drm_device *dev, |
9403 | static int intel_default_queue_flip(struct drm_device *dev, |
8613 | struct drm_crtc *crtc, |
9404 | struct drm_crtc *crtc, |
8614 | struct drm_framebuffer *fb, |
9405 | struct drm_framebuffer *fb, |
8615 | struct drm_i915_gem_object *obj, |
9406 | struct drm_i915_gem_object *obj, |
- | 9407 | struct intel_engine_cs *ring, |
|
8616 | uint32_t flags) |
9408 | uint32_t flags) |
8617 | { |
9409 | { |
8618 | return -ENODEV; |
9410 | return -ENODEV; |
8619 | } |
9411 | } |
8620 | 9412 | ||
8621 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9413 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8622 | struct drm_framebuffer *fb, |
9414 | struct drm_framebuffer *fb, |
8623 | struct drm_pending_vblank_event *event, |
9415 | struct drm_pending_vblank_event *event, |
8624 | uint32_t page_flip_flags) |
9416 | uint32_t page_flip_flags) |
8625 | { |
9417 | { |
8626 | struct drm_device *dev = crtc->dev; |
9418 | struct drm_device *dev = crtc->dev; |
8627 | struct drm_i915_private *dev_priv = dev->dev_private; |
9419 | struct drm_i915_private *dev_priv = dev->dev_private; |
8628 | struct drm_framebuffer *old_fb = crtc->fb; |
9420 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
8629 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
9421 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
8630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 9423 | enum pipe pipe = intel_crtc->pipe; |
|
8631 | struct intel_unpin_work *work; |
9424 | struct intel_unpin_work *work; |
- | 9425 | struct intel_engine_cs *ring; |
|
8632 | unsigned long flags; |
9426 | unsigned long flags; |
8633 | int ret; |
9427 | int ret; |
- | 9428 | ||
- | 9429 | /* |
|
- | 9430 | * drm_mode_page_flip_ioctl() should already catch this, but double |
|
- | 9431 | * check to be safe. In the future we may enable pageflipping from |
|
- | 9432 | * a disabled primary plane. |
|
- | 9433 | */ |
|
- | 9434 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
|
- | 9435 | return -EBUSY; |
|
8634 | 9436 | ||
8635 | /* Can't change pixel format via MI display flips. */ |
9437 | /* Can't change pixel format via MI display flips. */ |
8636 | if (fb->pixel_format != crtc->fb->pixel_format) |
9438 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
8637 | return -EINVAL; |
9439 | return -EINVAL; |
8638 | 9440 | ||
8639 | /* |
9441 | /* |
8640 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
9442 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
8641 | * Note that pitch changes could also affect these register. |
9443 | * Note that pitch changes could also affect these register. |
8642 | */ |
9444 | */ |
8643 | if (INTEL_INFO(dev)->gen > 3 && |
9445 | if (INTEL_INFO(dev)->gen > 3 && |
8644 | (fb->offsets[0] != crtc->fb->offsets[0] || |
9446 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
8645 | fb->pitches[0] != crtc->fb->pitches[0])) |
9447 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
8646 | return -EINVAL; |
9448 | return -EINVAL; |
8647 | 9449 | ||
8648 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
9450 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
8649 | if (work == NULL) |
9451 | if (work == NULL) |
8650 | return -ENOMEM; |
9452 | return -ENOMEM; |
8651 | 9453 | ||
8652 | work->event = event; |
9454 | work->event = event; |
8653 | work->crtc = crtc; |
9455 | work->crtc = crtc; |
8654 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
9456 | work->old_fb_obj = intel_fb_obj(old_fb); |
8655 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9457 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8656 | 9458 | ||
8657 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
9459 | ret = drm_crtc_vblank_get(crtc); |
8658 | if (ret) |
9460 | if (ret) |
8659 | goto free_work; |
9461 | goto free_work; |
8660 | 9462 | ||
8661 | /* We borrow the event spin lock for protecting unpin_work */ |
9463 | /* We borrow the event spin lock for protecting unpin_work */ |
8662 | spin_lock_irqsave(&dev->event_lock, flags); |
9464 | spin_lock_irqsave(&dev->event_lock, flags); |
8663 | if (intel_crtc->unpin_work) { |
9465 | if (intel_crtc->unpin_work) { |
8664 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9466 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8665 | kfree(work); |
9467 | kfree(work); |
8666 | drm_vblank_put(dev, intel_crtc->pipe); |
9468 | drm_crtc_vblank_put(crtc); |
8667 | 9469 | ||
8668 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
9470 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
8669 | return -EBUSY; |
9471 | return -EBUSY; |
8670 | } |
9472 | } |
8671 | intel_crtc->unpin_work = work; |
9473 | intel_crtc->unpin_work = work; |
8672 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9474 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8673 | 9475 | ||
8674 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9476 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8675 | flush_workqueue(dev_priv->wq); |
9477 | flush_workqueue(dev_priv->wq); |
8676 | 9478 | ||
8677 | ret = i915_mutex_lock_interruptible(dev); |
9479 | ret = i915_mutex_lock_interruptible(dev); |
8678 | if (ret) |
9480 | if (ret) |
8679 | goto cleanup; |
9481 | goto cleanup; |
8680 | 9482 | ||
8681 | /* Reference the objects for the scheduled work. */ |
9483 | /* Reference the objects for the scheduled work. */ |
8682 | drm_gem_object_reference(&work->old_fb_obj->base); |
9484 | drm_gem_object_reference(&work->old_fb_obj->base); |
8683 | drm_gem_object_reference(&obj->base); |
9485 | drm_gem_object_reference(&obj->base); |
8684 | 9486 | ||
8685 | crtc->fb = fb; |
9487 | crtc->primary->fb = fb; |
8686 | 9488 | ||
8687 | work->pending_flip_obj = obj; |
9489 | work->pending_flip_obj = obj; |
8688 | 9490 | ||
8689 | work->enable_stall_check = true; |
9491 | work->enable_stall_check = true; |
8690 | 9492 | ||
8691 | atomic_inc(&intel_crtc->unpin_work_count); |
9493 | atomic_inc(&intel_crtc->unpin_work_count); |
8692 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
9494 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
- | 9495 | ||
- | 9496 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
|
- | 9497 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
|
- | 9498 | ||
- | 9499 | if (IS_VALLEYVIEW(dev)) { |
|
- | 9500 | ring = &dev_priv->ring[BCS]; |
|
- | 9501 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
|
- | 9502 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
|
- | 9503 | ring = NULL; |
|
- | 9504 | } else if (IS_IVYBRIDGE(dev)) { |
|
- | 9505 | ring = &dev_priv->ring[BCS]; |
|
- | 9506 | } else if (INTEL_INFO(dev)->gen >= 7) { |
|
- | 9507 | ring = obj->ring; |
|
- | 9508 | if (ring == NULL || ring->id != RCS) |
|
- | 9509 | ring = &dev_priv->ring[BCS]; |
|
- | 9510 | } else { |
|
- | 9511 | ring = &dev_priv->ring[RCS]; |
|
- | 9512 | } |
|
8693 | 9513 | ||
8694 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
9514 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8695 | if (ret) |
9515 | if (ret) |
8696 | goto cleanup_pending; |
9516 | goto cleanup_pending; |
- | 9517 | ||
- | 9518 | work->gtt_offset = |
|
- | 9519 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; |
|
- | 9520 | ||
- | 9521 | if (use_mmio_flip(ring, obj)) |
|
- | 9522 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
|
- | 9523 | page_flip_flags); |
|
- | 9524 | else |
|
- | 9525 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
|
- | 9526 | page_flip_flags); |
|
- | 9527 | if (ret) |
|
- | 9528 | goto cleanup_unpin; |
|
- | 9529 | ||
- | 9530 | i915_gem_track_fb(work->old_fb_obj, obj, |
|
- | 9531 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
8697 | 9532 | ||
8698 | intel_disable_fbc(dev); |
9533 | intel_disable_fbc(dev); |
8699 | intel_mark_fb_busy(obj, NULL); |
9534 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8700 | mutex_unlock(&dev->struct_mutex); |
9535 | mutex_unlock(&dev->struct_mutex); |
8701 | 9536 | ||
8702 | trace_i915_flip_request(intel_crtc->plane, obj); |
9537 | trace_i915_flip_request(intel_crtc->plane, obj); |
8703 | 9538 | ||
8704 | return 0; |
9539 | return 0; |
- | 9540 | ||
- | 9541 | cleanup_unpin: |
|
8705 | 9542 | intel_unpin_fb_obj(obj); |
|
8706 | cleanup_pending: |
9543 | cleanup_pending: |
8707 | atomic_dec(&intel_crtc->unpin_work_count); |
9544 | atomic_dec(&intel_crtc->unpin_work_count); |
8708 | crtc->fb = old_fb; |
9545 | crtc->primary->fb = old_fb; |
8709 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9546 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8710 | drm_gem_object_unreference(&obj->base); |
9547 | drm_gem_object_unreference(&obj->base); |
8711 | mutex_unlock(&dev->struct_mutex); |
9548 | mutex_unlock(&dev->struct_mutex); |
8712 | 9549 | ||
8713 | cleanup: |
9550 | cleanup: |
8714 | spin_lock_irqsave(&dev->event_lock, flags); |
9551 | spin_lock_irqsave(&dev->event_lock, flags); |
8715 | intel_crtc->unpin_work = NULL; |
9552 | intel_crtc->unpin_work = NULL; |
8716 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9553 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8717 | 9554 | ||
8718 | drm_vblank_put(dev, intel_crtc->pipe); |
9555 | drm_crtc_vblank_put(crtc); |
8719 | free_work: |
9556 | free_work: |
8720 | kfree(work); |
9557 | kfree(work); |
- | 9558 | ||
- | 9559 | if (ret == -EIO) { |
|
- | 9560 | out_hang: |
|
- | 9561 | intel_crtc_wait_for_pending_flips(crtc); |
|
- | 9562 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); |
|
- | 9563 | if (ret == 0 && event) |
|
- | 9564 | drm_send_vblank_event(dev, pipe, event); |
|
8721 | 9565 | } |
|
8722 | return ret; |
9566 | return ret; |
8723 | } |
9567 | } |
8724 | #endif |
9568 | #endif |
8725 | 9569 | ||
8726 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
9570 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8727 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9571 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8728 | .load_lut = intel_crtc_load_lut, |
9572 | .load_lut = intel_crtc_load_lut, |
8729 | }; |
9573 | }; |
8730 | 9574 | ||
8731 | /** |
9575 | /** |
8732 | * intel_modeset_update_staged_output_state |
9576 | * intel_modeset_update_staged_output_state |
8733 | * |
9577 | * |
8734 | * Updates the staged output configuration state, e.g. after we've read out the |
9578 | * Updates the staged output configuration state, e.g. after we've read out the |
8735 | * current hw state. |
9579 | * current hw state. |
8736 | */ |
9580 | */ |
8737 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
9581 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8738 | { |
9582 | { |
- | 9583 | struct intel_crtc *crtc; |
|
8739 | struct intel_encoder *encoder; |
9584 | struct intel_encoder *encoder; |
8740 | struct intel_connector *connector; |
9585 | struct intel_connector *connector; |
8741 | 9586 | ||
8742 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9587 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8743 | base.head) { |
9588 | base.head) { |
8744 | connector->new_encoder = |
9589 | connector->new_encoder = |
8745 | to_intel_encoder(connector->base.encoder); |
9590 | to_intel_encoder(connector->base.encoder); |
8746 | } |
9591 | } |
8747 | 9592 | ||
8748 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9593 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8749 | base.head) { |
9594 | base.head) { |
8750 | encoder->new_crtc = |
9595 | encoder->new_crtc = |
8751 | to_intel_crtc(encoder->base.crtc); |
9596 | to_intel_crtc(encoder->base.crtc); |
8752 | } |
9597 | } |
- | 9598 | ||
- | 9599 | for_each_intel_crtc(dev, crtc) { |
|
- | 9600 | crtc->new_enabled = crtc->base.enabled; |
|
- | 9601 | ||
- | 9602 | if (crtc->new_enabled) |
|
- | 9603 | crtc->new_config = &crtc->config; |
|
- | 9604 | else |
|
- | 9605 | crtc->new_config = NULL; |
|
- | 9606 | } |
|
8753 | } |
9607 | } |
8754 | 9608 | ||
8755 | /** |
9609 | /** |
8756 | * intel_modeset_commit_output_state |
9610 | * intel_modeset_commit_output_state |
8757 | * |
9611 | * |
8758 | * This function copies the stage display pipe configuration to the real one. |
9612 | * This function copies the stage display pipe configuration to the real one. |
8759 | */ |
9613 | */ |
8760 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
9614 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
8761 | { |
9615 | { |
- | 9616 | struct intel_crtc *crtc; |
|
8762 | struct intel_encoder *encoder; |
9617 | struct intel_encoder *encoder; |
8763 | struct intel_connector *connector; |
9618 | struct intel_connector *connector; |
8764 | 9619 | ||
8765 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9620 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8766 | base.head) { |
9621 | base.head) { |
8767 | connector->base.encoder = &connector->new_encoder->base; |
9622 | connector->base.encoder = &connector->new_encoder->base; |
8768 | } |
9623 | } |
8769 | 9624 | ||
8770 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9625 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8771 | base.head) { |
9626 | base.head) { |
8772 | encoder->base.crtc = &encoder->new_crtc->base; |
9627 | encoder->base.crtc = &encoder->new_crtc->base; |
8773 | } |
9628 | } |
- | 9629 | ||
- | 9630 | for_each_intel_crtc(dev, crtc) { |
|
- | 9631 | crtc->base.enabled = crtc->new_enabled; |
|
- | 9632 | } |
|
8774 | } |
9633 | } |
8775 | 9634 | ||
8776 | static void |
9635 | static void |
8777 | connected_sink_compute_bpp(struct intel_connector * connector, |
9636 | connected_sink_compute_bpp(struct intel_connector *connector, |
8778 | struct intel_crtc_config *pipe_config) |
9637 | struct intel_crtc_config *pipe_config) |
8779 | { |
9638 | { |
8780 | int bpp = pipe_config->pipe_bpp; |
9639 | int bpp = pipe_config->pipe_bpp; |
8781 | 9640 | ||
8782 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
9641 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8783 | connector->base.base.id, |
9642 | connector->base.base.id, |
8784 | drm_get_connector_name(&connector->base)); |
9643 | connector->base.name); |
8785 | 9644 | ||
8786 | /* Don't use an invalid EDID bpc value */ |
9645 | /* Don't use an invalid EDID bpc value */ |
8787 | if (connector->base.display_info.bpc && |
9646 | if (connector->base.display_info.bpc && |
8788 | connector->base.display_info.bpc * 3 < bpp) { |
9647 | connector->base.display_info.bpc * 3 < bpp) { |
8789 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
9648 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
8790 | bpp, connector->base.display_info.bpc*3); |
9649 | bpp, connector->base.display_info.bpc*3); |
8791 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
9650 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
8792 | } |
9651 | } |
8793 | 9652 | ||
8794 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
9653 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
8795 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
9654 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
8796 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
9655 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
8797 | bpp); |
9656 | bpp); |
8798 | pipe_config->pipe_bpp = 24; |
9657 | pipe_config->pipe_bpp = 24; |
8799 | } |
9658 | } |
8800 | } |
9659 | } |
8801 | 9660 | ||
8802 | static int |
9661 | static int |
8803 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9662 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8804 | struct drm_framebuffer *fb, |
9663 | struct drm_framebuffer *fb, |
8805 | struct intel_crtc_config *pipe_config) |
9664 | struct intel_crtc_config *pipe_config) |
8806 | { |
9665 | { |
8807 | struct drm_device *dev = crtc->base.dev; |
9666 | struct drm_device *dev = crtc->base.dev; |
8808 | struct intel_connector *connector; |
9667 | struct intel_connector *connector; |
8809 | int bpp; |
9668 | int bpp; |
8810 | 9669 | ||
8811 | switch (fb->pixel_format) { |
9670 | switch (fb->pixel_format) { |
8812 | case DRM_FORMAT_C8: |
9671 | case DRM_FORMAT_C8: |
8813 | bpp = 8*3; /* since we go through a colormap */ |
9672 | bpp = 8*3; /* since we go through a colormap */ |
8814 | break; |
9673 | break; |
8815 | case DRM_FORMAT_XRGB1555: |
9674 | case DRM_FORMAT_XRGB1555: |
8816 | case DRM_FORMAT_ARGB1555: |
9675 | case DRM_FORMAT_ARGB1555: |
8817 | /* checked in intel_framebuffer_init already */ |
9676 | /* checked in intel_framebuffer_init already */ |
8818 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
9677 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
8819 | return -EINVAL; |
9678 | return -EINVAL; |
8820 | case DRM_FORMAT_RGB565: |
9679 | case DRM_FORMAT_RGB565: |
8821 | bpp = 6*3; /* min is 18bpp */ |
9680 | bpp = 6*3; /* min is 18bpp */ |
8822 | break; |
9681 | break; |
8823 | case DRM_FORMAT_XBGR8888: |
9682 | case DRM_FORMAT_XBGR8888: |
8824 | case DRM_FORMAT_ABGR8888: |
9683 | case DRM_FORMAT_ABGR8888: |
8825 | /* checked in intel_framebuffer_init already */ |
9684 | /* checked in intel_framebuffer_init already */ |
8826 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
9685 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8827 | return -EINVAL; |
9686 | return -EINVAL; |
8828 | case DRM_FORMAT_XRGB8888: |
9687 | case DRM_FORMAT_XRGB8888: |
8829 | case DRM_FORMAT_ARGB8888: |
9688 | case DRM_FORMAT_ARGB8888: |
8830 | bpp = 8*3; |
9689 | bpp = 8*3; |
8831 | break; |
9690 | break; |
8832 | case DRM_FORMAT_XRGB2101010: |
9691 | case DRM_FORMAT_XRGB2101010: |
8833 | case DRM_FORMAT_ARGB2101010: |
9692 | case DRM_FORMAT_ARGB2101010: |
8834 | case DRM_FORMAT_XBGR2101010: |
9693 | case DRM_FORMAT_XBGR2101010: |
8835 | case DRM_FORMAT_ABGR2101010: |
9694 | case DRM_FORMAT_ABGR2101010: |
8836 | /* checked in intel_framebuffer_init already */ |
9695 | /* checked in intel_framebuffer_init already */ |
8837 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
9696 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8838 | return -EINVAL; |
9697 | return -EINVAL; |
8839 | bpp = 10*3; |
9698 | bpp = 10*3; |
8840 | break; |
9699 | break; |
8841 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
9700 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
8842 | default: |
9701 | default: |
8843 | DRM_DEBUG_KMS("unsupported depth\n"); |
9702 | DRM_DEBUG_KMS("unsupported depth\n"); |
8844 | return -EINVAL; |
9703 | return -EINVAL; |
8845 | } |
9704 | } |
8846 | 9705 | ||
8847 | pipe_config->pipe_bpp = bpp; |
9706 | pipe_config->pipe_bpp = bpp; |
8848 | 9707 | ||
8849 | /* Clamp display bpp to EDID value */ |
9708 | /* Clamp display bpp to EDID value */ |
8850 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9709 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8851 | base.head) { |
9710 | base.head) { |
8852 | if (!connector->new_encoder || |
9711 | if (!connector->new_encoder || |
8853 | connector->new_encoder->new_crtc != crtc) |
9712 | connector->new_encoder->new_crtc != crtc) |
8854 | continue; |
9713 | continue; |
8855 | 9714 | ||
8856 | connected_sink_compute_bpp(connector, pipe_config); |
9715 | connected_sink_compute_bpp(connector, pipe_config); |
8857 | } |
9716 | } |
8858 | 9717 | ||
8859 | return bpp; |
9718 | return bpp; |
8860 | } |
9719 | } |
8861 | 9720 | ||
8862 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9721 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8863 | { |
9722 | { |
8864 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
9723 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
8865 | "type: 0x%x flags: 0x%x\n", |
9724 | "type: 0x%x flags: 0x%x\n", |
8866 | mode->crtc_clock, |
9725 | mode->crtc_clock, |
8867 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9726 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8868 | mode->crtc_hsync_end, mode->crtc_htotal, |
9727 | mode->crtc_hsync_end, mode->crtc_htotal, |
8869 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
9728 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
8870 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
9729 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
8871 | } |
9730 | } |
8872 | 9731 | ||
8873 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9732 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8874 | struct intel_crtc_config *pipe_config, |
9733 | struct intel_crtc_config *pipe_config, |
8875 | const char *context) |
9734 | const char *context) |
8876 | { |
9735 | { |
8877 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
9736 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
8878 | context, pipe_name(crtc->pipe)); |
9737 | context, pipe_name(crtc->pipe)); |
8879 | 9738 | ||
8880 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
9739 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
8881 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
9740 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
8882 | pipe_config->pipe_bpp, pipe_config->dither); |
9741 | pipe_config->pipe_bpp, pipe_config->dither); |
8883 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9742 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8884 | pipe_config->has_pch_encoder, |
9743 | pipe_config->has_pch_encoder, |
8885 | pipe_config->fdi_lanes, |
9744 | pipe_config->fdi_lanes, |
8886 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
9745 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8887 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
9746 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8888 | pipe_config->fdi_m_n.tu); |
9747 | pipe_config->fdi_m_n.tu); |
8889 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9748 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8890 | pipe_config->has_dp_encoder, |
9749 | pipe_config->has_dp_encoder, |
8891 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
9750 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
8892 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
9751 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
8893 | pipe_config->dp_m_n.tu); |
9752 | pipe_config->dp_m_n.tu); |
8894 | DRM_DEBUG_KMS("requested mode:\n"); |
9753 | DRM_DEBUG_KMS("requested mode:\n"); |
8895 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
9754 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8896 | DRM_DEBUG_KMS("adjusted mode:\n"); |
9755 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8897 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
9756 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8898 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
9757 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
8899 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
9758 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
8900 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9759 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8901 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
9760 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
8902 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9761 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8903 | pipe_config->gmch_pfit.control, |
9762 | pipe_config->gmch_pfit.control, |
8904 | pipe_config->gmch_pfit.pgm_ratios, |
9763 | pipe_config->gmch_pfit.pgm_ratios, |
8905 | pipe_config->gmch_pfit.lvds_border_bits); |
9764 | pipe_config->gmch_pfit.lvds_border_bits); |
8906 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
9765 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8907 | pipe_config->pch_pfit.pos, |
9766 | pipe_config->pch_pfit.pos, |
8908 | pipe_config->pch_pfit.size, |
9767 | pipe_config->pch_pfit.size, |
8909 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
9768 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8910 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
9769 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8911 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
9770 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
8912 | } |
9771 | } |
8913 | 9772 | ||
- | 9773 | static bool encoders_cloneable(const struct intel_encoder *a, |
|
8914 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
9774 | const struct intel_encoder *b) |
- | 9775 | { |
|
- | 9776 | /* masks could be asymmetric, so check both ways */ |
|
- | 9777 | return a == b || (a->cloneable & (1 << b->type) && |
|
- | 9778 | b->cloneable & (1 << a->type)); |
|
- | 9779 | } |
|
- | 9780 | ||
- | 9781 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
|
- | 9782 | struct intel_encoder *encoder) |
|
- | 9783 | { |
|
8915 | { |
9784 | struct drm_device *dev = crtc->base.dev; |
- | 9785 | struct intel_encoder *source_encoder; |
|
- | 9786 | ||
- | 9787 | list_for_each_entry(source_encoder, |
|
- | 9788 | &dev->mode_config.encoder_list, base.head) { |
|
- | 9789 | if (source_encoder->new_crtc != crtc) |
|
- | 9790 | continue; |
|
8916 | int num_encoders = 0; |
9791 | |
- | 9792 | if (!encoders_cloneable(encoder, source_encoder)) |
|
- | 9793 | return false; |
|
- | 9794 | } |
|
- | 9795 | ||
- | 9796 | return true; |
|
- | 9797 | } |
|
- | 9798 | ||
- | 9799 | static bool check_encoder_cloning(struct intel_crtc *crtc) |
|
- | 9800 | { |
|
8917 | bool uncloneable_encoders = false; |
9801 | struct drm_device *dev = crtc->base.dev; |
8918 | struct intel_encoder *encoder; |
9802 | struct intel_encoder *encoder; |
8919 | 9803 | ||
8920 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
9804 | list_for_each_entry(encoder, |
8921 | base.head) { |
9805 | &dev->mode_config.encoder_list, base.head) { |
8922 | if (&encoder->new_crtc->base != crtc) |
- | |
8923 | continue; |
9806 | if (encoder->new_crtc != crtc) |
8924 | 9807 | continue; |
|
8925 | num_encoders++; |
9808 | |
8926 | if (!encoder->cloneable) |
9809 | if (!check_single_encoder_cloning(crtc, encoder)) |
8927 | uncloneable_encoders = true; |
9810 | return false; |
8928 | } |
9811 | } |
8929 | 9812 | ||
8930 | return !(num_encoders > 1 && uncloneable_encoders); |
9813 | return true; |
8931 | } |
9814 | } |
8932 | 9815 | ||
8933 | static struct intel_crtc_config * |
9816 | static struct intel_crtc_config * |
8934 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
9817 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
8935 | struct drm_framebuffer *fb, |
9818 | struct drm_framebuffer *fb, |
8936 | struct drm_display_mode *mode) |
9819 | struct drm_display_mode *mode) |
8937 | { |
9820 | { |
8938 | struct drm_device *dev = crtc->dev; |
9821 | struct drm_device *dev = crtc->dev; |
8939 | struct intel_encoder *encoder; |
9822 | struct intel_encoder *encoder; |
8940 | struct intel_crtc_config *pipe_config; |
9823 | struct intel_crtc_config *pipe_config; |
8941 | int plane_bpp, ret = -EINVAL; |
9824 | int plane_bpp, ret = -EINVAL; |
8942 | bool retry = true; |
9825 | bool retry = true; |
8943 | 9826 | ||
8944 | if (!check_encoder_cloning(crtc)) { |
9827 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
8945 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9828 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8946 | return ERR_PTR(-EINVAL); |
9829 | return ERR_PTR(-EINVAL); |
8947 | } |
9830 | } |
8948 | 9831 | ||
8949 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9832 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8950 | if (!pipe_config) |
9833 | if (!pipe_config) |
8951 | return ERR_PTR(-ENOMEM); |
9834 | return ERR_PTR(-ENOMEM); |
8952 | 9835 | ||
8953 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9836 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8954 | drm_mode_copy(&pipe_config->requested_mode, mode); |
9837 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8955 | 9838 | ||
8956 | pipe_config->cpu_transcoder = |
9839 | pipe_config->cpu_transcoder = |
8957 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
9840 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8958 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9841 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8959 | 9842 | ||
8960 | /* |
9843 | /* |
8961 | * Sanitize sync polarity flags based on requested ones. If neither |
9844 | * Sanitize sync polarity flags based on requested ones. If neither |
8962 | * positive or negative polarity is requested, treat this as meaning |
9845 | * positive or negative polarity is requested, treat this as meaning |
8963 | * negative polarity. |
9846 | * negative polarity. |
8964 | */ |
9847 | */ |
8965 | if (!(pipe_config->adjusted_mode.flags & |
9848 | if (!(pipe_config->adjusted_mode.flags & |
8966 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
9849 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
8967 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
9850 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
8968 | 9851 | ||
8969 | if (!(pipe_config->adjusted_mode.flags & |
9852 | if (!(pipe_config->adjusted_mode.flags & |
8970 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
9853 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
8971 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
9854 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
8972 | 9855 | ||
8973 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9856 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8974 | * plane pixel format and any sink constraints into account. Returns the |
9857 | * plane pixel format and any sink constraints into account. Returns the |
8975 | * source plane bpp so that dithering can be selected on mismatches |
9858 | * source plane bpp so that dithering can be selected on mismatches |
8976 | * after encoders and crtc also have had their say. */ |
9859 | * after encoders and crtc also have had their say. */ |
8977 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
9860 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8978 | fb, pipe_config); |
9861 | fb, pipe_config); |
8979 | if (plane_bpp < 0) |
9862 | if (plane_bpp < 0) |
8980 | goto fail; |
9863 | goto fail; |
8981 | 9864 | ||
8982 | /* |
9865 | /* |
8983 | * Determine the real pipe dimensions. Note that stereo modes can |
9866 | * Determine the real pipe dimensions. Note that stereo modes can |
8984 | * increase the actual pipe size due to the frame doubling and |
9867 | * increase the actual pipe size due to the frame doubling and |
8985 | * insertion of additional space for blanks between the frame. This |
9868 | * insertion of additional space for blanks between the frame. This |
8986 | * is stored in the crtc timings. We use the requested mode to do this |
9869 | * is stored in the crtc timings. We use the requested mode to do this |
8987 | * computation to clearly distinguish it from the adjusted mode, which |
9870 | * computation to clearly distinguish it from the adjusted mode, which |
8988 | * can be changed by the connectors in the below retry loop. |
9871 | * can be changed by the connectors in the below retry loop. |
8989 | */ |
9872 | */ |
8990 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
9873 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
8991 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
9874 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
8992 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
9875 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
8993 | 9876 | ||
8994 | encoder_retry: |
9877 | encoder_retry: |
8995 | /* Ensure the port clock defaults are reset when retrying. */ |
9878 | /* Ensure the port clock defaults are reset when retrying. */ |
8996 | pipe_config->port_clock = 0; |
9879 | pipe_config->port_clock = 0; |
8997 | pipe_config->pixel_multiplier = 1; |
9880 | pipe_config->pixel_multiplier = 1; |
8998 | 9881 | ||
8999 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
9882 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
9000 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
9883 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
9001 | 9884 | ||
9002 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9885 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9003 | * adjust it according to limitations or connector properties, and also |
9886 | * adjust it according to limitations or connector properties, and also |
9004 | * a chance to reject the mode entirely. |
9887 | * a chance to reject the mode entirely. |
9005 | */ |
9888 | */ |
9006 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9889 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9007 | base.head) { |
9890 | base.head) { |
9008 | 9891 | ||
9009 | if (&encoder->new_crtc->base != crtc) |
9892 | if (&encoder->new_crtc->base != crtc) |
9010 | continue; |
9893 | continue; |
9011 | 9894 | ||
9012 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9895 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9013 | DRM_DEBUG_KMS("Encoder config failure\n"); |
9896 | DRM_DEBUG_KMS("Encoder config failure\n"); |
9014 | goto fail; |
9897 | goto fail; |
9015 | } |
9898 | } |
9016 | } |
9899 | } |
9017 | 9900 | ||
9018 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9901 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9019 | * done afterwards in case the encoder adjusts the mode. */ |
9902 | * done afterwards in case the encoder adjusts the mode. */ |
9020 | if (!pipe_config->port_clock) |
9903 | if (!pipe_config->port_clock) |
9021 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9904 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9022 | * pipe_config->pixel_multiplier; |
9905 | * pipe_config->pixel_multiplier; |
9023 | 9906 | ||
9024 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
9907 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
9025 | if (ret < 0) { |
9908 | if (ret < 0) { |
9026 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9909 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9027 | goto fail; |
9910 | goto fail; |
9028 | } |
9911 | } |
9029 | 9912 | ||
9030 | if (ret == RETRY) { |
9913 | if (ret == RETRY) { |
9031 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
9914 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
9032 | ret = -EINVAL; |
9915 | ret = -EINVAL; |
9033 | goto fail; |
9916 | goto fail; |
9034 | } |
9917 | } |
9035 | 9918 | ||
9036 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
9919 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
9037 | retry = false; |
9920 | retry = false; |
9038 | goto encoder_retry; |
9921 | goto encoder_retry; |
9039 | } |
9922 | } |
9040 | 9923 | ||
9041 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9924 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9042 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
9925 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
9043 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
9926 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
9044 | 9927 | ||
9045 | return pipe_config; |
9928 | return pipe_config; |
9046 | fail: |
9929 | fail: |
9047 | kfree(pipe_config); |
9930 | kfree(pipe_config); |
9048 | return ERR_PTR(ret); |
9931 | return ERR_PTR(ret); |
9049 | } |
9932 | } |
9050 | 9933 | ||
9051 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9934 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9052 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
9935 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
9053 | static void |
9936 | static void |
9054 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
9937 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
9055 | unsigned *prepare_pipes, unsigned *disable_pipes) |
9938 | unsigned *prepare_pipes, unsigned *disable_pipes) |
9056 | { |
9939 | { |
9057 | struct intel_crtc *intel_crtc; |
9940 | struct intel_crtc *intel_crtc; |
9058 | struct drm_device *dev = crtc->dev; |
9941 | struct drm_device *dev = crtc->dev; |
9059 | struct intel_encoder *encoder; |
9942 | struct intel_encoder *encoder; |
9060 | struct intel_connector *connector; |
9943 | struct intel_connector *connector; |
9061 | struct drm_crtc *tmp_crtc; |
9944 | struct drm_crtc *tmp_crtc; |
9062 | 9945 | ||
9063 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
9946 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
9064 | 9947 | ||
9065 | /* Check which crtcs have changed outputs connected to them, these need |
9948 | /* Check which crtcs have changed outputs connected to them, these need |
9066 | * to be part of the prepare_pipes mask. We don't (yet) support global |
9949 | * to be part of the prepare_pipes mask. We don't (yet) support global |
9067 | * modeset across multiple crtcs, so modeset_pipes will only have one |
9950 | * modeset across multiple crtcs, so modeset_pipes will only have one |
9068 | * bit set at most. */ |
9951 | * bit set at most. */ |
9069 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9952 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9070 | base.head) { |
9953 | base.head) { |
9071 | if (connector->base.encoder == &connector->new_encoder->base) |
9954 | if (connector->base.encoder == &connector->new_encoder->base) |
9072 | continue; |
9955 | continue; |
9073 | 9956 | ||
9074 | if (connector->base.encoder) { |
9957 | if (connector->base.encoder) { |
9075 | tmp_crtc = connector->base.encoder->crtc; |
9958 | tmp_crtc = connector->base.encoder->crtc; |
9076 | 9959 | ||
9077 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9960 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9078 | } |
9961 | } |
9079 | 9962 | ||
9080 | if (connector->new_encoder) |
9963 | if (connector->new_encoder) |
9081 | *prepare_pipes |= |
9964 | *prepare_pipes |= |
9082 | 1 << connector->new_encoder->new_crtc->pipe; |
9965 | 1 << connector->new_encoder->new_crtc->pipe; |
9083 | } |
9966 | } |
9084 | 9967 | ||
9085 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9968 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9086 | base.head) { |
9969 | base.head) { |
9087 | if (encoder->base.crtc == &encoder->new_crtc->base) |
9970 | if (encoder->base.crtc == &encoder->new_crtc->base) |
9088 | continue; |
9971 | continue; |
9089 | 9972 | ||
9090 | if (encoder->base.crtc) { |
9973 | if (encoder->base.crtc) { |
9091 | tmp_crtc = encoder->base.crtc; |
9974 | tmp_crtc = encoder->base.crtc; |
9092 | 9975 | ||
9093 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9976 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9094 | } |
9977 | } |
9095 | 9978 | ||
9096 | if (encoder->new_crtc) |
9979 | if (encoder->new_crtc) |
9097 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
9980 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
9098 | } |
9981 | } |
9099 | 9982 | ||
9100 | /* Check for any pipes that will be fully disabled ... */ |
9983 | /* Check for pipes that will be enabled/disabled ... */ |
9101 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
- | |
9102 | base.head) { |
- | |
9103 | bool used = false; |
- | |
9104 | - | ||
9105 | /* Don't try to disable disabled crtcs. */ |
9984 | for_each_intel_crtc(dev, intel_crtc) { |
9106 | if (!intel_crtc->base.enabled) |
9985 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
9107 | continue; |
- | |
9108 | - | ||
9109 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9986 | continue; |
9110 | base.head) { |
- | |
9111 | if (encoder->new_crtc == intel_crtc) |
- | |
9112 | used = true; |
- | |
9113 | } |
- | |
9114 | 9987 | ||
- | 9988 | if (!intel_crtc->new_enabled) |
|
- | 9989 | *disable_pipes |= 1 << intel_crtc->pipe; |
|
9115 | if (!used) |
9990 | else |
9116 | *disable_pipes |= 1 << intel_crtc->pipe; |
9991 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9117 | } |
9992 | } |
9118 | 9993 | ||
9119 | 9994 | ||
9120 | /* set_mode is also used to update properties on life display pipes. */ |
9995 | /* set_mode is also used to update properties on life display pipes. */ |
9121 | intel_crtc = to_intel_crtc(crtc); |
9996 | intel_crtc = to_intel_crtc(crtc); |
9122 | if (crtc->enabled) |
9997 | if (intel_crtc->new_enabled) |
9123 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9998 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9124 | 9999 | ||
9125 | /* |
10000 | /* |
9126 | * For simplicity do a full modeset on any pipe where the output routing |
10001 | * For simplicity do a full modeset on any pipe where the output routing |
9127 | * changed. We could be more clever, but that would require us to be |
10002 | * changed. We could be more clever, but that would require us to be |
9128 | * more careful with calling the relevant encoder->mode_set functions. |
10003 | * more careful with calling the relevant encoder->mode_set functions. |
9129 | */ |
10004 | */ |
9130 | if (*prepare_pipes) |
10005 | if (*prepare_pipes) |
9131 | *modeset_pipes = *prepare_pipes; |
10006 | *modeset_pipes = *prepare_pipes; |
9132 | 10007 | ||
9133 | /* ... and mask these out. */ |
10008 | /* ... and mask these out. */ |
9134 | *modeset_pipes &= ~(*disable_pipes); |
10009 | *modeset_pipes &= ~(*disable_pipes); |
9135 | *prepare_pipes &= ~(*disable_pipes); |
10010 | *prepare_pipes &= ~(*disable_pipes); |
9136 | 10011 | ||
9137 | /* |
10012 | /* |
9138 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
10013 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
9139 | * obies this rule, but the modeset restore mode of |
10014 | * obies this rule, but the modeset restore mode of |
9140 | * intel_modeset_setup_hw_state does not. |
10015 | * intel_modeset_setup_hw_state does not. |
9141 | */ |
10016 | */ |
9142 | *modeset_pipes &= 1 << intel_crtc->pipe; |
10017 | *modeset_pipes &= 1 << intel_crtc->pipe; |
9143 | *prepare_pipes &= 1 << intel_crtc->pipe; |
10018 | *prepare_pipes &= 1 << intel_crtc->pipe; |
9144 | 10019 | ||
9145 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
10020 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
9146 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
10021 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
9147 | } |
10022 | } |
9148 | 10023 | ||
9149 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
10024 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
9150 | { |
10025 | { |
9151 | struct drm_encoder *encoder; |
10026 | struct drm_encoder *encoder; |
9152 | struct drm_device *dev = crtc->dev; |
10027 | struct drm_device *dev = crtc->dev; |
9153 | 10028 | ||
9154 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10029 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9155 | if (encoder->crtc == crtc) |
10030 | if (encoder->crtc == crtc) |
9156 | return true; |
10031 | return true; |
9157 | 10032 | ||
9158 | return false; |
10033 | return false; |
9159 | } |
10034 | } |
9160 | 10035 | ||
9161 | static void |
10036 | static void |
9162 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
10037 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
9163 | { |
10038 | { |
9164 | struct intel_encoder *intel_encoder; |
10039 | struct intel_encoder *intel_encoder; |
9165 | struct intel_crtc *intel_crtc; |
10040 | struct intel_crtc *intel_crtc; |
9166 | struct drm_connector *connector; |
10041 | struct drm_connector *connector; |
9167 | 10042 | ||
9168 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
10043 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
9169 | base.head) { |
10044 | base.head) { |
9170 | if (!intel_encoder->base.crtc) |
10045 | if (!intel_encoder->base.crtc) |
9171 | continue; |
10046 | continue; |
9172 | 10047 | ||
9173 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
10048 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
9174 | 10049 | ||
9175 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
10050 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
9176 | intel_encoder->connectors_active = false; |
10051 | intel_encoder->connectors_active = false; |
9177 | } |
10052 | } |
9178 | 10053 | ||
9179 | intel_modeset_commit_output_state(dev); |
10054 | intel_modeset_commit_output_state(dev); |
9180 | 10055 | ||
9181 | /* Update computed state. */ |
10056 | /* Double check state. */ |
- | 10057 | for_each_intel_crtc(dev, intel_crtc) { |
|
9182 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
10058 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
- | 10059 | WARN_ON(intel_crtc->new_config && |
|
9183 | base.head) { |
10060 | intel_crtc->new_config != &intel_crtc->config); |
9184 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
10061 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
9185 | } |
10062 | } |
9186 | 10063 | ||
9187 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
10064 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9188 | if (!connector->encoder || !connector->encoder->crtc) |
10065 | if (!connector->encoder || !connector->encoder->crtc) |
9189 | continue; |
10066 | continue; |
9190 | 10067 | ||
9191 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
10068 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
9192 | 10069 | ||
9193 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
10070 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
9194 | struct drm_property *dpms_property = |
10071 | struct drm_property *dpms_property = |
9195 | dev->mode_config.dpms_property; |
10072 | dev->mode_config.dpms_property; |
9196 | 10073 | ||
9197 | connector->dpms = DRM_MODE_DPMS_ON; |
10074 | connector->dpms = DRM_MODE_DPMS_ON; |
9198 | drm_object_property_set_value(&connector->base, |
10075 | drm_object_property_set_value(&connector->base, |
9199 | dpms_property, |
10076 | dpms_property, |
9200 | DRM_MODE_DPMS_ON); |
10077 | DRM_MODE_DPMS_ON); |
9201 | 10078 | ||
9202 | intel_encoder = to_intel_encoder(connector->encoder); |
10079 | intel_encoder = to_intel_encoder(connector->encoder); |
9203 | intel_encoder->connectors_active = true; |
10080 | intel_encoder->connectors_active = true; |
9204 | } |
10081 | } |
9205 | } |
10082 | } |
9206 | 10083 | ||
9207 | } |
10084 | } |
9208 | 10085 | ||
9209 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
10086 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
9210 | { |
10087 | { |
9211 | int diff; |
10088 | int diff; |
9212 | 10089 | ||
9213 | if (clock1 == clock2) |
10090 | if (clock1 == clock2) |
9214 | return true; |
10091 | return true; |
9215 | 10092 | ||
9216 | if (!clock1 || !clock2) |
10093 | if (!clock1 || !clock2) |
9217 | return false; |
10094 | return false; |
9218 | 10095 | ||
9219 | diff = abs(clock1 - clock2); |
10096 | diff = abs(clock1 - clock2); |
9220 | 10097 | ||
9221 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
10098 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
9222 | return true; |
10099 | return true; |
9223 | 10100 | ||
9224 | return false; |
10101 | return false; |
9225 | } |
10102 | } |
9226 | 10103 | ||
9227 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10104 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9228 | list_for_each_entry((intel_crtc), \ |
10105 | list_for_each_entry((intel_crtc), \ |
9229 | &(dev)->mode_config.crtc_list, \ |
10106 | &(dev)->mode_config.crtc_list, \ |
9230 | base.head) \ |
10107 | base.head) \ |
9231 | if (mask & (1 <<(intel_crtc)->pipe)) |
10108 | if (mask & (1 <<(intel_crtc)->pipe)) |
9232 | 10109 | ||
9233 | static bool |
10110 | static bool |
9234 | intel_pipe_config_compare(struct drm_device *dev, |
10111 | intel_pipe_config_compare(struct drm_device *dev, |
9235 | struct intel_crtc_config *current_config, |
10112 | struct intel_crtc_config *current_config, |
9236 | struct intel_crtc_config *pipe_config) |
10113 | struct intel_crtc_config *pipe_config) |
9237 | { |
10114 | { |
9238 | #define PIPE_CONF_CHECK_X(name) \ |
10115 | #define PIPE_CONF_CHECK_X(name) \ |
9239 | if (current_config->name != pipe_config->name) { \ |
10116 | if (current_config->name != pipe_config->name) { \ |
9240 | DRM_ERROR("mismatch in " #name " " \ |
10117 | DRM_ERROR("mismatch in " #name " " \ |
9241 | "(expected 0x%08x, found 0x%08x)\n", \ |
10118 | "(expected 0x%08x, found 0x%08x)\n", \ |
9242 | current_config->name, \ |
10119 | current_config->name, \ |
9243 | pipe_config->name); \ |
10120 | pipe_config->name); \ |
9244 | return false; \ |
10121 | return false; \ |
9245 | } |
10122 | } |
9246 | 10123 | ||
9247 | #define PIPE_CONF_CHECK_I(name) \ |
10124 | #define PIPE_CONF_CHECK_I(name) \ |
9248 | if (current_config->name != pipe_config->name) { \ |
10125 | if (current_config->name != pipe_config->name) { \ |
9249 | DRM_ERROR("mismatch in " #name " " \ |
10126 | DRM_ERROR("mismatch in " #name " " \ |
9250 | "(expected %i, found %i)\n", \ |
10127 | "(expected %i, found %i)\n", \ |
9251 | current_config->name, \ |
10128 | current_config->name, \ |
9252 | pipe_config->name); \ |
10129 | pipe_config->name); \ |
9253 | return false; \ |
10130 | return false; \ |
9254 | } |
10131 | } |
9255 | 10132 | ||
9256 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10133 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9257 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
10134 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
9258 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
10135 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
9259 | "(expected %i, found %i)\n", \ |
10136 | "(expected %i, found %i)\n", \ |
9260 | current_config->name & (mask), \ |
10137 | current_config->name & (mask), \ |
9261 | pipe_config->name & (mask)); \ |
10138 | pipe_config->name & (mask)); \ |
9262 | return false; \ |
10139 | return false; \ |
9263 | } |
10140 | } |
9264 | 10141 | ||
9265 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10142 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9266 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
10143 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
9267 | DRM_ERROR("mismatch in " #name " " \ |
10144 | DRM_ERROR("mismatch in " #name " " \ |
9268 | "(expected %i, found %i)\n", \ |
10145 | "(expected %i, found %i)\n", \ |
9269 | current_config->name, \ |
10146 | current_config->name, \ |
9270 | pipe_config->name); \ |
10147 | pipe_config->name); \ |
9271 | return false; \ |
10148 | return false; \ |
9272 | } |
10149 | } |
9273 | 10150 | ||
9274 | #define PIPE_CONF_QUIRK(quirk) \ |
10151 | #define PIPE_CONF_QUIRK(quirk) \ |
9275 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
10152 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
9276 | 10153 | ||
9277 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10154 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9278 | 10155 | ||
9279 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10156 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9280 | PIPE_CONF_CHECK_I(fdi_lanes); |
10157 | PIPE_CONF_CHECK_I(fdi_lanes); |
9281 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10158 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9282 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
10159 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
9283 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
10160 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
9284 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
10161 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
9285 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
10162 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
9286 | 10163 | ||
9287 | PIPE_CONF_CHECK_I(has_dp_encoder); |
10164 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9288 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
10165 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
9289 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
10166 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
9290 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
10167 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
9291 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
10168 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
9292 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
10169 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
9293 | 10170 | ||
9294 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10171 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9295 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
10172 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
9296 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
10173 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
9297 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
10174 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
9298 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
10175 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
9299 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
10176 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
9300 | 10177 | ||
9301 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
10178 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
9302 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
10179 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
9303 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
10180 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
9304 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
10181 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
9305 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
10182 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
9306 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
10183 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
9307 | 10184 | ||
9308 | PIPE_CONF_CHECK_I(pixel_multiplier); |
10185 | PIPE_CONF_CHECK_I(pixel_multiplier); |
- | 10186 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
|
- | 10187 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
|
- | 10188 | IS_VALLEYVIEW(dev)) |
|
- | 10189 | PIPE_CONF_CHECK_I(limited_color_range); |
|
- | 10190 | ||
- | 10191 | PIPE_CONF_CHECK_I(has_audio); |
|
9309 | 10192 | ||
9310 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10193 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9311 | DRM_MODE_FLAG_INTERLACE); |
10194 | DRM_MODE_FLAG_INTERLACE); |
9312 | 10195 | ||
9313 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10196 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9314 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10197 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9315 | DRM_MODE_FLAG_PHSYNC); |
10198 | DRM_MODE_FLAG_PHSYNC); |
9316 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10199 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9317 | DRM_MODE_FLAG_NHSYNC); |
10200 | DRM_MODE_FLAG_NHSYNC); |
9318 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10201 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9319 | DRM_MODE_FLAG_PVSYNC); |
10202 | DRM_MODE_FLAG_PVSYNC); |
9320 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10203 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9321 | DRM_MODE_FLAG_NVSYNC); |
10204 | DRM_MODE_FLAG_NVSYNC); |
9322 | } |
10205 | } |
9323 | 10206 | ||
9324 | PIPE_CONF_CHECK_I(pipe_src_w); |
10207 | PIPE_CONF_CHECK_I(pipe_src_w); |
9325 | PIPE_CONF_CHECK_I(pipe_src_h); |
10208 | PIPE_CONF_CHECK_I(pipe_src_h); |
- | 10209 | ||
- | 10210 | /* |
|
- | 10211 | * FIXME: BIOS likes to set up a cloned config with lvds+external |
|
- | 10212 | * screen. Since we don't yet re-compute the pipe config when moving |
|
- | 10213 | * just the lvds port away to another pipe the sw tracking won't match. |
|
- | 10214 | * |
|
- | 10215 | * Proper atomic modesets with recomputed global state will fix this. |
|
- | 10216 | * Until then just don't check gmch state for inherited modes. |
|
- | 10217 | */ |
|
9326 | 10218 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { |
|
9327 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
10219 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9328 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
10220 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
9329 | if (INTEL_INFO(dev)->gen < 4) |
10221 | if (INTEL_INFO(dev)->gen < 4) |
9330 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
10222 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
9331 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
10223 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
- | 10224 | } |
|
- | 10225 | ||
9332 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10226 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9333 | if (current_config->pch_pfit.enabled) { |
10227 | if (current_config->pch_pfit.enabled) { |
9334 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
10228 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
9335 | PIPE_CONF_CHECK_I(pch_pfit.size); |
10229 | PIPE_CONF_CHECK_I(pch_pfit.size); |
9336 | } |
10230 | } |
9337 | 10231 | ||
9338 | /* BDW+ don't expose a synchronous way to read the state */ |
10232 | /* BDW+ don't expose a synchronous way to read the state */ |
9339 | if (IS_HASWELL(dev)) |
10233 | if (IS_HASWELL(dev)) |
9340 | PIPE_CONF_CHECK_I(ips_enabled); |
10234 | PIPE_CONF_CHECK_I(ips_enabled); |
9341 | 10235 | ||
9342 | PIPE_CONF_CHECK_I(double_wide); |
10236 | PIPE_CONF_CHECK_I(double_wide); |
- | 10237 | ||
- | 10238 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
|
9343 | 10239 | ||
9344 | PIPE_CONF_CHECK_I(shared_dpll); |
10240 | PIPE_CONF_CHECK_I(shared_dpll); |
9345 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
10241 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
9346 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
10242 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
9347 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10243 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9348 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
10244 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
- | 10245 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
|
9349 | 10246 | ||
9350 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10247 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9351 | PIPE_CONF_CHECK_I(pipe_bpp); |
10248 | PIPE_CONF_CHECK_I(pipe_bpp); |
9352 | - | ||
9353 | if (!HAS_DDI(dev)) { |
10249 | |
9354 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10250 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9355 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
- | |
9356 | } |
10251 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9357 | 10252 | ||
9358 | #undef PIPE_CONF_CHECK_X |
10253 | #undef PIPE_CONF_CHECK_X |
9359 | #undef PIPE_CONF_CHECK_I |
10254 | #undef PIPE_CONF_CHECK_I |
9360 | #undef PIPE_CONF_CHECK_FLAGS |
10255 | #undef PIPE_CONF_CHECK_FLAGS |
9361 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
10256 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
9362 | #undef PIPE_CONF_QUIRK |
10257 | #undef PIPE_CONF_QUIRK |
9363 | 10258 | ||
9364 | return true; |
10259 | return true; |
9365 | } |
10260 | } |
9366 | 10261 | ||
9367 | static void |
10262 | static void |
9368 | check_connector_state(struct drm_device *dev) |
10263 | check_connector_state(struct drm_device *dev) |
9369 | { |
10264 | { |
9370 | struct intel_connector *connector; |
10265 | struct intel_connector *connector; |
9371 | 10266 | ||
9372 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10267 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9373 | base.head) { |
10268 | base.head) { |
9374 | /* This also checks the encoder/connector hw state with the |
10269 | /* This also checks the encoder/connector hw state with the |
9375 | * ->get_hw_state callbacks. */ |
10270 | * ->get_hw_state callbacks. */ |
9376 | intel_connector_check_state(connector); |
10271 | intel_connector_check_state(connector); |
9377 | 10272 | ||
9378 | WARN(&connector->new_encoder->base != connector->base.encoder, |
10273 | WARN(&connector->new_encoder->base != connector->base.encoder, |
9379 | "connector's staged encoder doesn't match current encoder\n"); |
10274 | "connector's staged encoder doesn't match current encoder\n"); |
9380 | } |
10275 | } |
9381 | } |
10276 | } |
9382 | 10277 | ||
9383 | static void |
10278 | static void |
9384 | check_encoder_state(struct drm_device *dev) |
10279 | check_encoder_state(struct drm_device *dev) |
9385 | { |
10280 | { |
9386 | struct intel_encoder *encoder; |
10281 | struct intel_encoder *encoder; |
9387 | struct intel_connector *connector; |
10282 | struct intel_connector *connector; |
9388 | 10283 | ||
9389 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10284 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9390 | base.head) { |
10285 | base.head) { |
9391 | bool enabled = false; |
10286 | bool enabled = false; |
9392 | bool active = false; |
10287 | bool active = false; |
9393 | enum pipe pipe, tracked_pipe; |
10288 | enum pipe pipe, tracked_pipe; |
9394 | 10289 | ||
9395 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
10290 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
9396 | encoder->base.base.id, |
10291 | encoder->base.base.id, |
9397 | drm_get_encoder_name(&encoder->base)); |
10292 | encoder->base.name); |
9398 | 10293 | ||
9399 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
10294 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
9400 | "encoder's stage crtc doesn't match current crtc\n"); |
10295 | "encoder's stage crtc doesn't match current crtc\n"); |
9401 | WARN(encoder->connectors_active && !encoder->base.crtc, |
10296 | WARN(encoder->connectors_active && !encoder->base.crtc, |
9402 | "encoder's active_connectors set, but no crtc\n"); |
10297 | "encoder's active_connectors set, but no crtc\n"); |
9403 | 10298 | ||
9404 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10299 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9405 | base.head) { |
10300 | base.head) { |
9406 | if (connector->base.encoder != &encoder->base) |
10301 | if (connector->base.encoder != &encoder->base) |
9407 | continue; |
10302 | continue; |
9408 | enabled = true; |
10303 | enabled = true; |
9409 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
10304 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
9410 | active = true; |
10305 | active = true; |
9411 | } |
10306 | } |
- | 10307 | /* |
|
- | 10308 | * for MST connectors if we unplug the connector is gone |
|
- | 10309 | * away but the encoder is still connected to a crtc |
|
- | 10310 | * until a modeset happens in response to the hotplug. |
|
- | 10311 | */ |
|
- | 10312 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) |
|
- | 10313 | continue; |
|
- | 10314 | ||
9412 | WARN(!!encoder->base.crtc != enabled, |
10315 | WARN(!!encoder->base.crtc != enabled, |
9413 | "encoder's enabled state mismatch " |
10316 | "encoder's enabled state mismatch " |
9414 | "(expected %i, found %i)\n", |
10317 | "(expected %i, found %i)\n", |
9415 | !!encoder->base.crtc, enabled); |
10318 | !!encoder->base.crtc, enabled); |
9416 | WARN(active && !encoder->base.crtc, |
10319 | WARN(active && !encoder->base.crtc, |
9417 | "active encoder with no crtc\n"); |
10320 | "active encoder with no crtc\n"); |
9418 | 10321 | ||
9419 | WARN(encoder->connectors_active != active, |
10322 | WARN(encoder->connectors_active != active, |
9420 | "encoder's computed active state doesn't match tracked active state " |
10323 | "encoder's computed active state doesn't match tracked active state " |
9421 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
10324 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
9422 | 10325 | ||
9423 | active = encoder->get_hw_state(encoder, &pipe); |
10326 | active = encoder->get_hw_state(encoder, &pipe); |
9424 | WARN(active != encoder->connectors_active, |
10327 | WARN(active != encoder->connectors_active, |
9425 | "encoder's hw state doesn't match sw tracking " |
10328 | "encoder's hw state doesn't match sw tracking " |
9426 | "(expected %i, found %i)\n", |
10329 | "(expected %i, found %i)\n", |
9427 | encoder->connectors_active, active); |
10330 | encoder->connectors_active, active); |
9428 | 10331 | ||
9429 | if (!encoder->base.crtc) |
10332 | if (!encoder->base.crtc) |
9430 | continue; |
10333 | continue; |
9431 | 10334 | ||
9432 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
10335 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
9433 | WARN(active && pipe != tracked_pipe, |
10336 | WARN(active && pipe != tracked_pipe, |
9434 | "active encoder's pipe doesn't match" |
10337 | "active encoder's pipe doesn't match" |
9435 | "(expected %i, found %i)\n", |
10338 | "(expected %i, found %i)\n", |
9436 | tracked_pipe, pipe); |
10339 | tracked_pipe, pipe); |
9437 | 10340 | ||
9438 | } |
10341 | } |
9439 | } |
10342 | } |
9440 | 10343 | ||
9441 | static void |
10344 | static void |
9442 | check_crtc_state(struct drm_device *dev) |
10345 | check_crtc_state(struct drm_device *dev) |
9443 | { |
10346 | { |
9444 | drm_i915_private_t *dev_priv = dev->dev_private; |
10347 | struct drm_i915_private *dev_priv = dev->dev_private; |
9445 | struct intel_crtc *crtc; |
10348 | struct intel_crtc *crtc; |
9446 | struct intel_encoder *encoder; |
10349 | struct intel_encoder *encoder; |
9447 | struct intel_crtc_config pipe_config; |
10350 | struct intel_crtc_config pipe_config; |
9448 | 10351 | ||
9449 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
9450 | base.head) { |
10352 | for_each_intel_crtc(dev, crtc) { |
9451 | bool enabled = false; |
10353 | bool enabled = false; |
9452 | bool active = false; |
10354 | bool active = false; |
9453 | 10355 | ||
9454 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10356 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9455 | 10357 | ||
9456 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10358 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9457 | crtc->base.base.id); |
10359 | crtc->base.base.id); |
9458 | 10360 | ||
9459 | WARN(crtc->active && !crtc->base.enabled, |
10361 | WARN(crtc->active && !crtc->base.enabled, |
9460 | "active crtc, but not enabled in sw tracking\n"); |
10362 | "active crtc, but not enabled in sw tracking\n"); |
9461 | 10363 | ||
9462 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10364 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9463 | base.head) { |
10365 | base.head) { |
9464 | if (encoder->base.crtc != &crtc->base) |
10366 | if (encoder->base.crtc != &crtc->base) |
9465 | continue; |
10367 | continue; |
9466 | enabled = true; |
10368 | enabled = true; |
9467 | if (encoder->connectors_active) |
10369 | if (encoder->connectors_active) |
9468 | active = true; |
10370 | active = true; |
9469 | } |
10371 | } |
9470 | 10372 | ||
9471 | WARN(active != crtc->active, |
10373 | WARN(active != crtc->active, |
9472 | "crtc's computed active state doesn't match tracked active state " |
10374 | "crtc's computed active state doesn't match tracked active state " |
9473 | "(expected %i, found %i)\n", active, crtc->active); |
10375 | "(expected %i, found %i)\n", active, crtc->active); |
9474 | WARN(enabled != crtc->base.enabled, |
10376 | WARN(enabled != crtc->base.enabled, |
9475 | "crtc's computed enabled state doesn't match tracked enabled state " |
10377 | "crtc's computed enabled state doesn't match tracked enabled state " |
9476 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
10378 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
9477 | 10379 | ||
9478 | active = dev_priv->display.get_pipe_config(crtc, |
10380 | active = dev_priv->display.get_pipe_config(crtc, |
9479 | &pipe_config); |
10381 | &pipe_config); |
9480 | 10382 | ||
9481 | /* hw state is inconsistent with the pipe A quirk */ |
10383 | /* hw state is inconsistent with the pipe A quirk */ |
9482 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
10384 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
9483 | active = crtc->active; |
10385 | active = crtc->active; |
9484 | 10386 | ||
9485 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10387 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9486 | base.head) { |
10388 | base.head) { |
9487 | enum pipe pipe; |
10389 | enum pipe pipe; |
9488 | if (encoder->base.crtc != &crtc->base) |
10390 | if (encoder->base.crtc != &crtc->base) |
9489 | continue; |
10391 | continue; |
9490 | if (encoder->get_hw_state(encoder, &pipe)) |
10392 | if (encoder->get_hw_state(encoder, &pipe)) |
9491 | encoder->get_config(encoder, &pipe_config); |
10393 | encoder->get_config(encoder, &pipe_config); |
9492 | } |
10394 | } |
9493 | 10395 | ||
9494 | WARN(crtc->active != active, |
10396 | WARN(crtc->active != active, |
9495 | "crtc active state doesn't match with hw state " |
10397 | "crtc active state doesn't match with hw state " |
9496 | "(expected %i, found %i)\n", crtc->active, active); |
10398 | "(expected %i, found %i)\n", crtc->active, active); |
9497 | 10399 | ||
9498 | if (active && |
10400 | if (active && |
9499 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
10401 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
9500 | WARN(1, "pipe state doesn't match!\n"); |
10402 | WARN(1, "pipe state doesn't match!\n"); |
9501 | intel_dump_pipe_config(crtc, &pipe_config, |
10403 | intel_dump_pipe_config(crtc, &pipe_config, |
9502 | "[hw state]"); |
10404 | "[hw state]"); |
9503 | intel_dump_pipe_config(crtc, &crtc->config, |
10405 | intel_dump_pipe_config(crtc, &crtc->config, |
9504 | "[sw state]"); |
10406 | "[sw state]"); |
9505 | } |
10407 | } |
9506 | } |
10408 | } |
9507 | } |
10409 | } |
9508 | 10410 | ||
9509 | static void |
10411 | static void |
9510 | check_shared_dpll_state(struct drm_device *dev) |
10412 | check_shared_dpll_state(struct drm_device *dev) |
9511 | { |
10413 | { |
9512 | drm_i915_private_t *dev_priv = dev->dev_private; |
10414 | struct drm_i915_private *dev_priv = dev->dev_private; |
9513 | struct intel_crtc *crtc; |
10415 | struct intel_crtc *crtc; |
9514 | struct intel_dpll_hw_state dpll_hw_state; |
10416 | struct intel_dpll_hw_state dpll_hw_state; |
9515 | int i; |
10417 | int i; |
9516 | 10418 | ||
9517 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10419 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9518 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10420 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
9519 | int enabled_crtcs = 0, active_crtcs = 0; |
10421 | int enabled_crtcs = 0, active_crtcs = 0; |
9520 | bool active; |
10422 | bool active; |
9521 | 10423 | ||
9522 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
10424 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
9523 | 10425 | ||
9524 | DRM_DEBUG_KMS("%s\n", pll->name); |
10426 | DRM_DEBUG_KMS("%s\n", pll->name); |
9525 | 10427 | ||
9526 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
10428 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
9527 | 10429 | ||
9528 | WARN(pll->active > pll->refcount, |
10430 | WARN(pll->active > pll->refcount, |
9529 | "more active pll users than references: %i vs %i\n", |
10431 | "more active pll users than references: %i vs %i\n", |
9530 | pll->active, pll->refcount); |
10432 | pll->active, pll->refcount); |
9531 | WARN(pll->active && !pll->on, |
10433 | WARN(pll->active && !pll->on, |
9532 | "pll in active use but not on in sw tracking\n"); |
10434 | "pll in active use but not on in sw tracking\n"); |
9533 | WARN(pll->on && !pll->active, |
10435 | WARN(pll->on && !pll->active, |
9534 | "pll in on but not on in use in sw tracking\n"); |
10436 | "pll in on but not on in use in sw tracking\n"); |
9535 | WARN(pll->on != active, |
10437 | WARN(pll->on != active, |
9536 | "pll on state mismatch (expected %i, found %i)\n", |
10438 | "pll on state mismatch (expected %i, found %i)\n", |
9537 | pll->on, active); |
10439 | pll->on, active); |
9538 | 10440 | ||
9539 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
9540 | base.head) { |
10441 | for_each_intel_crtc(dev, crtc) { |
9541 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10442 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
9542 | enabled_crtcs++; |
10443 | enabled_crtcs++; |
9543 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10444 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
9544 | active_crtcs++; |
10445 | active_crtcs++; |
9545 | } |
10446 | } |
9546 | WARN(pll->active != active_crtcs, |
10447 | WARN(pll->active != active_crtcs, |
9547 | "pll active crtcs mismatch (expected %i, found %i)\n", |
10448 | "pll active crtcs mismatch (expected %i, found %i)\n", |
9548 | pll->active, active_crtcs); |
10449 | pll->active, active_crtcs); |
9549 | WARN(pll->refcount != enabled_crtcs, |
10450 | WARN(pll->refcount != enabled_crtcs, |
9550 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
10451 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
9551 | pll->refcount, enabled_crtcs); |
10452 | pll->refcount, enabled_crtcs); |
9552 | 10453 | ||
9553 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
10454 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
9554 | sizeof(dpll_hw_state)), |
10455 | sizeof(dpll_hw_state)), |
9555 | "pll hw state mismatch\n"); |
10456 | "pll hw state mismatch\n"); |
9556 | } |
10457 | } |
9557 | } |
10458 | } |
9558 | 10459 | ||
9559 | void |
10460 | void |
9560 | intel_modeset_check_state(struct drm_device *dev) |
10461 | intel_modeset_check_state(struct drm_device *dev) |
9561 | { |
10462 | { |
9562 | check_connector_state(dev); |
10463 | check_connector_state(dev); |
9563 | check_encoder_state(dev); |
10464 | check_encoder_state(dev); |
9564 | check_crtc_state(dev); |
10465 | check_crtc_state(dev); |
9565 | check_shared_dpll_state(dev); |
10466 | check_shared_dpll_state(dev); |
9566 | } |
10467 | } |
9567 | 10468 | ||
9568 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10469 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9569 | int dotclock) |
10470 | int dotclock) |
9570 | { |
10471 | { |
9571 | /* |
10472 | /* |
9572 | * FDI already provided one idea for the dotclock. |
10473 | * FDI already provided one idea for the dotclock. |
9573 | * Yell if the encoder disagrees. |
10474 | * Yell if the encoder disagrees. |
9574 | */ |
10475 | */ |
9575 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
10476 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
9576 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
10477 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
9577 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
10478 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
9578 | } |
10479 | } |
- | 10480 | ||
- | 10481 | static void update_scanline_offset(struct intel_crtc *crtc) |
|
- | 10482 | { |
|
- | 10483 | struct drm_device *dev = crtc->base.dev; |
|
- | 10484 | ||
- | 10485 | /* |
|
- | 10486 | * The scanline counter increments at the leading edge of hsync. |
|
- | 10487 | * |
|
- | 10488 | * On most platforms it starts counting from vtotal-1 on the |
|
- | 10489 | * first active line. That means the scanline counter value is |
|
- | 10490 | * always one less than what we would expect. Ie. just after |
|
- | 10491 | * start of vblank, which also occurs at start of hsync (on the |
|
- | 10492 | * last active line), the scanline counter will read vblank_start-1. |
|
- | 10493 | * |
|
- | 10494 | * On gen2 the scanline counter starts counting from 1 instead |
|
- | 10495 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
|
- | 10496 | * to keep the value positive), instead of adding one. |
|
- | 10497 | * |
|
- | 10498 | * On HSW+ the behaviour of the scanline counter depends on the output |
|
- | 10499 | * type. For DP ports it behaves like most other platforms, but on HDMI |
|
- | 10500 | * there's an extra 1 line difference. So we need to add two instead of |
|
- | 10501 | * one to the value. |
|
- | 10502 | */ |
|
- | 10503 | if (IS_GEN2(dev)) { |
|
- | 10504 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
|
- | 10505 | int vtotal; |
|
- | 10506 | ||
- | 10507 | vtotal = mode->crtc_vtotal; |
|
- | 10508 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 10509 | vtotal /= 2; |
|
- | 10510 | ||
- | 10511 | crtc->scanline_offset = vtotal - 1; |
|
- | 10512 | } else if (HAS_DDI(dev) && |
|
- | 10513 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { |
|
- | 10514 | crtc->scanline_offset = 2; |
|
- | 10515 | } else |
|
- | 10516 | crtc->scanline_offset = 1; |
|
- | 10517 | } |
|
9579 | 10518 | ||
9580 | static int __intel_set_mode(struct drm_crtc *crtc, |
10519 | static int __intel_set_mode(struct drm_crtc *crtc, |
9581 | struct drm_display_mode *mode, |
10520 | struct drm_display_mode *mode, |
9582 | int x, int y, struct drm_framebuffer *fb) |
10521 | int x, int y, struct drm_framebuffer *fb) |
9583 | { |
10522 | { |
9584 | struct drm_device *dev = crtc->dev; |
10523 | struct drm_device *dev = crtc->dev; |
9585 | drm_i915_private_t *dev_priv = dev->dev_private; |
10524 | struct drm_i915_private *dev_priv = dev->dev_private; |
9586 | struct drm_display_mode *saved_mode; |
10525 | struct drm_display_mode *saved_mode; |
9587 | struct intel_crtc_config *pipe_config = NULL; |
10526 | struct intel_crtc_config *pipe_config = NULL; |
9588 | struct intel_crtc *intel_crtc; |
10527 | struct intel_crtc *intel_crtc; |
9589 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
10528 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
9590 | int ret = 0; |
10529 | int ret = 0; |
9591 | 10530 | ||
9592 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
10531 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
9593 | if (!saved_mode) |
10532 | if (!saved_mode) |
9594 | return -ENOMEM; |
10533 | return -ENOMEM; |
9595 | 10534 | ||
9596 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
10535 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
9597 | &prepare_pipes, &disable_pipes); |
10536 | &prepare_pipes, &disable_pipes); |
9598 | 10537 | ||
9599 | *saved_mode = crtc->mode; |
10538 | *saved_mode = crtc->mode; |
9600 | 10539 | ||
9601 | /* Hack: Because we don't (yet) support global modeset on multiple |
10540 | /* Hack: Because we don't (yet) support global modeset on multiple |
9602 | * crtcs, we don't keep track of the new mode for more than one crtc. |
10541 | * crtcs, we don't keep track of the new mode for more than one crtc. |
9603 | * Hence simply check whether any bit is set in modeset_pipes in all the |
10542 | * Hence simply check whether any bit is set in modeset_pipes in all the |
9604 | * pieces of code that are not yet converted to deal with mutliple crtcs |
10543 | * pieces of code that are not yet converted to deal with mutliple crtcs |
9605 | * changing their mode at the same time. */ |
10544 | * changing their mode at the same time. */ |
9606 | if (modeset_pipes) { |
10545 | if (modeset_pipes) { |
9607 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
10546 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
9608 | if (IS_ERR(pipe_config)) { |
10547 | if (IS_ERR(pipe_config)) { |
9609 | ret = PTR_ERR(pipe_config); |
10548 | ret = PTR_ERR(pipe_config); |
9610 | pipe_config = NULL; |
10549 | pipe_config = NULL; |
9611 | 10550 | ||
9612 | goto out; |
10551 | goto out; |
9613 | } |
10552 | } |
9614 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10553 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9615 | "[modeset]"); |
10554 | "[modeset]"); |
- | 10555 | to_intel_crtc(crtc)->new_config = pipe_config; |
|
9616 | } |
10556 | } |
9617 | 10557 | ||
9618 | /* |
10558 | /* |
9619 | * See if the config requires any additional preparation, e.g. |
10559 | * See if the config requires any additional preparation, e.g. |
9620 | * to adjust global state with pipes off. We need to do this |
10560 | * to adjust global state with pipes off. We need to do this |
9621 | * here so we can get the modeset_pipe updated config for the new |
10561 | * here so we can get the modeset_pipe updated config for the new |
9622 | * mode set on this crtc. For other crtcs we need to use the |
10562 | * mode set on this crtc. For other crtcs we need to use the |
9623 | * adjusted_mode bits in the crtc directly. |
10563 | * adjusted_mode bits in the crtc directly. |
9624 | */ |
10564 | */ |
9625 | if (IS_VALLEYVIEW(dev)) { |
10565 | if (IS_VALLEYVIEW(dev)) { |
9626 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
10566 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
9627 | modeset_pipes, pipe_config); |
- | |
9628 | 10567 | ||
9629 | /* may have added more to prepare_pipes than we should */ |
10568 | /* may have added more to prepare_pipes than we should */ |
9630 | prepare_pipes &= ~disable_pipes; |
10569 | prepare_pipes &= ~disable_pipes; |
9631 | } |
10570 | } |
9632 | 10571 | ||
9633 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10572 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9634 | intel_crtc_disable(&intel_crtc->base); |
10573 | intel_crtc_disable(&intel_crtc->base); |
9635 | 10574 | ||
9636 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10575 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9637 | if (intel_crtc->base.enabled) |
10576 | if (intel_crtc->base.enabled) |
9638 | dev_priv->display.crtc_disable(&intel_crtc->base); |
10577 | dev_priv->display.crtc_disable(&intel_crtc->base); |
9639 | } |
10578 | } |
9640 | 10579 | ||
9641 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10580 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9642 | * to set it here already despite that we pass it down the callchain. |
10581 | * to set it here already despite that we pass it down the callchain. |
9643 | */ |
10582 | */ |
9644 | if (modeset_pipes) { |
10583 | if (modeset_pipes) { |
9645 | crtc->mode = *mode; |
10584 | crtc->mode = *mode; |
9646 | /* mode_set/enable/disable functions rely on a correct pipe |
10585 | /* mode_set/enable/disable functions rely on a correct pipe |
9647 | * config. */ |
10586 | * config. */ |
9648 | to_intel_crtc(crtc)->config = *pipe_config; |
10587 | to_intel_crtc(crtc)->config = *pipe_config; |
- | 10588 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
|
9649 | 10589 | ||
9650 | /* |
10590 | /* |
9651 | * Calculate and store various constants which |
10591 | * Calculate and store various constants which |
9652 | * are later needed by vblank and swap-completion |
10592 | * are later needed by vblank and swap-completion |
9653 | * timestamping. They are derived from true hwmode. |
10593 | * timestamping. They are derived from true hwmode. |
9654 | */ |
10594 | */ |
9655 | drm_calc_timestamping_constants(crtc, |
10595 | drm_calc_timestamping_constants(crtc, |
9656 | &pipe_config->adjusted_mode); |
10596 | &pipe_config->adjusted_mode); |
9657 | } |
10597 | } |
9658 | 10598 | ||
9659 | /* Only after disabling all output pipelines that will be changed can we |
10599 | /* Only after disabling all output pipelines that will be changed can we |
9660 | * update the the output configuration. */ |
10600 | * update the the output configuration. */ |
9661 | intel_modeset_update_state(dev, prepare_pipes); |
10601 | intel_modeset_update_state(dev, prepare_pipes); |
9662 | 10602 | ||
9663 | if (dev_priv->display.modeset_global_resources) |
10603 | if (dev_priv->display.modeset_global_resources) |
9664 | dev_priv->display.modeset_global_resources(dev); |
10604 | dev_priv->display.modeset_global_resources(dev); |
9665 | 10605 | ||
9666 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10606 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9667 | * on the DPLL. |
10607 | * on the DPLL. |
9668 | */ |
10608 | */ |
9669 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
10609 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
- | 10610 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
|
- | 10611 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
|
- | 10612 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
- | 10613 | ||
- | 10614 | mutex_lock(&dev->struct_mutex); |
|
- | 10615 | ret = intel_pin_and_fence_fb_obj(dev, |
|
- | 10616 | obj, |
|
- | 10617 | NULL); |
|
- | 10618 | if (ret != 0) { |
|
- | 10619 | DRM_ERROR("pin & fence failed\n"); |
|
- | 10620 | mutex_unlock(&dev->struct_mutex); |
|
- | 10621 | goto done; |
|
- | 10622 | } |
|
- | 10623 | if (old_fb) |
|
- | 10624 | intel_unpin_fb_obj(old_obj); |
|
- | 10625 | i915_gem_track_fb(old_obj, obj, |
|
- | 10626 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 10627 | mutex_unlock(&dev->struct_mutex); |
|
- | 10628 | ||
- | 10629 | crtc->primary->fb = fb; |
|
- | 10630 | crtc->x = x; |
|
- | 10631 | crtc->y = y; |
|
- | 10632 | ||
9670 | ret = intel_crtc_mode_set(&intel_crtc->base, |
10633 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
9671 | x, y, fb); |
10634 | x, y, fb); |
9672 | if (ret) |
10635 | if (ret) |
9673 | goto done; |
10636 | goto done; |
9674 | } |
10637 | } |
9675 | 10638 | ||
9676 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
10639 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
9677 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
10640 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
- | 10641 | update_scanline_offset(intel_crtc); |
|
- | 10642 | ||
9678 | dev_priv->display.crtc_enable(&intel_crtc->base); |
10643 | dev_priv->display.crtc_enable(&intel_crtc->base); |
- | 10644 | } |
|
9679 | 10645 | ||
9680 | /* FIXME: add subpixel order */ |
10646 | /* FIXME: add subpixel order */ |
9681 | done: |
10647 | done: |
9682 | if (ret && crtc->enabled) |
10648 | if (ret && crtc->enabled) |
9683 | crtc->mode = *saved_mode; |
10649 | crtc->mode = *saved_mode; |
9684 | 10650 | ||
9685 | out: |
10651 | out: |
9686 | kfree(pipe_config); |
10652 | kfree(pipe_config); |
9687 | kfree(saved_mode); |
10653 | kfree(saved_mode); |
9688 | return ret; |
10654 | return ret; |
9689 | } |
10655 | } |
9690 | 10656 | ||
9691 | static int intel_set_mode(struct drm_crtc *crtc, |
10657 | static int intel_set_mode(struct drm_crtc *crtc, |
9692 | struct drm_display_mode *mode, |
10658 | struct drm_display_mode *mode, |
9693 | int x, int y, struct drm_framebuffer *fb) |
10659 | int x, int y, struct drm_framebuffer *fb) |
9694 | { |
10660 | { |
9695 | int ret; |
10661 | int ret; |
9696 | 10662 | ||
9697 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
10663 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
9698 | 10664 | ||
9699 | if (ret == 0) |
10665 | if (ret == 0) |
9700 | intel_modeset_check_state(crtc->dev); |
10666 | intel_modeset_check_state(crtc->dev); |
9701 | 10667 | ||
9702 | return ret; |
10668 | return ret; |
9703 | } |
10669 | } |
9704 | 10670 | ||
9705 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10671 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9706 | { |
10672 | { |
9707 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
10673 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
9708 | } |
10674 | } |
9709 | 10675 | ||
9710 | #undef for_each_intel_crtc_masked |
10676 | #undef for_each_intel_crtc_masked |
9711 | 10677 | ||
9712 | static void intel_set_config_free(struct intel_set_config *config) |
10678 | static void intel_set_config_free(struct intel_set_config *config) |
9713 | { |
10679 | { |
9714 | if (!config) |
10680 | if (!config) |
9715 | return; |
10681 | return; |
9716 | 10682 | ||
9717 | kfree(config->save_connector_encoders); |
10683 | kfree(config->save_connector_encoders); |
9718 | kfree(config->save_encoder_crtcs); |
10684 | kfree(config->save_encoder_crtcs); |
- | 10685 | kfree(config->save_crtc_enabled); |
|
9719 | kfree(config); |
10686 | kfree(config); |
9720 | } |
10687 | } |
9721 | 10688 | ||
9722 | static int intel_set_config_save_state(struct drm_device *dev, |
10689 | static int intel_set_config_save_state(struct drm_device *dev, |
9723 | struct intel_set_config *config) |
10690 | struct intel_set_config *config) |
9724 | { |
10691 | { |
- | 10692 | struct drm_crtc *crtc; |
|
9725 | struct drm_encoder *encoder; |
10693 | struct drm_encoder *encoder; |
9726 | struct drm_connector *connector; |
10694 | struct drm_connector *connector; |
9727 | int count; |
10695 | int count; |
- | 10696 | ||
- | 10697 | config->save_crtc_enabled = |
|
- | 10698 | kcalloc(dev->mode_config.num_crtc, |
|
- | 10699 | sizeof(bool), GFP_KERNEL); |
|
- | 10700 | if (!config->save_crtc_enabled) |
|
- | 10701 | return -ENOMEM; |
|
9728 | 10702 | ||
9729 | config->save_encoder_crtcs = |
10703 | config->save_encoder_crtcs = |
9730 | kcalloc(dev->mode_config.num_encoder, |
10704 | kcalloc(dev->mode_config.num_encoder, |
9731 | sizeof(struct drm_crtc *), GFP_KERNEL); |
10705 | sizeof(struct drm_crtc *), GFP_KERNEL); |
9732 | if (!config->save_encoder_crtcs) |
10706 | if (!config->save_encoder_crtcs) |
9733 | return -ENOMEM; |
10707 | return -ENOMEM; |
9734 | 10708 | ||
9735 | config->save_connector_encoders = |
10709 | config->save_connector_encoders = |
9736 | kcalloc(dev->mode_config.num_connector, |
10710 | kcalloc(dev->mode_config.num_connector, |
9737 | sizeof(struct drm_encoder *), GFP_KERNEL); |
10711 | sizeof(struct drm_encoder *), GFP_KERNEL); |
9738 | if (!config->save_connector_encoders) |
10712 | if (!config->save_connector_encoders) |
9739 | return -ENOMEM; |
10713 | return -ENOMEM; |
9740 | 10714 | ||
9741 | /* Copy data. Note that driver private data is not affected. |
10715 | /* Copy data. Note that driver private data is not affected. |
9742 | * Should anything bad happen only the expected state is |
10716 | * Should anything bad happen only the expected state is |
9743 | * restored, not the drivers personal bookkeeping. |
10717 | * restored, not the drivers personal bookkeeping. |
9744 | */ |
10718 | */ |
9745 | count = 0; |
10719 | count = 0; |
- | 10720 | for_each_crtc(dev, crtc) { |
|
- | 10721 | config->save_crtc_enabled[count++] = crtc->enabled; |
|
- | 10722 | } |
|
- | 10723 | ||
- | 10724 | count = 0; |
|
9746 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
10725 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
9747 | config->save_encoder_crtcs[count++] = encoder->crtc; |
10726 | config->save_encoder_crtcs[count++] = encoder->crtc; |
9748 | } |
10727 | } |
9749 | 10728 | ||
9750 | count = 0; |
10729 | count = 0; |
9751 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
10730 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9752 | config->save_connector_encoders[count++] = connector->encoder; |
10731 | config->save_connector_encoders[count++] = connector->encoder; |
9753 | } |
10732 | } |
9754 | 10733 | ||
9755 | return 0; |
10734 | return 0; |
9756 | } |
10735 | } |
9757 | 10736 | ||
9758 | static void intel_set_config_restore_state(struct drm_device *dev, |
10737 | static void intel_set_config_restore_state(struct drm_device *dev, |
9759 | struct intel_set_config *config) |
10738 | struct intel_set_config *config) |
9760 | { |
10739 | { |
- | 10740 | struct intel_crtc *crtc; |
|
9761 | struct intel_encoder *encoder; |
10741 | struct intel_encoder *encoder; |
9762 | struct intel_connector *connector; |
10742 | struct intel_connector *connector; |
9763 | int count; |
10743 | int count; |
9764 | 10744 | ||
9765 | count = 0; |
10745 | count = 0; |
- | 10746 | for_each_intel_crtc(dev, crtc) { |
|
- | 10747 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
|
- | 10748 | ||
- | 10749 | if (crtc->new_enabled) |
|
- | 10750 | crtc->new_config = &crtc->config; |
|
- | 10751 | else |
|
- | 10752 | crtc->new_config = NULL; |
|
- | 10753 | } |
|
- | 10754 | ||
- | 10755 | count = 0; |
|
9766 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10756 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9767 | encoder->new_crtc = |
10757 | encoder->new_crtc = |
9768 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
10758 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
9769 | } |
10759 | } |
9770 | 10760 | ||
9771 | count = 0; |
10761 | count = 0; |
9772 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10762 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9773 | connector->new_encoder = |
10763 | connector->new_encoder = |
9774 | to_intel_encoder(config->save_connector_encoders[count++]); |
10764 | to_intel_encoder(config->save_connector_encoders[count++]); |
9775 | } |
10765 | } |
9776 | } |
10766 | } |
9777 | 10767 | ||
9778 | static bool |
10768 | static bool |
9779 | is_crtc_connector_off(struct drm_mode_set *set) |
10769 | is_crtc_connector_off(struct drm_mode_set *set) |
9780 | { |
10770 | { |
9781 | int i; |
10771 | int i; |
9782 | 10772 | ||
9783 | if (set->num_connectors == 0) |
10773 | if (set->num_connectors == 0) |
9784 | return false; |
10774 | return false; |
9785 | 10775 | ||
9786 | if (WARN_ON(set->connectors == NULL)) |
10776 | if (WARN_ON(set->connectors == NULL)) |
9787 | return false; |
10777 | return false; |
9788 | 10778 | ||
9789 | for (i = 0; i < set->num_connectors; i++) |
10779 | for (i = 0; i < set->num_connectors; i++) |
9790 | if (set->connectors[i]->encoder && |
10780 | if (set->connectors[i]->encoder && |
9791 | set->connectors[i]->encoder->crtc == set->crtc && |
10781 | set->connectors[i]->encoder->crtc == set->crtc && |
9792 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
10782 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
9793 | return true; |
10783 | return true; |
9794 | 10784 | ||
9795 | return false; |
10785 | return false; |
9796 | } |
10786 | } |
9797 | 10787 | ||
9798 | static void |
10788 | static void |
9799 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
10789 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
9800 | struct intel_set_config *config) |
10790 | struct intel_set_config *config) |
9801 | { |
10791 | { |
9802 | 10792 | ||
9803 | /* We should be able to check here if the fb has the same properties |
10793 | /* We should be able to check here if the fb has the same properties |
9804 | * and then just flip_or_move it */ |
10794 | * and then just flip_or_move it */ |
9805 | if (is_crtc_connector_off(set)) { |
10795 | if (is_crtc_connector_off(set)) { |
9806 | config->mode_changed = true; |
10796 | config->mode_changed = true; |
9807 | } else if (set->crtc->fb != set->fb) { |
10797 | } else if (set->crtc->primary->fb != set->fb) { |
- | 10798 | /* |
|
9808 | /* If we have no fb then treat it as a full mode set */ |
10799 | * If we have no fb, we can only flip as long as the crtc is |
- | 10800 | * active, otherwise we need a full mode set. The crtc may |
|
- | 10801 | * be active if we've only disabled the primary plane, or |
|
- | 10802 | * in fastboot situations. |
|
- | 10803 | */ |
|
9809 | if (set->crtc->fb == NULL) { |
10804 | if (set->crtc->primary->fb == NULL) { |
9810 | struct intel_crtc *intel_crtc = |
10805 | struct intel_crtc *intel_crtc = |
9811 | to_intel_crtc(set->crtc); |
10806 | to_intel_crtc(set->crtc); |
9812 | 10807 | ||
9813 | if (intel_crtc->active && i915_fastboot) { |
10808 | if (intel_crtc->active) { |
9814 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10809 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9815 | config->fb_changed = true; |
10810 | config->fb_changed = true; |
9816 | } else { |
10811 | } else { |
9817 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
10812 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9818 | config->mode_changed = true; |
10813 | config->mode_changed = true; |
9819 | } |
10814 | } |
9820 | } else if (set->fb == NULL) { |
10815 | } else if (set->fb == NULL) { |
9821 | config->mode_changed = true; |
10816 | config->mode_changed = true; |
9822 | } else if (set->fb->pixel_format != |
10817 | } else if (set->fb->pixel_format != |
9823 | set->crtc->fb->pixel_format) { |
10818 | set->crtc->primary->fb->pixel_format) { |
9824 | config->mode_changed = true; |
10819 | config->mode_changed = true; |
9825 | } else { |
10820 | } else { |
9826 | config->fb_changed = true; |
10821 | config->fb_changed = true; |
9827 | } |
10822 | } |
9828 | } |
10823 | } |
9829 | 10824 | ||
9830 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
10825 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
9831 | config->fb_changed = true; |
10826 | config->fb_changed = true; |
9832 | 10827 | ||
9833 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
10828 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
9834 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
10829 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
9835 | drm_mode_debug_printmodeline(&set->crtc->mode); |
10830 | drm_mode_debug_printmodeline(&set->crtc->mode); |
9836 | drm_mode_debug_printmodeline(set->mode); |
10831 | drm_mode_debug_printmodeline(set->mode); |
9837 | config->mode_changed = true; |
10832 | config->mode_changed = true; |
9838 | } |
10833 | } |
9839 | 10834 | ||
9840 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
10835 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
9841 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
10836 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
9842 | } |
10837 | } |
9843 | 10838 | ||
9844 | static int |
10839 | static int |
9845 | intel_modeset_stage_output_state(struct drm_device *dev, |
10840 | intel_modeset_stage_output_state(struct drm_device *dev, |
9846 | struct drm_mode_set *set, |
10841 | struct drm_mode_set *set, |
9847 | struct intel_set_config *config) |
10842 | struct intel_set_config *config) |
9848 | { |
10843 | { |
9849 | struct drm_crtc *new_crtc; |
- | |
9850 | struct intel_connector *connector; |
10844 | struct intel_connector *connector; |
9851 | struct intel_encoder *encoder; |
10845 | struct intel_encoder *encoder; |
- | 10846 | struct intel_crtc *crtc; |
|
9852 | int ro; |
10847 | int ro; |
9853 | 10848 | ||
9854 | /* The upper layers ensure that we either disable a crtc or have a list |
10849 | /* The upper layers ensure that we either disable a crtc or have a list |
9855 | * of connectors. For paranoia, double-check this. */ |
10850 | * of connectors. For paranoia, double-check this. */ |
9856 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
10851 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
9857 | WARN_ON(set->fb && (set->num_connectors == 0)); |
10852 | WARN_ON(set->fb && (set->num_connectors == 0)); |
9858 | 10853 | ||
9859 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10854 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9860 | base.head) { |
10855 | base.head) { |
9861 | /* Otherwise traverse passed in connector list and get encoders |
10856 | /* Otherwise traverse passed in connector list and get encoders |
9862 | * for them. */ |
10857 | * for them. */ |
9863 | for (ro = 0; ro < set->num_connectors; ro++) { |
10858 | for (ro = 0; ro < set->num_connectors; ro++) { |
9864 | if (set->connectors[ro] == &connector->base) { |
10859 | if (set->connectors[ro] == &connector->base) { |
9865 | connector->new_encoder = connector->encoder; |
10860 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
9866 | break; |
10861 | break; |
9867 | } |
10862 | } |
9868 | } |
10863 | } |
9869 | 10864 | ||
9870 | /* If we disable the crtc, disable all its connectors. Also, if |
10865 | /* If we disable the crtc, disable all its connectors. Also, if |
9871 | * the connector is on the changing crtc but not on the new |
10866 | * the connector is on the changing crtc but not on the new |
9872 | * connector list, disable it. */ |
10867 | * connector list, disable it. */ |
9873 | if ((!set->fb || ro == set->num_connectors) && |
10868 | if ((!set->fb || ro == set->num_connectors) && |
9874 | connector->base.encoder && |
10869 | connector->base.encoder && |
9875 | connector->base.encoder->crtc == set->crtc) { |
10870 | connector->base.encoder->crtc == set->crtc) { |
9876 | connector->new_encoder = NULL; |
10871 | connector->new_encoder = NULL; |
9877 | 10872 | ||
9878 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
10873 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9879 | connector->base.base.id, |
10874 | connector->base.base.id, |
9880 | drm_get_connector_name(&connector->base)); |
10875 | connector->base.name); |
9881 | } |
10876 | } |
9882 | 10877 | ||
9883 | 10878 | ||
9884 | if (&connector->new_encoder->base != connector->base.encoder) { |
10879 | if (&connector->new_encoder->base != connector->base.encoder) { |
9885 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
10880 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
9886 | config->mode_changed = true; |
10881 | config->mode_changed = true; |
9887 | } |
10882 | } |
9888 | } |
10883 | } |
9889 | /* connector->new_encoder is now updated for all connectors. */ |
10884 | /* connector->new_encoder is now updated for all connectors. */ |
9890 | 10885 | ||
9891 | /* Update crtc of enabled connectors. */ |
10886 | /* Update crtc of enabled connectors. */ |
9892 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10887 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9893 | base.head) { |
10888 | base.head) { |
- | 10889 | struct drm_crtc *new_crtc; |
|
- | 10890 | ||
9894 | if (!connector->new_encoder) |
10891 | if (!connector->new_encoder) |
9895 | continue; |
10892 | continue; |
9896 | 10893 | ||
9897 | new_crtc = connector->new_encoder->base.crtc; |
10894 | new_crtc = connector->new_encoder->base.crtc; |
9898 | 10895 | ||
9899 | for (ro = 0; ro < set->num_connectors; ro++) { |
10896 | for (ro = 0; ro < set->num_connectors; ro++) { |
9900 | if (set->connectors[ro] == &connector->base) |
10897 | if (set->connectors[ro] == &connector->base) |
9901 | new_crtc = set->crtc; |
10898 | new_crtc = set->crtc; |
9902 | } |
10899 | } |
9903 | 10900 | ||
9904 | /* Make sure the new CRTC will work with the encoder */ |
10901 | /* Make sure the new CRTC will work with the encoder */ |
9905 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10902 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9906 | new_crtc)) { |
10903 | new_crtc)) { |
9907 | return -EINVAL; |
10904 | return -EINVAL; |
9908 | } |
10905 | } |
9909 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10906 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9910 | 10907 | ||
9911 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
10908 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9912 | connector->base.base.id, |
10909 | connector->base.base.id, |
9913 | drm_get_connector_name(&connector->base), |
10910 | connector->base.name, |
9914 | new_crtc->base.id); |
10911 | new_crtc->base.id); |
9915 | } |
10912 | } |
9916 | 10913 | ||
9917 | /* Check for any encoders that needs to be disabled. */ |
10914 | /* Check for any encoders that needs to be disabled. */ |
9918 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10915 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9919 | base.head) { |
10916 | base.head) { |
9920 | int num_connectors = 0; |
10917 | int num_connectors = 0; |
9921 | list_for_each_entry(connector, |
10918 | list_for_each_entry(connector, |
9922 | &dev->mode_config.connector_list, |
10919 | &dev->mode_config.connector_list, |
9923 | base.head) { |
10920 | base.head) { |
9924 | if (connector->new_encoder == encoder) { |
10921 | if (connector->new_encoder == encoder) { |
9925 | WARN_ON(!connector->new_encoder->new_crtc); |
10922 | WARN_ON(!connector->new_encoder->new_crtc); |
9926 | num_connectors++; |
10923 | num_connectors++; |
9927 | } |
10924 | } |
9928 | } |
10925 | } |
9929 | 10926 | ||
9930 | if (num_connectors == 0) |
10927 | if (num_connectors == 0) |
9931 | encoder->new_crtc = NULL; |
10928 | encoder->new_crtc = NULL; |
9932 | else if (num_connectors > 1) |
10929 | else if (num_connectors > 1) |
9933 | return -EINVAL; |
10930 | return -EINVAL; |
9934 | 10931 | ||
9935 | /* Only now check for crtc changes so we don't miss encoders |
10932 | /* Only now check for crtc changes so we don't miss encoders |
9936 | * that will be disabled. */ |
10933 | * that will be disabled. */ |
9937 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
10934 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9938 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
10935 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9939 | config->mode_changed = true; |
10936 | config->mode_changed = true; |
9940 | } |
10937 | } |
9941 | } |
10938 | } |
9942 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
10939 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
- | 10940 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
|
- | 10941 | base.head) { |
|
- | 10942 | if (connector->new_encoder) |
|
- | 10943 | if (connector->new_encoder != connector->encoder) |
|
- | 10944 | connector->encoder = connector->new_encoder; |
|
- | 10945 | } |
|
- | 10946 | for_each_intel_crtc(dev, crtc) { |
|
- | 10947 | crtc->new_enabled = false; |
|
- | 10948 | ||
- | 10949 | list_for_each_entry(encoder, |
|
- | 10950 | &dev->mode_config.encoder_list, |
|
- | 10951 | base.head) { |
|
- | 10952 | if (encoder->new_crtc == crtc) { |
|
- | 10953 | crtc->new_enabled = true; |
|
- | 10954 | break; |
|
- | 10955 | } |
|
- | 10956 | } |
|
- | 10957 | ||
- | 10958 | if (crtc->new_enabled != crtc->base.enabled) { |
|
- | 10959 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
|
- | 10960 | crtc->new_enabled ? "en" : "dis"); |
|
- | 10961 | config->mode_changed = true; |
|
- | 10962 | } |
|
- | 10963 | ||
- | 10964 | if (crtc->new_enabled) |
|
- | 10965 | crtc->new_config = &crtc->config; |
|
- | 10966 | else |
|
- | 10967 | crtc->new_config = NULL; |
|
- | 10968 | } |
|
9943 | 10969 | ||
9944 | return 0; |
10970 | return 0; |
9945 | } |
10971 | } |
- | 10972 | ||
- | 10973 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
|
- | 10974 | { |
|
- | 10975 | struct drm_device *dev = crtc->base.dev; |
|
- | 10976 | struct intel_encoder *encoder; |
|
- | 10977 | struct intel_connector *connector; |
|
- | 10978 | ||
- | 10979 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", |
|
- | 10980 | pipe_name(crtc->pipe)); |
|
- | 10981 | ||
- | 10982 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
|
- | 10983 | if (connector->new_encoder && |
|
- | 10984 | connector->new_encoder->new_crtc == crtc) |
|
- | 10985 | connector->new_encoder = NULL; |
|
- | 10986 | } |
|
- | 10987 | ||
- | 10988 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
|
- | 10989 | if (encoder->new_crtc == crtc) |
|
- | 10990 | encoder->new_crtc = NULL; |
|
- | 10991 | } |
|
- | 10992 | ||
- | 10993 | crtc->new_enabled = false; |
|
- | 10994 | crtc->new_config = NULL; |
|
- | 10995 | } |
|
9946 | 10996 | ||
9947 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10997 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9948 | { |
10998 | { |
9949 | struct drm_device *dev; |
10999 | struct drm_device *dev; |
9950 | struct drm_mode_set save_set; |
11000 | struct drm_mode_set save_set; |
9951 | struct intel_set_config *config; |
11001 | struct intel_set_config *config; |
9952 | int ret; |
11002 | int ret; |
9953 | 11003 | ||
9954 | BUG_ON(!set); |
11004 | BUG_ON(!set); |
9955 | BUG_ON(!set->crtc); |
11005 | BUG_ON(!set->crtc); |
9956 | BUG_ON(!set->crtc->helper_private); |
11006 | BUG_ON(!set->crtc->helper_private); |
9957 | 11007 | ||
9958 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11008 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9959 | BUG_ON(!set->mode && set->fb); |
11009 | BUG_ON(!set->mode && set->fb); |
9960 | BUG_ON(set->fb && set->num_connectors == 0); |
11010 | BUG_ON(set->fb && set->num_connectors == 0); |
9961 | 11011 | ||
9962 | if (set->fb) { |
11012 | if (set->fb) { |
9963 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
11013 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
9964 | set->crtc->base.id, set->fb->base.id, |
11014 | set->crtc->base.id, set->fb->base.id, |
9965 | (int)set->num_connectors, set->x, set->y); |
11015 | (int)set->num_connectors, set->x, set->y); |
9966 | } else { |
11016 | } else { |
9967 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
11017 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
9968 | } |
11018 | } |
9969 | 11019 | ||
9970 | dev = set->crtc->dev; |
11020 | dev = set->crtc->dev; |
9971 | 11021 | ||
9972 | ret = -ENOMEM; |
11022 | ret = -ENOMEM; |
9973 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
11023 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
9974 | if (!config) |
11024 | if (!config) |
9975 | goto out_config; |
11025 | goto out_config; |
9976 | 11026 | ||
9977 | ret = intel_set_config_save_state(dev, config); |
11027 | ret = intel_set_config_save_state(dev, config); |
9978 | if (ret) |
11028 | if (ret) |
9979 | goto out_config; |
11029 | goto out_config; |
9980 | 11030 | ||
9981 | save_set.crtc = set->crtc; |
11031 | save_set.crtc = set->crtc; |
9982 | save_set.mode = &set->crtc->mode; |
11032 | save_set.mode = &set->crtc->mode; |
9983 | save_set.x = set->crtc->x; |
11033 | save_set.x = set->crtc->x; |
9984 | save_set.y = set->crtc->y; |
11034 | save_set.y = set->crtc->y; |
9985 | save_set.fb = set->crtc->fb; |
11035 | save_set.fb = set->crtc->primary->fb; |
9986 | 11036 | ||
9987 | /* Compute whether we need a full modeset, only an fb base update or no |
11037 | /* Compute whether we need a full modeset, only an fb base update or no |
9988 | * change at all. In the future we might also check whether only the |
11038 | * change at all. In the future we might also check whether only the |
9989 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
11039 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
9990 | * such cases. */ |
11040 | * such cases. */ |
9991 | intel_set_config_compute_mode_changes(set, config); |
11041 | intel_set_config_compute_mode_changes(set, config); |
9992 | 11042 | ||
9993 | ret = intel_modeset_stage_output_state(dev, set, config); |
11043 | ret = intel_modeset_stage_output_state(dev, set, config); |
9994 | if (ret) |
11044 | if (ret) |
9995 | goto fail; |
11045 | goto fail; |
9996 | 11046 | ||
9997 | if (config->mode_changed) { |
11047 | if (config->mode_changed) { |
9998 | ret = intel_set_mode(set->crtc, set->mode, |
11048 | ret = intel_set_mode(set->crtc, set->mode, |
9999 | set->x, set->y, set->fb); |
11049 | set->x, set->y, set->fb); |
10000 | } else if (config->fb_changed) { |
11050 | } else if (config->fb_changed) { |
- | 11051 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
10001 | // intel_crtc_wait_for_pending_flips(set->crtc); |
11052 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
- | 11053 | ||
10002 | 11054 | ||
10003 | ret = intel_pipe_set_base(set->crtc, |
11055 | ret = intel_pipe_set_base(set->crtc, |
10004 | set->x, set->y, set->fb); |
11056 | set->x, set->y, set->fb); |
- | 11057 | ||
- | 11058 | /* |
|
- | 11059 | * We need to make sure the primary plane is re-enabled if it |
|
- | 11060 | * has previously been turned off. |
|
- | 11061 | */ |
|
- | 11062 | if (!intel_crtc->primary_enabled && ret == 0) { |
|
- | 11063 | WARN_ON(!intel_crtc->active); |
|
- | 11064 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, |
|
- | 11065 | intel_crtc->pipe); |
|
- | 11066 | } |
|
- | 11067 | ||
10005 | /* |
11068 | /* |
10006 | * In the fastboot case this may be our only check of the |
11069 | * In the fastboot case this may be our only check of the |
10007 | * state after boot. It would be better to only do it on |
11070 | * state after boot. It would be better to only do it on |
10008 | * the first update, but we don't have a nice way of doing that |
11071 | * the first update, but we don't have a nice way of doing that |
10009 | * (and really, set_config isn't used much for high freq page |
11072 | * (and really, set_config isn't used much for high freq page |
10010 | * flipping, so increasing its cost here shouldn't be a big |
11073 | * flipping, so increasing its cost here shouldn't be a big |
10011 | * deal). |
11074 | * deal). |
10012 | */ |
11075 | */ |
10013 | if (i915_fastboot && ret == 0) |
11076 | if (i915.fastboot && ret == 0) |
10014 | intel_modeset_check_state(set->crtc->dev); |
11077 | intel_modeset_check_state(set->crtc->dev); |
10015 | } |
11078 | } |
10016 | 11079 | ||
10017 | if (ret) { |
11080 | if (ret) { |
10018 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11081 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10019 | set->crtc->base.id, ret); |
11082 | set->crtc->base.id, ret); |
10020 | fail: |
11083 | fail: |
10021 | intel_set_config_restore_state(dev, config); |
11084 | intel_set_config_restore_state(dev, config); |
- | 11085 | ||
- | 11086 | /* |
|
- | 11087 | * HACK: if the pipe was on, but we didn't have a framebuffer, |
|
- | 11088 | * force the pipe off to avoid oopsing in the modeset code |
|
- | 11089 | * due to fb==NULL. This should only happen during boot since |
|
- | 11090 | * we don't yet reconstruct the FB from the hardware state. |
|
- | 11091 | */ |
|
- | 11092 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
|
- | 11093 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
|
10022 | 11094 | ||
10023 | /* Try to restore the config */ |
11095 | /* Try to restore the config */ |
10024 | if (config->mode_changed && |
11096 | if (config->mode_changed && |
10025 | intel_set_mode(save_set.crtc, save_set.mode, |
11097 | intel_set_mode(save_set.crtc, save_set.mode, |
10026 | save_set.x, save_set.y, save_set.fb)) |
11098 | save_set.x, save_set.y, save_set.fb)) |
10027 | DRM_ERROR("failed to restore config after modeset failure\n"); |
11099 | DRM_ERROR("failed to restore config after modeset failure\n"); |
10028 | } |
11100 | } |
10029 | 11101 | ||
10030 | out_config: |
11102 | out_config: |
10031 | intel_set_config_free(config); |
11103 | intel_set_config_free(config); |
10032 | return ret; |
11104 | return ret; |
10033 | } |
11105 | } |
10034 | 11106 | ||
10035 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
11107 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
10036 | // .cursor_set = intel_crtc_cursor_set, |
- | |
10037 | .cursor_move = intel_crtc_cursor_move, |
- | |
10038 | .gamma_set = intel_crtc_gamma_set, |
11108 | .gamma_set = intel_crtc_gamma_set, |
10039 | .set_config = intel_crtc_set_config, |
11109 | .set_config = intel_crtc_set_config, |
10040 | .destroy = intel_crtc_destroy, |
11110 | .destroy = intel_crtc_destroy, |
10041 | // .page_flip = intel_crtc_page_flip, |
11111 | // .page_flip = intel_crtc_page_flip, |
10042 | }; |
11112 | }; |
10043 | - | ||
10044 | static void intel_cpu_pll_init(struct drm_device *dev) |
- | |
10045 | { |
- | |
10046 | if (HAS_DDI(dev)) |
- | |
10047 | intel_ddi_pll_init(dev); |
- | |
10048 | } |
- | |
10049 | 11113 | ||
10050 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11114 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10051 | struct intel_shared_dpll *pll, |
11115 | struct intel_shared_dpll *pll, |
10052 | struct intel_dpll_hw_state *hw_state) |
11116 | struct intel_dpll_hw_state *hw_state) |
10053 | { |
11117 | { |
10054 | uint32_t val; |
11118 | uint32_t val; |
- | 11119 | ||
- | 11120 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
|
- | 11121 | return false; |
|
10055 | 11122 | ||
10056 | val = I915_READ(PCH_DPLL(pll->id)); |
11123 | val = I915_READ(PCH_DPLL(pll->id)); |
10057 | hw_state->dpll = val; |
11124 | hw_state->dpll = val; |
10058 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
11125 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
10059 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
11126 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
10060 | 11127 | ||
10061 | return val & DPLL_VCO_ENABLE; |
11128 | return val & DPLL_VCO_ENABLE; |
10062 | } |
11129 | } |
10063 | 11130 | ||
10064 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11131 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10065 | struct intel_shared_dpll *pll) |
11132 | struct intel_shared_dpll *pll) |
10066 | { |
11133 | { |
10067 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
11134 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
10068 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
11135 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
10069 | } |
11136 | } |
10070 | 11137 | ||
10071 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11138 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10072 | struct intel_shared_dpll *pll) |
11139 | struct intel_shared_dpll *pll) |
10073 | { |
11140 | { |
10074 | /* PCH refclock must be enabled first */ |
11141 | /* PCH refclock must be enabled first */ |
10075 | ibx_assert_pch_refclk_enabled(dev_priv); |
11142 | ibx_assert_pch_refclk_enabled(dev_priv); |
10076 | 11143 | ||
10077 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11144 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10078 | 11145 | ||
10079 | /* Wait for the clocks to stabilize. */ |
11146 | /* Wait for the clocks to stabilize. */ |
10080 | POSTING_READ(PCH_DPLL(pll->id)); |
11147 | POSTING_READ(PCH_DPLL(pll->id)); |
10081 | udelay(150); |
11148 | udelay(150); |
10082 | 11149 | ||
10083 | /* The pixel multiplier can only be updated once the |
11150 | /* The pixel multiplier can only be updated once the |
10084 | * DPLL is enabled and the clocks are stable. |
11151 | * DPLL is enabled and the clocks are stable. |
10085 | * |
11152 | * |
10086 | * So write it again. |
11153 | * So write it again. |
10087 | */ |
11154 | */ |
10088 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11155 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10089 | POSTING_READ(PCH_DPLL(pll->id)); |
11156 | POSTING_READ(PCH_DPLL(pll->id)); |
10090 | udelay(200); |
11157 | udelay(200); |
10091 | } |
11158 | } |
10092 | 11159 | ||
10093 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
11160 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
10094 | struct intel_shared_dpll *pll) |
11161 | struct intel_shared_dpll *pll) |
10095 | { |
11162 | { |
10096 | struct drm_device *dev = dev_priv->dev; |
11163 | struct drm_device *dev = dev_priv->dev; |
10097 | struct intel_crtc *crtc; |
11164 | struct intel_crtc *crtc; |
10098 | 11165 | ||
10099 | /* Make sure no transcoder isn't still depending on us. */ |
11166 | /* Make sure no transcoder isn't still depending on us. */ |
10100 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
11167 | for_each_intel_crtc(dev, crtc) { |
10101 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11168 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10102 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
11169 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
10103 | } |
11170 | } |
10104 | 11171 | ||
10105 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11172 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10106 | POSTING_READ(PCH_DPLL(pll->id)); |
11173 | POSTING_READ(PCH_DPLL(pll->id)); |
10107 | udelay(200); |
11174 | udelay(200); |
10108 | } |
11175 | } |
10109 | 11176 | ||
10110 | static char *ibx_pch_dpll_names[] = { |
11177 | static char *ibx_pch_dpll_names[] = { |
10111 | "PCH DPLL A", |
11178 | "PCH DPLL A", |
10112 | "PCH DPLL B", |
11179 | "PCH DPLL B", |
10113 | }; |
11180 | }; |
10114 | 11181 | ||
10115 | static void ibx_pch_dpll_init(struct drm_device *dev) |
11182 | static void ibx_pch_dpll_init(struct drm_device *dev) |
10116 | { |
11183 | { |
10117 | struct drm_i915_private *dev_priv = dev->dev_private; |
11184 | struct drm_i915_private *dev_priv = dev->dev_private; |
10118 | int i; |
11185 | int i; |
10119 | 11186 | ||
10120 | dev_priv->num_shared_dpll = 2; |
11187 | dev_priv->num_shared_dpll = 2; |
10121 | 11188 | ||
10122 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11189 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10123 | dev_priv->shared_dplls[i].id = i; |
11190 | dev_priv->shared_dplls[i].id = i; |
10124 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
11191 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
10125 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
11192 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
10126 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11193 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10127 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
11194 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
10128 | dev_priv->shared_dplls[i].get_hw_state = |
11195 | dev_priv->shared_dplls[i].get_hw_state = |
10129 | ibx_pch_dpll_get_hw_state; |
11196 | ibx_pch_dpll_get_hw_state; |
10130 | } |
11197 | } |
10131 | } |
11198 | } |
10132 | 11199 | ||
10133 | static void intel_shared_dpll_init(struct drm_device *dev) |
11200 | static void intel_shared_dpll_init(struct drm_device *dev) |
10134 | { |
11201 | { |
10135 | struct drm_i915_private *dev_priv = dev->dev_private; |
11202 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 11203 | ||
- | 11204 | if (HAS_DDI(dev)) |
|
10136 | 11205 | intel_ddi_pll_init(dev); |
|
10137 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
11206 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
10138 | ibx_pch_dpll_init(dev); |
11207 | ibx_pch_dpll_init(dev); |
10139 | else |
11208 | else |
10140 | dev_priv->num_shared_dpll = 0; |
11209 | dev_priv->num_shared_dpll = 0; |
10141 | 11210 | ||
10142 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
11211 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
10143 | } |
11212 | } |
- | 11213 | ||
- | 11214 | static int |
|
- | 11215 | intel_primary_plane_disable(struct drm_plane *plane) |
|
- | 11216 | { |
|
- | 11217 | struct drm_device *dev = plane->dev; |
|
- | 11218 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11219 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11220 | struct intel_crtc *intel_crtc; |
|
- | 11221 | ||
- | 11222 | if (!plane->fb) |
|
- | 11223 | return 0; |
|
- | 11224 | ||
- | 11225 | BUG_ON(!plane->crtc); |
|
- | 11226 | ||
- | 11227 | intel_crtc = to_intel_crtc(plane->crtc); |
|
- | 11228 | ||
- | 11229 | /* |
|
- | 11230 | * Even though we checked plane->fb above, it's still possible that |
|
- | 11231 | * the primary plane has been implicitly disabled because the crtc |
|
- | 11232 | * coordinates given weren't visible, or because we detected |
|
- | 11233 | * that it was 100% covered by a sprite plane. Or, the CRTC may be |
|
- | 11234 | * off and we've set a fb, but haven't actually turned on the CRTC yet. |
|
- | 11235 | * In either case, we need to unpin the FB and let the fb pointer get |
|
- | 11236 | * updated, but otherwise we don't need to touch the hardware. |
|
- | 11237 | */ |
|
- | 11238 | if (!intel_crtc->primary_enabled) |
|
- | 11239 | goto disable_unpin; |
|
- | 11240 | ||
- | 11241 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, |
|
- | 11242 | intel_plane->pipe); |
|
- | 11243 | disable_unpin: |
|
- | 11244 | mutex_lock(&dev->struct_mutex); |
|
- | 11245 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
|
- | 11246 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11247 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
|
- | 11248 | mutex_unlock(&dev->struct_mutex); |
|
- | 11249 | plane->fb = NULL; |
|
- | 11250 | ||
- | 11251 | return 0; |
|
- | 11252 | } |
|
- | 11253 | ||
- | 11254 | static int |
|
- | 11255 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, |
|
- | 11256 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
|
- | 11257 | unsigned int crtc_w, unsigned int crtc_h, |
|
- | 11258 | uint32_t src_x, uint32_t src_y, |
|
- | 11259 | uint32_t src_w, uint32_t src_h) |
|
- | 11260 | { |
|
- | 11261 | struct drm_device *dev = crtc->dev; |
|
- | 11262 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11263 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 11264 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11265 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
- | 11266 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
|
- | 11267 | struct drm_rect dest = { |
|
- | 11268 | /* integer pixels */ |
|
- | 11269 | .x1 = crtc_x, |
|
- | 11270 | .y1 = crtc_y, |
|
- | 11271 | .x2 = crtc_x + crtc_w, |
|
- | 11272 | .y2 = crtc_y + crtc_h, |
|
- | 11273 | }; |
|
- | 11274 | struct drm_rect src = { |
|
- | 11275 | /* 16.16 fixed point */ |
|
- | 11276 | .x1 = src_x, |
|
- | 11277 | .y1 = src_y, |
|
- | 11278 | .x2 = src_x + src_w, |
|
- | 11279 | .y2 = src_y + src_h, |
|
- | 11280 | }; |
|
- | 11281 | const struct drm_rect clip = { |
|
- | 11282 | /* integer pixels */ |
|
- | 11283 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
|
- | 11284 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
|
- | 11285 | }; |
|
- | 11286 | bool visible; |
|
- | 11287 | int ret; |
|
- | 11288 | ||
- | 11289 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
|
- | 11290 | &src, &dest, &clip, |
|
- | 11291 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11292 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11293 | false, true, &visible); |
|
- | 11294 | ||
- | 11295 | if (ret) |
|
- | 11296 | return ret; |
|
- | 11297 | ||
- | 11298 | /* |
|
- | 11299 | * If the CRTC isn't enabled, we're just pinning the framebuffer, |
|
- | 11300 | * updating the fb pointer, and returning without touching the |
|
- | 11301 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to |
|
- | 11302 | * turn on the display with all planes setup as desired. |
|
- | 11303 | */ |
|
- | 11304 | if (!crtc->enabled) { |
|
- | 11305 | mutex_lock(&dev->struct_mutex); |
|
- | 11306 | ||
- | 11307 | /* |
|
- | 11308 | * If we already called setplane while the crtc was disabled, |
|
- | 11309 | * we may have an fb pinned; unpin it. |
|
- | 11310 | */ |
|
- | 11311 | if (plane->fb) |
|
- | 11312 | intel_unpin_fb_obj(old_obj); |
|
- | 11313 | ||
- | 11314 | i915_gem_track_fb(old_obj, obj, |
|
- | 11315 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11316 | ||
- | 11317 | /* Pin and return without programming hardware */ |
|
- | 11318 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
|
- | 11319 | mutex_unlock(&dev->struct_mutex); |
|
- | 11320 | ||
- | 11321 | return ret; |
|
- | 11322 | } |
|
- | 11323 | ||
- | 11324 | ||
- | 11325 | /* |
|
- | 11326 | * If clipping results in a non-visible primary plane, we'll disable |
|
- | 11327 | * the primary plane. Note that this is a bit different than what |
|
- | 11328 | * happens if userspace explicitly disables the plane by passing fb=0 |
|
- | 11329 | * because plane->fb still gets set and pinned. |
|
- | 11330 | */ |
|
- | 11331 | if (!visible) { |
|
- | 11332 | mutex_lock(&dev->struct_mutex); |
|
- | 11333 | ||
- | 11334 | /* |
|
- | 11335 | * Try to pin the new fb first so that we can bail out if we |
|
- | 11336 | * fail. |
|
- | 11337 | */ |
|
- | 11338 | if (plane->fb != fb) { |
|
- | 11339 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
|
- | 11340 | if (ret) { |
|
- | 11341 | mutex_unlock(&dev->struct_mutex); |
|
- | 11342 | return ret; |
|
- | 11343 | } |
|
- | 11344 | } |
|
- | 11345 | ||
- | 11346 | i915_gem_track_fb(old_obj, obj, |
|
- | 11347 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11348 | ||
- | 11349 | if (intel_crtc->primary_enabled) |
|
- | 11350 | intel_disable_primary_hw_plane(dev_priv, |
|
- | 11351 | intel_plane->plane, |
|
- | 11352 | intel_plane->pipe); |
|
- | 11353 | ||
- | 11354 | ||
- | 11355 | if (plane->fb != fb) |
|
- | 11356 | if (plane->fb) |
|
- | 11357 | intel_unpin_fb_obj(old_obj); |
|
- | 11358 | ||
- | 11359 | mutex_unlock(&dev->struct_mutex); |
|
- | 11360 | ||
- | 11361 | return 0; |
|
- | 11362 | } |
|
- | 11363 | ||
- | 11364 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); |
|
- | 11365 | if (ret) |
|
- | 11366 | return ret; |
|
- | 11367 | ||
- | 11368 | if (!intel_crtc->primary_enabled) |
|
- | 11369 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, |
|
- | 11370 | intel_crtc->pipe); |
|
- | 11371 | ||
- | 11372 | return 0; |
|
- | 11373 | } |
|
- | 11374 | ||
- | 11375 | /* Common destruction function for both primary and cursor planes */ |
|
- | 11376 | static void intel_plane_destroy(struct drm_plane *plane) |
|
- | 11377 | { |
|
- | 11378 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11379 | drm_plane_cleanup(plane); |
|
- | 11380 | kfree(intel_plane); |
|
- | 11381 | } |
|
- | 11382 | ||
- | 11383 | static const struct drm_plane_funcs intel_primary_plane_funcs = { |
|
- | 11384 | .update_plane = intel_primary_plane_setplane, |
|
- | 11385 | .disable_plane = intel_primary_plane_disable, |
|
- | 11386 | .destroy = intel_plane_destroy, |
|
- | 11387 | }; |
|
- | 11388 | ||
- | 11389 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
|
- | 11390 | int pipe) |
|
- | 11391 | { |
|
- | 11392 | struct intel_plane *primary; |
|
- | 11393 | const uint32_t *intel_primary_formats; |
|
- | 11394 | int num_formats; |
|
- | 11395 | ||
- | 11396 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
|
- | 11397 | if (primary == NULL) |
|
- | 11398 | return NULL; |
|
- | 11399 | ||
- | 11400 | primary->can_scale = false; |
|
- | 11401 | primary->max_downscale = 1; |
|
- | 11402 | primary->pipe = pipe; |
|
- | 11403 | primary->plane = pipe; |
|
- | 11404 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
|
- | 11405 | primary->plane = !pipe; |
|
- | 11406 | ||
- | 11407 | if (INTEL_INFO(dev)->gen <= 3) { |
|
- | 11408 | intel_primary_formats = intel_primary_formats_gen2; |
|
- | 11409 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); |
|
- | 11410 | } else { |
|
- | 11411 | intel_primary_formats = intel_primary_formats_gen4; |
|
- | 11412 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); |
|
- | 11413 | } |
|
- | 11414 | ||
- | 11415 | drm_universal_plane_init(dev, &primary->base, 0, |
|
- | 11416 | &intel_primary_plane_funcs, |
|
- | 11417 | intel_primary_formats, num_formats, |
|
- | 11418 | DRM_PLANE_TYPE_PRIMARY); |
|
- | 11419 | return &primary->base; |
|
- | 11420 | } |
|
- | 11421 | ||
- | 11422 | static int |
|
- | 11423 | intel_cursor_plane_disable(struct drm_plane *plane) |
|
- | 11424 | { |
|
- | 11425 | if (!plane->fb) |
|
- | 11426 | return 0; |
|
- | 11427 | ||
- | 11428 | BUG_ON(!plane->crtc); |
|
- | 11429 | ||
- | 11430 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); |
|
- | 11431 | } |
|
- | 11432 | ||
- | 11433 | static int |
|
- | 11434 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
|
- | 11435 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
|
- | 11436 | unsigned int crtc_w, unsigned int crtc_h, |
|
- | 11437 | uint32_t src_x, uint32_t src_y, |
|
- | 11438 | uint32_t src_w, uint32_t src_h) |
|
- | 11439 | { |
|
- | 11440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 11441 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
|
- | 11442 | struct drm_i915_gem_object *obj = intel_fb->obj; |
|
- | 11443 | struct drm_rect dest = { |
|
- | 11444 | /* integer pixels */ |
|
- | 11445 | .x1 = crtc_x, |
|
- | 11446 | .y1 = crtc_y, |
|
- | 11447 | .x2 = crtc_x + crtc_w, |
|
- | 11448 | .y2 = crtc_y + crtc_h, |
|
- | 11449 | }; |
|
- | 11450 | struct drm_rect src = { |
|
- | 11451 | /* 16.16 fixed point */ |
|
- | 11452 | .x1 = src_x, |
|
- | 11453 | .y1 = src_y, |
|
- | 11454 | .x2 = src_x + src_w, |
|
- | 11455 | .y2 = src_y + src_h, |
|
- | 11456 | }; |
|
- | 11457 | const struct drm_rect clip = { |
|
- | 11458 | /* integer pixels */ |
|
- | 11459 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
|
- | 11460 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
|
- | 11461 | }; |
|
- | 11462 | bool visible; |
|
- | 11463 | int ret; |
|
- | 11464 | ||
- | 11465 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
|
- | 11466 | &src, &dest, &clip, |
|
- | 11467 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11468 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11469 | true, true, &visible); |
|
- | 11470 | if (ret) |
|
- | 11471 | return ret; |
|
- | 11472 | ||
- | 11473 | crtc->cursor_x = crtc_x; |
|
- | 11474 | crtc->cursor_y = crtc_y; |
|
- | 11475 | if (fb != crtc->cursor->fb) { |
|
- | 11476 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
|
- | 11477 | } else { |
|
- | 11478 | intel_crtc_update_cursor(crtc, visible); |
|
- | 11479 | return 0; |
|
- | 11480 | } |
|
- | 11481 | } |
|
- | 11482 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
|
- | 11483 | .update_plane = intel_cursor_plane_update, |
|
- | 11484 | .disable_plane = intel_cursor_plane_disable, |
|
- | 11485 | .destroy = intel_plane_destroy, |
|
- | 11486 | }; |
|
- | 11487 | ||
- | 11488 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
|
- | 11489 | int pipe) |
|
- | 11490 | { |
|
- | 11491 | struct intel_plane *cursor; |
|
- | 11492 | ||
- | 11493 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
|
- | 11494 | if (cursor == NULL) |
|
- | 11495 | return NULL; |
|
- | 11496 | ||
- | 11497 | cursor->can_scale = false; |
|
- | 11498 | cursor->max_downscale = 1; |
|
- | 11499 | cursor->pipe = pipe; |
|
- | 11500 | cursor->plane = pipe; |
|
- | 11501 | ||
- | 11502 | drm_universal_plane_init(dev, &cursor->base, 0, |
|
- | 11503 | &intel_cursor_plane_funcs, |
|
- | 11504 | intel_cursor_formats, |
|
- | 11505 | ARRAY_SIZE(intel_cursor_formats), |
|
- | 11506 | DRM_PLANE_TYPE_CURSOR); |
|
- | 11507 | return &cursor->base; |
|
- | 11508 | } |
|
10144 | 11509 | ||
10145 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
11510 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
10146 | { |
11511 | { |
10147 | drm_i915_private_t *dev_priv = dev->dev_private; |
11512 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 11513 | struct intel_crtc *intel_crtc; |
|
- | 11514 | struct drm_plane *primary = NULL; |
|
10148 | struct intel_crtc *intel_crtc; |
11515 | struct drm_plane *cursor = NULL; |
10149 | int i; |
11516 | int i, ret; |
10150 | 11517 | ||
10151 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
11518 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
10152 | if (intel_crtc == NULL) |
11519 | if (intel_crtc == NULL) |
10153 | return; |
11520 | return; |
- | 11521 | ||
- | 11522 | primary = intel_primary_plane_create(dev, pipe); |
|
- | 11523 | if (!primary) |
|
- | 11524 | goto fail; |
|
- | 11525 | ||
- | 11526 | cursor = intel_cursor_plane_create(dev, pipe); |
|
- | 11527 | if (!cursor) |
|
- | 11528 | goto fail; |
|
10154 | 11529 | ||
- | 11530 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
|
- | 11531 | cursor, &intel_crtc_funcs); |
|
- | 11532 | if (ret) |
|
10155 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
11533 | goto fail; |
10156 | 11534 | ||
10157 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
11535 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
10158 | for (i = 0; i < 256; i++) { |
11536 | for (i = 0; i < 256; i++) { |
10159 | intel_crtc->lut_r[i] = i; |
11537 | intel_crtc->lut_r[i] = i; |
10160 | intel_crtc->lut_g[i] = i; |
11538 | intel_crtc->lut_g[i] = i; |
10161 | intel_crtc->lut_b[i] = i; |
11539 | intel_crtc->lut_b[i] = i; |
10162 | } |
11540 | } |
10163 | 11541 | ||
10164 | /* |
11542 | /* |
10165 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
11543 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
10166 | * is hooked to plane B. Hence we want plane A feeding pipe B. |
11544 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
10167 | */ |
11545 | */ |
10168 | intel_crtc->pipe = pipe; |
11546 | intel_crtc->pipe = pipe; |
10169 | intel_crtc->plane = pipe; |
11547 | intel_crtc->plane = pipe; |
10170 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
11548 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
10171 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
11549 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
10172 | intel_crtc->plane = !pipe; |
11550 | intel_crtc->plane = !pipe; |
10173 | } |
11551 | } |
- | 11552 | ||
- | 11553 | intel_crtc->cursor_base = ~0; |
|
- | 11554 | intel_crtc->cursor_cntl = ~0; |
|
- | 11555 | ||
- | 11556 | init_waitqueue_head(&intel_crtc->vbl_wait); |
|
10174 | 11557 | ||
10175 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11558 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10176 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
11559 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
10177 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
11560 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
10178 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
11561 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
10179 | 11562 | ||
10180 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
11563 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
- | 11564 | ||
- | 11565 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
|
- | 11566 | return; |
|
- | 11567 | ||
- | 11568 | fail: |
|
- | 11569 | if (primary) |
|
- | 11570 | drm_plane_cleanup(primary); |
|
- | 11571 | if (cursor) |
|
- | 11572 | drm_plane_cleanup(cursor); |
|
- | 11573 | kfree(intel_crtc); |
|
10181 | } |
11574 | } |
10182 | 11575 | ||
10183 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11576 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10184 | { |
11577 | { |
10185 | struct drm_encoder *encoder = connector->base.encoder; |
11578 | struct drm_encoder *encoder = connector->base.encoder; |
- | 11579 | struct drm_device *dev = connector->base.dev; |
|
10186 | 11580 | ||
10187 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); |
11581 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
10188 | 11582 | ||
10189 | if (!encoder) |
11583 | if (!encoder) |
10190 | return INVALID_PIPE; |
11584 | return INVALID_PIPE; |
10191 | 11585 | ||
10192 | return to_intel_crtc(encoder->crtc)->pipe; |
11586 | return to_intel_crtc(encoder->crtc)->pipe; |
10193 | } |
11587 | } |
10194 | 11588 | ||
10195 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
11589 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
10196 | struct drm_file *file) |
11590 | struct drm_file *file) |
10197 | { |
11591 | { |
10198 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
11592 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
10199 | struct drm_mode_object *drmmode_obj; |
11593 | struct drm_crtc *drmmode_crtc; |
10200 | struct intel_crtc *crtc; |
11594 | struct intel_crtc *crtc; |
10201 | 11595 | ||
10202 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11596 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10203 | return -ENODEV; |
11597 | return -ENODEV; |
10204 | 11598 | ||
10205 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
- | |
10206 | DRM_MODE_OBJECT_CRTC); |
11599 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
10207 | 11600 | ||
10208 | if (!drmmode_obj) { |
11601 | if (!drmmode_crtc) { |
10209 | DRM_ERROR("no such CRTC id\n"); |
11602 | DRM_ERROR("no such CRTC id\n"); |
10210 | return -ENOENT; |
11603 | return -ENOENT; |
10211 | } |
11604 | } |
10212 | 11605 | ||
10213 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11606 | crtc = to_intel_crtc(drmmode_crtc); |
10214 | pipe_from_crtc_id->pipe = crtc->pipe; |
11607 | pipe_from_crtc_id->pipe = crtc->pipe; |
10215 | 11608 | ||
10216 | return 0; |
11609 | return 0; |
10217 | } |
11610 | } |
10218 | 11611 | ||
10219 | static int intel_encoder_clones(struct intel_encoder *encoder) |
11612 | static int intel_encoder_clones(struct intel_encoder *encoder) |
10220 | { |
11613 | { |
10221 | struct drm_device *dev = encoder->base.dev; |
11614 | struct drm_device *dev = encoder->base.dev; |
10222 | struct intel_encoder *source_encoder; |
11615 | struct intel_encoder *source_encoder; |
10223 | int index_mask = 0; |
11616 | int index_mask = 0; |
10224 | int entry = 0; |
11617 | int entry = 0; |
10225 | 11618 | ||
10226 | list_for_each_entry(source_encoder, |
11619 | list_for_each_entry(source_encoder, |
10227 | &dev->mode_config.encoder_list, base.head) { |
11620 | &dev->mode_config.encoder_list, base.head) { |
10228 | - | ||
10229 | if (encoder == source_encoder) |
- | |
10230 | index_mask |= (1 << entry); |
- | |
10231 | - | ||
10232 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
- | |
10233 | if (encoder->cloneable && source_encoder->cloneable) |
11621 | if (encoders_cloneable(encoder, source_encoder)) |
10234 | index_mask |= (1 << entry); |
11622 | index_mask |= (1 << entry); |
10235 | 11623 | ||
10236 | entry++; |
11624 | entry++; |
10237 | } |
11625 | } |
10238 | 11626 | ||
10239 | return index_mask; |
11627 | return index_mask; |
10240 | } |
11628 | } |
10241 | 11629 | ||
10242 | static bool has_edp_a(struct drm_device *dev) |
11630 | static bool has_edp_a(struct drm_device *dev) |
10243 | { |
11631 | { |
10244 | struct drm_i915_private *dev_priv = dev->dev_private; |
11632 | struct drm_i915_private *dev_priv = dev->dev_private; |
10245 | 11633 | ||
10246 | if (!IS_MOBILE(dev)) |
11634 | if (!IS_MOBILE(dev)) |
10247 | return false; |
11635 | return false; |
10248 | 11636 | ||
10249 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
11637 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
10250 | return false; |
11638 | return false; |
10251 | - | ||
10252 | if (IS_GEN5(dev) && |
11639 | |
10253 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
11640 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
10254 | return false; |
11641 | return false; |
10255 | 11642 | ||
10256 | return true; |
11643 | return true; |
10257 | } |
11644 | } |
10258 | 11645 | ||
10259 | const char *intel_output_name(int output) |
11646 | const char *intel_output_name(int output) |
10260 | { |
11647 | { |
10261 | static const char *names[] = { |
11648 | static const char *names[] = { |
10262 | [INTEL_OUTPUT_UNUSED] = "Unused", |
11649 | [INTEL_OUTPUT_UNUSED] = "Unused", |
10263 | [INTEL_OUTPUT_ANALOG] = "Analog", |
11650 | [INTEL_OUTPUT_ANALOG] = "Analog", |
10264 | [INTEL_OUTPUT_DVO] = "DVO", |
11651 | [INTEL_OUTPUT_DVO] = "DVO", |
10265 | [INTEL_OUTPUT_SDVO] = "SDVO", |
11652 | [INTEL_OUTPUT_SDVO] = "SDVO", |
10266 | [INTEL_OUTPUT_LVDS] = "LVDS", |
11653 | [INTEL_OUTPUT_LVDS] = "LVDS", |
10267 | [INTEL_OUTPUT_TVOUT] = "TV", |
11654 | [INTEL_OUTPUT_TVOUT] = "TV", |
10268 | [INTEL_OUTPUT_HDMI] = "HDMI", |
11655 | [INTEL_OUTPUT_HDMI] = "HDMI", |
10269 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
11656 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
10270 | [INTEL_OUTPUT_EDP] = "eDP", |
11657 | [INTEL_OUTPUT_EDP] = "eDP", |
10271 | [INTEL_OUTPUT_DSI] = "DSI", |
11658 | [INTEL_OUTPUT_DSI] = "DSI", |
10272 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", |
11659 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", |
10273 | }; |
11660 | }; |
10274 | 11661 | ||
10275 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
11662 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
10276 | return "Invalid"; |
11663 | return "Invalid"; |
10277 | 11664 | ||
10278 | return names[output]; |
11665 | return names[output]; |
10279 | } |
11666 | } |
- | 11667 | ||
- | 11668 | static bool intel_crt_present(struct drm_device *dev) |
|
- | 11669 | { |
|
- | 11670 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11671 | ||
- | 11672 | if (IS_ULT(dev)) |
|
- | 11673 | return false; |
|
- | 11674 | ||
- | 11675 | if (IS_CHERRYVIEW(dev)) |
|
- | 11676 | return false; |
|
- | 11677 | ||
- | 11678 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) |
|
- | 11679 | return false; |
|
- | 11680 | ||
- | 11681 | return true; |
|
- | 11682 | } |
|
10280 | 11683 | ||
10281 | static void intel_setup_outputs(struct drm_device *dev) |
11684 | static void intel_setup_outputs(struct drm_device *dev) |
10282 | { |
11685 | { |
10283 | struct drm_i915_private *dev_priv = dev->dev_private; |
11686 | struct drm_i915_private *dev_priv = dev->dev_private; |
10284 | struct intel_encoder *encoder; |
11687 | struct intel_encoder *encoder; |
10285 | bool dpd_is_edp = false; |
11688 | bool dpd_is_edp = false; |
10286 | 11689 | ||
10287 | intel_lvds_init(dev); |
11690 | intel_lvds_init(dev); |
10288 | 11691 | ||
10289 | if (!IS_ULT(dev)) |
11692 | if (intel_crt_present(dev)) |
10290 | intel_crt_init(dev); |
11693 | intel_crt_init(dev); |
10291 | 11694 | ||
10292 | if (HAS_DDI(dev)) { |
11695 | if (HAS_DDI(dev)) { |
10293 | int found; |
11696 | int found; |
10294 | 11697 | ||
10295 | /* Haswell uses DDI functions to detect digital outputs */ |
11698 | /* Haswell uses DDI functions to detect digital outputs */ |
10296 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
11699 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
10297 | /* DDI A only supports eDP */ |
11700 | /* DDI A only supports eDP */ |
10298 | if (found) |
11701 | if (found) |
10299 | intel_ddi_init(dev, PORT_A); |
11702 | intel_ddi_init(dev, PORT_A); |
10300 | 11703 | ||
10301 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
11704 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
10302 | * register */ |
11705 | * register */ |
10303 | found = I915_READ(SFUSE_STRAP); |
11706 | found = I915_READ(SFUSE_STRAP); |
10304 | 11707 | ||
10305 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
11708 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
10306 | intel_ddi_init(dev, PORT_B); |
11709 | intel_ddi_init(dev, PORT_B); |
10307 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
11710 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
10308 | intel_ddi_init(dev, PORT_C); |
11711 | intel_ddi_init(dev, PORT_C); |
10309 | if (found & SFUSE_STRAP_DDID_DETECTED) |
11712 | if (found & SFUSE_STRAP_DDID_DETECTED) |
10310 | intel_ddi_init(dev, PORT_D); |
11713 | intel_ddi_init(dev, PORT_D); |
10311 | } else if (HAS_PCH_SPLIT(dev)) { |
11714 | } else if (HAS_PCH_SPLIT(dev)) { |
10312 | int found; |
11715 | int found; |
10313 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
11716 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
10314 | 11717 | ||
10315 | if (has_edp_a(dev)) |
11718 | if (has_edp_a(dev)) |
10316 | intel_dp_init(dev, DP_A, PORT_A); |
11719 | intel_dp_init(dev, DP_A, PORT_A); |
10317 | 11720 | ||
10318 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
11721 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
10319 | /* PCH SDVOB multiplex with HDMIB */ |
11722 | /* PCH SDVOB multiplex with HDMIB */ |
10320 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
11723 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
10321 | if (!found) |
11724 | if (!found) |
10322 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
11725 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
10323 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
11726 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
10324 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
11727 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
10325 | } |
11728 | } |
10326 | 11729 | ||
10327 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
11730 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
10328 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
11731 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
10329 | 11732 | ||
10330 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
11733 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
10331 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
11734 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
10332 | 11735 | ||
10333 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
11736 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
10334 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
11737 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
10335 | 11738 | ||
10336 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
11739 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
10337 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
11740 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
10338 | } else if (IS_VALLEYVIEW(dev)) { |
11741 | } else if (IS_VALLEYVIEW(dev)) { |
10339 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11742 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10340 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
11743 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
10341 | PORT_B); |
11744 | PORT_B); |
10342 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
11745 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
10343 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
11746 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
10344 | } |
11747 | } |
10345 | 11748 | ||
10346 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11749 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10347 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
11750 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
10348 | PORT_C); |
11751 | PORT_C); |
10349 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
11752 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
10350 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
11753 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
10351 | } |
11754 | } |
- | 11755 | ||
- | 11756 | if (IS_CHERRYVIEW(dev)) { |
|
- | 11757 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { |
|
- | 11758 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
|
- | 11759 | PORT_D); |
|
- | 11760 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) |
|
- | 11761 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); |
|
- | 11762 | } |
|
- | 11763 | } |
|
10352 | 11764 | ||
10353 | intel_dsi_init(dev); |
11765 | intel_dsi_init(dev); |
10354 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
11766 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
10355 | bool found = false; |
11767 | bool found = false; |
10356 | 11768 | ||
10357 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
11769 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
10358 | DRM_DEBUG_KMS("probing SDVOB\n"); |
11770 | DRM_DEBUG_KMS("probing SDVOB\n"); |
10359 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
11771 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
10360 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11772 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10361 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
11773 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
10362 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
11774 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
10363 | } |
11775 | } |
10364 | 11776 | ||
10365 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
11777 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
10366 | intel_dp_init(dev, DP_B, PORT_B); |
11778 | intel_dp_init(dev, DP_B, PORT_B); |
10367 | } |
11779 | } |
10368 | 11780 | ||
10369 | /* Before G4X SDVOC doesn't have its own detect register */ |
11781 | /* Before G4X SDVOC doesn't have its own detect register */ |
10370 | 11782 | ||
10371 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
11783 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
10372 | DRM_DEBUG_KMS("probing SDVOC\n"); |
11784 | DRM_DEBUG_KMS("probing SDVOC\n"); |
10373 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
11785 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
10374 | } |
11786 | } |
10375 | 11787 | ||
10376 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
11788 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
10377 | 11789 | ||
10378 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11790 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10379 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
11791 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
10380 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
11792 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
10381 | } |
11793 | } |
10382 | if (SUPPORTS_INTEGRATED_DP(dev)) |
11794 | if (SUPPORTS_INTEGRATED_DP(dev)) |
10383 | intel_dp_init(dev, DP_C, PORT_C); |
11795 | intel_dp_init(dev, DP_C, PORT_C); |
10384 | } |
11796 | } |
10385 | 11797 | ||
10386 | if (SUPPORTS_INTEGRATED_DP(dev) && |
11798 | if (SUPPORTS_INTEGRATED_DP(dev) && |
10387 | (I915_READ(DP_D) & DP_DETECTED)) |
11799 | (I915_READ(DP_D) & DP_DETECTED)) |
10388 | intel_dp_init(dev, DP_D, PORT_D); |
11800 | intel_dp_init(dev, DP_D, PORT_D); |
10389 | } else if (IS_GEN2(dev)) |
11801 | } else if (IS_GEN2(dev)) |
10390 | intel_dvo_init(dev); |
11802 | intel_dvo_init(dev); |
10391 | - | ||
- | 11803 | ||
10392 | // if (SUPPORTS_TV(dev)) |
11804 | |
10393 | // intel_tv_init(dev); |
11805 | intel_edp_psr_init(dev); |
10394 | 11806 | ||
10395 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11807 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10396 | encoder->base.possible_crtcs = encoder->crtc_mask; |
11808 | encoder->base.possible_crtcs = encoder->crtc_mask; |
10397 | encoder->base.possible_clones = |
11809 | encoder->base.possible_clones = |
10398 | intel_encoder_clones(encoder); |
11810 | intel_encoder_clones(encoder); |
10399 | } |
11811 | } |
10400 | 11812 | ||
10401 | intel_init_pch_refclk(dev); |
11813 | intel_init_pch_refclk(dev); |
10402 | 11814 | ||
10403 | drm_helper_move_panel_connectors_to_head(dev); |
11815 | drm_helper_move_panel_connectors_to_head(dev); |
10404 | } |
11816 | } |
10405 | 11817 | ||
10406 | 11818 | ||
10407 | 11819 | ||
10408 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
11820 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
10409 | // .destroy = intel_user_framebuffer_destroy, |
11821 | // .destroy = intel_user_framebuffer_destroy, |
10410 | // .create_handle = intel_user_framebuffer_create_handle, |
11822 | // .create_handle = intel_user_framebuffer_create_handle, |
10411 | }; |
11823 | }; |
10412 | 11824 | ||
10413 | int intel_framebuffer_init(struct drm_device *dev, |
11825 | static int intel_framebuffer_init(struct drm_device *dev, |
10414 | struct intel_framebuffer *intel_fb, |
11826 | struct intel_framebuffer *intel_fb, |
10415 | struct drm_mode_fb_cmd2 *mode_cmd, |
11827 | struct drm_mode_fb_cmd2 *mode_cmd, |
10416 | struct drm_i915_gem_object *obj) |
11828 | struct drm_i915_gem_object *obj) |
10417 | { |
11829 | { |
10418 | int aligned_height, tile_height; |
11830 | int aligned_height; |
10419 | int pitch_limit; |
11831 | int pitch_limit; |
10420 | int ret; |
11832 | int ret; |
10421 | 11833 | ||
10422 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11834 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10423 | 11835 | ||
10424 | if (obj->tiling_mode == I915_TILING_Y) { |
11836 | if (obj->tiling_mode == I915_TILING_Y) { |
10425 | DRM_DEBUG("hardware does not support tiling Y\n"); |
11837 | DRM_DEBUG("hardware does not support tiling Y\n"); |
10426 | return -EINVAL; |
11838 | return -EINVAL; |
10427 | } |
11839 | } |
10428 | 11840 | ||
10429 | if (mode_cmd->pitches[0] & 63) { |
11841 | if (mode_cmd->pitches[0] & 63) { |
10430 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
11842 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
10431 | mode_cmd->pitches[0]); |
11843 | mode_cmd->pitches[0]); |
10432 | return -EINVAL; |
11844 | return -EINVAL; |
10433 | } |
11845 | } |
10434 | 11846 | ||
10435 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11847 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10436 | pitch_limit = 32*1024; |
11848 | pitch_limit = 32*1024; |
10437 | } else if (INTEL_INFO(dev)->gen >= 4) { |
11849 | } else if (INTEL_INFO(dev)->gen >= 4) { |
10438 | if (obj->tiling_mode) |
11850 | if (obj->tiling_mode) |
10439 | pitch_limit = 16*1024; |
11851 | pitch_limit = 16*1024; |
10440 | else |
11852 | else |
10441 | pitch_limit = 32*1024; |
11853 | pitch_limit = 32*1024; |
10442 | } else if (INTEL_INFO(dev)->gen >= 3) { |
11854 | } else if (INTEL_INFO(dev)->gen >= 3) { |
10443 | if (obj->tiling_mode) |
11855 | if (obj->tiling_mode) |
10444 | pitch_limit = 8*1024; |
11856 | pitch_limit = 8*1024; |
10445 | else |
11857 | else |
10446 | pitch_limit = 16*1024; |
11858 | pitch_limit = 16*1024; |
10447 | } else |
11859 | } else |
10448 | /* XXX DSPC is limited to 4k tiled */ |
11860 | /* XXX DSPC is limited to 4k tiled */ |
10449 | pitch_limit = 8*1024; |
11861 | pitch_limit = 8*1024; |
10450 | 11862 | ||
10451 | if (mode_cmd->pitches[0] > pitch_limit) { |
11863 | if (mode_cmd->pitches[0] > pitch_limit) { |
10452 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
11864 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
10453 | obj->tiling_mode ? "tiled" : "linear", |
11865 | obj->tiling_mode ? "tiled" : "linear", |
10454 | mode_cmd->pitches[0], pitch_limit); |
11866 | mode_cmd->pitches[0], pitch_limit); |
10455 | return -EINVAL; |
11867 | return -EINVAL; |
10456 | } |
11868 | } |
10457 | 11869 | ||
10458 | if (obj->tiling_mode != I915_TILING_NONE && |
11870 | if (obj->tiling_mode != I915_TILING_NONE && |
10459 | mode_cmd->pitches[0] != obj->stride) { |
11871 | mode_cmd->pitches[0] != obj->stride) { |
10460 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
11872 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
10461 | mode_cmd->pitches[0], obj->stride); |
11873 | mode_cmd->pitches[0], obj->stride); |
10462 | return -EINVAL; |
11874 | return -EINVAL; |
10463 | } |
11875 | } |
10464 | 11876 | ||
10465 | /* Reject formats not supported by any plane early. */ |
11877 | /* Reject formats not supported by any plane early. */ |
10466 | switch (mode_cmd->pixel_format) { |
11878 | switch (mode_cmd->pixel_format) { |
10467 | case DRM_FORMAT_C8: |
11879 | case DRM_FORMAT_C8: |
10468 | case DRM_FORMAT_RGB565: |
11880 | case DRM_FORMAT_RGB565: |
10469 | case DRM_FORMAT_XRGB8888: |
11881 | case DRM_FORMAT_XRGB8888: |
10470 | case DRM_FORMAT_ARGB8888: |
11882 | case DRM_FORMAT_ARGB8888: |
10471 | break; |
11883 | break; |
10472 | case DRM_FORMAT_XRGB1555: |
11884 | case DRM_FORMAT_XRGB1555: |
10473 | case DRM_FORMAT_ARGB1555: |
11885 | case DRM_FORMAT_ARGB1555: |
10474 | if (INTEL_INFO(dev)->gen > 3) { |
11886 | if (INTEL_INFO(dev)->gen > 3) { |
10475 | DRM_DEBUG("unsupported pixel format: %s\n", |
11887 | DRM_DEBUG("unsupported pixel format: %s\n", |
10476 | drm_get_format_name(mode_cmd->pixel_format)); |
11888 | drm_get_format_name(mode_cmd->pixel_format)); |
10477 | return -EINVAL; |
11889 | return -EINVAL; |
10478 | } |
11890 | } |
10479 | break; |
11891 | break; |
10480 | case DRM_FORMAT_XBGR8888: |
11892 | case DRM_FORMAT_XBGR8888: |
10481 | case DRM_FORMAT_ABGR8888: |
11893 | case DRM_FORMAT_ABGR8888: |
10482 | case DRM_FORMAT_XRGB2101010: |
11894 | case DRM_FORMAT_XRGB2101010: |
10483 | case DRM_FORMAT_ARGB2101010: |
11895 | case DRM_FORMAT_ARGB2101010: |
10484 | case DRM_FORMAT_XBGR2101010: |
11896 | case DRM_FORMAT_XBGR2101010: |
10485 | case DRM_FORMAT_ABGR2101010: |
11897 | case DRM_FORMAT_ABGR2101010: |
10486 | if (INTEL_INFO(dev)->gen < 4) { |
11898 | if (INTEL_INFO(dev)->gen < 4) { |
10487 | DRM_DEBUG("unsupported pixel format: %s\n", |
11899 | DRM_DEBUG("unsupported pixel format: %s\n", |
10488 | drm_get_format_name(mode_cmd->pixel_format)); |
11900 | drm_get_format_name(mode_cmd->pixel_format)); |
10489 | return -EINVAL; |
11901 | return -EINVAL; |
10490 | } |
11902 | } |
10491 | break; |
11903 | break; |
10492 | case DRM_FORMAT_YUYV: |
11904 | case DRM_FORMAT_YUYV: |
10493 | case DRM_FORMAT_UYVY: |
11905 | case DRM_FORMAT_UYVY: |
10494 | case DRM_FORMAT_YVYU: |
11906 | case DRM_FORMAT_YVYU: |
10495 | case DRM_FORMAT_VYUY: |
11907 | case DRM_FORMAT_VYUY: |
10496 | if (INTEL_INFO(dev)->gen < 5) { |
11908 | if (INTEL_INFO(dev)->gen < 5) { |
10497 | DRM_DEBUG("unsupported pixel format: %s\n", |
11909 | DRM_DEBUG("unsupported pixel format: %s\n", |
10498 | drm_get_format_name(mode_cmd->pixel_format)); |
11910 | drm_get_format_name(mode_cmd->pixel_format)); |
10499 | return -EINVAL; |
11911 | return -EINVAL; |
10500 | } |
11912 | } |
10501 | break; |
11913 | break; |
10502 | default: |
11914 | default: |
10503 | DRM_DEBUG("unsupported pixel format: %s\n", |
11915 | DRM_DEBUG("unsupported pixel format: %s\n", |
10504 | drm_get_format_name(mode_cmd->pixel_format)); |
11916 | drm_get_format_name(mode_cmd->pixel_format)); |
10505 | return -EINVAL; |
11917 | return -EINVAL; |
10506 | } |
11918 | } |
10507 | 11919 | ||
10508 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11920 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10509 | if (mode_cmd->offsets[0] != 0) |
11921 | if (mode_cmd->offsets[0] != 0) |
10510 | return -EINVAL; |
11922 | return -EINVAL; |
10511 | - | ||
10512 | tile_height = IS_GEN2(dev) ? 16 : 8; |
11923 | |
10513 | aligned_height = ALIGN(mode_cmd->height, |
11924 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10514 | obj->tiling_mode ? tile_height : 1); |
11925 | obj->tiling_mode); |
10515 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11926 | /* FIXME drm helper for size checks (especially planar formats)? */ |
10516 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
11927 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
10517 | return -EINVAL; |
11928 | return -EINVAL; |
10518 | 11929 | ||
10519 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11930 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10520 | intel_fb->obj = obj; |
11931 | intel_fb->obj = obj; |
10521 | intel_fb->obj->framebuffer_references++; |
11932 | intel_fb->obj->framebuffer_references++; |
10522 | 11933 | ||
10523 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11934 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10524 | if (ret) { |
11935 | if (ret) { |
10525 | DRM_ERROR("framebuffer init failed %d\n", ret); |
11936 | DRM_ERROR("framebuffer init failed %d\n", ret); |
10526 | return ret; |
11937 | return ret; |
10527 | } |
11938 | } |
10528 | 11939 | ||
10529 | return 0; |
11940 | return 0; |
10530 | } |
11941 | } |
10531 | 11942 | ||
10532 | #ifndef CONFIG_DRM_I915_FBDEV |
11943 | #ifndef CONFIG_DRM_I915_FBDEV |
10533 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
11944 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
10534 | { |
11945 | { |
10535 | } |
11946 | } |
10536 | #endif |
11947 | #endif |
10537 | 11948 | ||
10538 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
11949 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
10539 | .fb_create = NULL, |
11950 | .fb_create = NULL, |
10540 | .output_poll_changed = intel_fbdev_output_poll_changed, |
11951 | .output_poll_changed = intel_fbdev_output_poll_changed, |
10541 | }; |
11952 | }; |
10542 | 11953 | ||
10543 | /* Set up chip specific display functions */ |
11954 | /* Set up chip specific display functions */ |
10544 | static void intel_init_display(struct drm_device *dev) |
11955 | static void intel_init_display(struct drm_device *dev) |
10545 | { |
11956 | { |
10546 | struct drm_i915_private *dev_priv = dev->dev_private; |
11957 | struct drm_i915_private *dev_priv = dev->dev_private; |
10547 | 11958 | ||
10548 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11959 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10549 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
11960 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
- | 11961 | else if (IS_CHERRYVIEW(dev)) |
|
- | 11962 | dev_priv->display.find_dpll = chv_find_best_dpll; |
|
10550 | else if (IS_VALLEYVIEW(dev)) |
11963 | else if (IS_VALLEYVIEW(dev)) |
10551 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
11964 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
10552 | else if (IS_PINEVIEW(dev)) |
11965 | else if (IS_PINEVIEW(dev)) |
10553 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
11966 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
10554 | else |
11967 | else |
10555 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
11968 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
10556 | 11969 | ||
10557 | if (HAS_DDI(dev)) { |
11970 | if (HAS_DDI(dev)) { |
10558 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
11971 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
- | 11972 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
|
10559 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
11973 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
10560 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11974 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10561 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
11975 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
10562 | dev_priv->display.off = haswell_crtc_off; |
11976 | dev_priv->display.off = ironlake_crtc_off; |
10563 | dev_priv->display.update_plane = ironlake_update_plane; |
11977 | dev_priv->display.update_primary_plane = |
- | 11978 | ironlake_update_primary_plane; |
|
10564 | } else if (HAS_PCH_SPLIT(dev)) { |
11979 | } else if (HAS_PCH_SPLIT(dev)) { |
10565 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
11980 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
- | 11981 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
|
10566 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
11982 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
10567 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11983 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10568 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
11984 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
10569 | dev_priv->display.off = ironlake_crtc_off; |
11985 | dev_priv->display.off = ironlake_crtc_off; |
10570 | dev_priv->display.update_plane = ironlake_update_plane; |
11986 | dev_priv->display.update_primary_plane = |
- | 11987 | ironlake_update_primary_plane; |
|
10571 | } else if (IS_VALLEYVIEW(dev)) { |
11988 | } else if (IS_VALLEYVIEW(dev)) { |
10572 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11989 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
- | 11990 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
|
10573 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11991 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10574 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
11992 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
10575 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
11993 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10576 | dev_priv->display.off = i9xx_crtc_off; |
11994 | dev_priv->display.off = i9xx_crtc_off; |
10577 | dev_priv->display.update_plane = i9xx_update_plane; |
11995 | dev_priv->display.update_primary_plane = |
- | 11996 | i9xx_update_primary_plane; |
|
10578 | } else { |
11997 | } else { |
10579 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11998 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
- | 11999 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
|
10580 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12000 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10581 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12001 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10582 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
12002 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10583 | dev_priv->display.off = i9xx_crtc_off; |
12003 | dev_priv->display.off = i9xx_crtc_off; |
10584 | dev_priv->display.update_plane = i9xx_update_plane; |
12004 | dev_priv->display.update_primary_plane = |
- | 12005 | i9xx_update_primary_plane; |
|
10585 | } |
12006 | } |
10586 | 12007 | ||
10587 | /* Returns the core display clock speed */ |
12008 | /* Returns the core display clock speed */ |
10588 | if (IS_VALLEYVIEW(dev)) |
12009 | if (IS_VALLEYVIEW(dev)) |
10589 | dev_priv->display.get_display_clock_speed = |
12010 | dev_priv->display.get_display_clock_speed = |
10590 | valleyview_get_display_clock_speed; |
12011 | valleyview_get_display_clock_speed; |
10591 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
12012 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
10592 | dev_priv->display.get_display_clock_speed = |
12013 | dev_priv->display.get_display_clock_speed = |
10593 | i945_get_display_clock_speed; |
12014 | i945_get_display_clock_speed; |
10594 | else if (IS_I915G(dev)) |
12015 | else if (IS_I915G(dev)) |
10595 | dev_priv->display.get_display_clock_speed = |
12016 | dev_priv->display.get_display_clock_speed = |
10596 | i915_get_display_clock_speed; |
12017 | i915_get_display_clock_speed; |
10597 | else if (IS_I945GM(dev) || IS_845G(dev)) |
12018 | else if (IS_I945GM(dev) || IS_845G(dev)) |
10598 | dev_priv->display.get_display_clock_speed = |
12019 | dev_priv->display.get_display_clock_speed = |
10599 | i9xx_misc_get_display_clock_speed; |
12020 | i9xx_misc_get_display_clock_speed; |
10600 | else if (IS_PINEVIEW(dev)) |
12021 | else if (IS_PINEVIEW(dev)) |
10601 | dev_priv->display.get_display_clock_speed = |
12022 | dev_priv->display.get_display_clock_speed = |
10602 | pnv_get_display_clock_speed; |
12023 | pnv_get_display_clock_speed; |
10603 | else if (IS_I915GM(dev)) |
12024 | else if (IS_I915GM(dev)) |
10604 | dev_priv->display.get_display_clock_speed = |
12025 | dev_priv->display.get_display_clock_speed = |
10605 | i915gm_get_display_clock_speed; |
12026 | i915gm_get_display_clock_speed; |
10606 | else if (IS_I865G(dev)) |
12027 | else if (IS_I865G(dev)) |
10607 | dev_priv->display.get_display_clock_speed = |
12028 | dev_priv->display.get_display_clock_speed = |
10608 | i865_get_display_clock_speed; |
12029 | i865_get_display_clock_speed; |
10609 | else if (IS_I85X(dev)) |
12030 | else if (IS_I85X(dev)) |
10610 | dev_priv->display.get_display_clock_speed = |
12031 | dev_priv->display.get_display_clock_speed = |
10611 | i855_get_display_clock_speed; |
12032 | i855_get_display_clock_speed; |
10612 | else /* 852, 830 */ |
12033 | else /* 852, 830 */ |
10613 | dev_priv->display.get_display_clock_speed = |
12034 | dev_priv->display.get_display_clock_speed = |
10614 | i830_get_display_clock_speed; |
12035 | i830_get_display_clock_speed; |
10615 | 12036 | ||
10616 | if (HAS_PCH_SPLIT(dev)) { |
12037 | if (HAS_PCH_SPLIT(dev)) { |
10617 | if (IS_GEN5(dev)) { |
12038 | if (IS_GEN5(dev)) { |
10618 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
12039 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
10619 | dev_priv->display.write_eld = ironlake_write_eld; |
12040 | dev_priv->display.write_eld = ironlake_write_eld; |
10620 | } else if (IS_GEN6(dev)) { |
12041 | } else if (IS_GEN6(dev)) { |
10621 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
12042 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
10622 | dev_priv->display.write_eld = ironlake_write_eld; |
12043 | dev_priv->display.write_eld = ironlake_write_eld; |
- | 12044 | dev_priv->display.modeset_global_resources = |
|
- | 12045 | snb_modeset_global_resources; |
|
10623 | } else if (IS_IVYBRIDGE(dev)) { |
12046 | } else if (IS_IVYBRIDGE(dev)) { |
10624 | /* FIXME: detect B0+ stepping and use auto training */ |
12047 | /* FIXME: detect B0+ stepping and use auto training */ |
10625 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
12048 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
10626 | dev_priv->display.write_eld = ironlake_write_eld; |
12049 | dev_priv->display.write_eld = ironlake_write_eld; |
10627 | dev_priv->display.modeset_global_resources = |
12050 | dev_priv->display.modeset_global_resources = |
10628 | ivb_modeset_global_resources; |
12051 | ivb_modeset_global_resources; |
10629 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
12052 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
10630 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
12053 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
10631 | dev_priv->display.write_eld = haswell_write_eld; |
12054 | dev_priv->display.write_eld = haswell_write_eld; |
10632 | dev_priv->display.modeset_global_resources = |
12055 | dev_priv->display.modeset_global_resources = |
10633 | haswell_modeset_global_resources; |
12056 | haswell_modeset_global_resources; |
10634 | } |
12057 | } |
10635 | } else if (IS_G4X(dev)) { |
12058 | } else if (IS_G4X(dev)) { |
10636 | dev_priv->display.write_eld = g4x_write_eld; |
12059 | dev_priv->display.write_eld = g4x_write_eld; |
10637 | } else if (IS_VALLEYVIEW(dev)) { |
12060 | } else if (IS_VALLEYVIEW(dev)) { |
10638 | dev_priv->display.modeset_global_resources = |
12061 | dev_priv->display.modeset_global_resources = |
10639 | valleyview_modeset_global_resources; |
12062 | valleyview_modeset_global_resources; |
10640 | dev_priv->display.write_eld = ironlake_write_eld; |
12063 | dev_priv->display.write_eld = ironlake_write_eld; |
10641 | } |
12064 | } |
10642 | 12065 | ||
10643 | /* Default just returns -ENODEV to indicate unsupported */ |
12066 | /* Default just returns -ENODEV to indicate unsupported */ |
10644 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
12067 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
10645 | 12068 | ||
10646 | 12069 | ||
10647 | 12070 | ||
10648 | 12071 | ||
10649 | intel_panel_init_backlight_funcs(dev); |
12072 | intel_panel_init_backlight_funcs(dev); |
10650 | } |
12073 | } |
10651 | 12074 | ||
10652 | /* |
12075 | /* |
10653 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
12076 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
10654 | * resume, or other times. This quirk makes sure that's the case for |
12077 | * resume, or other times. This quirk makes sure that's the case for |
10655 | * affected systems. |
12078 | * affected systems. |
10656 | */ |
12079 | */ |
10657 | static void quirk_pipea_force(struct drm_device *dev) |
12080 | static void quirk_pipea_force(struct drm_device *dev) |
10658 | { |
12081 | { |
10659 | struct drm_i915_private *dev_priv = dev->dev_private; |
12082 | struct drm_i915_private *dev_priv = dev->dev_private; |
10660 | 12083 | ||
10661 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
12084 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
10662 | DRM_INFO("applying pipe a force quirk\n"); |
12085 | DRM_INFO("applying pipe a force quirk\n"); |
10663 | } |
12086 | } |
10664 | 12087 | ||
10665 | /* |
12088 | /* |
10666 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
12089 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
10667 | */ |
12090 | */ |
10668 | static void quirk_ssc_force_disable(struct drm_device *dev) |
12091 | static void quirk_ssc_force_disable(struct drm_device *dev) |
10669 | { |
12092 | { |
10670 | struct drm_i915_private *dev_priv = dev->dev_private; |
12093 | struct drm_i915_private *dev_priv = dev->dev_private; |
10671 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
12094 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
10672 | DRM_INFO("applying lvds SSC disable quirk\n"); |
12095 | DRM_INFO("applying lvds SSC disable quirk\n"); |
10673 | } |
12096 | } |
10674 | 12097 | ||
10675 | /* |
12098 | /* |
10676 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12099 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10677 | * brightness value |
12100 | * brightness value |
10678 | */ |
12101 | */ |
10679 | static void quirk_invert_brightness(struct drm_device *dev) |
12102 | static void quirk_invert_brightness(struct drm_device *dev) |
10680 | { |
12103 | { |
10681 | struct drm_i915_private *dev_priv = dev->dev_private; |
12104 | struct drm_i915_private *dev_priv = dev->dev_private; |
10682 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
12105 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
10683 | DRM_INFO("applying inverted panel brightness quirk\n"); |
12106 | DRM_INFO("applying inverted panel brightness quirk\n"); |
10684 | } |
12107 | } |
- | 12108 | ||
- | 12109 | /* Some VBT's incorrectly indicate no backlight is present */ |
|
- | 12110 | static void quirk_backlight_present(struct drm_device *dev) |
|
- | 12111 | { |
|
- | 12112 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 12113 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
|
- | 12114 | DRM_INFO("applying backlight present quirk\n"); |
|
- | 12115 | } |
|
10685 | 12116 | ||
10686 | struct intel_quirk { |
12117 | struct intel_quirk { |
10687 | int device; |
12118 | int device; |
10688 | int subsystem_vendor; |
12119 | int subsystem_vendor; |
10689 | int subsystem_device; |
12120 | int subsystem_device; |
10690 | void (*hook)(struct drm_device *dev); |
12121 | void (*hook)(struct drm_device *dev); |
10691 | }; |
12122 | }; |
10692 | 12123 | ||
10693 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12124 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10694 | struct intel_dmi_quirk { |
12125 | struct intel_dmi_quirk { |
10695 | void (*hook)(struct drm_device *dev); |
12126 | void (*hook)(struct drm_device *dev); |
10696 | const struct dmi_system_id (*dmi_id_list)[]; |
12127 | const struct dmi_system_id (*dmi_id_list)[]; |
10697 | }; |
12128 | }; |
10698 | 12129 | ||
10699 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
12130 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
10700 | { |
12131 | { |
10701 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
12132 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
10702 | return 1; |
12133 | return 1; |
10703 | } |
12134 | } |
10704 | 12135 | ||
10705 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
12136 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
10706 | { |
12137 | { |
10707 | .dmi_id_list = &(const struct dmi_system_id[]) { |
12138 | .dmi_id_list = &(const struct dmi_system_id[]) { |
10708 | { |
12139 | { |
10709 | .callback = intel_dmi_reverse_brightness, |
12140 | .callback = intel_dmi_reverse_brightness, |
10710 | .ident = "NCR Corporation", |
12141 | .ident = "NCR Corporation", |
10711 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
12142 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
10712 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
12143 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
10713 | }, |
12144 | }, |
10714 | }, |
12145 | }, |
10715 | { } /* terminating entry */ |
12146 | { } /* terminating entry */ |
10716 | }, |
12147 | }, |
10717 | .hook = quirk_invert_brightness, |
12148 | .hook = quirk_invert_brightness, |
10718 | }, |
12149 | }, |
10719 | }; |
12150 | }; |
10720 | 12151 | ||
10721 | static struct intel_quirk intel_quirks[] = { |
12152 | static struct intel_quirk intel_quirks[] = { |
10722 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
12153 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
10723 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
12154 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
10724 | 12155 | ||
10725 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12156 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10726 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
12157 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
10727 | 12158 | ||
10728 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12159 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10729 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
12160 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
10730 | - | ||
10731 | /* 830 needs to leave pipe A & dpll A up */ |
- | |
10732 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
- | |
10733 | 12161 | ||
10734 | /* Lenovo U160 cannot use SSC on LVDS */ |
12162 | /* Lenovo U160 cannot use SSC on LVDS */ |
10735 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
12163 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
10736 | 12164 | ||
10737 | /* Sony Vaio Y cannot use SSC on LVDS */ |
12165 | /* Sony Vaio Y cannot use SSC on LVDS */ |
10738 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
12166 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
10739 | 12167 | ||
10740 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12168 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10741 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
12169 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
10742 | 12170 | ||
10743 | /* Acer/eMachines G725 */ |
12171 | /* Acer/eMachines G725 */ |
10744 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
12172 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
10745 | 12173 | ||
10746 | /* Acer/eMachines e725 */ |
12174 | /* Acer/eMachines e725 */ |
10747 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
12175 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
10748 | 12176 | ||
10749 | /* Acer/Packard Bell NCL20 */ |
12177 | /* Acer/Packard Bell NCL20 */ |
10750 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
12178 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
10751 | 12179 | ||
10752 | /* Acer Aspire 4736Z */ |
12180 | /* Acer Aspire 4736Z */ |
10753 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
12181 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
- | 12182 | ||
- | 12183 | /* Acer Aspire 5336 */ |
|
- | 12184 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
|
- | 12185 | ||
- | 12186 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
|
- | 12187 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
|
- | 12188 | ||
- | 12189 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
|
- | 12190 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
|
- | 12191 | ||
- | 12192 | /* HP Chromebook 14 (Celeron 2955U) */ |
|
- | 12193 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
|
10754 | }; |
12194 | }; |
10755 | 12195 | ||
10756 | static void intel_init_quirks(struct drm_device *dev) |
12196 | static void intel_init_quirks(struct drm_device *dev) |
10757 | { |
12197 | { |
10758 | struct pci_dev *d = dev->pdev; |
12198 | struct pci_dev *d = dev->pdev; |
10759 | int i; |
12199 | int i; |
10760 | 12200 | ||
10761 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
12201 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
10762 | struct intel_quirk *q = &intel_quirks[i]; |
12202 | struct intel_quirk *q = &intel_quirks[i]; |
10763 | 12203 | ||
10764 | if (d->device == q->device && |
12204 | if (d->device == q->device && |
10765 | (d->subsystem_vendor == q->subsystem_vendor || |
12205 | (d->subsystem_vendor == q->subsystem_vendor || |
10766 | q->subsystem_vendor == PCI_ANY_ID) && |
12206 | q->subsystem_vendor == PCI_ANY_ID) && |
10767 | (d->subsystem_device == q->subsystem_device || |
12207 | (d->subsystem_device == q->subsystem_device || |
10768 | q->subsystem_device == PCI_ANY_ID)) |
12208 | q->subsystem_device == PCI_ANY_ID)) |
10769 | q->hook(dev); |
12209 | q->hook(dev); |
10770 | } |
12210 | } |
10771 | } |
12211 | } |
10772 | 12212 | ||
10773 | /* Disable the VGA plane that we never use */ |
12213 | /* Disable the VGA plane that we never use */ |
10774 | static void i915_disable_vga(struct drm_device *dev) |
12214 | static void i915_disable_vga(struct drm_device *dev) |
10775 | { |
12215 | { |
10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
12216 | struct drm_i915_private *dev_priv = dev->dev_private; |
10777 | u8 sr1; |
12217 | u8 sr1; |
10778 | u32 vga_reg = i915_vgacntrl_reg(dev); |
12218 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10779 | 12219 | ||
10780 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
12220 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10781 | outb(SR01, VGA_SR_INDEX); |
12221 | outb(SR01, VGA_SR_INDEX); |
10782 | sr1 = inb(VGA_SR_DATA); |
12222 | sr1 = inb(VGA_SR_DATA); |
10783 | outb(sr1 | 1<<5, VGA_SR_DATA); |
12223 | outb(sr1 | 1<<5, VGA_SR_DATA); |
10784 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
12224 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
10785 | udelay(300); |
12225 | udelay(300); |
10786 | 12226 | ||
10787 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
12227 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10788 | POSTING_READ(vga_reg); |
12228 | POSTING_READ(vga_reg); |
10789 | } |
12229 | } |
10790 | 12230 | ||
10791 | void intel_modeset_init_hw(struct drm_device *dev) |
12231 | void intel_modeset_init_hw(struct drm_device *dev) |
10792 | { |
12232 | { |
10793 | intel_prepare_ddi(dev); |
12233 | intel_prepare_ddi(dev); |
- | 12234 | ||
- | 12235 | if (IS_VALLEYVIEW(dev)) |
|
- | 12236 | vlv_update_cdclk(dev); |
|
10794 | 12237 | ||
10795 | intel_init_clock_gating(dev); |
12238 | intel_init_clock_gating(dev); |
10796 | 12239 | ||
10797 | intel_reset_dpio(dev); |
12240 | intel_reset_dpio(dev); |
10798 | - | ||
10799 | mutex_lock(&dev->struct_mutex); |
12241 | |
10800 | intel_enable_gt_powersave(dev); |
- | |
10801 | mutex_unlock(&dev->struct_mutex); |
12242 | intel_enable_gt_powersave(dev); |
10802 | } |
12243 | } |
10803 | 12244 | ||
10804 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12245 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10805 | { |
12246 | { |
10806 | intel_suspend_hw(dev); |
12247 | intel_suspend_hw(dev); |
10807 | } |
12248 | } |
10808 | 12249 | ||
10809 | void intel_modeset_init(struct drm_device *dev) |
12250 | void intel_modeset_init(struct drm_device *dev) |
10810 | { |
12251 | { |
10811 | struct drm_i915_private *dev_priv = dev->dev_private; |
12252 | struct drm_i915_private *dev_priv = dev->dev_private; |
10812 | int i, j, ret; |
12253 | int sprite, ret; |
- | 12254 | enum pipe pipe; |
|
- | 12255 | struct intel_crtc *crtc; |
|
10813 | 12256 | ||
10814 | drm_mode_config_init(dev); |
12257 | drm_mode_config_init(dev); |
10815 | 12258 | ||
10816 | dev->mode_config.min_width = 0; |
12259 | dev->mode_config.min_width = 0; |
10817 | dev->mode_config.min_height = 0; |
12260 | dev->mode_config.min_height = 0; |
10818 | 12261 | ||
10819 | dev->mode_config.preferred_depth = 24; |
12262 | dev->mode_config.preferred_depth = 24; |
10820 | dev->mode_config.prefer_shadow = 1; |
12263 | dev->mode_config.prefer_shadow = 1; |
10821 | 12264 | ||
10822 | dev->mode_config.funcs = &intel_mode_funcs; |
12265 | dev->mode_config.funcs = &intel_mode_funcs; |
10823 | 12266 | ||
10824 | intel_init_quirks(dev); |
12267 | intel_init_quirks(dev); |
10825 | 12268 | ||
10826 | intel_init_pm(dev); |
12269 | intel_init_pm(dev); |
10827 | 12270 | ||
10828 | if (INTEL_INFO(dev)->num_pipes == 0) |
12271 | if (INTEL_INFO(dev)->num_pipes == 0) |
10829 | return; |
12272 | return; |
10830 | 12273 | ||
10831 | intel_init_display(dev); |
12274 | intel_init_display(dev); |
10832 | 12275 | ||
10833 | if (IS_GEN2(dev)) { |
12276 | if (IS_GEN2(dev)) { |
10834 | dev->mode_config.max_width = 2048; |
12277 | dev->mode_config.max_width = 2048; |
10835 | dev->mode_config.max_height = 2048; |
12278 | dev->mode_config.max_height = 2048; |
10836 | } else if (IS_GEN3(dev)) { |
12279 | } else if (IS_GEN3(dev)) { |
10837 | dev->mode_config.max_width = 4096; |
12280 | dev->mode_config.max_width = 4096; |
10838 | dev->mode_config.max_height = 4096; |
12281 | dev->mode_config.max_height = 4096; |
10839 | } else { |
12282 | } else { |
10840 | dev->mode_config.max_width = 8192; |
12283 | dev->mode_config.max_width = 8192; |
10841 | dev->mode_config.max_height = 8192; |
12284 | dev->mode_config.max_height = 8192; |
10842 | } |
12285 | } |
- | 12286 | ||
- | 12287 | if (IS_GEN2(dev)) { |
|
- | 12288 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
|
- | 12289 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
|
- | 12290 | } else { |
|
- | 12291 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
|
- | 12292 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
|
- | 12293 | } |
|
- | 12294 | ||
10843 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
12295 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
10844 | 12296 | ||
10845 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
12297 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10846 | INTEL_INFO(dev)->num_pipes, |
12298 | INTEL_INFO(dev)->num_pipes, |
10847 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
12299 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10848 | 12300 | ||
10849 | for_each_pipe(i) { |
12301 | for_each_pipe(pipe) { |
10850 | intel_crtc_init(dev, i); |
12302 | intel_crtc_init(dev, pipe); |
10851 | for (j = 0; j < dev_priv->num_plane; j++) { |
12303 | for_each_sprite(pipe, sprite) { |
10852 | ret = intel_plane_init(dev, i, j); |
12304 | ret = intel_plane_init(dev, pipe, sprite); |
10853 | if (ret) |
12305 | if (ret) |
10854 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
12306 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10855 | pipe_name(i), sprite_name(i, j), ret); |
12307 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
10856 | } |
12308 | } |
10857 | } |
12309 | } |
10858 | 12310 | ||
10859 | intel_init_dpio(dev); |
12311 | intel_init_dpio(dev); |
10860 | intel_reset_dpio(dev); |
12312 | intel_reset_dpio(dev); |
10861 | - | ||
10862 | intel_cpu_pll_init(dev); |
12313 | |
10863 | intel_shared_dpll_init(dev); |
12314 | intel_shared_dpll_init(dev); |
10864 | 12315 | ||
10865 | /* Just disable it once at startup */ |
12316 | /* Just disable it once at startup */ |
10866 | i915_disable_vga(dev); |
12317 | i915_disable_vga(dev); |
10867 | intel_setup_outputs(dev); |
12318 | intel_setup_outputs(dev); |
10868 | 12319 | ||
10869 | /* Just in case the BIOS is doing something questionable. */ |
12320 | /* Just in case the BIOS is doing something questionable. */ |
10870 | intel_disable_fbc(dev); |
12321 | intel_disable_fbc(dev); |
10871 | } |
- | |
10872 | 12322 | ||
10873 | static void |
12323 | drm_modeset_lock_all(dev); |
- | 12324 | intel_modeset_setup_hw_state(dev, false); |
|
- | 12325 | drm_modeset_unlock_all(dev); |
|
- | 12326 | ||
- | 12327 | for_each_intel_crtc(dev, crtc) { |
|
- | 12328 | if (!crtc->active) |
|
10874 | intel_connector_break_all_links(struct intel_connector *connector) |
12329 | continue; |
- | 12330 | ||
- | 12331 | /* |
|
- | 12332 | * Note that reserving the BIOS fb up front prevents us |
|
- | 12333 | * from stuffing other stolen allocations like the ring |
|
- | 12334 | * on top. This prevents some ugliness at boot time, and |
|
- | 12335 | * can even allow for smooth boot transitions if the BIOS |
|
- | 12336 | * fb is large enough for the active pipe configuration. |
|
10875 | { |
12337 | */ |
10876 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12338 | if (dev_priv->display.get_plane_config) { |
- | 12339 | dev_priv->display.get_plane_config(crtc, |
|
- | 12340 | &crtc->plane_config); |
|
10877 | connector->base.encoder = NULL; |
12341 | /* |
- | 12342 | * If the fb is shared between multiple heads, we'll |
|
- | 12343 | * just get the first one. |
|
10878 | connector->encoder->connectors_active = false; |
12344 | */ |
- | 12345 | intel_find_plane_obj(crtc, &crtc->plane_config); |
|
- | 12346 | } |
|
10879 | connector->encoder->base.crtc = NULL; |
12347 | } |
10880 | } |
12348 | } |
10881 | 12349 | ||
10882 | static void intel_enable_pipe_a(struct drm_device *dev) |
12350 | static void intel_enable_pipe_a(struct drm_device *dev) |
10883 | { |
12351 | { |
10884 | struct intel_connector *connector; |
12352 | struct intel_connector *connector; |
10885 | struct drm_connector *crt = NULL; |
12353 | struct drm_connector *crt = NULL; |
10886 | struct intel_load_detect_pipe load_detect_temp; |
12354 | struct intel_load_detect_pipe load_detect_temp; |
- | 12355 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
|
10887 | 12356 | ||
10888 | /* We can't just switch on the pipe A, we need to set things up with a |
12357 | /* We can't just switch on the pipe A, we need to set things up with a |
10889 | * proper mode and output configuration. As a gross hack, enable pipe A |
12358 | * proper mode and output configuration. As a gross hack, enable pipe A |
10890 | * by enabling the load detect pipe once. */ |
12359 | * by enabling the load detect pipe once. */ |
10891 | list_for_each_entry(connector, |
12360 | list_for_each_entry(connector, |
10892 | &dev->mode_config.connector_list, |
12361 | &dev->mode_config.connector_list, |
10893 | base.head) { |
12362 | base.head) { |
10894 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
12363 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
10895 | crt = &connector->base; |
12364 | crt = &connector->base; |
10896 | break; |
12365 | break; |
10897 | } |
12366 | } |
10898 | } |
12367 | } |
10899 | 12368 | ||
10900 | if (!crt) |
12369 | if (!crt) |
10901 | return; |
12370 | return; |
10902 | 12371 | ||
10903 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
12372 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
10904 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
- | |
10905 | - | ||
10906 | 12373 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
|
10907 | } |
12374 | } |
10908 | 12375 | ||
10909 | static bool |
12376 | static bool |
10910 | intel_check_plane_mapping(struct intel_crtc *crtc) |
12377 | intel_check_plane_mapping(struct intel_crtc *crtc) |
10911 | { |
12378 | { |
10912 | struct drm_device *dev = crtc->base.dev; |
12379 | struct drm_device *dev = crtc->base.dev; |
10913 | struct drm_i915_private *dev_priv = dev->dev_private; |
12380 | struct drm_i915_private *dev_priv = dev->dev_private; |
10914 | u32 reg, val; |
12381 | u32 reg, val; |
10915 | 12382 | ||
10916 | if (INTEL_INFO(dev)->num_pipes == 1) |
12383 | if (INTEL_INFO(dev)->num_pipes == 1) |
10917 | return true; |
12384 | return true; |
10918 | 12385 | ||
10919 | reg = DSPCNTR(!crtc->plane); |
12386 | reg = DSPCNTR(!crtc->plane); |
10920 | val = I915_READ(reg); |
12387 | val = I915_READ(reg); |
10921 | 12388 | ||
10922 | if ((val & DISPLAY_PLANE_ENABLE) && |
12389 | if ((val & DISPLAY_PLANE_ENABLE) && |
10923 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
12390 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
10924 | return false; |
12391 | return false; |
10925 | 12392 | ||
10926 | return true; |
12393 | return true; |
10927 | } |
12394 | } |
10928 | 12395 | ||
10929 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12396 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10930 | { |
12397 | { |
10931 | struct drm_device *dev = crtc->base.dev; |
12398 | struct drm_device *dev = crtc->base.dev; |
10932 | struct drm_i915_private *dev_priv = dev->dev_private; |
12399 | struct drm_i915_private *dev_priv = dev->dev_private; |
10933 | u32 reg; |
12400 | u32 reg; |
10934 | 12401 | ||
10935 | /* Clear any frame start delays used for debugging left by the BIOS */ |
12402 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10936 | reg = PIPECONF(crtc->config.cpu_transcoder); |
12403 | reg = PIPECONF(crtc->config.cpu_transcoder); |
10937 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12404 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
- | 12405 | ||
- | 12406 | /* restore vblank interrupts to correct state */ |
|
- | 12407 | if (crtc->active) |
|
- | 12408 | drm_vblank_on(dev, crtc->pipe); |
|
- | 12409 | else |
|
- | 12410 | drm_vblank_off(dev, crtc->pipe); |
|
10938 | 12411 | ||
10939 | /* We need to sanitize the plane -> pipe mapping first because this will |
12412 | /* We need to sanitize the plane -> pipe mapping first because this will |
10940 | * disable the crtc (and hence change the state) if it is wrong. Note |
12413 | * disable the crtc (and hence change the state) if it is wrong. Note |
10941 | * that gen4+ has a fixed plane -> pipe mapping. */ |
12414 | * that gen4+ has a fixed plane -> pipe mapping. */ |
10942 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
12415 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
10943 | struct intel_connector *connector; |
12416 | struct intel_connector *connector; |
10944 | bool plane; |
12417 | bool plane; |
10945 | 12418 | ||
10946 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12419 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10947 | crtc->base.base.id); |
12420 | crtc->base.base.id); |
10948 | 12421 | ||
10949 | /* Pipe has the wrong plane attached and the plane is active. |
12422 | /* Pipe has the wrong plane attached and the plane is active. |
10950 | * Temporarily change the plane mapping and disable everything |
12423 | * Temporarily change the plane mapping and disable everything |
10951 | * ... */ |
12424 | * ... */ |
10952 | plane = crtc->plane; |
12425 | plane = crtc->plane; |
10953 | crtc->plane = !plane; |
12426 | crtc->plane = !plane; |
- | 12427 | crtc->primary_enabled = true; |
|
10954 | dev_priv->display.crtc_disable(&crtc->base); |
12428 | dev_priv->display.crtc_disable(&crtc->base); |
10955 | crtc->plane = plane; |
12429 | crtc->plane = plane; |
10956 | 12430 | ||
10957 | /* ... and break all links. */ |
12431 | /* ... and break all links. */ |
10958 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
12432 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10959 | base.head) { |
12433 | base.head) { |
10960 | if (connector->encoder->base.crtc != &crtc->base) |
12434 | if (connector->encoder->base.crtc != &crtc->base) |
10961 | continue; |
12435 | continue; |
- | 12436 | ||
- | 12437 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
|
- | 12438 | connector->base.encoder = NULL; |
|
- | 12439 | } |
|
- | 12440 | /* multiple connectors may have the same encoder: |
|
10962 | 12441 | * handle them and break crtc link separately */ |
|
- | 12442 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
|
- | 12443 | base.head) |
|
- | 12444 | if (connector->encoder->base.crtc == &crtc->base) { |
|
- | 12445 | connector->encoder->base.crtc = NULL; |
|
10963 | intel_connector_break_all_links(connector); |
12446 | connector->encoder->connectors_active = false; |
10964 | } |
12447 | } |
10965 | 12448 | ||
10966 | WARN_ON(crtc->active); |
12449 | WARN_ON(crtc->active); |
10967 | crtc->base.enabled = false; |
12450 | crtc->base.enabled = false; |
10968 | } |
12451 | } |
10969 | 12452 | ||
10970 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12453 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10971 | crtc->pipe == PIPE_A && !crtc->active) { |
12454 | crtc->pipe == PIPE_A && !crtc->active) { |
10972 | /* BIOS forgot to enable pipe A, this mostly happens after |
12455 | /* BIOS forgot to enable pipe A, this mostly happens after |
10973 | * resume. Force-enable the pipe to fix this, the update_dpms |
12456 | * resume. Force-enable the pipe to fix this, the update_dpms |
10974 | * call below we restore the pipe to the right state, but leave |
12457 | * call below we restore the pipe to the right state, but leave |
10975 | * the required bits on. */ |
12458 | * the required bits on. */ |
10976 | intel_enable_pipe_a(dev); |
12459 | intel_enable_pipe_a(dev); |
10977 | } |
12460 | } |
10978 | 12461 | ||
10979 | /* Adjust the state of the output pipe according to whether we |
12462 | /* Adjust the state of the output pipe according to whether we |
10980 | * have active connectors/encoders. */ |
12463 | * have active connectors/encoders. */ |
10981 | intel_crtc_update_dpms(&crtc->base); |
12464 | intel_crtc_update_dpms(&crtc->base); |
10982 | 12465 | ||
10983 | if (crtc->active != crtc->base.enabled) { |
12466 | if (crtc->active != crtc->base.enabled) { |
10984 | struct intel_encoder *encoder; |
12467 | struct intel_encoder *encoder; |
10985 | 12468 | ||
10986 | /* This can happen either due to bugs in the get_hw_state |
12469 | /* This can happen either due to bugs in the get_hw_state |
10987 | * functions or because the pipe is force-enabled due to the |
12470 | * functions or because the pipe is force-enabled due to the |
10988 | * pipe A quirk. */ |
12471 | * pipe A quirk. */ |
10989 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
12472 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
10990 | crtc->base.base.id, |
12473 | crtc->base.base.id, |
10991 | crtc->base.enabled ? "enabled" : "disabled", |
12474 | crtc->base.enabled ? "enabled" : "disabled", |
10992 | crtc->active ? "enabled" : "disabled"); |
12475 | crtc->active ? "enabled" : "disabled"); |
10993 | 12476 | ||
10994 | crtc->base.enabled = crtc->active; |
12477 | crtc->base.enabled = crtc->active; |
10995 | 12478 | ||
10996 | /* Because we only establish the connector -> encoder -> |
12479 | /* Because we only establish the connector -> encoder -> |
10997 | * crtc links if something is active, this means the |
12480 | * crtc links if something is active, this means the |
10998 | * crtc is now deactivated. Break the links. connector |
12481 | * crtc is now deactivated. Break the links. connector |
10999 | * -> encoder links are only establish when things are |
12482 | * -> encoder links are only establish when things are |
11000 | * actually up, hence no need to break them. */ |
12483 | * actually up, hence no need to break them. */ |
11001 | WARN_ON(crtc->active); |
12484 | WARN_ON(crtc->active); |
11002 | 12485 | ||
11003 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
12486 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
11004 | WARN_ON(encoder->connectors_active); |
12487 | WARN_ON(encoder->connectors_active); |
11005 | encoder->base.crtc = NULL; |
12488 | encoder->base.crtc = NULL; |
11006 | } |
12489 | } |
11007 | } |
12490 | } |
- | 12491 | ||
- | 12492 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { |
|
- | 12493 | /* |
|
- | 12494 | * We start out with underrun reporting disabled to avoid races. |
|
- | 12495 | * For correct bookkeeping mark this on active crtcs. |
|
- | 12496 | * |
|
- | 12497 | * Also on gmch platforms we dont have any hardware bits to |
|
- | 12498 | * disable the underrun reporting. Which means we need to start |
|
- | 12499 | * out with underrun reporting disabled also on inactive pipes, |
|
- | 12500 | * since otherwise we'll complain about the garbage we read when |
|
- | 12501 | * e.g. coming up after runtime pm. |
|
- | 12502 | * |
|
- | 12503 | * No protection against concurrent access is required - at |
|
- | 12504 | * worst a fifo underrun happens which also sets this to false. |
|
- | 12505 | */ |
|
- | 12506 | crtc->cpu_fifo_underrun_disabled = true; |
|
- | 12507 | crtc->pch_fifo_underrun_disabled = true; |
|
- | 12508 | ||
- | 12509 | update_scanline_offset(crtc); |
|
- | 12510 | } |
|
11008 | } |
12511 | } |
11009 | 12512 | ||
11010 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
12513 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
11011 | { |
12514 | { |
11012 | struct intel_connector *connector; |
12515 | struct intel_connector *connector; |
11013 | struct drm_device *dev = encoder->base.dev; |
12516 | struct drm_device *dev = encoder->base.dev; |
11014 | 12517 | ||
11015 | /* We need to check both for a crtc link (meaning that the |
12518 | /* We need to check both for a crtc link (meaning that the |
11016 | * encoder is active and trying to read from a pipe) and the |
12519 | * encoder is active and trying to read from a pipe) and the |
11017 | * pipe itself being active. */ |
12520 | * pipe itself being active. */ |
11018 | bool has_active_crtc = encoder->base.crtc && |
12521 | bool has_active_crtc = encoder->base.crtc && |
11019 | to_intel_crtc(encoder->base.crtc)->active; |
12522 | to_intel_crtc(encoder->base.crtc)->active; |
11020 | 12523 | ||
11021 | if (encoder->connectors_active && !has_active_crtc) { |
12524 | if (encoder->connectors_active && !has_active_crtc) { |
11022 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
12525 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
11023 | encoder->base.base.id, |
12526 | encoder->base.base.id, |
11024 | drm_get_encoder_name(&encoder->base)); |
12527 | encoder->base.name); |
11025 | 12528 | ||
11026 | /* Connector is active, but has no active pipe. This is |
12529 | /* Connector is active, but has no active pipe. This is |
11027 | * fallout from our resume register restoring. Disable |
12530 | * fallout from our resume register restoring. Disable |
11028 | * the encoder manually again. */ |
12531 | * the encoder manually again. */ |
11029 | if (encoder->base.crtc) { |
12532 | if (encoder->base.crtc) { |
11030 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
12533 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
11031 | encoder->base.base.id, |
12534 | encoder->base.base.id, |
11032 | drm_get_encoder_name(&encoder->base)); |
12535 | encoder->base.name); |
11033 | encoder->disable(encoder); |
12536 | encoder->disable(encoder); |
- | 12537 | if (encoder->post_disable) |
|
- | 12538 | encoder->post_disable(encoder); |
|
11034 | } |
12539 | } |
- | 12540 | encoder->base.crtc = NULL; |
|
- | 12541 | encoder->connectors_active = false; |
|
11035 | 12542 | ||
11036 | /* Inconsistent output/port/pipe state happens presumably due to |
12543 | /* Inconsistent output/port/pipe state happens presumably due to |
11037 | * a bug in one of the get_hw_state functions. Or someplace else |
12544 | * a bug in one of the get_hw_state functions. Or someplace else |
11038 | * in our code, like the register restore mess on resume. Clamp |
12545 | * in our code, like the register restore mess on resume. Clamp |
11039 | * things to off as a safer default. */ |
12546 | * things to off as a safer default. */ |
11040 | list_for_each_entry(connector, |
12547 | list_for_each_entry(connector, |
11041 | &dev->mode_config.connector_list, |
12548 | &dev->mode_config.connector_list, |
11042 | base.head) { |
12549 | base.head) { |
11043 | if (connector->encoder != encoder) |
12550 | if (connector->encoder != encoder) |
11044 | continue; |
12551 | continue; |
11045 | - | ||
- | 12552 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
|
11046 | intel_connector_break_all_links(connector); |
12553 | connector->base.encoder = NULL; |
11047 | } |
12554 | } |
11048 | } |
12555 | } |
11049 | /* Enabled encoders without active connectors will be fixed in |
12556 | /* Enabled encoders without active connectors will be fixed in |
11050 | * the crtc fixup. */ |
12557 | * the crtc fixup. */ |
11051 | } |
12558 | } |
11052 | 12559 | ||
11053 | void i915_redisable_vga(struct drm_device *dev) |
12560 | void i915_redisable_vga_power_on(struct drm_device *dev) |
11054 | { |
12561 | { |
11055 | struct drm_i915_private *dev_priv = dev->dev_private; |
12562 | struct drm_i915_private *dev_priv = dev->dev_private; |
11056 | u32 vga_reg = i915_vgacntrl_reg(dev); |
12563 | u32 vga_reg = i915_vgacntrl_reg(dev); |
- | 12564 | ||
- | 12565 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
|
- | 12566 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
|
- | 12567 | i915_disable_vga(dev); |
|
- | 12568 | } |
|
- | 12569 | } |
|
- | 12570 | ||
- | 12571 | void i915_redisable_vga(struct drm_device *dev) |
|
- | 12572 | { |
|
- | 12573 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
11057 | 12574 | ||
11058 | /* This function can be called both from intel_modeset_setup_hw_state or |
12575 | /* This function can be called both from intel_modeset_setup_hw_state or |
11059 | * at a very early point in our resume sequence, where the power well |
12576 | * at a very early point in our resume sequence, where the power well |
11060 | * structures are not yet restored. Since this function is at a very |
12577 | * structures are not yet restored. Since this function is at a very |
11061 | * paranoid "someone might have enabled VGA while we were not looking" |
12578 | * paranoid "someone might have enabled VGA while we were not looking" |
11062 | * level, just check if the power well is enabled instead of trying to |
12579 | * level, just check if the power well is enabled instead of trying to |
11063 | * follow the "don't touch the power well if we don't need it" policy |
12580 | * follow the "don't touch the power well if we don't need it" policy |
11064 | * the rest of the driver uses. */ |
12581 | * the rest of the driver uses. */ |
11065 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
- | |
11066 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
12582 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
11067 | return; |
12583 | return; |
11068 | - | ||
11069 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
- | |
11070 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
12584 | |
11071 | i915_disable_vga(dev); |
12585 | i915_redisable_vga_power_on(dev); |
- | 12586 | } |
|
- | 12587 | ||
- | 12588 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
|
- | 12589 | { |
|
- | 12590 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
- | 12591 | ||
- | 12592 | if (!crtc->active) |
|
- | 12593 | return false; |
|
- | 12594 | ||
11072 | } |
12595 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; |
11073 | } |
12596 | } |
11074 | 12597 | ||
11075 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
12598 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
11076 | { |
12599 | { |
11077 | struct drm_i915_private *dev_priv = dev->dev_private; |
12600 | struct drm_i915_private *dev_priv = dev->dev_private; |
11078 | enum pipe pipe; |
12601 | enum pipe pipe; |
11079 | struct intel_crtc *crtc; |
12602 | struct intel_crtc *crtc; |
11080 | struct intel_encoder *encoder; |
12603 | struct intel_encoder *encoder; |
11081 | struct intel_connector *connector; |
12604 | struct intel_connector *connector; |
11082 | int i; |
12605 | int i; |
11083 | 12606 | ||
11084 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
11085 | base.head) { |
12607 | for_each_intel_crtc(dev, crtc) { |
- | 12608 | memset(&crtc->config, 0, sizeof(crtc->config)); |
|
- | 12609 | ||
11086 | memset(&crtc->config, 0, sizeof(crtc->config)); |
12610 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
11087 | 12611 | ||
11088 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12612 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11089 | &crtc->config); |
12613 | &crtc->config); |
11090 | 12614 | ||
11091 | crtc->base.enabled = crtc->active; |
12615 | crtc->base.enabled = crtc->active; |
11092 | crtc->primary_enabled = crtc->active; |
12616 | crtc->primary_enabled = primary_get_hw_state(crtc); |
11093 | 12617 | ||
11094 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
12618 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
11095 | crtc->base.base.id, |
12619 | crtc->base.base.id, |
11096 | crtc->active ? "enabled" : "disabled"); |
12620 | crtc->active ? "enabled" : "disabled"); |
11097 | } |
12621 | } |
11098 | - | ||
11099 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
- | |
11100 | if (HAS_DDI(dev)) |
- | |
11101 | intel_ddi_setup_hw_pll_state(dev); |
- | |
11102 | 12622 | ||
11103 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12623 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11104 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
12624 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
11105 | 12625 | ||
11106 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
12626 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
11107 | pll->active = 0; |
12627 | pll->active = 0; |
11108 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
12628 | for_each_intel_crtc(dev, crtc) { |
11109 | base.head) { |
- | |
11110 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12629 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
11111 | pll->active++; |
12630 | pll->active++; |
11112 | } |
12631 | } |
11113 | pll->refcount = pll->active; |
12632 | pll->refcount = pll->active; |
11114 | 12633 | ||
11115 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12634 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11116 | pll->name, pll->refcount, pll->on); |
12635 | pll->name, pll->refcount, pll->on); |
- | 12636 | ||
- | 12637 | if (pll->refcount) |
|
- | 12638 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
|
11117 | } |
12639 | } |
11118 | 12640 | ||
11119 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12641 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11120 | base.head) { |
12642 | base.head) { |
11121 | pipe = 0; |
12643 | pipe = 0; |
11122 | 12644 | ||
11123 | if (encoder->get_hw_state(encoder, &pipe)) { |
12645 | if (encoder->get_hw_state(encoder, &pipe)) { |
11124 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12646 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11125 | encoder->base.crtc = &crtc->base; |
12647 | encoder->base.crtc = &crtc->base; |
11126 | encoder->get_config(encoder, &crtc->config); |
12648 | encoder->get_config(encoder, &crtc->config); |
11127 | } else { |
12649 | } else { |
11128 | encoder->base.crtc = NULL; |
12650 | encoder->base.crtc = NULL; |
11129 | } |
12651 | } |
11130 | 12652 | ||
11131 | encoder->connectors_active = false; |
12653 | encoder->connectors_active = false; |
11132 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
12654 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
11133 | encoder->base.base.id, |
12655 | encoder->base.base.id, |
11134 | drm_get_encoder_name(&encoder->base), |
12656 | encoder->base.name, |
11135 | encoder->base.crtc ? "enabled" : "disabled", |
12657 | encoder->base.crtc ? "enabled" : "disabled", |
11136 | pipe_name(pipe)); |
12658 | pipe_name(pipe)); |
11137 | } |
12659 | } |
11138 | 12660 | ||
11139 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
12661 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11140 | base.head) { |
12662 | base.head) { |
11141 | if (connector->get_hw_state(connector)) { |
12663 | if (connector->get_hw_state(connector)) { |
11142 | connector->base.dpms = DRM_MODE_DPMS_ON; |
12664 | connector->base.dpms = DRM_MODE_DPMS_ON; |
11143 | connector->encoder->connectors_active = true; |
12665 | connector->encoder->connectors_active = true; |
11144 | connector->base.encoder = &connector->encoder->base; |
12666 | connector->base.encoder = &connector->encoder->base; |
11145 | } else { |
12667 | } else { |
11146 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12668 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11147 | connector->base.encoder = NULL; |
12669 | connector->base.encoder = NULL; |
11148 | } |
12670 | } |
11149 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
12671 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
11150 | connector->base.base.id, |
12672 | connector->base.base.id, |
11151 | drm_get_connector_name(&connector->base), |
12673 | connector->base.name, |
11152 | connector->base.encoder ? "enabled" : "disabled"); |
12674 | connector->base.encoder ? "enabled" : "disabled"); |
11153 | } |
12675 | } |
11154 | } |
12676 | } |
11155 | 12677 | ||
11156 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
12678 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
11157 | * and i915 state tracking structures. */ |
12679 | * and i915 state tracking structures. */ |
11158 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
12680 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
11159 | bool force_restore) |
12681 | bool force_restore) |
11160 | { |
12682 | { |
11161 | struct drm_i915_private *dev_priv = dev->dev_private; |
12683 | struct drm_i915_private *dev_priv = dev->dev_private; |
11162 | enum pipe pipe; |
12684 | enum pipe pipe; |
11163 | struct intel_crtc *crtc; |
12685 | struct intel_crtc *crtc; |
11164 | struct intel_encoder *encoder; |
12686 | struct intel_encoder *encoder; |
11165 | int i; |
12687 | int i; |
11166 | 12688 | ||
11167 | intel_modeset_readout_hw_state(dev); |
12689 | intel_modeset_readout_hw_state(dev); |
11168 | 12690 | ||
11169 | /* |
12691 | /* |
11170 | * Now that we have the config, copy it to each CRTC struct |
12692 | * Now that we have the config, copy it to each CRTC struct |
11171 | * Note that this could go away if we move to using crtc_config |
12693 | * Note that this could go away if we move to using crtc_config |
11172 | * checking everywhere. |
12694 | * checking everywhere. |
11173 | */ |
12695 | */ |
11174 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
12696 | for_each_intel_crtc(dev, crtc) { |
11175 | base.head) { |
- | |
11176 | if (crtc->active && i915_fastboot) { |
12697 | if (crtc->active && i915.fastboot) { |
11177 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
12698 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
11178 | - | ||
11179 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12699 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
11180 | crtc->base.base.id); |
12700 | crtc->base.base.id); |
11181 | drm_mode_debug_printmodeline(&crtc->base.mode); |
12701 | drm_mode_debug_printmodeline(&crtc->base.mode); |
11182 | } |
12702 | } |
11183 | } |
12703 | } |
11184 | 12704 | ||
11185 | /* HW state is read out, now we need to sanitize this mess. */ |
12705 | /* HW state is read out, now we need to sanitize this mess. */ |
11186 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12706 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11187 | base.head) { |
12707 | base.head) { |
11188 | intel_sanitize_encoder(encoder); |
12708 | intel_sanitize_encoder(encoder); |
11189 | } |
12709 | } |
11190 | 12710 | ||
11191 | for_each_pipe(pipe) { |
12711 | for_each_pipe(pipe) { |
11192 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12712 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11193 | intel_sanitize_crtc(crtc); |
12713 | intel_sanitize_crtc(crtc); |
11194 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
12714 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
11195 | } |
12715 | } |
11196 | 12716 | ||
11197 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12717 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11198 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
12718 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
11199 | 12719 | ||
11200 | if (!pll->on || pll->active) |
12720 | if (!pll->on || pll->active) |
11201 | continue; |
12721 | continue; |
11202 | 12722 | ||
11203 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
12723 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
11204 | 12724 | ||
11205 | pll->disable(dev_priv, pll); |
12725 | pll->disable(dev_priv, pll); |
11206 | pll->on = false; |
12726 | pll->on = false; |
11207 | } |
12727 | } |
11208 | 12728 | ||
11209 | if (HAS_PCH_SPLIT(dev)) |
12729 | if (HAS_PCH_SPLIT(dev)) |
11210 | ilk_wm_get_hw_state(dev); |
12730 | ilk_wm_get_hw_state(dev); |
11211 | 12731 | ||
11212 | if (force_restore) { |
12732 | if (force_restore) { |
11213 | i915_redisable_vga(dev); |
12733 | i915_redisable_vga(dev); |
11214 | 12734 | ||
11215 | /* |
12735 | /* |
11216 | * We need to use raw interfaces for restoring state to avoid |
12736 | * We need to use raw interfaces for restoring state to avoid |
11217 | * checking (bogus) intermediate states. |
12737 | * checking (bogus) intermediate states. |
11218 | */ |
12738 | */ |
11219 | for_each_pipe(pipe) { |
12739 | for_each_pipe(pipe) { |
11220 | struct drm_crtc *crtc = |
12740 | struct drm_crtc *crtc = |
11221 | dev_priv->pipe_to_crtc_mapping[pipe]; |
12741 | dev_priv->pipe_to_crtc_mapping[pipe]; |
11222 | 12742 | ||
11223 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
12743 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
11224 | crtc->fb); |
12744 | crtc->primary->fb); |
11225 | } |
12745 | } |
11226 | } else { |
12746 | } else { |
11227 | intel_modeset_update_staged_output_state(dev); |
12747 | intel_modeset_update_staged_output_state(dev); |
11228 | } |
12748 | } |
11229 | 12749 | ||
11230 | intel_modeset_check_state(dev); |
12750 | intel_modeset_check_state(dev); |
11231 | } |
12751 | } |
11232 | 12752 | ||
11233 | void intel_modeset_gem_init(struct drm_device *dev) |
12753 | void intel_modeset_gem_init(struct drm_device *dev) |
11234 | { |
12754 | { |
- | 12755 | struct drm_crtc *c; |
|
- | 12756 | struct drm_i915_gem_object *obj; |
|
- | 12757 | ||
- | 12758 | mutex_lock(&dev->struct_mutex); |
|
- | 12759 | intel_init_gt_powersave(dev); |
|
- | 12760 | mutex_unlock(&dev->struct_mutex); |
|
- | 12761 | ||
11235 | intel_modeset_init_hw(dev); |
12762 | intel_modeset_init_hw(dev); |
11236 | 12763 | ||
11237 | // intel_setup_overlay(dev); |
12764 | // intel_setup_overlay(dev); |
- | 12765 | ||
- | 12766 | /* |
|
- | 12767 | * Make sure any fbs we allocated at startup are properly |
|
- | 12768 | * pinned & fenced. When we do the allocation it's too early |
|
- | 12769 | * for this. |
|
11238 | 12770 | */ |
|
11239 | mutex_lock(&dev->mode_config.mutex); |
12771 | mutex_lock(&dev->struct_mutex); |
- | 12772 | for_each_crtc(dev, c) { |
|
- | 12773 | obj = intel_fb_obj(c->primary->fb); |
|
- | 12774 | if (obj == NULL) |
|
- | 12775 | continue; |
|
11240 | drm_mode_config_reset(dev); |
12776 | |
- | 12777 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
|
- | 12778 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
|
- | 12779 | to_intel_crtc(c)->pipe); |
|
- | 12780 | drm_framebuffer_unreference(c->primary->fb); |
|
- | 12781 | c->primary->fb = NULL; |
|
- | 12782 | } |
|
11241 | intel_modeset_setup_hw_state(dev, false); |
12783 | } |
- | 12784 | mutex_unlock(&dev->struct_mutex); |
|
- | 12785 | } |
|
- | 12786 | ||
- | 12787 | void intel_connector_unregister(struct intel_connector *intel_connector) |
|
- | 12788 | { |
|
- | 12789 | struct drm_connector *connector = &intel_connector->base; |
|
- | 12790 | ||
- | 12791 | intel_panel_destroy_backlight(connector); |
|
11242 | mutex_unlock(&dev->mode_config.mutex); |
12792 | drm_connector_unregister(connector); |
11243 | } |
12793 | } |
11244 | 12794 | ||
11245 | void intel_modeset_cleanup(struct drm_device *dev) |
12795 | void intel_modeset_cleanup(struct drm_device *dev) |
11246 | { |
12796 | { |
11247 | #if 0 |
12797 | #if 0 |
11248 | struct drm_i915_private *dev_priv = dev->dev_private; |
12798 | struct drm_i915_private *dev_priv = dev->dev_private; |
11249 | struct drm_crtc *crtc; |
- | |
11250 | struct drm_connector *connector; |
12799 | struct drm_connector *connector; |
11251 | 12800 | ||
11252 | /* |
12801 | /* |
11253 | * Interrupts and polling as the first thing to avoid creating havoc. |
12802 | * Interrupts and polling as the first thing to avoid creating havoc. |
11254 | * Too much stuff here (turning of rps, connectors, ...) would |
12803 | * Too much stuff here (turning of rps, connectors, ...) would |
11255 | * experience fancy races otherwise. |
12804 | * experience fancy races otherwise. |
11256 | */ |
12805 | */ |
11257 | drm_irq_uninstall(dev); |
12806 | drm_irq_uninstall(dev); |
11258 | cancel_work_sync(&dev_priv->hotplug_work); |
12807 | intel_hpd_cancel_work(dev_priv); |
- | 12808 | dev_priv->pm._irqs_disabled = true; |
|
- | 12809 | ||
11259 | /* |
12810 | /* |
11260 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
12811 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
11261 | * poll handlers. Hence disable polling after hpd handling is shut down. |
12812 | * poll handlers. Hence disable polling after hpd handling is shut down. |
11262 | */ |
12813 | */ |
11263 | drm_kms_helper_poll_fini(dev); |
12814 | drm_kms_helper_poll_fini(dev); |
11264 | 12815 | ||
11265 | mutex_lock(&dev->struct_mutex); |
12816 | mutex_lock(&dev->struct_mutex); |
11266 | 12817 | ||
11267 | intel_unregister_dsm_handler(); |
12818 | intel_unregister_dsm_handler(); |
11268 | - | ||
11269 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
- | |
11270 | /* Skip inactive CRTCs */ |
- | |
11271 | if (!crtc->fb) |
- | |
11272 | continue; |
- | |
11273 | - | ||
11274 | intel_increase_pllclock(crtc); |
- | |
11275 | } |
- | |
11276 | 12819 | ||
11277 | intel_disable_fbc(dev); |
12820 | intel_disable_fbc(dev); |
11278 | 12821 | ||
11279 | intel_disable_gt_powersave(dev); |
12822 | intel_disable_gt_powersave(dev); |
11280 | 12823 | ||
11281 | ironlake_teardown_rc6(dev); |
12824 | ironlake_teardown_rc6(dev); |
11282 | 12825 | ||
11283 | mutex_unlock(&dev->struct_mutex); |
12826 | mutex_unlock(&dev->struct_mutex); |
11284 | 12827 | ||
11285 | /* flush any delayed tasks or pending work */ |
12828 | /* flush any delayed tasks or pending work */ |
11286 | flush_scheduled_work(); |
12829 | flush_scheduled_work(); |
11287 | 12830 | ||
11288 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12831 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11289 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
12832 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
- | 12833 | struct intel_connector *intel_connector; |
|
- | 12834 | ||
11290 | intel_panel_destroy_backlight(connector); |
12835 | intel_connector = to_intel_connector(connector); |
11291 | drm_sysfs_connector_remove(connector); |
12836 | intel_connector->unregister(intel_connector); |
11292 | } |
12837 | } |
11293 | 12838 | ||
11294 | drm_mode_config_cleanup(dev); |
12839 | drm_mode_config_cleanup(dev); |
- | 12840 | ||
- | 12841 | intel_cleanup_overlay(dev); |
|
- | 12842 | ||
- | 12843 | mutex_lock(&dev->struct_mutex); |
|
- | 12844 | intel_cleanup_gt_powersave(dev); |
|
- | 12845 | mutex_unlock(&dev->struct_mutex); |
|
11295 | #endif |
12846 | #endif |
11296 | } |
12847 | } |
11297 | 12848 | ||
11298 | /* |
12849 | /* |
11299 | * Return which encoder is currently attached for connector. |
12850 | * Return which encoder is currently attached for connector. |
11300 | */ |
12851 | */ |
11301 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
12852 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
11302 | { |
12853 | { |
11303 | return &intel_attached_encoder(connector)->base; |
12854 | return &intel_attached_encoder(connector)->base; |
11304 | } |
12855 | } |
11305 | 12856 | ||
11306 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12857 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11307 | struct intel_encoder *encoder) |
12858 | struct intel_encoder *encoder) |
11308 | { |
12859 | { |
11309 | connector->encoder = encoder; |
12860 | connector->encoder = encoder; |
11310 | drm_mode_connector_attach_encoder(&connector->base, |
12861 | drm_mode_connector_attach_encoder(&connector->base, |
11311 | &encoder->base); |
12862 | &encoder->base); |
11312 | } |
12863 | } |
11313 | 12864 | ||
11314 | /* |
12865 | /* |
11315 | * set vga decode state - true == enable VGA decode |
12866 | * set vga decode state - true == enable VGA decode |
11316 | */ |
12867 | */ |
11317 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
12868 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
11318 | { |
12869 | { |
11319 | struct drm_i915_private *dev_priv = dev->dev_private; |
12870 | struct drm_i915_private *dev_priv = dev->dev_private; |
11320 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
12871 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
11321 | u16 gmch_ctrl; |
12872 | u16 gmch_ctrl; |
11322 | 12873 | ||
- | 12874 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
|
- | 12875 | DRM_ERROR("failed to read control word\n"); |
|
- | 12876 | return -EIO; |
|
- | 12877 | } |
|
- | 12878 | ||
- | 12879 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
|
- | 12880 | return 0; |
|
11323 | pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); |
12881 | |
11324 | if (state) |
12882 | if (state) |
11325 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
12883 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
11326 | else |
12884 | else |
11327 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
12885 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
- | 12886 | ||
11328 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
12887 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
- | 12888 | DRM_ERROR("failed to write control word\n"); |
|
- | 12889 | return -EIO; |
|
- | 12890 | } |
|
- | 12891 | ||
11329 | return 0; |
12892 | return 0; |
11330 | } |
12893 | } |
11331 | 12894 | ||
11332 | #ifdef CONFIG_DEBUG_FS |
12895 | #ifdef CONFIG_DEBUG_FS |
11333 | 12896 | ||
11334 | struct intel_display_error_state { |
12897 | struct intel_display_error_state { |
11335 | 12898 | ||
11336 | u32 power_well_driver; |
12899 | u32 power_well_driver; |
11337 | 12900 | ||
11338 | int num_transcoders; |
12901 | int num_transcoders; |
11339 | 12902 | ||
11340 | struct intel_cursor_error_state { |
12903 | struct intel_cursor_error_state { |
11341 | u32 control; |
12904 | u32 control; |
11342 | u32 position; |
12905 | u32 position; |
11343 | u32 base; |
12906 | u32 base; |
11344 | u32 size; |
12907 | u32 size; |
11345 | } cursor[I915_MAX_PIPES]; |
12908 | } cursor[I915_MAX_PIPES]; |
11346 | 12909 | ||
11347 | struct intel_pipe_error_state { |
12910 | struct intel_pipe_error_state { |
11348 | bool power_domain_on; |
12911 | bool power_domain_on; |
11349 | u32 source; |
12912 | u32 source; |
- | 12913 | u32 stat; |
|
11350 | } pipe[I915_MAX_PIPES]; |
12914 | } pipe[I915_MAX_PIPES]; |
11351 | 12915 | ||
11352 | struct intel_plane_error_state { |
12916 | struct intel_plane_error_state { |
11353 | u32 control; |
12917 | u32 control; |
11354 | u32 stride; |
12918 | u32 stride; |
11355 | u32 size; |
12919 | u32 size; |
11356 | u32 pos; |
12920 | u32 pos; |
11357 | u32 addr; |
12921 | u32 addr; |
11358 | u32 surface; |
12922 | u32 surface; |
11359 | u32 tile_offset; |
12923 | u32 tile_offset; |
11360 | } plane[I915_MAX_PIPES]; |
12924 | } plane[I915_MAX_PIPES]; |
11361 | 12925 | ||
11362 | struct intel_transcoder_error_state { |
12926 | struct intel_transcoder_error_state { |
11363 | bool power_domain_on; |
12927 | bool power_domain_on; |
11364 | enum transcoder cpu_transcoder; |
12928 | enum transcoder cpu_transcoder; |
11365 | 12929 | ||
11366 | u32 conf; |
12930 | u32 conf; |
11367 | 12931 | ||
11368 | u32 htotal; |
12932 | u32 htotal; |
11369 | u32 hblank; |
12933 | u32 hblank; |
11370 | u32 hsync; |
12934 | u32 hsync; |
11371 | u32 vtotal; |
12935 | u32 vtotal; |
11372 | u32 vblank; |
12936 | u32 vblank; |
11373 | u32 vsync; |
12937 | u32 vsync; |
11374 | } transcoder[4]; |
12938 | } transcoder[4]; |
11375 | }; |
12939 | }; |
11376 | 12940 | ||
11377 | struct intel_display_error_state * |
12941 | struct intel_display_error_state * |
11378 | intel_display_capture_error_state(struct drm_device *dev) |
12942 | intel_display_capture_error_state(struct drm_device *dev) |
11379 | { |
12943 | { |
11380 | drm_i915_private_t *dev_priv = dev->dev_private; |
12944 | struct drm_i915_private *dev_priv = dev->dev_private; |
11381 | struct intel_display_error_state *error; |
12945 | struct intel_display_error_state *error; |
11382 | int transcoders[] = { |
12946 | int transcoders[] = { |
11383 | TRANSCODER_A, |
12947 | TRANSCODER_A, |
11384 | TRANSCODER_B, |
12948 | TRANSCODER_B, |
11385 | TRANSCODER_C, |
12949 | TRANSCODER_C, |
11386 | TRANSCODER_EDP, |
12950 | TRANSCODER_EDP, |
11387 | }; |
12951 | }; |
11388 | int i; |
12952 | int i; |
11389 | 12953 | ||
11390 | if (INTEL_INFO(dev)->num_pipes == 0) |
12954 | if (INTEL_INFO(dev)->num_pipes == 0) |
11391 | return NULL; |
12955 | return NULL; |
11392 | 12956 | ||
11393 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
12957 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
11394 | if (error == NULL) |
12958 | if (error == NULL) |
11395 | return NULL; |
12959 | return NULL; |
11396 | 12960 | ||
11397 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
12961 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
11398 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12962 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11399 | 12963 | ||
11400 | for_each_pipe(i) { |
12964 | for_each_pipe(i) { |
11401 | error->pipe[i].power_domain_on = |
12965 | error->pipe[i].power_domain_on = |
11402 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); |
12966 | intel_display_power_enabled_unlocked(dev_priv, |
- | 12967 | POWER_DOMAIN_PIPE(i)); |
|
11403 | if (!error->pipe[i].power_domain_on) |
12968 | if (!error->pipe[i].power_domain_on) |
11404 | continue; |
12969 | continue; |
11405 | - | ||
11406 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
12970 | |
11407 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12971 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
11408 | error->cursor[i].position = I915_READ(CURPOS(i)); |
12972 | error->cursor[i].position = I915_READ(CURPOS(i)); |
11409 | error->cursor[i].base = I915_READ(CURBASE(i)); |
12973 | error->cursor[i].base = I915_READ(CURBASE(i)); |
11410 | } else { |
- | |
11411 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
- | |
11412 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
- | |
11413 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
- | |
11414 | } |
- | |
11415 | 12974 | ||
11416 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
12975 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
11417 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
12976 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
11418 | if (INTEL_INFO(dev)->gen <= 3) { |
12977 | if (INTEL_INFO(dev)->gen <= 3) { |
11419 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
12978 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
11420 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12979 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11421 | } |
12980 | } |
11422 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12981 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11423 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
12982 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
11424 | if (INTEL_INFO(dev)->gen >= 4) { |
12983 | if (INTEL_INFO(dev)->gen >= 4) { |
11425 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
12984 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
11426 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
12985 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
11427 | } |
12986 | } |
11428 | 12987 | ||
11429 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
12988 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
- | 12989 | ||
- | 12990 | if (HAS_GMCH_DISPLAY(dev)) |
|
- | 12991 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
|
11430 | } |
12992 | } |
11431 | 12993 | ||
11432 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
12994 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
11433 | if (HAS_DDI(dev_priv->dev)) |
12995 | if (HAS_DDI(dev_priv->dev)) |
11434 | error->num_transcoders++; /* Account for eDP. */ |
12996 | error->num_transcoders++; /* Account for eDP. */ |
11435 | 12997 | ||
11436 | for (i = 0; i < error->num_transcoders; i++) { |
12998 | for (i = 0; i < error->num_transcoders; i++) { |
11437 | enum transcoder cpu_transcoder = transcoders[i]; |
12999 | enum transcoder cpu_transcoder = transcoders[i]; |
11438 | 13000 | ||
11439 | error->transcoder[i].power_domain_on = |
13001 | error->transcoder[i].power_domain_on = |
11440 | intel_display_power_enabled_sw(dev, |
13002 | intel_display_power_enabled_unlocked(dev_priv, |
11441 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
13003 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
11442 | if (!error->transcoder[i].power_domain_on) |
13004 | if (!error->transcoder[i].power_domain_on) |
11443 | continue; |
13005 | continue; |
11444 | 13006 | ||
11445 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13007 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11446 | 13008 | ||
11447 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
13009 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
11448 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
13010 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
11449 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
13011 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
11450 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
13012 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
11451 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
13013 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
11452 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
13014 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
11453 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
13015 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
11454 | } |
13016 | } |
11455 | 13017 | ||
11456 | return error; |
13018 | return error; |
11457 | } |
13019 | } |
11458 | 13020 | ||
11459 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13021 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11460 | 13022 | ||
11461 | void |
13023 | void |
11462 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
13024 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
11463 | struct drm_device *dev, |
13025 | struct drm_device *dev, |
11464 | struct intel_display_error_state *error) |
13026 | struct intel_display_error_state *error) |
11465 | { |
13027 | { |
11466 | int i; |
13028 | int i; |
11467 | 13029 | ||
11468 | if (!error) |
13030 | if (!error) |
11469 | return; |
13031 | return; |
11470 | 13032 | ||
11471 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
13033 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
11472 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
13034 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
11473 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
13035 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
11474 | error->power_well_driver); |
13036 | error->power_well_driver); |
11475 | for_each_pipe(i) { |
13037 | for_each_pipe(i) { |
11476 | err_printf(m, "Pipe [%d]:\n", i); |
13038 | err_printf(m, "Pipe [%d]:\n", i); |
11477 | err_printf(m, " Power: %s\n", |
13039 | err_printf(m, " Power: %s\n", |
11478 | error->pipe[i].power_domain_on ? "on" : "off"); |
13040 | error->pipe[i].power_domain_on ? "on" : "off"); |
11479 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
13041 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
- | 13042 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
|
11480 | 13043 | ||
11481 | err_printf(m, "Plane [%d]:\n", i); |
13044 | err_printf(m, "Plane [%d]:\n", i); |
11482 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
13045 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
11483 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
13046 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
11484 | if (INTEL_INFO(dev)->gen <= 3) { |
13047 | if (INTEL_INFO(dev)->gen <= 3) { |
11485 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13048 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11486 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
13049 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
11487 | } |
13050 | } |
11488 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13051 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11489 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
13052 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
11490 | if (INTEL_INFO(dev)->gen >= 4) { |
13053 | if (INTEL_INFO(dev)->gen >= 4) { |
11491 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13054 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11492 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
13055 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
11493 | } |
13056 | } |
11494 | 13057 | ||
11495 | err_printf(m, "Cursor [%d]:\n", i); |
13058 | err_printf(m, "Cursor [%d]:\n", i); |
11496 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
13059 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
11497 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
13060 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
11498 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
13061 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
11499 | } |
13062 | } |
11500 | 13063 | ||
11501 | for (i = 0; i < error->num_transcoders; i++) { |
13064 | for (i = 0; i < error->num_transcoders; i++) { |
11502 | err_printf(m, "CPU transcoder: %c\n", |
13065 | err_printf(m, "CPU transcoder: %c\n", |
11503 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
13066 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
11504 | err_printf(m, " Power: %s\n", |
13067 | err_printf(m, " Power: %s\n", |
11505 | error->transcoder[i].power_domain_on ? "on" : "off"); |
13068 | error->transcoder[i].power_domain_on ? "on" : "off"); |
11506 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13069 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11507 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
13070 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
11508 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
13071 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
11509 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
13072 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
11510 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
13073 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
11511 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
13074 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
11512 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
13075 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
11513 | } |
13076 | } |
11514 | } |
13077 | } |
11515 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>>>><>><>>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>>><>>>>><>>><>><>=>>><>><>=>>><>><>>><>><>><>><>>><>><>><>><>>>>><>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>>=>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>>=>=>><>><>><>><>><>><>><>><>>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |
13078 | #endif>=>=>>=>=>>>>>5,><5,>>>>>>><>>>=>>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>><>>>><>><>>>>>>><>>>>><>>><>><>=>>><>><>=>>><>><>>><>><>><>><>>><>><>><>><>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>=>>><>><>><>><>><>><>><>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>=>>=>=>><>><>><>><>><>><>><>><>><>>><>><>>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>><>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>>><>><>><>=> |