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Line 37... | Line 37... | ||
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
- | 42 | #include |
|
- | 43 | #include |
|
42 | //#include |
44 | #include |
- | 45 | ||
- | 46 | static inline void ndelay(unsigned long x) |
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- | 47 | { |
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- | 48 | udelay(DIV_ROUND_UP(x, 1000)); |
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- | 49 | } |
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- | 50 | ||
- | 51 | /* Primary plane formats supported by all gen */ |
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- | 52 | #define COMMON_PRIMARY_FORMATS \ |
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- | 53 | DRM_FORMAT_C8, \ |
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- | 54 | DRM_FORMAT_RGB565, \ |
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- | 55 | DRM_FORMAT_XRGB8888, \ |
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- | 56 | DRM_FORMAT_ARGB8888 |
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- | 57 | ||
- | 58 | /* Primary plane formats for gen <= 3 */ |
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- | 59 | static const uint32_t intel_primary_formats_gen2[] = { |
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- | 60 | COMMON_PRIMARY_FORMATS, |
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- | 61 | DRM_FORMAT_XRGB1555, |
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- | 62 | DRM_FORMAT_ARGB1555, |
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- | 63 | }; |
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- | 64 | ||
- | 65 | /* Primary plane formats for gen >= 4 */ |
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- | 66 | static const uint32_t intel_primary_formats_gen4[] = { |
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- | 67 | COMMON_PRIMARY_FORMATS, \ |
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- | 68 | DRM_FORMAT_XBGR8888, |
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- | 69 | DRM_FORMAT_ABGR8888, |
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- | 70 | DRM_FORMAT_XRGB2101010, |
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- | 71 | DRM_FORMAT_ARGB2101010, |
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- | 72 | DRM_FORMAT_XBGR2101010, |
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- | 73 | DRM_FORMAT_ABGR2101010, |
|
- | 74 | }; |
|
- | 75 | ||
- | 76 | /* Cursor formats */ |
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- | 77 | static const uint32_t intel_cursor_formats[] = { |
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- | 78 | DRM_FORMAT_ARGB8888, |
|
- | 79 | }; |
|
- | 80 | ||
- | 81 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
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- | 82 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
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Line 43... | Line 83... | ||
43 | 83 | ||
44 | #define MAX_ERRNO 4095 |
84 | #define MAX_ERRNO 4095 |
Line 45... | Line 85... | ||
45 | phys_addr_t get_bus_addr(void); |
85 | phys_addr_t get_bus_addr(void); |
Line 53... | Line 93... | ||
53 | u8 v; |
93 | u8 v; |
54 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
94 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
55 | return v; |
95 | return v; |
56 | } |
96 | } |
Line 57... | Line 97... | ||
57 | 97 | ||
- | 98 | static void intel_increase_pllclock(struct drm_device *dev, |
|
58 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
99 | enum pipe pipe); |
Line 59... | Line 100... | ||
59 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
100 | void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
60 | 101 | ||
61 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
102 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
62 | struct intel_crtc_config *pipe_config); |
103 | struct intel_crtc_config *pipe_config); |
Line 63... | Line 104... | ||
63 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
104 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
64 | struct intel_crtc_config *pipe_config); |
105 | struct intel_crtc_config *pipe_config); |
- | 106 | ||
- | 107 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
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- | 108 | int x, int y, struct drm_framebuffer *old_fb); |
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- | 109 | static int intel_framebuffer_init(struct drm_device *dev, |
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- | 110 | struct intel_framebuffer *ifb, |
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- | 111 | struct drm_mode_fb_cmd2 *mode_cmd, |
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- | 112 | struct drm_i915_gem_object *obj); |
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- | 113 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
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- | 114 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
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- | 115 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
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- | 116 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
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- | 117 | struct intel_link_m_n *m_n); |
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- | 118 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
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Line -... | Line 119... | ||
- | 119 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
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- | 120 | static void intel_set_pipe_csc(struct drm_crtc *crtc); |
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- | 121 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
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- | 122 | ||
- | 123 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
|
- | 124 | { |
|
- | 125 | if (!connector->mst_port) |
|
Line 65... | Line 126... | ||
65 | 126 | return connector->encoder; |
|
66 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
127 | else |
67 | int x, int y, struct drm_framebuffer *old_fb); |
128 | return &connector->mst_port->mst_encoders[pipe]->base; |
Line 337... | Line 398... | ||
337 | .m2 = { .min = 11, .max = 156 }, |
398 | .m2 = { .min = 11, .max = 156 }, |
338 | .p1 = { .min = 2, .max = 3 }, |
399 | .p1 = { .min = 2, .max = 3 }, |
339 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
400 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
340 | }; |
401 | }; |
Line -... | Line 402... | ||
- | 402 | ||
- | 403 | static const intel_limit_t intel_limits_chv = { |
|
- | 404 | /* |
|
- | 405 | * These are the data rate limits (measured in fast clocks) |
|
- | 406 | * since those are the strictest limits we have. The fast |
|
- | 407 | * clock and actual rate limits are more relaxed, so checking |
|
- | 408 | * them would make no difference. |
|
- | 409 | */ |
|
- | 410 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
|
- | 411 | .vco = { .min = 4860000, .max = 6700000 }, |
|
- | 412 | .n = { .min = 1, .max = 1 }, |
|
- | 413 | .m1 = { .min = 2, .max = 2 }, |
|
- | 414 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
|
- | 415 | .p1 = { .min = 2, .max = 4 }, |
|
- | 416 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
|
- | 417 | }; |
|
341 | 418 | ||
342 | static void vlv_clock(int refclk, intel_clock_t *clock) |
419 | static void vlv_clock(int refclk, intel_clock_t *clock) |
343 | { |
420 | { |
344 | clock->m = clock->m1 * clock->m2; |
421 | clock->m = clock->m1 * clock->m2; |
345 | clock->p = clock->p1 * clock->p2; |
422 | clock->p = clock->p1 * clock->p2; |
Line 421... | Line 498... | ||
421 | } else if (IS_PINEVIEW(dev)) { |
498 | } else if (IS_PINEVIEW(dev)) { |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
499 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
423 | limit = &intel_limits_pineview_lvds; |
500 | limit = &intel_limits_pineview_lvds; |
424 | else |
501 | else |
425 | limit = &intel_limits_pineview_sdvo; |
502 | limit = &intel_limits_pineview_sdvo; |
- | 503 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 504 | limit = &intel_limits_chv; |
|
426 | } else if (IS_VALLEYVIEW(dev)) { |
505 | } else if (IS_VALLEYVIEW(dev)) { |
427 | limit = &intel_limits_vlv; |
506 | limit = &intel_limits_vlv; |
428 | } else if (!IS_GEN2(dev)) { |
507 | } else if (!IS_GEN2(dev)) { |
429 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
508 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
430 | limit = &intel_limits_i9xx_lvds; |
509 | limit = &intel_limits_i9xx_lvds; |
Line 465... | Line 544... | ||
465 | return; |
544 | return; |
466 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
545 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
467 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
546 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
468 | } |
547 | } |
Line -... | Line 548... | ||
- | 548 | ||
- | 549 | static void chv_clock(int refclk, intel_clock_t *clock) |
|
- | 550 | { |
|
- | 551 | clock->m = clock->m1 * clock->m2; |
|
- | 552 | clock->p = clock->p1 * clock->p2; |
|
- | 553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
|
- | 554 | return; |
|
- | 555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
|
- | 556 | clock->n << 22); |
|
- | 557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
- | 558 | } |
|
469 | 559 | ||
470 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
560 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
471 | /** |
561 | /** |
472 | * Returns whether the given set of divisors are valid for a given refclk with |
562 | * Returns whether the given set of divisors are valid for a given refclk with |
473 | * the given connectors. |
563 | * the given connectors. |
Line 740... | Line 830... | ||
740 | } |
830 | } |
Line 741... | Line 831... | ||
741 | 831 | ||
742 | return found; |
832 | return found; |
Line -... | Line 833... | ||
- | 833 | } |
|
- | 834 | ||
- | 835 | static bool |
|
- | 836 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
|
- | 837 | int target, int refclk, intel_clock_t *match_clock, |
|
- | 838 | intel_clock_t *best_clock) |
|
- | 839 | { |
|
- | 840 | struct drm_device *dev = crtc->dev; |
|
- | 841 | intel_clock_t clock; |
|
- | 842 | uint64_t m2; |
|
- | 843 | int found = false; |
|
- | 844 | ||
- | 845 | memset(best_clock, 0, sizeof(*best_clock)); |
|
- | 846 | ||
- | 847 | /* |
|
- | 848 | * Based on hardware doc, the n always set to 1, and m1 always |
|
- | 849 | * set to 2. If requires to support 200Mhz refclk, we need to |
|
- | 850 | * revisit this because n may not 1 anymore. |
|
- | 851 | */ |
|
- | 852 | clock.n = 1, clock.m1 = 2; |
|
- | 853 | target *= 5; /* fast clock */ |
|
- | 854 | ||
- | 855 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
|
- | 856 | for (clock.p2 = limit->p2.p2_fast; |
|
- | 857 | clock.p2 >= limit->p2.p2_slow; |
|
- | 858 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
|
- | 859 | ||
- | 860 | clock.p = clock.p1 * clock.p2; |
|
- | 861 | ||
- | 862 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
|
- | 863 | clock.n) << 22, refclk * clock.m1); |
|
- | 864 | ||
- | 865 | if (m2 > INT_MAX/clock.m1) |
|
- | 866 | continue; |
|
- | 867 | ||
- | 868 | clock.m2 = m2; |
|
- | 869 | ||
- | 870 | chv_clock(refclk, &clock); |
|
- | 871 | ||
- | 872 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
|
- | 873 | continue; |
|
- | 874 | ||
- | 875 | /* based on hardware requirement, prefer bigger p |
|
- | 876 | */ |
|
- | 877 | if (clock.p > best_clock->p) { |
|
- | 878 | *best_clock = clock; |
|
- | 879 | found = true; |
|
- | 880 | } |
|
- | 881 | } |
|
- | 882 | } |
|
- | 883 | ||
- | 884 | return found; |
|
743 | } |
885 | } |
744 | 886 | ||
745 | bool intel_crtc_active(struct drm_crtc *crtc) |
887 | bool intel_crtc_active(struct drm_crtc *crtc) |
Line 746... | Line 888... | ||
746 | { |
888 | { |
747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
748 | 890 | ||
749 | /* Be paranoid as we can arrive here with only partial |
891 | /* Be paranoid as we can arrive here with only partial |
750 | * state retrieved from the hardware during setup. |
892 | * state retrieved from the hardware during setup. |
751 | * |
893 | * |
752 | * We can ditch the adjusted_mode.crtc_clock check as soon |
894 | * We can ditch the adjusted_mode.crtc_clock check as soon |
753 | * as Haswell has gained clock readout/fastboot support. |
895 | * as Haswell has gained clock readout/fastboot support. |
754 | * |
896 | * |
755 | * We can ditch the crtc->fb check as soon as we can |
897 | * We can ditch the crtc->primary->fb check as soon as we can |
756 | * properly reconstruct framebuffers. |
898 | * properly reconstruct framebuffers. |
757 | */ |
899 | */ |
Line 758... | Line 900... | ||
758 | return intel_crtc->active && crtc->fb && |
900 | return intel_crtc->active && crtc->primary->fb && |
759 | intel_crtc->config.adjusted_mode.crtc_clock; |
901 | intel_crtc->config.adjusted_mode.crtc_clock; |
Line 774... | Line 916... | ||
774 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
916 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
Line 775... | Line 917... | ||
775 | 917 | ||
Line 776... | Line 918... | ||
776 | frame = I915_READ(frame_reg); |
918 | frame = I915_READ(frame_reg); |
777 | 919 | ||
778 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
920 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
Line 779... | Line 921... | ||
779 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
921 | WARN(1, "vblank wait timed out\n"); |
780 | } |
922 | } |
781 | 923 | ||
Line 977... | Line 1119... | ||
977 | bool state) |
1119 | bool state) |
978 | { |
1120 | { |
979 | bool cur_state; |
1121 | bool cur_state; |
980 | struct intel_dpll_hw_state hw_state; |
1122 | struct intel_dpll_hw_state hw_state; |
Line 981... | Line -... | ||
981 | - | ||
982 | if (HAS_PCH_LPT(dev_priv->dev)) { |
- | |
983 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
- | |
984 | return; |
- | |
985 | } |
- | |
986 | 1123 | ||
987 | if (WARN (!pll, |
1124 | if (WARN (!pll, |
988 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
1125 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
Line 989... | Line 1126... | ||
989 | return; |
1126 | return; |
Line 1042... | Line 1179... | ||
1042 | { |
1179 | { |
1043 | int reg; |
1180 | int reg; |
1044 | u32 val; |
1181 | u32 val; |
Line 1045... | Line 1182... | ||
1045 | 1182 | ||
1046 | /* ILK FDI PLL is always enabled */ |
1183 | /* ILK FDI PLL is always enabled */ |
1047 | if (dev_priv->info->gen == 5) |
1184 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
Line 1048... | Line 1185... | ||
1048 | return; |
1185 | return; |
1049 | 1186 | ||
1050 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1187 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
Line 1104... | Line 1241... | ||
1104 | enum pipe pipe, bool state) |
1241 | enum pipe pipe, bool state) |
1105 | { |
1242 | { |
1106 | struct drm_device *dev = dev_priv->dev; |
1243 | struct drm_device *dev = dev_priv->dev; |
1107 | bool cur_state; |
1244 | bool cur_state; |
Line 1108... | Line -... | ||
1108 | - | ||
1109 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
- | |
1110 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; |
1245 | |
1111 | else if (IS_845G(dev) || IS_I865G(dev)) |
1246 | if (IS_845G(dev) || IS_I865G(dev)) |
1112 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
1247 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
1113 | else |
1248 | else |
Line 1114... | Line 1249... | ||
1114 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
1249 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Line 1131... | Line 1266... | ||
1131 | 1266 | ||
1132 | /* if we need the pipe A quirk it must be always on */ |
1267 | /* if we need the pipe A quirk it must be always on */ |
1133 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1268 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
Line 1134... | Line 1269... | ||
1134 | state = true; |
1269 | state = true; |
1135 | 1270 | ||
1136 | if (!intel_display_power_enabled(dev_priv->dev, |
1271 | if (!intel_display_power_enabled(dev_priv, |
1137 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1272 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1138 | cur_state = false; |
1273 | cur_state = false; |
1139 | } else { |
1274 | } else { |
Line 1175... | Line 1310... | ||
1175 | 1310 | ||
1176 | /* Primary planes are fixed to pipes on gen4+ */ |
1311 | /* Primary planes are fixed to pipes on gen4+ */ |
1177 | if (INTEL_INFO(dev)->gen >= 4) { |
1312 | if (INTEL_INFO(dev)->gen >= 4) { |
1178 | reg = DSPCNTR(pipe); |
1313 | reg = DSPCNTR(pipe); |
1179 | val = I915_READ(reg); |
1314 | val = I915_READ(reg); |
1180 | WARN((val & DISPLAY_PLANE_ENABLE), |
1315 | WARN(val & DISPLAY_PLANE_ENABLE, |
1181 | "plane %c assertion failure, should be disabled but not\n", |
1316 | "plane %c assertion failure, should be disabled but not\n", |
1182 | plane_name(pipe)); |
1317 | plane_name(pipe)); |
1183 | return; |
1318 | return; |
Line 1197... | Line 1332... | ||
1197 | 1332 | ||
1198 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1333 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1199 | enum pipe pipe) |
1334 | enum pipe pipe) |
1200 | { |
1335 | { |
1201 | struct drm_device *dev = dev_priv->dev; |
1336 | struct drm_device *dev = dev_priv->dev; |
1202 | int reg, i; |
1337 | int reg, sprite; |
Line 1203... | Line 1338... | ||
1203 | u32 val; |
1338 | u32 val; |
1204 | 1339 | ||
1205 | if (IS_VALLEYVIEW(dev)) { |
1340 | if (IS_VALLEYVIEW(dev)) { |
1206 | for (i = 0; i < dev_priv->num_plane; i++) { |
1341 | for_each_sprite(pipe, sprite) { |
1207 | reg = SPCNTR(pipe, i); |
1342 | reg = SPCNTR(pipe, sprite); |
1208 | val = I915_READ(reg); |
1343 | val = I915_READ(reg); |
1209 | WARN((val & SP_ENABLE), |
1344 | WARN(val & SP_ENABLE, |
1210 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1345 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1211 | sprite_name(pipe, i), pipe_name(pipe)); |
1346 | sprite_name(pipe, sprite), pipe_name(pipe)); |
1212 | } |
1347 | } |
1213 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1348 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1214 | reg = SPRCTL(pipe); |
1349 | reg = SPRCTL(pipe); |
1215 | val = I915_READ(reg); |
1350 | val = I915_READ(reg); |
1216 | WARN((val & SPRITE_ENABLE), |
1351 | WARN(val & SPRITE_ENABLE, |
1217 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1352 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1218 | plane_name(pipe), pipe_name(pipe)); |
1353 | plane_name(pipe), pipe_name(pipe)); |
1219 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1354 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1220 | reg = DVSCNTR(pipe); |
1355 | reg = DVSCNTR(pipe); |
1221 | val = I915_READ(reg); |
1356 | val = I915_READ(reg); |
1222 | WARN((val & DVS_ENABLE), |
1357 | WARN(val & DVS_ENABLE, |
1223 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1358 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1224 | plane_name(pipe), pipe_name(pipe)); |
1359 | plane_name(pipe), pipe_name(pipe)); |
Line 1262... | Line 1397... | ||
1262 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1397 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1263 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1398 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1264 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1399 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1265 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1400 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1266 | return false; |
1401 | return false; |
- | 1402 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
|
- | 1403 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
|
- | 1404 | return false; |
|
1267 | } else { |
1405 | } else { |
1268 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1406 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1269 | return false; |
1407 | return false; |
1270 | } |
1408 | } |
1271 | return true; |
1409 | return true; |
Line 1278... | Line 1416... | ||
1278 | return false; |
1416 | return false; |
Line 1279... | Line 1417... | ||
1279 | 1417 | ||
1280 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1418 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1281 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1419 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
- | 1420 | return false; |
|
- | 1421 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
|
- | 1422 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
|
1282 | return false; |
1423 | return false; |
1283 | } else { |
1424 | } else { |
1284 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1425 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1285 | return false; |
1426 | return false; |
1286 | } |
1427 | } |
Line 1376... | Line 1517... | ||
1376 | struct drm_i915_private *dev_priv = dev->dev_private; |
1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1377... | Line 1518... | ||
1377 | 1518 | ||
1378 | if (!IS_VALLEYVIEW(dev)) |
1519 | if (!IS_VALLEYVIEW(dev)) |
Line -... | Line 1520... | ||
- | 1520 | return; |
|
- | 1521 | ||
- | 1522 | /* |
|
- | 1523 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), |
|
- | 1524 | * CHV x1 PHY (DP/HDMI D) |
|
- | 1525 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) |
|
- | 1526 | */ |
|
- | 1527 | if (IS_CHERRYVIEW(dev)) { |
|
- | 1528 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; |
|
1379 | return; |
1529 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; |
1380 | 1530 | } else { |
|
- | 1531 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
|
Line 1381... | Line 1532... | ||
1381 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
1532 | } |
1382 | } |
1533 | } |
1383 | 1534 | ||
Line 1384... | Line 1535... | ||
1384 | static void intel_reset_dpio(struct drm_device *dev) |
1535 | static void intel_reset_dpio(struct drm_device *dev) |
- | 1536 | { |
|
1385 | { |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1386... | Line -... | ||
1386 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1387 | 1538 | ||
1388 | if (!IS_VALLEYVIEW(dev)) |
1539 | if (IS_CHERRYVIEW(dev)) { |
1389 | return; |
- | |
1390 | 1540 | enum dpio_phy phy; |
|
1391 | /* |
1541 | u32 val; |
1392 | * Enable the CRI clock source so we can get at the display and the |
1542 | |
Line 1393... | Line 1543... | ||
1393 | * reference clock for VGA hotplug / manual detection. |
1543 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { |
1394 | */ |
- | |
1395 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
1544 | /* Poll for phypwrgood signal */ |
1396 | DPLL_REFA_CLK_ENABLE_VLV | |
- | |
1397 | DPLL_INTEGRATED_CRI_CLK_VLV); |
- | |
1398 | - | ||
1399 | /* |
1545 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & |
1400 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
1546 | PHY_POWERGOOD(phy), 1)) |
1401 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
1547 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
- | 1548 | ||
1402 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
1549 | /* |
1403 | * b. The other bits such as sfr settings / modesel may all be set |
1550 | * Deassert common lane reset for PHY. |
- | 1551 | * |
|
- | 1552 | * This should only be done on init and resume from S3 |
|
- | 1553 | * with both PLLs disabled, or we risk losing DPIO and |
|
- | 1554 | * PLL synchronization. |
|
1404 | * to 0. |
1555 | */ |
Line 1405... | Line 1556... | ||
1405 | * |
1556 | val = I915_READ(DISPLAY_PHY_CONTROL); |
1406 | * This should only be done on init and resume from S3 with both |
1557 | I915_WRITE(DISPLAY_PHY_CONTROL, |
1407 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. |
1558 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); |
Line 1445... | Line 1596... | ||
1445 | I915_WRITE(reg, dpll); |
1596 | I915_WRITE(reg, dpll); |
1446 | POSTING_READ(reg); |
1597 | POSTING_READ(reg); |
1447 | udelay(150); /* wait for warmup */ |
1598 | udelay(150); /* wait for warmup */ |
1448 | } |
1599 | } |
Line -... | Line 1600... | ||
- | 1600 | ||
- | 1601 | static void chv_enable_pll(struct intel_crtc *crtc) |
|
- | 1602 | { |
|
- | 1603 | struct drm_device *dev = crtc->base.dev; |
|
- | 1604 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1605 | int pipe = crtc->pipe; |
|
- | 1606 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 1607 | u32 tmp; |
|
- | 1608 | ||
- | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
|
- | 1610 | ||
- | 1611 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); |
|
- | 1612 | ||
- | 1613 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1614 | ||
- | 1615 | /* Enable back the 10bit clock to display controller */ |
|
- | 1616 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
|
- | 1617 | tmp |= DPIO_DCLKP_EN; |
|
- | 1618 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
|
- | 1619 | ||
- | 1620 | /* |
|
- | 1621 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
|
- | 1622 | */ |
|
- | 1623 | udelay(1); |
|
- | 1624 | ||
- | 1625 | /* Enable PLL */ |
|
- | 1626 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
|
- | 1627 | ||
- | 1628 | /* Check PLL is locked */ |
|
- | 1629 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
|
- | 1630 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
|
- | 1631 | ||
- | 1632 | /* not sure when this should be written */ |
|
- | 1633 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); |
|
- | 1634 | POSTING_READ(DPLL_MD(pipe)); |
|
- | 1635 | ||
- | 1636 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 1637 | } |
|
1449 | 1638 | ||
1450 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1639 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1451 | { |
1640 | { |
1452 | struct drm_device *dev = crtc->base.dev; |
1641 | struct drm_device *dev = crtc->base.dev; |
1453 | struct drm_i915_private *dev_priv = dev->dev_private; |
1642 | struct drm_i915_private *dev_priv = dev->dev_private; |
1454 | int reg = DPLL(crtc->pipe); |
1643 | int reg = DPLL(crtc->pipe); |
Line 1455... | Line 1644... | ||
1455 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1644 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
Line 1456... | Line 1645... | ||
1456 | 1645 | ||
1457 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Line 1458... | Line 1647... | ||
1458 | 1647 | ||
1459 | /* No really, not for ILK+ */ |
1648 | /* No really, not for ILK+ */ |
1460 | BUG_ON(dev_priv->info->gen >= 5); |
1649 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
Line 1528... | Line 1717... | ||
1528 | */ |
1717 | */ |
1529 | if (pipe == PIPE_B) |
1718 | if (pipe == PIPE_B) |
1530 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1719 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1531 | I915_WRITE(DPLL(pipe), val); |
1720 | I915_WRITE(DPLL(pipe), val); |
1532 | POSTING_READ(DPLL(pipe)); |
1721 | POSTING_READ(DPLL(pipe)); |
- | 1722 | ||
- | 1723 | } |
|
- | 1724 | ||
- | 1725 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
|
- | 1726 | { |
|
- | 1727 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 1728 | u32 val; |
|
- | 1729 | ||
- | 1730 | /* Make sure the pipe isn't still relying on us */ |
|
- | 1731 | assert_pipe_disabled(dev_priv, pipe); |
|
- | 1732 | ||
- | 1733 | /* Set PLL en = 0 */ |
|
- | 1734 | val = DPLL_SSC_REF_CLOCK_CHV; |
|
- | 1735 | if (pipe != PIPE_A) |
|
- | 1736 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 1737 | I915_WRITE(DPLL(pipe), val); |
|
- | 1738 | POSTING_READ(DPLL(pipe)); |
|
- | 1739 | ||
- | 1740 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1741 | ||
- | 1742 | /* Disable 10bit clock to display controller */ |
|
- | 1743 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
|
- | 1744 | val &= ~DPIO_DCLKP_EN; |
|
- | 1745 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
|
- | 1746 | ||
- | 1747 | /* disable left/right clock distribution */ |
|
- | 1748 | if (pipe != PIPE_B) { |
|
- | 1749 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
|
- | 1750 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
|
- | 1751 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
|
- | 1752 | } else { |
|
- | 1753 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
|
- | 1754 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
|
- | 1755 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
|
- | 1756 | } |
|
- | 1757 | ||
- | 1758 | mutex_unlock(&dev_priv->dpio_lock); |
|
1533 | } |
1759 | } |
Line 1534... | Line 1760... | ||
1534 | 1760 | ||
1535 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1761 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1536 | struct intel_digital_port *dport) |
1762 | struct intel_digital_port *dport) |
1537 | { |
1763 | { |
- | 1764 | u32 port_mask; |
|
Line 1538... | Line 1765... | ||
1538 | u32 port_mask; |
1765 | int dpll_reg; |
1539 | 1766 | ||
1540 | switch (dport->port) { |
1767 | switch (dport->port) { |
- | 1768 | case PORT_B: |
|
1541 | case PORT_B: |
1769 | port_mask = DPLL_PORTB_READY_MASK; |
1542 | port_mask = DPLL_PORTB_READY_MASK; |
1770 | dpll_reg = DPLL(0); |
1543 | break; |
1771 | break; |
- | 1772 | case PORT_C: |
|
- | 1773 | port_mask = DPLL_PORTC_READY_MASK; |
|
- | 1774 | dpll_reg = DPLL(0); |
|
- | 1775 | break; |
|
- | 1776 | case PORT_D: |
|
1544 | case PORT_C: |
1777 | port_mask = DPLL_PORTD_READY_MASK; |
1545 | port_mask = DPLL_PORTC_READY_MASK; |
1778 | dpll_reg = DPIO_PHY_STATUS; |
1546 | break; |
1779 | break; |
1547 | default: |
1780 | default: |
Line 1548... | Line 1781... | ||
1548 | BUG(); |
1781 | BUG(); |
1549 | } |
1782 | } |
1550 | 1783 | ||
- | 1784 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
|
- | 1785 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
|
- | 1786 | port_name(dport->port), I915_READ(dpll_reg)); |
|
- | 1787 | } |
|
- | 1788 | ||
- | 1789 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
|
- | 1790 | { |
|
- | 1791 | struct drm_device *dev = crtc->base.dev; |
|
- | 1792 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1793 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
|
- | 1794 | ||
- | 1795 | if (WARN_ON(pll == NULL)) |
|
- | 1796 | return; |
|
- | 1797 | ||
- | 1798 | WARN_ON(!pll->refcount); |
|
- | 1799 | if (pll->active == 0) { |
|
- | 1800 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
|
- | 1801 | WARN_ON(pll->on); |
|
- | 1802 | assert_shared_dpll_disabled(dev_priv, pll); |
|
1551 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1803 | |
Line 1552... | Line 1804... | ||
1552 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1804 | pll->mode_set(dev_priv, pll); |
1553 | port_name(dport->port), I915_READ(DPLL(0))); |
1805 | } |
1554 | } |
1806 | } |
1555 | 1807 | ||
1556 | /** |
1808 | /** |
1557 | * ironlake_enable_shared_dpll - enable PCH PLL |
1809 | * intel_enable_shared_dpll - enable PCH PLL |
1558 | * @dev_priv: i915 private structure |
1810 | * @dev_priv: i915 private structure |
1559 | * @pipe: pipe PLL to enable |
1811 | * @pipe: pipe PLL to enable |
1560 | * |
1812 | * |
1561 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1813 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
- | 1814 | * drives the transcoder clock. |
|
1562 | * drives the transcoder clock. |
1815 | */ |
1563 | */ |
1816 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
Line 1564... | Line -... | ||
1564 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
- | |
1565 | { |
- | |
1566 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1817 | { |
1567 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1818 | struct drm_device *dev = crtc->base.dev; |
Line 1568... | Line 1819... | ||
1568 | 1819 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
1569 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1820 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Line 1583... | Line 1834... | ||
1583 | assert_shared_dpll_enabled(dev_priv, pll); |
1834 | assert_shared_dpll_enabled(dev_priv, pll); |
1584 | return; |
1835 | return; |
1585 | } |
1836 | } |
1586 | WARN_ON(pll->on); |
1837 | WARN_ON(pll->on); |
Line -... | Line 1838... | ||
- | 1838 | ||
- | 1839 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
|
1587 | 1840 | ||
1588 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1841 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1589 | pll->enable(dev_priv, pll); |
1842 | pll->enable(dev_priv, pll); |
1590 | pll->on = true; |
1843 | pll->on = true; |
Line 1591... | Line 1844... | ||
1591 | } |
1844 | } |
1592 | 1845 | ||
- | 1846 | void intel_disable_shared_dpll(struct intel_crtc *crtc) |
|
1593 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1847 | { |
1594 | { |
1848 | struct drm_device *dev = crtc->base.dev; |
Line 1595... | Line 1849... | ||
1595 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1849 | struct drm_i915_private *dev_priv = dev->dev_private; |
1596 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1850 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1597 | 1851 | ||
1598 | /* PCH only available on ILK+ */ |
1852 | /* PCH only available on ILK+ */ |
Line 1599... | Line 1853... | ||
1599 | BUG_ON(dev_priv->info->gen < 5); |
1853 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1600 | if (WARN_ON(pll == NULL)) |
1854 | if (WARN_ON(pll == NULL)) |
Line 1618... | Line 1872... | ||
1618 | return; |
1872 | return; |
Line 1619... | Line 1873... | ||
1619 | 1873 | ||
1620 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1874 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1621 | pll->disable(dev_priv, pll); |
1875 | pll->disable(dev_priv, pll); |
- | 1876 | pll->on = false; |
|
- | 1877 | ||
1622 | pll->on = false; |
1878 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
Line 1623... | Line 1879... | ||
1623 | } |
1879 | } |
1624 | 1880 | ||
1625 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1881 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
Line 1629... | Line 1885... | ||
1629 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1885 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1631 | uint32_t reg, val, pipeconf_val; |
1887 | uint32_t reg, val, pipeconf_val; |
Line 1632... | Line 1888... | ||
1632 | 1888 | ||
1633 | /* PCH only available on ILK+ */ |
1889 | /* PCH only available on ILK+ */ |
Line 1634... | Line 1890... | ||
1634 | BUG_ON(dev_priv->info->gen < 5); |
1890 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1635 | 1891 | ||
1636 | /* Make sure PCH DPLL is enabled */ |
1892 | /* Make sure PCH DPLL is enabled */ |
Line 1682... | Line 1938... | ||
1682 | enum transcoder cpu_transcoder) |
1938 | enum transcoder cpu_transcoder) |
1683 | { |
1939 | { |
1684 | u32 val, pipeconf_val; |
1940 | u32 val, pipeconf_val; |
Line 1685... | Line 1941... | ||
1685 | 1941 | ||
1686 | /* PCH only available on ILK+ */ |
1942 | /* PCH only available on ILK+ */ |
Line 1687... | Line 1943... | ||
1687 | BUG_ON(dev_priv->info->gen < 5); |
1943 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
1688 | 1944 | ||
1689 | /* FDI must be feeding us bits for PCH ports */ |
1945 | /* FDI must be feeding us bits for PCH ports */ |
Line 1756... | Line 2012... | ||
1756 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2012 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1757 | } |
2013 | } |
Line 1758... | Line 2014... | ||
1758 | 2014 | ||
1759 | /** |
2015 | /** |
1760 | * intel_enable_pipe - enable a pipe, asserting requirements |
- | |
1761 | * @dev_priv: i915 private structure |
2016 | * intel_enable_pipe - enable a pipe, asserting requirements |
1762 | * @pipe: pipe to enable |
- | |
1763 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
2017 | * @crtc: crtc responsible for the pipe |
1764 | * |
2018 | * |
1765 | * Enable @pipe, making sure that various hardware specific requirements |
2019 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
1766 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
- | |
1767 | * |
- | |
1768 | * @pipe should be %PIPE_A or %PIPE_B. |
- | |
1769 | * |
- | |
1770 | * Will wait until the pipe is actually running (i.e. first vblank) before |
- | |
1771 | * returning. |
2020 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1772 | */ |
2021 | */ |
1773 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
- | |
1774 | bool pch_port, bool dsi) |
2022 | static void intel_enable_pipe(struct intel_crtc *crtc) |
- | 2023 | { |
|
- | 2024 | struct drm_device *dev = crtc->base.dev; |
|
- | 2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
1775 | { |
2026 | enum pipe pipe = crtc->pipe; |
1776 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2027 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1777 | pipe); |
2028 | pipe); |
1778 | enum pipe pch_transcoder; |
2029 | enum pipe pch_transcoder; |
1779 | int reg; |
2030 | int reg; |
Line 1792... | Line 2043... | ||
1792 | * A pipe without a PLL won't actually be able to drive bits from |
2043 | * A pipe without a PLL won't actually be able to drive bits from |
1793 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
2044 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1794 | * need the check. |
2045 | * need the check. |
1795 | */ |
2046 | */ |
1796 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
2047 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1797 | if (dsi) |
2048 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
1798 | assert_dsi_pll_enabled(dev_priv); |
2049 | assert_dsi_pll_enabled(dev_priv); |
1799 | else |
2050 | else |
1800 | assert_pll_enabled(dev_priv, pipe); |
2051 | assert_pll_enabled(dev_priv, pipe); |
1801 | else { |
2052 | else { |
1802 | if (pch_port) { |
2053 | if (crtc->config.has_pch_encoder) { |
1803 | /* if driving the PCH, we need FDI enabled */ |
2054 | /* if driving the PCH, we need FDI enabled */ |
1804 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
2055 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1805 | assert_fdi_tx_pll_enabled(dev_priv, |
2056 | assert_fdi_tx_pll_enabled(dev_priv, |
1806 | (enum pipe) cpu_transcoder); |
2057 | (enum pipe) cpu_transcoder); |
1807 | } |
2058 | } |
1808 | /* FIXME: assert CPU port conditions for SNB+ */ |
2059 | /* FIXME: assert CPU port conditions for SNB+ */ |
1809 | } |
2060 | } |
Line 1810... | Line 2061... | ||
1810 | 2061 | ||
1811 | reg = PIPECONF(cpu_transcoder); |
2062 | reg = PIPECONF(cpu_transcoder); |
1812 | val = I915_READ(reg); |
2063 | val = I915_READ(reg); |
- | 2064 | if (val & PIPECONF_ENABLE) { |
|
- | 2065 | WARN_ON(!(pipe == PIPE_A && |
|
1813 | if (val & PIPECONF_ENABLE) |
2066 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
- | 2067 | return; |
|
Line 1814... | Line 2068... | ||
1814 | return; |
2068 | } |
1815 | 2069 | ||
1816 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
2070 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Line 1817... | Line 2071... | ||
1817 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2071 | POSTING_READ(reg); |
1818 | } |
2072 | } |
1819 | 2073 | ||
Line 1863... | Line 2117... | ||
1863 | * trigger in order to latch. The display address reg provides this. |
2117 | * trigger in order to latch. The display address reg provides this. |
1864 | */ |
2118 | */ |
1865 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2119 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1866 | enum plane plane) |
2120 | enum plane plane) |
1867 | { |
2121 | { |
- | 2122 | struct drm_device *dev = dev_priv->dev; |
|
1868 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
2123 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
Line 1869... | Line 2124... | ||
1869 | 2124 | ||
1870 | I915_WRITE(reg, I915_READ(reg)); |
2125 | I915_WRITE(reg, I915_READ(reg)); |
1871 | POSTING_READ(reg); |
2126 | POSTING_READ(reg); |
Line 1872... | Line 2127... | ||
1872 | } |
2127 | } |
1873 | 2128 | ||
1874 | /** |
2129 | /** |
1875 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
2130 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
1876 | * @dev_priv: i915 private structure |
2131 | * @dev_priv: i915 private structure |
1877 | * @plane: plane to enable |
2132 | * @plane: plane to enable |
1878 | * @pipe: pipe being fed |
2133 | * @pipe: pipe being fed |
1879 | * |
2134 | * |
1880 | * Enable @plane on @pipe, making sure that @pipe is running first. |
2135 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1881 | */ |
2136 | */ |
1882 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
2137 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
- | 2138 | enum plane plane, enum pipe pipe) |
|
1883 | enum plane plane, enum pipe pipe) |
2139 | { |
1884 | { |
2140 | struct drm_device *dev = dev_priv->dev; |
1885 | struct intel_crtc *intel_crtc = |
2141 | struct intel_crtc *intel_crtc = |
1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
2142 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Line 1887... | Line 2143... | ||
1887 | int reg; |
2143 | int reg; |
1888 | u32 val; |
2144 | u32 val; |
Line 1889... | Line 2145... | ||
1889 | 2145 | ||
- | 2146 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
|
Line 1890... | Line 2147... | ||
1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
2147 | assert_pipe_enabled(dev_priv, pipe); |
Line 1891... | Line 2148... | ||
1891 | assert_pipe_enabled(dev_priv, pipe); |
2148 | |
1892 | 2149 | if (intel_crtc->primary_enabled) |
|
1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
2150 | return; |
1894 | - | ||
Line 1895... | Line 2151... | ||
1895 | intel_crtc->primary_enabled = true; |
2151 | |
1896 | 2152 | intel_crtc->primary_enabled = true; |
|
1897 | reg = DSPCNTR(plane); |
- | |
1898 | val = I915_READ(reg); |
2153 | |
Line 1899... | Line 2154... | ||
1899 | if (val & DISPLAY_PLANE_ENABLE) |
2154 | reg = DSPCNTR(plane); |
1900 | return; |
2155 | val = I915_READ(reg); |
1901 | 2156 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
|
1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
2157 | |
1903 | intel_flush_primary_plane(dev_priv, plane); |
2158 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2159 | intel_flush_primary_plane(dev_priv, plane); |
1905 | } |
2160 | } |
1906 | 2161 | ||
1907 | /** |
2162 | /** |
1908 | * intel_disable_primary_plane - disable the primary plane |
2163 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
1909 | * @dev_priv: i915 private structure |
2164 | * @dev_priv: i915 private structure |
1910 | * @plane: plane to disable |
2165 | * @plane: plane to disable |
1911 | * @pipe: pipe consuming the data |
2166 | * @pipe: pipe consuming the data |
1912 | * |
2167 | * |
1913 | * Disable @plane; should be an independent operation. |
2168 | * Disable @plane; should be an independent operation. |
Line 1914... | Line 2169... | ||
1914 | */ |
2169 | */ |
- | 2170 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
|
Line 1915... | Line 2171... | ||
1915 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
2171 | enum plane plane, enum pipe pipe) |
Line 1916... | Line 2172... | ||
1916 | enum plane plane, enum pipe pipe) |
2172 | { |
1917 | { |
2173 | struct intel_crtc *intel_crtc = |
1918 | struct intel_crtc *intel_crtc = |
2174 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
- | |
Line 1920... | Line 2175... | ||
1920 | int reg; |
2175 | int reg; |
1921 | u32 val; |
2176 | u32 val; |
1922 | - | ||
1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
2177 | |
Line 1924... | Line 2178... | ||
1924 | 2178 | if (!intel_crtc->primary_enabled) |
|
1925 | intel_crtc->primary_enabled = false; |
2179 | return; |
1926 | 2180 | ||
Line 1941... | Line 2195... | ||
1941 | return true; |
2195 | return true; |
1942 | #endif |
2196 | #endif |
1943 | return false; |
2197 | return false; |
1944 | } |
2198 | } |
Line -... | Line 2199... | ||
- | 2199 | ||
- | 2200 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
|
- | 2201 | { |
|
- | 2202 | int tile_height; |
|
- | 2203 | ||
- | 2204 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
|
- | 2205 | return ALIGN(height, tile_height); |
|
- | 2206 | } |
|
1945 | 2207 | ||
1946 | int |
2208 | int |
1947 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
2209 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1948 | struct drm_i915_gem_object *obj, |
2210 | struct drm_i915_gem_object *obj, |
1949 | struct intel_ring_buffer *pipelined) |
2211 | struct intel_engine_cs *pipelined) |
1950 | { |
2212 | { |
1951 | struct drm_i915_private *dev_priv = dev->dev_private; |
2213 | struct drm_i915_private *dev_priv = dev->dev_private; |
1952 | u32 alignment; |
2214 | u32 alignment; |
Line -... | Line 2215... | ||
- | 2215 | int ret; |
|
- | 2216 | ||
1953 | int ret; |
2217 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
1954 | 2218 | ||
1955 | switch (obj->tiling_mode) { |
2219 | switch (obj->tiling_mode) { |
1956 | case I915_TILING_NONE: |
2220 | case I915_TILING_NONE: |
1957 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2221 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
Line 2006... | Line 2270... | ||
2006 | return ret; |
2270 | return ret; |
2007 | } |
2271 | } |
Line 2008... | Line 2272... | ||
2008 | 2272 | ||
2009 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2273 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
- | 2274 | { |
|
- | 2275 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
|
2010 | { |
2276 | |
2011 | // i915_gem_object_unpin_fence(obj); |
2277 | i915_gem_object_unpin_fence(obj); |
2012 | // i915_gem_object_unpin(obj); |
2278 | // i915_gem_object_unpin_from_display_plane(obj); |
Line 2013... | Line 2279... | ||
2013 | } |
2279 | } |
2014 | 2280 | ||
2015 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2281 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
Line 2037... | Line 2303... | ||
2037 | *x = (offset & 4095) / cpp; |
2303 | *x = (offset & 4095) / cpp; |
2038 | return offset & -4096; |
2304 | return offset & -4096; |
2039 | } |
2305 | } |
2040 | } |
2306 | } |
Line -... | Line 2307... | ||
- | 2307 | ||
- | 2308 | int intel_format_to_fourcc(int format) |
|
- | 2309 | { |
|
- | 2310 | switch (format) { |
|
- | 2311 | case DISPPLANE_8BPP: |
|
- | 2312 | return DRM_FORMAT_C8; |
|
- | 2313 | case DISPPLANE_BGRX555: |
|
- | 2314 | return DRM_FORMAT_XRGB1555; |
|
- | 2315 | case DISPPLANE_BGRX565: |
|
- | 2316 | return DRM_FORMAT_RGB565; |
|
- | 2317 | default: |
|
- | 2318 | case DISPPLANE_BGRX888: |
|
- | 2319 | return DRM_FORMAT_XRGB8888; |
|
- | 2320 | case DISPPLANE_RGBX888: |
|
- | 2321 | return DRM_FORMAT_XBGR8888; |
|
- | 2322 | case DISPPLANE_BGRX101010: |
|
- | 2323 | return DRM_FORMAT_XRGB2101010; |
|
- | 2324 | case DISPPLANE_RGBX101010: |
|
- | 2325 | return DRM_FORMAT_XBGR2101010; |
|
- | 2326 | } |
|
- | 2327 | } |
|
- | 2328 | ||
- | 2329 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
|
- | 2330 | struct intel_plane_config *plane_config) |
|
- | 2331 | { |
|
- | 2332 | struct drm_device *dev = crtc->base.dev; |
|
- | 2333 | struct drm_i915_gem_object *obj = NULL; |
|
- | 2334 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
|
- | 2335 | u32 base = plane_config->base; |
|
- | 2336 | ||
- | 2337 | if (plane_config->size == 0) |
|
- | 2338 | return false; |
|
- | 2339 | ||
- | 2340 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
|
- | 2341 | plane_config->size); |
|
- | 2342 | if (!obj) |
|
- | 2343 | return false; |
|
- | 2344 | ||
- | 2345 | main_fb_obj = obj; |
|
- | 2346 | ||
- | 2347 | if (plane_config->tiled) { |
|
- | 2348 | obj->tiling_mode = I915_TILING_X; |
|
- | 2349 | obj->stride = crtc->base.primary->fb->pitches[0]; |
|
- | 2350 | } |
|
- | 2351 | ||
- | 2352 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
|
- | 2353 | mode_cmd.width = crtc->base.primary->fb->width; |
|
- | 2354 | mode_cmd.height = crtc->base.primary->fb->height; |
|
- | 2355 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; |
|
- | 2356 | ||
- | 2357 | mutex_lock(&dev->struct_mutex); |
|
- | 2358 | ||
- | 2359 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
|
- | 2360 | &mode_cmd, obj)) { |
|
- | 2361 | DRM_DEBUG_KMS("intel fb init failed\n"); |
|
- | 2362 | goto out_unref_obj; |
|
- | 2363 | } |
|
- | 2364 | ||
- | 2365 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
|
- | 2366 | mutex_unlock(&dev->struct_mutex); |
|
- | 2367 | ||
- | 2368 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); |
|
- | 2369 | return true; |
|
- | 2370 | ||
- | 2371 | out_unref_obj: |
|
- | 2372 | drm_gem_object_unreference(&obj->base); |
|
- | 2373 | mutex_unlock(&dev->struct_mutex); |
|
- | 2374 | return false; |
|
- | 2375 | } |
|
- | 2376 | ||
- | 2377 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
|
- | 2378 | struct intel_plane_config *plane_config) |
|
- | 2379 | { |
|
- | 2380 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 2381 | struct drm_crtc *c; |
|
- | 2382 | struct intel_crtc *i; |
|
- | 2383 | struct drm_i915_gem_object *obj; |
|
- | 2384 | ||
- | 2385 | if (!intel_crtc->base.primary->fb) |
|
- | 2386 | return; |
|
- | 2387 | ||
- | 2388 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
|
- | 2389 | return; |
|
- | 2390 | ||
- | 2391 | kfree(intel_crtc->base.primary->fb); |
|
- | 2392 | intel_crtc->base.primary->fb = NULL; |
|
- | 2393 | ||
- | 2394 | /* |
|
- | 2395 | * Failed to alloc the obj, check to see if we should share |
|
- | 2396 | * an fb with another CRTC instead |
|
- | 2397 | */ |
|
- | 2398 | for_each_crtc(dev, c) { |
|
- | 2399 | i = to_intel_crtc(c); |
|
- | 2400 | ||
- | 2401 | if (c == &intel_crtc->base) |
|
- | 2402 | continue; |
|
- | 2403 | ||
- | 2404 | if (!i->active) |
|
- | 2405 | continue; |
|
- | 2406 | ||
- | 2407 | obj = intel_fb_obj(c->primary->fb); |
|
- | 2408 | if (obj == NULL) |
|
- | 2409 | continue; |
|
- | 2410 | ||
- | 2411 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
|
- | 2412 | drm_framebuffer_reference(c->primary->fb); |
|
- | 2413 | intel_crtc->base.primary->fb = c->primary->fb; |
|
- | 2414 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
|
- | 2415 | break; |
|
- | 2416 | } |
|
- | 2417 | } |
|
- | 2418 | } |
|
2041 | 2419 | ||
- | 2420 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
|
2042 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2421 | struct drm_framebuffer *fb, |
2043 | int x, int y) |
2422 | int x, int y) |
2044 | { |
2423 | { |
2045 | struct drm_device *dev = crtc->dev; |
2424 | struct drm_device *dev = crtc->dev; |
2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
2425 | struct drm_i915_private *dev_priv = dev->dev_private; |
2047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
2048 | struct intel_framebuffer *intel_fb; |
2426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2049 | struct drm_i915_gem_object *obj; |
2427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2050 | int plane = intel_crtc->plane; |
2428 | int plane = intel_crtc->plane; |
2051 | unsigned long linear_offset; |
2429 | unsigned long linear_offset; |
2052 | u32 dspcntr; |
2430 | u32 dspcntr; |
Line 2053... | Line -... | ||
2053 | u32 reg; |
- | |
2054 | - | ||
2055 | switch (plane) { |
- | |
2056 | case 0: |
- | |
2057 | case 1: |
- | |
2058 | break; |
- | |
2059 | default: |
- | |
2060 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
- | |
2061 | return -EINVAL; |
- | |
2062 | } |
- | |
2063 | - | ||
2064 | intel_fb = to_intel_framebuffer(fb); |
- | |
2065 | obj = intel_fb->obj; |
2431 | u32 reg; |
2066 | 2432 | ||
2067 | reg = DSPCNTR(plane); |
2433 | reg = DSPCNTR(plane); |
2068 | dspcntr = I915_READ(reg); |
2434 | dspcntr = I915_READ(reg); |
2069 | /* Mask out pixel format bits in case we change it */ |
2435 | /* Mask out pixel format bits in case we change it */ |
Line 2133... | Line 2499... | ||
2133 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2499 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2134 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2500 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2135 | } else |
2501 | } else |
2136 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2502 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2137 | POSTING_READ(reg); |
2503 | POSTING_READ(reg); |
2138 | - | ||
2139 | return 0; |
- | |
2140 | } |
2504 | } |
Line 2141... | Line 2505... | ||
2141 | 2505 | ||
2142 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2506 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
- | 2507 | struct drm_framebuffer *fb, |
|
2143 | struct drm_framebuffer *fb, int x, int y) |
2508 | int x, int y) |
2144 | { |
2509 | { |
2145 | struct drm_device *dev = crtc->dev; |
2510 | struct drm_device *dev = crtc->dev; |
2146 | struct drm_i915_private *dev_priv = dev->dev_private; |
2511 | struct drm_i915_private *dev_priv = dev->dev_private; |
2147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
2148 | struct intel_framebuffer *intel_fb; |
2512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2149 | struct drm_i915_gem_object *obj; |
2513 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2150 | int plane = intel_crtc->plane; |
2514 | int plane = intel_crtc->plane; |
2151 | unsigned long linear_offset; |
2515 | unsigned long linear_offset; |
2152 | u32 dspcntr; |
2516 | u32 dspcntr; |
Line 2153... | Line -... | ||
2153 | u32 reg; |
- | |
2154 | - | ||
2155 | switch (plane) { |
- | |
2156 | case 0: |
- | |
2157 | case 1: |
- | |
2158 | case 2: |
- | |
2159 | break; |
- | |
2160 | default: |
- | |
2161 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
- | |
2162 | return -EINVAL; |
- | |
2163 | } |
- | |
2164 | - | ||
2165 | intel_fb = to_intel_framebuffer(fb); |
- | |
2166 | obj = intel_fb->obj; |
2517 | u32 reg; |
2167 | 2518 | ||
2168 | reg = DSPCNTR(plane); |
2519 | reg = DSPCNTR(plane); |
2169 | dspcntr = I915_READ(reg); |
2520 | dspcntr = I915_READ(reg); |
2170 | /* Mask out pixel format bits in case we change it */ |
2521 | /* Mask out pixel format bits in case we change it */ |
Line 2226... | Line 2577... | ||
2226 | } else { |
2577 | } else { |
2227 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2578 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2228 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2579 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2229 | } |
2580 | } |
2230 | POSTING_READ(reg); |
2581 | POSTING_READ(reg); |
2231 | - | ||
2232 | return 0; |
- | |
2233 | } |
2582 | } |
Line 2234... | Line 2583... | ||
2234 | 2583 | ||
2235 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2584 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2236 | static int |
2585 | static int |
Line 2240... | Line 2589... | ||
2240 | struct drm_device *dev = crtc->dev; |
2589 | struct drm_device *dev = crtc->dev; |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; |
2590 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2242... | Line 2591... | ||
2242 | 2591 | ||
2243 | if (dev_priv->display.disable_fbc) |
2592 | if (dev_priv->display.disable_fbc) |
2244 | dev_priv->display.disable_fbc(dev); |
2593 | dev_priv->display.disable_fbc(dev); |
- | 2594 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
|
- | 2595 | ||
Line 2245... | Line 2596... | ||
2245 | intel_increase_pllclock(crtc); |
2596 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2246 | 2597 | ||
Line 2247... | Line 2598... | ||
2247 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2598 | return 0; |
2248 | } |
2599 | } |
2249 | 2600 | ||
Line 2265... | Line 2616... | ||
2265 | * Need to make two loops over the crtcs so that we |
2616 | * Need to make two loops over the crtcs so that we |
2266 | * don't try to grab a crtc mutex before the |
2617 | * don't try to grab a crtc mutex before the |
2267 | * pending_flip_queue really got woken up. |
2618 | * pending_flip_queue really got woken up. |
2268 | */ |
2619 | */ |
Line 2269... | Line 2620... | ||
2269 | 2620 | ||
2270 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2621 | for_each_crtc(dev, crtc) { |
2271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 2272... | Line 2623... | ||
2272 | enum plane plane = intel_crtc->plane; |
2623 | enum plane plane = intel_crtc->plane; |
2273 | 2624 | ||
2274 | intel_prepare_page_flip(dev, plane); |
2625 | intel_prepare_page_flip(dev, plane); |
Line 2275... | Line 2626... | ||
2275 | intel_finish_page_flip_plane(dev, plane); |
2626 | intel_finish_page_flip_plane(dev, plane); |
2276 | } |
2627 | } |
Line 2277... | Line 2628... | ||
2277 | 2628 | ||
2278 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2629 | for_each_crtc(dev, crtc) { |
2279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2280 | 2631 | ||
2281 | mutex_lock(&crtc->mutex); |
2632 | drm_modeset_lock(&crtc->mutex, NULL); |
2282 | /* |
2633 | /* |
2283 | * FIXME: Once we have proper support for primary planes (and |
2634 | * FIXME: Once we have proper support for primary planes (and |
2284 | * disabling them without disabling the entire crtc) allow again |
2635 | * disabling them without disabling the entire crtc) allow again |
- | 2636 | * a NULL crtc->primary->fb. |
|
- | 2637 | */ |
|
2285 | * a NULL crtc->fb. |
2638 | if (intel_crtc->active && crtc->primary->fb) |
2286 | */ |
2639 | dev_priv->display.update_primary_plane(crtc, |
2287 | if (intel_crtc->active && crtc->fb) |
2640 | crtc->primary->fb, |
2288 | dev_priv->display.update_plane(crtc, crtc->fb, |
2641 | crtc->x, |
Line 2289... | Line 2642... | ||
2289 | crtc->x, crtc->y); |
2642 | crtc->y); |
2290 | mutex_unlock(&crtc->mutex); |
2643 | drm_modeset_unlock(&crtc->mutex); |
2291 | } |
2644 | } |
2292 | } |
2645 | } |
2293 | 2646 | ||
2294 | static int |
2647 | static int |
2295 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2648 | intel_finish_fb(struct drm_framebuffer *old_fb) |
Line 2296... | Line 2649... | ||
2296 | { |
2649 | { |
Line 2312... | Line 2665... | ||
2312 | dev_priv->mm.interruptible = was_interruptible; |
2665 | dev_priv->mm.interruptible = was_interruptible; |
Line 2313... | Line 2666... | ||
2313 | 2666 | ||
2314 | return ret; |
2667 | return ret; |
Line 2315... | Line 2668... | ||
2315 | } |
2668 | } |
2316 | 2669 | ||
2317 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2670 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2318 | { |
2671 | { |
2319 | struct drm_device *dev = crtc->dev; |
2672 | struct drm_device *dev = crtc->dev; |
- | 2673 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
Line 2320... | Line 2675... | ||
2320 | struct drm_i915_master_private *master_priv; |
2675 | unsigned long flags; |
- | 2676 | bool pending; |
|
2321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2677 | |
Line 2322... | Line 2678... | ||
2322 | 2678 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
|
2323 | if (!dev->primary->master) |
2679 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2324 | return; |
2680 | return false; |
Line 2325... | Line -... | ||
2325 | - | ||
2326 | master_priv = dev->primary->master->driver_priv; |
- | |
2327 | if (!master_priv->sarea_priv) |
- | |
2328 | return; |
- | |
2329 | 2681 | ||
2330 | switch (intel_crtc->pipe) { |
- | |
2331 | case 0: |
- | |
2332 | master_priv->sarea_priv->pipeA_x = x; |
- | |
2333 | master_priv->sarea_priv->pipeA_y = y; |
- | |
2334 | break; |
- | |
2335 | case 1: |
- | |
2336 | master_priv->sarea_priv->pipeB_x = x; |
- | |
2337 | master_priv->sarea_priv->pipeB_y = y; |
2682 | spin_lock_irqsave(&dev->event_lock, flags); |
2338 | break; |
2683 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
Line 2339... | Line 2684... | ||
2339 | default: |
2684 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2340 | break; |
2685 | |
2341 | } |
2686 | return pending; |
2342 | } |
2687 | } |
2343 | #endif |
2688 | #endif |
2344 | 2689 | ||
2345 | static int |
2690 | static int |
- | 2691 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
|
2346 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2692 | struct drm_framebuffer *fb) |
- | 2693 | { |
|
- | 2694 | struct drm_device *dev = crtc->dev; |
|
2347 | struct drm_framebuffer *fb) |
2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line -... | Line 2696... | ||
- | 2696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
2348 | { |
2697 | enum pipe pipe = intel_crtc->pipe; |
2349 | struct drm_device *dev = crtc->dev; |
2698 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2350 | struct drm_i915_private *dev_priv = dev->dev_private; |
2699 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2700 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
2352 | struct drm_framebuffer *old_fb; |
2701 | int ret; |
Line 2364... | Line 2713... | ||
2364 | INTEL_INFO(dev)->num_pipes); |
2713 | INTEL_INFO(dev)->num_pipes); |
2365 | return -EINVAL; |
2714 | return -EINVAL; |
2366 | } |
2715 | } |
Line 2367... | Line 2716... | ||
2367 | 2716 | ||
2368 | mutex_lock(&dev->struct_mutex); |
2717 | mutex_lock(&dev->struct_mutex); |
- | 2718 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
|
2369 | ret = intel_pin_and_fence_fb_obj(dev, |
2719 | if (ret == 0) |
2370 | to_intel_framebuffer(fb)->obj, |
2720 | i915_gem_track_fb(old_obj, obj, |
2371 | NULL); |
- | |
2372 | if (ret != 0) { |
2721 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
- | 2722 | mutex_unlock(&dev->struct_mutex); |
|
2373 | mutex_unlock(&dev->struct_mutex); |
2723 | if (ret != 0) { |
2374 | DRM_ERROR("pin & fence failed\n"); |
2724 | DRM_ERROR("pin & fence failed\n"); |
2375 | return ret; |
2725 | return ret; |
Line 2376... | Line 2726... | ||
2376 | } |
2726 | } |
Line 2386... | Line 2736... | ||
2386 | * To fix this properly, we need to hoist the checks up into |
2736 | * To fix this properly, we need to hoist the checks up into |
2387 | * compute_mode_changes (or above), check the actual pfit state and |
2737 | * compute_mode_changes (or above), check the actual pfit state and |
2388 | * whether the platform allows pfit disable with pipe active, and only |
2738 | * whether the platform allows pfit disable with pipe active, and only |
2389 | * then update the pipesrc and pfit state, even on the flip path. |
2739 | * then update the pipesrc and pfit state, even on the flip path. |
2390 | */ |
2740 | */ |
2391 | if (i915_fastboot) { |
2741 | if (i915.fastboot) { |
2392 | const struct drm_display_mode *adjusted_mode = |
2742 | const struct drm_display_mode *adjusted_mode = |
2393 | &intel_crtc->config.adjusted_mode; |
2743 | &intel_crtc->config.adjusted_mode; |
Line 2394... | Line 2744... | ||
2394 | 2744 | ||
2395 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2745 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
Line 2404... | Line 2754... | ||
2404 | } |
2754 | } |
2405 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2755 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2406 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
2756 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
2407 | } |
2757 | } |
Line 2408... | Line 2758... | ||
2408 | 2758 | ||
2409 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2759 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2410 | if (ret) { |
- | |
2411 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2760 | |
2412 | mutex_unlock(&dev->struct_mutex); |
2761 | if (intel_crtc->active) |
2413 | DRM_ERROR("failed to update base address\n"); |
- | |
2414 | return ret; |
- | |
Line 2415... | Line -... | ||
2415 | } |
- | |
2416 | 2762 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
2417 | old_fb = crtc->fb; |
2763 | |
2418 | crtc->fb = fb; |
2764 | crtc->primary->fb = fb; |
Line 2419... | Line 2765... | ||
2419 | crtc->x = x; |
2765 | crtc->x = x; |
2420 | crtc->y = y; |
2766 | crtc->y = y; |
2421 | 2767 | ||
- | 2768 | if (old_fb) { |
|
2422 | if (old_fb) { |
2769 | if (intel_crtc->active && old_fb != fb) |
- | 2770 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
2423 | if (intel_crtc->active && old_fb != fb) |
2771 | mutex_lock(&dev->struct_mutex); |
Line -... | Line 2772... | ||
- | 2772 | intel_unpin_fb_obj(old_obj); |
|
2424 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2773 | mutex_unlock(&dev->struct_mutex); |
2425 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
- | |
2426 | } |
2774 | } |
Line 2427... | Line 2775... | ||
2427 | 2775 | ||
2428 | intel_update_fbc(dev); |
2776 | mutex_lock(&dev->struct_mutex); |
Line 2510... | Line 2858... | ||
2510 | { |
2858 | { |
2511 | struct drm_device *dev = crtc->dev; |
2859 | struct drm_device *dev = crtc->dev; |
2512 | struct drm_i915_private *dev_priv = dev->dev_private; |
2860 | struct drm_i915_private *dev_priv = dev->dev_private; |
2513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2514 | int pipe = intel_crtc->pipe; |
2862 | int pipe = intel_crtc->pipe; |
2515 | int plane = intel_crtc->plane; |
- | |
2516 | u32 reg, temp, tries; |
2863 | u32 reg, temp, tries; |
Line 2517... | Line 2864... | ||
2517 | 2864 | ||
2518 | /* FDI needs bits from pipe & plane first */ |
2865 | /* FDI needs bits from pipe first */ |
2519 | assert_pipe_enabled(dev_priv, pipe); |
- | |
Line 2520... | Line 2866... | ||
2520 | assert_plane_enabled(dev_priv, plane); |
2866 | assert_pipe_enabled(dev_priv, pipe); |
2521 | 2867 | ||
2522 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2868 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2523 | for train result */ |
2869 | for train result */ |
Line 2946... | Line 3292... | ||
2946 | 3292 | ||
2947 | POSTING_READ(reg); |
3293 | POSTING_READ(reg); |
Line 2948... | Line 3294... | ||
2948 | udelay(100); |
3294 | udelay(100); |
2949 | 3295 | ||
2950 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
3296 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2951 | if (HAS_PCH_IBX(dev)) { |
- | |
Line 2952... | Line 3297... | ||
2952 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3297 | if (HAS_PCH_IBX(dev)) |
2953 | } |
3298 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2954 | 3299 | ||
2955 | /* still set train pattern 1 */ |
3300 | /* still set train pattern 1 */ |
Line 2975... | Line 3320... | ||
2975 | 3320 | ||
2976 | POSTING_READ(reg); |
3321 | POSTING_READ(reg); |
2977 | udelay(100); |
3322 | udelay(100); |
Line 2978... | Line 3323... | ||
2978 | } |
3323 | } |
2979 | 3324 | ||
2980 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3325 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2981 | { |
- | |
2982 | struct drm_device *dev = crtc->dev; |
- | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
2984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
Line -... | Line 3326... | ||
- | 3326 | { |
|
- | 3327 | struct intel_crtc *crtc; |
|
- | 3328 | ||
- | 3329 | /* Note that we don't need to be called with mode_config.lock here |
|
- | 3330 | * as our list of CRTC objects is static for the lifetime of the |
|
- | 3331 | * device and so cannot disappear as we iterate. Similarly, we can |
|
- | 3332 | * happily treat the predicates as racy, atomic checks as userspace |
|
2985 | unsigned long flags; |
3333 | * cannot claim and pin a new fb without at least acquring the |
2986 | bool pending; |
3334 | * struct_mutex and so serialising with us. |
2987 | 3335 | */ |
|
Line 2988... | Line -... | ||
2988 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
- | |
2989 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
3336 | for_each_intel_crtc(dev, crtc) { |
2990 | return false; |
3337 | if (atomic_read(&crtc->unpin_work_count) == 0) |
Line -... | Line 3338... | ||
- | 3338 | continue; |
|
- | 3339 | ||
- | 3340 | if (crtc->unpin_work) |
|
2991 | 3341 | intel_wait_for_vblank(dev, crtc->pipe); |
|
2992 | spin_lock_irqsave(&dev->event_lock, flags); |
3342 | |
Line 2993... | Line 3343... | ||
2993 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
3343 | return true; |
2994 | spin_unlock_irqrestore(&dev->event_lock, flags); |
3344 | } |
2995 | 3345 | ||
2996 | return pending; |
3346 | return false; |
2997 | } |
3347 | } |
Line 2998... | Line 3348... | ||
2998 | 3348 | ||
2999 | #if 0 |
3349 | #if 0 |
Line 3000... | Line 3350... | ||
3000 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3350 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
Line 3001... | Line 3351... | ||
3001 | { |
3351 | { |
3002 | struct drm_device *dev = crtc->dev; |
3352 | struct drm_device *dev = crtc->dev; |
- | 3353 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line 3003... | Line 3354... | ||
3003 | struct drm_i915_private *dev_priv = dev->dev_private; |
3354 | |
3004 | 3355 | if (crtc->primary->fb == NULL) |
|
3005 | if (crtc->fb == NULL) |
3356 | return; |
3006 | return; |
3357 | |
3007 | 3358 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
|
Line 3008... | Line 3359... | ||
3008 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3359 | |
Line 3220... | Line 3571... | ||
3220 | * transcoder that already use the clock when we share it. |
3571 | * transcoder that already use the clock when we share it. |
3221 | * |
3572 | * |
3222 | * Note that enable_shared_dpll tries to do the right thing, but |
3573 | * Note that enable_shared_dpll tries to do the right thing, but |
3223 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3574 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3224 | * the right LVDS enable sequence. */ |
3575 | * the right LVDS enable sequence. */ |
3225 | ironlake_enable_shared_dpll(intel_crtc); |
3576 | intel_enable_shared_dpll(intel_crtc); |
Line 3226... | Line 3577... | ||
3226 | 3577 | ||
3227 | /* set transcoder timing, panel must allow it */ |
3578 | /* set transcoder timing, panel must allow it */ |
3228 | assert_panel_unlocked(dev_priv, pipe); |
3579 | assert_panel_unlocked(dev_priv, pipe); |
Line 3284... | Line 3635... | ||
3284 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3635 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
Line 3285... | Line 3636... | ||
3285 | 3636 | ||
3286 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3637 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
Line 3287... | Line 3638... | ||
3287 | } |
3638 | } |
3288 | 3639 | ||
3289 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3640 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
Line 3290... | Line 3641... | ||
3290 | { |
3641 | { |
3291 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3642 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Line 3304... | Line 3655... | ||
3304 | } |
3655 | } |
Line 3305... | Line 3656... | ||
3305 | 3656 | ||
3306 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3657 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
Line 3307... | Line 3658... | ||
3307 | } |
3658 | } |
3308 | 3659 | ||
3309 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3660 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3310 | { |
3661 | { |
3311 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3662 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
Line 3324... | Line 3675... | ||
3324 | pll = &dev_priv->shared_dplls[i]; |
3675 | pll = &dev_priv->shared_dplls[i]; |
Line 3325... | Line 3676... | ||
3325 | 3676 | ||
3326 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3677 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
Line -... | Line 3678... | ||
- | 3678 | crtc->base.base.id, pll->name); |
|
- | 3679 | ||
3327 | crtc->base.base.id, pll->name); |
3680 | WARN_ON(pll->refcount); |
3328 | 3681 | ||
Line 3329... | Line 3682... | ||
3329 | goto found; |
3682 | goto found; |
3330 | } |
3683 | } |
Line 3357... | Line 3710... | ||
3357 | } |
3710 | } |
Line 3358... | Line 3711... | ||
3358 | 3711 | ||
Line 3359... | Line 3712... | ||
3359 | return NULL; |
3712 | return NULL; |
- | 3713 | ||
- | 3714 | found: |
|
- | 3715 | if (pll->refcount == 0) |
|
3360 | 3716 | pll->hw_state = crtc->config.dpll_hw_state; |
|
3361 | found: |
3717 | |
3362 | crtc->config.shared_dpll = i; |
3718 | crtc->config.shared_dpll = i; |
Line 3363... | Line -... | ||
3363 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
- | |
3364 | pipe_name(crtc->pipe)); |
- | |
3365 | - | ||
3366 | if (pll->active == 0) { |
- | |
3367 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
- | |
3368 | sizeof(pll->hw_state)); |
- | |
3369 | - | ||
3370 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
- | |
3371 | WARN_ON(pll->on); |
- | |
3372 | assert_shared_dpll_disabled(dev_priv, pll); |
- | |
3373 | 3719 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
|
Line 3374... | Line 3720... | ||
3374 | pll->mode_set(dev_priv, pll); |
3720 | pipe_name(crtc->pipe)); |
3375 | } |
3721 | |
Line 3415... | Line 3761... | ||
3415 | 3761 | ||
3416 | static void intel_enable_planes(struct drm_crtc *crtc) |
3762 | static void intel_enable_planes(struct drm_crtc *crtc) |
3417 | { |
3763 | { |
3418 | struct drm_device *dev = crtc->dev; |
3764 | struct drm_device *dev = crtc->dev; |
- | 3765 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
|
3419 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3766 | struct drm_plane *plane; |
Line 3420... | Line 3767... | ||
3420 | struct intel_plane *intel_plane; |
3767 | struct intel_plane *intel_plane; |
- | 3768 | ||
3421 | 3769 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
|
3422 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3770 | intel_plane = to_intel_plane(plane); |
3423 | if (intel_plane->pipe == pipe) |
3771 | if (intel_plane->pipe == pipe) |
- | 3772 | intel_plane_restore(&intel_plane->base); |
|
Line 3424... | Line 3773... | ||
3424 | intel_plane_restore(&intel_plane->base); |
3773 | } |
3425 | } |
3774 | } |
3426 | 3775 | ||
3427 | static void intel_disable_planes(struct drm_crtc *crtc) |
3776 | static void intel_disable_planes(struct drm_crtc *crtc) |
- | 3777 | { |
|
3428 | { |
3778 | struct drm_device *dev = crtc->dev; |
Line 3429... | Line 3779... | ||
3429 | struct drm_device *dev = crtc->dev; |
3779 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
- | 3780 | struct drm_plane *plane; |
|
3430 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3781 | struct intel_plane *intel_plane; |
3431 | struct intel_plane *intel_plane; |
3782 | |
3432 | 3783 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
|
- | 3784 | intel_plane = to_intel_plane(plane); |
|
Line 3433... | Line 3785... | ||
3433 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3785 | if (intel_plane->pipe == pipe) |
3434 | if (intel_plane->pipe == pipe) |
3786 | intel_plane_disable(&intel_plane->base); |
- | 3787 | } |
|
3435 | intel_plane_disable(&intel_plane->base); |
3788 | } |
Line 3436... | Line 3789... | ||
3436 | } |
3789 | |
3437 | 3790 | void hsw_enable_ips(struct intel_crtc *crtc) |
|
Line 3438... | Line 3791... | ||
3438 | void hsw_enable_ips(struct intel_crtc *crtc) |
3791 | { |
3439 | { |
- | |
3440 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3792 | struct drm_device *dev = crtc->base.dev; |
3441 | - | ||
- | 3793 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
3442 | if (!crtc->config.ips_enabled) |
3794 | |
3443 | return; |
3795 | if (!crtc->config.ips_enabled) |
3444 | 3796 | return; |
|
3445 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3797 | |
3446 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3798 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3447 | * only after intel_enable_plane. And intel_enable_plane already waits |
3799 | intel_wait_for_vblank(dev, crtc->pipe); |
3448 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3800 | |
Line 3475... | Line 3827... | ||
3475 | 3827 | ||
3476 | if (!crtc->config.ips_enabled) |
3828 | if (!crtc->config.ips_enabled) |
Line 3477... | Line 3829... | ||
3477 | return; |
3829 | return; |
3478 | 3830 | ||
3479 | assert_plane_enabled(dev_priv, crtc->plane); |
3831 | assert_plane_enabled(dev_priv, crtc->plane); |
3480 | if (IS_BROADWELL(crtc->base.dev)) { |
3832 | if (IS_BROADWELL(dev)) { |
3481 | mutex_lock(&dev_priv->rps.hw_lock); |
3833 | mutex_lock(&dev_priv->rps.hw_lock); |
- | 3834 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
|
- | 3835 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 3836 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
|
3482 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
3837 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) |
3483 | mutex_unlock(&dev_priv->rps.hw_lock); |
3838 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
3484 | } else { |
3839 | } else { |
3485 | I915_WRITE(IPS_CTL, 0); |
3840 | I915_WRITE(IPS_CTL, 0); |
Line 3511... | Line 3866... | ||
3511 | else |
3866 | else |
3512 | assert_pll_enabled(dev_priv, pipe); |
3867 | assert_pll_enabled(dev_priv, pipe); |
3513 | } |
3868 | } |
Line 3514... | Line 3869... | ||
3514 | 3869 | ||
3515 | /* use legacy palette for Ironlake */ |
3870 | /* use legacy palette for Ironlake */ |
3516 | if (HAS_PCH_SPLIT(dev)) |
3871 | if (!HAS_GMCH_DISPLAY(dev)) |
Line 3517... | Line 3872... | ||
3517 | palreg = LGC_PALETTE(pipe); |
3872 | palreg = LGC_PALETTE(pipe); |
3518 | 3873 | ||
3519 | /* Workaround : Do not read or write the pipe palette/gamma data while |
3874 | /* Workaround : Do not read or write the pipe palette/gamma data while |
Line 3535... | Line 3890... | ||
3535 | 3890 | ||
3536 | if (reenable_ips) |
3891 | if (reenable_ips) |
3537 | hsw_enable_ips(intel_crtc); |
3892 | hsw_enable_ips(intel_crtc); |
Line -... | Line 3893... | ||
- | 3893 | } |
|
- | 3894 | ||
- | 3895 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
|
- | 3896 | { |
|
- | 3897 | if (!enable && intel_crtc->overlay) { |
|
- | 3898 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 3899 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3900 | ||
- | 3901 | mutex_lock(&dev->struct_mutex); |
|
- | 3902 | dev_priv->mm.interruptible = false; |
|
- | 3903 | dev_priv->mm.interruptible = true; |
|
- | 3904 | mutex_unlock(&dev->struct_mutex); |
|
- | 3905 | } |
|
- | 3906 | ||
- | 3907 | /* Let userspace switch the overlay on again. In most cases userspace |
|
- | 3908 | * has to recompute where to put it anyway. |
|
- | 3909 | */ |
|
- | 3910 | } |
|
- | 3911 | ||
- | 3912 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
|
- | 3913 | { |
|
- | 3914 | struct drm_device *dev = crtc->dev; |
|
- | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3916 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3917 | int pipe = intel_crtc->pipe; |
|
- | 3918 | int plane = intel_crtc->plane; |
|
- | 3919 | ||
- | 3920 | drm_vblank_on(dev, pipe); |
|
- | 3921 | ||
- | 3922 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
|
- | 3923 | intel_enable_planes(crtc); |
|
- | 3924 | intel_crtc_update_cursor(crtc, true); |
|
- | 3925 | intel_crtc_dpms_overlay(intel_crtc, true); |
|
- | 3926 | ||
- | 3927 | hsw_enable_ips(intel_crtc); |
|
- | 3928 | ||
- | 3929 | mutex_lock(&dev->struct_mutex); |
|
- | 3930 | intel_update_fbc(dev); |
|
- | 3931 | mutex_unlock(&dev->struct_mutex); |
|
- | 3932 | } |
|
- | 3933 | ||
- | 3934 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
|
- | 3935 | { |
|
- | 3936 | struct drm_device *dev = crtc->dev; |
|
- | 3937 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3939 | int pipe = intel_crtc->pipe; |
|
- | 3940 | int plane = intel_crtc->plane; |
|
- | 3941 | ||
- | 3942 | ||
- | 3943 | if (dev_priv->fbc.plane == plane) |
|
- | 3944 | intel_disable_fbc(dev); |
|
- | 3945 | ||
- | 3946 | hsw_disable_ips(intel_crtc); |
|
- | 3947 | ||
- | 3948 | intel_crtc_dpms_overlay(intel_crtc, false); |
|
- | 3949 | intel_crtc_update_cursor(crtc, false); |
|
- | 3950 | intel_disable_planes(crtc); |
|
- | 3951 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
|
- | 3952 | drm_vblank_off(dev, pipe); |
|
3538 | } |
3953 | } |
3539 | 3954 | ||
3540 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3955 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3541 | { |
3956 | { |
3542 | struct drm_device *dev = crtc->dev; |
3957 | struct drm_device *dev = crtc->dev; |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; |
3958 | struct drm_i915_private *dev_priv = dev->dev_private; |
3544 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3959 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3545 | struct intel_encoder *encoder; |
3960 | struct intel_encoder *encoder; |
Line 3546... | Line 3961... | ||
3546 | int pipe = intel_crtc->pipe; |
3961 | int pipe = intel_crtc->pipe; |
Line 3547... | Line 3962... | ||
3547 | int plane = intel_crtc->plane; |
3962 | enum plane plane = intel_crtc->plane; |
3548 | 3963 | ||
Line -... | Line 3964... | ||
- | 3964 | WARN_ON(!crtc->enabled); |
|
- | 3965 | ||
- | 3966 | if (intel_crtc->active) |
|
- | 3967 | return; |
|
- | 3968 | ||
- | 3969 | if (intel_crtc->config.has_pch_encoder) |
|
- | 3970 | intel_prepare_shared_dpll(intel_crtc); |
|
- | 3971 | ||
- | 3972 | if (intel_crtc->config.has_dp_encoder) |
|
- | 3973 | intel_dp_set_m_n(intel_crtc); |
|
- | 3974 | ||
- | 3975 | intel_set_pipe_timings(intel_crtc); |
|
- | 3976 | ||
- | 3977 | if (intel_crtc->config.has_pch_encoder) { |
|
- | 3978 | intel_cpu_transcoder_set_m_n(intel_crtc, |
|
- | 3979 | &intel_crtc->config.fdi_m_n); |
|
- | 3980 | } |
|
- | 3981 | ||
- | 3982 | ironlake_set_pipeconf(crtc); |
|
- | 3983 | ||
- | 3984 | /* Set up the display plane register */ |
|
- | 3985 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
|
3549 | WARN_ON(!crtc->enabled); |
3986 | POSTING_READ(DSPCNTR(plane)); |
Line 3550... | Line 3987... | ||
3550 | 3987 | ||
3551 | if (intel_crtc->active) |
3988 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
Line 3577... | Line 4014... | ||
3577 | * clocks enabled |
4014 | * clocks enabled |
3578 | */ |
4015 | */ |
3579 | intel_crtc_load_lut(crtc); |
4016 | intel_crtc_load_lut(crtc); |
Line 3580... | Line 4017... | ||
3580 | 4017 | ||
3581 | intel_update_watermarks(crtc); |
- | |
3582 | intel_enable_pipe(dev_priv, pipe, |
- | |
3583 | intel_crtc->config.has_pch_encoder, false); |
- | |
3584 | intel_enable_primary_plane(dev_priv, plane, pipe); |
4018 | intel_update_watermarks(crtc); |
3585 | intel_enable_planes(crtc); |
- | |
Line 3586... | Line 4019... | ||
3586 | intel_crtc_update_cursor(crtc, true); |
4019 | intel_enable_pipe(intel_crtc); |
3587 | 4020 | ||
Line 3588... | Line -... | ||
3588 | if (intel_crtc->config.has_pch_encoder) |
- | |
3589 | ironlake_pch_enable(crtc); |
- | |
3590 | - | ||
3591 | mutex_lock(&dev->struct_mutex); |
- | |
3592 | intel_update_fbc(dev); |
4021 | if (intel_crtc->config.has_pch_encoder) |
3593 | mutex_unlock(&dev->struct_mutex); |
4022 | ironlake_pch_enable(crtc); |
Line 3594... | Line 4023... | ||
3594 | 4023 | ||
3595 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4024 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Line 3596... | Line -... | ||
3596 | encoder->enable(encoder); |
- | |
3597 | - | ||
3598 | if (HAS_PCH_CPT(dev)) |
- | |
3599 | cpt_verify_modeset(dev, intel_crtc->pipe); |
- | |
3600 | - | ||
3601 | /* |
- | |
3602 | * There seems to be a race in PCH platform hw (at least on some |
- | |
3603 | * outputs) where an enabled pipe still completes any pageflip right |
- | |
3604 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
4025 | encoder->enable(encoder); |
3605 | * as the first vblank happend, everything works as expected. Hence just |
4026 | |
Line 3606... | Line 4027... | ||
3606 | * wait for one vblank before returning to avoid strange things |
4027 | if (HAS_PCH_CPT(dev)) |
3607 | * happening. |
4028 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3608 | */ |
4029 | |
3609 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4030 | intel_crtc_enable_planes(crtc); |
3610 | } |
4031 | } |
Line 3611... | Line -... | ||
3611 | - | ||
3612 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
- | |
3613 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
- | |
3614 | { |
- | |
3615 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
- | |
3616 | } |
- | |
3617 | - | ||
3618 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
- | |
3619 | { |
- | |
3620 | struct drm_device *dev = crtc->dev; |
- | |
3621 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3623 | int pipe = intel_crtc->pipe; |
- | |
3624 | int plane = intel_crtc->plane; |
- | |
3625 | - | ||
3626 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
3627 | intel_enable_planes(crtc); |
- | |
3628 | intel_crtc_update_cursor(crtc, true); |
- | |
3629 | - | ||
3630 | hsw_enable_ips(intel_crtc); |
- | |
3631 | - | ||
3632 | mutex_lock(&dev->struct_mutex); |
- | |
3633 | intel_update_fbc(dev); |
- | |
3634 | mutex_unlock(&dev->struct_mutex); |
- | |
3635 | } |
- | |
3636 | - | ||
3637 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) |
- | |
3638 | { |
- | |
3639 | struct drm_device *dev = crtc->dev; |
- | |
3640 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3642 | int pipe = intel_crtc->pipe; |
- | |
3643 | int plane = intel_crtc->plane; |
- | |
3644 | - | ||
3645 | // intel_crtc_wait_for_pending_flips(crtc); |
- | |
3646 | // drm_vblank_off(dev, pipe); |
- | |
3647 | - | ||
3648 | /* FBC must be disabled before disabling the plane on HSW. */ |
- | |
3649 | if (dev_priv->fbc.plane == plane) |
- | |
3650 | intel_disable_fbc(dev); |
- | |
3651 | - | ||
3652 | hsw_disable_ips(intel_crtc); |
4032 | |
3653 | 4033 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
|
3654 | intel_crtc_update_cursor(crtc, false); |
4034 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3655 | intel_disable_planes(crtc); |
4035 | { |
3656 | intel_disable_primary_plane(dev_priv, plane, pipe); |
4036 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
Line 3667... | Line 4047... | ||
3667 | struct drm_device *dev = crtc->base.dev; |
4047 | struct drm_device *dev = crtc->base.dev; |
3668 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
4048 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
Line 3669... | Line 4049... | ||
3669 | 4049 | ||
3670 | /* We want to get the other_active_crtc only if there's only 1 other |
4050 | /* We want to get the other_active_crtc only if there's only 1 other |
3671 | * active crtc. */ |
4051 | * active crtc. */ |
3672 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { |
4052 | for_each_intel_crtc(dev, crtc_it) { |
3673 | if (!crtc_it->active || crtc_it == crtc) |
4053 | if (!crtc_it->active || crtc_it == crtc) |
Line 3674... | Line 4054... | ||
3674 | continue; |
4054 | continue; |
3675 | 4055 | ||
Line 3690... | Line 4070... | ||
3690 | struct drm_device *dev = crtc->dev; |
4070 | struct drm_device *dev = crtc->dev; |
3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
4071 | struct drm_i915_private *dev_priv = dev->dev_private; |
3692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3693 | struct intel_encoder *encoder; |
4073 | struct intel_encoder *encoder; |
3694 | int pipe = intel_crtc->pipe; |
4074 | int pipe = intel_crtc->pipe; |
- | 4075 | enum plane plane = intel_crtc->plane; |
|
Line 3695... | Line 4076... | ||
3695 | 4076 | ||
Line 3696... | Line 4077... | ||
3696 | WARN_ON(!crtc->enabled); |
4077 | WARN_ON(!crtc->enabled); |
3697 | 4078 | ||
Line 3698... | Line 4079... | ||
3698 | if (intel_crtc->active) |
4079 | if (intel_crtc->active) |
- | 4080 | return; |
|
Line 3699... | Line -... | ||
3699 | return; |
- | |
3700 | 4081 | ||
3701 | intel_crtc->active = true; |
4082 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
Line -... | Line 4083... | ||
- | 4083 | intel_enable_shared_dpll(intel_crtc); |
|
- | 4084 | ||
3702 | 4085 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4086 | intel_dp_set_m_n(intel_crtc); |
|
- | 4087 | ||
- | 4088 | intel_set_pipe_timings(intel_crtc); |
|
- | 4089 | ||
- | 4090 | if (intel_crtc->config.has_pch_encoder) { |
|
- | 4091 | intel_cpu_transcoder_set_m_n(intel_crtc, |
|
- | 4092 | &intel_crtc->config.fdi_m_n); |
|
- | 4093 | } |
|
- | 4094 | ||
- | 4095 | haswell_set_pipeconf(crtc); |
|
- | 4096 | ||
- | 4097 | intel_set_pipe_csc(crtc); |
|
3703 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4098 | |
- | 4099 | /* Set up the display plane register */ |
|
Line -... | Line 4100... | ||
- | 4100 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
|
- | 4101 | POSTING_READ(DSPCNTR(plane)); |
|
- | 4102 | ||
3704 | if (intel_crtc->config.has_pch_encoder) |
4103 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
3705 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
4104 | crtc->x, crtc->y); |
3706 | 4105 | ||
Line -... | Line 4106... | ||
- | 4106 | intel_crtc->active = true; |
|
- | 4107 | ||
- | 4108 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
|
- | 4109 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 4110 | if (encoder->pre_enable) |
|
3707 | if (intel_crtc->config.has_pch_encoder) |
4111 | encoder->pre_enable(encoder); |
Line 3708... | Line 4112... | ||
3708 | dev_priv->display.fdi_link_train(crtc); |
4112 | |
Line 3709... | Line 4113... | ||
3709 | 4113 | if (intel_crtc->config.has_pch_encoder) { |
|
Line 3723... | Line 4127... | ||
3723 | 4127 | ||
3724 | intel_ddi_set_pipe_settings(crtc); |
4128 | intel_ddi_set_pipe_settings(crtc); |
Line 3725... | Line 4129... | ||
3725 | intel_ddi_enable_transcoder_func(crtc); |
4129 | intel_ddi_enable_transcoder_func(crtc); |
3726 | 4130 | ||
3727 | intel_update_watermarks(crtc); |
- | |
Line 3728... | Line 4131... | ||
3728 | intel_enable_pipe(dev_priv, pipe, |
4131 | intel_update_watermarks(crtc); |
3729 | intel_crtc->config.has_pch_encoder, false); |
4132 | intel_enable_pipe(intel_crtc); |
Line -... | Line 4133... | ||
- | 4133 | ||
- | 4134 | if (intel_crtc->config.has_pch_encoder) |
|
- | 4135 | lpt_pch_enable(crtc); |
|
3730 | 4136 | ||
3731 | if (intel_crtc->config.has_pch_encoder) |
4137 | if (intel_crtc->config.dp_encoder_is_mst) |
3732 | lpt_pch_enable(crtc); |
4138 | intel_ddi_set_vc_payload_alloc(crtc, true); |
3733 | 4139 | ||
Line 3734... | Line 4140... | ||
3734 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4140 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3735 | encoder->enable(encoder); |
4141 | encoder->enable(encoder); |
3736 | intel_opregion_notify_encoder(encoder, true); |
4142 | intel_opregion_notify_encoder(encoder, true); |
3737 | } |
4143 | } |
3738 | - | ||
3739 | /* If we change the relative order between pipe/planes enabling, we need |
- | |
3740 | * to change the workaround. */ |
- | |
3741 | haswell_mode_set_planes_workaround(intel_crtc); |
- | |
3742 | haswell_crtc_enable_planes(crtc); |
- | |
3743 | - | ||
3744 | /* |
- | |
3745 | * There seems to be a race in PCH platform hw (at least on some |
- | |
3746 | * outputs) where an enabled pipe still completes any pageflip right |
- | |
3747 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
- | |
3748 | * as the first vblank happend, everything works as expected. Hence just |
4144 | |
Line 3749... | Line 4145... | ||
3749 | * wait for one vblank before returning to avoid strange things |
4145 | /* If we change the relative order between pipe/planes enabling, we need |
3750 | * happening. |
4146 | * to change the workaround. */ |
3751 | */ |
4147 | haswell_mode_set_planes_workaround(intel_crtc); |
Line 3772... | Line 4168... | ||
3772 | struct drm_device *dev = crtc->dev; |
4168 | struct drm_device *dev = crtc->dev; |
3773 | struct drm_i915_private *dev_priv = dev->dev_private; |
4169 | struct drm_i915_private *dev_priv = dev->dev_private; |
3774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3775 | struct intel_encoder *encoder; |
4171 | struct intel_encoder *encoder; |
3776 | int pipe = intel_crtc->pipe; |
4172 | int pipe = intel_crtc->pipe; |
3777 | int plane = intel_crtc->plane; |
- | |
3778 | u32 reg, temp; |
4173 | u32 reg, temp; |
Line 3779... | Line -... | ||
3779 | - | ||
3780 | 4174 | ||
3781 | if (!intel_crtc->active) |
4175 | if (!intel_crtc->active) |
Line -... | Line 4176... | ||
- | 4176 | return; |
|
- | 4177 | ||
3782 | return; |
4178 | intel_crtc_disable_planes(crtc); |
3783 | 4179 | ||
Line 3784... | Line -... | ||
3784 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
3785 | encoder->disable(encoder); |
- | |
3786 | - | ||
3787 | // intel_crtc_wait_for_pending_flips(crtc); |
- | |
3788 | // drm_vblank_off(dev, pipe); |
- | |
3789 | - | ||
3790 | if (dev_priv->fbc.plane == plane) |
- | |
3791 | intel_disable_fbc(dev); |
- | |
3792 | - | ||
3793 | intel_crtc_update_cursor(crtc, false); |
- | |
3794 | intel_disable_planes(crtc); |
4180 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3795 | intel_disable_primary_plane(dev_priv, plane, pipe); |
4181 | encoder->disable(encoder); |
Line 3796... | Line 4182... | ||
3796 | 4182 | ||
Line -... | Line 4183... | ||
- | 4183 | if (intel_crtc->config.has_pch_encoder) |
|
- | 4184 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
|
- | 4185 | ||
3797 | if (intel_crtc->config.has_pch_encoder) |
4186 | intel_disable_pipe(dev_priv, pipe); |
Line 3798... | Line 4187... | ||
3798 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
4187 | |
3799 | 4188 | if (intel_crtc->config.dp_encoder_is_mst) |
|
3800 | intel_disable_pipe(dev_priv, pipe); |
4189 | intel_ddi_set_vc_payload_alloc(crtc, false); |
Line 3850... | Line 4239... | ||
3850 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4239 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Line 3851... | Line 4240... | ||
3851 | 4240 | ||
3852 | if (!intel_crtc->active) |
4241 | if (!intel_crtc->active) |
Line 3853... | Line 4242... | ||
3853 | return; |
4242 | return; |
Line 3854... | Line 4243... | ||
3854 | 4243 | ||
3855 | haswell_crtc_disable_planes(crtc); |
4244 | intel_crtc_disable_planes(crtc); |
3856 | 4245 | ||
3857 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4246 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Line 3867... | Line 4256... | ||
3867 | 4256 | ||
Line 3868... | Line 4257... | ||
3868 | ironlake_pfit_disable(intel_crtc); |
4257 | ironlake_pfit_disable(intel_crtc); |
Line 3869... | Line -... | ||
3869 | - | ||
3870 | intel_ddi_disable_pipe_clock(intel_crtc); |
- | |
3871 | - | ||
3872 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
3873 | if (encoder->post_disable) |
4258 | |
3874 | encoder->post_disable(encoder); |
4259 | intel_ddi_disable_pipe_clock(intel_crtc); |
3875 | 4260 | ||
3876 | if (intel_crtc->config.has_pch_encoder) { |
4261 | if (intel_crtc->config.has_pch_encoder) { |
3877 | lpt_disable_pch_transcoder(dev_priv); |
4262 | lpt_disable_pch_transcoder(dev_priv); |
Line -... | Line 4263... | ||
- | 4263 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
|
- | 4264 | intel_ddi_fdi_disable(crtc); |
|
- | 4265 | } |
|
- | 4266 | ||
3878 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
4267 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3879 | intel_ddi_fdi_disable(crtc); |
4268 | if (encoder->post_disable) |
Line 3880... | Line 4269... | ||
3880 | } |
4269 | encoder->post_disable(encoder); |
3881 | 4270 | ||
3882 | intel_crtc->active = false; |
4271 | intel_crtc->active = false; |
- | 4272 | intel_update_watermarks(crtc); |
|
- | 4273 | ||
- | 4274 | mutex_lock(&dev->struct_mutex); |
|
3883 | intel_update_watermarks(crtc); |
4275 | intel_update_fbc(dev); |
Line 3884... | Line 4276... | ||
3884 | 4276 | mutex_unlock(&dev->struct_mutex); |
|
3885 | mutex_lock(&dev->struct_mutex); |
4277 | |
3886 | intel_update_fbc(dev); |
4278 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
3887 | mutex_unlock(&dev->struct_mutex); |
4279 | intel_disable_shared_dpll(intel_crtc); |
3888 | } |
4280 | } |
Line 3889... | Line -... | ||
3889 | - | ||
3890 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
- | |
3891 | { |
- | |
3892 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3893 | intel_put_shared_dpll(intel_crtc); |
- | |
3894 | } |
- | |
3895 | - | ||
3896 | static void haswell_crtc_off(struct drm_crtc *crtc) |
- | |
3897 | { |
- | |
3898 | intel_ddi_put_crtc_pll(crtc); |
- | |
3899 | } |
- | |
3900 | - | ||
3901 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
- | |
3902 | { |
- | |
3903 | if (!enable && intel_crtc->overlay) { |
- | |
3904 | struct drm_device *dev = intel_crtc->base.dev; |
- | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3906 | - | ||
3907 | mutex_lock(&dev->struct_mutex); |
- | |
3908 | dev_priv->mm.interruptible = false; |
- | |
3909 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
- | |
3910 | dev_priv->mm.interruptible = true; |
- | |
3911 | mutex_unlock(&dev->struct_mutex); |
- | |
3912 | } |
- | |
3913 | - | ||
3914 | /* Let userspace switch the overlay on again. In most cases userspace |
- | |
3915 | * has to recompute where to put it anyway. |
- | |
3916 | */ |
- | |
3917 | } |
- | |
3918 | - | ||
3919 | /** |
- | |
3920 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
- | |
3921 | * cursor plane briefly if not already running after enabling the display |
- | |
3922 | * plane. |
- | |
3923 | * This workaround avoids occasional blank screens when self refresh is |
- | |
3924 | * enabled. |
- | |
3925 | */ |
- | |
3926 | static void |
- | |
3927 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
- | |
3928 | { |
- | |
3929 | u32 cntl = I915_READ(CURCNTR(pipe)); |
- | |
3930 | - | ||
3931 | if ((cntl & CURSOR_MODE) == 0) { |
- | |
3932 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
- | |
3933 | - | ||
3934 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
- | |
Line 3935... | Line 4281... | ||
3935 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
4281 | |
3936 | intel_wait_for_vblank(dev_priv->dev, pipe); |
4282 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3937 | I915_WRITE(CURCNTR(pipe), cntl); |
4283 | { |
3938 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
4284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 3962... | Line 4308... | ||
3962 | /* Border color in case we don't scale up to the full screen. Black by |
4308 | /* Border color in case we don't scale up to the full screen. Black by |
3963 | * default, change to something else for debugging. */ |
4309 | * default, change to something else for debugging. */ |
3964 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
4310 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3965 | } |
4311 | } |
Line -... | Line 4312... | ||
- | 4312 | ||
- | 4313 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
|
- | 4314 | { |
|
- | 4315 | switch (port) { |
|
- | 4316 | case PORT_A: |
|
- | 4317 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
|
- | 4318 | case PORT_B: |
|
- | 4319 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
|
- | 4320 | case PORT_C: |
|
- | 4321 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
|
- | 4322 | case PORT_D: |
|
- | 4323 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
|
- | 4324 | default: |
|
- | 4325 | WARN_ON_ONCE(1); |
|
- | 4326 | return POWER_DOMAIN_PORT_OTHER; |
|
- | 4327 | } |
|
- | 4328 | } |
|
- | 4329 | ||
- | 4330 | #define for_each_power_domain(domain, mask) \ |
|
- | 4331 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
|
- | 4332 | if ((1 << (domain)) & (mask)) |
|
- | 4333 | ||
- | 4334 | enum intel_display_power_domain |
|
- | 4335 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
|
- | 4336 | { |
|
- | 4337 | struct drm_device *dev = intel_encoder->base.dev; |
|
- | 4338 | struct intel_digital_port *intel_dig_port; |
|
- | 4339 | ||
- | 4340 | switch (intel_encoder->type) { |
|
- | 4341 | case INTEL_OUTPUT_UNKNOWN: |
|
- | 4342 | /* Only DDI platforms should ever use this output type */ |
|
- | 4343 | WARN_ON_ONCE(!HAS_DDI(dev)); |
|
- | 4344 | case INTEL_OUTPUT_DISPLAYPORT: |
|
- | 4345 | case INTEL_OUTPUT_HDMI: |
|
- | 4346 | case INTEL_OUTPUT_EDP: |
|
- | 4347 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
|
- | 4348 | return port_to_power_domain(intel_dig_port->port); |
|
- | 4349 | case INTEL_OUTPUT_DP_MST: |
|
- | 4350 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
|
- | 4351 | return port_to_power_domain(intel_dig_port->port); |
|
- | 4352 | case INTEL_OUTPUT_ANALOG: |
|
- | 4353 | return POWER_DOMAIN_PORT_CRT; |
|
- | 4354 | case INTEL_OUTPUT_DSI: |
|
- | 4355 | return POWER_DOMAIN_PORT_DSI; |
|
- | 4356 | default: |
|
- | 4357 | return POWER_DOMAIN_PORT_OTHER; |
|
- | 4358 | } |
|
- | 4359 | } |
|
- | 4360 | ||
- | 4361 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
|
- | 4362 | { |
|
- | 4363 | struct drm_device *dev = crtc->dev; |
|
- | 4364 | struct intel_encoder *intel_encoder; |
|
- | 4365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 4366 | enum pipe pipe = intel_crtc->pipe; |
|
- | 4367 | unsigned long mask; |
|
- | 4368 | enum transcoder transcoder; |
|
- | 4369 | ||
- | 4370 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
|
- | 4371 | ||
- | 4372 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
|
- | 4373 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
|
- | 4374 | if (intel_crtc->config.pch_pfit.enabled || |
|
- | 4375 | intel_crtc->config.pch_pfit.force_thru) |
|
- | 4376 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
|
- | 4377 | ||
- | 4378 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
|
- | 4379 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
|
- | 4380 | ||
- | 4381 | return mask; |
|
- | 4382 | } |
|
- | 4383 | ||
- | 4384 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
|
- | 4385 | bool enable) |
|
- | 4386 | { |
|
- | 4387 | if (dev_priv->power_domains.init_power_on == enable) |
|
- | 4388 | return; |
|
- | 4389 | ||
- | 4390 | if (enable) |
|
- | 4391 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
|
- | 4392 | else |
|
- | 4393 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
|
- | 4394 | ||
- | 4395 | dev_priv->power_domains.init_power_on = enable; |
|
- | 4396 | } |
|
- | 4397 | ||
- | 4398 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
|
- | 4399 | { |
|
- | 4400 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4401 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
|
- | 4402 | struct intel_crtc *crtc; |
|
- | 4403 | ||
- | 4404 | /* |
|
- | 4405 | * First get all needed power domains, then put all unneeded, to avoid |
|
- | 4406 | * any unnecessary toggling of the power wells. |
|
- | 4407 | */ |
|
- | 4408 | for_each_intel_crtc(dev, crtc) { |
|
- | 4409 | enum intel_display_power_domain domain; |
|
- | 4410 | ||
- | 4411 | if (!crtc->base.enabled) |
|
- | 4412 | continue; |
|
- | 4413 | ||
- | 4414 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
|
- | 4415 | ||
- | 4416 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
|
- | 4417 | intel_display_power_get(dev_priv, domain); |
|
- | 4418 | } |
|
- | 4419 | ||
- | 4420 | for_each_intel_crtc(dev, crtc) { |
|
- | 4421 | enum intel_display_power_domain domain; |
|
- | 4422 | ||
- | 4423 | for_each_power_domain(domain, crtc->enabled_power_domains) |
|
- | 4424 | intel_display_power_put(dev_priv, domain); |
|
- | 4425 | ||
- | 4426 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
|
- | 4427 | } |
|
- | 4428 | ||
- | 4429 | intel_display_set_init_power(dev_priv, false); |
|
- | 4430 | } |
|
- | 4431 | ||
3966 | 4432 | /* returns HPLL frequency in kHz */ |
|
3967 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
4433 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
3968 | { |
4434 | { |
Line 3969... | Line 4435... | ||
3969 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
4435 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
3970 | 4436 | ||
3971 | /* Obtain SKU information */ |
4437 | /* Obtain SKU information */ |
3972 | mutex_lock(&dev_priv->dpio_lock); |
4438 | mutex_lock(&dev_priv->dpio_lock); |
3973 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
4439 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
Line 3974... | Line 4440... | ||
3974 | CCK_FUSE_HPLL_FREQ_MASK; |
4440 | CCK_FUSE_HPLL_FREQ_MASK; |
- | 4441 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 4442 | ||
- | 4443 | return vco_freq[hpll_freq] * 1000; |
|
- | 4444 | } |
|
- | 4445 | ||
- | 4446 | static void vlv_update_cdclk(struct drm_device *dev) |
|
- | 4447 | { |
|
- | 4448 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4449 | ||
- | 4450 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
|
- | 4451 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", |
|
- | 4452 | dev_priv->vlv_cdclk_freq); |
|
- | 4453 | ||
- | 4454 | /* |
|
- | 4455 | * Program the gmbus_freq based on the cdclk frequency. |
|
- | 4456 | * BSpec erroneously claims we should aim for 4MHz, but |
|
3975 | mutex_unlock(&dev_priv->dpio_lock); |
4457 | * in fact 1MHz is the correct frequency. |
Line 3976... | Line 4458... | ||
3976 | 4458 | */ |
|
3977 | return vco_freq[hpll_freq]; |
4459 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); |
3978 | } |
4460 | } |
3979 | 4461 | ||
3980 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4462 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
Line -... | Line 4463... | ||
- | 4463 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
|
- | 4464 | { |
|
3981 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
4465 | struct drm_i915_private *dev_priv = dev->dev_private; |
3982 | { |
4466 | u32 val, cmd; |
3983 | struct drm_i915_private *dev_priv = dev->dev_private; |
4467 | |
3984 | u32 val, cmd; |
4468 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
3985 | 4469 | ||
3986 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4470 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
Line 3987... | Line 4471... | ||
3987 | cmd = 2; |
4471 | cmd = 2; |
Line 4000... | Line 4484... | ||
4000 | 50)) { |
4484 | 50)) { |
4001 | DRM_ERROR("timed out waiting for CDclk change\n"); |
4485 | DRM_ERROR("timed out waiting for CDclk change\n"); |
4002 | } |
4486 | } |
4003 | mutex_unlock(&dev_priv->rps.hw_lock); |
4487 | mutex_unlock(&dev_priv->rps.hw_lock); |
Line 4004... | Line 4488... | ||
4004 | 4488 | ||
4005 | if (cdclk == 400) { |
4489 | if (cdclk == 400000) { |
Line 4006... | Line 4490... | ||
4006 | u32 divider, vco; |
4490 | u32 divider, vco; |
4007 | 4491 | ||
Line 4008... | Line 4492... | ||
4008 | vco = valleyview_get_vco(dev_priv); |
4492 | vco = valleyview_get_vco(dev_priv); |
4009 | divider = ((vco << 1) / cdclk) - 1; |
4493 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
4010 | 4494 | ||
4011 | mutex_lock(&dev_priv->dpio_lock); |
4495 | mutex_lock(&dev_priv->dpio_lock); |
4012 | /* adjust cdclk divider */ |
4496 | /* adjust cdclk divider */ |
4013 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
4497 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
- | 4498 | val &= ~DISPLAY_FREQUENCY_VALUES; |
|
- | 4499 | val |= divider; |
|
- | 4500 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
|
- | 4501 | ||
- | 4502 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
|
4014 | val &= ~0xf; |
4503 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
4015 | val |= divider; |
4504 | 50)) |
Line 4016... | Line 4505... | ||
4016 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
4505 | DRM_ERROR("timed out waiting for CDclk change\n"); |
4017 | mutex_unlock(&dev_priv->dpio_lock); |
4506 | mutex_unlock(&dev_priv->dpio_lock); |
Line 4024... | Line 4513... | ||
4024 | 4513 | ||
4025 | /* |
4514 | /* |
4026 | * For high bandwidth configs, we set a higher latency in the bunit |
4515 | * For high bandwidth configs, we set a higher latency in the bunit |
4027 | * so that the core display fetch happens in time to avoid underruns. |
4516 | * so that the core display fetch happens in time to avoid underruns. |
4028 | */ |
4517 | */ |
4029 | if (cdclk == 400) |
4518 | if (cdclk == 400000) |
4030 | val |= 4500 / 250; /* 4.5 usec */ |
4519 | val |= 4500 / 250; /* 4.5 usec */ |
4031 | else |
4520 | else |
4032 | val |= 3000 / 250; /* 3.0 usec */ |
4521 | val |= 3000 / 250; /* 3.0 usec */ |
4033 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
4522 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
Line 4034... | Line -... | ||
4034 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
4035 | 4523 | mutex_unlock(&dev_priv->dpio_lock); |
|
4036 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ |
- | |
4037 | intel_i2c_reset(dev); |
- | |
4038 | } |
- | |
4039 | - | ||
4040 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
- | |
4041 | { |
- | |
4042 | int cur_cdclk, vco; |
- | |
4043 | int divider; |
- | |
4044 | - | ||
4045 | vco = valleyview_get_vco(dev_priv); |
- | |
4046 | - | ||
4047 | mutex_lock(&dev_priv->dpio_lock); |
- | |
4048 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
- | |
4049 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
4050 | - | ||
4051 | divider &= 0xf; |
- | |
4052 | - | ||
4053 | cur_cdclk = (vco << 1) / (divider + 1); |
- | |
4054 | 4524 | ||
Line 4055... | Line 4525... | ||
4055 | return cur_cdclk; |
4525 | vlv_update_cdclk(dev); |
4056 | } |
4526 | } |
4057 | 4527 | ||
4058 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
- | |
4059 | int max_pixclk) |
- | |
4060 | { |
4528 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
- | 4529 | int max_pixclk) |
|
Line 4061... | Line 4530... | ||
4061 | int cur_cdclk; |
4530 | { |
4062 | 4531 | int vco = valleyview_get_vco(dev_priv); |
|
4063 | cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4532 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; |
4064 | 4533 | ||
4065 | /* |
4534 | /* |
4066 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
4535 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
4067 | * 200MHz |
4536 | * 200MHz |
4068 | * 267MHz |
4537 | * 267MHz |
- | 4538 | * 320/333MHz (depends on HPLL freq) |
|
- | 4539 | * 400MHz |
|
- | 4540 | * So we check to see whether we're above 90% of the lower bin and |
|
- | 4541 | * adjust if needed. |
|
4069 | * 320MHz |
4542 | * |
4070 | * 400MHz |
4543 | * We seem to get an unstable or solid color picture at 200MHz. |
4071 | * So we check to see whether we're above 90% of the lower bin and |
4544 | * Not sure what's wrong. For now use 200MHz only when all pipes |
4072 | * adjust if needed. |
4545 | * are off. |
4073 | */ |
4546 | */ |
- | 4547 | if (max_pixclk > freq_320*9/10) |
|
- | 4548 | return 400000; |
|
4074 | if (max_pixclk > 288000) { |
4549 | else if (max_pixclk > 266667*9/10) |
4075 | return 400; |
4550 | return freq_320; |
4076 | } else if (max_pixclk > 240000) { |
- | |
4077 | return 320; |
4551 | else if (max_pixclk > 0) |
Line -... | Line 4552... | ||
- | 4552 | return 266667; |
|
4078 | } else |
4553 | else |
4079 | return 266; |
- | |
4080 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
- | |
4081 | } |
4554 | return 200000; |
4082 | 4555 | } |
|
4083 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, |
4556 | |
4084 | unsigned modeset_pipes, |
4557 | /* compute the max pixel clock for new configuration */ |
Line 4085... | Line 4558... | ||
4085 | struct intel_crtc_config *pipe_config) |
4558 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
4086 | { |
- | |
4087 | struct drm_device *dev = dev_priv->dev; |
- | |
4088 | struct intel_crtc *intel_crtc; |
- | |
4089 | int max_pixclk = 0; |
- | |
4090 | 4559 | { |
|
4091 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4560 | struct drm_device *dev = dev_priv->dev; |
4092 | base.head) { |
4561 | struct intel_crtc *intel_crtc; |
4093 | if (modeset_pipes & (1 << intel_crtc->pipe)) |
4562 | int max_pixclk = 0; |
Line 4094... | Line 4563... | ||
4094 | max_pixclk = max(max_pixclk, |
4563 | |
4095 | pipe_config->adjusted_mode.crtc_clock); |
4564 | for_each_intel_crtc(dev, intel_crtc) { |
Line 4096... | Line 4565... | ||
4096 | else if (intel_crtc->base.enabled) |
4565 | if (intel_crtc->new_enabled) |
4097 | max_pixclk = max(max_pixclk, |
4566 | max_pixclk = max(max_pixclk, |
4098 | intel_crtc->config.adjusted_mode.crtc_clock); |
- | |
4099 | } |
- | |
4100 | 4567 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
|
4101 | return max_pixclk; |
4568 | } |
4102 | } |
4569 | |
4103 | 4570 | return max_pixclk; |
|
4104 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
- | |
4105 | unsigned *prepare_pipes, |
- | |
Line 4106... | Line 4571... | ||
4106 | unsigned modeset_pipes, |
4571 | } |
- | 4572 | ||
4107 | struct intel_crtc_config *pipe_config) |
4573 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
Line 4108... | Line 4574... | ||
4108 | { |
4574 | unsigned *prepare_pipes) |
4109 | struct drm_i915_private *dev_priv = dev->dev_private; |
4575 | { |
4110 | struct intel_crtc *intel_crtc; |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; |
4111 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, |
4577 | struct intel_crtc *intel_crtc; |
4112 | pipe_config); |
4578 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
Line 4113... | Line 4579... | ||
4113 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4579 | |
4114 | 4580 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
|
4115 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) |
4581 | dev_priv->vlv_cdclk_freq) |
4116 | return; |
4582 | return; |
4117 | - | ||
4118 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4583 | |
Line 4119... | Line 4584... | ||
4119 | base.head) |
4584 | /* disable/enable all currently active pipes while we change cdclk */ |
4120 | if (intel_crtc->base.enabled) |
4585 | for_each_intel_crtc(dev, intel_crtc) |
- | 4586 | if (intel_crtc->base.enabled) |
|
4121 | *prepare_pipes |= (1 << intel_crtc->pipe); |
4587 | *prepare_pipes |= (1 << intel_crtc->pipe); |
Line 4122... | Line 4588... | ||
4122 | } |
4588 | } |
4123 | 4589 | ||
4124 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
4590 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
Line 4139... | Line 4605... | ||
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4140 | struct intel_encoder *encoder; |
4606 | struct intel_encoder *encoder; |
4141 | int pipe = intel_crtc->pipe; |
4607 | int pipe = intel_crtc->pipe; |
4142 | int plane = intel_crtc->plane; |
4608 | int plane = intel_crtc->plane; |
4143 | bool is_dsi; |
4609 | bool is_dsi; |
- | 4610 | u32 dspcntr; |
|
Line 4144... | Line 4611... | ||
4144 | 4611 | ||
Line 4145... | Line 4612... | ||
4145 | WARN_ON(!crtc->enabled); |
4612 | WARN_ON(!crtc->enabled); |
4146 | 4613 | ||
Line -... | Line 4614... | ||
- | 4614 | if (intel_crtc->active) |
|
- | 4615 | return; |
|
- | 4616 | ||
- | 4617 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
|
- | 4618 | ||
- | 4619 | if (!is_dsi && !IS_CHERRYVIEW(dev)) |
|
- | 4620 | vlv_prepare_pll(intel_crtc); |
|
- | 4621 | ||
- | 4622 | /* Set up the display plane register */ |
|
- | 4623 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
|
- | 4624 | ||
- | 4625 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4626 | intel_dp_set_m_n(intel_crtc); |
|
- | 4627 | ||
- | 4628 | intel_set_pipe_timings(intel_crtc); |
|
- | 4629 | ||
- | 4630 | /* pipesrc and dspsize control the size that is scaled from, |
|
- | 4631 | * which should always be the user's requested size. |
|
- | 4632 | */ |
|
- | 4633 | I915_WRITE(DSPSIZE(plane), |
|
- | 4634 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
|
- | 4635 | (intel_crtc->config.pipe_src_w - 1)); |
|
- | 4636 | I915_WRITE(DSPPOS(plane), 0); |
|
- | 4637 | ||
- | 4638 | i9xx_set_pipeconf(intel_crtc); |
|
- | 4639 | ||
- | 4640 | I915_WRITE(DSPCNTR(plane), dspcntr); |
|
- | 4641 | POSTING_READ(DSPCNTR(plane)); |
|
- | 4642 | ||
4147 | if (intel_crtc->active) |
4643 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, |
Line -... | Line 4644... | ||
- | 4644 | crtc->x, crtc->y); |
|
- | 4645 | ||
4148 | return; |
4646 | intel_crtc->active = true; |
4149 | 4647 | ||
4150 | intel_crtc->active = true; |
4648 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
Line 4151... | Line -... | ||
4151 | - | ||
4152 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
4153 | if (encoder->pre_pll_enable) |
4649 | |
- | 4650 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 4651 | if (encoder->pre_pll_enable) |
|
- | 4652 | encoder->pre_pll_enable(encoder); |
|
4154 | encoder->pre_pll_enable(encoder); |
4653 | |
- | 4654 | if (!is_dsi) { |
|
Line 4155... | Line 4655... | ||
4155 | 4655 | if (IS_CHERRYVIEW(dev)) |
|
4156 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4656 | chv_enable_pll(intel_crtc); |
4157 | 4657 | else |
|
Line 4158... | Line 4658... | ||
4158 | if (!is_dsi) |
4658 | vlv_enable_pll(intel_crtc); |
Line 4159... | Line 4659... | ||
4159 | vlv_enable_pll(intel_crtc); |
4659 | } |
Line 4160... | Line 4660... | ||
4160 | 4660 | ||
4161 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
4162 | if (encoder->pre_enable) |
- | |
4163 | encoder->pre_enable(encoder); |
4661 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4164 | - | ||
4165 | i9xx_pfit_enable(intel_crtc); |
- | |
4166 | - | ||
Line 4167... | Line 4662... | ||
4167 | intel_crtc_load_lut(crtc); |
4662 | if (encoder->pre_enable) |
4168 | 4663 | encoder->pre_enable(encoder); |
|
- | 4664 | ||
- | 4665 | i9xx_pfit_enable(intel_crtc); |
|
- | 4666 | ||
- | 4667 | intel_crtc_load_lut(crtc); |
|
- | 4668 | ||
- | 4669 | intel_update_watermarks(crtc); |
|
- | 4670 | intel_enable_pipe(intel_crtc); |
|
- | 4671 | ||
- | 4672 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 4673 | encoder->enable(encoder); |
|
- | 4674 | ||
- | 4675 | intel_crtc_enable_planes(crtc); |
|
- | 4676 | ||
- | 4677 | /* Underruns don't raise interrupts, so check manually. */ |
|
4169 | intel_update_watermarks(crtc); |
4678 | i9xx_check_fifo_underruns(dev); |
Line 4170... | Line 4679... | ||
4170 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
4679 | } |
4171 | intel_enable_primary_plane(dev_priv, plane, pipe); |
4680 | |
4172 | intel_enable_planes(crtc); |
4681 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4173 | intel_crtc_update_cursor(crtc, true); |
4682 | { |
4174 | 4683 | struct drm_device *dev = crtc->base.dev; |
|
4175 | intel_update_fbc(dev); |
4684 | struct drm_i915_private *dev_priv = dev->dev_private; |
4176 | 4685 | ||
4177 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4686 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); |
- | 4687 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); |
|
Line 4178... | Line 4688... | ||
4178 | encoder->enable(encoder); |
4688 | } |
Line 4179... | Line 4689... | ||
4179 | } |
4689 | |
4180 | 4690 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
|
Line -... | Line 4691... | ||
- | 4691 | { |
|
- | 4692 | struct drm_device *dev = crtc->dev; |
|
- | 4693 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 4695 | struct intel_encoder *encoder; |
|
- | 4696 | int pipe = intel_crtc->pipe; |
|
- | 4697 | int plane = intel_crtc->plane; |
|
- | 4698 | u32 dspcntr; |
|
- | 4699 | ||
- | 4700 | WARN_ON(!crtc->enabled); |
|
- | 4701 | ||
- | 4702 | if (intel_crtc->active) |
|
- | 4703 | return; |
|
- | 4704 | ||
- | 4705 | i9xx_set_pll_dividers(intel_crtc); |
|
- | 4706 | ||
- | 4707 | /* Set up the display plane register */ |
|
- | 4708 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
|
- | 4709 | ||
- | 4710 | if (pipe == 0) |
|
- | 4711 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
|
- | 4712 | else |
|
- | 4713 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
|
- | 4714 | ||
- | 4715 | if (intel_crtc->config.has_dp_encoder) |
|
- | 4716 | intel_dp_set_m_n(intel_crtc); |
|
- | 4717 | ||
- | 4718 | intel_set_pipe_timings(intel_crtc); |
|
- | 4719 | ||
- | 4720 | /* pipesrc and dspsize control the size that is scaled from, |
|
- | 4721 | * which should always be the user's requested size. |
|
4181 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
4722 | */ |
Line -... | Line 4723... | ||
- | 4723 | I915_WRITE(DSPSIZE(plane), |
|
- | 4724 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
|
- | 4725 | (intel_crtc->config.pipe_src_w - 1)); |
|
4182 | { |
4726 | I915_WRITE(DSPPOS(plane), 0); |
4183 | struct drm_device *dev = crtc->dev; |
4727 | |
4184 | struct drm_i915_private *dev_priv = dev->dev_private; |
4728 | i9xx_set_pipeconf(intel_crtc); |
Line 4185... | Line 4729... | ||
4185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4729 | |
Line 4203... | Line 4747... | ||
4203 | i9xx_pfit_enable(intel_crtc); |
4747 | i9xx_pfit_enable(intel_crtc); |
Line 4204... | Line 4748... | ||
4204 | 4748 | ||
Line 4205... | Line 4749... | ||
4205 | intel_crtc_load_lut(crtc); |
4749 | intel_crtc_load_lut(crtc); |
4206 | - | ||
4207 | intel_update_watermarks(crtc); |
- | |
4208 | intel_enable_pipe(dev_priv, pipe, false, false); |
4750 | |
4209 | intel_enable_primary_plane(dev_priv, plane, pipe); |
- | |
4210 | intel_enable_planes(crtc); |
- | |
4211 | /* The fixup needs to happen before cursor is enabled */ |
- | |
4212 | if (IS_G4X(dev)) |
- | |
4213 | g4x_fixup_plane(dev_priv, pipe); |
- | |
4214 | intel_crtc_update_cursor(crtc, true); |
- | |
4215 | - | ||
4216 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
- | |
4217 | intel_crtc_dpms_overlay(intel_crtc, true); |
- | |
Line 4218... | Line 4751... | ||
4218 | 4751 | intel_update_watermarks(crtc); |
|
4219 | intel_update_fbc(dev); |
4752 | intel_enable_pipe(intel_crtc); |
- | 4753 | ||
- | 4754 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 4755 | encoder->enable(encoder); |
|
- | 4756 | ||
- | 4757 | intel_crtc_enable_planes(crtc); |
|
- | 4758 | ||
- | 4759 | /* |
|
- | 4760 | * Gen2 reports pipe underruns whenever all planes are disabled. |
|
- | 4761 | * So don't enable underrun reporting before at least some planes |
|
- | 4762 | * are enabled. |
|
- | 4763 | * FIXME: Need to fix the logic to work when we turn off all planes |
|
- | 4764 | * but leave the pipe running. |
|
- | 4765 | */ |
|
- | 4766 | if (IS_GEN2(dev)) |
|
- | 4767 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
|
4220 | 4768 | ||
Line 4221... | Line 4769... | ||
4221 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4769 | /* Underruns don't raise interrupts, so check manually. */ |
4222 | encoder->enable(encoder); |
4770 | i9xx_check_fifo_underruns(dev); |
4223 | } |
4771 | } |
Line 4242... | Line 4790... | ||
4242 | struct drm_device *dev = crtc->dev; |
4790 | struct drm_device *dev = crtc->dev; |
4243 | struct drm_i915_private *dev_priv = dev->dev_private; |
4791 | struct drm_i915_private *dev_priv = dev->dev_private; |
4244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4245 | struct intel_encoder *encoder; |
4793 | struct intel_encoder *encoder; |
4246 | int pipe = intel_crtc->pipe; |
4794 | int pipe = intel_crtc->pipe; |
4247 | int plane = intel_crtc->plane; |
- | |
Line 4248... | Line 4795... | ||
4248 | 4795 | ||
4249 | if (!intel_crtc->active) |
4796 | if (!intel_crtc->active) |
Line -... | Line 4797... | ||
- | 4797 | return; |
|
- | 4798 | ||
4250 | return; |
4799 | /* |
- | 4800 | * Gen2 reports pipe underruns whenever all planes are disabled. |
|
4251 | 4801 | * So diasble underrun reporting before all the planes get disabled. |
|
- | 4802 | * FIXME: Need to fix the logic to work when we turn off all planes |
|
- | 4803 | * but leave the pipe running. |
|
- | 4804 | */ |
|
Line -... | Line 4805... | ||
- | 4805 | if (IS_GEN2(dev)) |
|
- | 4806 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
|
- | 4807 | ||
- | 4808 | /* |
|
- | 4809 | * Vblank time updates from the shadow to live plane control register |
|
- | 4810 | * are blocked if the memory self-refresh mode is active at that |
|
- | 4811 | * moment. So to make sure the plane gets truly disabled, disable |
|
4252 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4812 | * first the self-refresh mode. The self-refresh enable bit in turn |
- | 4813 | * will be checked/applied by the HW only at the next frame start |
|
4253 | encoder->disable(encoder); |
4814 | * event which is after the vblank start event, so we need to have a |
4254 | 4815 | * wait-for-vblank between disabling the plane and the pipe. |
|
Line 4255... | Line 4816... | ||
4255 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
4816 | */ |
4256 | // intel_crtc_wait_for_pending_flips(crtc); |
4817 | intel_set_memory_cxsr(dev_priv, false); |
Line -... | Line 4818... | ||
- | 4818 | intel_crtc_disable_planes(crtc); |
|
- | 4819 | ||
4257 | // drm_vblank_off(dev, pipe); |
4820 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4258 | 4821 | encoder->disable(encoder); |
|
4259 | if (dev_priv->fbc.plane == plane) |
4822 | |
- | 4823 | /* |
|
4260 | intel_disable_fbc(dev); |
4824 | * On gen2 planes are double buffered but the pipe isn't, so we must |
Line 4261... | Line 4825... | ||
4261 | 4825 | * wait for planes to fully turn off before disabling the pipe. |
|
Line 4262... | Line 4826... | ||
4262 | intel_crtc_dpms_overlay(intel_crtc, false); |
4826 | * We also need to wait on all gmch platforms because of the |
Line 4263... | Line 4827... | ||
4263 | intel_crtc_update_cursor(crtc, false); |
4827 | * self-refresh mode constraint explained above. |
4264 | intel_disable_planes(crtc); |
4828 | */ |
4265 | intel_disable_primary_plane(dev_priv, plane, pipe); |
4829 | intel_wait_for_vblank(dev, pipe); |
Line 4266... | Line 4830... | ||
4266 | 4830 | ||
- | 4831 | intel_disable_pipe(dev_priv, pipe); |
|
- | 4832 | ||
- | 4833 | i9xx_pfit_disable(intel_crtc); |
|
4267 | intel_disable_pipe(dev_priv, pipe); |
4834 | |
4268 | 4835 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
4269 | i9xx_pfit_disable(intel_crtc); |
4836 | if (encoder->post_disable) |
- | 4837 | encoder->post_disable(encoder); |
|
- | 4838 | ||
- | 4839 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
|
- | 4840 | if (IS_CHERRYVIEW(dev)) |
|
Line 4270... | Line 4841... | ||
4270 | 4841 | chv_disable_pll(dev_priv, pipe); |
|
4271 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4842 | else if (IS_VALLEYVIEW(dev)) |
Line -... | Line 4843... | ||
- | 4843 | vlv_disable_pll(dev_priv, pipe); |
|
4272 | if (encoder->post_disable) |
4844 | else |
- | 4845 | i9xx_disable_pll(dev_priv, pipe); |
|
4273 | encoder->post_disable(encoder); |
4846 | } |
Line 4274... | Line 4847... | ||
4274 | 4847 | ||
4275 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4848 | if (!IS_GEN2(dev)) |
4276 | vlv_disable_pll(dev_priv, pipe); |
4849 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
Line 4316... | Line 4889... | ||
4316 | default: |
4889 | default: |
4317 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
4890 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
4318 | break; |
4891 | break; |
4319 | } |
4892 | } |
4320 | #endif |
4893 | #endif |
- | 4894 | } |
|
- | 4895 | ||
- | 4896 | /* Master function to enable/disable CRTC and corresponding power wells */ |
|
- | 4897 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) |
|
- | 4898 | { |
|
- | 4899 | struct drm_device *dev = crtc->dev; |
|
- | 4900 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 4902 | enum intel_display_power_domain domain; |
|
- | 4903 | unsigned long domains; |
|
- | 4904 | ||
- | 4905 | if (enable) { |
|
- | 4906 | if (!intel_crtc->active) { |
|
- | 4907 | domains = get_crtc_power_domains(crtc); |
|
- | 4908 | for_each_power_domain(domain, domains) |
|
- | 4909 | intel_display_power_get(dev_priv, domain); |
|
- | 4910 | intel_crtc->enabled_power_domains = domains; |
|
Line -... | Line 4911... | ||
- | 4911 | ||
- | 4912 | dev_priv->display.crtc_enable(crtc); |
|
- | 4913 | } |
|
- | 4914 | } else { |
|
- | 4915 | if (intel_crtc->active) { |
|
- | 4916 | dev_priv->display.crtc_disable(crtc); |
|
- | 4917 | ||
- | 4918 | domains = intel_crtc->enabled_power_domains; |
|
- | 4919 | for_each_power_domain(domain, domains) |
|
- | 4920 | intel_display_power_put(dev_priv, domain); |
|
- | 4921 | intel_crtc->enabled_power_domains = 0; |
|
- | 4922 | } |
|
4321 | 4923 | } |
|
Line 4322... | Line 4924... | ||
4322 | } |
4924 | } |
4323 | 4925 | ||
4324 | /** |
4926 | /** |
4325 | * Sets the power management mode of the pipe and plane. |
4927 | * Sets the power management mode of the pipe and plane. |
4326 | */ |
4928 | */ |
4327 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
4929 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
4328 | { |
- | |
4329 | struct drm_device *dev = crtc->dev; |
4930 | { |
4330 | struct drm_i915_private *dev_priv = dev->dev_private; |
4931 | struct drm_device *dev = crtc->dev; |
Line 4331... | Line 4932... | ||
4331 | struct intel_encoder *intel_encoder; |
4932 | struct intel_encoder *intel_encoder; |
4332 | bool enable = false; |
4933 | bool enable = false; |
Line 4333... | Line -... | ||
4333 | - | ||
4334 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4934 | |
4335 | enable |= intel_encoder->connectors_active; |
- | |
4336 | - | ||
Line 4337... | Line 4935... | ||
4337 | if (enable) |
4935 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4338 | dev_priv->display.crtc_enable(crtc); |
4936 | enable |= intel_encoder->connectors_active; |
Line 4339... | Line 4937... | ||
4339 | else |
4937 | |
4340 | dev_priv->display.crtc_disable(crtc); |
4938 | intel_crtc_control(crtc, enable); |
4341 | 4939 | ||
4342 | intel_crtc_update_sarea(crtc, enable); |
4940 | intel_crtc_update_sarea(crtc, enable); |
4343 | } |
4941 | } |
- | 4942 | ||
4344 | 4943 | static void intel_crtc_disable(struct drm_crtc *crtc) |
|
Line 4345... | Line 4944... | ||
4345 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4944 | { |
4346 | { |
4945 | struct drm_device *dev = crtc->dev; |
Line 4347... | Line 4946... | ||
4347 | struct drm_device *dev = crtc->dev; |
4946 | struct drm_connector *connector; |
4348 | struct drm_connector *connector; |
- | |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4947 | struct drm_i915_private *dev_priv = dev->dev_private; |
4350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4948 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
Line 4351... | Line -... | ||
4351 | - | ||
4352 | /* crtc should still be enabled when we disable it. */ |
- | |
4353 | WARN_ON(!crtc->enabled); |
- | |
4354 | - | ||
4355 | dev_priv->display.crtc_disable(crtc); |
4949 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
4356 | intel_crtc->eld_vld = false; |
4950 | |
4357 | intel_crtc_update_sarea(crtc, false); |
4951 | /* crtc should still be enabled when we disable it. */ |
- | 4952 | WARN_ON(!crtc->enabled); |
|
- | 4953 | ||
4358 | dev_priv->display.off(crtc); |
4954 | dev_priv->display.crtc_disable(crtc); |
4359 | 4955 | intel_crtc_update_sarea(crtc, false); |
|
4360 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
4956 | dev_priv->display.off(crtc); |
Line 4361... | Line 4957... | ||
4361 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
4957 | |
4362 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
4958 | if (crtc->primary->fb) { |
4363 | 4959 | mutex_lock(&dev->struct_mutex); |
|
Line 4415... | Line 5011... | ||
4415 | bool encoder_enabled; |
5011 | bool encoder_enabled; |
4416 | enum pipe pipe; |
5012 | enum pipe pipe; |
Line 4417... | Line 5013... | ||
4417 | 5013 | ||
4418 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5014 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4419 | connector->base.base.id, |
5015 | connector->base.base.id, |
- | 5016 | connector->base.name); |
|
- | 5017 | ||
- | 5018 | /* there is no real hw state for MST connectors */ |
|
- | 5019 | if (connector->mst_port) |
|
Line 4420... | Line 5020... | ||
4420 | drm_get_connector_name(&connector->base)); |
5020 | return; |
4421 | 5021 | ||
4422 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5022 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
4423 | "wrong connector dpms state\n"); |
5023 | "wrong connector dpms state\n"); |
- | 5024 | WARN(connector->base.encoder != &encoder->base, |
|
- | 5025 | "active connector not linked to encoder\n"); |
|
4424 | WARN(connector->base.encoder != &encoder->base, |
5026 | |
4425 | "active connector not linked to encoder\n"); |
5027 | if (encoder) { |
Line 4426... | Line 5028... | ||
4426 | WARN(!encoder->connectors_active, |
5028 | WARN(!encoder->connectors_active, |
4427 | "encoder->connectors_active not set\n"); |
5029 | "encoder->connectors_active not set\n"); |
Line 4437... | Line 5039... | ||
4437 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5039 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
4438 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
5040 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
4439 | "encoder active on the wrong pipe\n"); |
5041 | "encoder active on the wrong pipe\n"); |
4440 | } |
5042 | } |
4441 | } |
5043 | } |
- | 5044 | } |
|
Line 4442... | Line 5045... | ||
4442 | 5045 | ||
4443 | /* Even simpler default implementation, if there's really no special case to |
5046 | /* Even simpler default implementation, if there's really no special case to |
4444 | * consider. */ |
5047 | * consider. */ |
4445 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
5048 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
Line 4577... | Line 5180... | ||
4577 | } |
5180 | } |
Line 4578... | Line 5181... | ||
4578 | 5181 | ||
4579 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5182 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4580 | struct intel_crtc_config *pipe_config) |
5183 | struct intel_crtc_config *pipe_config) |
4581 | { |
5184 | { |
4582 | pipe_config->ips_enabled = i915_enable_ips && |
5185 | pipe_config->ips_enabled = i915.enable_ips && |
4583 | hsw_crtc_supports_ips(crtc) && |
5186 | hsw_crtc_supports_ips(crtc) && |
4584 | pipe_config->pipe_bpp <= 24; |
5187 | pipe_config->pipe_bpp <= 24; |
Line 4585... | Line 5188... | ||
4585 | } |
5188 | } |
Line 4639... | Line 5242... | ||
4639 | } |
5242 | } |
Line 4640... | Line 5243... | ||
4640 | 5243 | ||
4641 | if (HAS_IPS(dev)) |
5244 | if (HAS_IPS(dev)) |
Line -... | Line 5245... | ||
- | 5245 | hsw_compute_ips_config(crtc, pipe_config); |
|
4642 | hsw_compute_ips_config(crtc, pipe_config); |
5246 | |
4643 | 5247 | /* |
|
- | 5248 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the |
|
4644 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
5249 | * old clock survives for now. |
4645 | * clock survives for now. */ |
5250 | */ |
Line 4646... | Line 5251... | ||
4646 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5251 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) |
4647 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
5252 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
Line 4648... | Line 5253... | ||
4648 | 5253 | ||
4649 | if (pipe_config->has_pch_encoder) |
5254 | if (pipe_config->has_pch_encoder) |
Line 4650... | Line 5255... | ||
4650 | return ironlake_fdi_compute_config(crtc, pipe_config); |
5255 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4651 | 5256 | ||
- | 5257 | return 0; |
|
- | 5258 | } |
|
- | 5259 | ||
- | 5260 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
|
- | 5261 | { |
|
- | 5262 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5263 | int vco = valleyview_get_vco(dev_priv); |
|
- | 5264 | u32 val; |
|
- | 5265 | int divider; |
|
- | 5266 | ||
- | 5267 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 5268 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
|
- | 5269 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 5270 | ||
- | 5271 | divider = val & DISPLAY_FREQUENCY_VALUES; |
|
4652 | return 0; |
5272 | |
4653 | } |
5273 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
Line 4654... | Line 5274... | ||
4654 | 5274 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
|
4655 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5275 | "cdclk change in progress\n"); |
4656 | { |
5276 | |
Line 4778... | Line 5398... | ||
4778 | &m_n->link_m, &m_n->link_n); |
5398 | &m_n->link_m, &m_n->link_n); |
4779 | } |
5399 | } |
Line 4780... | Line 5400... | ||
4780 | 5400 | ||
4781 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5401 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4782 | { |
5402 | { |
4783 | if (i915_panel_use_ssc >= 0) |
5403 | if (i915.panel_use_ssc >= 0) |
4784 | return i915_panel_use_ssc != 0; |
5404 | return i915.panel_use_ssc != 0; |
4785 | return dev_priv->vbt.lvds_use_ssc |
5405 | return dev_priv->vbt.lvds_use_ssc |
4786 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
5406 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Line 4787... | Line 5407... | ||
4787 | } |
5407 | } |
Line 4819... | Line 5439... | ||
4819 | 5439 | ||
4820 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
5440 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4821 | intel_clock_t *reduced_clock) |
5441 | intel_clock_t *reduced_clock) |
4822 | { |
5442 | { |
4823 | struct drm_device *dev = crtc->base.dev; |
- | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4825 | int pipe = crtc->pipe; |
5443 | struct drm_device *dev = crtc->base.dev; |
Line 4826... | Line 5444... | ||
4826 | u32 fp, fp2 = 0; |
5444 | u32 fp, fp2 = 0; |
4827 | 5445 | ||
4828 | if (IS_PINEVIEW(dev)) { |
5446 | if (IS_PINEVIEW(dev)) { |
Line 4833... | Line 5451... | ||
4833 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
5451 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4834 | if (reduced_clock) |
5452 | if (reduced_clock) |
4835 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
5453 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4836 | } |
5454 | } |
Line 4837... | Line -... | ||
4837 | - | ||
4838 | I915_WRITE(FP0(pipe), fp); |
5455 | |
Line 4839... | Line 5456... | ||
4839 | crtc->config.dpll_hw_state.fp0 = fp; |
5456 | crtc->config.dpll_hw_state.fp0 = fp; |
4840 | 5457 | ||
4841 | crtc->lowfreq_avail = false; |
5458 | crtc->lowfreq_avail = false; |
4842 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
- | |
4843 | reduced_clock && i915_powersave) { |
5459 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4844 | I915_WRITE(FP1(pipe), fp2); |
5460 | reduced_clock && i915.powersave) { |
4845 | crtc->config.dpll_hw_state.fp1 = fp2; |
5461 | crtc->config.dpll_hw_state.fp1 = fp2; |
4846 | crtc->lowfreq_avail = true; |
- | |
4847 | } else { |
5462 | crtc->lowfreq_avail = true; |
4848 | I915_WRITE(FP1(pipe), fp); |
5463 | } else { |
4849 | crtc->config.dpll_hw_state.fp1 = fp; |
5464 | crtc->config.dpll_hw_state.fp1 = fp; |
Line 4850... | Line 5465... | ||
4850 | } |
5465 | } |
Line 4921... | Line 5536... | ||
4921 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
5536 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4922 | } |
5537 | } |
Line 4923... | Line 5538... | ||
4923 | 5538 | ||
4924 | static void vlv_update_pll(struct intel_crtc *crtc) |
5539 | static void vlv_update_pll(struct intel_crtc *crtc) |
- | 5540 | { |
|
- | 5541 | u32 dpll, dpll_md; |
|
- | 5542 | ||
- | 5543 | /* |
|
- | 5544 | * Enable DPIO clock input. We should never disable the reference |
|
- | 5545 | * clock for pipe B, since VGA hotplug / manual detection depends |
|
- | 5546 | * on it. |
|
- | 5547 | */ |
|
- | 5548 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
|
- | 5549 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
|
- | 5550 | /* We should never disable this, set it here for state tracking */ |
|
- | 5551 | if (crtc->pipe == PIPE_B) |
|
- | 5552 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 5553 | dpll |= DPLL_VCO_ENABLE; |
|
- | 5554 | crtc->config.dpll_hw_state.dpll = dpll; |
|
- | 5555 | ||
- | 5556 | dpll_md = (crtc->config.pixel_multiplier - 1) |
|
- | 5557 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
|
- | 5558 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
|
- | 5559 | } |
|
- | 5560 | ||
- | 5561 | static void vlv_prepare_pll(struct intel_crtc *crtc) |
|
4925 | { |
5562 | { |
4926 | struct drm_device *dev = crtc->base.dev; |
5563 | struct drm_device *dev = crtc->base.dev; |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; |
5564 | struct drm_i915_private *dev_priv = dev->dev_private; |
4928 | int pipe = crtc->pipe; |
5565 | int pipe = crtc->pipe; |
4929 | u32 dpll, mdiv; |
5566 | u32 mdiv; |
4930 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
5567 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
Line 4931... | Line 5568... | ||
4931 | u32 coreclk, reg_val, dpll_md; |
5568 | u32 coreclk, reg_val; |
Line 4932... | Line 5569... | ||
4932 | 5569 | ||
4933 | mutex_lock(&dev_priv->dpio_lock); |
5570 | mutex_lock(&dev_priv->dpio_lock); |
Line 4939... | Line 5576... | ||
4939 | bestp2 = crtc->config.dpll.p2; |
5576 | bestp2 = crtc->config.dpll.p2; |
Line 4940... | Line 5577... | ||
4940 | 5577 | ||
Line 4941... | Line 5578... | ||
4941 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5578 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4942 | 5579 | ||
4943 | /* PLL B needs special handling */ |
5580 | /* PLL B needs special handling */ |
Line 4944... | Line 5581... | ||
4944 | if (pipe) |
5581 | if (pipe == PIPE_B) |
4945 | vlv_pllb_recal_opamp(dev_priv, pipe); |
5582 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Line 4983... | Line 5620... | ||
4983 | 0x00d0000f); |
5620 | 0x00d0000f); |
Line 4984... | Line 5621... | ||
4984 | 5621 | ||
4985 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
5622 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4986 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
5623 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4987 | /* Use SSC source */ |
5624 | /* Use SSC source */ |
4988 | if (!pipe) |
5625 | if (pipe == PIPE_A) |
4989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5626 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4990 | 0x0df40000); |
5627 | 0x0df40000); |
4991 | else |
5628 | else |
4992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5629 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4993 | 0x0df70000); |
5630 | 0x0df70000); |
4994 | } else { /* HDMI or VGA */ |
5631 | } else { /* HDMI or VGA */ |
4995 | /* Use bend source */ |
5632 | /* Use bend source */ |
4996 | if (!pipe) |
5633 | if (pipe == PIPE_A) |
4997 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5634 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4998 | 0x0df70000); |
5635 | 0x0df70000); |
4999 | else |
5636 | else |
5000 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5637 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Line 5007... | Line 5644... | ||
5007 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5644 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5008 | coreclk |= 0x01000000; |
5645 | coreclk |= 0x01000000; |
5009 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
5646 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
Line 5010... | Line 5647... | ||
5010 | 5647 | ||
- | 5648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
|
- | 5649 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 5650 | } |
|
- | 5651 | ||
- | 5652 | static void chv_update_pll(struct intel_crtc *crtc) |
|
- | 5653 | { |
|
- | 5654 | struct drm_device *dev = crtc->base.dev; |
|
- | 5655 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5656 | int pipe = crtc->pipe; |
|
- | 5657 | int dpll_reg = DPLL(crtc->pipe); |
|
- | 5658 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 5659 | u32 loopfilter, intcoeff; |
|
- | 5660 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
|
- | 5661 | int refclk; |
|
- | 5662 | ||
- | 5663 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
|
- | 5664 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
|
- | 5665 | DPLL_VCO_ENABLE; |
|
- | 5666 | if (pipe != PIPE_A) |
|
- | 5667 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 5668 | ||
- | 5669 | crtc->config.dpll_hw_state.dpll_md = |
|
- | 5670 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
|
- | 5671 | ||
- | 5672 | bestn = crtc->config.dpll.n; |
|
- | 5673 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; |
|
- | 5674 | bestm1 = crtc->config.dpll.m1; |
|
- | 5675 | bestm2 = crtc->config.dpll.m2 >> 22; |
|
- | 5676 | bestp1 = crtc->config.dpll.p1; |
|
Line 5011... | Line 5677... | ||
5011 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
5677 | bestp2 = crtc->config.dpll.p2; |
5012 | - | ||
5013 | /* |
- | |
5014 | * Enable DPIO clock input. We should never disable the reference |
5678 | |
5015 | * clock for pipe B, since VGA hotplug / manual detection depends |
5679 | /* |
5016 | * on it. |
- | |
5017 | */ |
- | |
5018 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
- | |
5019 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
5680 | * Enable Refclk and SSC |
5020 | /* We should never disable this, set it here for state tracking */ |
- | |
5021 | if (pipe == PIPE_B) |
- | |
5022 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
5681 | */ |
Line 5023... | Line -... | ||
5023 | dpll |= DPLL_VCO_ENABLE; |
- | |
5024 | crtc->config.dpll_hw_state.dpll = dpll; |
5682 | I915_WRITE(dpll_reg, |
5025 | - | ||
Line -... | Line 5683... | ||
- | 5683 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
|
- | 5684 | ||
- | 5685 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 5686 | ||
- | 5687 | /* p1 and p2 divider */ |
|
- | 5688 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
|
- | 5689 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
|
- | 5690 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
|
- | 5691 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
|
- | 5692 | 1 << DPIO_CHV_K_DIV_SHIFT); |
|
- | 5693 | ||
- | 5694 | /* Feedback post-divider - m2 */ |
|
- | 5695 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
|
- | 5696 | ||
- | 5697 | /* Feedback refclk divider - n and m1 */ |
|
- | 5698 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
|
- | 5699 | DPIO_CHV_M1_DIV_BY_2 | |
|
- | 5700 | 1 << DPIO_CHV_N_DIV_SHIFT); |
|
5026 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5701 | |
- | 5702 | /* M2 fraction division */ |
|
- | 5703 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
|
- | 5704 | ||
- | 5705 | /* M2 fraction division enable */ |
|
- | 5706 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), |
|
- | 5707 | DPIO_CHV_FRAC_DIV_EN | |
|
- | 5708 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); |
|
- | 5709 | ||
- | 5710 | /* Loop filter */ |
|
- | 5711 | refclk = i9xx_get_refclk(&crtc->base, 0); |
|
- | 5712 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
|
- | 5713 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; |
|
- | 5714 | if (refclk == 100000) |
|
- | 5715 | intcoeff = 11; |
|
- | 5716 | else if (refclk == 38400) |
|
- | 5717 | intcoeff = 10; |
|
- | 5718 | else |
|
- | 5719 | intcoeff = 9; |
|
- | 5720 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; |
|
- | 5721 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
|
5027 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5722 | |
Line 5028... | Line 5723... | ||
5028 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5723 | /* AFC Recal */ |
5029 | 5724 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
|
Line 5030... | Line 5725... | ||
5030 | if (crtc->config.has_dp_encoder) |
5725 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
Line 5105... | Line 5800... | ||
5105 | if (INTEL_INFO(dev)->gen >= 4) { |
5800 | if (INTEL_INFO(dev)->gen >= 4) { |
5106 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5801 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5107 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5802 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5108 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5803 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5109 | } |
5804 | } |
5110 | - | ||
5111 | if (crtc->config.has_dp_encoder) |
- | |
5112 | intel_dp_set_m_n(crtc); |
- | |
5113 | } |
5805 | } |
Line 5114... | Line 5806... | ||
5114 | 5806 | ||
5115 | static void i8xx_update_pll(struct intel_crtc *crtc, |
5807 | static void i8xx_update_pll(struct intel_crtc *crtc, |
5116 | intel_clock_t *reduced_clock, |
5808 | intel_clock_t *reduced_clock, |
Line 5155... | Line 5847... | ||
5155 | struct drm_i915_private *dev_priv = dev->dev_private; |
5847 | struct drm_i915_private *dev_priv = dev->dev_private; |
5156 | enum pipe pipe = intel_crtc->pipe; |
5848 | enum pipe pipe = intel_crtc->pipe; |
5157 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5849 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5158 | struct drm_display_mode *adjusted_mode = |
5850 | struct drm_display_mode *adjusted_mode = |
5159 | &intel_crtc->config.adjusted_mode; |
5851 | &intel_crtc->config.adjusted_mode; |
5160 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5852 | uint32_t crtc_vtotal, crtc_vblank_end; |
- | 5853 | int vsyncshift = 0; |
|
Line 5161... | Line 5854... | ||
5161 | 5854 | ||
5162 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5855 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5163 | * the hw state checker will get angry at the mismatch. */ |
5856 | * the hw state checker will get angry at the mismatch. */ |
5164 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
5857 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
Line 5165... | Line 5858... | ||
5165 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
5858 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
5166 | 5859 | ||
5167 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5860 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5168 | /* the chip adds 2 halflines automatically */ |
5861 | /* the chip adds 2 halflines automatically */ |
- | 5862 | crtc_vtotal -= 1; |
|
5169 | crtc_vtotal -= 1; |
5863 | crtc_vblank_end -= 1; |
5170 | crtc_vblank_end -= 1; |
5864 | |
5171 | vsyncshift = adjusted_mode->crtc_hsync_start |
5865 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
- | 5866 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
|
- | 5867 | else |
|
5172 | - adjusted_mode->crtc_htotal / 2; |
5868 | vsyncshift = adjusted_mode->crtc_hsync_start - |
- | 5869 | adjusted_mode->crtc_htotal / 2; |
|
5173 | } else { |
5870 | if (vsyncshift < 0) |
Line 5174... | Line 5871... | ||
5174 | vsyncshift = 0; |
5871 | vsyncshift += adjusted_mode->crtc_htotal; |
5175 | } |
5872 | } |
Line 5253... | Line 5950... | ||
5253 | 5950 | ||
5254 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
5951 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
5255 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
5952 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
Line 5256... | Line 5953... | ||
5256 | } |
5953 | } |
5257 | 5954 | ||
5258 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5955 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
- | 5956 | struct intel_crtc_config *pipe_config) |
|
- | 5957 | { |
|
- | 5958 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
|
- | 5959 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
|
- | 5960 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
|
- | 5961 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
|
5259 | struct intel_crtc_config *pipe_config) |
5962 | |
- | 5963 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
|
- | 5964 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
|
Line 5260... | Line -... | ||
5260 | { |
- | |
5261 | struct drm_crtc *crtc = &intel_crtc->base; |
5965 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
5262 | - | ||
5263 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
- | |
5264 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
- | |
5265 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
- | |
5266 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
- | |
5267 | - | ||
5268 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
- | |
Line 5269... | Line -... | ||
5269 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
- | |
5270 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
- | |
5271 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
5966 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
5272 | 5967 | ||
5273 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
5968 | mode->flags = pipe_config->adjusted_mode.flags; |
Line 5274... | Line 5969... | ||
5274 | 5969 | ||
5275 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
5970 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5276 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5971 | mode->flags |= pipe_config->adjusted_mode.flags; |
Line 5321... | Line 6016... | ||
5321 | } else { |
6016 | } else { |
5322 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
6017 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
5323 | } |
6018 | } |
5324 | } |
6019 | } |
Line -... | Line 6020... | ||
- | 6020 | ||
5325 | 6021 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
|
5326 | if (!IS_GEN2(dev) && |
6022 | if (INTEL_INFO(dev)->gen < 4 || |
5327 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6023 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
5328 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6024 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
- | 6025 | else |
|
- | 6026 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
|
5329 | else |
6027 | } else |
Line 5330... | Line 6028... | ||
5330 | pipeconf |= PIPECONF_PROGRESSIVE; |
6028 | pipeconf |= PIPECONF_PROGRESSIVE; |
5331 | 6029 | ||
Line 5341... | Line 6039... | ||
5341 | struct drm_framebuffer *fb) |
6039 | struct drm_framebuffer *fb) |
5342 | { |
6040 | { |
5343 | struct drm_device *dev = crtc->dev; |
6041 | struct drm_device *dev = crtc->dev; |
5344 | struct drm_i915_private *dev_priv = dev->dev_private; |
6042 | struct drm_i915_private *dev_priv = dev->dev_private; |
5345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5346 | int pipe = intel_crtc->pipe; |
- | |
5347 | int plane = intel_crtc->plane; |
- | |
5348 | int refclk, num_connectors = 0; |
6044 | int refclk, num_connectors = 0; |
5349 | intel_clock_t clock, reduced_clock; |
6045 | intel_clock_t clock, reduced_clock; |
5350 | u32 dspcntr; |
- | |
5351 | bool ok, has_reduced_clock = false; |
6046 | bool ok, has_reduced_clock = false; |
5352 | bool is_lvds = false, is_dsi = false; |
6047 | bool is_lvds = false, is_dsi = false; |
5353 | struct intel_encoder *encoder; |
6048 | struct intel_encoder *encoder; |
5354 | const intel_limit_t *limit; |
6049 | const intel_limit_t *limit; |
5355 | int ret; |
- | |
Line 5356... | Line 6050... | ||
5356 | 6050 | ||
5357 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6051 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5358 | switch (encoder->type) { |
6052 | switch (encoder->type) { |
5359 | case INTEL_OUTPUT_LVDS: |
6053 | case INTEL_OUTPUT_LVDS: |
Line 5366... | Line 6060... | ||
5366 | 6060 | ||
5367 | num_connectors++; |
6061 | num_connectors++; |
Line 5368... | Line 6062... | ||
5368 | } |
6062 | } |
5369 | 6063 | ||
Line 5370... | Line 6064... | ||
5370 | if (is_dsi) |
6064 | if (is_dsi) |
5371 | goto skip_dpll; |
6065 | return 0; |
Line 5372... | Line 6066... | ||
5372 | 6066 | ||
Line 5411... | Line 6105... | ||
5411 | 6105 | ||
5412 | if (IS_GEN2(dev)) { |
6106 | if (IS_GEN2(dev)) { |
5413 | i8xx_update_pll(intel_crtc, |
6107 | i8xx_update_pll(intel_crtc, |
5414 | has_reduced_clock ? &reduced_clock : NULL, |
6108 | has_reduced_clock ? &reduced_clock : NULL, |
- | 6109 | num_connectors); |
|
- | 6110 | } else if (IS_CHERRYVIEW(dev)) { |
|
5415 | num_connectors); |
6111 | chv_update_pll(intel_crtc); |
5416 | } else if (IS_VALLEYVIEW(dev)) { |
6112 | } else if (IS_VALLEYVIEW(dev)) { |
5417 | vlv_update_pll(intel_crtc); |
6113 | vlv_update_pll(intel_crtc); |
5418 | } else { |
6114 | } else { |
5419 | i9xx_update_pll(intel_crtc, |
6115 | i9xx_update_pll(intel_crtc, |
5420 | has_reduced_clock ? &reduced_clock : NULL, |
6116 | has_reduced_clock ? &reduced_clock : NULL, |
5421 | num_connectors); |
6117 | num_connectors); |
Line 5422... | Line -... | ||
5422 | } |
- | |
5423 | - | ||
5424 | skip_dpll: |
- | |
5425 | /* Set up the display plane register */ |
- | |
5426 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
- | |
5427 | - | ||
5428 | if (!IS_VALLEYVIEW(dev)) { |
- | |
5429 | if (pipe == 0) |
- | |
5430 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
- | |
5431 | else |
- | |
5432 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
- | |
5433 | } |
- | |
5434 | - | ||
5435 | intel_set_pipe_timings(intel_crtc); |
- | |
5436 | - | ||
5437 | /* pipesrc and dspsize control the size that is scaled from, |
- | |
5438 | * which should always be the user's requested size. |
- | |
5439 | */ |
- | |
5440 | I915_WRITE(DSPSIZE(plane), |
- | |
5441 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
- | |
5442 | (intel_crtc->config.pipe_src_w - 1)); |
- | |
5443 | I915_WRITE(DSPPOS(plane), 0); |
- | |
5444 | - | ||
5445 | i9xx_set_pipeconf(intel_crtc); |
- | |
5446 | - | ||
5447 | I915_WRITE(DSPCNTR(plane), dspcntr); |
- | |
5448 | POSTING_READ(DSPCNTR(plane)); |
- | |
5449 | - | ||
5450 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6118 | } |
5451 | 6119 | ||
Line 5452... | Line 6120... | ||
5452 | return ret; |
6120 | return 0; |
5453 | } |
6121 | } |
5454 | 6122 | ||
Line 5490... | Line 6158... | ||
5490 | int pipe = pipe_config->cpu_transcoder; |
6158 | int pipe = pipe_config->cpu_transcoder; |
5491 | intel_clock_t clock; |
6159 | intel_clock_t clock; |
5492 | u32 mdiv; |
6160 | u32 mdiv; |
5493 | int refclk = 100000; |
6161 | int refclk = 100000; |
Line -... | Line 6162... | ||
- | 6162 | ||
- | 6163 | /* In case of MIPI DPLL will not even be used */ |
|
- | 6164 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
|
- | 6165 | return; |
|
5494 | 6166 | ||
5495 | mutex_lock(&dev_priv->dpio_lock); |
6167 | mutex_lock(&dev_priv->dpio_lock); |
5496 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
6168 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Line 5497... | Line 6169... | ||
5497 | mutex_unlock(&dev_priv->dpio_lock); |
6169 | mutex_unlock(&dev_priv->dpio_lock); |
Line 5506... | Line 6178... | ||
5506 | 6178 | ||
5507 | /* clock.dot is the fast clock */ |
6179 | /* clock.dot is the fast clock */ |
5508 | pipe_config->port_clock = clock.dot / 5; |
6180 | pipe_config->port_clock = clock.dot / 5; |
Line -... | Line 6181... | ||
- | 6181 | } |
|
- | 6182 | ||
- | 6183 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
|
- | 6184 | struct intel_plane_config *plane_config) |
|
- | 6185 | { |
|
- | 6186 | struct drm_device *dev = crtc->base.dev; |
|
- | 6187 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6188 | u32 val, base, offset; |
|
- | 6189 | int pipe = crtc->pipe, plane = crtc->plane; |
|
- | 6190 | int fourcc, pixel_format; |
|
- | 6191 | int aligned_height; |
|
- | 6192 | ||
- | 6193 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
|
- | 6194 | if (!crtc->base.primary->fb) { |
|
- | 6195 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
|
- | 6196 | return; |
|
- | 6197 | } |
|
- | 6198 | ||
- | 6199 | val = I915_READ(DSPCNTR(plane)); |
|
- | 6200 | ||
- | 6201 | if (INTEL_INFO(dev)->gen >= 4) |
|
- | 6202 | if (val & DISPPLANE_TILED) |
|
- | 6203 | plane_config->tiled = true; |
|
- | 6204 | ||
- | 6205 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
|
- | 6206 | fourcc = intel_format_to_fourcc(pixel_format); |
|
- | 6207 | crtc->base.primary->fb->pixel_format = fourcc; |
|
- | 6208 | crtc->base.primary->fb->bits_per_pixel = |
|
- | 6209 | drm_format_plane_cpp(fourcc, 0) * 8; |
|
- | 6210 | ||
- | 6211 | if (INTEL_INFO(dev)->gen >= 4) { |
|
- | 6212 | if (plane_config->tiled) |
|
- | 6213 | offset = I915_READ(DSPTILEOFF(plane)); |
|
- | 6214 | else |
|
- | 6215 | offset = I915_READ(DSPLINOFF(plane)); |
|
- | 6216 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
|
- | 6217 | } else { |
|
- | 6218 | base = I915_READ(DSPADDR(plane)); |
|
- | 6219 | } |
|
- | 6220 | plane_config->base = base; |
|
- | 6221 | ||
- | 6222 | val = I915_READ(PIPESRC(pipe)); |
|
- | 6223 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
|
- | 6224 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
|
- | 6225 | ||
- | 6226 | val = I915_READ(DSPSTRIDE(pipe)); |
|
- | 6227 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
|
- | 6228 | ||
- | 6229 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
|
- | 6230 | plane_config->tiled); |
|
- | 6231 | ||
- | 6232 | plane_config->size = 16*1024*1024; |
|
- | 6233 | ||
- | 6234 | ||
- | 6235 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
|
- | 6236 | pipe, plane, crtc->base.primary->fb->width, |
|
- | 6237 | crtc->base.primary->fb->height, |
|
- | 6238 | crtc->base.primary->fb->bits_per_pixel, base, |
|
- | 6239 | crtc->base.primary->fb->pitches[0], |
|
- | 6240 | plane_config->size); |
|
- | 6241 | ||
- | 6242 | } |
|
- | 6243 | ||
- | 6244 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
|
- | 6245 | struct intel_crtc_config *pipe_config) |
|
- | 6246 | { |
|
- | 6247 | struct drm_device *dev = crtc->base.dev; |
|
- | 6248 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6249 | int pipe = pipe_config->cpu_transcoder; |
|
- | 6250 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
|
- | 6251 | intel_clock_t clock; |
|
- | 6252 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; |
|
- | 6253 | int refclk = 100000; |
|
- | 6254 | ||
- | 6255 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 6256 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
|
- | 6257 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
|
- | 6258 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
|
- | 6259 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
|
- | 6260 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 6261 | ||
- | 6262 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
|
- | 6263 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); |
|
- | 6264 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
|
- | 6265 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
|
- | 6266 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
|
- | 6267 | ||
- | 6268 | chv_clock(refclk, &clock); |
|
- | 6269 | ||
- | 6270 | /* clock.dot is the fast clock */ |
|
- | 6271 | pipe_config->port_clock = clock.dot / 5; |
|
5509 | } |
6272 | } |
5510 | 6273 | ||
5511 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6274 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5512 | struct intel_crtc_config *pipe_config) |
6275 | struct intel_crtc_config *pipe_config) |
5513 | { |
6276 | { |
5514 | struct drm_device *dev = crtc->base.dev; |
6277 | struct drm_device *dev = crtc->base.dev; |
Line -... | Line 6278... | ||
- | 6278 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6279 | uint32_t tmp; |
|
- | 6280 | ||
- | 6281 | if (!intel_display_power_enabled(dev_priv, |
|
5515 | struct drm_i915_private *dev_priv = dev->dev_private; |
6282 | POWER_DOMAIN_PIPE(crtc->pipe))) |
5516 | uint32_t tmp; |
6283 | return false; |
Line 5517... | Line 6284... | ||
5517 | 6284 | ||
5518 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6285 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Line 5536... | Line 6303... | ||
5536 | default: |
6303 | default: |
5537 | break; |
6304 | break; |
5538 | } |
6305 | } |
5539 | } |
6306 | } |
Line -... | Line 6307... | ||
- | 6307 | ||
- | 6308 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
|
- | 6309 | pipe_config->limited_color_range = true; |
|
5540 | 6310 | ||
5541 | if (INTEL_INFO(dev)->gen < 4) |
6311 | if (INTEL_INFO(dev)->gen < 4) |
Line 5542... | Line 6312... | ||
5542 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
6312 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
Line 5571... | Line 6341... | ||
5571 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
6341 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5572 | DPLL_PORTC_READY_MASK | |
6342 | DPLL_PORTC_READY_MASK | |
5573 | DPLL_PORTB_READY_MASK); |
6343 | DPLL_PORTB_READY_MASK); |
5574 | } |
6344 | } |
Line -... | Line 6345... | ||
- | 6345 | ||
- | 6346 | if (IS_CHERRYVIEW(dev)) |
|
5575 | 6347 | chv_crtc_clock_get(crtc, pipe_config); |
|
5576 | if (IS_VALLEYVIEW(dev)) |
6348 | else if (IS_VALLEYVIEW(dev)) |
5577 | vlv_crtc_clock_get(crtc, pipe_config); |
6349 | vlv_crtc_clock_get(crtc, pipe_config); |
5578 | else |
6350 | else |
Line 5579... | Line 6351... | ||
5579 | i9xx_crtc_clock_get(crtc, pipe_config); |
6351 | i9xx_crtc_clock_get(crtc, pipe_config); |
Line 5692... | Line 6464... | ||
5692 | /* Enable CPU source on CPU attached eDP */ |
6464 | /* Enable CPU source on CPU attached eDP */ |
5693 | if (has_cpu_edp) { |
6465 | if (has_cpu_edp) { |
5694 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
6466 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5695 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
6467 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5696 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
6468 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5697 | } |
- | |
5698 | else |
6469 | } else |
5699 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
6470 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5700 | } else |
6471 | } else |
5701 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6472 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Line 5702... | Line 6473... | ||
5702 | 6473 | ||
Line 6174... | Line 6945... | ||
6174 | * Account for spread spectrum to avoid |
6945 | * Account for spread spectrum to avoid |
6175 | * oversubscribing the link. Max center spread |
6946 | * oversubscribing the link. Max center spread |
6176 | * is 2.5%; use 5% for safety's sake. |
6947 | * is 2.5%; use 5% for safety's sake. |
6177 | */ |
6948 | */ |
6178 | u32 bps = target_clock * bpp * 21 / 20; |
6949 | u32 bps = target_clock * bpp * 21 / 20; |
6179 | return bps / (link_bw * 8) + 1; |
6950 | return DIV_ROUND_UP(bps, link_bw * 8); |
6180 | } |
6951 | } |
Line 6181... | Line 6952... | ||
6181 | 6952 | ||
6182 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6953 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6183 | { |
6954 | { |
Line 6272... | Line 7043... | ||
6272 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
7043 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
6273 | int x, int y, |
7044 | int x, int y, |
6274 | struct drm_framebuffer *fb) |
7045 | struct drm_framebuffer *fb) |
6275 | { |
7046 | { |
6276 | struct drm_device *dev = crtc->dev; |
7047 | struct drm_device *dev = crtc->dev; |
6277 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6279 | int pipe = intel_crtc->pipe; |
- | |
6280 | int plane = intel_crtc->plane; |
- | |
6281 | int num_connectors = 0; |
7049 | int num_connectors = 0; |
6282 | intel_clock_t clock, reduced_clock; |
7050 | intel_clock_t clock, reduced_clock; |
6283 | u32 dpll = 0, fp = 0, fp2 = 0; |
7051 | u32 dpll = 0, fp = 0, fp2 = 0; |
6284 | bool ok, has_reduced_clock = false; |
7052 | bool ok, has_reduced_clock = false; |
6285 | bool is_lvds = false; |
7053 | bool is_lvds = false; |
6286 | struct intel_encoder *encoder; |
7054 | struct intel_encoder *encoder; |
6287 | struct intel_shared_dpll *pll; |
7055 | struct intel_shared_dpll *pll; |
6288 | int ret; |
- | |
Line 6289... | Line 7056... | ||
6289 | 7056 | ||
6290 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
7057 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6291 | switch (encoder->type) { |
7058 | switch (encoder->type) { |
6292 | case INTEL_OUTPUT_LVDS: |
7059 | case INTEL_OUTPUT_LVDS: |
Line 6333... | Line 7100... | ||
6333 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
7100 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
Line 6334... | Line 7101... | ||
6334 | 7101 | ||
6335 | pll = intel_get_shared_dpll(intel_crtc); |
7102 | pll = intel_get_shared_dpll(intel_crtc); |
6336 | if (pll == NULL) { |
7103 | if (pll == NULL) { |
6337 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
7104 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6338 | pipe_name(pipe)); |
7105 | pipe_name(intel_crtc->pipe)); |
6339 | return -EINVAL; |
7106 | return -EINVAL; |
6340 | } |
7107 | } |
6341 | } else |
7108 | } else |
Line 6342... | Line -... | ||
6342 | intel_put_shared_dpll(intel_crtc); |
- | |
6343 | - | ||
6344 | if (intel_crtc->config.has_dp_encoder) |
- | |
6345 | intel_dp_set_m_n(intel_crtc); |
7109 | intel_put_shared_dpll(intel_crtc); |
6346 | 7110 | ||
6347 | if (is_lvds && has_reduced_clock && i915_powersave) |
7111 | if (is_lvds && has_reduced_clock && i915.powersave) |
6348 | intel_crtc->lowfreq_avail = true; |
7112 | intel_crtc->lowfreq_avail = true; |
Line 6349... | Line -... | ||
6349 | else |
- | |
6350 | intel_crtc->lowfreq_avail = false; |
- | |
6351 | - | ||
6352 | intel_set_pipe_timings(intel_crtc); |
- | |
6353 | - | ||
6354 | if (intel_crtc->config.has_pch_encoder) { |
- | |
6355 | intel_cpu_transcoder_set_m_n(intel_crtc, |
- | |
6356 | &intel_crtc->config.fdi_m_n); |
- | |
6357 | } |
- | |
6358 | - | ||
6359 | ironlake_set_pipeconf(crtc); |
- | |
6360 | - | ||
6361 | /* Set up the display plane register */ |
- | |
6362 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
- | |
6363 | POSTING_READ(DSPCNTR(plane)); |
- | |
6364 | 7113 | else |
|
6365 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7114 | intel_crtc->lowfreq_avail = false; |
Line 6366... | Line 7115... | ||
6366 | 7115 | ||
6367 | return ret; |
7116 | return 0; |
6368 | } |
7117 | } |
Line 6449... | Line 7198... | ||
6449 | PF_PIPE_SEL_IVB(crtc->pipe)); |
7198 | PF_PIPE_SEL_IVB(crtc->pipe)); |
6450 | } |
7199 | } |
6451 | } |
7200 | } |
6452 | } |
7201 | } |
Line -... | Line 7202... | ||
- | 7202 | ||
- | 7203 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
|
- | 7204 | struct intel_plane_config *plane_config) |
|
- | 7205 | { |
|
- | 7206 | struct drm_device *dev = crtc->base.dev; |
|
- | 7207 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7208 | u32 val, base, offset; |
|
- | 7209 | int pipe = crtc->pipe, plane = crtc->plane; |
|
- | 7210 | int fourcc, pixel_format; |
|
- | 7211 | int aligned_height; |
|
- | 7212 | ||
- | 7213 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
|
- | 7214 | if (!crtc->base.primary->fb) { |
|
- | 7215 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
|
- | 7216 | return; |
|
- | 7217 | } |
|
- | 7218 | ||
- | 7219 | val = I915_READ(DSPCNTR(plane)); |
|
- | 7220 | ||
- | 7221 | if (INTEL_INFO(dev)->gen >= 4) |
|
- | 7222 | if (val & DISPPLANE_TILED) |
|
- | 7223 | plane_config->tiled = true; |
|
- | 7224 | ||
- | 7225 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
|
- | 7226 | fourcc = intel_format_to_fourcc(pixel_format); |
|
- | 7227 | crtc->base.primary->fb->pixel_format = fourcc; |
|
- | 7228 | crtc->base.primary->fb->bits_per_pixel = |
|
- | 7229 | drm_format_plane_cpp(fourcc, 0) * 8; |
|
- | 7230 | ||
- | 7231 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
|
- | 7232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
|
- | 7233 | offset = I915_READ(DSPOFFSET(plane)); |
|
- | 7234 | } else { |
|
- | 7235 | if (plane_config->tiled) |
|
- | 7236 | offset = I915_READ(DSPTILEOFF(plane)); |
|
- | 7237 | else |
|
- | 7238 | offset = I915_READ(DSPLINOFF(plane)); |
|
- | 7239 | } |
|
- | 7240 | plane_config->base = base; |
|
- | 7241 | ||
- | 7242 | val = I915_READ(PIPESRC(pipe)); |
|
- | 7243 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
|
- | 7244 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
|
- | 7245 | ||
- | 7246 | val = I915_READ(DSPSTRIDE(pipe)); |
|
- | 7247 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
|
- | 7248 | ||
- | 7249 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
|
- | 7250 | plane_config->tiled); |
|
- | 7251 | ||
- | 7252 | plane_config->size = 16*1024*1024; |
|
- | 7253 | ||
- | 7254 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
|
- | 7255 | pipe, plane, crtc->base.primary->fb->width, |
|
- | 7256 | crtc->base.primary->fb->height, |
|
- | 7257 | crtc->base.primary->fb->bits_per_pixel, base, |
|
- | 7258 | crtc->base.primary->fb->pitches[0], |
|
- | 7259 | plane_config->size); |
|
- | 7260 | } |
|
6453 | 7261 | ||
6454 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7262 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6455 | struct intel_crtc_config *pipe_config) |
7263 | struct intel_crtc_config *pipe_config) |
6456 | { |
7264 | { |
6457 | struct drm_device *dev = crtc->base.dev; |
7265 | struct drm_device *dev = crtc->base.dev; |
6458 | struct drm_i915_private *dev_priv = dev->dev_private; |
7266 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line -... | Line 7267... | ||
- | 7267 | uint32_t tmp; |
|
- | 7268 | ||
- | 7269 | if (!intel_display_power_enabled(dev_priv, |
|
- | 7270 | POWER_DOMAIN_PIPE(crtc->pipe))) |
|
6459 | uint32_t tmp; |
7271 | return false; |
6460 | 7272 | ||
Line 6461... | Line 7273... | ||
6461 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
7273 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6462 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7274 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Line 6480... | Line 7292... | ||
6480 | break; |
7292 | break; |
6481 | default: |
7293 | default: |
6482 | break; |
7294 | break; |
6483 | } |
7295 | } |
Line -... | Line 7296... | ||
- | 7296 | ||
- | 7297 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
|
- | 7298 | pipe_config->limited_color_range = true; |
|
6484 | 7299 | ||
6485 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
7300 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Line 6486... | Line 7301... | ||
6486 | struct intel_shared_dpll *pll; |
7301 | struct intel_shared_dpll *pll; |
Line 6527... | Line 7342... | ||
6527 | } |
7342 | } |
Line 6528... | Line 7343... | ||
6528 | 7343 | ||
6529 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7344 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6530 | { |
7345 | { |
6531 | struct drm_device *dev = dev_priv->dev; |
- | |
6532 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
7346 | struct drm_device *dev = dev_priv->dev; |
6533 | struct intel_crtc *crtc; |
- | |
6534 | unsigned long irqflags; |
- | |
Line 6535... | Line 7347... | ||
6535 | uint32_t val; |
7347 | struct intel_crtc *crtc; |
6536 | 7348 | ||
6537 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
7349 | for_each_intel_crtc(dev, crtc) |
Line 6538... | Line 7350... | ||
6538 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
7350 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
6539 | pipe_name(crtc->pipe)); |
7351 | pipe_name(crtc->pipe)); |
6540 | 7352 | ||
6541 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
7353 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
6542 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
7354 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
6543 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
7355 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
6544 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
7356 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
- | 7357 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
|
6545 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7358 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
6546 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
7359 | "CPU PWM1 enabled\n"); |
6547 | "CPU PWM1 enabled\n"); |
7360 | if (IS_HASWELL(dev)) |
6548 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
7361 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
6549 | "CPU PWM2 enabled\n"); |
7362 | "CPU PWM2 enabled\n"); |
6550 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7363 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
6551 | "PCH PWM1 enabled\n"); |
7364 | "PCH PWM1 enabled\n"); |
Line -... | Line 7365... | ||
- | 7365 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
|
- | 7366 | "Utility pin enabled\n"); |
|
- | 7367 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
|
- | 7368 | ||
- | 7369 | /* |
|
- | 7370 | * In theory we can still leave IRQs enabled, as long as only the HPD |
|
6552 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
7371 | * interrupts remain enabled. We used to check for that, but since it's |
- | 7372 | * gen-specific and since we only disable LCPLL after we fully disable |
|
- | 7373 | * the interrupts, the check below should be enough. |
|
- | 7374 | */ |
|
- | 7375 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
|
- | 7376 | } |
|
- | 7377 | ||
- | 7378 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
|
6553 | "Utility pin enabled\n"); |
7379 | { |
- | 7380 | struct drm_device *dev = dev_priv->dev; |
|
6554 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
7381 | |
- | 7382 | if (IS_HASWELL(dev)) |
|
- | 7383 | return I915_READ(D_COMP_HSW); |
|
6555 | 7384 | else |
|
- | 7385 | return I915_READ(D_COMP_BDW); |
|
- | 7386 | } |
|
- | 7387 | ||
6556 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7388 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
- | 7389 | { |
|
6557 | val = I915_READ(DEIMR); |
7390 | struct drm_device *dev = dev_priv->dev; |
- | 7391 | ||
6558 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
7392 | if (IS_HASWELL(dev)) { |
6559 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
7393 | mutex_lock(&dev_priv->rps.hw_lock); |
- | 7394 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
|
- | 7395 | val)) |
|
- | 7396 | DRM_ERROR("Failed to write to D_COMP\n"); |
|
- | 7397 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
6560 | val = I915_READ(SDEIMR); |
7398 | } else { |
Line 6561... | Line 7399... | ||
6561 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
7399 | I915_WRITE(D_COMP_BDW, val); |
6562 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
7400 | POSTING_READ(D_COMP_BDW); |
6563 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
7401 | } |
Line 6596... | Line 7434... | ||
6596 | POSTING_READ(LCPLL_CTL); |
7434 | POSTING_READ(LCPLL_CTL); |
Line 6597... | Line 7435... | ||
6597 | 7435 | ||
6598 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
7436 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
Line 6599... | Line 7437... | ||
6599 | DRM_ERROR("LCPLL still locked\n"); |
7437 | DRM_ERROR("LCPLL still locked\n"); |
6600 | 7438 | ||
6601 | val = I915_READ(D_COMP); |
7439 | val = hsw_read_dcomp(dev_priv); |
6602 | val |= D_COMP_COMP_DISABLE; |
- | |
6603 | mutex_lock(&dev_priv->rps.hw_lock); |
- | |
6604 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
- | |
6605 | DRM_ERROR("Failed to disable D_COMP\n"); |
- | |
6606 | mutex_unlock(&dev_priv->rps.hw_lock); |
7440 | val |= D_COMP_COMP_DISABLE; |
Line 6607... | Line 7441... | ||
6607 | POSTING_READ(D_COMP); |
7441 | hsw_write_dcomp(dev_priv, val); |
- | 7442 | ndelay(100); |
|
6608 | delay(1); |
7443 | |
Line 6609... | Line 7444... | ||
6609 | 7444 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
|
6610 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
7445 | 1)) |
6611 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7446 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
Line 6623... | Line 7458... | ||
6623 | * source. |
7458 | * source. |
6624 | */ |
7459 | */ |
6625 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
7460 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6626 | { |
7461 | { |
6627 | uint32_t val; |
7462 | uint32_t val; |
- | 7463 | unsigned long irqflags; |
|
Line 6628... | Line 7464... | ||
6628 | 7464 | ||
Line 6629... | Line 7465... | ||
6629 | val = I915_READ(LCPLL_CTL); |
7465 | val = I915_READ(LCPLL_CTL); |
6630 | 7466 | ||
6631 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
7467 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
Line -... | Line 7468... | ||
- | 7468 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
|
6632 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
7469 | return; |
- | 7470 | ||
- | 7471 | /* |
|
- | 7472 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
|
- | 7473 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
|
- | 7474 | * |
|
- | 7475 | * The other problem is that hsw_restore_lcpll() is called as part of |
|
- | 7476 | * the runtime PM resume sequence, so we can't just call |
|
- | 7477 | * gen6_gt_force_wake_get() because that function calls |
|
6633 | return; |
7478 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount |
- | 7479 | * while we are on the resume sequence. So to solve this problem we have |
|
- | 7480 | * to call special forcewake code that doesn't touch runtime PM and |
|
- | 7481 | * doesn't enable the forcewake delayed work. |
|
6634 | 7482 | */ |
|
- | 7483 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
Line 6635... | Line 7484... | ||
6635 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
7484 | if (dev_priv->uncore.forcewake_count++ == 0) |
6636 | * we'll hang the machine! */ |
7485 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
6637 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
7486 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
6638 | 7487 | ||
6639 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7488 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
Line 6640... | Line 7489... | ||
6640 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
7489 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6641 | I915_WRITE(LCPLL_CTL, val); |
7490 | I915_WRITE(LCPLL_CTL, val); |
6642 | POSTING_READ(LCPLL_CTL); |
7491 | POSTING_READ(LCPLL_CTL); |
6643 | } |
7492 | } |
6644 | - | ||
6645 | val = I915_READ(D_COMP); |
- | |
6646 | val |= D_COMP_COMP_FORCE; |
- | |
6647 | val &= ~D_COMP_COMP_DISABLE; |
- | |
Line 6648... | Line 7493... | ||
6648 | mutex_lock(&dev_priv->rps.hw_lock); |
7493 | |
6649 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
7494 | val = hsw_read_dcomp(dev_priv); |
6650 | DRM_ERROR("Failed to enable D_COMP\n"); |
7495 | val |= D_COMP_COMP_FORCE; |
Line 6666... | Line 7511... | ||
6666 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
7511 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6667 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
7512 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6668 | DRM_ERROR("Switching back to LCPLL failed\n"); |
7513 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6669 | } |
7514 | } |
Line -... | Line 7515... | ||
- | 7515 | ||
- | 7516 | /* See the big comment above. */ |
|
- | 7517 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
6670 | 7518 | if (--dev_priv->uncore.forcewake_count == 0) |
|
- | 7519 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
|
6671 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
7520 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Line -... | Line 7521... | ||
- | 7521 | } |
|
- | 7522 | ||
- | 7523 | /* |
|
- | 7524 | * Package states C8 and deeper are really deep PC states that can only be |
|
- | 7525 | * reached when all the devices on the system allow it, so even if the graphics |
|
- | 7526 | * device allows PC8+, it doesn't mean the system will actually get to these |
|
- | 7527 | * states. Our driver only allows PC8+ when going into runtime PM. |
|
- | 7528 | * |
|
- | 7529 | * The requirements for PC8+ are that all the outputs are disabled, the power |
|
- | 7530 | * well is disabled and most interrupts are disabled, and these are also |
|
- | 7531 | * requirements for runtime PM. When these conditions are met, we manually do |
|
- | 7532 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
|
- | 7533 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
|
- | 7534 | * hang the machine. |
|
- | 7535 | * |
|
- | 7536 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
|
- | 7537 | * the state of some registers, so when we come back from PC8+ we need to |
|
- | 7538 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
|
- | 7539 | * need to take care of the registers kept by RC6. Notice that this happens even |
|
- | 7540 | * if we don't put the device in PCI D3 state (which is what currently happens |
|
- | 7541 | * because of the runtime PM support). |
|
- | 7542 | * |
|
- | 7543 | * For more, read "Display Sequences for Package C8" on the hardware |
|
6672 | } |
7544 | * documentation. |
6673 | 7545 | */ |
|
6674 | void hsw_enable_pc8_work(struct work_struct *__work) |
- | |
6675 | { |
- | |
6676 | struct drm_i915_private *dev_priv = |
- | |
6677 | container_of(to_delayed_work(__work), struct drm_i915_private, |
7546 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
6678 | pc8.enable_work); |
7547 | { |
Line 6679... | Line -... | ||
6679 | struct drm_device *dev = dev_priv->dev; |
- | |
6680 | uint32_t val; |
- | |
6681 | - | ||
6682 | WARN_ON(!HAS_PC8(dev)); |
- | |
6683 | - | ||
6684 | if (dev_priv->pc8.enabled) |
7548 | struct drm_device *dev = dev_priv->dev; |
Line 6685... | Line -... | ||
6685 | return; |
- | |
6686 | - | ||
6687 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7549 | uint32_t val; |
6688 | 7550 | ||
6689 | dev_priv->pc8.enabled = true; |
7551 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6690 | 7552 | ||
6691 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7553 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
Line 6692... | Line 7554... | ||
6692 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7554 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6693 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
- | |
6694 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7555 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6695 | } |
- | |
6696 | - | ||
6697 | lpt_disable_clkout_dp(dev); |
7556 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
Line 6698... | Line -... | ||
6698 | hsw_pc8_disable_interrupts(dev); |
- | |
6699 | hsw_disable_lcpll(dev_priv, true, true); |
- | |
6700 | - | ||
6701 | intel_runtime_pm_put(dev_priv); |
- | |
6702 | } |
- | |
6703 | - | ||
6704 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6705 | { |
- | |
6706 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
- | |
6707 | WARN(dev_priv->pc8.disable_count < 1, |
- | |
6708 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
- | |
6709 | - | ||
6710 | dev_priv->pc8.disable_count--; |
- | |
6711 | if (dev_priv->pc8.disable_count != 0) |
- | |
6712 | return; |
7557 | } |
6713 | 7558 | ||
6714 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
7559 | lpt_disable_clkout_dp(dev); |
6715 | msecs_to_jiffies(i915_pc8_timeout)); |
7560 | hsw_disable_lcpll(dev_priv, true, true); |
Line 6716... | Line -... | ||
6716 | } |
- | |
6717 | - | ||
6718 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6719 | { |
- | |
6720 | struct drm_device *dev = dev_priv->dev; |
- | |
6721 | uint32_t val; |
- | |
6722 | - | ||
6723 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
- | |
6724 | WARN(dev_priv->pc8.disable_count < 0, |
- | |
6725 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
- | |
6726 | - | ||
6727 | dev_priv->pc8.disable_count++; |
- | |
6728 | if (dev_priv->pc8.disable_count != 1) |
- | |
6729 | return; |
- | |
6730 | 7561 | } |
|
Line 6731... | Line -... | ||
6731 | WARN_ON(!HAS_PC8(dev)); |
- | |
6732 | - | ||
6733 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
7562 | |
6734 | if (!dev_priv->pc8.enabled) |
- | |
6735 | return; |
7563 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
Line 6736... | Line 7564... | ||
6736 | 7564 | { |
|
6737 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7565 | struct drm_device *dev = dev_priv->dev; |
6738 | 7566 | uint32_t val; |
|
6739 | intel_runtime_pm_get(dev_priv); |
7567 | |
6740 | 7568 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
|
Line 6741... | Line 7569... | ||
6741 | hsw_restore_lcpll(dev_priv); |
7569 | |
6742 | hsw_pc8_restore_interrupts(dev); |
- | |
6743 | lpt_init_pch_refclk(dev); |
- | |
6744 | - | ||
6745 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
- | |
6746 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
- | |
6747 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
7570 | hsw_restore_lcpll(dev_priv); |
Line 6748... | Line 7571... | ||
6748 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7571 | lpt_init_pch_refclk(dev); |
6749 | } |
7572 | |
6750 | - | ||
6751 | intel_prepare_ddi(dev); |
- | |
6752 | i915_gem_init_swizzling(dev); |
- | |
6753 | mutex_lock(&dev_priv->rps.hw_lock); |
- | |
6754 | gen6_update_ring_freq(dev); |
7573 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6755 | mutex_unlock(&dev_priv->rps.hw_lock); |
- | |
6756 | dev_priv->pc8.enabled = false; |
7574 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
Line 6757... | Line 7575... | ||
6757 | } |
7575 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6758 | 7576 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
|
6759 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6760 | { |
- | |
6761 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6762 | return; |
- | |
6763 | 7577 | } |
|
6764 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6765 | __hsw_enable_package_c8(dev_priv); |
7578 | |
Line 6766... | Line 7579... | ||
6766 | mutex_unlock(&dev_priv->pc8.lock); |
7579 | intel_prepare_ddi(dev); |
- | 7580 | } |
|
- | 7581 | ||
6767 | } |
7582 | static void snb_modeset_global_resources(struct drm_device *dev) |
6768 | - | ||
6769 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
7583 | { |
6770 | { |
- | |
Line 6771... | Line -... | ||
6771 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6772 | return; |
7584 | modeset_update_crtc_power_domains(dev); |
6773 | 7585 | } |
|
Line 6774... | Line -... | ||
6774 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6775 | __hsw_disable_package_c8(dev_priv); |
- | |
6776 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6777 | } |
- | |
6778 | - | ||
6779 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
- | |
6780 | { |
7586 | |
6781 | struct drm_device *dev = dev_priv->dev; |
- | |
Line 6782... | Line 7587... | ||
6782 | struct intel_crtc *crtc; |
7587 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6783 | uint32_t val; |
7588 | { |
Line 6784... | Line -... | ||
6784 | - | ||
6785 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
7589 | modeset_update_crtc_power_domains(dev); |
6786 | if (crtc->base.enabled) |
- | |
6787 | return false; |
- | |
6788 | - | ||
6789 | /* This case is still possible since we have the i915.disable_power_well |
7590 | } |
6790 | * parameter and also the KVMr or something else might be requesting the |
7591 | |
- | 7592 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
|
6791 | * power well. */ |
7593 | int x, int y, |
6792 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
- | |
6793 | if (val != 0) { |
- | |
6794 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
- | |
6795 | return false; |
- | |
6796 | } |
- | |
6797 | - | ||
6798 | return true; |
- | |
6799 | } |
- | |
6800 | 7594 | struct drm_framebuffer *fb) |
|
6801 | /* Since we're called from modeset_global_resources there's no way to |
- | |
6802 | * symmetrically increase and decrease the refcount, so we use |
- | |
6803 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
- | |
6804 | * or not. |
- | |
6805 | */ |
7595 | { |
6806 | static void hsw_update_package_c8(struct drm_device *dev) |
- | |
6807 | { |
- | |
6808 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6809 | bool allow; |
- | |
6810 | - | ||
6811 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6812 | return; |
- | |
6813 | - | ||
6814 | if (!i915_enable_pc8) |
- | |
6815 | return; |
- | |
6816 | - | ||
6817 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6818 | - | ||
6819 | allow = hsw_can_enable_package_c8(dev_priv); |
- | |
6820 | - | ||
6821 | if (allow == dev_priv->pc8.requirements_met) |
- | |
6822 | goto done; |
- | |
6823 | - | ||
6824 | dev_priv->pc8.requirements_met = allow; |
- | |
6825 | - | ||
6826 | if (allow) |
- | |
6827 | __hsw_enable_package_c8(dev_priv); |
- | |
6828 | else |
- | |
6829 | __hsw_disable_package_c8(dev_priv); |
- | |
6830 | - | ||
6831 | done: |
- | |
6832 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6833 | } |
- | |
6834 | 7596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
6835 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
- | |
6836 | { |
- | |
6837 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6838 | return; |
- | |
6839 | - | ||
6840 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6841 | if (!dev_priv->pc8.gpu_idle) { |
- | |
6842 | dev_priv->pc8.gpu_idle = true; |
- | |
6843 | __hsw_enable_package_c8(dev_priv); |
- | |
6844 | } |
- | |
6845 | mutex_unlock(&dev_priv->pc8.lock); |
- | |
6846 | } |
- | |
Line 6847... | Line 7597... | ||
6847 | 7597 | ||
6848 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
- | |
6849 | { |
- | |
6850 | if (!HAS_PC8(dev_priv->dev)) |
- | |
6851 | return; |
- | |
Line 6852... | Line 7598... | ||
6852 | 7598 | if (!intel_ddi_pll_select(intel_crtc)) |
|
Line 6853... | Line -... | ||
6853 | mutex_lock(&dev_priv->pc8.lock); |
- | |
6854 | if (dev_priv->pc8.gpu_idle) { |
- | |
6855 | dev_priv->pc8.gpu_idle = false; |
- | |
6856 | __hsw_disable_package_c8(dev_priv); |
7599 | return -EINVAL; |
Line -... | Line 7600... | ||
- | 7600 | ||
- | 7601 | intel_crtc->lowfreq_avail = false; |
|
- | 7602 | ||
6857 | } |
7603 | return 0; |
- | 7604 | } |
|
- | 7605 | ||
- | 7606 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
|
6858 | mutex_unlock(&dev_priv->pc8.lock); |
7607 | struct intel_crtc_config *pipe_config) |
Line 6859... | Line -... | ||
6859 | } |
- | |
6860 | - | ||
6861 | #define for_each_power_domain(domain, mask) \ |
- | |
6862 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
- | |
6863 | if ((1 << (domain)) & (mask)) |
7608 | { |
6864 | - | ||
6865 | static unsigned long get_pipe_power_domains(struct drm_device *dev, |
- | |
6866 | enum pipe pipe, bool pfit_enabled) |
- | |
6867 | { |
- | |
6868 | unsigned long mask; |
- | |
6869 | enum transcoder transcoder; |
7609 | struct drm_device *dev = crtc->base.dev; |
Line -... | Line 7610... | ||
- | 7610 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
6870 | 7611 | struct intel_shared_dpll *pll; |
|
6871 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
7612 | enum port port; |
Line 6872... | Line -... | ||
6872 | - | ||
6873 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
- | |
6874 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
- | |
6875 | if (pfit_enabled) |
- | |
6876 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
- | |
6877 | 7613 | uint32_t tmp; |
|
6878 | return mask; |
7614 | |
6879 | } |
7615 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
- | 7616 | ||
6880 | 7617 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
|
6881 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
7618 | |
6882 | { |
- | |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6884 | - | ||
6885 | if (dev_priv->power_domains.init_power_on == enable) |
- | |
6886 | return; |
- | |
6887 | - | ||
6888 | if (enable) |
- | |
6889 | intel_display_power_get(dev, POWER_DOMAIN_INIT); |
- | |
6890 | else |
- | |
6891 | intel_display_power_put(dev, POWER_DOMAIN_INIT); |
- | |
6892 | - | ||
6893 | dev_priv->power_domains.init_power_on = enable; |
- | |
6894 | } |
- | |
6895 | - | ||
6896 | static void modeset_update_power_wells(struct drm_device *dev) |
- | |
6897 | { |
- | |
6898 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
- | |
6899 | struct intel_crtc *crtc; |
- | |
6900 | - | ||
6901 | /* |
- | |
6902 | * First get all needed power domains, then put all unneeded, to avoid |
- | |
6903 | * any unnecessary toggling of the power wells. |
- | |
6904 | */ |
- | |
6905 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
- | |
6906 | enum intel_display_power_domain domain; |
- | |
6907 | - | ||
6908 | if (!crtc->base.enabled) |
- | |
6909 | continue; |
- | |
6910 | - | ||
6911 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
- | |
6912 | crtc->pipe, |
- | |
6913 | crtc->config.pch_pfit.enabled); |
- | |
6914 | - | ||
6915 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
- | |
6916 | intel_display_power_get(dev, domain); |
- | |
6917 | } |
- | |
6918 | - | ||
6919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
- | |
6920 | enum intel_display_power_domain domain; |
- | |
6921 | - | ||
6922 | for_each_power_domain(domain, crtc->enabled_power_domains) |
- | |
6923 | intel_display_power_put(dev, domain); |
- | |
6924 | - | ||
6925 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
- | |
6926 | } |
- | |
6927 | 7619 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
|
6928 | intel_display_set_init_power(dev, false); |
- | |
6929 | } |
- | |
6930 | - | ||
Line -... | Line 7620... | ||
- | 7620 | ||
- | 7621 | switch (pipe_config->ddi_pll_sel) { |
|
6931 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7622 | case PORT_CLK_SEL_WRPLL1: |
Line 6932... | Line 7623... | ||
6932 | { |
7623 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; |
6933 | modeset_update_power_wells(dev); |
- | |
6934 | hsw_update_package_c8(dev); |
- | |
6935 | } |
7624 | break; |
6936 | - | ||
6937 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
- | |
6938 | int x, int y, |
- | |
6939 | struct drm_framebuffer *fb) |
- | |
6940 | { |
- | |
6941 | struct drm_device *dev = crtc->dev; |
- | |
6942 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
6944 | int plane = intel_crtc->plane; |
- | |
6945 | int ret; |
- | |
6946 | - | ||
6947 | if (!intel_ddi_pll_select(intel_crtc)) |
- | |
6948 | return -EINVAL; |
7625 | case PORT_CLK_SEL_WRPLL2: |
Line 6949... | Line 7626... | ||
6949 | intel_ddi_pll_enable(intel_crtc); |
7626 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
6950 | 7627 | break; |
|
6951 | if (intel_crtc->config.has_dp_encoder) |
7628 | } |
6952 | intel_dp_set_m_n(intel_crtc); |
7629 | |
6953 | 7630 | if (pipe_config->shared_dpll >= 0) { |
|
6954 | intel_crtc->lowfreq_avail = false; |
7631 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
6955 | 7632 | ||
Line -... | Line 7633... | ||
- | 7633 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
|
- | 7634 | &pipe_config->dpll_hw_state)); |
|
- | 7635 | } |
|
- | 7636 | ||
6956 | intel_set_pipe_timings(intel_crtc); |
7637 | /* |
6957 | 7638 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
|
Line 6958... | Line 7639... | ||
6958 | if (intel_crtc->config.has_pch_encoder) { |
7639 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6959 | intel_cpu_transcoder_set_m_n(intel_crtc, |
7640 | * the PCH transcoder is on. |
Line 7004... | Line 7685... | ||
7004 | 7685 | ||
7005 | if (trans_edp_pipe == crtc->pipe) |
7686 | if (trans_edp_pipe == crtc->pipe) |
7006 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
7687 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
Line 7007... | Line 7688... | ||
7007 | } |
7688 | } |
7008 | 7689 | ||
7009 | if (!intel_display_power_enabled(dev, |
7690 | if (!intel_display_power_enabled(dev_priv, |
Line 7010... | Line 7691... | ||
7010 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
7691 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
7011 | return false; |
7692 | return false; |
7012 | 7693 | ||
Line 7013... | Line -... | ||
7013 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
- | |
7014 | if (!(tmp & PIPECONF_ENABLE)) |
- | |
7015 | return false; |
- | |
7016 | - | ||
7017 | /* |
- | |
7018 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
- | |
7019 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
- | |
7020 | * the PCH transcoder is on. |
- | |
7021 | */ |
- | |
7022 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
- | |
7023 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
- | |
7024 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
- | |
7025 | pipe_config->has_pch_encoder = true; |
- | |
7026 | - | ||
7027 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7694 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
7028 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
- | |
Line 7029... | Line 7695... | ||
7029 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
7695 | if (!(tmp & PIPECONF_ENABLE)) |
Line 7030... | Line 7696... | ||
7030 | 7696 | return false; |
|
7031 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
7697 | |
7032 | } |
7698 | haswell_get_ddi_port_state(crtc, pipe_config); |
Line 7033... | Line 7699... | ||
7033 | 7699 | ||
7034 | intel_get_pipe_timings(crtc, pipe_config); |
7700 | intel_get_pipe_timings(crtc, pipe_config); |
7035 | 7701 | ||
Line 7044... | Line 7710... | ||
7044 | pipe_config->pixel_multiplier = 1; |
7710 | pipe_config->pixel_multiplier = 1; |
Line 7045... | Line 7711... | ||
7045 | 7711 | ||
7046 | return true; |
7712 | return true; |
Line 7047... | Line -... | ||
7047 | } |
- | |
7048 | - | ||
7049 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
- | |
7050 | int x, int y, |
- | |
7051 | struct drm_framebuffer *fb) |
- | |
7052 | { |
- | |
7053 | struct drm_device *dev = crtc->dev; |
- | |
7054 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
7055 | struct intel_encoder *encoder; |
- | |
7056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7057 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
- | |
7058 | int pipe = intel_crtc->pipe; |
- | |
7059 | int ret; |
- | |
7060 | - | ||
7061 | drm_vblank_pre_modeset(dev, pipe); |
- | |
7062 | - | ||
7063 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
- | |
7064 | - | ||
7065 | drm_vblank_post_modeset(dev, pipe); |
- | |
7066 | - | ||
7067 | if (ret != 0) |
- | |
7068 | return ret; |
- | |
7069 | - | ||
7070 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
- | |
7071 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
- | |
7072 | encoder->base.base.id, |
- | |
7073 | drm_get_encoder_name(&encoder->base), |
- | |
7074 | mode->base.id, mode->name); |
- | |
7075 | encoder->mode_set(encoder); |
- | |
7076 | } |
- | |
7077 | - | ||
7078 | return 0; |
- | |
7079 | } |
7713 | } |
7080 | 7714 | ||
7081 | static struct { |
7715 | static struct { |
7082 | int clock; |
7716 | int clock; |
7083 | u32 config; |
7717 | u32 config; |
Line 7190... | Line 7824... | ||
7190 | struct drm_crtc *crtc, |
7824 | struct drm_crtc *crtc, |
7191 | struct drm_display_mode *mode) |
7825 | struct drm_display_mode *mode) |
7192 | { |
7826 | { |
7193 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7827 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7194 | uint8_t *eld = connector->eld; |
7828 | uint8_t *eld = connector->eld; |
7195 | struct drm_device *dev = crtc->dev; |
- | |
7196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7197 | uint32_t eldv; |
7829 | uint32_t eldv; |
7198 | uint32_t i; |
7830 | uint32_t i; |
7199 | int len; |
7831 | int len; |
7200 | int pipe = to_intel_crtc(crtc)->pipe; |
7832 | int pipe = to_intel_crtc(crtc)->pipe; |
7201 | int tmp; |
7833 | int tmp; |
Line 7203... | Line 7835... | ||
7203 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
7835 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
7204 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
7836 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
7205 | int aud_config = HSW_AUD_CFG(pipe); |
7837 | int aud_config = HSW_AUD_CFG(pipe); |
7206 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
7838 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
Line 7207... | Line -... | ||
7207 | - | ||
7208 | - | ||
7209 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
- | |
7210 | 7839 | ||
7211 | /* Audio output enable */ |
7840 | /* Audio output enable */ |
7212 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
7841 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
7213 | tmp = I915_READ(aud_cntrl_st2); |
7842 | tmp = I915_READ(aud_cntrl_st2); |
7214 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
7843 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
- | 7844 | I915_WRITE(aud_cntrl_st2, tmp); |
|
Line 7215... | Line -... | ||
7215 | I915_WRITE(aud_cntrl_st2, tmp); |
- | |
7216 | 7845 | POSTING_READ(aud_cntrl_st2); |
|
Line 7217... | Line 7846... | ||
7217 | /* Wait for 1 vertical blank */ |
7846 | |
7218 | intel_wait_for_vblank(dev, pipe); |
7847 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
7219 | 7848 | ||
7220 | /* Set ELD valid state */ |
7849 | /* Set ELD valid state */ |
Line 7233... | Line 7862... | ||
7233 | I915_WRITE(aud_config, tmp); |
7862 | I915_WRITE(aud_config, tmp); |
Line 7234... | Line 7863... | ||
7234 | 7863 | ||
Line 7235... | Line 7864... | ||
7235 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7864 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7236 | - | ||
Line 7237... | Line 7865... | ||
7237 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
7865 | |
7238 | intel_crtc->eld_vld = true; |
7866 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
7239 | 7867 | ||
7240 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7868 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Line 7380... | Line 8008... | ||
7380 | if (!connector) |
8008 | if (!connector) |
7381 | return; |
8009 | return; |
Line 7382... | Line 8010... | ||
7382 | 8010 | ||
7383 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8011 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7384 | connector->base.id, |
8012 | connector->base.id, |
7385 | drm_get_connector_name(connector), |
8013 | connector->name, |
7386 | connector->encoder->base.id, |
8014 | connector->encoder->base.id, |
Line 7387... | Line 8015... | ||
7387 | drm_get_encoder_name(connector->encoder)); |
8015 | connector->encoder->name); |
Line 7388... | Line 8016... | ||
7388 | 8016 | ||
7389 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
8017 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
Line 7395... | Line 8023... | ||
7395 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8023 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7396 | { |
8024 | { |
7397 | struct drm_device *dev = crtc->dev; |
8025 | struct drm_device *dev = crtc->dev; |
7398 | struct drm_i915_private *dev_priv = dev->dev_private; |
8026 | struct drm_i915_private *dev_priv = dev->dev_private; |
7399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7400 | bool visible = base != 0; |
- | |
7401 | u32 cntl; |
8028 | uint32_t cntl; |
Line 7402... | Line 8029... | ||
7402 | 8029 | ||
7403 | if (intel_crtc->cursor_visible == visible) |
- | |
7404 | return; |
- | |
7405 | - | ||
7406 | cntl = I915_READ(_CURACNTR); |
- | |
7407 | if (visible) { |
8030 | if (base != intel_crtc->cursor_base) { |
7408 | /* On these chipsets we can only modify the base whilst |
8031 | /* On these chipsets we can only modify the base whilst |
7409 | * the cursor is disabled. |
8032 | * the cursor is disabled. |
- | 8033 | */ |
|
- | 8034 | if (intel_crtc->cursor_cntl) { |
|
- | 8035 | I915_WRITE(_CURACNTR, 0); |
|
- | 8036 | POSTING_READ(_CURACNTR); |
|
- | 8037 | intel_crtc->cursor_cntl = 0; |
|
- | 8038 | } |
|
7410 | */ |
8039 | |
- | 8040 | I915_WRITE(_CURABASE, base); |
|
- | 8041 | POSTING_READ(_CURABASE); |
|
Line 7411... | Line -... | ||
7411 | I915_WRITE(_CURABASE, base); |
- | |
7412 | 8042 | } |
|
- | 8043 | ||
- | 8044 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
|
7413 | cntl &= ~(CURSOR_FORMAT_MASK); |
8045 | cntl = 0; |
7414 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
8046 | if (base) |
7415 | cntl |= CURSOR_ENABLE | |
8047 | cntl = (CURSOR_ENABLE | |
7416 | CURSOR_GAMMA_ENABLE | |
- | |
7417 | CURSOR_FORMAT_ARGB; |
8048 | CURSOR_GAMMA_ENABLE | |
7418 | } else |
8049 | CURSOR_FORMAT_ARGB); |
7419 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
- | |
- | 8050 | if (intel_crtc->cursor_cntl != cntl) { |
|
7420 | I915_WRITE(_CURACNTR, cntl); |
8051 | I915_WRITE(_CURACNTR, cntl); |
- | 8052 | POSTING_READ(_CURACNTR); |
|
7421 | 8053 | intel_crtc->cursor_cntl = cntl; |
|
Line 7422... | Line 8054... | ||
7422 | intel_crtc->cursor_visible = visible; |
8054 | } |
7423 | } |
8055 | } |
7424 | 8056 | ||
7425 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
8057 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
7426 | { |
8058 | { |
7427 | struct drm_device *dev = crtc->dev; |
8059 | struct drm_device *dev = crtc->dev; |
7428 | struct drm_i915_private *dev_priv = dev->dev_private; |
8060 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 7429... | Line -... | ||
7429 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7430 | int pipe = intel_crtc->pipe; |
8061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7431 | bool visible = base != 0; |
8062 | int pipe = intel_crtc->pipe; |
- | 8063 | uint32_t cntl; |
|
- | 8064 | ||
- | 8065 | cntl = 0; |
|
- | 8066 | if (base) { |
|
- | 8067 | cntl = MCURSOR_GAMMA_ENABLE; |
|
- | 8068 | switch (intel_crtc->cursor_width) { |
|
7432 | 8069 | case 64: |
|
- | 8070 | cntl |= CURSOR_MODE_64_ARGB_AX; |
|
- | 8071 | break; |
|
7433 | if (intel_crtc->cursor_visible != visible) { |
8072 | case 128: |
- | 8073 | cntl |= CURSOR_MODE_128_ARGB_AX; |
|
- | 8074 | break; |
|
- | 8075 | case 256: |
|
- | 8076 | cntl |= CURSOR_MODE_256_ARGB_AX; |
|
- | 8077 | break; |
|
7434 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
8078 | default: |
7435 | if (base) { |
- | |
7436 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
- | |
7437 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
- | |
7438 | cntl |= pipe << 28; /* Connect to correct pipe */ |
8079 | WARN_ON(1); |
- | 8080 | return; |
|
7439 | } else { |
8081 | } |
7440 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
- | |
- | 8082 | cntl |= pipe << 28; /* Connect to correct pipe */ |
|
7441 | cntl |= CURSOR_MODE_DISABLE; |
8083 | } |
7442 | } |
8084 | if (intel_crtc->cursor_cntl != cntl) { |
- | 8085 | I915_WRITE(CURCNTR(pipe), cntl); |
|
7443 | I915_WRITE(CURCNTR(pipe), cntl); |
8086 | POSTING_READ(CURCNTR(pipe)); |
7444 | - | ||
7445 | intel_crtc->cursor_visible = visible; |
8087 | intel_crtc->cursor_cntl = cntl; |
7446 | } |
8088 | } |
7447 | /* and commit changes on next vblank */ |
8089 | |
Line 7448... | Line 8090... | ||
7448 | POSTING_READ(CURCNTR(pipe)); |
8090 | /* and commit changes on next vblank */ |
7449 | I915_WRITE(CURBASE(pipe), base); |
8091 | I915_WRITE(CURBASE(pipe), base); |
7450 | POSTING_READ(CURBASE(pipe)); |
8092 | POSTING_READ(CURBASE(pipe)); |
7451 | } |
8093 | } |
7452 | 8094 | ||
7453 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8095 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7454 | { |
8096 | { |
Line 7455... | Line -... | ||
7455 | struct drm_device *dev = crtc->dev; |
- | |
7456 | struct drm_i915_private *dev_priv = dev->dev_private; |
8097 | struct drm_device *dev = crtc->dev; |
7457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8098 | struct drm_i915_private *dev_priv = dev->dev_private; |
7458 | int pipe = intel_crtc->pipe; |
8099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 8100 | int pipe = intel_crtc->pipe; |
|
- | 8101 | uint32_t cntl; |
|
7459 | bool visible = base != 0; |
8102 | |
- | 8103 | cntl = 0; |
|
7460 | 8104 | if (base) { |
|
7461 | if (intel_crtc->cursor_visible != visible) { |
8105 | cntl = MCURSOR_GAMMA_ENABLE; |
- | 8106 | switch (intel_crtc->cursor_width) { |
|
- | 8107 | case 64: |
|
7462 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
8108 | cntl |= CURSOR_MODE_64_ARGB_AX; |
- | 8109 | break; |
|
- | 8110 | case 128: |
|
- | 8111 | cntl |= CURSOR_MODE_128_ARGB_AX; |
|
- | 8112 | break; |
|
7463 | if (base) { |
8113 | case 256: |
7464 | cntl &= ~CURSOR_MODE; |
- | |
7465 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
- | |
7466 | } else { |
- | |
7467 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
8114 | cntl |= CURSOR_MODE_256_ARGB_AX; |
- | 8115 | break; |
|
7468 | cntl |= CURSOR_MODE_DISABLE; |
8116 | default: |
Line -... | Line 8117... | ||
- | 8117 | WARN_ON(1); |
|
- | 8118 | return; |
|
- | 8119 | } |
|
7469 | } |
8120 | } |
7470 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
8121 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
- | 8122 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
|
7471 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
8123 | |
7472 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
- | |
7473 | } |
8124 | if (intel_crtc->cursor_cntl != cntl) { |
7474 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
8125 | I915_WRITE(CURCNTR(pipe), cntl); |
7475 | 8126 | POSTING_READ(CURCNTR(pipe)); |
|
Line 7476... | Line 8127... | ||
7476 | intel_crtc->cursor_visible = visible; |
8127 | intel_crtc->cursor_cntl = cntl; |
7477 | } |
8128 | } |
7478 | /* and commit changes on next vblank */ |
8129 | |
7479 | POSTING_READ(CURCNTR_IVB(pipe)); |
8130 | /* and commit changes on next vblank */ |
7480 | I915_WRITE(CURBASE_IVB(pipe), base); |
8131 | I915_WRITE(CURBASE(pipe), base); |
7481 | POSTING_READ(CURBASE_IVB(pipe)); |
8132 | POSTING_READ(CURBASE(pipe)); |
7482 | } |
8133 | } |
7483 | 8134 | ||
7484 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
8135 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
7485 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8136 | void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7486 | bool on) |
8137 | bool on) |
7487 | { |
- | |
Line 7488... | Line 8138... | ||
7488 | struct drm_device *dev = crtc->dev; |
8138 | { |
7489 | struct drm_i915_private *dev_priv = dev->dev_private; |
8139 | struct drm_device *dev = crtc->dev; |
Line 7490... | Line 8140... | ||
7490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8140 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 7519... | Line 8169... | ||
7519 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
8169 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
7520 | y = -y; |
8170 | y = -y; |
7521 | } |
8171 | } |
7522 | pos |= y << CURSOR_Y_SHIFT; |
8172 | pos |= y << CURSOR_Y_SHIFT; |
Line 7523... | Line -... | ||
7523 | - | ||
7524 | visible = base != 0; |
8173 | |
7525 | if (!visible && !intel_crtc->cursor_visible) |
8174 | if (base == 0 && intel_crtc->cursor_base == 0) |
Line 7526... | Line -... | ||
7526 | return; |
- | |
7527 | - | ||
7528 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
- | |
7529 | I915_WRITE(CURPOS_IVB(pipe), pos); |
- | |
7530 | ivb_update_cursor(crtc, base); |
8175 | return; |
- | 8176 | ||
- | 8177 | I915_WRITE(CURPOS(pipe), pos); |
|
- | 8178 | ||
- | 8179 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
- | 8180 | ivb_update_cursor(crtc, base); |
|
- | 8181 | else if (IS_845G(dev) || IS_I865G(dev)) |
|
7531 | } else { |
8182 | i845_update_cursor(crtc, base); |
7532 | I915_WRITE(CURPOS(pipe), pos); |
- | |
- | 8183 | else |
|
7533 | i9xx_update_cursor(crtc, base); |
8184 | i9xx_update_cursor(crtc, base); |
Line -... | Line 8185... | ||
- | 8185 | intel_crtc->cursor_base = base; |
|
- | 8186 | } |
|
7534 | } |
8187 | |
- | 8188 | /* |
|
- | 8189 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object |
|
- | 8190 | * |
|
- | 8191 | * Note that the object's reference will be consumed if the update fails. If |
|
7535 | } |
8192 | * the update succeeds, the reference of the old object (if any) will be |
7536 | 8193 | * consumed. |
|
7537 | #if 0 |
- | |
7538 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
8194 | */ |
7539 | struct drm_file *file, |
8195 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, |
7540 | uint32_t handle, |
8196 | struct drm_i915_gem_object *obj, |
7541 | uint32_t width, uint32_t height) |
8197 | uint32_t width, uint32_t height) |
7542 | { |
8198 | { |
7543 | struct drm_device *dev = crtc->dev; |
8199 | struct drm_device *dev = crtc->dev; |
- | 8200 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
7544 | struct drm_i915_private *dev_priv = dev->dev_private; |
8201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8202 | enum pipe pipe = intel_crtc->pipe; |
Line 7546... | Line 8203... | ||
7546 | struct drm_i915_gem_object *obj; |
8203 | unsigned old_width; |
7547 | uint32_t addr; |
8204 | uint32_t addr; |
7548 | int ret; |
8205 | int ret; |
7549 | 8206 | ||
7550 | /* if we want to turn off the cursor ignore width and height */ |
8207 | /* if we want to turn off the cursor ignore width and height */ |
7551 | if (!handle) { |
8208 | if (!obj) { |
7552 | DRM_DEBUG_KMS("cursor off\n"); |
8209 | DRM_DEBUG_KMS("cursor off\n"); |
7553 | addr = 0; |
8210 | addr = 0; |
Line 7554... | Line 8211... | ||
7554 | obj = NULL; |
8211 | obj = NULL; |
7555 | mutex_lock(&dev->struct_mutex); |
8212 | mutex_lock(&dev->struct_mutex); |
- | 8213 | goto finish; |
|
- | 8214 | } |
|
7556 | goto finish; |
8215 | |
7557 | } |
8216 | /* Check for which cursor types we support */ |
7558 | 8217 | if (!((width == 64 && height == 64) || |
|
Line 7559... | Line -... | ||
7559 | /* Currently we only support 64x64 cursors */ |
- | |
7560 | if (width != 64 || height != 64) { |
- | |
7561 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
- | |
7562 | return -EINVAL; |
- | |
7563 | } |
8218 | (width == 128 && height == 128 && !IS_GEN2(dev)) || |
7564 | 8219 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { |
|
7565 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
8220 | DRM_DEBUG("Cursor dimension not supported\n"); |
7566 | if (&obj->base == NULL) |
8221 | return -EINVAL; |
7567 | return -ENOENT; |
8222 | } |
Line 7568... | Line 8223... | ||
7568 | 8223 | ||
7569 | if (obj->base.size < width * height * 4) { |
8224 | if (obj->base.size < width * height * 4) { |
7570 | DRM_ERROR("buffer is to small\n"); |
8225 | DRM_DEBUG_KMS("buffer is too small\n"); |
7571 | ret = -ENOMEM; |
8226 | ret = -ENOMEM; |
Line 7572... | Line 8227... | ||
7572 | goto fail; |
8227 | goto fail; |
7573 | } |
8228 | } |
7574 | 8229 | ||
7575 | /* we only need to pin inside GTT if cursor is non-phy */ |
8230 | /* we only need to pin inside GTT if cursor is non-phy */ |
7576 | mutex_lock(&dev->struct_mutex); |
8231 | mutex_lock(&dev->struct_mutex); |
Line 7577... | Line 8232... | ||
7577 | if (!dev_priv->info->cursor_needs_physical) { |
8232 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
Line 7592... | Line 8247... | ||
7592 | if (need_vtd_wa(dev)) |
8247 | if (need_vtd_wa(dev)) |
7593 | alignment = 64*1024; |
8248 | alignment = 64*1024; |
Line 7594... | Line 8249... | ||
7594 | 8249 | ||
7595 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
8250 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
7596 | if (ret) { |
8251 | if (ret) { |
7597 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
8252 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
7598 | goto fail_locked; |
8253 | goto fail_locked; |
Line 7599... | Line 8254... | ||
7599 | } |
8254 | } |
7600 | 8255 | ||
7601 | ret = i915_gem_object_put_fence(obj); |
8256 | ret = i915_gem_object_put_fence(obj); |
7602 | if (ret) { |
8257 | if (ret) { |
7603 | DRM_ERROR("failed to release fence for cursor"); |
8258 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
Line 7604... | Line 8259... | ||
7604 | goto fail_unpin; |
8259 | goto fail_unpin; |
7605 | } |
8260 | } |
7606 | 8261 | ||
7607 | addr = i915_gem_obj_ggtt_offset(obj); |
8262 | addr = i915_gem_obj_ggtt_offset(obj); |
7608 | } else { |
- | |
7609 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
- | |
7610 | ret = i915_gem_attach_phys_object(dev, obj, |
8263 | } else { |
7611 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
8264 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
7612 | align); |
8265 | // ret = i915_gem_object_attach_phys(obj, align); |
7613 | if (ret) { |
8266 | // if (ret) { |
7614 | DRM_ERROR("failed to attach phys object\n"); |
8267 | // DRM_DEBUG_KMS("failed to attach phys object\n"); |
7615 | goto fail_locked; |
8268 | // goto fail_locked; |
Line 7616... | Line 8269... | ||
7616 | } |
8269 | // } |
7617 | addr = obj->phys_obj->handle->busaddr; |
8270 | // addr = obj->phys_handle->busaddr; |
Line 7618... | Line 8271... | ||
7618 | } |
8271 | } |
7619 | 8272 | ||
7620 | if (IS_GEN2(dev)) |
8273 | if (IS_GEN2(dev)) |
7621 | I915_WRITE(CURSIZE, (height << 12) | width); |
- | |
7622 | - | ||
7623 | finish: |
- | |
7624 | if (intel_crtc->cursor_bo) { |
8274 | I915_WRITE(CURSIZE, (height << 12) | width); |
7625 | if (dev_priv->info->cursor_needs_physical) { |
- | |
7626 | if (intel_crtc->cursor_bo != obj) |
8275 | |
Line -... | Line 8276... | ||
- | 8276 | finish: |
|
- | 8277 | if (intel_crtc->cursor_bo) { |
|
7627 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
8278 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
Line -... | Line 8279... | ||
- | 8279 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
|
- | 8280 | } |
|
7628 | } else |
8281 | |
7629 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
8282 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
7630 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
8283 | INTEL_FRONTBUFFER_CURSOR(pipe)); |
7631 | } |
8284 | mutex_unlock(&dev->struct_mutex); |
Line 7632... | Line 8285... | ||
7632 | 8285 | ||
- | 8286 | old_width = intel_crtc->cursor_width; |
|
- | 8287 | ||
7633 | mutex_unlock(&dev->struct_mutex); |
8288 | intel_crtc->cursor_addr = addr; |
- | 8289 | intel_crtc->cursor_bo = obj; |
|
Line 7634... | Line 8290... | ||
7634 | 8290 | intel_crtc->cursor_width = width; |
|
7635 | intel_crtc->cursor_addr = addr; |
8291 | intel_crtc->cursor_height = height; |
7636 | intel_crtc->cursor_bo = obj; |
8292 | |
7637 | intel_crtc->cursor_width = width; |
8293 | if (intel_crtc->active) { |
7638 | intel_crtc->cursor_height = height; |
8294 | if (old_width != width) |
7639 | 8295 | intel_update_watermarks(crtc); |
|
7640 | if (intel_crtc->active) |
8296 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7641 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
8297 | } |
7642 | 8298 | ||
7643 | return 0; |
- | |
7644 | fail_unpin: |
- | |
7645 | i915_gem_object_unpin_from_display_plane(obj); |
- | |
7646 | fail_locked: |
- | |
7647 | mutex_unlock(&dev->struct_mutex); |
- | |
7648 | fail: |
- | |
7649 | drm_gem_object_unreference_unlocked(&obj->base); |
- | |
7650 | return ret; |
- | |
7651 | } |
- | |
7652 | #endif |
- | |
7653 | - | ||
7654 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
- | |
7655 | { |
- | |
7656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
Line 7657... | Line 8299... | ||
7657 | 8299 | return 0; |
|
7658 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
8300 | fail_unpin: |
7659 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); |
8301 | i915_gem_object_unpin_from_display_plane(obj); |
7660 | 8302 | fail_locked: |
|
Line 7684... | Line 8326... | ||
7684 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
8326 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7685 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
8327 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7686 | }; |
8328 | }; |
Line 7687... | Line 8329... | ||
7687 | 8329 | ||
7688 | struct drm_framebuffer * |
8330 | struct drm_framebuffer * |
7689 | intel_framebuffer_create(struct drm_device *dev, |
8331 | __intel_framebuffer_create(struct drm_device *dev, |
7690 | struct drm_mode_fb_cmd2 *mode_cmd, |
8332 | struct drm_mode_fb_cmd2 *mode_cmd, |
7691 | struct drm_i915_gem_object *obj) |
8333 | struct drm_i915_gem_object *obj) |
7692 | { |
8334 | { |
7693 | struct intel_framebuffer *intel_fb; |
8335 | struct intel_framebuffer *intel_fb; |
Line 7697... | Line 8339... | ||
7697 | if (!intel_fb) { |
8339 | if (!intel_fb) { |
7698 | drm_gem_object_unreference_unlocked(&obj->base); |
8340 | drm_gem_object_unreference_unlocked(&obj->base); |
7699 | return ERR_PTR(-ENOMEM); |
8341 | return ERR_PTR(-ENOMEM); |
7700 | } |
8342 | } |
Line 7701... | Line -... | ||
7701 | - | ||
7702 | ret = i915_mutex_lock_interruptible(dev); |
- | |
7703 | if (ret) |
- | |
7704 | goto err; |
- | |
7705 | 8343 | ||
7706 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
- | |
7707 | mutex_unlock(&dev->struct_mutex); |
8344 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7708 | if (ret) |
8345 | if (ret) |
Line 7709... | Line 8346... | ||
7709 | goto err; |
8346 | goto err; |
7710 | 8347 | ||
Line 7714... | Line 8351... | ||
7714 | kfree(intel_fb); |
8351 | kfree(intel_fb); |
Line 7715... | Line 8352... | ||
7715 | 8352 | ||
7716 | return ERR_PTR(ret); |
8353 | return ERR_PTR(ret); |
Line -... | Line 8354... | ||
- | 8354 | } |
|
- | 8355 | ||
- | 8356 | static struct drm_framebuffer * |
|
- | 8357 | intel_framebuffer_create(struct drm_device *dev, |
|
- | 8358 | struct drm_mode_fb_cmd2 *mode_cmd, |
|
- | 8359 | struct drm_i915_gem_object *obj) |
|
- | 8360 | { |
|
- | 8361 | struct drm_framebuffer *fb; |
|
- | 8362 | int ret; |
|
- | 8363 | ||
- | 8364 | ret = i915_mutex_lock_interruptible(dev); |
|
- | 8365 | if (ret) |
|
- | 8366 | return ERR_PTR(ret); |
|
- | 8367 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
|
- | 8368 | mutex_unlock(&dev->struct_mutex); |
|
- | 8369 | ||
- | 8370 | return fb; |
|
7717 | } |
8371 | } |
7718 | 8372 | ||
7719 | static u32 |
8373 | static u32 |
7720 | intel_framebuffer_pitch_for_width(int width, int bpp) |
8374 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7721 | { |
8375 | { |
Line 7725... | Line 8379... | ||
7725 | 8379 | ||
7726 | static u32 |
8380 | static u32 |
7727 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
8381 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7728 | { |
8382 | { |
7729 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
8383 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7730 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
8384 | return PAGE_ALIGN(pitch * mode->vdisplay); |
Line 7731... | Line 8385... | ||
7731 | } |
8385 | } |
7732 | 8386 | ||
7733 | static struct drm_framebuffer * |
8387 | static struct drm_framebuffer * |
7734 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
8388 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7735 | struct drm_display_mode *mode, |
8389 | struct drm_display_mode *mode, |
7736 | int depth, int bpp) |
8390 | int depth, int bpp) |
7737 | { |
8391 | { |
Line -... | Line 8392... | ||
- | 8392 | struct drm_i915_gem_object *obj; |
|
- | 8393 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
|
7738 | struct drm_i915_gem_object *obj; |
8394 | |
- | 8395 | obj = i915_gem_alloc_object(dev, |
|
- | 8396 | intel_framebuffer_size_for_mode(mode, bpp)); |
|
- | 8397 | if (obj == NULL) |
|
- | 8398 | return ERR_PTR(-ENOMEM); |
|
- | 8399 | ||
- | 8400 | mode_cmd.width = mode->hdisplay; |
|
- | 8401 | mode_cmd.height = mode->vdisplay; |
|
- | 8402 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
|
- | 8403 | bpp); |
|
7739 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
8404 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Line 7740... | Line 8405... | ||
7740 | 8405 | ||
7741 | return NULL; |
8406 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
7742 | } |
8407 | } |
Line 7748... | Line 8413... | ||
7748 | #ifdef CONFIG_DRM_I915_FBDEV |
8413 | #ifdef CONFIG_DRM_I915_FBDEV |
7749 | struct drm_i915_private *dev_priv = dev->dev_private; |
8414 | struct drm_i915_private *dev_priv = dev->dev_private; |
7750 | struct drm_i915_gem_object *obj; |
8415 | struct drm_i915_gem_object *obj; |
7751 | struct drm_framebuffer *fb; |
8416 | struct drm_framebuffer *fb; |
Line 7752... | Line 8417... | ||
7752 | 8417 | ||
7753 | if (dev_priv->fbdev == NULL) |
8418 | if (!dev_priv->fbdev) |
Line 7754... | Line 8419... | ||
7754 | return NULL; |
8419 | return NULL; |
7755 | - | ||
7756 | obj = dev_priv->fbdev->ifb.obj; |
8420 | |
Line -... | Line 8421... | ||
- | 8421 | if (!dev_priv->fbdev->fb) |
|
- | 8422 | return NULL; |
|
- | 8423 | ||
7757 | if (obj == NULL) |
8424 | obj = dev_priv->fbdev->fb->obj; |
7758 | return NULL; |
8425 | BUG_ON(!obj); |
7759 | 8426 | ||
7760 | fb = &dev_priv->fbdev->ifb.base; |
8427 | fb = &dev_priv->fbdev->fb->base; |
Line 7761... | Line 8428... | ||
7761 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8428 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
Line 7771... | Line 8438... | ||
7771 | #endif |
8438 | #endif |
7772 | } |
8439 | } |
Line 7773... | Line 8440... | ||
7773 | 8440 | ||
7774 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
8441 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7775 | struct drm_display_mode *mode, |
8442 | struct drm_display_mode *mode, |
- | 8443 | struct intel_load_detect_pipe *old, |
|
7776 | struct intel_load_detect_pipe *old) |
8444 | struct drm_modeset_acquire_ctx *ctx) |
7777 | { |
8445 | { |
7778 | struct intel_crtc *intel_crtc; |
8446 | struct intel_crtc *intel_crtc; |
7779 | struct intel_encoder *intel_encoder = |
8447 | struct intel_encoder *intel_encoder = |
7780 | intel_attached_encoder(connector); |
8448 | intel_attached_encoder(connector); |
7781 | struct drm_crtc *possible_crtc; |
8449 | struct drm_crtc *possible_crtc; |
7782 | struct drm_encoder *encoder = &intel_encoder->base; |
8450 | struct drm_encoder *encoder = &intel_encoder->base; |
7783 | struct drm_crtc *crtc = NULL; |
8451 | struct drm_crtc *crtc = NULL; |
7784 | struct drm_device *dev = encoder->dev; |
8452 | struct drm_device *dev = encoder->dev; |
- | 8453 | struct drm_framebuffer *fb; |
|
7785 | struct drm_framebuffer *fb; |
8454 | struct drm_mode_config *config = &dev->mode_config; |
Line 7786... | Line 8455... | ||
7786 | int i = -1; |
8455 | int ret, i = -1; |
7787 | 8456 | ||
7788 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8457 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
- | 8458 | connector->base.id, connector->name, |
|
- | 8459 | encoder->base.id, encoder->name); |
|
- | 8460 | ||
- | 8461 | retry: |
|
- | 8462 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
|
Line 7789... | Line 8463... | ||
7789 | connector->base.id, drm_get_connector_name(connector), |
8463 | if (ret) |
7790 | encoder->base.id, drm_get_encoder_name(encoder)); |
8464 | goto fail_unlock; |
7791 | 8465 | ||
7792 | /* |
8466 | /* |
Line 7801... | Line 8475... | ||
7801 | 8475 | ||
7802 | /* See if we already have a CRTC for this connector */ |
8476 | /* See if we already have a CRTC for this connector */ |
7803 | if (encoder->crtc) { |
8477 | if (encoder->crtc) { |
Line 7804... | Line 8478... | ||
7804 | crtc = encoder->crtc; |
8478 | crtc = encoder->crtc; |
- | 8479 | ||
- | 8480 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
|
Line 7805... | Line 8481... | ||
7805 | 8481 | if (ret) |
|
7806 | mutex_lock(&crtc->mutex); |
8482 | goto fail_unlock; |
Line 7807... | Line 8483... | ||
7807 | 8483 | ||
Line 7814... | Line 8490... | ||
7814 | 8490 | ||
7815 | return true; |
8491 | return true; |
Line 7816... | Line 8492... | ||
7816 | } |
8492 | } |
7817 | 8493 | ||
7818 | /* Find an unused one (if possible) */ |
8494 | /* Find an unused one (if possible) */ |
7819 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
8495 | for_each_crtc(dev, possible_crtc) { |
7820 | i++; |
8496 | i++; |
7821 | if (!(encoder->possible_crtcs & (1 << i))) |
8497 | if (!(encoder->possible_crtcs & (1 << i))) |
- | 8498 | continue; |
|
- | 8499 | if (possible_crtc->enabled) |
|
- | 8500 | continue; |
|
- | 8501 | /* This can occur when applying the pipe A quirk on resume. */ |
|
- | 8502 | if (to_intel_crtc(possible_crtc)->new_enabled) |
|
7822 | continue; |
8503 | continue; |
7823 | if (!possible_crtc->enabled) { |
8504 | |
7824 | crtc = possible_crtc; |
8505 | crtc = possible_crtc; |
7825 | break; |
- | |
Line 7826... | Line 8506... | ||
7826 | } |
8506 | break; |
7827 | } |
8507 | } |
7828 | 8508 | ||
7829 | /* |
8509 | /* |
7830 | * If we didn't find an unused CRTC, don't use any. |
8510 | * If we didn't find an unused CRTC, don't use any. |
7831 | */ |
8511 | */ |
7832 | if (!crtc) { |
8512 | if (!crtc) { |
Line 7833... | Line 8513... | ||
7833 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8513 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
- | 8514 | goto fail_unlock; |
|
- | 8515 | } |
|
7834 | return false; |
8516 | |
7835 | } |
8517 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
Line 7836... | Line 8518... | ||
7836 | 8518 | if (ret) |
|
- | 8519 | goto fail_unlock; |
|
- | 8520 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
|
7837 | mutex_lock(&crtc->mutex); |
8521 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7838 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8522 | |
7839 | to_intel_connector(connector)->new_encoder = intel_encoder; |
8523 | intel_crtc = to_intel_crtc(crtc); |
Line 7840... | Line 8524... | ||
7840 | 8524 | intel_crtc->new_enabled = true; |
|
Line 7860... | Line 8544... | ||
7860 | old->release_fb = fb; |
8544 | old->release_fb = fb; |
7861 | } else |
8545 | } else |
7862 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
8546 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7863 | if (IS_ERR(fb)) { |
8547 | if (IS_ERR(fb)) { |
7864 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
8548 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7865 | mutex_unlock(&crtc->mutex); |
- | |
7866 | return false; |
8549 | goto fail; |
7867 | } |
8550 | } |
Line 7868... | Line 8551... | ||
7868 | 8551 | ||
7869 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
8552 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7870 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
8553 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7871 | if (old->release_fb) |
8554 | if (old->release_fb) |
7872 | old->release_fb->funcs->destroy(old->release_fb); |
- | |
7873 | mutex_unlock(&crtc->mutex); |
8555 | old->release_fb->funcs->destroy(old->release_fb); |
7874 | return false; |
8556 | goto fail; |
Line 7875... | Line 8557... | ||
7875 | } |
8557 | } |
7876 | 8558 | ||
7877 | /* let the connector get through one full cycle before testing */ |
8559 | /* let the connector get through one full cycle before testing */ |
- | 8560 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 8561 | return true; |
|
- | 8562 | ||
- | 8563 | fail: |
|
- | 8564 | intel_crtc->new_enabled = crtc->enabled; |
|
- | 8565 | if (intel_crtc->new_enabled) |
|
- | 8566 | intel_crtc->new_config = &intel_crtc->config; |
|
- | 8567 | else |
|
- | 8568 | intel_crtc->new_config = NULL; |
|
- | 8569 | fail_unlock: |
|
- | 8570 | if (ret == -EDEADLK) { |
|
- | 8571 | drm_modeset_backoff(ctx); |
|
- | 8572 | goto retry; |
|
- | 8573 | } |
|
7878 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
8574 | |
Line 7879... | Line 8575... | ||
7879 | return true; |
8575 | return false; |
7880 | } |
8576 | } |
7881 | 8577 | ||
7882 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8578 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7883 | struct intel_load_detect_pipe *old) |
8579 | struct intel_load_detect_pipe *old) |
7884 | { |
8580 | { |
7885 | struct intel_encoder *intel_encoder = |
8581 | struct intel_encoder *intel_encoder = |
- | 8582 | intel_attached_encoder(connector); |
|
Line 7886... | Line 8583... | ||
7886 | intel_attached_encoder(connector); |
8583 | struct drm_encoder *encoder = &intel_encoder->base; |
7887 | struct drm_encoder *encoder = &intel_encoder->base; |
8584 | struct drm_crtc *crtc = encoder->crtc; |
7888 | struct drm_crtc *crtc = encoder->crtc; |
8585 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 7889... | Line 8586... | ||
7889 | 8586 | ||
7890 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8587 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7891 | connector->base.id, drm_get_connector_name(connector), |
8588 | connector->base.id, connector->name, |
- | 8589 | encoder->base.id, encoder->name); |
|
- | 8590 | ||
7892 | encoder->base.id, drm_get_encoder_name(encoder)); |
8591 | if (old->load_detect_temp) { |
Line 7893... | Line 8592... | ||
7893 | 8592 | to_intel_connector(connector)->new_encoder = NULL; |
|
7894 | if (old->load_detect_temp) { |
8593 | intel_encoder->new_crtc = NULL; |
7895 | to_intel_connector(connector)->new_encoder = NULL; |
8594 | intel_crtc->new_enabled = false; |
7896 | intel_encoder->new_crtc = NULL; |
8595 | intel_crtc->new_config = NULL; |
Line 7897... | Line -... | ||
7897 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
- | |
7898 | 8596 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
|
7899 | if (old->release_fb) { |
8597 | |
Line 7900... | Line 8598... | ||
7900 | drm_framebuffer_unregister_private(old->release_fb); |
8598 | if (old->release_fb) { |
7901 | drm_framebuffer_unreference(old->release_fb); |
8599 | drm_framebuffer_unregister_private(old->release_fb); |
7902 | } |
8600 | drm_framebuffer_unreference(old->release_fb); |
7903 | - | ||
7904 | mutex_unlock(&crtc->mutex); |
- | |
7905 | return; |
8601 | } |
Line 7906... | Line 8602... | ||
7906 | } |
8602 | |
7907 | 8603 | return; |
|
7908 | /* Switch crtc and encoder back off if necessary */ |
8604 | } |
Line 8101... | Line 8797... | ||
8101 | drm_mode_set_name(mode); |
8797 | drm_mode_set_name(mode); |
Line 8102... | Line 8798... | ||
8102 | 8798 | ||
8103 | return mode; |
8799 | return mode; |
Line 8104... | Line 8800... | ||
8104 | } |
8800 | } |
- | 8801 | ||
8105 | 8802 | static void intel_increase_pllclock(struct drm_device *dev, |
|
8106 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
- | |
8107 | { |
8803 | enum pipe pipe) |
8108 | struct drm_device *dev = crtc->dev; |
- | |
8109 | drm_i915_private_t *dev_priv = dev->dev_private; |
- | |
8110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8804 | { |
8111 | int pipe = intel_crtc->pipe; |
8805 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 8112... | Line 8806... | ||
8112 | int dpll_reg = DPLL(pipe); |
8806 | int dpll_reg = DPLL(pipe); |
8113 | int dpll; |
8807 | int dpll; |
Line 8114... | Line 8808... | ||
8114 | 8808 | ||
8115 | if (HAS_PCH_SPLIT(dev)) |
8809 | if (!HAS_GMCH_DISPLAY(dev)) |
Line 8135... | Line 8829... | ||
8135 | } |
8829 | } |
Line 8136... | Line 8830... | ||
8136 | 8830 | ||
8137 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8831 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8138 | { |
8832 | { |
8139 | struct drm_device *dev = crtc->dev; |
8833 | struct drm_device *dev = crtc->dev; |
8140 | drm_i915_private_t *dev_priv = dev->dev_private; |
8834 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 8141... | Line 8835... | ||
8141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8142 | 8836 | ||
Line 8143... | Line 8837... | ||
8143 | if (HAS_PCH_SPLIT(dev)) |
8837 | if (!HAS_GMCH_DISPLAY(dev)) |
8144 | return; |
8838 | return; |
Line 8172... | Line 8866... | ||
8172 | 8866 | ||
8173 | void intel_mark_busy(struct drm_device *dev) |
8867 | void intel_mark_busy(struct drm_device *dev) |
8174 | { |
8868 | { |
Line -... | Line 8869... | ||
- | 8869 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 8870 | ||
- | 8871 | if (dev_priv->mm.busy) |
|
8175 | struct drm_i915_private *dev_priv = dev->dev_private; |
8872 | return; |
8176 | 8873 | ||
- | 8874 | intel_runtime_pm_get(dev_priv); |
|
8177 | hsw_package_c8_gpu_busy(dev_priv); |
8875 | i915_update_gfx_val(dev_priv); |
Line 8178... | Line 8876... | ||
8178 | i915_update_gfx_val(dev_priv); |
8876 | dev_priv->mm.busy = true; |
8179 | } |
8877 | } |
8180 | 8878 | ||
8181 | void intel_mark_idle(struct drm_device *dev) |
8879 | void intel_mark_idle(struct drm_device *dev) |
Line 8182... | Line -... | ||
8182 | { |
- | |
8183 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8184 | struct drm_crtc *crtc; |
8880 | { |
8185 | 8881 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line -... | Line 8882... | ||
- | 8882 | struct drm_crtc *crtc; |
|
- | 8883 | ||
- | 8884 | if (!dev_priv->mm.busy) |
|
- | 8885 | return; |
|
- | 8886 | ||
8186 | hsw_package_c8_gpu_idle(dev_priv); |
8887 | dev_priv->mm.busy = false; |
8187 | 8888 | ||
8188 | if (!i915_powersave) |
8889 | if (!i915.powersave) |
Line 8189... | Line 8890... | ||
8189 | return; |
8890 | goto out; |
8190 | 8891 | ||
Line 8191... | Line 8892... | ||
8191 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8892 | for_each_crtc(dev, crtc) { |
8192 | if (!crtc->fb) |
8893 | if (!crtc->primary->fb) |
- | 8894 | continue; |
|
- | 8895 | ||
- | 8896 | intel_decrease_pllclock(crtc); |
|
8193 | continue; |
8897 | } |
Line -... | Line 8898... | ||
- | 8898 | ||
- | 8899 | if (INTEL_INFO(dev)->gen >= 6) |
|
- | 8900 | gen6_rps_idle(dev->dev_private); |
|
- | 8901 | ||
- | 8902 | out: |
|
- | 8903 | intel_runtime_pm_put(dev_priv); |
|
- | 8904 | } |
|
- | 8905 | ||
- | 8906 | ||
- | 8907 | /** |
|
8194 | 8908 | * intel_mark_fb_busy - mark given planes as busy |
|
- | 8909 | * @dev: DRM device |
|
8195 | intel_decrease_pllclock(crtc); |
8910 | * @frontbuffer_bits: bits for the affected planes |
8196 | } |
8911 | * @ring: optional ring for asynchronous commands |
8197 | - | ||
8198 | if (dev_priv->info->gen >= 6) |
8912 | * |
Line 8199... | Line 8913... | ||
8199 | gen6_rps_idle(dev->dev_private); |
8913 | * This function gets called every time the screen contents change. It can be |
8200 | } |
8914 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. |
Line 8201... | Line -... | ||
8201 | - | ||
8202 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8915 | */ |
8203 | struct intel_ring_buffer *ring) |
- | |
8204 | { |
- | |
8205 | struct drm_device *dev = obj->base.dev; |
8916 | static void intel_mark_fb_busy(struct drm_device *dev, |
8206 | struct drm_crtc *crtc; |
8917 | unsigned frontbuffer_bits, |
Line 8207... | Line 8918... | ||
8207 | 8918 | struct intel_engine_cs *ring) |
|
8208 | if (!i915_powersave) |
8919 | { |
8209 | return; |
8920 | enum pipe pipe; |
8210 | 8921 | ||
8211 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8922 | if (!i915.powersave) |
Line -... | Line 8923... | ||
- | 8923 | return; |
|
- | 8924 | ||
- | 8925 | for_each_pipe(pipe) { |
|
- | 8926 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
|
- | 8927 | continue; |
|
- | 8928 | ||
- | 8929 | intel_increase_pllclock(dev, pipe); |
|
- | 8930 | if (ring && intel_fbc_enabled(dev)) |
|
- | 8931 | ring->fbc_dirty = true; |
|
- | 8932 | } |
|
- | 8933 | } |
|
- | 8934 | ||
- | 8935 | /** |
|
- | 8936 | * intel_fb_obj_invalidate - invalidate frontbuffer object |
|
- | 8937 | * @obj: GEM object to invalidate |
|
- | 8938 | * @ring: set for asynchronous rendering |
|
- | 8939 | * |
|
- | 8940 | * This function gets called every time rendering on the given object starts and |
|
- | 8941 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must |
|
- | 8942 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed |
|
- | 8943 | * until the rendering completes or a flip on this frontbuffer plane is |
|
- | 8944 | * scheduled. |
|
- | 8945 | */ |
|
- | 8946 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
|
- | 8947 | struct intel_engine_cs *ring) |
|
- | 8948 | { |
|
- | 8949 | struct drm_device *dev = obj->base.dev; |
|
- | 8950 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 8951 | ||
- | 8952 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
- | 8953 | ||
- | 8954 | if (!obj->frontbuffer_bits) |
|
- | 8955 | return; |
|
- | 8956 | ||
- | 8957 | if (ring) { |
|
- | 8958 | mutex_lock(&dev_priv->fb_tracking.lock); |
|
- | 8959 | dev_priv->fb_tracking.busy_bits |
|
- | 8960 | |= obj->frontbuffer_bits; |
|
- | 8961 | dev_priv->fb_tracking.flip_bits |
|
- | 8962 | &= ~obj->frontbuffer_bits; |
|
- | 8963 | mutex_unlock(&dev_priv->fb_tracking.lock); |
|
- | 8964 | } |
|
- | 8965 | ||
- | 8966 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); |
|
- | 8967 | ||
- | 8968 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
|
- | 8969 | } |
|
- | 8970 | ||
- | 8971 | /** |
|
- | 8972 | * intel_frontbuffer_flush - flush frontbuffer |
|
- | 8973 | * @dev: DRM device |
|
- | 8974 | * @frontbuffer_bits: frontbuffer plane tracking bits |
|
- | 8975 | * |
|
- | 8976 | * This function gets called every time rendering on the given planes has |
|
- | 8977 | * completed and frontbuffer caching can be started again. Flushes will get |
|
- | 8978 | * delayed if they're blocked by some oustanding asynchronous rendering. |
|
- | 8979 | * |
|
- | 8980 | * Can be called without any locks held. |
|
- | 8981 | */ |
|
- | 8982 | void intel_frontbuffer_flush(struct drm_device *dev, |
|
- | 8983 | unsigned frontbuffer_bits) |
|
8212 | if (!crtc->fb) |
8984 | { |
8213 | continue; |
8985 | struct drm_i915_private *dev_priv = dev->dev_private; |
8214 | 8986 | ||
8215 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8987 | /* Delay flushing when rings are still busy.*/ |
8216 | continue; |
8988 | mutex_lock(&dev_priv->fb_tracking.lock); |
Line 8247... | Line 9019... | ||
8247 | static void intel_unpin_work_fn(struct work_struct *__work) |
9019 | static void intel_unpin_work_fn(struct work_struct *__work) |
8248 | { |
9020 | { |
8249 | struct intel_unpin_work *work = |
9021 | struct intel_unpin_work *work = |
8250 | container_of(__work, struct intel_unpin_work, work); |
9022 | container_of(__work, struct intel_unpin_work, work); |
8251 | struct drm_device *dev = work->crtc->dev; |
9023 | struct drm_device *dev = work->crtc->dev; |
- | 9024 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
|
Line 8252... | Line 9025... | ||
8252 | 9025 | ||
8253 | mutex_lock(&dev->struct_mutex); |
9026 | mutex_lock(&dev->struct_mutex); |
8254 | intel_unpin_fb_obj(work->old_fb_obj); |
9027 | intel_unpin_fb_obj(work->old_fb_obj); |
8255 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9028 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
Line 8265... | Line 9038... | ||
8265 | } |
9038 | } |
Line 8266... | Line 9039... | ||
8266 | 9039 | ||
8267 | static void do_intel_finish_page_flip(struct drm_device *dev, |
9040 | static void do_intel_finish_page_flip(struct drm_device *dev, |
8268 | struct drm_crtc *crtc) |
9041 | struct drm_crtc *crtc) |
8269 | { |
9042 | { |
8270 | drm_i915_private_t *dev_priv = dev->dev_private; |
9043 | struct drm_i915_private *dev_priv = dev->dev_private; |
8271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8272 | struct intel_unpin_work *work; |
9045 | struct intel_unpin_work *work; |
Line 8273... | Line 9046... | ||
8273 | unsigned long flags; |
9046 | unsigned long flags; |
Line 8293... | Line 9066... | ||
8293 | intel_crtc->unpin_work = NULL; |
9066 | intel_crtc->unpin_work = NULL; |
Line 8294... | Line 9067... | ||
8294 | 9067 | ||
8295 | if (work->event) |
9068 | if (work->event) |
Line 8296... | Line 9069... | ||
8296 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
9069 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
Line 8297... | Line 9070... | ||
8297 | 9070 | ||
Line 8298... | Line 9071... | ||
8298 | drm_vblank_put(dev, intel_crtc->pipe); |
9071 | drm_crtc_vblank_put(crtc); |
Line 8306... | Line 9079... | ||
8306 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
9079 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
8307 | } |
9080 | } |
Line 8308... | Line 9081... | ||
8308 | 9081 | ||
8309 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9082 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8310 | { |
9083 | { |
8311 | drm_i915_private_t *dev_priv = dev->dev_private; |
9084 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 8312... | Line 9085... | ||
8312 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9085 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8313 | 9086 | ||
Line 8314... | Line 9087... | ||
8314 | do_intel_finish_page_flip(dev, crtc); |
9087 | do_intel_finish_page_flip(dev, crtc); |
8315 | } |
9088 | } |
8316 | 9089 | ||
8317 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
9090 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
Line 8318... | Line 9091... | ||
8318 | { |
9091 | { |
8319 | drm_i915_private_t *dev_priv = dev->dev_private; |
9092 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line -... | Line 9093... | ||
- | 9093 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
|
- | 9094 | ||
- | 9095 | do_intel_finish_page_flip(dev, crtc); |
|
- | 9096 | } |
|
- | 9097 | ||
- | 9098 | /* Is 'a' after or equal to 'b'? */ |
|
- | 9099 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
|
- | 9100 | { |
|
- | 9101 | return !((a - b) & 0x80000000); |
|
- | 9102 | } |
|
- | 9103 | ||
- | 9104 | static bool page_flip_finished(struct intel_crtc *crtc) |
|
- | 9105 | { |
|
- | 9106 | struct drm_device *dev = crtc->base.dev; |
|
- | 9107 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 9108 | ||
- | 9109 | /* |
|
- | 9110 | * The relevant registers doen't exist on pre-ctg. |
|
- | 9111 | * As the flip done interrupt doesn't trigger for mmio |
|
- | 9112 | * flips on gmch platforms, a flip count check isn't |
|
- | 9113 | * really needed there. But since ctg has the registers, |
|
- | 9114 | * include it in the check anyway. |
|
- | 9115 | */ |
|
- | 9116 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
|
- | 9117 | return true; |
|
- | 9118 | ||
- | 9119 | /* |
|
- | 9120 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
|
- | 9121 | * used the same base address. In that case the mmio flip might |
|
- | 9122 | * have completed, but the CS hasn't even executed the flip yet. |
|
- | 9123 | * |
|
- | 9124 | * A flip count check isn't enough as the CS might have updated |
|
- | 9125 | * the base address just after start of vblank, but before we |
|
- | 9126 | * managed to process the interrupt. This means we'd complete the |
|
- | 9127 | * CS flip too soon. |
|
- | 9128 | * |
|
- | 9129 | * Combining both checks should get us a good enough result. It may |
|
- | 9130 | * still happen that the CS flip has been executed, but has not |
|
- | 9131 | * yet actually completed. But in case the base address is the same |
|
- | 9132 | * anyway, we don't really care. |
|
- | 9133 | */ |
|
- | 9134 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
|
8320 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9135 | crtc->unpin_work->gtt_offset && |
8321 | 9136 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), |
|
8322 | do_intel_finish_page_flip(dev, crtc); |
9137 | crtc->unpin_work->flip_count); |
8323 | } |
9138 | } |
8324 | 9139 | ||
8325 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9140 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
Line 8326... | Line 9141... | ||
8326 | { |
9141 | { |
8327 | drm_i915_private_t *dev_priv = dev->dev_private; |
9142 | struct drm_i915_private *dev_priv = dev->dev_private; |
8328 | struct intel_crtc *intel_crtc = |
9143 | struct intel_crtc *intel_crtc = |
8329 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
9144 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
8330 | unsigned long flags; |
9145 | unsigned long flags; |
8331 | 9146 | ||
8332 | /* NB: An MMIO update of the plane base pointer will also |
9147 | /* NB: An MMIO update of the plane base pointer will also |
8333 | * generate a page-flip completion irq, i.e. every modeset |
9148 | * generate a page-flip completion irq, i.e. every modeset |
8334 | * is also accompanied by a spurious intel_prepare_page_flip(). |
9149 | * is also accompanied by a spurious intel_prepare_page_flip(). |
Line 8335... | Line 9150... | ||
8335 | */ |
9150 | */ |
8336 | spin_lock_irqsave(&dev->event_lock, flags); |
9151 | spin_lock_irqsave(&dev->event_lock, flags); |
8337 | if (intel_crtc->unpin_work) |
9152 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
8338 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
9153 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
8339 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9154 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8340 | } |
9155 | } |
Line 8350... | Line 9165... | ||
8350 | 9165 | ||
8351 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9166 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8352 | struct drm_crtc *crtc, |
9167 | struct drm_crtc *crtc, |
8353 | struct drm_framebuffer *fb, |
9168 | struct drm_framebuffer *fb, |
- | 9169 | struct drm_i915_gem_object *obj, |
|
8354 | struct drm_i915_gem_object *obj, |
9170 | struct intel_engine_cs *ring, |
8355 | uint32_t flags) |
9171 | uint32_t flags) |
8356 | { |
- | |
8357 | struct drm_i915_private *dev_priv = dev->dev_private; |
9172 | { |
8358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8359 | u32 flip_mask; |
- | |
8360 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
9174 | u32 flip_mask; |
Line 8361... | Line -... | ||
8361 | int ret; |
- | |
8362 | - | ||
8363 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8364 | if (ret) |
- | |
8365 | goto err; |
9175 | int ret; |
8366 | 9176 | ||
8367 | ret = intel_ring_begin(ring, 6); |
9177 | ret = intel_ring_begin(ring, 6); |
Line 8368... | Line 9178... | ||
8368 | if (ret) |
9178 | if (ret) |
8369 | goto err_unpin; |
9179 | return ret; |
8370 | 9180 | ||
8371 | /* Can't queue multiple flips, so wait for the previous |
9181 | /* Can't queue multiple flips, so wait for the previous |
Line 8378... | Line 9188... | ||
8378 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9188 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8379 | intel_ring_emit(ring, MI_NOOP); |
9189 | intel_ring_emit(ring, MI_NOOP); |
8380 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9190 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8381 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9191 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8382 | intel_ring_emit(ring, fb->pitches[0]); |
9192 | intel_ring_emit(ring, fb->pitches[0]); |
8383 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9193 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8384 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
9194 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Line 8385... | Line 9195... | ||
8385 | 9195 | ||
8386 | intel_mark_page_flip_active(intel_crtc); |
9196 | intel_mark_page_flip_active(intel_crtc); |
8387 | __intel_ring_advance(ring); |
9197 | __intel_ring_advance(ring); |
8388 | return 0; |
- | |
8389 | - | ||
8390 | err_unpin: |
- | |
8391 | intel_unpin_fb_obj(obj); |
- | |
8392 | err: |
- | |
8393 | return ret; |
9198 | return 0; |
Line 8394... | Line 9199... | ||
8394 | } |
9199 | } |
8395 | 9200 | ||
8396 | static int intel_gen3_queue_flip(struct drm_device *dev, |
9201 | static int intel_gen3_queue_flip(struct drm_device *dev, |
8397 | struct drm_crtc *crtc, |
9202 | struct drm_crtc *crtc, |
- | 9203 | struct drm_framebuffer *fb, |
|
8398 | struct drm_framebuffer *fb, |
9204 | struct drm_i915_gem_object *obj, |
8399 | struct drm_i915_gem_object *obj, |
9205 | struct intel_engine_cs *ring, |
8400 | uint32_t flags) |
- | |
8401 | { |
9206 | uint32_t flags) |
8402 | struct drm_i915_private *dev_priv = dev->dev_private; |
9207 | { |
8403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
8404 | u32 flip_mask; |
9208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 8405... | Line -... | ||
8405 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
- | |
8406 | int ret; |
- | |
8407 | - | ||
8408 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8409 | if (ret) |
9209 | u32 flip_mask; |
8410 | goto err; |
9210 | int ret; |
8411 | 9211 | ||
Line 8412... | Line 9212... | ||
8412 | ret = intel_ring_begin(ring, 6); |
9212 | ret = intel_ring_begin(ring, 6); |
8413 | if (ret) |
9213 | if (ret) |
8414 | goto err_unpin; |
9214 | return ret; |
8415 | 9215 | ||
8416 | if (intel_crtc->plane) |
9216 | if (intel_crtc->plane) |
8417 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
9217 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
8418 | else |
9218 | else |
8419 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
9219 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
8420 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9220 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8421 | intel_ring_emit(ring, MI_NOOP); |
9221 | intel_ring_emit(ring, MI_NOOP); |
8422 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
9222 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
Line 8423... | Line 9223... | ||
8423 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9223 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8424 | intel_ring_emit(ring, fb->pitches[0]); |
9224 | intel_ring_emit(ring, fb->pitches[0]); |
8425 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9225 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8426 | intel_ring_emit(ring, MI_NOOP); |
- | |
8427 | - | ||
8428 | intel_mark_page_flip_active(intel_crtc); |
- | |
8429 | __intel_ring_advance(ring); |
- | |
8430 | return 0; |
- | |
8431 | 9226 | intel_ring_emit(ring, MI_NOOP); |
|
Line 8432... | Line 9227... | ||
8432 | err_unpin: |
9227 | |
8433 | intel_unpin_fb_obj(obj); |
9228 | intel_mark_page_flip_active(intel_crtc); |
8434 | err: |
9229 | __intel_ring_advance(ring); |
8435 | return ret; |
9230 | return 0; |
- | 9231 | } |
|
8436 | } |
9232 | |
8437 | 9233 | static int intel_gen4_queue_flip(struct drm_device *dev, |
|
8438 | static int intel_gen4_queue_flip(struct drm_device *dev, |
9234 | struct drm_crtc *crtc, |
8439 | struct drm_crtc *crtc, |
9235 | struct drm_framebuffer *fb, |
8440 | struct drm_framebuffer *fb, |
9236 | struct drm_i915_gem_object *obj, |
8441 | struct drm_i915_gem_object *obj, |
- | |
8442 | uint32_t flags) |
9237 | struct intel_engine_cs *ring, |
Line 8443... | Line -... | ||
8443 | { |
- | |
8444 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
8446 | uint32_t pf, pipesrc; |
- | |
8447 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
9238 | uint32_t flags) |
8448 | int ret; |
9239 | { |
8449 | 9240 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line 8450... | Line 9241... | ||
8450 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
9241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8451 | if (ret) |
9242 | uint32_t pf, pipesrc; |
8452 | goto err; |
9243 | int ret; |
8453 | 9244 | ||
8454 | ret = intel_ring_begin(ring, 4); |
9245 | ret = intel_ring_begin(ring, 4); |
8455 | if (ret) |
9246 | if (ret) |
8456 | goto err_unpin; |
9247 | return ret; |
8457 | - | ||
8458 | /* i965+ uses the linear or tiled offsets from the |
9248 | |
8459 | * Display Registers (which do not change across a page-flip) |
9249 | /* i965+ uses the linear or tiled offsets from the |
Line 8460... | Line 9250... | ||
8460 | * so we need only reprogram the base address. |
9250 | * Display Registers (which do not change across a page-flip) |
8461 | */ |
9251 | * so we need only reprogram the base address. |
8462 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9252 | */ |
Line 8475... | Line 9265... | ||
8475 | intel_ring_emit(ring, pf | pipesrc); |
9265 | intel_ring_emit(ring, pf | pipesrc); |
Line 8476... | Line 9266... | ||
8476 | 9266 | ||
8477 | intel_mark_page_flip_active(intel_crtc); |
9267 | intel_mark_page_flip_active(intel_crtc); |
8478 | __intel_ring_advance(ring); |
9268 | __intel_ring_advance(ring); |
8479 | return 0; |
- | |
8480 | - | ||
8481 | err_unpin: |
- | |
8482 | intel_unpin_fb_obj(obj); |
- | |
8483 | err: |
- | |
8484 | return ret; |
9269 | return 0; |
Line 8485... | Line 9270... | ||
8485 | } |
9270 | } |
8486 | 9271 | ||
8487 | static int intel_gen6_queue_flip(struct drm_device *dev, |
9272 | static int intel_gen6_queue_flip(struct drm_device *dev, |
8488 | struct drm_crtc *crtc, |
9273 | struct drm_crtc *crtc, |
- | 9274 | struct drm_framebuffer *fb, |
|
8489 | struct drm_framebuffer *fb, |
9275 | struct drm_i915_gem_object *obj, |
8490 | struct drm_i915_gem_object *obj, |
9276 | struct intel_engine_cs *ring, |
8491 | uint32_t flags) |
9277 | uint32_t flags) |
8492 | { |
9278 | { |
8493 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9279 | struct drm_i915_private *dev_priv = dev->dev_private; |
8495 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
9280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 8496... | Line -... | ||
8496 | uint32_t pf, pipesrc; |
- | |
8497 | int ret; |
- | |
8498 | - | ||
8499 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8500 | if (ret) |
9281 | uint32_t pf, pipesrc; |
8501 | goto err; |
9282 | int ret; |
8502 | 9283 | ||
Line 8503... | Line 9284... | ||
8503 | ret = intel_ring_begin(ring, 4); |
9284 | ret = intel_ring_begin(ring, 4); |
8504 | if (ret) |
9285 | if (ret) |
8505 | goto err_unpin; |
9286 | return ret; |
8506 | 9287 | ||
Line 8507... | Line 9288... | ||
8507 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9288 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8508 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
9289 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8509 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
9290 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
8510 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9291 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Line 8520... | Line 9301... | ||
8520 | intel_ring_emit(ring, pf | pipesrc); |
9301 | intel_ring_emit(ring, pf | pipesrc); |
Line 8521... | Line 9302... | ||
8521 | 9302 | ||
8522 | intel_mark_page_flip_active(intel_crtc); |
9303 | intel_mark_page_flip_active(intel_crtc); |
8523 | __intel_ring_advance(ring); |
9304 | __intel_ring_advance(ring); |
8524 | return 0; |
- | |
8525 | - | ||
8526 | err_unpin: |
- | |
8527 | intel_unpin_fb_obj(obj); |
- | |
8528 | err: |
- | |
8529 | return ret; |
9305 | return 0; |
Line 8530... | Line 9306... | ||
8530 | } |
9306 | } |
8531 | 9307 | ||
8532 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9308 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8533 | struct drm_crtc *crtc, |
9309 | struct drm_crtc *crtc, |
- | 9310 | struct drm_framebuffer *fb, |
|
8534 | struct drm_framebuffer *fb, |
9311 | struct drm_i915_gem_object *obj, |
8535 | struct drm_i915_gem_object *obj, |
9312 | struct intel_engine_cs *ring, |
8536 | uint32_t flags) |
- | |
8537 | { |
9313 | uint32_t flags) |
8538 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9314 | { |
8540 | struct intel_ring_buffer *ring; |
9315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 8541... | Line -... | ||
8541 | uint32_t plane_bit = 0; |
- | |
8542 | int len, ret; |
- | |
8543 | - | ||
8544 | ring = obj->ring; |
- | |
8545 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
- | |
8546 | ring = &dev_priv->ring[BCS]; |
- | |
8547 | - | ||
8548 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
- | |
8549 | if (ret) |
9316 | uint32_t plane_bit = 0; |
8550 | goto err; |
9317 | int len, ret; |
8551 | 9318 | ||
8552 | switch(intel_crtc->plane) { |
9319 | switch (intel_crtc->plane) { |
8553 | case PLANE_A: |
9320 | case PLANE_A: |
Line 8559... | Line 9326... | ||
8559 | case PLANE_C: |
9326 | case PLANE_C: |
8560 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
9327 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
8561 | break; |
9328 | break; |
8562 | default: |
9329 | default: |
8563 | WARN_ONCE(1, "unknown plane in flip command\n"); |
9330 | WARN_ONCE(1, "unknown plane in flip command\n"); |
8564 | ret = -ENODEV; |
9331 | return -ENODEV; |
8565 | goto err_unpin; |
- | |
8566 | } |
9332 | } |
Line 8567... | Line 9333... | ||
8567 | 9333 | ||
8568 | len = 4; |
9334 | len = 4; |
8569 | if (ring->id == RCS) |
9335 | if (ring->id == RCS) { |
- | 9336 | len += 6; |
|
- | 9337 | /* |
|
- | 9338 | * On Gen 8, SRM is now taking an extra dword to accommodate |
|
- | 9339 | * 48bits addresses, and we need a NOOP for the batch size to |
|
- | 9340 | * stay even. |
|
- | 9341 | */ |
|
- | 9342 | if (IS_GEN8(dev)) |
|
- | 9343 | len += 2; |
|
- | 9344 | } |
|
- | 9345 | ||
- | 9346 | /* |
|
- | 9347 | * BSpec MI_DISPLAY_FLIP for IVB: |
|
- | 9348 | * "The full packet must be contained within the same cache line." |
|
- | 9349 | * |
|
- | 9350 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
|
- | 9351 | * cacheline, if we ever start emitting more commands before |
|
- | 9352 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
|
- | 9353 | * then do the cacheline alignment, and finally emit the |
|
- | 9354 | * MI_DISPLAY_FLIP. |
|
- | 9355 | */ |
|
- | 9356 | ret = intel_ring_cacheline_align(ring); |
|
- | 9357 | if (ret) |
|
Line 8570... | Line 9358... | ||
8570 | len += 6; |
9358 | return ret; |
8571 | 9359 | ||
8572 | ret = intel_ring_begin(ring, len); |
9360 | ret = intel_ring_begin(ring, len); |
Line 8573... | Line 9361... | ||
8573 | if (ret) |
9361 | if (ret) |
8574 | goto err_unpin; |
9362 | return ret; |
8575 | 9363 | ||
8576 | /* Unmask the flip-done completion message. Note that the bspec says that |
9364 | /* Unmask the flip-done completion message. Note that the bspec says that |
Line 8586... | Line 9374... | ||
8586 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
9374 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
8587 | intel_ring_emit(ring, DERRMR); |
9375 | intel_ring_emit(ring, DERRMR); |
8588 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
9376 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8589 | DERRMR_PIPEB_PRI_FLIP_DONE | |
9377 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8590 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
9378 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
- | 9379 | if (IS_GEN8(dev)) |
|
- | 9380 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | |
|
- | 9381 | MI_SRM_LRM_GLOBAL_GTT); |
|
- | 9382 | else |
|
8591 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
9383 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8592 | MI_SRM_LRM_GLOBAL_GTT); |
9384 | MI_SRM_LRM_GLOBAL_GTT); |
8593 | intel_ring_emit(ring, DERRMR); |
9385 | intel_ring_emit(ring, DERRMR); |
8594 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
9386 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
- | 9387 | if (IS_GEN8(dev)) { |
|
- | 9388 | intel_ring_emit(ring, 0); |
|
- | 9389 | intel_ring_emit(ring, MI_NOOP); |
|
- | 9390 | } |
|
8595 | } |
9391 | } |
Line 8596... | Line 9392... | ||
8596 | 9392 | ||
8597 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
9393 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
8598 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
9394 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
8599 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
9395 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Line 8600... | Line 9396... | ||
8600 | intel_ring_emit(ring, (MI_NOOP)); |
9396 | intel_ring_emit(ring, (MI_NOOP)); |
8601 | 9397 | ||
8602 | intel_mark_page_flip_active(intel_crtc); |
9398 | intel_mark_page_flip_active(intel_crtc); |
8603 | __intel_ring_advance(ring); |
- | |
8604 | return 0; |
- | |
8605 | - | ||
8606 | err_unpin: |
- | |
8607 | intel_unpin_fb_obj(obj); |
- | |
8608 | err: |
9399 | __intel_ring_advance(ring); |
Line 8609... | Line 9400... | ||
8609 | return ret; |
9400 | return 0; |
8610 | } |
9401 | } |
8611 | 9402 | ||
8612 | static int intel_default_queue_flip(struct drm_device *dev, |
9403 | static int intel_default_queue_flip(struct drm_device *dev, |
- | 9404 | struct drm_crtc *crtc, |
|
8613 | struct drm_crtc *crtc, |
9405 | struct drm_framebuffer *fb, |
8614 | struct drm_framebuffer *fb, |
9406 | struct drm_i915_gem_object *obj, |
8615 | struct drm_i915_gem_object *obj, |
9407 | struct intel_engine_cs *ring, |
8616 | uint32_t flags) |
9408 | uint32_t flags) |
Line 8623... | Line 9415... | ||
8623 | struct drm_pending_vblank_event *event, |
9415 | struct drm_pending_vblank_event *event, |
8624 | uint32_t page_flip_flags) |
9416 | uint32_t page_flip_flags) |
8625 | { |
9417 | { |
8626 | struct drm_device *dev = crtc->dev; |
9418 | struct drm_device *dev = crtc->dev; |
8627 | struct drm_i915_private *dev_priv = dev->dev_private; |
9419 | struct drm_i915_private *dev_priv = dev->dev_private; |
8628 | struct drm_framebuffer *old_fb = crtc->fb; |
9420 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
8629 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
9421 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
8630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 9423 | enum pipe pipe = intel_crtc->pipe; |
|
8631 | struct intel_unpin_work *work; |
9424 | struct intel_unpin_work *work; |
- | 9425 | struct intel_engine_cs *ring; |
|
8632 | unsigned long flags; |
9426 | unsigned long flags; |
8633 | int ret; |
9427 | int ret; |
Line -... | Line 9428... | ||
- | 9428 | ||
- | 9429 | /* |
|
- | 9430 | * drm_mode_page_flip_ioctl() should already catch this, but double |
|
- | 9431 | * check to be safe. In the future we may enable pageflipping from |
|
- | 9432 | * a disabled primary plane. |
|
- | 9433 | */ |
|
- | 9434 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
|
- | 9435 | return -EBUSY; |
|
8634 | 9436 | ||
8635 | /* Can't change pixel format via MI display flips. */ |
9437 | /* Can't change pixel format via MI display flips. */ |
8636 | if (fb->pixel_format != crtc->fb->pixel_format) |
9438 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
Line 8637... | Line 9439... | ||
8637 | return -EINVAL; |
9439 | return -EINVAL; |
8638 | 9440 | ||
8639 | /* |
9441 | /* |
8640 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
9442 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
8641 | * Note that pitch changes could also affect these register. |
9443 | * Note that pitch changes could also affect these register. |
8642 | */ |
9444 | */ |
8643 | if (INTEL_INFO(dev)->gen > 3 && |
9445 | if (INTEL_INFO(dev)->gen > 3 && |
8644 | (fb->offsets[0] != crtc->fb->offsets[0] || |
9446 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
Line 8645... | Line 9447... | ||
8645 | fb->pitches[0] != crtc->fb->pitches[0])) |
9447 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
8646 | return -EINVAL; |
9448 | return -EINVAL; |
8647 | 9449 | ||
Line 8648... | Line 9450... | ||
8648 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
9450 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
8649 | if (work == NULL) |
9451 | if (work == NULL) |
8650 | return -ENOMEM; |
9452 | return -ENOMEM; |
8651 | 9453 | ||
Line 8652... | Line 9454... | ||
8652 | work->event = event; |
9454 | work->event = event; |
8653 | work->crtc = crtc; |
9455 | work->crtc = crtc; |
8654 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
9456 | work->old_fb_obj = intel_fb_obj(old_fb); |
Line 8655... | Line 9457... | ||
8655 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9457 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8656 | 9458 | ||
8657 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
9459 | ret = drm_crtc_vblank_get(crtc); |
8658 | if (ret) |
9460 | if (ret) |
8659 | goto free_work; |
9461 | goto free_work; |
8660 | 9462 | ||
Line 8661... | Line 9463... | ||
8661 | /* We borrow the event spin lock for protecting unpin_work */ |
9463 | /* We borrow the event spin lock for protecting unpin_work */ |
8662 | spin_lock_irqsave(&dev->event_lock, flags); |
9464 | spin_lock_irqsave(&dev->event_lock, flags); |
8663 | if (intel_crtc->unpin_work) { |
9465 | if (intel_crtc->unpin_work) { |
8664 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9466 | spin_unlock_irqrestore(&dev->event_lock, flags); |
Line 8680... | Line 9482... | ||
8680 | 9482 | ||
8681 | /* Reference the objects for the scheduled work. */ |
9483 | /* Reference the objects for the scheduled work. */ |
8682 | drm_gem_object_reference(&work->old_fb_obj->base); |
9484 | drm_gem_object_reference(&work->old_fb_obj->base); |
Line 8683... | Line 9485... | ||
8683 | drm_gem_object_reference(&obj->base); |
9485 | drm_gem_object_reference(&obj->base); |
Line 8684... | Line 9486... | ||
8684 | 9486 | ||
Line 8685... | Line 9487... | ||
8685 | crtc->fb = fb; |
9487 | crtc->primary->fb = fb; |
Line 8686... | Line 9488... | ||
8686 | 9488 | ||
8687 | work->pending_flip_obj = obj; |
9489 | work->pending_flip_obj = obj; |
Line -... | Line 9490... | ||
- | 9490 | ||
- | 9491 | work->enable_stall_check = true; |
|
- | 9492 | ||
- | 9493 | atomic_inc(&intel_crtc->unpin_work_count); |
|
- | 9494 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
|
- | 9495 | ||
- | 9496 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
|
- | 9497 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
|
- | 9498 | ||
- | 9499 | if (IS_VALLEYVIEW(dev)) { |
|
- | 9500 | ring = &dev_priv->ring[BCS]; |
|
- | 9501 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
|
- | 9502 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
|
- | 9503 | ring = NULL; |
|
- | 9504 | } else if (IS_IVYBRIDGE(dev)) { |
|
- | 9505 | ring = &dev_priv->ring[BCS]; |
|
- | 9506 | } else if (INTEL_INFO(dev)->gen >= 7) { |
|
- | 9507 | ring = obj->ring; |
|
8688 | 9508 | if (ring == NULL || ring->id != RCS) |
|
8689 | work->enable_stall_check = true; |
9509 | ring = &dev_priv->ring[BCS]; |
8690 | 9510 | } else { |
|
Line -... | Line 9511... | ||
- | 9511 | ring = &dev_priv->ring[RCS]; |
|
- | 9512 | } |
|
- | 9513 | ||
- | 9514 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
|
- | 9515 | if (ret) |
|
- | 9516 | goto cleanup_pending; |
|
- | 9517 | ||
- | 9518 | work->gtt_offset = |
|
- | 9519 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; |
|
- | 9520 | ||
- | 9521 | if (use_mmio_flip(ring, obj)) |
|
- | 9522 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
|
- | 9523 | page_flip_flags); |
|
- | 9524 | else |
|
- | 9525 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
|
8691 | atomic_inc(&intel_crtc->unpin_work_count); |
9526 | page_flip_flags); |
8692 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
9527 | if (ret) |
8693 | 9528 | goto cleanup_unpin; |
|
Line 8694... | Line 9529... | ||
8694 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
9529 | |
Line 8695... | Line 9530... | ||
8695 | if (ret) |
9530 | i915_gem_track_fb(work->old_fb_obj, obj, |
Line -... | Line 9531... | ||
- | 9531 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
- | 9532 | ||
8696 | goto cleanup_pending; |
9533 | intel_disable_fbc(dev); |
8697 | 9534 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
8698 | intel_disable_fbc(dev); |
9535 | mutex_unlock(&dev->struct_mutex); |
8699 | intel_mark_fb_busy(obj, NULL); |
9536 | |
8700 | mutex_unlock(&dev->struct_mutex); |
9537 | trace_i915_flip_request(intel_crtc->plane, obj); |
8701 | 9538 | ||
Line 8702... | Line 9539... | ||
8702 | trace_i915_flip_request(intel_crtc->plane, obj); |
9539 | return 0; |
8703 | 9540 | ||
8704 | return 0; |
9541 | cleanup_unpin: |
8705 | 9542 | intel_unpin_fb_obj(obj); |
|
Line 8706... | Line 9543... | ||
8706 | cleanup_pending: |
9543 | cleanup_pending: |
8707 | atomic_dec(&intel_crtc->unpin_work_count); |
9544 | atomic_dec(&intel_crtc->unpin_work_count); |
8708 | crtc->fb = old_fb; |
9545 | crtc->primary->fb = old_fb; |
Line -... | Line 9546... | ||
- | 9546 | drm_gem_object_unreference(&work->old_fb_obj->base); |
|
- | 9547 | drm_gem_object_unreference(&obj->base); |
|
- | 9548 | mutex_unlock(&dev->struct_mutex); |
|
- | 9549 | ||
- | 9550 | cleanup: |
|
- | 9551 | spin_lock_irqsave(&dev->event_lock, flags); |
|
- | 9552 | intel_crtc->unpin_work = NULL; |
|
8709 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9553 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8710 | drm_gem_object_unreference(&obj->base); |
9554 | |
8711 | mutex_unlock(&dev->struct_mutex); |
9555 | drm_crtc_vblank_put(crtc); |
Line 8712... | Line 9556... | ||
8712 | 9556 | free_work: |
|
Line 8734... | Line 9578... | ||
8734 | * Updates the staged output configuration state, e.g. after we've read out the |
9578 | * Updates the staged output configuration state, e.g. after we've read out the |
8735 | * current hw state. |
9579 | * current hw state. |
8736 | */ |
9580 | */ |
8737 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
9581 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8738 | { |
9582 | { |
- | 9583 | struct intel_crtc *crtc; |
|
8739 | struct intel_encoder *encoder; |
9584 | struct intel_encoder *encoder; |
8740 | struct intel_connector *connector; |
9585 | struct intel_connector *connector; |
Line 8741... | Line 9586... | ||
8741 | 9586 | ||
8742 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9587 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
Line 8748... | Line 9593... | ||
8748 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9593 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8749 | base.head) { |
9594 | base.head) { |
8750 | encoder->new_crtc = |
9595 | encoder->new_crtc = |
8751 | to_intel_crtc(encoder->base.crtc); |
9596 | to_intel_crtc(encoder->base.crtc); |
8752 | } |
9597 | } |
- | 9598 | ||
- | 9599 | for_each_intel_crtc(dev, crtc) { |
|
- | 9600 | crtc->new_enabled = crtc->base.enabled; |
|
- | 9601 | ||
- | 9602 | if (crtc->new_enabled) |
|
- | 9603 | crtc->new_config = &crtc->config; |
|
- | 9604 | else |
|
- | 9605 | crtc->new_config = NULL; |
|
- | 9606 | } |
|
8753 | } |
9607 | } |
Line 8754... | Line 9608... | ||
8754 | 9608 | ||
8755 | /** |
9609 | /** |
8756 | * intel_modeset_commit_output_state |
9610 | * intel_modeset_commit_output_state |
8757 | * |
9611 | * |
8758 | * This function copies the stage display pipe configuration to the real one. |
9612 | * This function copies the stage display pipe configuration to the real one. |
8759 | */ |
9613 | */ |
8760 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
9614 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
- | 9615 | { |
|
8761 | { |
9616 | struct intel_crtc *crtc; |
8762 | struct intel_encoder *encoder; |
9617 | struct intel_encoder *encoder; |
Line 8763... | Line 9618... | ||
8763 | struct intel_connector *connector; |
9618 | struct intel_connector *connector; |
8764 | 9619 | ||
Line 8769... | Line 9624... | ||
8769 | 9624 | ||
8770 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9625 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8771 | base.head) { |
9626 | base.head) { |
8772 | encoder->base.crtc = &encoder->new_crtc->base; |
9627 | encoder->base.crtc = &encoder->new_crtc->base; |
- | 9628 | } |
|
- | 9629 | ||
- | 9630 | for_each_intel_crtc(dev, crtc) { |
|
- | 9631 | crtc->base.enabled = crtc->new_enabled; |
|
8773 | } |
9632 | } |
Line 8774... | Line 9633... | ||
8774 | } |
9633 | } |
8775 | 9634 | ||
8776 | static void |
9635 | static void |
8777 | connected_sink_compute_bpp(struct intel_connector * connector, |
9636 | connected_sink_compute_bpp(struct intel_connector *connector, |
8778 | struct intel_crtc_config *pipe_config) |
9637 | struct intel_crtc_config *pipe_config) |
Line 8779... | Line 9638... | ||
8779 | { |
9638 | { |
8780 | int bpp = pipe_config->pipe_bpp; |
9639 | int bpp = pipe_config->pipe_bpp; |
8781 | 9640 | ||
Line 8782... | Line 9641... | ||
8782 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
9641 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8783 | connector->base.base.id, |
9642 | connector->base.base.id, |
8784 | drm_get_connector_name(&connector->base)); |
9643 | connector->base.name); |
8785 | 9644 | ||
Line 8909... | Line 9768... | ||
8909 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
9768 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8910 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
9769 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8911 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
9770 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
8912 | } |
9771 | } |
Line 8913... | Line 9772... | ||
8913 | 9772 | ||
- | 9773 | static bool encoders_cloneable(const struct intel_encoder *a, |
|
8914 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
9774 | const struct intel_encoder *b) |
- | 9775 | { |
|
- | 9776 | /* masks could be asymmetric, so check both ways */ |
|
- | 9777 | return a == b || (a->cloneable & (1 << b->type) && |
|
- | 9778 | b->cloneable & (1 << a->type)); |
|
- | 9779 | } |
|
- | 9780 | ||
- | 9781 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
|
- | 9782 | struct intel_encoder *encoder) |
|
- | 9783 | { |
|
8915 | { |
9784 | struct drm_device *dev = crtc->base.dev; |
- | 9785 | struct intel_encoder *source_encoder; |
|
- | 9786 | ||
- | 9787 | list_for_each_entry(source_encoder, |
|
- | 9788 | &dev->mode_config.encoder_list, base.head) { |
|
- | 9789 | if (source_encoder->new_crtc != crtc) |
|
- | 9790 | continue; |
|
8916 | int num_encoders = 0; |
9791 | |
- | 9792 | if (!encoders_cloneable(encoder, source_encoder)) |
|
- | 9793 | return false; |
|
- | 9794 | } |
|
- | 9795 | ||
- | 9796 | return true; |
|
- | 9797 | } |
|
- | 9798 | ||
- | 9799 | static bool check_encoder_cloning(struct intel_crtc *crtc) |
|
- | 9800 | { |
|
8917 | bool uncloneable_encoders = false; |
9801 | struct drm_device *dev = crtc->base.dev; |
Line 8918... | Line 9802... | ||
8918 | struct intel_encoder *encoder; |
9802 | struct intel_encoder *encoder; |
8919 | 9803 | ||
8920 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
9804 | list_for_each_entry(encoder, |
8921 | base.head) { |
9805 | &dev->mode_config.encoder_list, base.head) { |
Line 8922... | Line -... | ||
8922 | if (&encoder->new_crtc->base != crtc) |
- | |
8923 | continue; |
9806 | if (encoder->new_crtc != crtc) |
8924 | 9807 | continue; |
|
8925 | num_encoders++; |
9808 | |
Line 8926... | Line 9809... | ||
8926 | if (!encoder->cloneable) |
9809 | if (!check_single_encoder_cloning(crtc, encoder)) |
8927 | uncloneable_encoders = true; |
9810 | return false; |
Line 8928... | Line 9811... | ||
8928 | } |
9811 | } |
8929 | 9812 | ||
8930 | return !(num_encoders > 1 && uncloneable_encoders); |
9813 | return true; |
Line 8939... | Line 9822... | ||
8939 | struct intel_encoder *encoder; |
9822 | struct intel_encoder *encoder; |
8940 | struct intel_crtc_config *pipe_config; |
9823 | struct intel_crtc_config *pipe_config; |
8941 | int plane_bpp, ret = -EINVAL; |
9824 | int plane_bpp, ret = -EINVAL; |
8942 | bool retry = true; |
9825 | bool retry = true; |
Line 8943... | Line 9826... | ||
8943 | 9826 | ||
8944 | if (!check_encoder_cloning(crtc)) { |
9827 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
8945 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9828 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8946 | return ERR_PTR(-EINVAL); |
9829 | return ERR_PTR(-EINVAL); |
Line 8947... | Line 9830... | ||
8947 | } |
9830 | } |
Line 9095... | Line 9978... | ||
9095 | 9978 | ||
9096 | if (encoder->new_crtc) |
9979 | if (encoder->new_crtc) |
9097 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
9980 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
Line 9098... | Line 9981... | ||
9098 | } |
9981 | } |
9099 | 9982 | ||
9100 | /* Check for any pipes that will be fully disabled ... */ |
- | |
9101 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
- | |
9102 | base.head) { |
- | |
9103 | bool used = false; |
- | |
9104 | 9983 | /* Check for pipes that will be enabled/disabled ... */ |
|
9105 | /* Don't try to disable disabled crtcs. */ |
9984 | for_each_intel_crtc(dev, intel_crtc) { |
Line 9106... | Line -... | ||
9106 | if (!intel_crtc->base.enabled) |
- | |
9107 | continue; |
- | |
9108 | 9985 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
|
9109 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
- | |
9110 | base.head) { |
- | |
9111 | if (encoder->new_crtc == intel_crtc) |
- | |
9112 | used = true; |
- | |
9113 | } |
9986 | continue; |
- | 9987 | ||
- | 9988 | if (!intel_crtc->new_enabled) |
|
9114 | 9989 | *disable_pipes |= 1 << intel_crtc->pipe; |
|
Line 9115... | Line 9990... | ||
9115 | if (!used) |
9990 | else |
9116 | *disable_pipes |= 1 << intel_crtc->pipe; |
9991 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9117 | } |
9992 | } |
9118 | 9993 | ||
Line 9119... | Line 9994... | ||
9119 | 9994 | ||
9120 | /* set_mode is also used to update properties on life display pipes. */ |
9995 | /* set_mode is also used to update properties on life display pipes. */ |
9121 | intel_crtc = to_intel_crtc(crtc); |
9996 | intel_crtc = to_intel_crtc(crtc); |
Line 9176... | Line 10051... | ||
9176 | intel_encoder->connectors_active = false; |
10051 | intel_encoder->connectors_active = false; |
9177 | } |
10052 | } |
Line 9178... | Line 10053... | ||
9178 | 10053 | ||
Line 9179... | Line 10054... | ||
9179 | intel_modeset_commit_output_state(dev); |
10054 | intel_modeset_commit_output_state(dev); |
9180 | 10055 | ||
- | 10056 | /* Double check state. */ |
|
9181 | /* Update computed state. */ |
10057 | for_each_intel_crtc(dev, intel_crtc) { |
- | 10058 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
|
9182 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
10059 | WARN_ON(intel_crtc->new_config && |
9183 | base.head) { |
10060 | intel_crtc->new_config != &intel_crtc->config); |
Line 9184... | Line 10061... | ||
9184 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
10061 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
9185 | } |
10062 | } |
9186 | 10063 | ||
Line 9304... | Line 10181... | ||
9304 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
10181 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
9305 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
10182 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
9306 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
10183 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
Line 9307... | Line 10184... | ||
9307 | 10184 | ||
- | 10185 | PIPE_CONF_CHECK_I(pixel_multiplier); |
|
- | 10186 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
|
- | 10187 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
|
- | 10188 | IS_VALLEYVIEW(dev)) |
|
- | 10189 | PIPE_CONF_CHECK_I(limited_color_range); |
|
- | 10190 | ||
Line 9308... | Line 10191... | ||
9308 | PIPE_CONF_CHECK_I(pixel_multiplier); |
10191 | PIPE_CONF_CHECK_I(has_audio); |
9309 | 10192 | ||
Line 9310... | Line 10193... | ||
9310 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10193 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
Line 9322... | Line 10205... | ||
9322 | } |
10205 | } |
Line 9323... | Line 10206... | ||
9323 | 10206 | ||
9324 | PIPE_CONF_CHECK_I(pipe_src_w); |
10207 | PIPE_CONF_CHECK_I(pipe_src_w); |
Line -... | Line 10208... | ||
- | 10208 | PIPE_CONF_CHECK_I(pipe_src_h); |
|
- | 10209 | ||
- | 10210 | /* |
|
- | 10211 | * FIXME: BIOS likes to set up a cloned config with lvds+external |
|
- | 10212 | * screen. Since we don't yet re-compute the pipe config when moving |
|
- | 10213 | * just the lvds port away to another pipe the sw tracking won't match. |
|
- | 10214 | * |
|
- | 10215 | * Proper atomic modesets with recomputed global state will fix this. |
|
- | 10216 | * Until then just don't check gmch state for inherited modes. |
|
9325 | PIPE_CONF_CHECK_I(pipe_src_h); |
10217 | */ |
9326 | 10218 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { |
|
9327 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
10219 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9328 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
10220 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
9329 | if (INTEL_INFO(dev)->gen < 4) |
10221 | if (INTEL_INFO(dev)->gen < 4) |
- | 10222 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
|
- | 10223 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
|
9330 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
10224 | } |
9331 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
10225 | |
9332 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10226 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9333 | if (current_config->pch_pfit.enabled) { |
10227 | if (current_config->pch_pfit.enabled) { |
9334 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
10228 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
Line 9339... | Line 10233... | ||
9339 | if (IS_HASWELL(dev)) |
10233 | if (IS_HASWELL(dev)) |
9340 | PIPE_CONF_CHECK_I(ips_enabled); |
10234 | PIPE_CONF_CHECK_I(ips_enabled); |
Line 9341... | Line 10235... | ||
9341 | 10235 | ||
Line -... | Line 10236... | ||
- | 10236 | PIPE_CONF_CHECK_I(double_wide); |
|
- | 10237 | ||
9342 | PIPE_CONF_CHECK_I(double_wide); |
10238 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
9343 | 10239 | ||
9344 | PIPE_CONF_CHECK_I(shared_dpll); |
10240 | PIPE_CONF_CHECK_I(shared_dpll); |
9345 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
10241 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
9346 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
10242 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
- | 10243 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
|
Line 9347... | Line 10244... | ||
9347 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10244 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
9348 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
10245 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
Line 9349... | Line -... | ||
9349 | - | ||
9350 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10246 | |
9351 | PIPE_CONF_CHECK_I(pipe_bpp); |
10247 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9352 | - | ||
Line 9353... | Line 10248... | ||
9353 | if (!HAS_DDI(dev)) { |
10248 | PIPE_CONF_CHECK_I(pipe_bpp); |
9354 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10249 | |
9355 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
10250 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9356 | } |
10251 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
Line 9392... | Line 10287... | ||
9392 | bool active = false; |
10287 | bool active = false; |
9393 | enum pipe pipe, tracked_pipe; |
10288 | enum pipe pipe, tracked_pipe; |
Line 9394... | Line 10289... | ||
9394 | 10289 | ||
9395 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
10290 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
9396 | encoder->base.base.id, |
10291 | encoder->base.base.id, |
Line 9397... | Line 10292... | ||
9397 | drm_get_encoder_name(&encoder->base)); |
10292 | encoder->base.name); |
9398 | 10293 | ||
9399 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
10294 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
9400 | "encoder's stage crtc doesn't match current crtc\n"); |
10295 | "encoder's stage crtc doesn't match current crtc\n"); |
Line 9407... | Line 10302... | ||
9407 | continue; |
10302 | continue; |
9408 | enabled = true; |
10303 | enabled = true; |
9409 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
10304 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
9410 | active = true; |
10305 | active = true; |
9411 | } |
10306 | } |
- | 10307 | /* |
|
- | 10308 | * for MST connectors if we unplug the connector is gone |
|
- | 10309 | * away but the encoder is still connected to a crtc |
|
- | 10310 | * until a modeset happens in response to the hotplug. |
|
- | 10311 | */ |
|
- | 10312 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) |
|
- | 10313 | continue; |
|
- | 10314 | ||
9412 | WARN(!!encoder->base.crtc != enabled, |
10315 | WARN(!!encoder->base.crtc != enabled, |
9413 | "encoder's enabled state mismatch " |
10316 | "encoder's enabled state mismatch " |
9414 | "(expected %i, found %i)\n", |
10317 | "(expected %i, found %i)\n", |
9415 | !!encoder->base.crtc, enabled); |
10318 | !!encoder->base.crtc, enabled); |
9416 | WARN(active && !encoder->base.crtc, |
10319 | WARN(active && !encoder->base.crtc, |
Line 9439... | Line 10342... | ||
9439 | } |
10342 | } |
Line 9440... | Line 10343... | ||
9440 | 10343 | ||
9441 | static void |
10344 | static void |
9442 | check_crtc_state(struct drm_device *dev) |
10345 | check_crtc_state(struct drm_device *dev) |
9443 | { |
10346 | { |
9444 | drm_i915_private_t *dev_priv = dev->dev_private; |
10347 | struct drm_i915_private *dev_priv = dev->dev_private; |
9445 | struct intel_crtc *crtc; |
10348 | struct intel_crtc *crtc; |
9446 | struct intel_encoder *encoder; |
10349 | struct intel_encoder *encoder; |
Line 9447... | Line 10350... | ||
9447 | struct intel_crtc_config pipe_config; |
10350 | struct intel_crtc_config pipe_config; |
9448 | - | ||
9449 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10351 | |
9450 | base.head) { |
10352 | for_each_intel_crtc(dev, crtc) { |
Line 9451... | Line 10353... | ||
9451 | bool enabled = false; |
10353 | bool enabled = false; |
Line 9507... | Line 10409... | ||
9507 | } |
10409 | } |
Line 9508... | Line 10410... | ||
9508 | 10410 | ||
9509 | static void |
10411 | static void |
9510 | check_shared_dpll_state(struct drm_device *dev) |
10412 | check_shared_dpll_state(struct drm_device *dev) |
9511 | { |
10413 | { |
9512 | drm_i915_private_t *dev_priv = dev->dev_private; |
10414 | struct drm_i915_private *dev_priv = dev->dev_private; |
9513 | struct intel_crtc *crtc; |
10415 | struct intel_crtc *crtc; |
9514 | struct intel_dpll_hw_state dpll_hw_state; |
10416 | struct intel_dpll_hw_state dpll_hw_state; |
Line 9515... | Line 10417... | ||
9515 | int i; |
10417 | int i; |
Line 9534... | Line 10436... | ||
9534 | "pll in on but not on in use in sw tracking\n"); |
10436 | "pll in on but not on in use in sw tracking\n"); |
9535 | WARN(pll->on != active, |
10437 | WARN(pll->on != active, |
9536 | "pll on state mismatch (expected %i, found %i)\n", |
10438 | "pll on state mismatch (expected %i, found %i)\n", |
9537 | pll->on, active); |
10439 | pll->on, active); |
Line 9538... | Line 10440... | ||
9538 | 10440 | ||
9539 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
9540 | base.head) { |
10441 | for_each_intel_crtc(dev, crtc) { |
9541 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10442 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
9542 | enabled_crtcs++; |
10443 | enabled_crtcs++; |
9543 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10444 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
9544 | active_crtcs++; |
10445 | active_crtcs++; |
Line 9575... | Line 10476... | ||
9575 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
10476 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
9576 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
10477 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
9577 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
10478 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
9578 | } |
10479 | } |
Line -... | Line 10480... | ||
- | 10480 | ||
- | 10481 | static void update_scanline_offset(struct intel_crtc *crtc) |
|
- | 10482 | { |
|
- | 10483 | struct drm_device *dev = crtc->base.dev; |
|
- | 10484 | ||
- | 10485 | /* |
|
- | 10486 | * The scanline counter increments at the leading edge of hsync. |
|
- | 10487 | * |
|
- | 10488 | * On most platforms it starts counting from vtotal-1 on the |
|
- | 10489 | * first active line. That means the scanline counter value is |
|
- | 10490 | * always one less than what we would expect. Ie. just after |
|
- | 10491 | * start of vblank, which also occurs at start of hsync (on the |
|
- | 10492 | * last active line), the scanline counter will read vblank_start-1. |
|
- | 10493 | * |
|
- | 10494 | * On gen2 the scanline counter starts counting from 1 instead |
|
- | 10495 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
|
- | 10496 | * to keep the value positive), instead of adding one. |
|
- | 10497 | * |
|
- | 10498 | * On HSW+ the behaviour of the scanline counter depends on the output |
|
- | 10499 | * type. For DP ports it behaves like most other platforms, but on HDMI |
|
- | 10500 | * there's an extra 1 line difference. So we need to add two instead of |
|
- | 10501 | * one to the value. |
|
- | 10502 | */ |
|
- | 10503 | if (IS_GEN2(dev)) { |
|
- | 10504 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
|
- | 10505 | int vtotal; |
|
- | 10506 | ||
- | 10507 | vtotal = mode->crtc_vtotal; |
|
- | 10508 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 10509 | vtotal /= 2; |
|
- | 10510 | ||
- | 10511 | crtc->scanline_offset = vtotal - 1; |
|
- | 10512 | } else if (HAS_DDI(dev) && |
|
- | 10513 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { |
|
- | 10514 | crtc->scanline_offset = 2; |
|
- | 10515 | } else |
|
- | 10516 | crtc->scanline_offset = 1; |
|
- | 10517 | } |
|
9579 | 10518 | ||
9580 | static int __intel_set_mode(struct drm_crtc *crtc, |
10519 | static int __intel_set_mode(struct drm_crtc *crtc, |
9581 | struct drm_display_mode *mode, |
10520 | struct drm_display_mode *mode, |
9582 | int x, int y, struct drm_framebuffer *fb) |
10521 | int x, int y, struct drm_framebuffer *fb) |
9583 | { |
10522 | { |
9584 | struct drm_device *dev = crtc->dev; |
10523 | struct drm_device *dev = crtc->dev; |
9585 | drm_i915_private_t *dev_priv = dev->dev_private; |
10524 | struct drm_i915_private *dev_priv = dev->dev_private; |
9586 | struct drm_display_mode *saved_mode; |
10525 | struct drm_display_mode *saved_mode; |
9587 | struct intel_crtc_config *pipe_config = NULL; |
10526 | struct intel_crtc_config *pipe_config = NULL; |
9588 | struct intel_crtc *intel_crtc; |
10527 | struct intel_crtc *intel_crtc; |
9589 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
10528 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
Line 9611... | Line 10550... | ||
9611 | 10550 | ||
9612 | goto out; |
10551 | goto out; |
9613 | } |
10552 | } |
9614 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10553 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
- | 10554 | "[modeset]"); |
|
9615 | "[modeset]"); |
10555 | to_intel_crtc(crtc)->new_config = pipe_config; |
Line 9616... | Line 10556... | ||
9616 | } |
10556 | } |
9617 | 10557 | ||
9618 | /* |
10558 | /* |
9619 | * See if the config requires any additional preparation, e.g. |
10559 | * See if the config requires any additional preparation, e.g. |
9620 | * to adjust global state with pipes off. We need to do this |
10560 | * to adjust global state with pipes off. We need to do this |
9621 | * here so we can get the modeset_pipe updated config for the new |
10561 | * here so we can get the modeset_pipe updated config for the new |
9622 | * mode set on this crtc. For other crtcs we need to use the |
10562 | * mode set on this crtc. For other crtcs we need to use the |
9623 | * adjusted_mode bits in the crtc directly. |
10563 | * adjusted_mode bits in the crtc directly. |
9624 | */ |
10564 | */ |
9625 | if (IS_VALLEYVIEW(dev)) { |
- | |
Line 9626... | Line 10565... | ||
9626 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
10565 | if (IS_VALLEYVIEW(dev)) { |
9627 | modeset_pipes, pipe_config); |
10566 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
9628 | 10567 | ||
Line 9644... | Line 10583... | ||
9644 | if (modeset_pipes) { |
10583 | if (modeset_pipes) { |
9645 | crtc->mode = *mode; |
10584 | crtc->mode = *mode; |
9646 | /* mode_set/enable/disable functions rely on a correct pipe |
10585 | /* mode_set/enable/disable functions rely on a correct pipe |
9647 | * config. */ |
10586 | * config. */ |
9648 | to_intel_crtc(crtc)->config = *pipe_config; |
10587 | to_intel_crtc(crtc)->config = *pipe_config; |
- | 10588 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
|
Line 9649... | Line 10589... | ||
9649 | 10589 | ||
9650 | /* |
10590 | /* |
9651 | * Calculate and store various constants which |
10591 | * Calculate and store various constants which |
9652 | * are later needed by vblank and swap-completion |
10592 | * are later needed by vblank and swap-completion |
Line 9665... | Line 10605... | ||
9665 | 10605 | ||
9666 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10606 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9667 | * on the DPLL. |
10607 | * on the DPLL. |
9668 | */ |
10608 | */ |
- | 10609 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
|
- | 10610 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
|
- | 10611 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
|
- | 10612 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
- | 10613 | ||
- | 10614 | mutex_lock(&dev->struct_mutex); |
|
- | 10615 | ret = intel_pin_and_fence_fb_obj(dev, |
|
- | 10616 | obj, |
|
- | 10617 | NULL); |
|
- | 10618 | if (ret != 0) { |
|
- | 10619 | DRM_ERROR("pin & fence failed\n"); |
|
- | 10620 | mutex_unlock(&dev->struct_mutex); |
|
- | 10621 | goto done; |
|
- | 10622 | } |
|
- | 10623 | if (old_fb) |
|
- | 10624 | intel_unpin_fb_obj(old_obj); |
|
- | 10625 | i915_gem_track_fb(old_obj, obj, |
|
- | 10626 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 10627 | mutex_unlock(&dev->struct_mutex); |
|
- | 10628 | ||
- | 10629 | crtc->primary->fb = fb; |
|
- | 10630 | crtc->x = x; |
|
- | 10631 | crtc->y = y; |
|
9669 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
10632 | |
9670 | ret = intel_crtc_mode_set(&intel_crtc->base, |
10633 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
9671 | x, y, fb); |
10634 | x, y, fb); |
9672 | if (ret) |
10635 | if (ret) |
9673 | goto done; |
10636 | goto done; |
Line 9674... | Line 10637... | ||
9674 | } |
10637 | } |
9675 | 10638 | ||
- | 10639 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
|
- | 10640 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
|
9676 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
10641 | update_scanline_offset(intel_crtc); |
- | 10642 | ||
Line 9677... | Line 10643... | ||
9677 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
10643 | dev_priv->display.crtc_enable(&intel_crtc->base); |
9678 | dev_priv->display.crtc_enable(&intel_crtc->base); |
10644 | } |
9679 | 10645 | ||
9680 | /* FIXME: add subpixel order */ |
10646 | /* FIXME: add subpixel order */ |
Line 9702... | Line 10668... | ||
9702 | return ret; |
10668 | return ret; |
9703 | } |
10669 | } |
Line 9704... | Line 10670... | ||
9704 | 10670 | ||
9705 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10671 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9706 | { |
10672 | { |
9707 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
10673 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
Line 9708... | Line 10674... | ||
9708 | } |
10674 | } |
Line 9709... | Line 10675... | ||
9709 | 10675 | ||
Line 9714... | Line 10680... | ||
9714 | if (!config) |
10680 | if (!config) |
9715 | return; |
10681 | return; |
Line 9716... | Line 10682... | ||
9716 | 10682 | ||
9717 | kfree(config->save_connector_encoders); |
10683 | kfree(config->save_connector_encoders); |
- | 10684 | kfree(config->save_encoder_crtcs); |
|
9718 | kfree(config->save_encoder_crtcs); |
10685 | kfree(config->save_crtc_enabled); |
9719 | kfree(config); |
10686 | kfree(config); |
Line 9720... | Line 10687... | ||
9720 | } |
10687 | } |
9721 | 10688 | ||
9722 | static int intel_set_config_save_state(struct drm_device *dev, |
10689 | static int intel_set_config_save_state(struct drm_device *dev, |
- | 10690 | struct intel_set_config *config) |
|
9723 | struct intel_set_config *config) |
10691 | { |
9724 | { |
10692 | struct drm_crtc *crtc; |
9725 | struct drm_encoder *encoder; |
10693 | struct drm_encoder *encoder; |
Line -... | Line 10694... | ||
- | 10694 | struct drm_connector *connector; |
|
- | 10695 | int count; |
|
- | 10696 | ||
- | 10697 | config->save_crtc_enabled = |
|
- | 10698 | kcalloc(dev->mode_config.num_crtc, |
|
- | 10699 | sizeof(bool), GFP_KERNEL); |
|
9726 | struct drm_connector *connector; |
10700 | if (!config->save_crtc_enabled) |
9727 | int count; |
10701 | return -ENOMEM; |
9728 | 10702 | ||
9729 | config->save_encoder_crtcs = |
10703 | config->save_encoder_crtcs = |
9730 | kcalloc(dev->mode_config.num_encoder, |
10704 | kcalloc(dev->mode_config.num_encoder, |
Line 9741... | Line 10715... | ||
9741 | /* Copy data. Note that driver private data is not affected. |
10715 | /* Copy data. Note that driver private data is not affected. |
9742 | * Should anything bad happen only the expected state is |
10716 | * Should anything bad happen only the expected state is |
9743 | * restored, not the drivers personal bookkeeping. |
10717 | * restored, not the drivers personal bookkeeping. |
9744 | */ |
10718 | */ |
9745 | count = 0; |
10719 | count = 0; |
- | 10720 | for_each_crtc(dev, crtc) { |
|
- | 10721 | config->save_crtc_enabled[count++] = crtc->enabled; |
|
- | 10722 | } |
|
- | 10723 | ||
- | 10724 | count = 0; |
|
9746 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
10725 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
9747 | config->save_encoder_crtcs[count++] = encoder->crtc; |
10726 | config->save_encoder_crtcs[count++] = encoder->crtc; |
9748 | } |
10727 | } |
Line 9749... | Line 10728... | ||
9749 | 10728 | ||
Line 9756... | Line 10735... | ||
9756 | } |
10735 | } |
Line 9757... | Line 10736... | ||
9757 | 10736 | ||
9758 | static void intel_set_config_restore_state(struct drm_device *dev, |
10737 | static void intel_set_config_restore_state(struct drm_device *dev, |
9759 | struct intel_set_config *config) |
10738 | struct intel_set_config *config) |
- | 10739 | { |
|
9760 | { |
10740 | struct intel_crtc *crtc; |
9761 | struct intel_encoder *encoder; |
10741 | struct intel_encoder *encoder; |
9762 | struct intel_connector *connector; |
10742 | struct intel_connector *connector; |
Line 9763... | Line 10743... | ||
9763 | int count; |
10743 | int count; |
- | 10744 | ||
- | 10745 | count = 0; |
|
- | 10746 | for_each_intel_crtc(dev, crtc) { |
|
- | 10747 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
|
- | 10748 | ||
- | 10749 | if (crtc->new_enabled) |
|
- | 10750 | crtc->new_config = &crtc->config; |
|
- | 10751 | else |
|
- | 10752 | crtc->new_config = NULL; |
|
- | 10753 | } |
|
9764 | 10754 | ||
9765 | count = 0; |
10755 | count = 0; |
9766 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10756 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9767 | encoder->new_crtc = |
10757 | encoder->new_crtc = |
Line 9802... | Line 10792... | ||
9802 | 10792 | ||
9803 | /* We should be able to check here if the fb has the same properties |
10793 | /* We should be able to check here if the fb has the same properties |
9804 | * and then just flip_or_move it */ |
10794 | * and then just flip_or_move it */ |
9805 | if (is_crtc_connector_off(set)) { |
10795 | if (is_crtc_connector_off(set)) { |
9806 | config->mode_changed = true; |
10796 | config->mode_changed = true; |
- | 10797 | } else if (set->crtc->primary->fb != set->fb) { |
|
9807 | } else if (set->crtc->fb != set->fb) { |
10798 | /* |
- | 10799 | * If we have no fb, we can only flip as long as the crtc is |
|
- | 10800 | * active, otherwise we need a full mode set. The crtc may |
|
- | 10801 | * be active if we've only disabled the primary plane, or |
|
- | 10802 | * in fastboot situations. |
|
9808 | /* If we have no fb then treat it as a full mode set */ |
10803 | */ |
9809 | if (set->crtc->fb == NULL) { |
10804 | if (set->crtc->primary->fb == NULL) { |
9810 | struct intel_crtc *intel_crtc = |
10805 | struct intel_crtc *intel_crtc = |
Line 9811... | Line 10806... | ||
9811 | to_intel_crtc(set->crtc); |
10806 | to_intel_crtc(set->crtc); |
9812 | 10807 | ||
9813 | if (intel_crtc->active && i915_fastboot) { |
10808 | if (intel_crtc->active) { |
9814 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10809 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9815 | config->fb_changed = true; |
10810 | config->fb_changed = true; |
9816 | } else { |
10811 | } else { |
9817 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
10812 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9818 | config->mode_changed = true; |
10813 | config->mode_changed = true; |
9819 | } |
10814 | } |
9820 | } else if (set->fb == NULL) { |
10815 | } else if (set->fb == NULL) { |
9821 | config->mode_changed = true; |
10816 | config->mode_changed = true; |
9822 | } else if (set->fb->pixel_format != |
10817 | } else if (set->fb->pixel_format != |
9823 | set->crtc->fb->pixel_format) { |
10818 | set->crtc->primary->fb->pixel_format) { |
9824 | config->mode_changed = true; |
10819 | config->mode_changed = true; |
9825 | } else { |
10820 | } else { |
9826 | config->fb_changed = true; |
10821 | config->fb_changed = true; |
Line 9844... | Line 10839... | ||
9844 | static int |
10839 | static int |
9845 | intel_modeset_stage_output_state(struct drm_device *dev, |
10840 | intel_modeset_stage_output_state(struct drm_device *dev, |
9846 | struct drm_mode_set *set, |
10841 | struct drm_mode_set *set, |
9847 | struct intel_set_config *config) |
10842 | struct intel_set_config *config) |
9848 | { |
10843 | { |
9849 | struct drm_crtc *new_crtc; |
- | |
9850 | struct intel_connector *connector; |
10844 | struct intel_connector *connector; |
9851 | struct intel_encoder *encoder; |
10845 | struct intel_encoder *encoder; |
- | 10846 | struct intel_crtc *crtc; |
|
9852 | int ro; |
10847 | int ro; |
Line 9853... | Line 10848... | ||
9853 | 10848 | ||
9854 | /* The upper layers ensure that we either disable a crtc or have a list |
10849 | /* The upper layers ensure that we either disable a crtc or have a list |
9855 | * of connectors. For paranoia, double-check this. */ |
10850 | * of connectors. For paranoia, double-check this. */ |
Line 9860... | Line 10855... | ||
9860 | base.head) { |
10855 | base.head) { |
9861 | /* Otherwise traverse passed in connector list and get encoders |
10856 | /* Otherwise traverse passed in connector list and get encoders |
9862 | * for them. */ |
10857 | * for them. */ |
9863 | for (ro = 0; ro < set->num_connectors; ro++) { |
10858 | for (ro = 0; ro < set->num_connectors; ro++) { |
9864 | if (set->connectors[ro] == &connector->base) { |
10859 | if (set->connectors[ro] == &connector->base) { |
9865 | connector->new_encoder = connector->encoder; |
10860 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
9866 | break; |
10861 | break; |
9867 | } |
10862 | } |
9868 | } |
10863 | } |
Line 9869... | Line 10864... | ||
9869 | 10864 | ||
Line 9875... | Line 10870... | ||
9875 | connector->base.encoder->crtc == set->crtc) { |
10870 | connector->base.encoder->crtc == set->crtc) { |
9876 | connector->new_encoder = NULL; |
10871 | connector->new_encoder = NULL; |
Line 9877... | Line 10872... | ||
9877 | 10872 | ||
9878 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
10873 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9879 | connector->base.base.id, |
10874 | connector->base.base.id, |
9880 | drm_get_connector_name(&connector->base)); |
10875 | connector->base.name); |
Line 9881... | Line 10876... | ||
9881 | } |
10876 | } |
9882 | 10877 | ||
Line 9889... | Line 10884... | ||
9889 | /* connector->new_encoder is now updated for all connectors. */ |
10884 | /* connector->new_encoder is now updated for all connectors. */ |
Line 9890... | Line 10885... | ||
9890 | 10885 | ||
9891 | /* Update crtc of enabled connectors. */ |
10886 | /* Update crtc of enabled connectors. */ |
9892 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10887 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
- | 10888 | base.head) { |
|
- | 10889 | struct drm_crtc *new_crtc; |
|
9893 | base.head) { |
10890 | |
9894 | if (!connector->new_encoder) |
10891 | if (!connector->new_encoder) |
Line 9895... | Line 10892... | ||
9895 | continue; |
10892 | continue; |
Line 9904... | Line 10901... | ||
9904 | /* Make sure the new CRTC will work with the encoder */ |
10901 | /* Make sure the new CRTC will work with the encoder */ |
9905 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10902 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9906 | new_crtc)) { |
10903 | new_crtc)) { |
9907 | return -EINVAL; |
10904 | return -EINVAL; |
9908 | } |
10905 | } |
9909 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10906 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
Line 9910... | Line 10907... | ||
9910 | 10907 | ||
9911 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
10908 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9912 | connector->base.base.id, |
10909 | connector->base.base.id, |
9913 | drm_get_connector_name(&connector->base), |
10910 | connector->base.name, |
9914 | new_crtc->base.id); |
10911 | new_crtc->base.id); |
Line 9915... | Line 10912... | ||
9915 | } |
10912 | } |
9916 | 10913 | ||
Line 9938... | Line 10935... | ||
9938 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
10935 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9939 | config->mode_changed = true; |
10936 | config->mode_changed = true; |
9940 | } |
10937 | } |
9941 | } |
10938 | } |
9942 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
10939 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
- | 10940 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
|
- | 10941 | base.head) { |
|
- | 10942 | if (connector->new_encoder) |
|
- | 10943 | if (connector->new_encoder != connector->encoder) |
|
- | 10944 | connector->encoder = connector->new_encoder; |
|
- | 10945 | } |
|
- | 10946 | for_each_intel_crtc(dev, crtc) { |
|
- | 10947 | crtc->new_enabled = false; |
|
- | 10948 | ||
- | 10949 | list_for_each_entry(encoder, |
|
- | 10950 | &dev->mode_config.encoder_list, |
|
- | 10951 | base.head) { |
|
- | 10952 | if (encoder->new_crtc == crtc) { |
|
- | 10953 | crtc->new_enabled = true; |
|
- | 10954 | break; |
|
- | 10955 | } |
|
- | 10956 | } |
|
- | 10957 | ||
- | 10958 | if (crtc->new_enabled != crtc->base.enabled) { |
|
- | 10959 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
|
- | 10960 | crtc->new_enabled ? "en" : "dis"); |
|
- | 10961 | config->mode_changed = true; |
|
- | 10962 | } |
|
- | 10963 | ||
- | 10964 | if (crtc->new_enabled) |
|
- | 10965 | crtc->new_config = &crtc->config; |
|
- | 10966 | else |
|
- | 10967 | crtc->new_config = NULL; |
|
- | 10968 | } |
|
Line 9943... | Line 10969... | ||
9943 | 10969 | ||
9944 | return 0; |
10970 | return 0; |
Line -... | Line 10971... | ||
- | 10971 | } |
|
- | 10972 | ||
- | 10973 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
|
- | 10974 | { |
|
- | 10975 | struct drm_device *dev = crtc->base.dev; |
|
- | 10976 | struct intel_encoder *encoder; |
|
- | 10977 | struct intel_connector *connector; |
|
- | 10978 | ||
- | 10979 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", |
|
- | 10980 | pipe_name(crtc->pipe)); |
|
- | 10981 | ||
- | 10982 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
|
- | 10983 | if (connector->new_encoder && |
|
- | 10984 | connector->new_encoder->new_crtc == crtc) |
|
- | 10985 | connector->new_encoder = NULL; |
|
- | 10986 | } |
|
- | 10987 | ||
- | 10988 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
|
- | 10989 | if (encoder->new_crtc == crtc) |
|
- | 10990 | encoder->new_crtc = NULL; |
|
- | 10991 | } |
|
- | 10992 | ||
- | 10993 | crtc->new_enabled = false; |
|
- | 10994 | crtc->new_config = NULL; |
|
9945 | } |
10995 | } |
9946 | 10996 | ||
9947 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10997 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9948 | { |
10998 | { |
9949 | struct drm_device *dev; |
10999 | struct drm_device *dev; |
Line 9980... | Line 11030... | ||
9980 | 11030 | ||
9981 | save_set.crtc = set->crtc; |
11031 | save_set.crtc = set->crtc; |
9982 | save_set.mode = &set->crtc->mode; |
11032 | save_set.mode = &set->crtc->mode; |
9983 | save_set.x = set->crtc->x; |
11033 | save_set.x = set->crtc->x; |
9984 | save_set.y = set->crtc->y; |
11034 | save_set.y = set->crtc->y; |
Line 9985... | Line 11035... | ||
9985 | save_set.fb = set->crtc->fb; |
11035 | save_set.fb = set->crtc->primary->fb; |
9986 | 11036 | ||
9987 | /* Compute whether we need a full modeset, only an fb base update or no |
11037 | /* Compute whether we need a full modeset, only an fb base update or no |
9988 | * change at all. In the future we might also check whether only the |
11038 | * change at all. In the future we might also check whether only the |
Line 9996... | Line 11046... | ||
9996 | 11046 | ||
9997 | if (config->mode_changed) { |
11047 | if (config->mode_changed) { |
9998 | ret = intel_set_mode(set->crtc, set->mode, |
11048 | ret = intel_set_mode(set->crtc, set->mode, |
9999 | set->x, set->y, set->fb); |
11049 | set->x, set->y, set->fb); |
- | 11050 | } else if (config->fb_changed) { |
|
10000 | } else if (config->fb_changed) { |
11051 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 11052 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
|
Line 10001... | Line 11053... | ||
10001 | // intel_crtc_wait_for_pending_flips(set->crtc); |
11053 | |
10002 | 11054 | ||
- | 11055 | ret = intel_pipe_set_base(set->crtc, |
|
- | 11056 | set->x, set->y, set->fb); |
|
- | 11057 | ||
- | 11058 | /* |
|
- | 11059 | * We need to make sure the primary plane is re-enabled if it |
|
- | 11060 | * has previously been turned off. |
|
- | 11061 | */ |
|
- | 11062 | if (!intel_crtc->primary_enabled && ret == 0) { |
|
- | 11063 | WARN_ON(!intel_crtc->active); |
|
- | 11064 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, |
|
- | 11065 | intel_crtc->pipe); |
|
10003 | ret = intel_pipe_set_base(set->crtc, |
11066 | } |
10004 | set->x, set->y, set->fb); |
11067 | |
10005 | /* |
11068 | /* |
10006 | * In the fastboot case this may be our only check of the |
11069 | * In the fastboot case this may be our only check of the |
10007 | * state after boot. It would be better to only do it on |
11070 | * state after boot. It would be better to only do it on |
10008 | * the first update, but we don't have a nice way of doing that |
11071 | * the first update, but we don't have a nice way of doing that |
10009 | * (and really, set_config isn't used much for high freq page |
11072 | * (and really, set_config isn't used much for high freq page |
10010 | * flipping, so increasing its cost here shouldn't be a big |
11073 | * flipping, so increasing its cost here shouldn't be a big |
10011 | * deal). |
11074 | * deal). |
10012 | */ |
11075 | */ |
10013 | if (i915_fastboot && ret == 0) |
11076 | if (i915.fastboot && ret == 0) |
Line 10014... | Line 11077... | ||
10014 | intel_modeset_check_state(set->crtc->dev); |
11077 | intel_modeset_check_state(set->crtc->dev); |
10015 | } |
11078 | } |
10016 | 11079 | ||
10017 | if (ret) { |
11080 | if (ret) { |
10018 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11081 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
Line -... | Line 11082... | ||
- | 11082 | set->crtc->base.id, ret); |
|
- | 11083 | fail: |
|
- | 11084 | intel_set_config_restore_state(dev, config); |
|
- | 11085 | ||
- | 11086 | /* |
|
- | 11087 | * HACK: if the pipe was on, but we didn't have a framebuffer, |
|
- | 11088 | * force the pipe off to avoid oopsing in the modeset code |
|
- | 11089 | * due to fb==NULL. This should only happen during boot since |
|
- | 11090 | * we don't yet reconstruct the FB from the hardware state. |
|
10019 | set->crtc->base.id, ret); |
11091 | */ |
10020 | fail: |
11092 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
10021 | intel_set_config_restore_state(dev, config); |
11093 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
10022 | 11094 | ||
10023 | /* Try to restore the config */ |
11095 | /* Try to restore the config */ |
Line 10031... | Line 11103... | ||
10031 | intel_set_config_free(config); |
11103 | intel_set_config_free(config); |
10032 | return ret; |
11104 | return ret; |
10033 | } |
11105 | } |
Line 10034... | Line 11106... | ||
10034 | 11106 | ||
10035 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
- | |
10036 | // .cursor_set = intel_crtc_cursor_set, |
- | |
10037 | .cursor_move = intel_crtc_cursor_move, |
11107 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
10038 | .gamma_set = intel_crtc_gamma_set, |
11108 | .gamma_set = intel_crtc_gamma_set, |
10039 | .set_config = intel_crtc_set_config, |
11109 | .set_config = intel_crtc_set_config, |
10040 | .destroy = intel_crtc_destroy, |
11110 | .destroy = intel_crtc_destroy, |
10041 | // .page_flip = intel_crtc_page_flip, |
11111 | // .page_flip = intel_crtc_page_flip, |
Line 10042... | Line -... | ||
10042 | }; |
- | |
10043 | - | ||
10044 | static void intel_cpu_pll_init(struct drm_device *dev) |
- | |
10045 | { |
- | |
10046 | if (HAS_DDI(dev)) |
- | |
10047 | intel_ddi_pll_init(dev); |
- | |
10048 | } |
11112 | }; |
10049 | 11113 | ||
10050 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11114 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10051 | struct intel_shared_dpll *pll, |
11115 | struct intel_shared_dpll *pll, |
10052 | struct intel_dpll_hw_state *hw_state) |
11116 | struct intel_dpll_hw_state *hw_state) |
Line -... | Line 11117... | ||
- | 11117 | { |
|
- | 11118 | uint32_t val; |
|
- | 11119 | ||
10053 | { |
11120 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
10054 | uint32_t val; |
11121 | return false; |
10055 | 11122 | ||
10056 | val = I915_READ(PCH_DPLL(pll->id)); |
11123 | val = I915_READ(PCH_DPLL(pll->id)); |
Line 10095... | Line 11162... | ||
10095 | { |
11162 | { |
10096 | struct drm_device *dev = dev_priv->dev; |
11163 | struct drm_device *dev = dev_priv->dev; |
10097 | struct intel_crtc *crtc; |
11164 | struct intel_crtc *crtc; |
Line 10098... | Line 11165... | ||
10098 | 11165 | ||
10099 | /* Make sure no transcoder isn't still depending on us. */ |
11166 | /* Make sure no transcoder isn't still depending on us. */ |
10100 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
11167 | for_each_intel_crtc(dev, crtc) { |
10101 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11168 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10102 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
11169 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
Line 10103... | Line 11170... | ||
10103 | } |
11170 | } |
Line 10132... | Line 11199... | ||
10132 | 11199 | ||
10133 | static void intel_shared_dpll_init(struct drm_device *dev) |
11200 | static void intel_shared_dpll_init(struct drm_device *dev) |
10134 | { |
11201 | { |
Line -... | Line 11202... | ||
- | 11202 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11203 | ||
10135 | struct drm_i915_private *dev_priv = dev->dev_private; |
11204 | if (HAS_DDI(dev)) |
10136 | 11205 | intel_ddi_pll_init(dev); |
|
10137 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
11206 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
10138 | ibx_pch_dpll_init(dev); |
11207 | ibx_pch_dpll_init(dev); |
Line 10139... | Line 11208... | ||
10139 | else |
11208 | else |
10140 | dev_priv->num_shared_dpll = 0; |
11209 | dev_priv->num_shared_dpll = 0; |
Line -... | Line 11210... | ||
- | 11210 | ||
- | 11211 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
|
- | 11212 | } |
|
- | 11213 | ||
- | 11214 | static int |
|
- | 11215 | intel_primary_plane_disable(struct drm_plane *plane) |
|
- | 11216 | { |
|
- | 11217 | struct drm_device *dev = plane->dev; |
|
- | 11218 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11219 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11220 | struct intel_crtc *intel_crtc; |
|
- | 11221 | ||
- | 11222 | if (!plane->fb) |
|
- | 11223 | return 0; |
|
- | 11224 | ||
- | 11225 | BUG_ON(!plane->crtc); |
|
- | 11226 | ||
- | 11227 | intel_crtc = to_intel_crtc(plane->crtc); |
|
- | 11228 | ||
- | 11229 | /* |
|
- | 11230 | * Even though we checked plane->fb above, it's still possible that |
|
- | 11231 | * the primary plane has been implicitly disabled because the crtc |
|
- | 11232 | * coordinates given weren't visible, or because we detected |
|
- | 11233 | * that it was 100% covered by a sprite plane. Or, the CRTC may be |
|
- | 11234 | * off and we've set a fb, but haven't actually turned on the CRTC yet. |
|
- | 11235 | * In either case, we need to unpin the FB and let the fb pointer get |
|
- | 11236 | * updated, but otherwise we don't need to touch the hardware. |
|
- | 11237 | */ |
|
- | 11238 | if (!intel_crtc->primary_enabled) |
|
- | 11239 | goto disable_unpin; |
|
- | 11240 | ||
- | 11241 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, |
|
- | 11242 | intel_plane->pipe); |
|
- | 11243 | disable_unpin: |
|
- | 11244 | mutex_lock(&dev->struct_mutex); |
|
- | 11245 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
|
- | 11246 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11247 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
|
- | 11248 | mutex_unlock(&dev->struct_mutex); |
|
- | 11249 | plane->fb = NULL; |
|
- | 11250 | ||
- | 11251 | return 0; |
|
- | 11252 | } |
|
- | 11253 | ||
- | 11254 | static int |
|
- | 11255 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, |
|
- | 11256 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
|
- | 11257 | unsigned int crtc_w, unsigned int crtc_h, |
|
- | 11258 | uint32_t src_x, uint32_t src_y, |
|
- | 11259 | uint32_t src_w, uint32_t src_h) |
|
- | 11260 | { |
|
- | 11261 | struct drm_device *dev = crtc->dev; |
|
- | 11262 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11263 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 11264 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11265 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
- | 11266 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
|
- | 11267 | struct drm_rect dest = { |
|
- | 11268 | /* integer pixels */ |
|
- | 11269 | .x1 = crtc_x, |
|
- | 11270 | .y1 = crtc_y, |
|
- | 11271 | .x2 = crtc_x + crtc_w, |
|
- | 11272 | .y2 = crtc_y + crtc_h, |
|
- | 11273 | }; |
|
- | 11274 | struct drm_rect src = { |
|
- | 11275 | /* 16.16 fixed point */ |
|
- | 11276 | .x1 = src_x, |
|
- | 11277 | .y1 = src_y, |
|
- | 11278 | .x2 = src_x + src_w, |
|
- | 11279 | .y2 = src_y + src_h, |
|
- | 11280 | }; |
|
- | 11281 | const struct drm_rect clip = { |
|
- | 11282 | /* integer pixels */ |
|
- | 11283 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
|
- | 11284 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
|
- | 11285 | }; |
|
- | 11286 | bool visible; |
|
- | 11287 | int ret; |
|
- | 11288 | ||
- | 11289 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
|
- | 11290 | &src, &dest, &clip, |
|
- | 11291 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11292 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11293 | false, true, &visible); |
|
- | 11294 | ||
- | 11295 | if (ret) |
|
- | 11296 | return ret; |
|
- | 11297 | ||
- | 11298 | /* |
|
- | 11299 | * If the CRTC isn't enabled, we're just pinning the framebuffer, |
|
- | 11300 | * updating the fb pointer, and returning without touching the |
|
- | 11301 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to |
|
- | 11302 | * turn on the display with all planes setup as desired. |
|
- | 11303 | */ |
|
- | 11304 | if (!crtc->enabled) { |
|
- | 11305 | mutex_lock(&dev->struct_mutex); |
|
- | 11306 | ||
- | 11307 | /* |
|
- | 11308 | * If we already called setplane while the crtc was disabled, |
|
- | 11309 | * we may have an fb pinned; unpin it. |
|
- | 11310 | */ |
|
- | 11311 | if (plane->fb) |
|
- | 11312 | intel_unpin_fb_obj(old_obj); |
|
- | 11313 | ||
- | 11314 | i915_gem_track_fb(old_obj, obj, |
|
- | 11315 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11316 | ||
- | 11317 | /* Pin and return without programming hardware */ |
|
- | 11318 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
|
- | 11319 | mutex_unlock(&dev->struct_mutex); |
|
- | 11320 | ||
- | 11321 | return ret; |
|
- | 11322 | } |
|
- | 11323 | ||
- | 11324 | ||
- | 11325 | /* |
|
- | 11326 | * If clipping results in a non-visible primary plane, we'll disable |
|
- | 11327 | * the primary plane. Note that this is a bit different than what |
|
- | 11328 | * happens if userspace explicitly disables the plane by passing fb=0 |
|
- | 11329 | * because plane->fb still gets set and pinned. |
|
- | 11330 | */ |
|
- | 11331 | if (!visible) { |
|
- | 11332 | mutex_lock(&dev->struct_mutex); |
|
- | 11333 | ||
- | 11334 | /* |
|
- | 11335 | * Try to pin the new fb first so that we can bail out if we |
|
- | 11336 | * fail. |
|
- | 11337 | */ |
|
- | 11338 | if (plane->fb != fb) { |
|
- | 11339 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
|
- | 11340 | if (ret) { |
|
- | 11341 | mutex_unlock(&dev->struct_mutex); |
|
- | 11342 | return ret; |
|
- | 11343 | } |
|
- | 11344 | } |
|
- | 11345 | ||
- | 11346 | i915_gem_track_fb(old_obj, obj, |
|
- | 11347 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
|
- | 11348 | ||
- | 11349 | if (intel_crtc->primary_enabled) |
|
- | 11350 | intel_disable_primary_hw_plane(dev_priv, |
|
- | 11351 | intel_plane->plane, |
|
- | 11352 | intel_plane->pipe); |
|
- | 11353 | ||
- | 11354 | ||
- | 11355 | if (plane->fb != fb) |
|
- | 11356 | if (plane->fb) |
|
- | 11357 | intel_unpin_fb_obj(old_obj); |
|
- | 11358 | ||
- | 11359 | mutex_unlock(&dev->struct_mutex); |
|
- | 11360 | ||
- | 11361 | return 0; |
|
- | 11362 | } |
|
- | 11363 | ||
- | 11364 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); |
|
- | 11365 | if (ret) |
|
- | 11366 | return ret; |
|
- | 11367 | ||
- | 11368 | if (!intel_crtc->primary_enabled) |
|
- | 11369 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, |
|
- | 11370 | intel_crtc->pipe); |
|
- | 11371 | ||
- | 11372 | return 0; |
|
- | 11373 | } |
|
- | 11374 | ||
- | 11375 | /* Common destruction function for both primary and cursor planes */ |
|
- | 11376 | static void intel_plane_destroy(struct drm_plane *plane) |
|
- | 11377 | { |
|
- | 11378 | struct intel_plane *intel_plane = to_intel_plane(plane); |
|
- | 11379 | drm_plane_cleanup(plane); |
|
- | 11380 | kfree(intel_plane); |
|
- | 11381 | } |
|
- | 11382 | ||
- | 11383 | static const struct drm_plane_funcs intel_primary_plane_funcs = { |
|
- | 11384 | .update_plane = intel_primary_plane_setplane, |
|
- | 11385 | .disable_plane = intel_primary_plane_disable, |
|
- | 11386 | .destroy = intel_plane_destroy, |
|
- | 11387 | }; |
|
- | 11388 | ||
- | 11389 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
|
- | 11390 | int pipe) |
|
- | 11391 | { |
|
- | 11392 | struct intel_plane *primary; |
|
- | 11393 | const uint32_t *intel_primary_formats; |
|
- | 11394 | int num_formats; |
|
- | 11395 | ||
- | 11396 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
|
- | 11397 | if (primary == NULL) |
|
- | 11398 | return NULL; |
|
- | 11399 | ||
- | 11400 | primary->can_scale = false; |
|
- | 11401 | primary->max_downscale = 1; |
|
- | 11402 | primary->pipe = pipe; |
|
- | 11403 | primary->plane = pipe; |
|
- | 11404 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
|
- | 11405 | primary->plane = !pipe; |
|
- | 11406 | ||
- | 11407 | if (INTEL_INFO(dev)->gen <= 3) { |
|
- | 11408 | intel_primary_formats = intel_primary_formats_gen2; |
|
- | 11409 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); |
|
- | 11410 | } else { |
|
- | 11411 | intel_primary_formats = intel_primary_formats_gen4; |
|
- | 11412 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); |
|
- | 11413 | } |
|
- | 11414 | ||
- | 11415 | drm_universal_plane_init(dev, &primary->base, 0, |
|
- | 11416 | &intel_primary_plane_funcs, |
|
- | 11417 | intel_primary_formats, num_formats, |
|
- | 11418 | DRM_PLANE_TYPE_PRIMARY); |
|
- | 11419 | return &primary->base; |
|
- | 11420 | } |
|
- | 11421 | ||
- | 11422 | static int |
|
- | 11423 | intel_cursor_plane_disable(struct drm_plane *plane) |
|
- | 11424 | { |
|
- | 11425 | if (!plane->fb) |
|
- | 11426 | return 0; |
|
- | 11427 | ||
- | 11428 | BUG_ON(!plane->crtc); |
|
- | 11429 | ||
- | 11430 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); |
|
- | 11431 | } |
|
- | 11432 | ||
- | 11433 | static int |
|
- | 11434 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
|
- | 11435 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
|
- | 11436 | unsigned int crtc_w, unsigned int crtc_h, |
|
- | 11437 | uint32_t src_x, uint32_t src_y, |
|
- | 11438 | uint32_t src_w, uint32_t src_h) |
|
- | 11439 | { |
|
- | 11440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 11441 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
|
- | 11442 | struct drm_i915_gem_object *obj = intel_fb->obj; |
|
- | 11443 | struct drm_rect dest = { |
|
- | 11444 | /* integer pixels */ |
|
- | 11445 | .x1 = crtc_x, |
|
- | 11446 | .y1 = crtc_y, |
|
- | 11447 | .x2 = crtc_x + crtc_w, |
|
- | 11448 | .y2 = crtc_y + crtc_h, |
|
- | 11449 | }; |
|
- | 11450 | struct drm_rect src = { |
|
- | 11451 | /* 16.16 fixed point */ |
|
- | 11452 | .x1 = src_x, |
|
- | 11453 | .y1 = src_y, |
|
- | 11454 | .x2 = src_x + src_w, |
|
- | 11455 | .y2 = src_y + src_h, |
|
- | 11456 | }; |
|
- | 11457 | const struct drm_rect clip = { |
|
- | 11458 | /* integer pixels */ |
|
- | 11459 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
|
- | 11460 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
|
- | 11461 | }; |
|
- | 11462 | bool visible; |
|
- | 11463 | int ret; |
|
- | 11464 | ||
- | 11465 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
|
- | 11466 | &src, &dest, &clip, |
|
- | 11467 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11468 | DRM_PLANE_HELPER_NO_SCALING, |
|
- | 11469 | true, true, &visible); |
|
- | 11470 | if (ret) |
|
- | 11471 | return ret; |
|
- | 11472 | ||
- | 11473 | crtc->cursor_x = crtc_x; |
|
- | 11474 | crtc->cursor_y = crtc_y; |
|
- | 11475 | if (fb != crtc->cursor->fb) { |
|
- | 11476 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
|
- | 11477 | } else { |
|
- | 11478 | intel_crtc_update_cursor(crtc, visible); |
|
- | 11479 | return 0; |
|
- | 11480 | } |
|
- | 11481 | } |
|
- | 11482 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
|
- | 11483 | .update_plane = intel_cursor_plane_update, |
|
- | 11484 | .disable_plane = intel_cursor_plane_disable, |
|
- | 11485 | .destroy = intel_plane_destroy, |
|
- | 11486 | }; |
|
- | 11487 | ||
- | 11488 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
|
- | 11489 | int pipe) |
|
- | 11490 | { |
|
- | 11491 | struct intel_plane *cursor; |
|
- | 11492 | ||
- | 11493 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
|
- | 11494 | if (cursor == NULL) |
|
- | 11495 | return NULL; |
|
- | 11496 | ||
- | 11497 | cursor->can_scale = false; |
|
- | 11498 | cursor->max_downscale = 1; |
|
- | 11499 | cursor->pipe = pipe; |
|
- | 11500 | cursor->plane = pipe; |
|
- | 11501 | ||
- | 11502 | drm_universal_plane_init(dev, &cursor->base, 0, |
|
- | 11503 | &intel_cursor_plane_funcs, |
|
- | 11504 | intel_cursor_formats, |
|
- | 11505 | ARRAY_SIZE(intel_cursor_formats), |
|
10141 | 11506 | DRM_PLANE_TYPE_CURSOR); |
|
10142 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
11507 | return &cursor->base; |
10143 | } |
11508 | } |
10144 | 11509 | ||
- | 11510 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
|
- | 11511 | { |
|
10145 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
11512 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10146... | Line 11513... | ||
10146 | { |
11513 | struct intel_crtc *intel_crtc; |
10147 | drm_i915_private_t *dev_priv = dev->dev_private; |
11514 | struct drm_plane *primary = NULL; |
10148 | struct intel_crtc *intel_crtc; |
11515 | struct drm_plane *cursor = NULL; |
Line -... | Line 11516... | ||
- | 11516 | int i, ret; |
|
- | 11517 | ||
- | 11518 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
|
- | 11519 | if (intel_crtc == NULL) |
|
- | 11520 | return; |
|
- | 11521 | ||
- | 11522 | primary = intel_primary_plane_create(dev, pipe); |
|
- | 11523 | if (!primary) |
|
10149 | int i; |
11524 | goto fail; |
- | 11525 | ||
- | 11526 | cursor = intel_cursor_plane_create(dev, pipe); |
|
- | 11527 | if (!cursor) |
|
Line 10150... | Line 11528... | ||
10150 | 11528 | goto fail; |
|
10151 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
11529 | |
10152 | if (intel_crtc == NULL) |
11530 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
10153 | return; |
11531 | cursor, &intel_crtc_funcs); |
10154 | 11532 | if (ret) |
|
10155 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
11533 | goto fail; |
Line 10156... | Line 11534... | ||
10156 | 11534 | ||
10157 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
11535 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
10158 | for (i = 0; i < 256; i++) { |
11536 | for (i = 0; i < 256; i++) { |
10159 | intel_crtc->lut_r[i] = i; |
11537 | intel_crtc->lut_r[i] = i; |
10160 | intel_crtc->lut_g[i] = i; |
11538 | intel_crtc->lut_g[i] = i; |
10161 | intel_crtc->lut_b[i] = i; |
11539 | intel_crtc->lut_b[i] = i; |
10162 | } |
11540 | } |
10163 | 11541 | ||
10164 | /* |
11542 | /* |
10165 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
11543 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
Line -... | Line 11544... | ||
- | 11544 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
|
- | 11545 | */ |
|
- | 11546 | intel_crtc->pipe = pipe; |
|
- | 11547 | intel_crtc->plane = pipe; |
|
- | 11548 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
|
10166 | * is hooked to plane B. Hence we want plane A feeding pipe B. |
11549 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
10167 | */ |
11550 | intel_crtc->plane = !pipe; |
10168 | intel_crtc->pipe = pipe; |
11551 | } |
10169 | intel_crtc->plane = pipe; |
11552 | |
Line 10170... | Line 11553... | ||
10170 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
11553 | intel_crtc->cursor_base = ~0; |
- | 11554 | intel_crtc->cursor_cntl = ~0; |
|
- | 11555 | ||
- | 11556 | init_waitqueue_head(&intel_crtc->vbl_wait); |
|
- | 11557 | ||
- | 11558 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
|
- | 11559 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
|
- | 11560 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
|
- | 11561 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
|
- | 11562 | ||
- | 11563 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
|
10171 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
11564 | |
Line 10172... | Line 11565... | ||
10172 | intel_crtc->plane = !pipe; |
11565 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
10173 | } |
11566 | return; |
10174 | 11567 | ||
- | 11568 | fail: |
|
Line 10175... | Line 11569... | ||
10175 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11569 | if (primary) |
Line 10176... | Line 11570... | ||
10176 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
11570 | drm_plane_cleanup(primary); |
10177 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
11571 | if (cursor) |
Line 10178... | Line 11572... | ||
10178 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
11572 | drm_plane_cleanup(cursor); |
Line 10194... | Line 11588... | ||
10194 | 11588 | ||
10195 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
11589 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
10196 | struct drm_file *file) |
11590 | struct drm_file *file) |
10197 | { |
11591 | { |
10198 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
11592 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
10199 | struct drm_mode_object *drmmode_obj; |
11593 | struct drm_crtc *drmmode_crtc; |
Line 10200... | Line 11594... | ||
10200 | struct intel_crtc *crtc; |
11594 | struct intel_crtc *crtc; |
10201 | 11595 | ||
Line 10202... | Line 11596... | ||
10202 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11596 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10203 | return -ENODEV; |
- | |
Line 10204... | Line 11597... | ||
10204 | 11597 | return -ENODEV; |
|
10205 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11598 | |
10206 | DRM_MODE_OBJECT_CRTC); |
11599 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
10207 | 11600 | ||
Line 10208... | Line 11601... | ||
10208 | if (!drmmode_obj) { |
11601 | if (!drmmode_crtc) { |
10209 | DRM_ERROR("no such CRTC id\n"); |
11602 | DRM_ERROR("no such CRTC id\n"); |
Line 10210... | Line 11603... | ||
10210 | return -ENOENT; |
11603 | return -ENOENT; |
10211 | } |
11604 | } |
Line 10223... | Line 11616... | ||
10223 | int index_mask = 0; |
11616 | int index_mask = 0; |
10224 | int entry = 0; |
11617 | int entry = 0; |
Line 10225... | Line 11618... | ||
10225 | 11618 | ||
10226 | list_for_each_entry(source_encoder, |
11619 | list_for_each_entry(source_encoder, |
10227 | &dev->mode_config.encoder_list, base.head) { |
- | |
10228 | - | ||
10229 | if (encoder == source_encoder) |
- | |
10230 | index_mask |= (1 << entry); |
- | |
10231 | - | ||
10232 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
11620 | &dev->mode_config.encoder_list, base.head) { |
10233 | if (encoder->cloneable && source_encoder->cloneable) |
11621 | if (encoders_cloneable(encoder, source_encoder)) |
Line 10234... | Line 11622... | ||
10234 | index_mask |= (1 << entry); |
11622 | index_mask |= (1 << entry); |
10235 | 11623 | ||
Line 10247... | Line 11635... | ||
10247 | return false; |
11635 | return false; |
Line 10248... | Line 11636... | ||
10248 | 11636 | ||
10249 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
11637 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
Line 10250... | Line -... | ||
10250 | return false; |
- | |
10251 | 11638 | return false; |
|
10252 | if (IS_GEN5(dev) && |
11639 | |
Line 10253... | Line 11640... | ||
10253 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
11640 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
10254 | return false; |
11641 | return false; |
Line 10276... | Line 11663... | ||
10276 | return "Invalid"; |
11663 | return "Invalid"; |
Line 10277... | Line 11664... | ||
10277 | 11664 | ||
10278 | return names[output]; |
11665 | return names[output]; |
Line -... | Line 11666... | ||
- | 11666 | } |
|
- | 11667 | ||
- | 11668 | static bool intel_crt_present(struct drm_device *dev) |
|
- | 11669 | { |
|
- | 11670 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 11671 | ||
- | 11672 | if (IS_ULT(dev)) |
|
- | 11673 | return false; |
|
- | 11674 | ||
- | 11675 | if (IS_CHERRYVIEW(dev)) |
|
- | 11676 | return false; |
|
- | 11677 | ||
- | 11678 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) |
|
- | 11679 | return false; |
|
- | 11680 | ||
- | 11681 | return true; |
|
10279 | } |
11682 | } |
10280 | 11683 | ||
10281 | static void intel_setup_outputs(struct drm_device *dev) |
11684 | static void intel_setup_outputs(struct drm_device *dev) |
10282 | { |
11685 | { |
10283 | struct drm_i915_private *dev_priv = dev->dev_private; |
11686 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10284... | Line 11687... | ||
10284 | struct intel_encoder *encoder; |
11687 | struct intel_encoder *encoder; |
Line 10285... | Line 11688... | ||
10285 | bool dpd_is_edp = false; |
11688 | bool dpd_is_edp = false; |
10286 | 11689 | ||
Line 10287... | Line 11690... | ||
10287 | intel_lvds_init(dev); |
11690 | intel_lvds_init(dev); |
10288 | 11691 | ||
Line 10348... | Line 11751... | ||
10348 | PORT_C); |
11751 | PORT_C); |
10349 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
11752 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
10350 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
11753 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
10351 | } |
11754 | } |
Line -... | Line 11755... | ||
- | 11755 | ||
- | 11756 | if (IS_CHERRYVIEW(dev)) { |
|
- | 11757 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { |
|
- | 11758 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
|
- | 11759 | PORT_D); |
|
- | 11760 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) |
|
- | 11761 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); |
|
- | 11762 | } |
|
- | 11763 | } |
|
10352 | 11764 | ||
10353 | intel_dsi_init(dev); |
11765 | intel_dsi_init(dev); |
10354 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
11766 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Line 10355... | Line 11767... | ||
10355 | bool found = false; |
11767 | bool found = false; |
Line 10387... | Line 11799... | ||
10387 | (I915_READ(DP_D) & DP_DETECTED)) |
11799 | (I915_READ(DP_D) & DP_DETECTED)) |
10388 | intel_dp_init(dev, DP_D, PORT_D); |
11800 | intel_dp_init(dev, DP_D, PORT_D); |
10389 | } else if (IS_GEN2(dev)) |
11801 | } else if (IS_GEN2(dev)) |
10390 | intel_dvo_init(dev); |
11802 | intel_dvo_init(dev); |
Line 10391... | Line -... | ||
10391 | - | ||
- | 11803 | ||
10392 | // if (SUPPORTS_TV(dev)) |
11804 | |
Line 10393... | Line 11805... | ||
10393 | // intel_tv_init(dev); |
11805 | intel_edp_psr_init(dev); |
10394 | 11806 | ||
10395 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11807 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10396 | encoder->base.possible_crtcs = encoder->crtc_mask; |
11808 | encoder->base.possible_crtcs = encoder->crtc_mask; |
Line 10408... | Line 11820... | ||
10408 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
11820 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
10409 | // .destroy = intel_user_framebuffer_destroy, |
11821 | // .destroy = intel_user_framebuffer_destroy, |
10410 | // .create_handle = intel_user_framebuffer_create_handle, |
11822 | // .create_handle = intel_user_framebuffer_create_handle, |
10411 | }; |
11823 | }; |
Line 10412... | Line 11824... | ||
10412 | 11824 | ||
10413 | int intel_framebuffer_init(struct drm_device *dev, |
11825 | static int intel_framebuffer_init(struct drm_device *dev, |
10414 | struct intel_framebuffer *intel_fb, |
11826 | struct intel_framebuffer *intel_fb, |
10415 | struct drm_mode_fb_cmd2 *mode_cmd, |
11827 | struct drm_mode_fb_cmd2 *mode_cmd, |
10416 | struct drm_i915_gem_object *obj) |
11828 | struct drm_i915_gem_object *obj) |
10417 | { |
11829 | { |
10418 | int aligned_height, tile_height; |
11830 | int aligned_height; |
10419 | int pitch_limit; |
11831 | int pitch_limit; |
Line 10420... | Line 11832... | ||
10420 | int ret; |
11832 | int ret; |
Line 10507... | Line 11919... | ||
10507 | 11919 | ||
10508 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11920 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10509 | if (mode_cmd->offsets[0] != 0) |
11921 | if (mode_cmd->offsets[0] != 0) |
Line 10510... | Line -... | ||
10510 | return -EINVAL; |
- | |
10511 | 11922 | return -EINVAL; |
|
10512 | tile_height = IS_GEN2(dev) ? 16 : 8; |
11923 | |
10513 | aligned_height = ALIGN(mode_cmd->height, |
11924 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10514 | obj->tiling_mode ? tile_height : 1); |
11925 | obj->tiling_mode); |
10515 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11926 | /* FIXME drm helper for size checks (especially planar formats)? */ |
Line 10516... | Line 11927... | ||
10516 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
11927 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
Line 10545... | Line 11956... | ||
10545 | { |
11956 | { |
10546 | struct drm_i915_private *dev_priv = dev->dev_private; |
11957 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10547... | Line 11958... | ||
10547 | 11958 | ||
10548 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11959 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
- | 11960 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
|
- | 11961 | else if (IS_CHERRYVIEW(dev)) |
|
10549 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
11962 | dev_priv->display.find_dpll = chv_find_best_dpll; |
10550 | else if (IS_VALLEYVIEW(dev)) |
11963 | else if (IS_VALLEYVIEW(dev)) |
10551 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
11964 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
10552 | else if (IS_PINEVIEW(dev)) |
11965 | else if (IS_PINEVIEW(dev)) |
10553 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
11966 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
10554 | else |
11967 | else |
Line 10555... | Line 11968... | ||
10555 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
11968 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
10556 | 11969 | ||
- | 11970 | if (HAS_DDI(dev)) { |
|
10557 | if (HAS_DDI(dev)) { |
11971 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
10558 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
11972 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
10559 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
11973 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
10560 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11974 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10561 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
11975 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
- | 11976 | dev_priv->display.off = ironlake_crtc_off; |
|
10562 | dev_priv->display.off = haswell_crtc_off; |
11977 | dev_priv->display.update_primary_plane = |
10563 | dev_priv->display.update_plane = ironlake_update_plane; |
11978 | ironlake_update_primary_plane; |
- | 11979 | } else if (HAS_PCH_SPLIT(dev)) { |
|
10564 | } else if (HAS_PCH_SPLIT(dev)) { |
11980 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
10565 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
11981 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
10566 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
11982 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
10567 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11983 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10568 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
11984 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
- | 11985 | dev_priv->display.off = ironlake_crtc_off; |
|
10569 | dev_priv->display.off = ironlake_crtc_off; |
11986 | dev_priv->display.update_primary_plane = |
10570 | dev_priv->display.update_plane = ironlake_update_plane; |
11987 | ironlake_update_primary_plane; |
- | 11988 | } else if (IS_VALLEYVIEW(dev)) { |
|
10571 | } else if (IS_VALLEYVIEW(dev)) { |
11989 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
10572 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11990 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
10573 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11991 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10574 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
11992 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
10575 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
11993 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
- | 11994 | dev_priv->display.off = i9xx_crtc_off; |
|
10576 | dev_priv->display.off = i9xx_crtc_off; |
11995 | dev_priv->display.update_primary_plane = |
10577 | dev_priv->display.update_plane = i9xx_update_plane; |
11996 | i9xx_update_primary_plane; |
- | 11997 | } else { |
|
10578 | } else { |
11998 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
10579 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11999 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
10580 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12000 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10581 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12001 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10582 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
12002 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
- | 12003 | dev_priv->display.off = i9xx_crtc_off; |
|
10583 | dev_priv->display.off = i9xx_crtc_off; |
12004 | dev_priv->display.update_primary_plane = |
Line 10584... | Line 12005... | ||
10584 | dev_priv->display.update_plane = i9xx_update_plane; |
12005 | i9xx_update_primary_plane; |
10585 | } |
12006 | } |
10586 | 12007 | ||
Line 10618... | Line 12039... | ||
10618 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
12039 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
10619 | dev_priv->display.write_eld = ironlake_write_eld; |
12040 | dev_priv->display.write_eld = ironlake_write_eld; |
10620 | } else if (IS_GEN6(dev)) { |
12041 | } else if (IS_GEN6(dev)) { |
10621 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
12042 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
10622 | dev_priv->display.write_eld = ironlake_write_eld; |
12043 | dev_priv->display.write_eld = ironlake_write_eld; |
- | 12044 | dev_priv->display.modeset_global_resources = |
|
- | 12045 | snb_modeset_global_resources; |
|
10623 | } else if (IS_IVYBRIDGE(dev)) { |
12046 | } else if (IS_IVYBRIDGE(dev)) { |
10624 | /* FIXME: detect B0+ stepping and use auto training */ |
12047 | /* FIXME: detect B0+ stepping and use auto training */ |
10625 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
12048 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
10626 | dev_priv->display.write_eld = ironlake_write_eld; |
12049 | dev_priv->display.write_eld = ironlake_write_eld; |
10627 | dev_priv->display.modeset_global_resources = |
12050 | dev_priv->display.modeset_global_resources = |
Line 10681... | Line 12104... | ||
10681 | struct drm_i915_private *dev_priv = dev->dev_private; |
12104 | struct drm_i915_private *dev_priv = dev->dev_private; |
10682 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
12105 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
10683 | DRM_INFO("applying inverted panel brightness quirk\n"); |
12106 | DRM_INFO("applying inverted panel brightness quirk\n"); |
10684 | } |
12107 | } |
Line -... | Line 12108... | ||
- | 12108 | ||
- | 12109 | /* Some VBT's incorrectly indicate no backlight is present */ |
|
- | 12110 | static void quirk_backlight_present(struct drm_device *dev) |
|
- | 12111 | { |
|
- | 12112 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 12113 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
|
- | 12114 | DRM_INFO("applying backlight present quirk\n"); |
|
- | 12115 | } |
|
10685 | 12116 | ||
10686 | struct intel_quirk { |
12117 | struct intel_quirk { |
10687 | int device; |
12118 | int device; |
10688 | int subsystem_vendor; |
12119 | int subsystem_vendor; |
10689 | int subsystem_device; |
12120 | int subsystem_device; |
Line 10726... | Line 12157... | ||
10726 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
12157 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
Line 10727... | Line 12158... | ||
10727 | 12158 | ||
10728 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12159 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
Line 10729... | Line -... | ||
10729 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
- | |
10730 | - | ||
10731 | /* 830 needs to leave pipe A & dpll A up */ |
- | |
10732 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
12160 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
10733 | 12161 | ||
Line 10734... | Line 12162... | ||
10734 | /* Lenovo U160 cannot use SSC on LVDS */ |
12162 | /* Lenovo U160 cannot use SSC on LVDS */ |
10735 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
12163 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Line 10749... | Line 12177... | ||
10749 | /* Acer/Packard Bell NCL20 */ |
12177 | /* Acer/Packard Bell NCL20 */ |
10750 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
12178 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
Line 10751... | Line 12179... | ||
10751 | 12179 | ||
10752 | /* Acer Aspire 4736Z */ |
12180 | /* Acer Aspire 4736Z */ |
- | 12181 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
|
- | 12182 | ||
- | 12183 | /* Acer Aspire 5336 */ |
|
- | 12184 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
|
- | 12185 | ||
- | 12186 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
|
- | 12187 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
|
- | 12188 | ||
- | 12189 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
|
- | 12190 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
|
- | 12191 | ||
- | 12192 | /* HP Chromebook 14 (Celeron 2955U) */ |
|
10753 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
12193 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
Line 10754... | Line 12194... | ||
10754 | }; |
12194 | }; |
10755 | 12195 | ||
10756 | static void intel_init_quirks(struct drm_device *dev) |
12196 | static void intel_init_quirks(struct drm_device *dev) |
Line 10790... | Line 12230... | ||
10790 | 12230 | ||
10791 | void intel_modeset_init_hw(struct drm_device *dev) |
12231 | void intel_modeset_init_hw(struct drm_device *dev) |
10792 | { |
12232 | { |
Line -... | Line 12233... | ||
- | 12233 | intel_prepare_ddi(dev); |
|
- | 12234 | ||
- | 12235 | if (IS_VALLEYVIEW(dev)) |
|
10793 | intel_prepare_ddi(dev); |
12236 | vlv_update_cdclk(dev); |
Line 10794... | Line 12237... | ||
10794 | 12237 | ||
Line 10795... | Line -... | ||
10795 | intel_init_clock_gating(dev); |
- | |
10796 | 12238 | intel_init_clock_gating(dev); |
|
10797 | intel_reset_dpio(dev); |
- | |
10798 | 12239 | ||
Line 10799... | Line 12240... | ||
10799 | mutex_lock(&dev->struct_mutex); |
12240 | intel_reset_dpio(dev); |
10800 | intel_enable_gt_powersave(dev); |
12241 | |
10801 | mutex_unlock(&dev->struct_mutex); |
12242 | intel_enable_gt_powersave(dev); |
10802 | } |
12243 | } |
Line 10803... | Line 12244... | ||
10803 | 12244 | ||
10804 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12245 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10805 | { |
12246 | { |
10806 | intel_suspend_hw(dev); |
12247 | intel_suspend_hw(dev); |
- | 12248 | } |
|
- | 12249 | ||
Line 10807... | Line 12250... | ||
10807 | } |
12250 | void intel_modeset_init(struct drm_device *dev) |
Line 10808... | Line 12251... | ||
10808 | 12251 | { |
|
10809 | void intel_modeset_init(struct drm_device *dev) |
12252 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10838... | Line 12281... | ||
10838 | dev->mode_config.max_height = 4096; |
12281 | dev->mode_config.max_height = 4096; |
10839 | } else { |
12282 | } else { |
10840 | dev->mode_config.max_width = 8192; |
12283 | dev->mode_config.max_width = 8192; |
10841 | dev->mode_config.max_height = 8192; |
12284 | dev->mode_config.max_height = 8192; |
10842 | } |
12285 | } |
- | 12286 | ||
- | 12287 | if (IS_GEN2(dev)) { |
|
- | 12288 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
|
- | 12289 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
|
- | 12290 | } else { |
|
- | 12291 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
|
- | 12292 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
|
- | 12293 | } |
|
- | 12294 | ||
10843 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
12295 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
Line 10844... | Line 12296... | ||
10844 | 12296 | ||
10845 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
12297 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10846 | INTEL_INFO(dev)->num_pipes, |
12298 | INTEL_INFO(dev)->num_pipes, |
Line 10847... | Line 12299... | ||
10847 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
12299 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10848 | 12300 | ||
10849 | for_each_pipe(i) { |
12301 | for_each_pipe(pipe) { |
10850 | intel_crtc_init(dev, i); |
12302 | intel_crtc_init(dev, pipe); |
10851 | for (j = 0; j < dev_priv->num_plane; j++) { |
12303 | for_each_sprite(pipe, sprite) { |
10852 | ret = intel_plane_init(dev, i, j); |
12304 | ret = intel_plane_init(dev, pipe, sprite); |
10853 | if (ret) |
12305 | if (ret) |
10854 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
12306 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10855 | pipe_name(i), sprite_name(i, j), ret); |
12307 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
Line 10856... | Line 12308... | ||
10856 | } |
12308 | } |
10857 | } |
12309 | } |
Line 10858... | Line -... | ||
10858 | - | ||
10859 | intel_init_dpio(dev); |
12310 | |
Line 10860... | Line 12311... | ||
10860 | intel_reset_dpio(dev); |
12311 | intel_init_dpio(dev); |
10861 | 12312 | intel_reset_dpio(dev); |
|
10862 | intel_cpu_pll_init(dev); |
12313 | |
Line 10863... | Line 12314... | ||
10863 | intel_shared_dpll_init(dev); |
12314 | intel_shared_dpll_init(dev); |
10864 | 12315 | ||
10865 | /* Just disable it once at startup */ |
- | |
Line 10866... | Line 12316... | ||
10866 | i915_disable_vga(dev); |
12316 | /* Just disable it once at startup */ |
10867 | intel_setup_outputs(dev); |
12317 | i915_disable_vga(dev); |
- | 12318 | intel_setup_outputs(dev); |
|
- | 12319 | ||
- | 12320 | /* Just in case the BIOS is doing something questionable. */ |
|
- | 12321 | intel_disable_fbc(dev); |
|
- | 12322 | ||
10868 | 12323 | drm_modeset_lock_all(dev); |
|
- | 12324 | intel_modeset_setup_hw_state(dev, false); |
|
- | 12325 | drm_modeset_unlock_all(dev); |
|
- | 12326 | ||
- | 12327 | for_each_intel_crtc(dev, crtc) { |
|
- | 12328 | if (!crtc->active) |
|
- | 12329 | continue; |
|
- | 12330 | ||
10869 | /* Just in case the BIOS is doing something questionable. */ |
12331 | /* |
10870 | intel_disable_fbc(dev); |
12332 | * Note that reserving the BIOS fb up front prevents us |
- | 12333 | * from stuffing other stolen allocations like the ring |
|
- | 12334 | * on top. This prevents some ugliness at boot time, and |
|
10871 | } |
12335 | * can even allow for smooth boot transitions if the BIOS |
- | 12336 | * fb is large enough for the active pipe configuration. |
|
- | 12337 | */ |
|
10872 | 12338 | if (dev_priv->display.get_plane_config) { |
|
- | 12339 | dev_priv->display.get_plane_config(crtc, |
|
- | 12340 | &crtc->plane_config); |
|
10873 | static void |
12341 | /* |
Line 10874... | Line 12342... | ||
10874 | intel_connector_break_all_links(struct intel_connector *connector) |
12342 | * If the fb is shared between multiple heads, we'll |
10875 | { |
12343 | * just get the first one. |
10876 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12344 | */ |
10877 | connector->base.encoder = NULL; |
12345 | intel_find_plane_obj(crtc, &crtc->plane_config); |
10878 | connector->encoder->connectors_active = false; |
12346 | } |
- | 12347 | } |
|
Line 10879... | Line 12348... | ||
10879 | connector->encoder->base.crtc = NULL; |
12348 | } |
10880 | } |
12349 | |
10881 | 12350 | static void intel_enable_pipe_a(struct drm_device *dev) |
|
10882 | static void intel_enable_pipe_a(struct drm_device *dev) |
12351 | { |
Line 10898... | Line 12367... | ||
10898 | } |
12367 | } |
Line 10899... | Line 12368... | ||
10899 | 12368 | ||
10900 | if (!crt) |
12369 | if (!crt) |
Line 10901... | Line 12370... | ||
10901 | return; |
12370 | return; |
10902 | 12371 | ||
10903 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
- | |
10904 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
- | |
10905 | 12372 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
|
Line 10906... | Line 12373... | ||
10906 | 12373 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
|
10907 | } |
12374 | } |
10908 | 12375 | ||
Line 10934... | Line 12401... | ||
10934 | 12401 | ||
10935 | /* Clear any frame start delays used for debugging left by the BIOS */ |
12402 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10936 | reg = PIPECONF(crtc->config.cpu_transcoder); |
12403 | reg = PIPECONF(crtc->config.cpu_transcoder); |
Line -... | Line 12404... | ||
- | 12404 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
|
- | 12405 | ||
- | 12406 | /* restore vblank interrupts to correct state */ |
|
- | 12407 | if (crtc->active) |
|
- | 12408 | drm_vblank_on(dev, crtc->pipe); |
|
- | 12409 | else |
|
10937 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12410 | drm_vblank_off(dev, crtc->pipe); |
10938 | 12411 | ||
10939 | /* We need to sanitize the plane -> pipe mapping first because this will |
12412 | /* We need to sanitize the plane -> pipe mapping first because this will |
10940 | * disable the crtc (and hence change the state) if it is wrong. Note |
12413 | * disable the crtc (and hence change the state) if it is wrong. Note |
10941 | * that gen4+ has a fixed plane -> pipe mapping. */ |
12414 | * that gen4+ has a fixed plane -> pipe mapping. */ |
Line 10949... | Line 12422... | ||
10949 | /* Pipe has the wrong plane attached and the plane is active. |
12422 | /* Pipe has the wrong plane attached and the plane is active. |
10950 | * Temporarily change the plane mapping and disable everything |
12423 | * Temporarily change the plane mapping and disable everything |
10951 | * ... */ |
12424 | * ... */ |
10952 | plane = crtc->plane; |
12425 | plane = crtc->plane; |
10953 | crtc->plane = !plane; |
12426 | crtc->plane = !plane; |
- | 12427 | crtc->primary_enabled = true; |
|
10954 | dev_priv->display.crtc_disable(&crtc->base); |
12428 | dev_priv->display.crtc_disable(&crtc->base); |
10955 | crtc->plane = plane; |
12429 | crtc->plane = plane; |
Line 10956... | Line 12430... | ||
10956 | 12430 | ||
10957 | /* ... and break all links. */ |
12431 | /* ... and break all links. */ |
10958 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
12432 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10959 | base.head) { |
12433 | base.head) { |
10960 | if (connector->encoder->base.crtc != &crtc->base) |
12434 | if (connector->encoder->base.crtc != &crtc->base) |
Line -... | Line 12435... | ||
- | 12435 | continue; |
|
- | 12436 | ||
- | 12437 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
|
- | 12438 | connector->base.encoder = NULL; |
|
- | 12439 | } |
|
10961 | continue; |
12440 | /* multiple connectors may have the same encoder: |
- | 12441 | * handle them and break crtc link separately */ |
|
- | 12442 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
|
- | 12443 | base.head) |
|
- | 12444 | if (connector->encoder->base.crtc == &crtc->base) { |
|
10962 | 12445 | connector->encoder->base.crtc = NULL; |
|
Line 10963... | Line 12446... | ||
10963 | intel_connector_break_all_links(connector); |
12446 | connector->encoder->connectors_active = false; |
10964 | } |
12447 | } |
10965 | 12448 | ||
Line 11003... | Line 12486... | ||
11003 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
12486 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
11004 | WARN_ON(encoder->connectors_active); |
12487 | WARN_ON(encoder->connectors_active); |
11005 | encoder->base.crtc = NULL; |
12488 | encoder->base.crtc = NULL; |
11006 | } |
12489 | } |
11007 | } |
12490 | } |
- | 12491 | ||
- | 12492 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { |
|
- | 12493 | /* |
|
- | 12494 | * We start out with underrun reporting disabled to avoid races. |
|
- | 12495 | * For correct bookkeeping mark this on active crtcs. |
|
- | 12496 | * |
|
- | 12497 | * Also on gmch platforms we dont have any hardware bits to |
|
- | 12498 | * disable the underrun reporting. Which means we need to start |
|
- | 12499 | * out with underrun reporting disabled also on inactive pipes, |
|
- | 12500 | * since otherwise we'll complain about the garbage we read when |
|
- | 12501 | * e.g. coming up after runtime pm. |
|
- | 12502 | * |
|
- | 12503 | * No protection against concurrent access is required - at |
|
- | 12504 | * worst a fifo underrun happens which also sets this to false. |
|
- | 12505 | */ |
|
- | 12506 | crtc->cpu_fifo_underrun_disabled = true; |
|
- | 12507 | crtc->pch_fifo_underrun_disabled = true; |
|
- | 12508 | ||
- | 12509 | update_scanline_offset(crtc); |
|
- | 12510 | } |
|
11008 | } |
12511 | } |
Line 11009... | Line 12512... | ||
11009 | 12512 | ||
11010 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
12513 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
11011 | { |
12514 | { |
Line 11019... | Line 12522... | ||
11019 | to_intel_crtc(encoder->base.crtc)->active; |
12522 | to_intel_crtc(encoder->base.crtc)->active; |
Line 11020... | Line 12523... | ||
11020 | 12523 | ||
11021 | if (encoder->connectors_active && !has_active_crtc) { |
12524 | if (encoder->connectors_active && !has_active_crtc) { |
11022 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
12525 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
11023 | encoder->base.base.id, |
12526 | encoder->base.base.id, |
Line 11024... | Line 12527... | ||
11024 | drm_get_encoder_name(&encoder->base)); |
12527 | encoder->base.name); |
11025 | 12528 | ||
11026 | /* Connector is active, but has no active pipe. This is |
12529 | /* Connector is active, but has no active pipe. This is |
11027 | * fallout from our resume register restoring. Disable |
12530 | * fallout from our resume register restoring. Disable |
11028 | * the encoder manually again. */ |
12531 | * the encoder manually again. */ |
11029 | if (encoder->base.crtc) { |
12532 | if (encoder->base.crtc) { |
11030 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
12533 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
11031 | encoder->base.base.id, |
12534 | encoder->base.base.id, |
- | 12535 | encoder->base.name); |
|
- | 12536 | encoder->disable(encoder); |
|
11032 | drm_get_encoder_name(&encoder->base)); |
12537 | if (encoder->post_disable) |
- | 12538 | encoder->post_disable(encoder); |
|
- | 12539 | } |
|
Line 11033... | Line 12540... | ||
11033 | encoder->disable(encoder); |
12540 | encoder->base.crtc = NULL; |
11034 | } |
12541 | encoder->connectors_active = false; |
11035 | 12542 | ||
11036 | /* Inconsistent output/port/pipe state happens presumably due to |
12543 | /* Inconsistent output/port/pipe state happens presumably due to |
11037 | * a bug in one of the get_hw_state functions. Or someplace else |
12544 | * a bug in one of the get_hw_state functions. Or someplace else |
11038 | * in our code, like the register restore mess on resume. Clamp |
12545 | * in our code, like the register restore mess on resume. Clamp |
11039 | * things to off as a safer default. */ |
12546 | * things to off as a safer default. */ |
11040 | list_for_each_entry(connector, |
12547 | list_for_each_entry(connector, |
11041 | &dev->mode_config.connector_list, |
12548 | &dev->mode_config.connector_list, |
11042 | base.head) { |
- | |
- | 12549 | base.head) { |
|
11043 | if (connector->encoder != encoder) |
12550 | if (connector->encoder != encoder) |
11044 | continue; |
12551 | continue; |
11045 | 12552 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
|
11046 | intel_connector_break_all_links(connector); |
12553 | connector->base.encoder = NULL; |
11047 | } |
12554 | } |
11048 | } |
12555 | } |
Line 11049... | Line 12556... | ||
11049 | /* Enabled encoders without active connectors will be fixed in |
12556 | /* Enabled encoders without active connectors will be fixed in |
11050 | * the crtc fixup. */ |
12557 | * the crtc fixup. */ |
11051 | } |
12558 | } |
11052 | 12559 | ||
Line -... | Line 12560... | ||
- | 12560 | void i915_redisable_vga_power_on(struct drm_device *dev) |
|
- | 12561 | { |
|
- | 12562 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 12563 | u32 vga_reg = i915_vgacntrl_reg(dev); |
|
- | 12564 | ||
- | 12565 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
|
- | 12566 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
|
- | 12567 | i915_disable_vga(dev); |
|
- | 12568 | } |
|
- | 12569 | } |
|
11053 | void i915_redisable_vga(struct drm_device *dev) |
12570 | |
11054 | { |
12571 | void i915_redisable_vga(struct drm_device *dev) |
11055 | struct drm_i915_private *dev_priv = dev->dev_private; |
12572 | { |
11056 | u32 vga_reg = i915_vgacntrl_reg(dev); |
12573 | struct drm_i915_private *dev_priv = dev->dev_private; |
11057 | 12574 | ||
11058 | /* This function can be called both from intel_modeset_setup_hw_state or |
12575 | /* This function can be called both from intel_modeset_setup_hw_state or |
11059 | * at a very early point in our resume sequence, where the power well |
12576 | * at a very early point in our resume sequence, where the power well |
11060 | * structures are not yet restored. Since this function is at a very |
- | |
11061 | * paranoid "someone might have enabled VGA while we were not looking" |
12577 | * structures are not yet restored. Since this function is at a very |
11062 | * level, just check if the power well is enabled instead of trying to |
12578 | * paranoid "someone might have enabled VGA while we were not looking" |
Line 11063... | Line -... | ||
11063 | * follow the "don't touch the power well if we don't need it" policy |
- | |
11064 | * the rest of the driver uses. */ |
- | |
11065 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
12579 | * level, just check if the power well is enabled instead of trying to |
11066 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
12580 | * follow the "don't touch the power well if we don't need it" policy |
- | 12581 | * the rest of the driver uses. */ |
|
- | 12582 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
|
- | 12583 | return; |
|
- | 12584 | ||
- | 12585 | i915_redisable_vga_power_on(dev); |
|
- | 12586 | } |
|
- | 12587 | ||
- | 12588 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
|
- | 12589 | { |
|
11067 | return; |
12590 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
Line 11068... | Line 12591... | ||
11068 | 12591 | ||
11069 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12592 | if (!crtc->active) |
11070 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
12593 | return false; |
Line 11079... | Line 12602... | ||
11079 | struct intel_crtc *crtc; |
12602 | struct intel_crtc *crtc; |
11080 | struct intel_encoder *encoder; |
12603 | struct intel_encoder *encoder; |
11081 | struct intel_connector *connector; |
12604 | struct intel_connector *connector; |
11082 | int i; |
12605 | int i; |
Line 11083... | Line 12606... | ||
11083 | 12606 | ||
11084 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
11085 | base.head) { |
12607 | for_each_intel_crtc(dev, crtc) { |
Line -... | Line 12608... | ||
- | 12608 | memset(&crtc->config, 0, sizeof(crtc->config)); |
|
- | 12609 | ||
11086 | memset(&crtc->config, 0, sizeof(crtc->config)); |
12610 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
11087 | 12611 | ||
Line 11088... | Line 12612... | ||
11088 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12612 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11089 | &crtc->config); |
12613 | &crtc->config); |
Line 11090... | Line 12614... | ||
11090 | 12614 | ||
11091 | crtc->base.enabled = crtc->active; |
12615 | crtc->base.enabled = crtc->active; |
11092 | crtc->primary_enabled = crtc->active; |
12616 | crtc->primary_enabled = primary_get_hw_state(crtc); |
11093 | 12617 | ||
Line 11094... | Line -... | ||
11094 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
- | |
11095 | crtc->base.base.id, |
- | |
11096 | crtc->active ? "enabled" : "disabled"); |
- | |
11097 | } |
- | |
11098 | 12618 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
|
11099 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
12619 | crtc->base.base.id, |
Line 11100... | Line 12620... | ||
11100 | if (HAS_DDI(dev)) |
12620 | crtc->active ? "enabled" : "disabled"); |
11101 | intel_ddi_setup_hw_pll_state(dev); |
12621 | } |
11102 | 12622 | ||
11103 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
- | |
11104 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
12623 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11105 | 12624 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
|
11106 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
12625 | |
11107 | pll->active = 0; |
12626 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
Line 11108... | Line 12627... | ||
11108 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
12627 | pll->active = 0; |
11109 | base.head) { |
12628 | for_each_intel_crtc(dev, crtc) { |
- | 12629 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
|
- | 12630 | pll->active++; |
|
- | 12631 | } |
|
11110 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12632 | pll->refcount = pll->active; |
Line 11111... | Line 12633... | ||
11111 | pll->active++; |
12633 | |
11112 | } |
12634 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11113 | pll->refcount = pll->active; |
12635 | pll->name, pll->refcount, pll->on); |
Line 11129... | Line 12651... | ||
11129 | } |
12651 | } |
Line 11130... | Line 12652... | ||
11130 | 12652 | ||
11131 | encoder->connectors_active = false; |
12653 | encoder->connectors_active = false; |
11132 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
12654 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
11133 | encoder->base.base.id, |
12655 | encoder->base.base.id, |
11134 | drm_get_encoder_name(&encoder->base), |
12656 | encoder->base.name, |
11135 | encoder->base.crtc ? "enabled" : "disabled", |
12657 | encoder->base.crtc ? "enabled" : "disabled", |
11136 | pipe_name(pipe)); |
12658 | pipe_name(pipe)); |
Line 11137... | Line 12659... | ||
11137 | } |
12659 | } |
Line 11146... | Line 12668... | ||
11146 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12668 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11147 | connector->base.encoder = NULL; |
12669 | connector->base.encoder = NULL; |
11148 | } |
12670 | } |
11149 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
12671 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
11150 | connector->base.base.id, |
12672 | connector->base.base.id, |
11151 | drm_get_connector_name(&connector->base), |
12673 | connector->base.name, |
11152 | connector->base.encoder ? "enabled" : "disabled"); |
12674 | connector->base.encoder ? "enabled" : "disabled"); |
11153 | } |
12675 | } |
11154 | } |
12676 | } |
Line 11155... | Line 12677... | ||
11155 | 12677 | ||
Line 11169... | Line 12691... | ||
11169 | /* |
12691 | /* |
11170 | * Now that we have the config, copy it to each CRTC struct |
12692 | * Now that we have the config, copy it to each CRTC struct |
11171 | * Note that this could go away if we move to using crtc_config |
12693 | * Note that this could go away if we move to using crtc_config |
11172 | * checking everywhere. |
12694 | * checking everywhere. |
11173 | */ |
12695 | */ |
11174 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
12696 | for_each_intel_crtc(dev, crtc) { |
11175 | base.head) { |
- | |
11176 | if (crtc->active && i915_fastboot) { |
12697 | if (crtc->active && i915.fastboot) { |
11177 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
12698 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
11178 | - | ||
11179 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12699 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
11180 | crtc->base.base.id); |
12700 | crtc->base.base.id); |
11181 | drm_mode_debug_printmodeline(&crtc->base.mode); |
12701 | drm_mode_debug_printmodeline(&crtc->base.mode); |
11182 | } |
12702 | } |
11183 | } |
12703 | } |
Line 11219... | Line 12739... | ||
11219 | for_each_pipe(pipe) { |
12739 | for_each_pipe(pipe) { |
11220 | struct drm_crtc *crtc = |
12740 | struct drm_crtc *crtc = |
11221 | dev_priv->pipe_to_crtc_mapping[pipe]; |
12741 | dev_priv->pipe_to_crtc_mapping[pipe]; |
Line 11222... | Line 12742... | ||
11222 | 12742 | ||
11223 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
12743 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
11224 | crtc->fb); |
12744 | crtc->primary->fb); |
11225 | } |
12745 | } |
11226 | } else { |
12746 | } else { |
11227 | intel_modeset_update_staged_output_state(dev); |
12747 | intel_modeset_update_staged_output_state(dev); |
Line 11228... | Line 12748... | ||
11228 | } |
12748 | } |
11229 | 12749 | ||
Line 11230... | Line 12750... | ||
11230 | intel_modeset_check_state(dev); |
12750 | intel_modeset_check_state(dev); |
11231 | } |
12751 | } |
- | 12752 | ||
- | 12753 | void intel_modeset_gem_init(struct drm_device *dev) |
|
- | 12754 | { |
|
- | 12755 | struct drm_crtc *c; |
|
- | 12756 | struct drm_i915_gem_object *obj; |
|
- | 12757 | ||
- | 12758 | mutex_lock(&dev->struct_mutex); |
|
11232 | 12759 | intel_init_gt_powersave(dev); |
|
Line 11233... | Line 12760... | ||
11233 | void intel_modeset_gem_init(struct drm_device *dev) |
12760 | mutex_unlock(&dev->struct_mutex); |
Line -... | Line 12761... | ||
- | 12761 | ||
- | 12762 | intel_modeset_init_hw(dev); |
|
- | 12763 | ||
- | 12764 | // intel_setup_overlay(dev); |
|
- | 12765 | ||
11234 | { |
12766 | /* |
11235 | intel_modeset_init_hw(dev); |
12767 | * Make sure any fbs we allocated at startup are properly |
- | 12768 | * pinned & fenced. When we do the allocation it's too early |
|
- | 12769 | * for this. |
|
- | 12770 | */ |
|
- | 12771 | mutex_lock(&dev->struct_mutex); |
|
11236 | 12772 | for_each_crtc(dev, c) { |
|
- | 12773 | obj = intel_fb_obj(c->primary->fb); |
|
- | 12774 | if (obj == NULL) |
|
- | 12775 | continue; |
|
- | 12776 | ||
- | 12777 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
|
- | 12778 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
|
11237 | // intel_setup_overlay(dev); |
12779 | to_intel_crtc(c)->pipe); |
- | 12780 | drm_framebuffer_unreference(c->primary->fb); |
|
- | 12781 | c->primary->fb = NULL; |
|
- | 12782 | } |
|
- | 12783 | } |
|
- | 12784 | mutex_unlock(&dev->struct_mutex); |
|
- | 12785 | } |
|
- | 12786 | ||
- | 12787 | void intel_connector_unregister(struct intel_connector *intel_connector) |
|
11238 | 12788 | { |
|
Line 11239... | Line 12789... | ||
11239 | mutex_lock(&dev->mode_config.mutex); |
12789 | struct drm_connector *connector = &intel_connector->base; |
11240 | drm_mode_config_reset(dev); |
12790 | |
11241 | intel_modeset_setup_hw_state(dev, false); |
12791 | intel_panel_destroy_backlight(connector); |
11242 | mutex_unlock(&dev->mode_config.mutex); |
12792 | drm_connector_unregister(connector); |
11243 | } |
- | |
11244 | 12793 | } |
|
Line 11245... | Line 12794... | ||
11245 | void intel_modeset_cleanup(struct drm_device *dev) |
12794 | |
11246 | { |
12795 | void intel_modeset_cleanup(struct drm_device *dev) |
11247 | #if 0 |
12796 | { |
11248 | struct drm_i915_private *dev_priv = dev->dev_private; |
12797 | #if 0 |
11249 | struct drm_crtc *crtc; |
12798 | struct drm_i915_private *dev_priv = dev->dev_private; |
11250 | struct drm_connector *connector; |
12799 | struct drm_connector *connector; |
11251 | 12800 | ||
- | 12801 | /* |
|
- | 12802 | * Interrupts and polling as the first thing to avoid creating havoc. |
|
11252 | /* |
12803 | * Too much stuff here (turning of rps, connectors, ...) would |
11253 | * Interrupts and polling as the first thing to avoid creating havoc. |
12804 | * experience fancy races otherwise. |
11254 | * Too much stuff here (turning of rps, connectors, ...) would |
12805 | */ |
11255 | * experience fancy races otherwise. |
12806 | drm_irq_uninstall(dev); |
11256 | */ |
12807 | intel_hpd_cancel_work(dev_priv); |
Line 11257... | Line 12808... | ||
11257 | drm_irq_uninstall(dev); |
12808 | dev_priv->pm._irqs_disabled = true; |
Line 11258... | Line 12809... | ||
11258 | cancel_work_sync(&dev_priv->hotplug_work); |
12809 | |
Line 11259... | Line -... | ||
11259 | /* |
- | |
11260 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
- | |
11261 | * poll handlers. Hence disable polling after hpd handling is shut down. |
- | |
11262 | */ |
- | |
11263 | drm_kms_helper_poll_fini(dev); |
- | |
11264 | - | ||
11265 | mutex_lock(&dev->struct_mutex); |
- | |
11266 | - | ||
11267 | intel_unregister_dsm_handler(); |
12810 | /* |
Line 11268... | Line 12811... | ||
11268 | 12811 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
|
Line 11269... | Line 12812... | ||
11269 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
12812 | * poll handlers. Hence disable polling after hpd handling is shut down. |
Line 11285... | Line 12828... | ||
11285 | /* flush any delayed tasks or pending work */ |
12828 | /* flush any delayed tasks or pending work */ |
11286 | flush_scheduled_work(); |
12829 | flush_scheduled_work(); |
Line 11287... | Line 12830... | ||
11287 | 12830 | ||
11288 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12831 | /* destroy the backlight and sysfs files before encoders/connectors */ |
- | 12832 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
- | 12833 | struct intel_connector *intel_connector; |
|
11289 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
12834 | |
11290 | intel_panel_destroy_backlight(connector); |
12835 | intel_connector = to_intel_connector(connector); |
11291 | drm_sysfs_connector_remove(connector); |
12836 | intel_connector->unregister(intel_connector); |
Line 11292... | Line 12837... | ||
11292 | } |
12837 | } |
- | 12838 | ||
- | 12839 | drm_mode_config_cleanup(dev); |
|
- | 12840 | ||
- | 12841 | intel_cleanup_overlay(dev); |
|
- | 12842 | ||
- | 12843 | mutex_lock(&dev->struct_mutex); |
|
11293 | 12844 | intel_cleanup_gt_powersave(dev); |
|
11294 | drm_mode_config_cleanup(dev); |
12845 | mutex_unlock(&dev->struct_mutex); |
Line 11295... | Line 12846... | ||
11295 | #endif |
12846 | #endif |
11296 | } |
12847 | } |
Line 11318... | Line 12869... | ||
11318 | { |
12869 | { |
11319 | struct drm_i915_private *dev_priv = dev->dev_private; |
12870 | struct drm_i915_private *dev_priv = dev->dev_private; |
11320 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
12871 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
11321 | u16 gmch_ctrl; |
12872 | u16 gmch_ctrl; |
Line 11322... | Line 12873... | ||
11322 | 12873 | ||
- | 12874 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
|
- | 12875 | DRM_ERROR("failed to read control word\n"); |
|
- | 12876 | return -EIO; |
|
- | 12877 | } |
|
- | 12878 | ||
- | 12879 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
|
- | 12880 | return 0; |
|
11323 | pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); |
12881 | |
11324 | if (state) |
12882 | if (state) |
11325 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
12883 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
11326 | else |
12884 | else |
- | 12885 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
|
11327 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
12886 | |
- | 12887 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
|
- | 12888 | DRM_ERROR("failed to write control word\n"); |
|
- | 12889 | return -EIO; |
|
- | 12890 | } |
|
11328 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
12891 | |
11329 | return 0; |
12892 | return 0; |
Line 11330... | Line 12893... | ||
11330 | } |
12893 | } |
Line 11345... | Line 12908... | ||
11345 | } cursor[I915_MAX_PIPES]; |
12908 | } cursor[I915_MAX_PIPES]; |
Line 11346... | Line 12909... | ||
11346 | 12909 | ||
11347 | struct intel_pipe_error_state { |
12910 | struct intel_pipe_error_state { |
11348 | bool power_domain_on; |
12911 | bool power_domain_on; |
- | 12912 | u32 source; |
|
11349 | u32 source; |
12913 | u32 stat; |
Line 11350... | Line 12914... | ||
11350 | } pipe[I915_MAX_PIPES]; |
12914 | } pipe[I915_MAX_PIPES]; |
11351 | 12915 | ||
11352 | struct intel_plane_error_state { |
12916 | struct intel_plane_error_state { |
Line 11375... | Line 12939... | ||
11375 | }; |
12939 | }; |
Line 11376... | Line 12940... | ||
11376 | 12940 | ||
11377 | struct intel_display_error_state * |
12941 | struct intel_display_error_state * |
11378 | intel_display_capture_error_state(struct drm_device *dev) |
12942 | intel_display_capture_error_state(struct drm_device *dev) |
11379 | { |
12943 | { |
11380 | drm_i915_private_t *dev_priv = dev->dev_private; |
12944 | struct drm_i915_private *dev_priv = dev->dev_private; |
11381 | struct intel_display_error_state *error; |
12945 | struct intel_display_error_state *error; |
11382 | int transcoders[] = { |
12946 | int transcoders[] = { |
11383 | TRANSCODER_A, |
12947 | TRANSCODER_A, |
11384 | TRANSCODER_B, |
12948 | TRANSCODER_B, |
Line 11397... | Line 12961... | ||
11397 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
12961 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
11398 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12962 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
Line 11399... | Line 12963... | ||
11399 | 12963 | ||
11400 | for_each_pipe(i) { |
12964 | for_each_pipe(i) { |
11401 | error->pipe[i].power_domain_on = |
12965 | error->pipe[i].power_domain_on = |
- | 12966 | intel_display_power_enabled_unlocked(dev_priv, |
|
11402 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); |
12967 | POWER_DOMAIN_PIPE(i)); |
11403 | if (!error->pipe[i].power_domain_on) |
12968 | if (!error->pipe[i].power_domain_on) |
Line 11404... | Line -... | ||
11404 | continue; |
- | |
11405 | 12969 | continue; |
|
11406 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
12970 | |
11407 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12971 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
11408 | error->cursor[i].position = I915_READ(CURPOS(i)); |
- | |
11409 | error->cursor[i].base = I915_READ(CURBASE(i)); |
- | |
11410 | } else { |
- | |
11411 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
- | |
11412 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
- | |
Line 11413... | Line 12972... | ||
11413 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
12972 | error->cursor[i].position = I915_READ(CURPOS(i)); |
11414 | } |
12973 | error->cursor[i].base = I915_READ(CURBASE(i)); |
11415 | 12974 | ||
11416 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
12975 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
Line 11425... | Line 12984... | ||
11425 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
12984 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
11426 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
12985 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
11427 | } |
12986 | } |
Line 11428... | Line 12987... | ||
11428 | 12987 | ||
- | 12988 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
|
- | 12989 | ||
- | 12990 | if (HAS_GMCH_DISPLAY(dev)) |
|
11429 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
12991 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
Line 11430... | Line 12992... | ||
11430 | } |
12992 | } |
11431 | 12993 | ||
11432 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
12994 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
Line 11433... | Line 12995... | ||
11433 | if (HAS_DDI(dev_priv->dev)) |
12995 | if (HAS_DDI(dev_priv->dev)) |
11434 | error->num_transcoders++; /* Account for eDP. */ |
12996 | error->num_transcoders++; /* Account for eDP. */ |
Line 11435... | Line 12997... | ||
11435 | 12997 | ||
11436 | for (i = 0; i < error->num_transcoders; i++) { |
12998 | for (i = 0; i < error->num_transcoders; i++) { |
11437 | enum transcoder cpu_transcoder = transcoders[i]; |
12999 | enum transcoder cpu_transcoder = transcoders[i]; |
11438 | 13000 | ||
11439 | error->transcoder[i].power_domain_on = |
13001 | error->transcoder[i].power_domain_on = |
Line 11440... | Line 13002... | ||
11440 | intel_display_power_enabled_sw(dev, |
13002 | intel_display_power_enabled_unlocked(dev_priv, |
Line 11475... | Line 13037... | ||
11475 | for_each_pipe(i) { |
13037 | for_each_pipe(i) { |
11476 | err_printf(m, "Pipe [%d]:\n", i); |
13038 | err_printf(m, "Pipe [%d]:\n", i); |
11477 | err_printf(m, " Power: %s\n", |
13039 | err_printf(m, " Power: %s\n", |
11478 | error->pipe[i].power_domain_on ? "on" : "off"); |
13040 | error->pipe[i].power_domain_on ? "on" : "off"); |
11479 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
13041 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
- | 13042 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
|
Line 11480... | Line 13043... | ||
11480 | 13043 | ||
11481 | err_printf(m, "Plane [%d]:\n", i); |
13044 | err_printf(m, "Plane [%d]:\n", i); |
11482 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
13045 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
11483 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
13046 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |