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Line 42... | Line 42... | ||
42 | //#include |
42 | //#include |
Line 43... | Line 43... | ||
43 | 43 | ||
44 | #define MAX_ERRNO 4095 |
44 | #define MAX_ERRNO 4095 |
Line -... | Line 45... | ||
- | 45 | phys_addr_t get_bus_addr(void); |
|
- | 46 | ||
45 | phys_addr_t get_bus_addr(void); |
47 | static inline void outb(u8 v, u16 port) |
- | 48 | { |
|
- | 49 | asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); |
|
- | 50 | } |
|
- | 51 | static inline u8 inb(u16 port) |
|
- | 52 | { |
|
- | 53 | u8 v; |
|
- | 54 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
|
- | 55 | return v; |
|
46 | 56 | } |
|
47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
57 | |
Line 48... | Line 58... | ||
48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
58 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
59 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
50 | 60 | ||
51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
61 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
Line 52... | Line 62... | ||
52 | struct intel_crtc_config *pipe_config); |
62 | struct intel_crtc_config *pipe_config); |
53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
63 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Line 70... | Line 80... | ||
70 | struct intel_limit { |
80 | struct intel_limit { |
71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
81 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
72 | intel_p2_t p2; |
82 | intel_p2_t p2; |
73 | }; |
83 | }; |
Line 74... | Line -... | ||
74 | - | ||
75 | /* FDI */ |
- | |
76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
- | |
77 | 84 | ||
78 | int |
85 | int |
79 | intel_pch_rawclk(struct drm_device *dev) |
86 | intel_pch_rawclk(struct drm_device *dev) |
80 | { |
87 | { |
Line 95... | Line 102... | ||
95 | return 27; |
102 | return 27; |
96 | } |
103 | } |
Line 97... | Line 104... | ||
97 | 104 | ||
98 | static const intel_limit_t intel_limits_i8xx_dac = { |
105 | static const intel_limit_t intel_limits_i8xx_dac = { |
99 | .dot = { .min = 25000, .max = 350000 }, |
106 | .dot = { .min = 25000, .max = 350000 }, |
100 | .vco = { .min = 930000, .max = 1400000 }, |
107 | .vco = { .min = 908000, .max = 1512000 }, |
101 | .n = { .min = 3, .max = 16 }, |
108 | .n = { .min = 2, .max = 16 }, |
102 | .m = { .min = 96, .max = 140 }, |
109 | .m = { .min = 96, .max = 140 }, |
103 | .m1 = { .min = 18, .max = 26 }, |
110 | .m1 = { .min = 18, .max = 26 }, |
104 | .m2 = { .min = 6, .max = 16 }, |
111 | .m2 = { .min = 6, .max = 16 }, |
105 | .p = { .min = 4, .max = 128 }, |
112 | .p = { .min = 4, .max = 128 }, |
Line 108... | Line 115... | ||
108 | .p2_slow = 4, .p2_fast = 2 }, |
115 | .p2_slow = 4, .p2_fast = 2 }, |
109 | }; |
116 | }; |
Line 110... | Line 117... | ||
110 | 117 | ||
111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
118 | static const intel_limit_t intel_limits_i8xx_dvo = { |
112 | .dot = { .min = 25000, .max = 350000 }, |
119 | .dot = { .min = 25000, .max = 350000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, |
120 | .vco = { .min = 908000, .max = 1512000 }, |
114 | .n = { .min = 3, .max = 16 }, |
121 | .n = { .min = 2, .max = 16 }, |
115 | .m = { .min = 96, .max = 140 }, |
122 | .m = { .min = 96, .max = 140 }, |
116 | .m1 = { .min = 18, .max = 26 }, |
123 | .m1 = { .min = 18, .max = 26 }, |
117 | .m2 = { .min = 6, .max = 16 }, |
124 | .m2 = { .min = 6, .max = 16 }, |
118 | .p = { .min = 4, .max = 128 }, |
125 | .p = { .min = 4, .max = 128 }, |
Line 121... | Line 128... | ||
121 | .p2_slow = 4, .p2_fast = 4 }, |
128 | .p2_slow = 4, .p2_fast = 4 }, |
122 | }; |
129 | }; |
Line 123... | Line 130... | ||
123 | 130 | ||
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
131 | static const intel_limit_t intel_limits_i8xx_lvds = { |
125 | .dot = { .min = 25000, .max = 350000 }, |
132 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, |
133 | .vco = { .min = 908000, .max = 1512000 }, |
127 | .n = { .min = 3, .max = 16 }, |
134 | .n = { .min = 2, .max = 16 }, |
128 | .m = { .min = 96, .max = 140 }, |
135 | .m = { .min = 96, .max = 140 }, |
129 | .m1 = { .min = 18, .max = 26 }, |
136 | .m1 = { .min = 18, .max = 26 }, |
130 | .m2 = { .min = 6, .max = 16 }, |
137 | .m2 = { .min = 6, .max = 16 }, |
131 | .p = { .min = 4, .max = 128 }, |
138 | .p = { .min = 4, .max = 128 }, |
Line 314... | Line 321... | ||
314 | .p1 = { .min = 2, .max = 6 }, |
321 | .p1 = { .min = 2, .max = 6 }, |
315 | .p2 = { .dot_limit = 225000, |
322 | .p2 = { .dot_limit = 225000, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
323 | .p2_slow = 7, .p2_fast = 7 }, |
317 | }; |
324 | }; |
Line 318... | Line 325... | ||
318 | 325 | ||
- | 326 | static const intel_limit_t intel_limits_vlv = { |
|
319 | static const intel_limit_t intel_limits_vlv_dac = { |
327 | /* |
320 | .dot = { .min = 25000, .max = 270000 }, |
328 | * These are the data rate limits (measured in fast clocks) |
321 | .vco = { .min = 4000000, .max = 6000000 }, |
- | |
322 | .n = { .min = 1, .max = 7 }, |
329 | * since those are the strictest limits we have. The fast |
323 | .m = { .min = 22, .max = 450 }, /* guess */ |
- | |
324 | .m1 = { .min = 2, .max = 3 }, |
- | |
325 | .m2 = { .min = 11, .max = 156 }, |
330 | * clock and actual rate limits are more relaxed, so checking |
326 | .p = { .min = 10, .max = 30 }, |
- | |
327 | .p1 = { .min = 1, .max = 3 }, |
- | |
328 | .p2 = { .dot_limit = 270000, |
- | |
329 | .p2_slow = 2, .p2_fast = 20 }, |
331 | * them would make no difference. |
330 | }; |
- | |
331 | - | ||
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
332 | */ |
333 | .dot = { .min = 25000, .max = 270000 }, |
333 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
335 | .n = { .min = 1, .max = 7 }, |
- | |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
335 | .n = { .min = 1, .max = 7 }, |
337 | .m1 = { .min = 2, .max = 3 }, |
336 | .m1 = { .min = 2, .max = 3 }, |
338 | .m2 = { .min = 11, .max = 156 }, |
- | |
339 | .p = { .min = 10, .max = 30 }, |
337 | .m2 = { .min = 11, .max = 156 }, |
340 | .p1 = { .min = 2, .max = 3 }, |
- | |
341 | .p2 = { .dot_limit = 270000, |
338 | .p1 = { .min = 2, .max = 3 }, |
342 | .p2_slow = 2, .p2_fast = 20 }, |
339 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
Line 343... | Line 340... | ||
343 | }; |
340 | }; |
- | 341 | ||
344 | 342 | static void vlv_clock(int refclk, intel_clock_t *clock) |
|
345 | static const intel_limit_t intel_limits_vlv_dp = { |
343 | { |
346 | .dot = { .min = 25000, .max = 270000 }, |
344 | clock->m = clock->m1 * clock->m2; |
- | 345 | clock->p = clock->p1 * clock->p2; |
|
347 | .vco = { .min = 4000000, .max = 6000000 }, |
346 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
348 | .n = { .min = 1, .max = 7 }, |
347 | return; |
- | 348 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
|
- | 349 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
- | 350 | } |
|
- | 351 | ||
- | 352 | /** |
|
- | 353 | * Returns whether any output on the specified pipe is of the specified type |
|
- | 354 | */ |
|
349 | .m = { .min = 22, .max = 450 }, |
355 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
350 | .m1 = { .min = 2, .max = 3 }, |
356 | { |
- | 357 | struct drm_device *dev = crtc->dev; |
|
351 | .m2 = { .min = 11, .max = 156 }, |
358 | struct intel_encoder *encoder; |
352 | .p = { .min = 10, .max = 30 }, |
359 | |
353 | .p1 = { .min = 1, .max = 3 }, |
360 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | 361 | if (encoder->type == type) |
|
- | 362 | return true; |
|
354 | .p2 = { .dot_limit = 270000, |
363 | |
Line 355... | Line 364... | ||
355 | .p2_slow = 2, .p2_fast = 20 }, |
364 | return false; |
356 | }; |
365 | } |
357 | 366 | ||
358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
367 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
Line 413... | Line 422... | ||
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
414 | limit = &intel_limits_pineview_lvds; |
423 | limit = &intel_limits_pineview_lvds; |
415 | else |
424 | else |
416 | limit = &intel_limits_pineview_sdvo; |
425 | limit = &intel_limits_pineview_sdvo; |
417 | } else if (IS_VALLEYVIEW(dev)) { |
426 | } else if (IS_VALLEYVIEW(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
- | |
419 | limit = &intel_limits_vlv_dac; |
- | |
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
- | |
421 | limit = &intel_limits_vlv_hdmi; |
- | |
422 | else |
- | |
423 | limit = &intel_limits_vlv_dp; |
427 | limit = &intel_limits_vlv; |
424 | } else if (!IS_GEN2(dev)) { |
428 | } else if (!IS_GEN2(dev)) { |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
429 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
426 | limit = &intel_limits_i9xx_lvds; |
430 | limit = &intel_limits_i9xx_lvds; |
427 | else |
431 | else |
428 | limit = &intel_limits_i9xx_sdvo; |
432 | limit = &intel_limits_i9xx_sdvo; |
Line 440... | Line 444... | ||
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
444 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
445 | static void pineview_clock(int refclk, intel_clock_t *clock) |
442 | { |
446 | { |
443 | clock->m = clock->m2 + 2; |
447 | clock->m = clock->m2 + 2; |
444 | clock->p = clock->p1 * clock->p2; |
448 | clock->p = clock->p1 * clock->p2; |
- | 449 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
|
- | 450 | return; |
|
445 | clock->vco = refclk * clock->m / clock->n; |
451 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
446 | clock->dot = clock->vco / clock->p; |
452 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
447 | } |
453 | } |
Line 448... | Line 454... | ||
448 | 454 | ||
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
455 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
450 | { |
456 | { |
Line 453... | Line 459... | ||
453 | 459 | ||
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
460 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
455 | { |
461 | { |
456 | clock->m = i9xx_dpll_compute_m(clock); |
462 | clock->m = i9xx_dpll_compute_m(clock); |
457 | clock->p = clock->p1 * clock->p2; |
463 | clock->p = clock->p1 * clock->p2; |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
- | |
459 | clock->dot = clock->vco / clock->p; |
- | |
460 | } |
- | |
461 | - | ||
462 | /** |
- | |
463 | * Returns whether any output on the specified pipe is of the specified type |
464 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
464 | */ |
465 | return; |
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
- | |
466 | { |
- | |
467 | struct drm_device *dev = crtc->dev; |
- | |
468 | struct intel_encoder *encoder; |
- | |
469 | 466 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
|
470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
471 | if (encoder->type == type) |
- | |
472 | return true; |
- | |
473 | - | ||
474 | return false; |
467 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Line 475... | Line 468... | ||
475 | } |
468 | } |
476 | 469 | ||
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
470 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Line 482... | Line 475... | ||
482 | 475 | ||
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
476 | static bool intel_PLL_is_valid(struct drm_device *dev, |
484 | const intel_limit_t *limit, |
477 | const intel_limit_t *limit, |
485 | const intel_clock_t *clock) |
478 | const intel_clock_t *clock) |
- | 479 | { |
|
- | 480 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
|
486 | { |
481 | INTELPllInvalid("n out of range\n"); |
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
482 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
488 | INTELPllInvalid("p1 out of range\n"); |
- | |
489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
- | |
490 | INTELPllInvalid("p out of range\n"); |
483 | INTELPllInvalid("p1 out of range\n"); |
491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
484 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
492 | INTELPllInvalid("m2 out of range\n"); |
485 | INTELPllInvalid("m2 out of range\n"); |
493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
486 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
- | 487 | INTELPllInvalid("m1 out of range\n"); |
|
- | 488 | ||
494 | INTELPllInvalid("m1 out of range\n"); |
489 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
490 | if (clock->m1 <= clock->m2) |
- | 491 | INTELPllInvalid("m1 <= m2\n"); |
|
- | 492 | ||
- | 493 | if (!IS_VALLEYVIEW(dev)) { |
|
- | 494 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
|
496 | INTELPllInvalid("m1 <= m2\n"); |
495 | INTELPllInvalid("p out of range\n"); |
497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
496 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
498 | INTELPllInvalid("m out of range\n"); |
- | |
499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
- | |
- | 497 | INTELPllInvalid("m out of range\n"); |
|
- | 498 | } |
|
500 | INTELPllInvalid("n out of range\n"); |
499 | |
501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
500 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
502 | INTELPllInvalid("vco out of range\n"); |
501 | INTELPllInvalid("vco out of range\n"); |
503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
502 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
504 | * connector, etc., rather than just a single range. |
503 | * connector, etc., rather than just a single range. |
Line 689... | Line 688... | ||
689 | static bool |
688 | static bool |
690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
689 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
691 | int target, int refclk, intel_clock_t *match_clock, |
690 | int target, int refclk, intel_clock_t *match_clock, |
692 | intel_clock_t *best_clock) |
691 | intel_clock_t *best_clock) |
693 | { |
692 | { |
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
693 | struct drm_device *dev = crtc->dev; |
695 | u32 m, n, fastclk; |
694 | intel_clock_t clock; |
- | 695 | unsigned int bestppm = 1000000; |
|
696 | u32 updrate, minupdate, p; |
696 | /* min update 19.2 MHz */ |
697 | unsigned long bestppm, ppm, absppm; |
697 | int max_n = min(limit->n.max, refclk / 19200); |
698 | int dotclk, flag; |
698 | bool found = false; |
699 | 699 | ||
700 | flag = 0; |
- | |
701 | dotclk = target * 1000; |
- | |
702 | bestppm = 1000000; |
- | |
703 | ppm = absppm = 0; |
- | |
704 | fastclk = dotclk / (2*100); |
700 | target *= 5; /* fast clock */ |
705 | updrate = 0; |
701 | |
706 | minupdate = 19200; |
- | |
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
- | |
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
702 | memset(best_clock, 0, sizeof(*best_clock)); |
Line 709... | Line 703... | ||
709 | 703 | ||
710 | /* based on hardware requirement, prefer smaller n to precision */ |
704 | /* based on hardware requirement, prefer smaller n to precision */ |
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
- | |
712 | updrate = refclk / n; |
705 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
706 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
- | |
715 | if (p2 > 10) |
707 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
716 | p2 = p2 - 1; |
708 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
717 | p = p1 * p2; |
709 | clock.p = clock.p1 * clock.p2; |
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
710 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
711 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
- | 712 | unsigned int ppm, diff; |
|
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
713 | |
721 | refclk) / (2*refclk)); |
714 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
- | 715 | refclk * clock.m1); |
|
722 | m = m1 * m2; |
716 | |
- | 717 | vlv_clock(refclk, &clock); |
|
723 | vco = updrate * m; |
718 | |
- | 719 | if (!intel_PLL_is_valid(dev, limit, |
|
- | 720 | &clock)) |
|
- | 721 | continue; |
|
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
722 | |
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
723 | diff = abs(clock.dot - target); |
- | 724 | ppm = div_u64(1000000ULL * diff, target); |
|
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
725 | |
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
726 | if (ppm < 100 && clock.p > best_clock->p) { |
728 | bestppm = 0; |
- | |
729 | flag = 1; |
- | |
730 | } |
- | |
731 | if (absppm < bestppm - 10) { |
727 | bestppm = 0; |
732 | bestppm = absppm; |
728 | *best_clock = clock; |
733 | flag = 1; |
729 | found = true; |
734 | } |
- | |
735 | if (flag) { |
- | |
- | 730 | } |
|
736 | bestn = n; |
731 | |
737 | bestm1 = m1; |
- | |
738 | bestm2 = m2; |
732 | if (bestppm >= 10 && ppm < bestppm - 10) { |
739 | bestp1 = p1; |
733 | bestppm = ppm; |
740 | bestp2 = p2; |
734 | *best_clock = clock; |
741 | flag = 0; |
735 | found = true; |
742 | } |
736 | } |
743 | } |
737 | } |
744 | } |
738 | } |
745 | } |
739 | } |
- | 740 | } |
|
- | 741 | ||
746 | } |
742 | return found; |
747 | } |
- | |
748 | best_clock->n = bestn; |
- | |
749 | best_clock->m1 = bestm1; |
- | |
750 | best_clock->m2 = bestm2; |
- | |
751 | best_clock->p1 = bestp1; |
- | |
Line -... | Line 743... | ||
- | 743 | } |
|
- | 744 | ||
- | 745 | bool intel_crtc_active(struct drm_crtc *crtc) |
|
- | 746 | { |
|
- | 747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 748 | ||
- | 749 | /* Be paranoid as we can arrive here with only partial |
|
- | 750 | * state retrieved from the hardware during setup. |
|
- | 751 | * |
|
- | 752 | * We can ditch the adjusted_mode.crtc_clock check as soon |
|
- | 753 | * as Haswell has gained clock readout/fastboot support. |
|
- | 754 | * |
|
- | 755 | * We can ditch the crtc->fb check as soon as we can |
|
752 | best_clock->p2 = bestp2; |
756 | * properly reconstruct framebuffers. |
- | 757 | */ |
|
753 | 758 | return intel_crtc->active && crtc->fb && |
|
Line 754... | Line 759... | ||
754 | return true; |
759 | intel_crtc->config.adjusted_mode.crtc_clock; |
755 | } |
760 | } |
756 | 761 | ||
Line 761... | Line 766... | ||
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 762... | Line 767... | ||
762 | 767 | ||
763 | return intel_crtc->config.cpu_transcoder; |
768 | return intel_crtc->config.cpu_transcoder; |
Line 764... | Line 769... | ||
764 | } |
769 | } |
765 | 770 | ||
766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
771 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
767 | { |
772 | { |
Line 768... | Line 773... | ||
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
773 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 769... | Line 774... | ||
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
774 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
770 | 775 | ||
Line 785... | Line 790... | ||
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
790 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
786 | { |
791 | { |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | struct drm_i915_private *dev_priv = dev->dev_private; |
788 | int pipestat_reg = PIPESTAT(pipe); |
793 | int pipestat_reg = PIPESTAT(pipe); |
Line 789... | Line 794... | ||
789 | 794 | ||
790 | if (INTEL_INFO(dev)->gen >= 5) { |
795 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
791 | ironlake_wait_for_vblank(dev, pipe); |
796 | g4x_wait_for_vblank(dev, pipe); |
792 | return; |
797 | return; |
Line 793... | Line 798... | ||
793 | } |
798 | } |
794 | 799 | ||
Line 813... | Line 818... | ||
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
818 | PIPE_VBLANK_INTERRUPT_STATUS, |
814 | 50)) |
819 | 50)) |
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
820 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
816 | } |
821 | } |
Line -... | Line 822... | ||
- | 822 | ||
- | 823 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
|
- | 824 | { |
|
- | 825 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 826 | u32 reg = PIPEDSL(pipe); |
|
- | 827 | u32 line1, line2; |
|
- | 828 | u32 line_mask; |
|
- | 829 | ||
- | 830 | if (IS_GEN2(dev)) |
|
- | 831 | line_mask = DSL_LINEMASK_GEN2; |
|
- | 832 | else |
|
- | 833 | line_mask = DSL_LINEMASK_GEN3; |
|
- | 834 | ||
- | 835 | line1 = I915_READ(reg) & line_mask; |
|
- | 836 | mdelay(5); |
|
- | 837 | line2 = I915_READ(reg) & line_mask; |
|
- | 838 | ||
- | 839 | return line1 == line2; |
|
- | 840 | } |
|
817 | 841 | ||
818 | /* |
842 | /* |
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
843 | * intel_wait_for_pipe_off - wait for pipe to turn off |
820 | * @dev: drm device |
844 | * @dev: drm device |
821 | * @pipe: pipe to wait for |
845 | * @pipe: pipe to wait for |
Line 844... | Line 868... | ||
844 | /* Wait for the Pipe State to go off */ |
868 | /* Wait for the Pipe State to go off */ |
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
869 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
846 | 100)) |
870 | 100)) |
847 | WARN(1, "pipe_off wait timed out\n"); |
871 | WARN(1, "pipe_off wait timed out\n"); |
848 | } else { |
872 | } else { |
849 | u32 last_line, line_mask; |
- | |
850 | int reg = PIPEDSL(pipe); |
- | |
851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
- | |
852 | - | ||
853 | if (IS_GEN2(dev)) |
- | |
854 | line_mask = DSL_LINEMASK_GEN2; |
- | |
855 | else |
- | |
856 | line_mask = DSL_LINEMASK_GEN3; |
- | |
857 | - | ||
858 | /* Wait for the display line to settle */ |
873 | /* Wait for the display line to settle */ |
859 | do { |
- | |
860 | last_line = I915_READ(reg) & line_mask; |
- | |
861 | mdelay(5); |
- | |
862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
- | |
863 | time_after(timeout, GetTimerTicks())); |
- | |
864 | if (time_after(GetTimerTicks(), timeout)) |
874 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
865 | WARN(1, "pipe_off wait timed out\n"); |
875 | WARN(1, "pipe_off wait timed out\n"); |
866 | } |
876 | } |
867 | } |
877 | } |
Line 868... | Line 878... | ||
868 | 878 | ||
Line 930... | Line 940... | ||
930 | WARN(cur_state != state, |
940 | WARN(cur_state != state, |
931 | "PLL state assertion failure (expected %s, current %s)\n", |
941 | "PLL state assertion failure (expected %s, current %s)\n", |
932 | state_string(state), state_string(cur_state)); |
942 | state_string(state), state_string(cur_state)); |
933 | } |
943 | } |
Line -... | Line 944... | ||
- | 944 | ||
- | 945 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
|
- | 946 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
|
- | 947 | { |
|
- | 948 | u32 val; |
|
- | 949 | bool cur_state; |
|
- | 950 | ||
- | 951 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 952 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
|
- | 953 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 954 | ||
- | 955 | cur_state = val & DSI_PLL_VCO_EN; |
|
- | 956 | WARN(cur_state != state, |
|
- | 957 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
|
- | 958 | state_string(state), state_string(cur_state)); |
|
- | 959 | } |
|
- | 960 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
|
- | 961 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
|
934 | 962 | ||
935 | struct intel_shared_dpll * |
963 | struct intel_shared_dpll * |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
964 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
937 | { |
965 | { |
Line 1070... | Line 1098... | ||
1070 | WARN(panel_pipe == pipe && locked, |
1098 | WARN(panel_pipe == pipe && locked, |
1071 | "panel assertion failure, pipe %c regs locked\n", |
1099 | "panel assertion failure, pipe %c regs locked\n", |
1072 | pipe_name(pipe)); |
1100 | pipe_name(pipe)); |
1073 | } |
1101 | } |
Line -... | Line 1102... | ||
- | 1102 | ||
- | 1103 | static void assert_cursor(struct drm_i915_private *dev_priv, |
|
- | 1104 | enum pipe pipe, bool state) |
|
- | 1105 | { |
|
- | 1106 | struct drm_device *dev = dev_priv->dev; |
|
- | 1107 | bool cur_state; |
|
- | 1108 | ||
- | 1109 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
|
- | 1110 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; |
|
- | 1111 | else if (IS_845G(dev) || IS_I865G(dev)) |
|
- | 1112 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
|
- | 1113 | else |
|
- | 1114 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
|
- | 1115 | ||
- | 1116 | WARN(cur_state != state, |
|
- | 1117 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
|
- | 1118 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
|
- | 1119 | } |
|
- | 1120 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
|
- | 1121 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
|
1074 | 1122 | ||
1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
1123 | void assert_pipe(struct drm_i915_private *dev_priv, |
1076 | enum pipe pipe, bool state) |
1124 | enum pipe pipe, bool state) |
1077 | { |
1125 | { |
1078 | int reg; |
1126 | int reg; |
Line 1175... | Line 1223... | ||
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1223 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1176 | plane_name(pipe), pipe_name(pipe)); |
1224 | plane_name(pipe), pipe_name(pipe)); |
1177 | } |
1225 | } |
1178 | } |
1226 | } |
Line 1179... | Line 1227... | ||
1179 | 1227 | ||
1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1228 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1181 | { |
1229 | { |
1182 | u32 val; |
1230 | u32 val; |
Line 1183... | Line 1231... | ||
1183 | bool enabled; |
1231 | bool enabled; |
1184 | - | ||
1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
- | |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
- | |
Line 1187... | Line 1232... | ||
1187 | return; |
1232 | |
1188 | } |
1233 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
1189 | 1234 | ||
1190 | val = I915_READ(PCH_DREF_CONTROL); |
1235 | val = I915_READ(PCH_DREF_CONTROL); |
Line 1324... | Line 1369... | ||
1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1369 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1370 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1371 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1327 | } |
1372 | } |
Line -... | Line 1373... | ||
- | 1373 | ||
- | 1374 | static void intel_init_dpio(struct drm_device *dev) |
|
- | 1375 | { |
|
- | 1376 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1377 | ||
- | 1378 | if (!IS_VALLEYVIEW(dev)) |
|
- | 1379 | return; |
|
- | 1380 | ||
- | 1381 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
|
- | 1382 | } |
|
- | 1383 | ||
- | 1384 | static void intel_reset_dpio(struct drm_device *dev) |
|
- | 1385 | { |
|
- | 1386 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1387 | ||
- | 1388 | if (!IS_VALLEYVIEW(dev)) |
|
- | 1389 | return; |
|
- | 1390 | ||
- | 1391 | /* |
|
- | 1392 | * Enable the CRI clock source so we can get at the display and the |
|
- | 1393 | * reference clock for VGA hotplug / manual detection. |
|
- | 1394 | */ |
|
- | 1395 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
|
- | 1396 | DPLL_REFA_CLK_ENABLE_VLV | |
|
- | 1397 | DPLL_INTEGRATED_CRI_CLK_VLV); |
|
- | 1398 | ||
- | 1399 | /* |
|
- | 1400 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
|
- | 1401 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
|
- | 1402 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
|
- | 1403 | * b. The other bits such as sfr settings / modesel may all be set |
|
- | 1404 | * to 0. |
|
- | 1405 | * |
|
- | 1406 | * This should only be done on init and resume from S3 with both |
|
- | 1407 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. |
|
- | 1408 | */ |
|
- | 1409 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
|
- | 1410 | } |
|
1328 | 1411 | ||
1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1412 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1330 | { |
1413 | { |
1331 | struct drm_device *dev = crtc->base.dev; |
1414 | struct drm_device *dev = crtc->base.dev; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1437... | Line 1520... | ||
1437 | u32 val = 0; |
1520 | u32 val = 0; |
Line 1438... | Line 1521... | ||
1438 | 1521 | ||
1439 | /* Make sure the pipe isn't still relying on us */ |
1522 | /* Make sure the pipe isn't still relying on us */ |
Line -... | Line 1523... | ||
- | 1523 | assert_pipe_disabled(dev_priv, pipe); |
|
1440 | assert_pipe_disabled(dev_priv, pipe); |
1524 | |
- | 1525 | /* |
|
- | 1526 | * Leave integrated clock source and reference clock enabled for pipe B. |
|
1441 | 1527 | * The latter is needed for VGA hotplug / manual detection. |
|
1442 | /* Leave integrated clock source enabled */ |
1528 | */ |
1443 | if (pipe == PIPE_B) |
1529 | if (pipe == PIPE_B) |
1444 | val = DPLL_INTEGRATED_CRI_CLK_VLV; |
1530 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1445 | I915_WRITE(DPLL(pipe), val); |
1531 | I915_WRITE(DPLL(pipe), val); |
Line 1446... | Line 1532... | ||
1446 | POSTING_READ(DPLL(pipe)); |
1532 | POSTING_READ(DPLL(pipe)); |
- | 1533 | } |
|
1447 | } |
1534 | |
1448 | 1535 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
|
Line 1449... | Line 1536... | ||
1449 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1536 | struct intel_digital_port *dport) |
- | 1537 | { |
|
1450 | { |
1538 | u32 port_mask; |
1451 | u32 port_mask; |
1539 | |
- | 1540 | switch (dport->port) { |
|
1452 | 1541 | case PORT_B: |
|
- | 1542 | port_mask = DPLL_PORTB_READY_MASK; |
|
- | 1543 | break; |
|
- | 1544 | case PORT_C: |
|
- | 1545 | port_mask = DPLL_PORTC_READY_MASK; |
|
Line 1453... | Line 1546... | ||
1453 | if (!port) |
1546 | break; |
1454 | port_mask = DPLL_PORTB_READY_MASK; |
1547 | default: |
1455 | else |
1548 | BUG(); |
1456 | port_mask = DPLL_PORTC_READY_MASK; |
1549 | } |
Line 1457... | Line 1550... | ||
1457 | 1550 | ||
1458 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1551 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1459 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1552 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
Line 1676... | Line 1769... | ||
1676 | * |
1769 | * |
1677 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1770 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1678 | * returning. |
1771 | * returning. |
1679 | */ |
1772 | */ |
1680 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1773 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1681 | bool pch_port) |
1774 | bool pch_port, bool dsi) |
1682 | { |
1775 | { |
1683 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1776 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1684 | pipe); |
1777 | pipe); |
1685 | enum pipe pch_transcoder; |
1778 | enum pipe pch_transcoder; |
1686 | int reg; |
1779 | int reg; |
1687 | u32 val; |
1780 | u32 val; |
Line 1688... | Line 1781... | ||
1688 | 1781 | ||
- | 1782 | assert_planes_disabled(dev_priv, pipe); |
|
1689 | assert_planes_disabled(dev_priv, pipe); |
1783 | assert_cursor_disabled(dev_priv, pipe); |
Line 1690... | Line 1784... | ||
1690 | assert_sprites_disabled(dev_priv, pipe); |
1784 | assert_sprites_disabled(dev_priv, pipe); |
1691 | 1785 | ||
1692 | if (HAS_PCH_LPT(dev_priv->dev)) |
1786 | if (HAS_PCH_LPT(dev_priv->dev)) |
Line 1698... | Line 1792... | ||
1698 | * A pipe without a PLL won't actually be able to drive bits from |
1792 | * A pipe without a PLL won't actually be able to drive bits from |
1699 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1793 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1700 | * need the check. |
1794 | * need the check. |
1701 | */ |
1795 | */ |
1702 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1796 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
- | 1797 | if (dsi) |
|
- | 1798 | assert_dsi_pll_enabled(dev_priv); |
|
- | 1799 | else |
|
1703 | assert_pll_enabled(dev_priv, pipe); |
1800 | assert_pll_enabled(dev_priv, pipe); |
1704 | else { |
1801 | else { |
1705 | if (pch_port) { |
1802 | if (pch_port) { |
1706 | /* if driving the PCH, we need FDI enabled */ |
1803 | /* if driving the PCH, we need FDI enabled */ |
1707 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1804 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
Line 1743... | Line 1840... | ||
1743 | /* |
1840 | /* |
1744 | * Make sure planes won't keep trying to pump pixels to us, |
1841 | * Make sure planes won't keep trying to pump pixels to us, |
1745 | * or we might hang the display. |
1842 | * or we might hang the display. |
1746 | */ |
1843 | */ |
1747 | assert_planes_disabled(dev_priv, pipe); |
1844 | assert_planes_disabled(dev_priv, pipe); |
- | 1845 | assert_cursor_disabled(dev_priv, pipe); |
|
1748 | assert_sprites_disabled(dev_priv, pipe); |
1846 | assert_sprites_disabled(dev_priv, pipe); |
Line 1749... | Line 1847... | ||
1749 | 1847 | ||
1750 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1848 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1751 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1849 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
Line 1762... | Line 1860... | ||
1762 | 1860 | ||
1763 | /* |
1861 | /* |
1764 | * Plane regs are double buffered, going from enabled->disabled needs a |
1862 | * Plane regs are double buffered, going from enabled->disabled needs a |
1765 | * trigger in order to latch. The display address reg provides this. |
1863 | * trigger in order to latch. The display address reg provides this. |
1766 | */ |
1864 | */ |
1767 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1865 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1768 | enum plane plane) |
1866 | enum plane plane) |
1769 | { |
- | |
1770 | if (dev_priv->info->gen >= 4) |
1867 | { |
1771 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1868 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1772 | else |
1869 | |
- | 1870 | I915_WRITE(reg, I915_READ(reg)); |
|
1773 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1871 | POSTING_READ(reg); |
Line 1774... | Line 1872... | ||
1774 | } |
1872 | } |
1775 | 1873 | ||
1776 | /** |
1874 | /** |
1777 | * intel_enable_plane - enable a display plane on a given pipe |
1875 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
1778 | * @dev_priv: i915 private structure |
1876 | * @dev_priv: i915 private structure |
1779 | * @plane: plane to enable |
1877 | * @plane: plane to enable |
1780 | * @pipe: pipe being fed |
1878 | * @pipe: pipe being fed |
1781 | * |
1879 | * |
1782 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1880 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1783 | */ |
1881 | */ |
1784 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1882 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
- | 1883 | enum plane plane, enum pipe pipe) |
|
- | 1884 | { |
|
1785 | enum plane plane, enum pipe pipe) |
1885 | struct intel_crtc *intel_crtc = |
1786 | { |
1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Line 1787... | Line 1887... | ||
1787 | int reg; |
1887 | int reg; |
1788 | u32 val; |
1888 | u32 val; |
Line -... | Line 1889... | ||
- | 1889 | ||
- | 1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
|
- | 1891 | assert_pipe_enabled(dev_priv, pipe); |
|
- | 1892 | ||
1789 | 1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
|
1790 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1894 | |
1791 | assert_pipe_enabled(dev_priv, pipe); |
1895 | intel_crtc->primary_enabled = true; |
1792 | 1896 | ||
Line 1793... | Line 1897... | ||
1793 | reg = DSPCNTR(plane); |
1897 | reg = DSPCNTR(plane); |
1794 | val = I915_READ(reg); |
1898 | val = I915_READ(reg); |
1795 | if (val & DISPLAY_PLANE_ENABLE) |
1899 | if (val & DISPLAY_PLANE_ENABLE) |
1796 | return; |
1900 | return; |
Line 1797... | Line 1901... | ||
1797 | 1901 | ||
1798 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1799 | intel_flush_display_plane(dev_priv, plane); |
1903 | intel_flush_primary_plane(dev_priv, plane); |
1800 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1801 | } |
1905 | } |
1802 | 1906 | ||
1803 | /** |
1907 | /** |
1804 | * intel_disable_plane - disable a display plane |
1908 | * intel_disable_primary_plane - disable the primary plane |
1805 | * @dev_priv: i915 private structure |
1909 | * @dev_priv: i915 private structure |
1806 | * @plane: plane to disable |
1910 | * @plane: plane to disable |
1807 | * @pipe: pipe consuming the data |
1911 | * @pipe: pipe consuming the data |
- | 1912 | * |
|
- | 1913 | * Disable @plane; should be an independent operation. |
|
1808 | * |
1914 | */ |
1809 | * Disable @plane; should be an independent operation. |
1915 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
Line -... | Line 1916... | ||
- | 1916 | enum plane plane, enum pipe pipe) |
|
- | 1917 | { |
|
- | 1918 | struct intel_crtc *intel_crtc = |
|
- | 1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
|
1810 | */ |
1920 | int reg; |
1811 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1921 | u32 val; |
1812 | enum plane plane, enum pipe pipe) |
1922 | |
1813 | { |
1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
Line 1814... | Line 1924... | ||
1814 | int reg; |
1924 | |
1815 | u32 val; |
1925 | intel_crtc->primary_enabled = false; |
1816 | 1926 | ||
1817 | reg = DSPCNTR(plane); |
1927 | reg = DSPCNTR(plane); |
Line 1818... | Line 1928... | ||
1818 | val = I915_READ(reg); |
1928 | val = I915_READ(reg); |
1819 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1929 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
Line 1854... | Line 1964... | ||
1854 | case I915_TILING_X: |
1964 | case I915_TILING_X: |
1855 | /* pin() will align the object as required by fence */ |
1965 | /* pin() will align the object as required by fence */ |
1856 | alignment = 0; |
1966 | alignment = 0; |
1857 | break; |
1967 | break; |
1858 | case I915_TILING_Y: |
1968 | case I915_TILING_Y: |
1859 | /* Despite that we check this in framebuffer_init userspace can |
- | |
1860 | * screw us over and change the tiling after the fact. Only |
- | |
1861 | * pinned buffers can't change their tiling. */ |
- | |
1862 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
1969 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
1863 | return -EINVAL; |
1970 | return -EINVAL; |
1864 | default: |
1971 | default: |
1865 | BUG(); |
1972 | BUG(); |
1866 | } |
1973 | } |
Line 2019... | Line 2126... | ||
2019 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2126 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2020 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2127 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2021 | fb->pitches[0]); |
2128 | fb->pitches[0]); |
2022 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2129 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2023 | if (INTEL_INFO(dev)->gen >= 4) { |
2130 | if (INTEL_INFO(dev)->gen >= 4) { |
2024 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2131 | I915_WRITE(DSPSURF(plane), |
2025 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2132 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2026 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2133 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2027 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2134 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2028 | } else |
2135 | } else |
2029 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2136 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
Line 2092... | Line 2199... | ||
2092 | if (obj->tiling_mode != I915_TILING_NONE) |
2199 | if (obj->tiling_mode != I915_TILING_NONE) |
2093 | dspcntr |= DISPPLANE_TILED; |
2200 | dspcntr |= DISPPLANE_TILED; |
2094 | else |
2201 | else |
2095 | dspcntr &= ~DISPPLANE_TILED; |
2202 | dspcntr &= ~DISPPLANE_TILED; |
Line 2096... | Line 2203... | ||
2096 | 2203 | ||
2097 | if (IS_HASWELL(dev)) |
2204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2098 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2205 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2099 | else |
2206 | else |
Line 2100... | Line 2207... | ||
2100 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2207 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Line 2110... | Line 2217... | ||
2110 | 2217 | ||
2111 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2218 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2112 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2219 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2113 | fb->pitches[0]); |
2220 | fb->pitches[0]); |
2114 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2221 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2115 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2222 | I915_WRITE(DSPSURF(plane), |
2116 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2223 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2117 | if (IS_HASWELL(dev)) { |
2224 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2118 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2225 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2119 | } else { |
2226 | } else { |
2120 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2227 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2121 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2228 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
Line 2170... | Line 2277... | ||
2170 | 2277 | ||
2171 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2278 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Line 2172... | Line 2279... | ||
2172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 2280 | ||
- | 2281 | mutex_lock(&crtc->mutex); |
|
- | 2282 | /* |
|
- | 2283 | * FIXME: Once we have proper support for primary planes (and |
|
- | 2284 | * disabling them without disabling the entire crtc) allow again |
|
2173 | 2285 | * a NULL crtc->fb. |
|
2174 | mutex_lock(&crtc->mutex); |
2286 | */ |
2175 | if (intel_crtc->active) |
2287 | if (intel_crtc->active && crtc->fb) |
2176 | dev_priv->display.update_plane(crtc, crtc->fb, |
2288 | dev_priv->display.update_plane(crtc, crtc->fb, |
2177 | crtc->x, crtc->y); |
2289 | crtc->x, crtc->y); |
2178 | mutex_unlock(&crtc->mutex); |
2290 | mutex_unlock(&crtc->mutex); |
Line 2261... | Line 2373... | ||
2261 | mutex_unlock(&dev->struct_mutex); |
2373 | mutex_unlock(&dev->struct_mutex); |
2262 | DRM_ERROR("pin & fence failed\n"); |
2374 | DRM_ERROR("pin & fence failed\n"); |
2263 | return ret; |
2375 | return ret; |
2264 | } |
2376 | } |
Line -... | Line 2377... | ||
- | 2377 | ||
2265 | 2378 | /* |
|
- | 2379 | * Update pipe size and adjust fitter if needed: the reason for this is |
|
- | 2380 | * that in compute_mode_changes we check the native mode (not the pfit |
|
- | 2381 | * mode) to see if we can flip rather than do a full mode set. In the |
|
- | 2382 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
|
- | 2383 | * pfit state, we'll end up with a big fb scanned out into the wrong |
|
- | 2384 | * sized surface. |
|
- | 2385 | * |
|
- | 2386 | * To fix this properly, we need to hoist the checks up into |
|
- | 2387 | * compute_mode_changes (or above), check the actual pfit state and |
|
- | 2388 | * whether the platform allows pfit disable with pipe active, and only |
|
- | 2389 | * then update the pipesrc and pfit state, even on the flip path. |
|
2266 | /* Update pipe size and adjust fitter if needed */ |
2390 | */ |
- | 2391 | if (i915_fastboot) { |
|
- | 2392 | const struct drm_display_mode *adjusted_mode = |
|
- | 2393 | &intel_crtc->config.adjusted_mode; |
|
2267 | if (i915_fastboot) { |
2394 | |
2268 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2395 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2269 | ((crtc->mode.hdisplay - 1) << 16) | |
2396 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2270 | (crtc->mode.vdisplay - 1)); |
2397 | (adjusted_mode->crtc_vdisplay - 1)); |
2271 | if (!intel_crtc->config.pch_pfit.enabled && |
2398 | if (!intel_crtc->config.pch_pfit.enabled && |
2272 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2399 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2273 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2400 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2274 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2401 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2275 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2402 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2276 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2403 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
- | 2404 | } |
|
- | 2405 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
|
2277 | } |
2406 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
Line 2278... | Line 2407... | ||
2278 | } |
2407 | } |
2279 | 2408 | ||
2280 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2409 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
Line 2890... | Line 3019... | ||
2890 | /* Program iCLKIP clock to the desired frequency */ |
3019 | /* Program iCLKIP clock to the desired frequency */ |
2891 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
3020 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2892 | { |
3021 | { |
2893 | struct drm_device *dev = crtc->dev; |
3022 | struct drm_device *dev = crtc->dev; |
2894 | struct drm_i915_private *dev_priv = dev->dev_private; |
3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 3024 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
|
2895 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3025 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2896 | u32 temp; |
3026 | u32 temp; |
Line 2897... | Line 3027... | ||
2897 | 3027 | ||
Line 2907... | Line 3037... | ||
2907 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3037 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2908 | SBI_SSCCTL_DISABLE, |
3038 | SBI_SSCCTL_DISABLE, |
2909 | SBI_ICLK); |
3039 | SBI_ICLK); |
Line 2910... | Line 3040... | ||
2910 | 3040 | ||
2911 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
3041 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2912 | if (crtc->mode.clock == 20000) { |
3042 | if (clock == 20000) { |
2913 | auxdiv = 1; |
3043 | auxdiv = 1; |
2914 | divsel = 0x41; |
3044 | divsel = 0x41; |
2915 | phaseinc = 0x20; |
3045 | phaseinc = 0x20; |
2916 | } else { |
3046 | } else { |
2917 | /* The iCLK virtual clock root frequency is in MHz, |
3047 | /* The iCLK virtual clock root frequency is in MHz, |
2918 | * but the crtc->mode.clock in in KHz. To get the divisors, |
3048 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
2919 | * it is necessary to divide one by another, so we |
3049 | * divisors, it is necessary to divide one by another, so we |
2920 | * convert the virtual clock precision to KHz here for higher |
3050 | * convert the virtual clock precision to KHz here for higher |
2921 | * precision. |
3051 | * precision. |
2922 | */ |
3052 | */ |
2923 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3053 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2924 | u32 iclk_pi_range = 64; |
3054 | u32 iclk_pi_range = 64; |
Line 2925... | Line 3055... | ||
2925 | u32 desired_divisor, msb_divisor_value, pi_value; |
3055 | u32 desired_divisor, msb_divisor_value, pi_value; |
2926 | 3056 | ||
2927 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
3057 | desired_divisor = (iclk_virtual_root_freq / clock); |
Line 2928... | Line 3058... | ||
2928 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3058 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2929 | pi_value = desired_divisor % iclk_pi_range; |
3059 | pi_value = desired_divisor % iclk_pi_range; |
Line 2938... | Line 3068... | ||
2938 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
3068 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2939 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
3069 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2940 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
3070 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
Line 2941... | Line 3071... | ||
2941 | 3071 | ||
2942 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
3072 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2943 | crtc->mode.clock, |
3073 | clock, |
2944 | auxdiv, |
3074 | auxdiv, |
2945 | divsel, |
3075 | divsel, |
2946 | phasedir, |
3076 | phasedir, |
Line 3303... | Line 3433... | ||
3303 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3433 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3304 | if (intel_plane->pipe == pipe) |
3434 | if (intel_plane->pipe == pipe) |
3305 | intel_plane_disable(&intel_plane->base); |
3435 | intel_plane_disable(&intel_plane->base); |
3306 | } |
3436 | } |
Line -... | Line 3437... | ||
- | 3437 | ||
- | 3438 | void hsw_enable_ips(struct intel_crtc *crtc) |
|
- | 3439 | { |
|
- | 3440 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
- | 3441 | ||
- | 3442 | if (!crtc->config.ips_enabled) |
|
- | 3443 | return; |
|
- | 3444 | ||
- | 3445 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
|
- | 3446 | * We guarantee that the plane is enabled by calling intel_enable_ips |
|
- | 3447 | * only after intel_enable_plane. And intel_enable_plane already waits |
|
- | 3448 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
|
- | 3449 | assert_plane_enabled(dev_priv, crtc->plane); |
|
- | 3450 | if (IS_BROADWELL(crtc->base.dev)) { |
|
- | 3451 | mutex_lock(&dev_priv->rps.hw_lock); |
|
- | 3452 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
|
- | 3453 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 3454 | /* Quoting Art Runyan: "its not safe to expect any particular |
|
- | 3455 | * value in IPS_CTL bit 31 after enabling IPS through the |
|
- | 3456 | * mailbox." Moreover, the mailbox may return a bogus state, |
|
- | 3457 | * so we need to just enable it and continue on. |
|
- | 3458 | */ |
|
- | 3459 | } else { |
|
- | 3460 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
|
- | 3461 | /* The bit only becomes 1 in the next vblank, so this wait here |
|
- | 3462 | * is essentially intel_wait_for_vblank. If we don't have this |
|
- | 3463 | * and don't wait for vblanks until the end of crtc_enable, then |
|
- | 3464 | * the HW state readout code will complain that the expected |
|
- | 3465 | * IPS_CTL value is not the one we read. */ |
|
- | 3466 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
|
- | 3467 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
|
- | 3468 | } |
|
- | 3469 | } |
|
- | 3470 | ||
- | 3471 | void hsw_disable_ips(struct intel_crtc *crtc) |
|
- | 3472 | { |
|
- | 3473 | struct drm_device *dev = crtc->base.dev; |
|
- | 3474 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3475 | ||
- | 3476 | if (!crtc->config.ips_enabled) |
|
- | 3477 | return; |
|
- | 3478 | ||
- | 3479 | assert_plane_enabled(dev_priv, crtc->plane); |
|
- | 3480 | if (IS_BROADWELL(crtc->base.dev)) { |
|
- | 3481 | mutex_lock(&dev_priv->rps.hw_lock); |
|
- | 3482 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
|
- | 3483 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 3484 | } else { |
|
- | 3485 | I915_WRITE(IPS_CTL, 0); |
|
- | 3486 | POSTING_READ(IPS_CTL); |
|
- | 3487 | } |
|
- | 3488 | ||
- | 3489 | /* We need to wait for a vblank before we can disable the plane. */ |
|
- | 3490 | intel_wait_for_vblank(dev, crtc->pipe); |
|
- | 3491 | } |
|
- | 3492 | ||
- | 3493 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
|
- | 3494 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
|
- | 3495 | { |
|
- | 3496 | struct drm_device *dev = crtc->dev; |
|
- | 3497 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3499 | enum pipe pipe = intel_crtc->pipe; |
|
- | 3500 | int palreg = PALETTE(pipe); |
|
- | 3501 | int i; |
|
- | 3502 | bool reenable_ips = false; |
|
- | 3503 | ||
- | 3504 | /* The clocks have to be on to load the palette. */ |
|
- | 3505 | if (!crtc->enabled || !intel_crtc->active) |
|
- | 3506 | return; |
|
- | 3507 | ||
- | 3508 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
|
- | 3509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
|
- | 3510 | assert_dsi_pll_enabled(dev_priv); |
|
- | 3511 | else |
|
- | 3512 | assert_pll_enabled(dev_priv, pipe); |
|
- | 3513 | } |
|
- | 3514 | ||
- | 3515 | /* use legacy palette for Ironlake */ |
|
- | 3516 | if (HAS_PCH_SPLIT(dev)) |
|
- | 3517 | palreg = LGC_PALETTE(pipe); |
|
- | 3518 | ||
- | 3519 | /* Workaround : Do not read or write the pipe palette/gamma data while |
|
- | 3520 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
|
- | 3521 | */ |
|
- | 3522 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
|
- | 3523 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
|
- | 3524 | GAMMA_MODE_MODE_SPLIT)) { |
|
- | 3525 | hsw_disable_ips(intel_crtc); |
|
- | 3526 | reenable_ips = true; |
|
- | 3527 | } |
|
- | 3528 | ||
- | 3529 | for (i = 0; i < 256; i++) { |
|
- | 3530 | I915_WRITE(palreg + 4 * i, |
|
- | 3531 | (intel_crtc->lut_r[i] << 16) | |
|
- | 3532 | (intel_crtc->lut_g[i] << 8) | |
|
- | 3533 | intel_crtc->lut_b[i]); |
|
- | 3534 | } |
|
- | 3535 | ||
- | 3536 | if (reenable_ips) |
|
- | 3537 | hsw_enable_ips(intel_crtc); |
|
- | 3538 | } |
|
3307 | 3539 | ||
3308 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3540 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3309 | { |
3541 | { |
3310 | struct drm_device *dev = crtc->dev; |
3542 | struct drm_device *dev = crtc->dev; |
3311 | struct drm_i915_private *dev_priv = dev->dev_private; |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 3322... | Line 3554... | ||
3322 | intel_crtc->active = true; |
3554 | intel_crtc->active = true; |
Line 3323... | Line 3555... | ||
3323 | 3555 | ||
3324 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3556 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
Line 3325... | Line -... | ||
3325 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
- | |
3326 | - | ||
3327 | intel_update_watermarks(dev); |
3557 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3328 | 3558 | ||
3329 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3559 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Line 3330... | Line 3560... | ||
3330 | if (encoder->pre_enable) |
3560 | if (encoder->pre_enable) |
Line 3346... | Line 3576... | ||
3346 | * On ILK+ LUT must be loaded before the pipe is running but with |
3576 | * On ILK+ LUT must be loaded before the pipe is running but with |
3347 | * clocks enabled |
3577 | * clocks enabled |
3348 | */ |
3578 | */ |
3349 | intel_crtc_load_lut(crtc); |
3579 | intel_crtc_load_lut(crtc); |
Line -... | Line 3580... | ||
- | 3580 | ||
3350 | 3581 | intel_update_watermarks(crtc); |
|
3351 | intel_enable_pipe(dev_priv, pipe, |
3582 | intel_enable_pipe(dev_priv, pipe, |
3352 | intel_crtc->config.has_pch_encoder); |
3583 | intel_crtc->config.has_pch_encoder, false); |
3353 | intel_enable_plane(dev_priv, plane, pipe); |
3584 | intel_enable_primary_plane(dev_priv, plane, pipe); |
3354 | intel_enable_planes(crtc); |
3585 | intel_enable_planes(crtc); |
Line 3355... | Line 3586... | ||
3355 | intel_crtc_update_cursor(crtc, true); |
3586 | intel_crtc_update_cursor(crtc, true); |
3356 | 3587 | ||
Line 3382... | Line 3613... | ||
3382 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3613 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3383 | { |
3614 | { |
3384 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3615 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3385 | } |
3616 | } |
Line 3386... | Line 3617... | ||
3386 | 3617 | ||
3387 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3618 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
- | 3619 | { |
|
3388 | { |
3620 | struct drm_device *dev = crtc->dev; |
- | 3621 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3623 | int pipe = intel_crtc->pipe; |
|
Line -... | Line 3624... | ||
- | 3624 | int plane = intel_crtc->plane; |
|
3389 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3625 | |
3390 | 3626 | intel_enable_primary_plane(dev_priv, plane, pipe); |
|
Line 3391... | Line -... | ||
3391 | if (!crtc->config.ips_enabled) |
- | |
3392 | return; |
- | |
3393 | 3627 | intel_enable_planes(crtc); |
|
- | 3628 | intel_crtc_update_cursor(crtc, true); |
|
3394 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3629 | |
3395 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3630 | hsw_enable_ips(intel_crtc); |
3396 | * only after intel_enable_plane. And intel_enable_plane already waits |
3631 | |
3397 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3632 | mutex_lock(&dev->struct_mutex); |
Line 3398... | Line 3633... | ||
3398 | assert_plane_enabled(dev_priv, crtc->plane); |
3633 | intel_update_fbc(dev); |
3399 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3634 | mutex_unlock(&dev->struct_mutex); |
3400 | } |
3635 | } |
3401 | 3636 | ||
- | 3637 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) |
|
- | 3638 | { |
|
- | 3639 | struct drm_device *dev = crtc->dev; |
|
Line -... | Line 3640... | ||
- | 3640 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3642 | int pipe = intel_crtc->pipe; |
|
- | 3643 | int plane = intel_crtc->plane; |
|
3402 | static void hsw_disable_ips(struct intel_crtc *crtc) |
3644 | |
- | 3645 | // intel_crtc_wait_for_pending_flips(crtc); |
|
- | 3646 | // drm_vblank_off(dev, pipe); |
|
- | 3647 | ||
- | 3648 | /* FBC must be disabled before disabling the plane on HSW. */ |
|
- | 3649 | if (dev_priv->fbc.plane == plane) |
|
- | 3650 | intel_disable_fbc(dev); |
|
- | 3651 | ||
- | 3652 | hsw_disable_ips(intel_crtc); |
|
- | 3653 | ||
- | 3654 | intel_crtc_update_cursor(crtc, false); |
|
- | 3655 | intel_disable_planes(crtc); |
|
- | 3656 | intel_disable_primary_plane(dev_priv, plane, pipe); |
|
- | 3657 | } |
|
- | 3658 | ||
- | 3659 | /* |
|
- | 3660 | * This implements the workaround described in the "notes" section of the mode |
|
- | 3661 | * set sequence documentation. When going from no pipes or single pipe to |
|
- | 3662 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
|
- | 3663 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
|
- | 3664 | */ |
|
- | 3665 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
|
- | 3666 | { |
|
- | 3667 | struct drm_device *dev = crtc->base.dev; |
|
- | 3668 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
|
- | 3669 | ||
- | 3670 | /* We want to get the other_active_crtc only if there's only 1 other |
|
- | 3671 | * active crtc. */ |
|
3403 | { |
3672 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { |
Line 3404... | Line 3673... | ||
3404 | struct drm_device *dev = crtc->base.dev; |
3673 | if (!crtc_it->active || crtc_it == crtc) |
- | 3674 | continue; |
|
3405 | struct drm_i915_private *dev_priv = dev->dev_private; |
3675 | |
- | 3676 | if (other_active_crtc) |
|
Line 3406... | Line 3677... | ||
3406 | 3677 | return; |
|
3407 | if (!crtc->config.ips_enabled) |
3678 | |
3408 | return; |
3679 | other_active_crtc = crtc_it; |
Line 3409... | Line 3680... | ||
3409 | 3680 | } |
|
3410 | assert_plane_enabled(dev_priv, crtc->plane); |
3681 | if (!other_active_crtc) |
3411 | I915_WRITE(IPS_CTL, 0); |
3682 | return; |
3412 | 3683 | ||
3413 | /* We need to wait for a vblank before we can disable the plane. */ |
3684 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3414 | intel_wait_for_vblank(dev, crtc->pipe); |
3685 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3415 | } |
3686 | } |
3416 | - | ||
Line 3417... | Line 3687... | ||
3417 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3687 | |
Line 3418... | Line 3688... | ||
3418 | { |
3688 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3419 | struct drm_device *dev = crtc->dev; |
3689 | { |
Line 3432... | Line 3702... | ||
3432 | 3702 | ||
3433 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3703 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3434 | if (intel_crtc->config.has_pch_encoder) |
3704 | if (intel_crtc->config.has_pch_encoder) |
Line 3435... | Line -... | ||
3435 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
- | |
3436 | - | ||
3437 | intel_update_watermarks(dev); |
3705 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3438 | 3706 | ||
Line 3439... | Line 3707... | ||
3439 | if (intel_crtc->config.has_pch_encoder) |
3707 | if (intel_crtc->config.has_pch_encoder) |
3440 | dev_priv->display.fdi_link_train(crtc); |
3708 | dev_priv->display.fdi_link_train(crtc); |
Line 3454... | Line 3722... | ||
3454 | intel_crtc_load_lut(crtc); |
3722 | intel_crtc_load_lut(crtc); |
Line 3455... | Line 3723... | ||
3455 | 3723 | ||
3456 | intel_ddi_set_pipe_settings(crtc); |
3724 | intel_ddi_set_pipe_settings(crtc); |
Line -... | Line 3725... | ||
- | 3725 | intel_ddi_enable_transcoder_func(crtc); |
|
3457 | intel_ddi_enable_transcoder_func(crtc); |
3726 | |
3458 | 3727 | intel_update_watermarks(crtc); |
|
3459 | intel_enable_pipe(dev_priv, pipe, |
- | |
3460 | intel_crtc->config.has_pch_encoder); |
- | |
3461 | intel_enable_plane(dev_priv, plane, pipe); |
- | |
3462 | intel_enable_planes(crtc); |
- | |
3463 | intel_crtc_update_cursor(crtc, true); |
- | |
Line 3464... | Line 3728... | ||
3464 | 3728 | intel_enable_pipe(dev_priv, pipe, |
|
3465 | hsw_enable_ips(intel_crtc); |
3729 | intel_crtc->config.has_pch_encoder, false); |
Line 3466... | Line -... | ||
3466 | - | ||
3467 | if (intel_crtc->config.has_pch_encoder) |
- | |
3468 | lpt_pch_enable(crtc); |
- | |
3469 | - | ||
3470 | mutex_lock(&dev->struct_mutex); |
3730 | |
3471 | intel_update_fbc(dev); |
3731 | if (intel_crtc->config.has_pch_encoder) |
- | 3732 | lpt_pch_enable(crtc); |
|
- | 3733 | ||
- | 3734 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
- | 3735 | encoder->enable(encoder); |
|
- | 3736 | intel_opregion_notify_encoder(encoder, true); |
|
- | 3737 | } |
|
- | 3738 | ||
Line 3472... | Line 3739... | ||
3472 | mutex_unlock(&dev->struct_mutex); |
3739 | /* If we change the relative order between pipe/planes enabling, we need |
3473 | 3740 | * to change the workaround. */ |
|
3474 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3741 | haswell_mode_set_planes_workaround(intel_crtc); |
3475 | encoder->enable(encoder); |
3742 | haswell_crtc_enable_planes(crtc); |
Line 3523... | Line 3790... | ||
3523 | if (dev_priv->fbc.plane == plane) |
3790 | if (dev_priv->fbc.plane == plane) |
3524 | intel_disable_fbc(dev); |
3791 | intel_disable_fbc(dev); |
Line 3525... | Line 3792... | ||
3525 | 3792 | ||
3526 | intel_crtc_update_cursor(crtc, false); |
3793 | intel_crtc_update_cursor(crtc, false); |
3527 | intel_disable_planes(crtc); |
3794 | intel_disable_planes(crtc); |
Line 3528... | Line 3795... | ||
3528 | intel_disable_plane(dev_priv, plane, pipe); |
3795 | intel_disable_primary_plane(dev_priv, plane, pipe); |
3529 | 3796 | ||
Line 3530... | Line 3797... | ||
3530 | if (intel_crtc->config.has_pch_encoder) |
3797 | if (intel_crtc->config.has_pch_encoder) |
Line 3564... | Line 3831... | ||
3564 | 3831 | ||
3565 | ironlake_fdi_pll_disable(intel_crtc); |
3832 | ironlake_fdi_pll_disable(intel_crtc); |
Line 3566... | Line 3833... | ||
3566 | } |
3833 | } |
3567 | 3834 | ||
Line 3568... | Line 3835... | ||
3568 | intel_crtc->active = false; |
3835 | intel_crtc->active = false; |
3569 | intel_update_watermarks(dev); |
3836 | intel_update_watermarks(crtc); |
3570 | 3837 | ||
3571 | mutex_lock(&dev->struct_mutex); |
3838 | mutex_lock(&dev->struct_mutex); |
Line 3578... | Line 3845... | ||
3578 | struct drm_device *dev = crtc->dev; |
3845 | struct drm_device *dev = crtc->dev; |
3579 | struct drm_i915_private *dev_priv = dev->dev_private; |
3846 | struct drm_i915_private *dev_priv = dev->dev_private; |
3580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3581 | struct intel_encoder *encoder; |
3848 | struct intel_encoder *encoder; |
3582 | int pipe = intel_crtc->pipe; |
3849 | int pipe = intel_crtc->pipe; |
3583 | int plane = intel_crtc->plane; |
- | |
3584 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3850 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Line 3585... | Line 3851... | ||
3585 | 3851 | ||
3586 | if (!intel_crtc->active) |
3852 | if (!intel_crtc->active) |
Line 3587... | Line -... | ||
3587 | return; |
- | |
3588 | - | ||
3589 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | |
3590 | encoder->disable(encoder); |
- | |
3591 | - | ||
3592 | - | ||
3593 | /* FBC must be disabled before disabling the plane on HSW. */ |
3853 | return; |
Line 3594... | Line 3854... | ||
3594 | if (dev_priv->fbc.plane == plane) |
3854 | |
3595 | intel_disable_fbc(dev); |
- | |
3596 | 3855 | haswell_crtc_disable_planes(crtc); |
|
3597 | hsw_disable_ips(intel_crtc); |
3856 | |
3598 | - | ||
- | 3857 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
Line 3599... | Line 3858... | ||
3599 | intel_crtc_update_cursor(crtc, false); |
3858 | intel_opregion_notify_encoder(encoder, false); |
3600 | intel_disable_planes(crtc); |
3859 | encoder->disable(encoder); |
3601 | intel_disable_plane(dev_priv, plane, pipe); |
3860 | } |
Line 3619... | Line 3878... | ||
3619 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3878 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3620 | intel_ddi_fdi_disable(crtc); |
3879 | intel_ddi_fdi_disable(crtc); |
3621 | } |
3880 | } |
Line 3622... | Line 3881... | ||
3622 | 3881 | ||
3623 | intel_crtc->active = false; |
3882 | intel_crtc->active = false; |
Line 3624... | Line 3883... | ||
3624 | intel_update_watermarks(dev); |
3883 | intel_update_watermarks(crtc); |
3625 | 3884 | ||
3626 | mutex_lock(&dev->struct_mutex); |
3885 | mutex_lock(&dev->struct_mutex); |
3627 | intel_update_fbc(dev); |
3886 | intel_update_fbc(dev); |
Line 3703... | Line 3962... | ||
3703 | /* Border color in case we don't scale up to the full screen. Black by |
3962 | /* Border color in case we don't scale up to the full screen. Black by |
3704 | * default, change to something else for debugging. */ |
3963 | * default, change to something else for debugging. */ |
3705 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3964 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3706 | } |
3965 | } |
Line -... | Line 3966... | ||
- | 3966 | ||
- | 3967 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
|
- | 3968 | { |
|
- | 3969 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
|
- | 3970 | ||
- | 3971 | /* Obtain SKU information */ |
|
- | 3972 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 3973 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
|
- | 3974 | CCK_FUSE_HPLL_FREQ_MASK; |
|
- | 3975 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 3976 | ||
- | 3977 | return vco_freq[hpll_freq]; |
|
- | 3978 | } |
|
- | 3979 | ||
- | 3980 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
|
- | 3981 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
|
- | 3982 | { |
|
- | 3983 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3984 | u32 val, cmd; |
|
- | 3985 | ||
- | 3986 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
|
- | 3987 | cmd = 2; |
|
- | 3988 | else if (cdclk == 266) |
|
- | 3989 | cmd = 1; |
|
- | 3990 | else |
|
- | 3991 | cmd = 0; |
|
- | 3992 | ||
- | 3993 | mutex_lock(&dev_priv->rps.hw_lock); |
|
- | 3994 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
|
- | 3995 | val &= ~DSPFREQGUAR_MASK; |
|
- | 3996 | val |= (cmd << DSPFREQGUAR_SHIFT); |
|
- | 3997 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
|
- | 3998 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
|
- | 3999 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
|
- | 4000 | 50)) { |
|
- | 4001 | DRM_ERROR("timed out waiting for CDclk change\n"); |
|
- | 4002 | } |
|
- | 4003 | mutex_unlock(&dev_priv->rps.hw_lock); |
|
- | 4004 | ||
- | 4005 | if (cdclk == 400) { |
|
- | 4006 | u32 divider, vco; |
|
- | 4007 | ||
- | 4008 | vco = valleyview_get_vco(dev_priv); |
|
- | 4009 | divider = ((vco << 1) / cdclk) - 1; |
|
- | 4010 | ||
- | 4011 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 4012 | /* adjust cdclk divider */ |
|
- | 4013 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
|
- | 4014 | val &= ~0xf; |
|
- | 4015 | val |= divider; |
|
- | 4016 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
|
- | 4017 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 4018 | } |
|
- | 4019 | ||
- | 4020 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 4021 | /* adjust self-refresh exit latency value */ |
|
- | 4022 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
|
- | 4023 | val &= ~0x7f; |
|
- | 4024 | ||
- | 4025 | /* |
|
- | 4026 | * For high bandwidth configs, we set a higher latency in the bunit |
|
- | 4027 | * so that the core display fetch happens in time to avoid underruns. |
|
- | 4028 | */ |
|
- | 4029 | if (cdclk == 400) |
|
- | 4030 | val |= 4500 / 250; /* 4.5 usec */ |
|
- | 4031 | else |
|
- | 4032 | val |= 3000 / 250; /* 3.0 usec */ |
|
- | 4033 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
|
- | 4034 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 4035 | ||
- | 4036 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ |
|
- | 4037 | intel_i2c_reset(dev); |
|
- | 4038 | } |
|
- | 4039 | ||
- | 4040 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
|
- | 4041 | { |
|
- | 4042 | int cur_cdclk, vco; |
|
- | 4043 | int divider; |
|
- | 4044 | ||
- | 4045 | vco = valleyview_get_vco(dev_priv); |
|
- | 4046 | ||
- | 4047 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 4048 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
|
- | 4049 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 4050 | ||
- | 4051 | divider &= 0xf; |
|
- | 4052 | ||
- | 4053 | cur_cdclk = (vco << 1) / (divider + 1); |
|
- | 4054 | ||
- | 4055 | return cur_cdclk; |
|
- | 4056 | } |
|
- | 4057 | ||
- | 4058 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
|
- | 4059 | int max_pixclk) |
|
- | 4060 | { |
|
- | 4061 | int cur_cdclk; |
|
- | 4062 | ||
- | 4063 | cur_cdclk = valleyview_cur_cdclk(dev_priv); |
|
- | 4064 | ||
- | 4065 | /* |
|
- | 4066 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
|
- | 4067 | * 200MHz |
|
- | 4068 | * 267MHz |
|
- | 4069 | * 320MHz |
|
- | 4070 | * 400MHz |
|
- | 4071 | * So we check to see whether we're above 90% of the lower bin and |
|
- | 4072 | * adjust if needed. |
|
- | 4073 | */ |
|
- | 4074 | if (max_pixclk > 288000) { |
|
- | 4075 | return 400; |
|
- | 4076 | } else if (max_pixclk > 240000) { |
|
- | 4077 | return 320; |
|
- | 4078 | } else |
|
- | 4079 | return 266; |
|
- | 4080 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
|
- | 4081 | } |
|
- | 4082 | ||
- | 4083 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, |
|
- | 4084 | unsigned modeset_pipes, |
|
- | 4085 | struct intel_crtc_config *pipe_config) |
|
- | 4086 | { |
|
- | 4087 | struct drm_device *dev = dev_priv->dev; |
|
- | 4088 | struct intel_crtc *intel_crtc; |
|
- | 4089 | int max_pixclk = 0; |
|
- | 4090 | ||
- | 4091 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
|
- | 4092 | base.head) { |
|
- | 4093 | if (modeset_pipes & (1 << intel_crtc->pipe)) |
|
- | 4094 | max_pixclk = max(max_pixclk, |
|
- | 4095 | pipe_config->adjusted_mode.crtc_clock); |
|
- | 4096 | else if (intel_crtc->base.enabled) |
|
- | 4097 | max_pixclk = max(max_pixclk, |
|
- | 4098 | intel_crtc->config.adjusted_mode.crtc_clock); |
|
- | 4099 | } |
|
- | 4100 | ||
- | 4101 | return max_pixclk; |
|
- | 4102 | } |
|
- | 4103 | ||
- | 4104 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
|
- | 4105 | unsigned *prepare_pipes, |
|
- | 4106 | unsigned modeset_pipes, |
|
- | 4107 | struct intel_crtc_config *pipe_config) |
|
- | 4108 | { |
|
- | 4109 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4110 | struct intel_crtc *intel_crtc; |
|
- | 4111 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, |
|
- | 4112 | pipe_config); |
|
- | 4113 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
|
- | 4114 | ||
- | 4115 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) |
|
- | 4116 | return; |
|
- | 4117 | ||
- | 4118 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
|
- | 4119 | base.head) |
|
- | 4120 | if (intel_crtc->base.enabled) |
|
- | 4121 | *prepare_pipes |= (1 << intel_crtc->pipe); |
|
- | 4122 | } |
|
- | 4123 | ||
- | 4124 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
|
- | 4125 | { |
|
- | 4126 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4127 | int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL); |
|
- | 4128 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
|
- | 4129 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
|
- | 4130 | ||
- | 4131 | if (req_cdclk != cur_cdclk) |
|
- | 4132 | valleyview_set_cdclk(dev, req_cdclk); |
|
- | 4133 | } |
|
3707 | 4134 | ||
3708 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4135 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3709 | { |
4136 | { |
3710 | struct drm_device *dev = crtc->dev; |
4137 | struct drm_device *dev = crtc->dev; |
3711 | struct drm_i915_private *dev_priv = dev->dev_private; |
4138 | struct drm_i915_private *dev_priv = dev->dev_private; |
3712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3713 | struct intel_encoder *encoder; |
4140 | struct intel_encoder *encoder; |
3714 | int pipe = intel_crtc->pipe; |
4141 | int pipe = intel_crtc->pipe; |
- | 4142 | int plane = intel_crtc->plane; |
|
Line 3715... | Line 4143... | ||
3715 | int plane = intel_crtc->plane; |
4143 | bool is_dsi; |
Line 3716... | Line 4144... | ||
3716 | 4144 | ||
3717 | WARN_ON(!crtc->enabled); |
4145 | WARN_ON(!crtc->enabled); |
Line 3718... | Line 4146... | ||
3718 | 4146 | ||
3719 | if (intel_crtc->active) |
- | |
Line 3720... | Line 4147... | ||
3720 | return; |
4147 | if (intel_crtc->active) |
3721 | 4148 | return; |
|
3722 | intel_crtc->active = true; |
4149 | |
Line -... | Line 4150... | ||
- | 4150 | intel_crtc->active = true; |
|
- | 4151 | ||
- | 4152 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
3723 | intel_update_watermarks(dev); |
4153 | if (encoder->pre_pll_enable) |
Line 3724... | Line 4154... | ||
3724 | 4154 | encoder->pre_pll_enable(encoder); |
|
3725 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4155 | |
3726 | if (encoder->pre_pll_enable) |
4156 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
Line 3727... | Line 4157... | ||
3727 | encoder->pre_pll_enable(encoder); |
4157 | |
Line 3728... | Line 4158... | ||
3728 | 4158 | if (!is_dsi) |
|
Line -... | Line 4159... | ||
- | 4159 | vlv_enable_pll(intel_crtc); |
|
3729 | vlv_enable_pll(intel_crtc); |
4160 | |
3730 | 4161 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
3731 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4162 | if (encoder->pre_enable) |
3732 | if (encoder->pre_enable) |
4163 | encoder->pre_enable(encoder); |
Line 3733... | Line 4164... | ||
3733 | encoder->pre_enable(encoder); |
4164 | |
Line 3760... | Line 4191... | ||
3760 | 4191 | ||
3761 | if (intel_crtc->active) |
4192 | if (intel_crtc->active) |
Line 3762... | Line 4193... | ||
3762 | return; |
4193 | return; |
3763 | - | ||
Line 3764... | Line 4194... | ||
3764 | intel_crtc->active = true; |
4194 | |
3765 | intel_update_watermarks(dev); |
4195 | intel_crtc->active = true; |
3766 | 4196 | ||
Line 3772... | Line 4202... | ||
3772 | 4202 | ||
Line 3773... | Line 4203... | ||
3773 | i9xx_pfit_enable(intel_crtc); |
4203 | i9xx_pfit_enable(intel_crtc); |
Line -... | Line 4204... | ||
- | 4204 | ||
3774 | 4205 | intel_crtc_load_lut(crtc); |
|
3775 | intel_crtc_load_lut(crtc); |
4206 | |
3776 | 4207 | intel_update_watermarks(crtc); |
|
3777 | intel_enable_pipe(dev_priv, pipe, false); |
4208 | intel_enable_pipe(dev_priv, pipe, false, false); |
3778 | intel_enable_plane(dev_priv, plane, pipe); |
4209 | intel_enable_primary_plane(dev_priv, plane, pipe); |
3779 | intel_enable_planes(crtc); |
4210 | intel_enable_planes(crtc); |
3780 | /* The fixup needs to happen before cursor is enabled */ |
4211 | /* The fixup needs to happen before cursor is enabled */ |
Line 3829... | Line 4260... | ||
3829 | intel_disable_fbc(dev); |
4260 | intel_disable_fbc(dev); |
Line 3830... | Line 4261... | ||
3830 | 4261 | ||
3831 | intel_crtc_dpms_overlay(intel_crtc, false); |
4262 | intel_crtc_dpms_overlay(intel_crtc, false); |
3832 | intel_crtc_update_cursor(crtc, false); |
4263 | intel_crtc_update_cursor(crtc, false); |
3833 | intel_disable_planes(crtc); |
4264 | intel_disable_planes(crtc); |
Line 3834... | Line 4265... | ||
3834 | intel_disable_plane(dev_priv, plane, pipe); |
4265 | intel_disable_primary_plane(dev_priv, plane, pipe); |
Line 3835... | Line 4266... | ||
3835 | 4266 | ||
Line 3836... | Line 4267... | ||
3836 | intel_disable_pipe(dev_priv, pipe); |
4267 | intel_disable_pipe(dev_priv, pipe); |
3837 | 4268 | ||
3838 | i9xx_pfit_disable(intel_crtc); |
4269 | i9xx_pfit_disable(intel_crtc); |
Line 3839... | Line 4270... | ||
3839 | 4270 | ||
3840 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4271 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3841 | if (encoder->post_disable) |
4272 | if (encoder->post_disable) |
3842 | encoder->post_disable(encoder); |
4273 | encoder->post_disable(encoder); |
Line 3843... | Line 4274... | ||
3843 | 4274 | ||
- | 4275 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
|
- | 4276 | vlv_disable_pll(dev_priv, pipe); |
|
3844 | if (IS_VALLEYVIEW(dev)) |
4277 | else if (!IS_VALLEYVIEW(dev)) |
3845 | vlv_disable_pll(dev_priv, pipe); |
- | |
3846 | else |
4278 | i9xx_disable_pll(dev_priv, pipe); |
Line 3847... | Line 4279... | ||
3847 | i9xx_disable_pll(dev_priv, pipe); |
4279 | |
3848 | 4280 | intel_crtc->active = false; |
|
3849 | intel_crtc->active = false; |
4281 | intel_update_watermarks(crtc); |
Line 3924... | Line 4356... | ||
3924 | intel_crtc->eld_vld = false; |
4356 | intel_crtc->eld_vld = false; |
3925 | intel_crtc_update_sarea(crtc, false); |
4357 | intel_crtc_update_sarea(crtc, false); |
3926 | dev_priv->display.off(crtc); |
4358 | dev_priv->display.off(crtc); |
Line 3927... | Line 4359... | ||
3927 | 4359 | ||
- | 4360 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
|
3928 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
4361 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
Line 3929... | Line 4362... | ||
3929 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
4362 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3930 | 4363 | ||
3931 | if (crtc->fb) { |
4364 | if (crtc->fb) { |
Line 4051... | Line 4484... | ||
4051 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4484 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4052 | pipe_name(pipe), pipe_config->fdi_lanes); |
4485 | pipe_name(pipe), pipe_config->fdi_lanes); |
4053 | return false; |
4486 | return false; |
4054 | } |
4487 | } |
Line 4055... | Line 4488... | ||
4055 | 4488 | ||
4056 | if (IS_HASWELL(dev)) { |
4489 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
4057 | if (pipe_config->fdi_lanes > 2) { |
4490 | if (pipe_config->fdi_lanes > 2) { |
4058 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4491 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4059 | pipe_config->fdi_lanes); |
4492 | pipe_config->fdi_lanes); |
4060 | return false; |
4493 | return false; |
Line 4113... | Line 4546... | ||
4113 | * Hence the bw of each lane in terms of the mode signal |
4546 | * Hence the bw of each lane in terms of the mode signal |
4114 | * is: |
4547 | * is: |
4115 | */ |
4548 | */ |
4116 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4549 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
Line 4117... | Line 4550... | ||
4117 | 4550 | ||
4118 | fdi_dotclock = adjusted_mode->clock; |
- | |
Line 4119... | Line 4551... | ||
4119 | fdi_dotclock /= pipe_config->pixel_multiplier; |
4551 | fdi_dotclock = adjusted_mode->crtc_clock; |
4120 | 4552 | ||
Line 4121... | Line 4553... | ||
4121 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4553 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
Line 4156... | Line 4588... | ||
4156 | struct intel_crtc_config *pipe_config) |
4588 | struct intel_crtc_config *pipe_config) |
4157 | { |
4589 | { |
4158 | struct drm_device *dev = crtc->base.dev; |
4590 | struct drm_device *dev = crtc->base.dev; |
4159 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4591 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Line -... | Line 4592... | ||
- | 4592 | ||
4160 | 4593 | /* FIXME should check pixel clock limits on all platforms */ |
|
- | 4594 | if (INTEL_INFO(dev)->gen < 4) { |
|
- | 4595 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4596 | int clock_limit = |
|
- | 4597 | dev_priv->display.get_display_clock_speed(dev); |
|
- | 4598 | ||
- | 4599 | /* |
|
- | 4600 | * Enable pixel doubling when the dot clock |
|
- | 4601 | * is > 90% of the (display) core speed. |
|
4161 | if (HAS_PCH_SPLIT(dev)) { |
4602 | * |
- | 4603 | * GDG double wide on either pipe, |
|
- | 4604 | * otherwise pipe A only. |
|
- | 4605 | */ |
|
- | 4606 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
|
- | 4607 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
|
4162 | /* FDI link clock is fixed at 2.7G */ |
4608 | clock_limit *= 2; |
- | 4609 | pipe_config->double_wide = true; |
|
- | 4610 | } |
|
4163 | if (pipe_config->requested_mode.clock * 3 |
4611 | |
4164 | > IRONLAKE_FDI_FREQ * 4) |
4612 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
4165 | return -EINVAL; |
4613 | return -EINVAL; |
Line -... | Line 4614... | ||
- | 4614 | } |
|
- | 4615 | ||
- | 4616 | /* |
|
- | 4617 | * Pipe horizontal size must be even in: |
|
- | 4618 | * - DVO ganged mode |
|
- | 4619 | * - LVDS dual channel mode |
|
- | 4620 | * - Double wide pipe |
|
- | 4621 | */ |
|
- | 4622 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
|
- | 4623 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
|
4166 | } |
4624 | pipe_config->pipe_src_w &= ~1; |
4167 | 4625 | ||
4168 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4626 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4169 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4627 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4170 | */ |
4628 | */ |
Line 4326... | Line 4784... | ||
4326 | return i915_panel_use_ssc != 0; |
4784 | return i915_panel_use_ssc != 0; |
4327 | return dev_priv->vbt.lvds_use_ssc |
4785 | return dev_priv->vbt.lvds_use_ssc |
4328 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4786 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4329 | } |
4787 | } |
Line 4330... | Line -... | ||
4330 | - | ||
4331 | static int vlv_get_refclk(struct drm_crtc *crtc) |
- | |
4332 | { |
- | |
4333 | struct drm_device *dev = crtc->dev; |
- | |
4334 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4335 | int refclk = 27000; /* for DP & HDMI */ |
- | |
4336 | - | ||
4337 | return 100000; /* only one validated so far */ |
- | |
4338 | - | ||
4339 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
- | |
4340 | refclk = 96000; |
- | |
4341 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
- | |
4342 | if (intel_panel_use_ssc(dev_priv)) |
- | |
4343 | refclk = 100000; |
- | |
4344 | else |
- | |
4345 | refclk = 96000; |
- | |
4346 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
- | |
4347 | refclk = 100000; |
- | |
4348 | } |
- | |
4349 | - | ||
4350 | return refclk; |
- | |
4351 | } |
- | |
4352 | 4788 | ||
4353 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4789 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4354 | { |
4790 | { |
4355 | struct drm_device *dev = crtc->dev; |
4791 | struct drm_device *dev = crtc->dev; |
4356 | struct drm_i915_private *dev_priv = dev->dev_private; |
4792 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 4357... | Line 4793... | ||
4357 | int refclk; |
4793 | int refclk; |
4358 | 4794 | ||
4359 | if (IS_VALLEYVIEW(dev)) { |
4795 | if (IS_VALLEYVIEW(dev)) { |
4360 | refclk = vlv_get_refclk(crtc); |
4796 | refclk = 100000; |
4361 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4797 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4362 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4798 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4363 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
- | |
4364 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4799 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4365 | refclk / 1000); |
4800 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
4366 | } else if (!IS_GEN2(dev)) { |
4801 | } else if (!IS_GEN2(dev)) { |
4367 | refclk = 96000; |
4802 | refclk = 96000; |
4368 | } else { |
4803 | } else { |
Line 4413... | Line 4848... | ||
4413 | I915_WRITE(FP1(pipe), fp); |
4848 | I915_WRITE(FP1(pipe), fp); |
4414 | crtc->config.dpll_hw_state.fp1 = fp; |
4849 | crtc->config.dpll_hw_state.fp1 = fp; |
4415 | } |
4850 | } |
4416 | } |
4851 | } |
Line 4417... | Line 4852... | ||
4417 | 4852 | ||
- | 4853 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
|
4418 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4854 | pipe) |
4419 | { |
4855 | { |
Line 4420... | Line 4856... | ||
4420 | u32 reg_val; |
4856 | u32 reg_val; |
4421 | 4857 | ||
4422 | /* |
4858 | /* |
4423 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4859 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4424 | * and set it to a reasonable value instead. |
4860 | * and set it to a reasonable value instead. |
4425 | */ |
4861 | */ |
4426 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4862 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
4427 | reg_val &= 0xffffff00; |
4863 | reg_val &= 0xffffff00; |
Line 4428... | Line 4864... | ||
4428 | reg_val |= 0x00000030; |
4864 | reg_val |= 0x00000030; |
4429 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4865 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
4430 | 4866 | ||
4431 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4867 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Line 4432... | Line 4868... | ||
4432 | reg_val &= 0x8cffffff; |
4868 | reg_val &= 0x8cffffff; |
4433 | reg_val = 0x8c000000; |
4869 | reg_val = 0x8c000000; |
4434 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4870 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Line 4435... | Line 4871... | ||
4435 | 4871 | ||
4436 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4872 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
4437 | reg_val &= 0xffffff00; |
4873 | reg_val &= 0xffffff00; |
4438 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4874 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
4439 | 4875 | ||
Line 4440... | Line 4876... | ||
4440 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4876 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
4441 | reg_val &= 0x00ffffff; |
4877 | reg_val &= 0x00ffffff; |
4442 | reg_val |= 0xb0000000; |
4878 | reg_val |= 0xb0000000; |
Line 4504... | Line 4940... | ||
4504 | 4940 | ||
Line 4505... | Line 4941... | ||
4505 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4941 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4506 | 4942 | ||
4507 | /* PLL B needs special handling */ |
4943 | /* PLL B needs special handling */ |
Line 4508... | Line 4944... | ||
4508 | if (pipe) |
4944 | if (pipe) |
4509 | vlv_pllb_recal_opamp(dev_priv); |
4945 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Line 4510... | Line 4946... | ||
4510 | 4946 | ||
4511 | /* Set up Tx target for periodic Rcomp update */ |
4947 | /* Set up Tx target for periodic Rcomp update */ |
4512 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
4948 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
4513 | 4949 | ||
Line 4514... | Line 4950... | ||
4514 | /* Disable target IRef on PLL */ |
4950 | /* Disable target IRef on PLL */ |
4515 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
4951 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
Line 4516... | Line 4952... | ||
4516 | reg_val &= 0x00ffffff; |
4952 | reg_val &= 0x00ffffff; |
4517 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
4953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
4518 | 4954 | ||
4519 | /* Disable fast lock */ |
4955 | /* Disable fast lock */ |
Line 4529... | Line 4965... | ||
4529 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4965 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4530 | * but we don't support that). |
4966 | * but we don't support that). |
4531 | * Note: don't use the DAC post divider as it seems unstable. |
4967 | * Note: don't use the DAC post divider as it seems unstable. |
4532 | */ |
4968 | */ |
4533 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4969 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4534 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4970 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Line 4535... | Line 4971... | ||
4535 | 4971 | ||
4536 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4972 | mdiv |= DPIO_ENABLE_CALIBRATION; |
Line 4537... | Line 4973... | ||
4537 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
4538 | 4974 | ||
4539 | /* Set HBR and RBR LPF coefficients */ |
4975 | /* Set HBR and RBR LPF coefficients */ |
4540 | if (crtc->config.port_clock == 162000 || |
4976 | if (crtc->config.port_clock == 162000 || |
4541 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4977 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4542 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4978 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4543 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4979 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
4544 | 0x009f0003); |
4980 | 0x009f0003); |
4545 | else |
4981 | else |
Line 4546... | Line 4982... | ||
4546 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4982 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
4547 | 0x00d0000f); |
4983 | 0x00d0000f); |
4548 | 4984 | ||
4549 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4985 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4550 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4986 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4551 | /* Use SSC source */ |
4987 | /* Use SSC source */ |
4552 | if (!pipe) |
4988 | if (!pipe) |
4553 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4554 | 0x0df40000); |
4990 | 0x0df40000); |
4555 | else |
4991 | else |
4556 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4557 | 0x0df70000); |
4993 | 0x0df70000); |
4558 | } else { /* HDMI or VGA */ |
4994 | } else { /* HDMI or VGA */ |
4559 | /* Use bend source */ |
4995 | /* Use bend source */ |
4560 | if (!pipe) |
4996 | if (!pipe) |
4561 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4997 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4562 | 0x0df70000); |
4998 | 0x0df70000); |
4563 | else |
4999 | else |
Line 4564... | Line 5000... | ||
4564 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
5000 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
4565 | 0x0df40000); |
5001 | 0x0df40000); |
4566 | } |
5002 | } |
4567 | 5003 | ||
4568 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
5004 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
4569 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5005 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
Line 4570... | Line 5006... | ||
4570 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
5006 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
Line -... | Line 5007... | ||
- | 5007 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
|
4571 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5008 | coreclk |= 0x01000000; |
- | 5009 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
|
- | 5010 | ||
- | 5011 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
|
4572 | coreclk |= 0x01000000; |
5012 | |
4573 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
5013 | /* |
4574 | 5014 | * Enable DPIO clock input. We should never disable the reference |
|
4575 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
5015 | * clock for pipe B, since VGA hotplug / manual detection depends |
4576 | 5016 | * on it. |
|
Line 4715... | Line 5155... | ||
4715 | struct drm_i915_private *dev_priv = dev->dev_private; |
5155 | struct drm_i915_private *dev_priv = dev->dev_private; |
4716 | enum pipe pipe = intel_crtc->pipe; |
5156 | enum pipe pipe = intel_crtc->pipe; |
4717 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5157 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4718 | struct drm_display_mode *adjusted_mode = |
5158 | struct drm_display_mode *adjusted_mode = |
4719 | &intel_crtc->config.adjusted_mode; |
5159 | &intel_crtc->config.adjusted_mode; |
4720 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
- | |
4721 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5160 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
Line 4722... | Line 5161... | ||
4722 | 5161 | ||
4723 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5162 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4724 | * the hw state checker will get angry at the mismatch. */ |
5163 | * the hw state checker will get angry at the mismatch. */ |
Line 4768... | Line 5207... | ||
4768 | 5207 | ||
4769 | /* pipesrc controls the size that is scaled from, which should |
5208 | /* pipesrc controls the size that is scaled from, which should |
4770 | * always be the user's requested size. |
5209 | * always be the user's requested size. |
4771 | */ |
5210 | */ |
- | 5211 | I915_WRITE(PIPESRC(pipe), |
|
4772 | I915_WRITE(PIPESRC(pipe), |
5212 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
4773 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
5213 | (intel_crtc->config.pipe_src_h - 1)); |
Line 4774... | Line 5214... | ||
4774 | } |
5214 | } |
4775 | 5215 | ||
4776 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5216 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
Line 4806... | Line 5246... | ||
4806 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
5246 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
4807 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
5247 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
4808 | } |
5248 | } |
Line 4809... | Line 5249... | ||
4809 | 5249 | ||
4810 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
5250 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
4811 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
5251 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
- | 5252 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
|
- | 5253 | ||
- | 5254 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
|
4812 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
5255 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
Line 4813... | Line 5256... | ||
4813 | } |
5256 | } |
4814 | 5257 | ||
4815 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5258 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
Line 4827... | Line 5270... | ||
4827 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
5270 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
4828 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
5271 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
Line 4829... | Line 5272... | ||
4829 | 5272 | ||
Line 4830... | Line 5273... | ||
4830 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
5273 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
4831 | 5274 | ||
4832 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
5275 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
Line 4833... | Line 5276... | ||
4833 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5276 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4834 | } |
5277 | } |
Line 4843... | Line 5286... | ||
4843 | 5286 | ||
4844 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5287 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4845 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
5288 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
Line 4846... | Line -... | ||
4846 | pipeconf |= PIPECONF_ENABLE; |
- | |
4847 | - | ||
4848 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
- | |
4849 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
- | |
4850 | * core speed. |
- | |
4851 | * |
- | |
4852 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
- | |
4853 | * pipe == 0 check? |
5289 | pipeconf |= PIPECONF_ENABLE; |
4854 | */ |
- | |
4855 | if (intel_crtc->config.requested_mode.clock > |
5290 | |
4856 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
- | |
Line 4857... | Line 5291... | ||
4857 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
5291 | if (intel_crtc->config.double_wide) |
4858 | } |
5292 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4859 | 5293 | ||
4860 | /* only g4x and later have fancy bpc/dither controls */ |
5294 | /* only g4x and later have fancy bpc/dither controls */ |
Line 4907... | Line 5341... | ||
4907 | struct drm_framebuffer *fb) |
5341 | struct drm_framebuffer *fb) |
4908 | { |
5342 | { |
4909 | struct drm_device *dev = crtc->dev; |
5343 | struct drm_device *dev = crtc->dev; |
4910 | struct drm_i915_private *dev_priv = dev->dev_private; |
5344 | struct drm_i915_private *dev_priv = dev->dev_private; |
4911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4912 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
- | |
4913 | int pipe = intel_crtc->pipe; |
5346 | int pipe = intel_crtc->pipe; |
4914 | int plane = intel_crtc->plane; |
5347 | int plane = intel_crtc->plane; |
4915 | int refclk, num_connectors = 0; |
5348 | int refclk, num_connectors = 0; |
4916 | intel_clock_t clock, reduced_clock; |
5349 | intel_clock_t clock, reduced_clock; |
4917 | u32 dspcntr; |
5350 | u32 dspcntr; |
4918 | bool ok, has_reduced_clock = false; |
5351 | bool ok, has_reduced_clock = false; |
4919 | bool is_lvds = false; |
5352 | bool is_lvds = false, is_dsi = false; |
4920 | struct intel_encoder *encoder; |
5353 | struct intel_encoder *encoder; |
4921 | const intel_limit_t *limit; |
5354 | const intel_limit_t *limit; |
4922 | int ret; |
5355 | int ret; |
Line 4923... | Line 5356... | ||
4923 | 5356 | ||
4924 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5357 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4925 | switch (encoder->type) { |
5358 | switch (encoder->type) { |
4926 | case INTEL_OUTPUT_LVDS: |
5359 | case INTEL_OUTPUT_LVDS: |
4927 | is_lvds = true; |
5360 | is_lvds = true; |
- | 5361 | break; |
|
- | 5362 | case INTEL_OUTPUT_DSI: |
|
- | 5363 | is_dsi = true; |
|
4928 | break; |
5364 | break; |
Line 4929... | Line 5365... | ||
4929 | } |
5365 | } |
4930 | 5366 | ||
Line -... | Line 5367... | ||
- | 5367 | num_connectors++; |
|
- | 5368 | } |
|
- | 5369 | ||
- | 5370 | if (is_dsi) |
|
4931 | num_connectors++; |
5371 | goto skip_dpll; |
Line 4932... | Line 5372... | ||
4932 | } |
5372 | |
4933 | 5373 | if (!intel_crtc->config.clock_set) { |
|
4934 | refclk = i9xx_get_refclk(crtc, num_connectors); |
5374 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4935 | 5375 | ||
- | 5376 | /* |
|
4936 | /* |
5377 | * Returns a set of divisors for the desired target clock with |
4937 | * Returns a set of divisors for the desired target clock with the given |
5378 | * the given refclk, or FALSE. The returned values represent |
4938 | * refclk, or FALSE. The returned values represent the clock equation: |
5379 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
4939 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
5380 | * 2) / p1 / p2. |
4940 | */ |
5381 | */ |
4941 | limit = intel_limit(crtc, refclk); |
5382 | limit = intel_limit(crtc, refclk); |
4942 | ok = dev_priv->display.find_dpll(limit, crtc, |
5383 | ok = dev_priv->display.find_dpll(limit, crtc, |
4943 | intel_crtc->config.port_clock, |
5384 | intel_crtc->config.port_clock, |
4944 | refclk, NULL, &clock); |
5385 | refclk, NULL, &clock); |
Line 4945... | Line 5386... | ||
4945 | if (!ok && !intel_crtc->config.clock_set) { |
5386 | if (!ok) { |
4946 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5387 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4947 | return -EINVAL; |
5388 | return -EINVAL; |
4948 | } |
5389 | } |
4949 | 5390 | ||
4950 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5391 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4951 | /* |
5392 | /* |
4952 | * Ensure we match the reduced clock's P to the target clock. |
5393 | * Ensure we match the reduced clock's P to the target |
4953 | * If the clocks don't match, we can't switch the display clock |
5394 | * clock. If the clocks don't match, we can't switch |
4954 | * by using the FP0/FP1. In such case we will disable the LVDS |
5395 | * the display clock by using the FP0/FP1. In such case |
4955 | * downclock feature. |
5396 | * we will disable the LVDS downclock feature. |
4956 | */ |
5397 | */ |
4957 | has_reduced_clock = |
5398 | has_reduced_clock = |
4958 | dev_priv->display.find_dpll(limit, crtc, |
5399 | dev_priv->display.find_dpll(limit, crtc, |
4959 | dev_priv->lvds_downclock, |
- | |
4960 | refclk, &clock, |
5400 | dev_priv->lvds_downclock, |
4961 | &reduced_clock); |
5401 | refclk, &clock, |
4962 | } |
5402 | &reduced_clock); |
4963 | /* Compat-code for transition, will disappear. */ |
5403 | } |
4964 | if (!intel_crtc->config.clock_set) { |
5404 | /* Compat-code for transition, will disappear. */ |
4965 | intel_crtc->config.dpll.n = clock.n; |
5405 | intel_crtc->config.dpll.n = clock.n; |
Line 4966... | Line 5406... | ||
4966 | intel_crtc->config.dpll.m1 = clock.m1; |
5406 | intel_crtc->config.dpll.m1 = clock.m1; |
4967 | intel_crtc->config.dpll.m2 = clock.m2; |
5407 | intel_crtc->config.dpll.m2 = clock.m2; |
4968 | intel_crtc->config.dpll.p1 = clock.p1; |
5408 | intel_crtc->config.dpll.p1 = clock.p1; |
4969 | intel_crtc->config.dpll.p2 = clock.p2; |
5409 | intel_crtc->config.dpll.p2 = clock.p2; |
4970 | } |
5410 | } |
4971 | 5411 | ||
4972 | if (IS_GEN2(dev)) |
5412 | if (IS_GEN2(dev)) { |
4973 | i8xx_update_pll(intel_crtc, |
5413 | i8xx_update_pll(intel_crtc, |
4974 | has_reduced_clock ? &reduced_clock : NULL, |
5414 | has_reduced_clock ? &reduced_clock : NULL, |
4975 | num_connectors); |
5415 | num_connectors); |
- | 5416 | } else if (IS_VALLEYVIEW(dev)) { |
|
Line -... | Line 5417... | ||
- | 5417 | vlv_update_pll(intel_crtc); |
|
4976 | else if (IS_VALLEYVIEW(dev)) |
5418 | } else { |
4977 | vlv_update_pll(intel_crtc); |
5419 | i9xx_update_pll(intel_crtc, |
Line 4978... | Line 5420... | ||
4978 | else |
5420 | has_reduced_clock ? &reduced_clock : NULL, |
4979 | i9xx_update_pll(intel_crtc, |
5421 | num_connectors); |
Line 4994... | Line 5436... | ||
4994 | 5436 | ||
4995 | /* pipesrc and dspsize control the size that is scaled from, |
5437 | /* pipesrc and dspsize control the size that is scaled from, |
4996 | * which should always be the user's requested size. |
5438 | * which should always be the user's requested size. |
4997 | */ |
5439 | */ |
4998 | I915_WRITE(DSPSIZE(plane), |
5440 | I915_WRITE(DSPSIZE(plane), |
4999 | ((mode->vdisplay - 1) << 16) | |
5441 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5000 | (mode->hdisplay - 1)); |
5442 | (intel_crtc->config.pipe_src_w - 1)); |
Line 5001... | Line 5443... | ||
5001 | I915_WRITE(DSPPOS(plane), 0); |
5443 | I915_WRITE(DSPPOS(plane), 0); |
Line 5002... | Line 5444... | ||
5002 | 5444 | ||
5003 | i9xx_set_pipeconf(intel_crtc); |
5445 | i9xx_set_pipeconf(intel_crtc); |
Line 5004... | Line 5446... | ||
5004 | 5446 | ||
Line 5005... | Line -... | ||
5005 | I915_WRITE(DSPCNTR(plane), dspcntr); |
- | |
5006 | POSTING_READ(DSPCNTR(plane)); |
- | |
5007 | 5447 | I915_WRITE(DSPCNTR(plane), dspcntr); |
|
5008 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5448 | POSTING_READ(DSPCNTR(plane)); |
Line 5009... | Line 5449... | ||
5009 | 5449 | ||
5010 | intel_update_watermarks(dev); |
5450 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5011 | 5451 | ||
5012 | return ret; |
5452 | return ret; |
5013 | } |
5453 | } |
5014 | 5454 | ||
Line -... | Line 5455... | ||
- | 5455 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
|
- | 5456 | struct intel_crtc_config *pipe_config) |
|
- | 5457 | { |
|
5015 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5458 | struct drm_device *dev = crtc->base.dev; |
5016 | struct intel_crtc_config *pipe_config) |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; |
5017 | { |
5460 | uint32_t tmp; |
Line 5018... | Line 5461... | ||
5018 | struct drm_device *dev = crtc->base.dev; |
5461 | |
Line 5048... | Line 5491... | ||
5048 | intel_clock_t clock; |
5491 | intel_clock_t clock; |
5049 | u32 mdiv; |
5492 | u32 mdiv; |
5050 | int refclk = 100000; |
5493 | int refclk = 100000; |
Line 5051... | Line 5494... | ||
5051 | 5494 | ||
5052 | mutex_lock(&dev_priv->dpio_lock); |
5495 | mutex_lock(&dev_priv->dpio_lock); |
5053 | mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
5496 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Line 5054... | Line 5497... | ||
5054 | mutex_unlock(&dev_priv->dpio_lock); |
5497 | mutex_unlock(&dev_priv->dpio_lock); |
5055 | 5498 | ||
5056 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5499 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5057 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5500 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5058 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
5501 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
Line 5059... | Line -... | ||
5059 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
- | |
5060 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
5502 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
Line -... | Line 5503... | ||
- | 5503 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
|
5061 | 5504 | ||
5062 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
5505 | vlv_clock(refclk, &clock); |
Line 5063... | Line 5506... | ||
5063 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
5506 | |
5064 | 5507 | /* clock.dot is the fast clock */ |
|
5065 | pipe_config->adjusted_mode.clock = clock.dot / 10; |
5508 | pipe_config->port_clock = clock.dot / 5; |
Line 5093... | Line 5536... | ||
5093 | default: |
5536 | default: |
5094 | break; |
5537 | break; |
5095 | } |
5538 | } |
5096 | } |
5539 | } |
Line -... | Line 5540... | ||
- | 5540 | ||
- | 5541 | if (INTEL_INFO(dev)->gen < 4) |
|
- | 5542 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
|
5097 | 5543 | ||
Line 5098... | Line 5544... | ||
5098 | intel_get_pipe_timings(crtc, pipe_config); |
5544 | intel_get_pipe_timings(crtc, pipe_config); |
Line 5099... | Line 5545... | ||
5099 | 5545 | ||
Line 5125... | Line 5571... | ||
5125 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5571 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5126 | DPLL_PORTC_READY_MASK | |
5572 | DPLL_PORTC_READY_MASK | |
5127 | DPLL_PORTB_READY_MASK); |
5573 | DPLL_PORTB_READY_MASK); |
5128 | } |
5574 | } |
Line -... | Line 5575... | ||
- | 5575 | ||
- | 5576 | if (IS_VALLEYVIEW(dev)) |
|
- | 5577 | vlv_crtc_clock_get(crtc, pipe_config); |
|
- | 5578 | else |
|
- | 5579 | i9xx_crtc_clock_get(crtc, pipe_config); |
|
5129 | 5580 | ||
5130 | return true; |
5581 | return true; |
Line 5131... | Line 5582... | ||
5131 | } |
5582 | } |
5132 | 5583 | ||
Line 5497... | Line 5948... | ||
5497 | } |
5948 | } |
5498 | num_connectors++; |
5949 | num_connectors++; |
5499 | } |
5950 | } |
Line 5500... | Line 5951... | ||
5500 | 5951 | ||
5501 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5952 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5502 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5953 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
5503 | dev_priv->vbt.lvds_ssc_freq); |
5954 | dev_priv->vbt.lvds_ssc_freq); |
5504 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
5955 | return dev_priv->vbt.lvds_ssc_freq; |
Line 5505... | Line 5956... | ||
5505 | } |
5956 | } |
5506 | 5957 | ||
Line 5613... | Line 6064... | ||
5613 | } |
6064 | } |
5614 | } |
6065 | } |
Line 5615... | Line 6066... | ||
5615 | 6066 | ||
5616 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
6067 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
- | 6068 | { |
|
5617 | { |
6069 | struct drm_device *dev = crtc->dev; |
5618 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 6071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
5619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6072 | enum pipe pipe = intel_crtc->pipe; |
5620 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
6073 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Line 5621... | Line 6074... | ||
5621 | uint32_t val; |
6074 | uint32_t val; |
Line 5622... | Line 6075... | ||
5622 | 6075 | ||
5623 | val = 0; |
6076 | val = 0; |
Line 5624... | Line 6077... | ||
5624 | 6077 | ||
5625 | if (intel_crtc->config.dither) |
6078 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
5626 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6079 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
Line 5633... | Line 6086... | ||
5633 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6086 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5634 | POSTING_READ(PIPECONF(cpu_transcoder)); |
6087 | POSTING_READ(PIPECONF(cpu_transcoder)); |
Line 5635... | Line 6088... | ||
5635 | 6088 | ||
5636 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
6089 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
- | 6090 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
|
- | 6091 | ||
- | 6092 | if (IS_BROADWELL(dev)) { |
|
- | 6093 | val = 0; |
|
- | 6094 | ||
- | 6095 | switch (intel_crtc->config.pipe_bpp) { |
|
- | 6096 | case 18: |
|
- | 6097 | val |= PIPEMISC_DITHER_6_BPC; |
|
- | 6098 | break; |
|
- | 6099 | case 24: |
|
- | 6100 | val |= PIPEMISC_DITHER_8_BPC; |
|
- | 6101 | break; |
|
- | 6102 | case 30: |
|
- | 6103 | val |= PIPEMISC_DITHER_10_BPC; |
|
- | 6104 | break; |
|
- | 6105 | case 36: |
|
- | 6106 | val |= PIPEMISC_DITHER_12_BPC; |
|
- | 6107 | break; |
|
- | 6108 | default: |
|
- | 6109 | /* Case prevented by pipe_config_set_bpp. */ |
|
- | 6110 | BUG(); |
|
- | 6111 | } |
|
- | 6112 | ||
- | 6113 | if (intel_crtc->config.dither) |
|
- | 6114 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
|
- | 6115 | ||
- | 6116 | I915_WRITE(PIPEMISC(pipe), val); |
|
5637 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
6117 | } |
Line 5638... | Line 6118... | ||
5638 | } |
6118 | } |
5639 | 6119 | ||
5640 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6120 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
Line 5732... | Line 6212... | ||
5732 | 6212 | ||
5733 | /* Enable autotuning of the PLL clock (if permissible) */ |
6213 | /* Enable autotuning of the PLL clock (if permissible) */ |
5734 | factor = 21; |
6214 | factor = 21; |
5735 | if (is_lvds) { |
6215 | if (is_lvds) { |
5736 | if ((intel_panel_use_ssc(dev_priv) && |
6216 | if ((intel_panel_use_ssc(dev_priv) && |
5737 | dev_priv->vbt.lvds_ssc_freq == 100) || |
6217 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
5738 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
6218 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
5739 | factor = 25; |
6219 | factor = 25; |
5740 | } else if (intel_crtc->config.sdvo_tv_clock) |
6220 | } else if (intel_crtc->config.sdvo_tv_clock) |
Line 5867... | Line 6347... | ||
5867 | if (is_lvds && has_reduced_clock && i915_powersave) |
6347 | if (is_lvds && has_reduced_clock && i915_powersave) |
5868 | intel_crtc->lowfreq_avail = true; |
6348 | intel_crtc->lowfreq_avail = true; |
5869 | else |
6349 | else |
5870 | intel_crtc->lowfreq_avail = false; |
6350 | intel_crtc->lowfreq_avail = false; |
Line 5871... | Line -... | ||
5871 | - | ||
5872 | if (intel_crtc->config.has_pch_encoder) { |
- | |
5873 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
- | |
5874 | - | ||
5875 | } |
- | |
5876 | 6351 | ||
Line 5877... | Line 6352... | ||
5877 | intel_set_pipe_timings(intel_crtc); |
6352 | intel_set_pipe_timings(intel_crtc); |
5878 | 6353 | ||
5879 | if (intel_crtc->config.has_pch_encoder) { |
6354 | if (intel_crtc->config.has_pch_encoder) { |
Line 5887... | Line 6362... | ||
5887 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
6362 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5888 | POSTING_READ(DSPCNTR(plane)); |
6363 | POSTING_READ(DSPCNTR(plane)); |
Line 5889... | Line 6364... | ||
5889 | 6364 | ||
Line 5890... | Line -... | ||
5890 | ret = intel_pipe_set_base(crtc, x, y, fb); |
- | |
5891 | - | ||
5892 | intel_update_watermarks(dev); |
6365 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5893 | 6366 | ||
Line 5894... | Line 6367... | ||
5894 | return ret; |
6367 | return ret; |
5895 | } |
6368 | } |
5896 | 6369 | ||
5897 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6370 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
5898 | struct intel_crtc_config *pipe_config) |
6371 | struct intel_link_m_n *m_n) |
5899 | { |
6372 | { |
Line 5900... | Line 6373... | ||
5900 | struct drm_device *dev = crtc->base.dev; |
6373 | struct drm_device *dev = crtc->base.dev; |
5901 | struct drm_i915_private *dev_priv = dev->dev_private; |
6374 | struct drm_i915_private *dev_priv = dev->dev_private; |
5902 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
6375 | enum pipe pipe = crtc->pipe; |
5903 | 6376 | ||
5904 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
6377 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
5905 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
6378 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
5906 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
6379 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
5907 | & ~TU_SIZE_MASK; |
6380 | & ~TU_SIZE_MASK; |
Line -... | Line 6381... | ||
- | 6381 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
|
- | 6382 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
|
- | 6383 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
|
- | 6384 | } |
|
- | 6385 | ||
- | 6386 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
|
- | 6387 | enum transcoder transcoder, |
|
- | 6388 | struct intel_link_m_n *m_n) |
|
- | 6389 | { |
|
- | 6390 | struct drm_device *dev = crtc->base.dev; |
|
- | 6391 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6392 | enum pipe pipe = crtc->pipe; |
|
- | 6393 | ||
- | 6394 | if (INTEL_INFO(dev)->gen >= 5) { |
|
- | 6395 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
|
- | 6396 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
|
- | 6397 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
|
- | 6398 | & ~TU_SIZE_MASK; |
|
- | 6399 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
|
- | 6400 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
|
- | 6401 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
|
- | 6402 | } else { |
|
- | 6403 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
|
- | 6404 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
|
- | 6405 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
|
- | 6406 | & ~TU_SIZE_MASK; |
|
- | 6407 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
|
- | 6408 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
|
- | 6409 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
|
- | 6410 | } |
|
- | 6411 | } |
|
- | 6412 | ||
- | 6413 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
|
- | 6414 | struct intel_crtc_config *pipe_config) |
|
- | 6415 | { |
|
- | 6416 | if (crtc->config.has_pch_encoder) |
|
- | 6417 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
|
- | 6418 | else |
|
- | 6419 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
|
- | 6420 | &pipe_config->dp_m_n); |
|
- | 6421 | } |
|
- | 6422 | ||
- | 6423 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
|
- | 6424 | struct intel_crtc_config *pipe_config) |
|
5908 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
6425 | { |
5909 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
6426 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
5910 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6427 | &pipe_config->fdi_m_n); |
5911 | } |
6428 | } |
5912 | 6429 | ||
Line 5994... | Line 6511... | ||
5994 | 6511 | ||
5995 | tmp = pipe_config->dpll_hw_state.dpll; |
6512 | tmp = pipe_config->dpll_hw_state.dpll; |
5996 | pipe_config->pixel_multiplier = |
6513 | pipe_config->pixel_multiplier = |
5997 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
6514 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
- | 6515 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
|
- | 6516 | ||
5998 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
6517 | ironlake_pch_clock_get(crtc, pipe_config); |
5999 | } else { |
6518 | } else { |
6000 | pipe_config->pixel_multiplier = 1; |
6519 | pipe_config->pixel_multiplier = 1; |
Line 6001... | Line 6520... | ||
6001 | } |
6520 | } |
Line 6034... | Line 6553... | ||
6034 | "Utility pin enabled\n"); |
6553 | "Utility pin enabled\n"); |
6035 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
6554 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
Line 6036... | Line 6555... | ||
6036 | 6555 | ||
6037 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
6556 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
6038 | val = I915_READ(DEIMR); |
6557 | val = I915_READ(DEIMR); |
6039 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
6558 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
6040 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6559 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6041 | val = I915_READ(SDEIMR); |
6560 | val = I915_READ(SDEIMR); |
6042 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6561 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6043 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6562 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
Line 6050... | Line 6569... | ||
6050 | * - Sequence for display software to allow package C8+ |
6569 | * - Sequence for display software to allow package C8+ |
6051 | * The steps implemented here are just the steps that actually touch the LCPLL |
6570 | * The steps implemented here are just the steps that actually touch the LCPLL |
6052 | * register. Callers should take care of disabling all the display engine |
6571 | * register. Callers should take care of disabling all the display engine |
6053 | * functions, doing the mode unset, fixing interrupts, etc. |
6572 | * functions, doing the mode unset, fixing interrupts, etc. |
6054 | */ |
6573 | */ |
6055 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6574 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6056 | bool switch_to_fclk, bool allow_power_down) |
6575 | bool switch_to_fclk, bool allow_power_down) |
6057 | { |
6576 | { |
6058 | uint32_t val; |
6577 | uint32_t val; |
Line 6059... | Line 6578... | ||
6059 | 6578 | ||
Line 6079... | Line 6598... | ||
6079 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6598 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6080 | DRM_ERROR("LCPLL still locked\n"); |
6599 | DRM_ERROR("LCPLL still locked\n"); |
Line 6081... | Line 6600... | ||
6081 | 6600 | ||
6082 | val = I915_READ(D_COMP); |
6601 | val = I915_READ(D_COMP); |
- | 6602 | val |= D_COMP_COMP_DISABLE; |
|
- | 6603 | mutex_lock(&dev_priv->rps.hw_lock); |
|
6083 | val |= D_COMP_COMP_DISABLE; |
6604 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
- | 6605 | DRM_ERROR("Failed to disable D_COMP\n"); |
|
6084 | I915_WRITE(D_COMP, val); |
6606 | mutex_unlock(&dev_priv->rps.hw_lock); |
6085 | POSTING_READ(D_COMP); |
6607 | POSTING_READ(D_COMP); |
Line 6086... | Line 6608... | ||
6086 | udelay(100); |
6608 | delay(1); |
6087 | 6609 | ||
Line 6088... | Line 6610... | ||
6088 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
6610 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
Line 6098... | Line 6620... | ||
6098 | 6620 | ||
6099 | /* |
6621 | /* |
6100 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6622 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6101 | * source. |
6623 | * source. |
6102 | */ |
6624 | */ |
6103 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6625 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6104 | { |
6626 | { |
Line 6105... | Line 6627... | ||
6105 | uint32_t val; |
6627 | uint32_t val; |
Line 6110... | Line 6632... | ||
6110 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6632 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6111 | return; |
6633 | return; |
Line 6112... | Line 6634... | ||
6112 | 6634 | ||
6113 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6635 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6114 | * we'll hang the machine! */ |
6636 | * we'll hang the machine! */ |
Line 6115... | Line 6637... | ||
6115 | gen6_gt_force_wake_get(dev_priv); |
6637 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6116 | 6638 | ||
6117 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6639 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6118 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6640 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6119 | I915_WRITE(LCPLL_CTL, val); |
6641 | I915_WRITE(LCPLL_CTL, val); |
Line 6120... | Line 6642... | ||
6120 | POSTING_READ(LCPLL_CTL); |
6642 | POSTING_READ(LCPLL_CTL); |
6121 | } |
6643 | } |
6122 | 6644 | ||
- | 6645 | val = I915_READ(D_COMP); |
|
- | 6646 | val |= D_COMP_COMP_FORCE; |
|
6123 | val = I915_READ(D_COMP); |
6647 | val &= ~D_COMP_COMP_DISABLE; |
- | 6648 | mutex_lock(&dev_priv->rps.hw_lock); |
|
6124 | val |= D_COMP_COMP_FORCE; |
6649 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
Line 6125... | Line 6650... | ||
6125 | val &= ~D_COMP_COMP_DISABLE; |
6650 | DRM_ERROR("Failed to enable D_COMP\n"); |
6126 | I915_WRITE(D_COMP, val); |
6651 | mutex_unlock(&dev_priv->rps.hw_lock); |
6127 | POSTING_READ(D_COMP); |
6652 | POSTING_READ(D_COMP); |
Line 6141... | Line 6666... | ||
6141 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6666 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6142 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6667 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6143 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6668 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6144 | } |
6669 | } |
Line 6145... | Line 6670... | ||
6145 | 6670 | ||
6146 | gen6_gt_force_wake_put(dev_priv); |
6671 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Line 6147... | Line 6672... | ||
6147 | } |
6672 | } |
6148 | 6673 | ||
6149 | void hsw_enable_pc8_work(struct work_struct *__work) |
6674 | void hsw_enable_pc8_work(struct work_struct *__work) |
6150 | { |
6675 | { |
6151 | struct drm_i915_private *dev_priv = |
6676 | struct drm_i915_private *dev_priv = |
6152 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6677 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6153 | pc8.enable_work); |
6678 | pc8.enable_work); |
Line -... | Line 6679... | ||
- | 6679 | struct drm_device *dev = dev_priv->dev; |
|
- | 6680 | uint32_t val; |
|
6154 | struct drm_device *dev = dev_priv->dev; |
6681 | |
6155 | uint32_t val; |
6682 | WARN_ON(!HAS_PC8(dev)); |
Line 6156... | Line 6683... | ||
6156 | 6683 | ||
Line 6168... | Line 6695... | ||
6168 | } |
6695 | } |
Line 6169... | Line 6696... | ||
6169 | 6696 | ||
6170 | lpt_disable_clkout_dp(dev); |
6697 | lpt_disable_clkout_dp(dev); |
6171 | hsw_pc8_disable_interrupts(dev); |
6698 | hsw_pc8_disable_interrupts(dev); |
- | 6699 | hsw_disable_lcpll(dev_priv, true, true); |
|
- | 6700 | ||
6172 | hsw_disable_lcpll(dev_priv, true, true); |
6701 | intel_runtime_pm_put(dev_priv); |
Line 6173... | Line 6702... | ||
6173 | } |
6702 | } |
6174 | 6703 | ||
6175 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6704 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
Line 6197... | Line 6726... | ||
6197 | 6726 | ||
6198 | dev_priv->pc8.disable_count++; |
6727 | dev_priv->pc8.disable_count++; |
6199 | if (dev_priv->pc8.disable_count != 1) |
6728 | if (dev_priv->pc8.disable_count != 1) |
Line -... | Line 6729... | ||
- | 6729 | return; |
|
- | 6730 | ||
6200 | return; |
6731 | WARN_ON(!HAS_PC8(dev)); |
6201 | 6732 | ||
6202 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6733 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
Line 6203... | Line 6734... | ||
6203 | if (!dev_priv->pc8.enabled) |
6734 | if (!dev_priv->pc8.enabled) |
Line -... | Line 6735... | ||
- | 6735 | return; |
|
- | 6736 | ||
6204 | return; |
6737 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6205 | 6738 | ||
6206 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6739 | intel_runtime_pm_get(dev_priv); |
Line 6207... | Line 6740... | ||
6207 | 6740 | ||
Line 6223... | Line 6756... | ||
6223 | dev_priv->pc8.enabled = false; |
6756 | dev_priv->pc8.enabled = false; |
6224 | } |
6757 | } |
Line 6225... | Line 6758... | ||
6225 | 6758 | ||
6226 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6759 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
- | 6760 | { |
|
- | 6761 | if (!HAS_PC8(dev_priv->dev)) |
|
- | 6762 | return; |
|
6227 | { |
6763 | |
6228 | mutex_lock(&dev_priv->pc8.lock); |
6764 | mutex_lock(&dev_priv->pc8.lock); |
6229 | __hsw_enable_package_c8(dev_priv); |
6765 | __hsw_enable_package_c8(dev_priv); |
6230 | mutex_unlock(&dev_priv->pc8.lock); |
6766 | mutex_unlock(&dev_priv->pc8.lock); |
Line 6231... | Line 6767... | ||
6231 | } |
6767 | } |
6232 | 6768 | ||
- | 6769 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
|
- | 6770 | { |
|
- | 6771 | if (!HAS_PC8(dev_priv->dev)) |
|
6233 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6772 | return; |
6234 | { |
6773 | |
6235 | mutex_lock(&dev_priv->pc8.lock); |
6774 | mutex_lock(&dev_priv->pc8.lock); |
6236 | __hsw_disable_package_c8(dev_priv); |
6775 | __hsw_disable_package_c8(dev_priv); |
Line 6267... | Line 6806... | ||
6267 | static void hsw_update_package_c8(struct drm_device *dev) |
6806 | static void hsw_update_package_c8(struct drm_device *dev) |
6268 | { |
6807 | { |
6269 | struct drm_i915_private *dev_priv = dev->dev_private; |
6808 | struct drm_i915_private *dev_priv = dev->dev_private; |
6270 | bool allow; |
6809 | bool allow; |
Line -... | Line 6810... | ||
- | 6810 | ||
- | 6811 | if (!HAS_PC8(dev_priv->dev)) |
|
- | 6812 | return; |
|
6271 | 6813 | ||
6272 | if (!i915_enable_pc8) |
6814 | if (!i915_enable_pc8) |
Line 6273... | Line 6815... | ||
6273 | return; |
6815 | return; |
Line 6290... | Line 6832... | ||
6290 | mutex_unlock(&dev_priv->pc8.lock); |
6832 | mutex_unlock(&dev_priv->pc8.lock); |
6291 | } |
6833 | } |
Line 6292... | Line 6834... | ||
6292 | 6834 | ||
6293 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
6835 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
- | 6836 | { |
|
- | 6837 | if (!HAS_PC8(dev_priv->dev)) |
|
- | 6838 | return; |
|
- | 6839 | ||
6294 | { |
6840 | mutex_lock(&dev_priv->pc8.lock); |
6295 | if (!dev_priv->pc8.gpu_idle) { |
6841 | if (!dev_priv->pc8.gpu_idle) { |
6296 | dev_priv->pc8.gpu_idle = true; |
6842 | dev_priv->pc8.gpu_idle = true; |
6297 | hsw_enable_package_c8(dev_priv); |
6843 | __hsw_enable_package_c8(dev_priv); |
- | 6844 | } |
|
6298 | } |
6845 | mutex_unlock(&dev_priv->pc8.lock); |
Line 6299... | Line 6846... | ||
6299 | } |
6846 | } |
6300 | 6847 | ||
- | 6848 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
|
- | 6849 | { |
|
- | 6850 | if (!HAS_PC8(dev_priv->dev)) |
|
- | 6851 | return; |
|
6301 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
6852 | |
6302 | { |
6853 | mutex_lock(&dev_priv->pc8.lock); |
6303 | if (dev_priv->pc8.gpu_idle) { |
6854 | if (dev_priv->pc8.gpu_idle) { |
6304 | dev_priv->pc8.gpu_idle = false; |
6855 | dev_priv->pc8.gpu_idle = false; |
- | 6856 | __hsw_disable_package_c8(dev_priv); |
|
6305 | hsw_disable_package_c8(dev_priv); |
6857 | } |
Line -... | Line 6858... | ||
- | 6858 | mutex_unlock(&dev_priv->pc8.lock); |
|
- | 6859 | } |
|
- | 6860 | ||
- | 6861 | #define for_each_power_domain(domain, mask) \ |
|
6306 | } |
6862 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
- | 6863 | if ((1 << (domain)) & (mask)) |
|
6307 | } |
6864 | |
6308 | 6865 | static unsigned long get_pipe_power_domains(struct drm_device *dev, |
|
- | 6866 | enum pipe pipe, bool pfit_enabled) |
|
- | 6867 | { |
|
- | 6868 | unsigned long mask; |
|
- | 6869 | enum transcoder transcoder; |
|
- | 6870 | ||
- | 6871 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
|
- | 6872 | ||
- | 6873 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
|
- | 6874 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
|
- | 6875 | if (pfit_enabled) |
|
- | 6876 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
|
- | 6877 | ||
- | 6878 | return mask; |
|
- | 6879 | } |
|
- | 6880 | ||
- | 6881 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
|
- | 6882 | { |
|
- | 6883 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6884 | ||
- | 6885 | if (dev_priv->power_domains.init_power_on == enable) |
|
- | 6886 | return; |
|
- | 6887 | ||
- | 6888 | if (enable) |
|
- | 6889 | intel_display_power_get(dev, POWER_DOMAIN_INIT); |
|
- | 6890 | else |
|
- | 6891 | intel_display_power_put(dev, POWER_DOMAIN_INIT); |
|
- | 6892 | ||
- | 6893 | dev_priv->power_domains.init_power_on = enable; |
|
- | 6894 | } |
|
- | 6895 | ||
6309 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6896 | static void modeset_update_power_wells(struct drm_device *dev) |
Line -... | Line 6897... | ||
- | 6897 | { |
|
- | 6898 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
|
- | 6899 | struct intel_crtc *crtc; |
|
- | 6900 | ||
6310 | { |
6901 | /* |
- | 6902 | * First get all needed power domains, then put all unneeded, to avoid |
|
- | 6903 | * any unnecessary toggling of the power wells. |
|
6311 | bool enable = false; |
6904 | */ |
6312 | struct intel_crtc *crtc; |
6905 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
Line -... | Line 6906... | ||
- | 6906 | enum intel_display_power_domain domain; |
|
- | 6907 | ||
6313 | 6908 | if (!crtc->base.enabled) |
|
- | 6909 | continue; |
|
6314 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6910 | |
6315 | if (!crtc->base.enabled) |
6911 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6316 | continue; |
6912 | crtc->pipe, |
Line -... | Line 6913... | ||
- | 6913 | crtc->config.pch_pfit.enabled); |
|
- | 6914 | ||
- | 6915 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
|
- | 6916 | intel_display_power_get(dev, domain); |
|
6317 | 6917 | } |
|
Line -... | Line 6918... | ||
- | 6918 | ||
- | 6919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
|
- | 6920 | enum intel_display_power_domain domain; |
|
- | 6921 | ||
- | 6922 | for_each_power_domain(domain, crtc->enabled_power_domains) |
|
- | 6923 | intel_display_power_put(dev, domain); |
|
- | 6924 | ||
- | 6925 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
|
- | 6926 | } |
|
6318 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6927 | |
6319 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
6928 | intel_display_set_init_power(dev, false); |
Line 6320... | Line 6929... | ||
6320 | enable = true; |
6929 | } |
6321 | } |
6930 | |
Line 6333... | Line 6942... | ||
6333 | struct drm_i915_private *dev_priv = dev->dev_private; |
6942 | struct drm_i915_private *dev_priv = dev->dev_private; |
6334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6335 | int plane = intel_crtc->plane; |
6944 | int plane = intel_crtc->plane; |
6336 | int ret; |
6945 | int ret; |
Line 6337... | Line 6946... | ||
6337 | 6946 | ||
6338 | if (!intel_ddi_pll_mode_set(crtc)) |
6947 | if (!intel_ddi_pll_select(intel_crtc)) |
- | 6948 | return -EINVAL; |
|
Line 6339... | Line 6949... | ||
6339 | return -EINVAL; |
6949 | intel_ddi_pll_enable(intel_crtc); |
6340 | 6950 | ||
Line 6341... | Line 6951... | ||
6341 | if (intel_crtc->config.has_dp_encoder) |
6951 | if (intel_crtc->config.has_dp_encoder) |
Line 6358... | Line 6968... | ||
6358 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6968 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6359 | POSTING_READ(DSPCNTR(plane)); |
6969 | POSTING_READ(DSPCNTR(plane)); |
Line 6360... | Line 6970... | ||
6360 | 6970 | ||
Line 6361... | Line -... | ||
6361 | ret = intel_pipe_set_base(crtc, x, y, fb); |
- | |
6362 | - | ||
6363 | intel_update_watermarks(dev); |
6971 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6364 | 6972 | ||
Line 6365... | Line 6973... | ||
6365 | return ret; |
6973 | return ret; |
6366 | } |
6974 | } |
Line 6427... | Line 7035... | ||
6427 | 7035 | ||
6428 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7036 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6429 | if (intel_display_power_enabled(dev, pfit_domain)) |
7037 | if (intel_display_power_enabled(dev, pfit_domain)) |
Line -... | Line 7038... | ||
- | 7038 | ironlake_get_pfit_config(crtc, pipe_config); |
|
6430 | ironlake_get_pfit_config(crtc, pipe_config); |
7039 | |
6431 | 7040 | if (IS_HASWELL(dev)) |
|
Line 6432... | Line 7041... | ||
6432 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
7041 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
Line 6467... | Line 7076... | ||
6467 | } |
7076 | } |
Line 6468... | Line 7077... | ||
6468 | 7077 | ||
6469 | return 0; |
7078 | return 0; |
Line -... | Line 7079... | ||
- | 7079 | } |
|
- | 7080 | ||
- | 7081 | static struct { |
|
- | 7082 | int clock; |
|
- | 7083 | u32 config; |
|
- | 7084 | } hdmi_audio_clock[] = { |
|
- | 7085 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
|
- | 7086 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
|
- | 7087 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
|
- | 7088 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
|
- | 7089 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
|
- | 7090 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
|
- | 7091 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
|
- | 7092 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
|
- | 7093 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
|
- | 7094 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
|
- | 7095 | }; |
|
- | 7096 | ||
- | 7097 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
|
- | 7098 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
|
- | 7099 | { |
|
- | 7100 | int i; |
|
- | 7101 | ||
- | 7102 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
|
- | 7103 | if (mode->clock == hdmi_audio_clock[i].clock) |
|
- | 7104 | break; |
|
- | 7105 | } |
|
- | 7106 | ||
- | 7107 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
|
- | 7108 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
|
- | 7109 | i = 1; |
|
- | 7110 | } |
|
- | 7111 | ||
- | 7112 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
|
- | 7113 | hdmi_audio_clock[i].clock, |
|
- | 7114 | hdmi_audio_clock[i].config); |
|
- | 7115 | ||
- | 7116 | return hdmi_audio_clock[i].config; |
|
6470 | } |
7117 | } |
6471 | 7118 | ||
6472 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7119 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6473 | int reg_eldv, uint32_t bits_eldv, |
7120 | int reg_eldv, uint32_t bits_eldv, |
6474 | int reg_elda, uint32_t bits_elda, |
7121 | int reg_elda, uint32_t bits_elda, |
Line 6497... | Line 7144... | ||
6497 | 7144 | ||
6498 | return true; |
7145 | return true; |
Line 6499... | Line 7146... | ||
6499 | } |
7146 | } |
6500 | 7147 | ||
- | 7148 | static void g4x_write_eld(struct drm_connector *connector, |
|
6501 | static void g4x_write_eld(struct drm_connector *connector, |
7149 | struct drm_crtc *crtc, |
6502 | struct drm_crtc *crtc) |
7150 | struct drm_display_mode *mode) |
6503 | { |
7151 | { |
6504 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7152 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6505 | uint8_t *eld = connector->eld; |
7153 | uint8_t *eld = connector->eld; |
Line 6537... | Line 7185... | ||
6537 | i |= eldv; |
7185 | i |= eldv; |
6538 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7186 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6539 | } |
7187 | } |
Line 6540... | Line 7188... | ||
6540 | 7188 | ||
6541 | static void haswell_write_eld(struct drm_connector *connector, |
7189 | static void haswell_write_eld(struct drm_connector *connector, |
- | 7190 | struct drm_crtc *crtc, |
|
6542 | struct drm_crtc *crtc) |
7191 | struct drm_display_mode *mode) |
6543 | { |
7192 | { |
6544 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7193 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6545 | uint8_t *eld = connector->eld; |
7194 | uint8_t *eld = connector->eld; |
6546 | struct drm_device *dev = crtc->dev; |
7195 | struct drm_device *dev = crtc->dev; |
Line 6590... | Line 7239... | ||
6590 | 7239 | ||
6591 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7240 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6592 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7241 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6593 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7242 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6594 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7243 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6595 | } else |
7244 | } else { |
- | 7245 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
|
Line 6596... | Line 7246... | ||
6596 | I915_WRITE(aud_config, 0); |
7246 | } |
6597 | 7247 | ||
6598 | if (intel_eld_uptodate(connector, |
7248 | if (intel_eld_uptodate(connector, |
6599 | aud_cntrl_st2, eldv, |
7249 | aud_cntrl_st2, eldv, |
Line 6624... | Line 7274... | ||
6624 | I915_WRITE(aud_cntrl_st2, i); |
7274 | I915_WRITE(aud_cntrl_st2, i); |
Line 6625... | Line 7275... | ||
6625 | 7275 | ||
Line 6626... | Line 7276... | ||
6626 | } |
7276 | } |
6627 | 7277 | ||
- | 7278 | static void ironlake_write_eld(struct drm_connector *connector, |
|
6628 | static void ironlake_write_eld(struct drm_connector *connector, |
7279 | struct drm_crtc *crtc, |
6629 | struct drm_crtc *crtc) |
7280 | struct drm_display_mode *mode) |
6630 | { |
7281 | { |
6631 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7282 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6632 | uint8_t *eld = connector->eld; |
7283 | uint8_t *eld = connector->eld; |
Line 6642... | Line 7293... | ||
6642 | if (HAS_PCH_IBX(connector->dev)) { |
7293 | if (HAS_PCH_IBX(connector->dev)) { |
6643 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7294 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6644 | aud_config = IBX_AUD_CFG(pipe); |
7295 | aud_config = IBX_AUD_CFG(pipe); |
6645 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
7296 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
6646 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
7297 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
- | 7298 | } else if (IS_VALLEYVIEW(connector->dev)) { |
|
- | 7299 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
|
- | 7300 | aud_config = VLV_AUD_CFG(pipe); |
|
- | 7301 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
|
- | 7302 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
|
6647 | } else { |
7303 | } else { |
6648 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7304 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6649 | aud_config = CPT_AUD_CFG(pipe); |
7305 | aud_config = CPT_AUD_CFG(pipe); |
6650 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
7306 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
6651 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
7307 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6652 | } |
7308 | } |
Line 6653... | Line 7309... | ||
6653 | 7309 | ||
Line -... | Line 7310... | ||
- | 7310 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
|
- | 7311 | ||
- | 7312 | if (IS_VALLEYVIEW(connector->dev)) { |
|
- | 7313 | struct intel_encoder *intel_encoder; |
|
- | 7314 | struct intel_digital_port *intel_dig_port; |
|
- | 7315 | ||
- | 7316 | intel_encoder = intel_attached_encoder(connector); |
|
- | 7317 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
|
6654 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
7318 | i = intel_dig_port->port; |
- | 7319 | } else { |
|
6655 | 7320 | i = I915_READ(aud_cntl_st); |
|
- | 7321 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
|
- | 7322 | /* DIP_Port_Select, 0x1 = PortB */ |
|
6656 | i = I915_READ(aud_cntl_st); |
7323 | } |
6657 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
7324 | |
6658 | if (!i) { |
7325 | if (!i) { |
6659 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
7326 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
6660 | /* operate blindly on all ports */ |
7327 | /* operate blindly on all ports */ |
Line 6668... | Line 7335... | ||
6668 | 7335 | ||
6669 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7336 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6670 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
7337 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6671 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7338 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6672 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7339 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6673 | } else |
7340 | } else { |
- | 7341 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
|
Line 6674... | Line 7342... | ||
6674 | I915_WRITE(aud_config, 0); |
7342 | } |
6675 | 7343 | ||
6676 | if (intel_eld_uptodate(connector, |
7344 | if (intel_eld_uptodate(connector, |
6677 | aud_cntrl_st2, eldv, |
7345 | aud_cntrl_st2, eldv, |
Line 6719... | Line 7387... | ||
6719 | drm_get_encoder_name(connector->encoder)); |
7387 | drm_get_encoder_name(connector->encoder)); |
Line 6720... | Line 7388... | ||
6720 | 7388 | ||
Line 6721... | Line 7389... | ||
6721 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
7389 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
6722 | 7390 | ||
6723 | if (dev_priv->display.write_eld) |
- | |
6724 | dev_priv->display.write_eld(connector, crtc); |
- | |
6725 | } |
- | |
6726 | - | ||
6727 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
- | |
6728 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
- | |
6729 | { |
- | |
6730 | struct drm_device *dev = crtc->dev; |
- | |
6731 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
6733 | enum pipe pipe = intel_crtc->pipe; |
- | |
6734 | int palreg = PALETTE(pipe); |
- | |
6735 | int i; |
- | |
6736 | bool reenable_ips = false; |
- | |
6737 | - | ||
6738 | /* The clocks have to be on to load the palette. */ |
- | |
6739 | if (!crtc->enabled || !intel_crtc->active) |
- | |
6740 | return; |
- | |
6741 | - | ||
6742 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
- | |
6743 | assert_pll_enabled(dev_priv, pipe); |
- | |
6744 | - | ||
6745 | /* use legacy palette for Ironlake */ |
- | |
6746 | if (HAS_PCH_SPLIT(dev)) |
- | |
6747 | palreg = LGC_PALETTE(pipe); |
- | |
6748 | - | ||
6749 | /* Workaround : Do not read or write the pipe palette/gamma data while |
- | |
6750 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
- | |
6751 | */ |
- | |
6752 | if (intel_crtc->config.ips_enabled && |
- | |
6753 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
- | |
6754 | GAMMA_MODE_MODE_SPLIT)) { |
- | |
6755 | hsw_disable_ips(intel_crtc); |
7391 | if (dev_priv->display.write_eld) |
Line 6756... | Line -... | ||
6756 | reenable_ips = true; |
- | |
6757 | } |
- | |
6758 | - | ||
6759 | for (i = 0; i < 256; i++) { |
- | |
6760 | I915_WRITE(palreg + 4 * i, |
- | |
6761 | (intel_crtc->lut_r[i] << 16) | |
- | |
6762 | (intel_crtc->lut_g[i] << 8) | |
- | |
6763 | intel_crtc->lut_b[i]); |
- | |
6764 | } |
- | |
6765 | - | ||
6766 | if (reenable_ips) |
- | |
6767 | hsw_enable_ips(intel_crtc); |
- | |
6768 | } |
7392 | dev_priv->display.write_eld(connector, crtc, mode); |
6769 | 7393 | } |
|
6770 | #if 0 |
7394 | |
6771 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7395 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6772 | { |
7396 | { |
Line 6795... | Line 7419... | ||
6795 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
7419 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
6796 | I915_WRITE(_CURACNTR, cntl); |
7420 | I915_WRITE(_CURACNTR, cntl); |
Line 6797... | Line 7421... | ||
6797 | 7421 | ||
6798 | intel_crtc->cursor_visible = visible; |
7422 | intel_crtc->cursor_visible = visible; |
6799 | } |
- | |
Line 6800... | Line 7423... | ||
6800 | #endif |
7423 | } |
6801 | 7424 | ||
6802 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
7425 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6803 | { |
7426 | { |
Line 6842... | Line 7465... | ||
6842 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
7465 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6843 | } else { |
7466 | } else { |
6844 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
7467 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6845 | cntl |= CURSOR_MODE_DISABLE; |
7468 | cntl |= CURSOR_MODE_DISABLE; |
6846 | } |
7469 | } |
6847 | if (IS_HASWELL(dev)) { |
7470 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
6848 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
7471 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
6849 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7472 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6850 | } |
7473 | } |
6851 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7474 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
Line 6866... | Line 7489... | ||
6866 | struct drm_i915_private *dev_priv = dev->dev_private; |
7489 | struct drm_i915_private *dev_priv = dev->dev_private; |
6867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6868 | int pipe = intel_crtc->pipe; |
7491 | int pipe = intel_crtc->pipe; |
6869 | int x = intel_crtc->cursor_x; |
7492 | int x = intel_crtc->cursor_x; |
6870 | int y = intel_crtc->cursor_y; |
7493 | int y = intel_crtc->cursor_y; |
6871 | u32 base, pos; |
7494 | u32 base = 0, pos = 0; |
6872 | bool visible; |
7495 | bool visible; |
Line 6873... | Line 7496... | ||
6873 | 7496 | ||
6874 | pos = 0; |
- | |
6875 | - | ||
6876 | if (on && crtc->enabled && crtc->fb) { |
7497 | if (on) |
6877 | base = intel_crtc->cursor_addr; |
- | |
6878 | if (x > (int) crtc->fb->width) |
- | |
Line 6879... | Line 7498... | ||
6879 | base = 0; |
7498 | base = intel_crtc->cursor_addr; |
6880 | 7499 | ||
6881 | if (y > (int) crtc->fb->height) |
7500 | if (x >= intel_crtc->config.pipe_src_w) |
- | 7501 | base = 0; |
|
6882 | base = 0; |
7502 | |
Line 6883... | Line 7503... | ||
6883 | } else |
7503 | if (y >= intel_crtc->config.pipe_src_h) |
6884 | base = 0; |
7504 | base = 0; |
6885 | 7505 | ||
Line 6886... | Line 7506... | ||
6886 | if (x < 0) { |
7506 | if (x < 0) { |
6887 | if (x + intel_crtc->cursor_width < 0) |
7507 | if (x + intel_crtc->cursor_width <= 0) |
6888 | base = 0; |
7508 | base = 0; |
6889 | 7509 | ||
Line 6890... | Line 7510... | ||
6890 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
7510 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6891 | x = -x; |
7511 | x = -x; |
6892 | } |
7512 | } |
Line 6893... | Line 7513... | ||
6893 | pos |= x << CURSOR_X_SHIFT; |
7513 | pos |= x << CURSOR_X_SHIFT; |
6894 | 7514 | ||
6895 | if (y < 0) { |
7515 | if (y < 0) { |
Line 6903... | Line 7523... | ||
6903 | 7523 | ||
6904 | visible = base != 0; |
7524 | visible = base != 0; |
6905 | if (!visible && !intel_crtc->cursor_visible) |
7525 | if (!visible && !intel_crtc->cursor_visible) |
Line 6906... | Line 7526... | ||
6906 | return; |
7526 | return; |
6907 | 7527 | ||
6908 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
7528 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
6909 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7529 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6910 | ivb_update_cursor(crtc, base); |
7530 | ivb_update_cursor(crtc, base); |
6911 | } else { |
7531 | } else { |
Line 7033... | Line 7653... | ||
7033 | 7653 | ||
7034 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7654 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7035 | { |
7655 | { |
Line 7036... | Line 7656... | ||
7036 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7037 | 7657 | ||
Line 7038... | Line 7658... | ||
7038 | intel_crtc->cursor_x = x; |
7658 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7039 | intel_crtc->cursor_y = y; |
7659 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); |
Line 7040... | Line 7660... | ||
7040 | 7660 | ||
7041 | if (intel_crtc->active) |
7661 | if (intel_crtc->active) |
Line 7042... | Line -... | ||
7042 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
- | |
7043 | - | ||
7044 | return 0; |
- | |
7045 | } |
- | |
7046 | - | ||
7047 | /** Sets the color ramps on behalf of RandR */ |
- | |
7048 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
- | |
7049 | u16 blue, int regno) |
- | |
7050 | { |
- | |
7051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7052 | - | ||
7053 | intel_crtc->lut_r[regno] = red >> 8; |
- | |
7054 | intel_crtc->lut_g[regno] = green >> 8; |
- | |
7055 | intel_crtc->lut_b[regno] = blue >> 8; |
- | |
7056 | } |
- | |
7057 | - | ||
7058 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
- | |
7059 | u16 *blue, int regno) |
- | |
7060 | { |
- | |
7061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
7062 | - | ||
7063 | *red = intel_crtc->lut_r[regno] << 8; |
7662 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7064 | *green = intel_crtc->lut_g[regno] << 8; |
7663 | |
7065 | *blue = intel_crtc->lut_b[regno] << 8; |
7664 | return 0; |
7066 | } |
7665 | } |
7067 | 7666 | ||
Line 7084... | Line 7683... | ||
7084 | static struct drm_display_mode load_detect_mode = { |
7683 | static struct drm_display_mode load_detect_mode = { |
7085 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7684 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7086 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7685 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7087 | }; |
7686 | }; |
Line 7088... | Line 7687... | ||
7088 | 7687 | ||
7089 | static struct drm_framebuffer * |
7688 | struct drm_framebuffer * |
7090 | intel_framebuffer_create(struct drm_device *dev, |
7689 | intel_framebuffer_create(struct drm_device *dev, |
7091 | struct drm_mode_fb_cmd2 *mode_cmd, |
7690 | struct drm_mode_fb_cmd2 *mode_cmd, |
7092 | struct drm_i915_gem_object *obj) |
7691 | struct drm_i915_gem_object *obj) |
7093 | { |
7692 | { |
Line 7098... | Line 7697... | ||
7098 | if (!intel_fb) { |
7697 | if (!intel_fb) { |
7099 | drm_gem_object_unreference_unlocked(&obj->base); |
7698 | drm_gem_object_unreference_unlocked(&obj->base); |
7100 | return ERR_PTR(-ENOMEM); |
7699 | return ERR_PTR(-ENOMEM); |
7101 | } |
7700 | } |
Line -... | Line 7701... | ||
- | 7701 | ||
- | 7702 | ret = i915_mutex_lock_interruptible(dev); |
|
- | 7703 | if (ret) |
|
- | 7704 | goto err; |
|
7102 | 7705 | ||
- | 7706 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
|
7103 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7707 | mutex_unlock(&dev->struct_mutex); |
- | 7708 | if (ret) |
|
- | 7709 | goto err; |
|
- | 7710 | ||
- | 7711 | return &intel_fb->base; |
|
7104 | if (ret) { |
7712 | err: |
7105 | drm_gem_object_unreference_unlocked(&obj->base); |
7713 | drm_gem_object_unreference_unlocked(&obj->base); |
7106 | kfree(intel_fb); |
- | |
7107 | return ERR_PTR(ret); |
- | |
Line 7108... | Line 7714... | ||
7108 | } |
7714 | kfree(intel_fb); |
7109 | 7715 | ||
Line 7110... | Line 7716... | ||
7110 | return &intel_fb->base; |
7716 | return ERR_PTR(ret); |
7111 | } |
7717 | } |
7112 | 7718 | ||
Line 7137... | Line 7743... | ||
7137 | 7743 | ||
7138 | static struct drm_framebuffer * |
7744 | static struct drm_framebuffer * |
7139 | mode_fits_in_fbdev(struct drm_device *dev, |
7745 | mode_fits_in_fbdev(struct drm_device *dev, |
7140 | struct drm_display_mode *mode) |
7746 | struct drm_display_mode *mode) |
- | 7747 | { |
|
7141 | { |
7748 | #ifdef CONFIG_DRM_I915_FBDEV |
7142 | struct drm_i915_private *dev_priv = dev->dev_private; |
7749 | struct drm_i915_private *dev_priv = dev->dev_private; |
7143 | struct drm_i915_gem_object *obj; |
7750 | struct drm_i915_gem_object *obj; |
Line 7144... | Line 7751... | ||
7144 | struct drm_framebuffer *fb; |
7751 | struct drm_framebuffer *fb; |
Line 7157... | Line 7764... | ||
7157 | 7764 | ||
7158 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7765 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Line 7159... | Line 7766... | ||
7159 | return NULL; |
7766 | return NULL; |
- | 7767 | ||
- | 7768 | return fb; |
|
- | 7769 | #else |
|
7160 | 7770 | return NULL; |
|
Line 7161... | Line 7771... | ||
7161 | return fb; |
7771 | #endif |
7162 | } |
7772 | } |
7163 | 7773 | ||
Line 7300... | Line 7910... | ||
7300 | connector->funcs->dpms(connector, old->dpms_mode); |
7910 | connector->funcs->dpms(connector, old->dpms_mode); |
Line 7301... | Line 7911... | ||
7301 | 7911 | ||
7302 | mutex_unlock(&crtc->mutex); |
7912 | mutex_unlock(&crtc->mutex); |
Line -... | Line 7913... | ||
- | 7913 | } |
|
- | 7914 | ||
- | 7915 | static int i9xx_pll_refclk(struct drm_device *dev, |
|
- | 7916 | const struct intel_crtc_config *pipe_config) |
|
- | 7917 | { |
|
- | 7918 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7919 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
|
- | 7920 | ||
- | 7921 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
|
- | 7922 | return dev_priv->vbt.lvds_ssc_freq; |
|
- | 7923 | else if (HAS_PCH_SPLIT(dev)) |
|
- | 7924 | return 120000; |
|
- | 7925 | else if (!IS_GEN2(dev)) |
|
- | 7926 | return 96000; |
|
- | 7927 | else |
|
- | 7928 | return 48000; |
|
7303 | } |
7929 | } |
7304 | 7930 | ||
7305 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7931 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7306 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7932 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7307 | struct intel_crtc_config *pipe_config) |
7933 | struct intel_crtc_config *pipe_config) |
7308 | { |
7934 | { |
7309 | struct drm_device *dev = crtc->base.dev; |
7935 | struct drm_device *dev = crtc->base.dev; |
7310 | struct drm_i915_private *dev_priv = dev->dev_private; |
7936 | struct drm_i915_private *dev_priv = dev->dev_private; |
7311 | int pipe = pipe_config->cpu_transcoder; |
7937 | int pipe = pipe_config->cpu_transcoder; |
7312 | u32 dpll = I915_READ(DPLL(pipe)); |
7938 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
- | 7939 | u32 fp; |
|
Line 7313... | Line 7940... | ||
7313 | u32 fp; |
7940 | intel_clock_t clock; |
7314 | intel_clock_t clock; |
7941 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
7315 | 7942 | ||
7316 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7943 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Line 7317... | Line 7944... | ||
7317 | fp = I915_READ(FP0(pipe)); |
7944 | fp = pipe_config->dpll_hw_state.fp0; |
7318 | else |
7945 | else |
7319 | fp = I915_READ(FP1(pipe)); |
7946 | fp = pipe_config->dpll_hw_state.fp1; |
7320 | 7947 | ||
Line 7345... | Line 7972... | ||
7345 | 7 : 14; |
7972 | 7 : 14; |
7346 | break; |
7973 | break; |
7347 | default: |
7974 | default: |
7348 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7975 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7349 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7976 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7350 | pipe_config->adjusted_mode.clock = 0; |
- | |
7351 | return; |
7977 | return; |
7352 | } |
7978 | } |
Line 7353... | Line 7979... | ||
7353 | 7979 | ||
7354 | if (IS_PINEVIEW(dev)) |
7980 | if (IS_PINEVIEW(dev)) |
7355 | pineview_clock(96000, &clock); |
7981 | pineview_clock(refclk, &clock); |
7356 | else |
7982 | else |
7357 | i9xx_clock(96000, &clock); |
7983 | i9xx_clock(refclk, &clock); |
- | 7984 | } else { |
|
7358 | } else { |
7985 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
Line 7359... | Line 7986... | ||
7359 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
7986 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
7360 | 7987 | ||
7361 | if (is_lvds) { |
7988 | if (is_lvds) { |
7362 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
- | |
Line 7363... | Line 7989... | ||
7363 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7989 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7364 | clock.p2 = 14; |
- | |
7365 | - | ||
7366 | if ((dpll & PLL_REF_INPUT_MASK) == |
7990 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7367 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
7991 | |
7368 | /* XXX: might not be 66MHz */ |
7992 | if (lvds & LVDS_CLKB_POWER_UP) |
7369 | i9xx_clock(66000, &clock); |
7993 | clock.p2 = 7; |
7370 | } else |
7994 | else |
7371 | i9xx_clock(48000, &clock); |
7995 | clock.p2 = 14; |
7372 | } else { |
7996 | } else { |
7373 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7997 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
Line 7378... | Line 8002... | ||
7378 | } |
8002 | } |
7379 | if (dpll & PLL_P2_DIVIDE_BY_4) |
8003 | if (dpll & PLL_P2_DIVIDE_BY_4) |
7380 | clock.p2 = 4; |
8004 | clock.p2 = 4; |
7381 | else |
8005 | else |
7382 | clock.p2 = 2; |
8006 | clock.p2 = 2; |
7383 | - | ||
7384 | i9xx_clock(48000, &clock); |
- | |
7385 | } |
8007 | } |
- | 8008 | ||
- | 8009 | i9xx_clock(refclk, &clock); |
|
7386 | } |
8010 | } |
Line -... | Line 8011... | ||
- | 8011 | ||
- | 8012 | /* |
|
- | 8013 | * This value includes pixel_multiplier. We will use |
|
- | 8014 | * port_clock to compute adjusted_mode.crtc_clock in the |
|
- | 8015 | * encoder's get_config() function. |
|
7387 | 8016 | */ |
|
7388 | pipe_config->adjusted_mode.clock = clock.dot; |
8017 | pipe_config->port_clock = clock.dot; |
Line 7389... | Line 8018... | ||
7389 | } |
8018 | } |
7390 | 8019 | ||
7391 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
8020 | int intel_dotclock_calculate(int link_freq, |
7392 | struct intel_crtc_config *pipe_config) |
- | |
7393 | { |
- | |
7394 | struct drm_device *dev = crtc->base.dev; |
- | |
7395 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
7396 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
- | |
7397 | int link_freq, repeat; |
- | |
7398 | u64 clock; |
- | |
7399 | u32 link_m, link_n; |
- | |
7400 | - | ||
7401 | repeat = pipe_config->pixel_multiplier; |
8021 | const struct intel_link_m_n *m_n) |
7402 | 8022 | { |
|
7403 | /* |
8023 | /* |
7404 | * The calculation for the data clock is: |
8024 | * The calculation for the data clock is: |
7405 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
8025 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
7406 | * But we want to avoid losing precison if possible, so: |
8026 | * But we want to avoid losing precison if possible, so: |
7407 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
8027 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
7408 | * |
8028 | * |
7409 | * and the link clock is simpler: |
8029 | * and the link clock is simpler: |
Line 7410... | Line -... | ||
7410 | * link_clock = (m * link_clock * repeat) / n |
- | |
7411 | */ |
- | |
7412 | - | ||
7413 | /* |
- | |
7414 | * We need to get the FDI or DP link clock here to derive |
- | |
7415 | * the M/N dividers. |
- | |
7416 | * |
- | |
7417 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
- | |
7418 | * For DP, it's either 1.62GHz or 2.7GHz. |
8030 | * link_clock = (m * link_clock) / n |
7419 | * We do our calculations in 10*MHz since we don't need much precison. |
- | |
7420 | */ |
8031 | */ |
7421 | if (pipe_config->has_pch_encoder) |
- | |
Line 7422... | Line -... | ||
7422 | link_freq = intel_fdi_link_freq(dev) * 10000; |
- | |
7423 | else |
8032 | |
- | 8033 | if (!m_n->link_n) |
|
Line -... | Line 8034... | ||
- | 8034 | return 0; |
|
7424 | link_freq = pipe_config->port_clock; |
8035 | |
7425 | 8036 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
|
- | 8037 | } |
|
Line 7426... | Line 8038... | ||
7426 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
8038 | |
7427 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
8039 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Line -... | Line 8040... | ||
- | 8040 | struct intel_crtc_config *pipe_config) |
|
- | 8041 | { |
|
- | 8042 | struct drm_device *dev = crtc->base.dev; |
|
- | 8043 | ||
- | 8044 | /* read out port_clock from the DPLL */ |
|
- | 8045 | i9xx_crtc_clock_get(crtc, pipe_config); |
|
7428 | 8046 | ||
- | 8047 | /* |
|
- | 8048 | * This value does not include pixel_multiplier. |
|
7429 | if (!link_m || !link_n) |
8049 | * We will check that port_clock and adjusted_mode.crtc_clock |
Line 7430... | Line 8050... | ||
7430 | return; |
8050 | * agree once we know their relationship in the encoder's |
7431 | 8051 | * get_config() function. |
|
7432 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
8052 | */ |
Line 7446... | Line 8066... | ||
7446 | struct intel_crtc_config pipe_config; |
8066 | struct intel_crtc_config pipe_config; |
7447 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8067 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7448 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
8068 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
7449 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
8069 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
7450 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
8070 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
- | 8071 | enum pipe pipe = intel_crtc->pipe; |
|
Line 7451... | Line 8072... | ||
7451 | 8072 | ||
7452 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
8073 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7453 | if (!mode) |
8074 | if (!mode) |
Line 7458... | Line 8079... | ||
7458 | * back out of crtc_clock_get. |
8079 | * back out of crtc_clock_get. |
7459 | * |
8080 | * |
7460 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
8081 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
7461 | * to use a real value here instead. |
8082 | * to use a real value here instead. |
7462 | */ |
8083 | */ |
7463 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
8084 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
7464 | pipe_config.pixel_multiplier = 1; |
8085 | pipe_config.pixel_multiplier = 1; |
- | 8086 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
|
- | 8087 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
|
- | 8088 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
|
7465 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8089 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
Line 7466... | Line 8090... | ||
7466 | 8090 | ||
7467 | mode->clock = pipe_config.adjusted_mode.clock; |
8091 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
7468 | mode->hdisplay = (htot & 0xffff) + 1; |
8092 | mode->hdisplay = (htot & 0xffff) + 1; |
7469 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
8093 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
7470 | mode->hsync_start = (hsync & 0xffff) + 1; |
8094 | mode->hsync_start = (hsync & 0xffff) + 1; |
7471 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
8095 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
Line 7568... | Line 8192... | ||
7568 | if (!crtc->fb) |
8192 | if (!crtc->fb) |
7569 | continue; |
8193 | continue; |
Line 7570... | Line 8194... | ||
7570 | 8194 | ||
7571 | intel_decrease_pllclock(crtc); |
8195 | intel_decrease_pllclock(crtc); |
- | 8196 | } |
|
- | 8197 | ||
- | 8198 | if (dev_priv->info->gen >= 6) |
|
7572 | } |
8199 | gen6_rps_idle(dev->dev_private); |
Line 7573... | Line 8200... | ||
7573 | } |
8200 | } |
7574 | 8201 | ||
7575 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8202 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
Line 7755... | Line 8382... | ||
7755 | intel_ring_emit(ring, fb->pitches[0]); |
8382 | intel_ring_emit(ring, fb->pitches[0]); |
7756 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8383 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7757 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
8384 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Line 7758... | Line 8385... | ||
7758 | 8385 | ||
7759 | intel_mark_page_flip_active(intel_crtc); |
8386 | intel_mark_page_flip_active(intel_crtc); |
7760 | intel_ring_advance(ring); |
8387 | __intel_ring_advance(ring); |
Line 7761... | Line 8388... | ||
7761 | return 0; |
8388 | return 0; |
7762 | 8389 | ||
7763 | err_unpin: |
8390 | err_unpin: |
Line 7797... | Line 8424... | ||
7797 | intel_ring_emit(ring, fb->pitches[0]); |
8424 | intel_ring_emit(ring, fb->pitches[0]); |
7798 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8425 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7799 | intel_ring_emit(ring, MI_NOOP); |
8426 | intel_ring_emit(ring, MI_NOOP); |
Line 7800... | Line 8427... | ||
7800 | 8427 | ||
7801 | intel_mark_page_flip_active(intel_crtc); |
8428 | intel_mark_page_flip_active(intel_crtc); |
7802 | intel_ring_advance(ring); |
8429 | __intel_ring_advance(ring); |
Line 7803... | Line 8430... | ||
7803 | return 0; |
8430 | return 0; |
7804 | 8431 | ||
7805 | err_unpin: |
8432 | err_unpin: |
Line 7846... | Line 8473... | ||
7846 | pf = 0; |
8473 | pf = 0; |
7847 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8474 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7848 | intel_ring_emit(ring, pf | pipesrc); |
8475 | intel_ring_emit(ring, pf | pipesrc); |
Line 7849... | Line 8476... | ||
7849 | 8476 | ||
7850 | intel_mark_page_flip_active(intel_crtc); |
8477 | intel_mark_page_flip_active(intel_crtc); |
7851 | intel_ring_advance(ring); |
8478 | __intel_ring_advance(ring); |
Line 7852... | Line 8479... | ||
7852 | return 0; |
8479 | return 0; |
7853 | 8480 | ||
7854 | err_unpin: |
8481 | err_unpin: |
Line 7891... | Line 8518... | ||
7891 | pf = 0; |
8518 | pf = 0; |
7892 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8519 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7893 | intel_ring_emit(ring, pf | pipesrc); |
8520 | intel_ring_emit(ring, pf | pipesrc); |
Line 7894... | Line 8521... | ||
7894 | 8521 | ||
7895 | intel_mark_page_flip_active(intel_crtc); |
8522 | intel_mark_page_flip_active(intel_crtc); |
7896 | intel_ring_advance(ring); |
8523 | __intel_ring_advance(ring); |
Line 7897... | Line 8524... | ||
7897 | return 0; |
8524 | return 0; |
7898 | 8525 | ||
7899 | err_unpin: |
8526 | err_unpin: |
Line 7959... | Line 8586... | ||
7959 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
8586 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
7960 | intel_ring_emit(ring, DERRMR); |
8587 | intel_ring_emit(ring, DERRMR); |
7961 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8588 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
7962 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8589 | DERRMR_PIPEB_PRI_FLIP_DONE | |
7963 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
8590 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
7964 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
8591 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
- | 8592 | MI_SRM_LRM_GLOBAL_GTT); |
|
7965 | intel_ring_emit(ring, DERRMR); |
8593 | intel_ring_emit(ring, DERRMR); |
7966 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
8594 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
7967 | } |
8595 | } |
Line 7968... | Line 8596... | ||
7968 | 8596 | ||
7969 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
8597 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7970 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
8598 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7971 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8599 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Line 7972... | Line 8600... | ||
7972 | intel_ring_emit(ring, (MI_NOOP)); |
8600 | intel_ring_emit(ring, (MI_NOOP)); |
7973 | 8601 | ||
7974 | intel_mark_page_flip_active(intel_crtc); |
8602 | intel_mark_page_flip_active(intel_crtc); |
Line 7975... | Line 8603... | ||
7975 | intel_ring_advance(ring); |
8603 | __intel_ring_advance(ring); |
7976 | return 0; |
8604 | return 0; |
7977 | 8605 | ||
Line 8015... | Line 8643... | ||
8015 | if (INTEL_INFO(dev)->gen > 3 && |
8643 | if (INTEL_INFO(dev)->gen > 3 && |
8016 | (fb->offsets[0] != crtc->fb->offsets[0] || |
8644 | (fb->offsets[0] != crtc->fb->offsets[0] || |
8017 | fb->pitches[0] != crtc->fb->pitches[0])) |
8645 | fb->pitches[0] != crtc->fb->pitches[0])) |
8018 | return -EINVAL; |
8646 | return -EINVAL; |
Line 8019... | Line 8647... | ||
8019 | 8647 | ||
8020 | work = kzalloc(sizeof *work, GFP_KERNEL); |
8648 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
8021 | if (work == NULL) |
8649 | if (work == NULL) |
Line 8022... | Line 8650... | ||
8022 | return -ENOMEM; |
8650 | return -ENOMEM; |
8023 | 8651 | ||
Line 8098... | Line 8726... | ||
8098 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8726 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8099 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8727 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8100 | .load_lut = intel_crtc_load_lut, |
8728 | .load_lut = intel_crtc_load_lut, |
8101 | }; |
8729 | }; |
Line 8102... | Line -... | ||
8102 | - | ||
8103 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
- | |
8104 | struct drm_crtc *crtc) |
- | |
8105 | { |
- | |
8106 | struct drm_device *dev; |
- | |
8107 | struct drm_crtc *tmp; |
- | |
8108 | int crtc_mask = 1; |
- | |
8109 | - | ||
8110 | WARN(!crtc, "checking null crtc?\n"); |
- | |
8111 | - | ||
8112 | dev = crtc->dev; |
- | |
8113 | - | ||
8114 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
- | |
8115 | if (tmp == crtc) |
- | |
8116 | break; |
- | |
8117 | crtc_mask <<= 1; |
- | |
8118 | } |
- | |
8119 | - | ||
8120 | if (encoder->possible_crtcs & crtc_mask) |
- | |
8121 | return true; |
- | |
8122 | return false; |
- | |
8123 | } |
- | |
8124 | 8730 | ||
8125 | /** |
8731 | /** |
8126 | * intel_modeset_update_staged_output_state |
8732 | * intel_modeset_update_staged_output_state |
8127 | * |
8733 | * |
8128 | * Updates the staged output configuration state, e.g. after we've read out the |
8734 | * Updates the staged output configuration state, e.g. after we've read out the |
Line 8251... | Line 8857... | ||
8251 | } |
8857 | } |
Line 8252... | Line 8858... | ||
8252 | 8858 | ||
8253 | return bpp; |
8859 | return bpp; |
Line -... | Line 8860... | ||
- | 8860 | } |
|
- | 8861 | ||
- | 8862 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
|
- | 8863 | { |
|
- | 8864 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
|
- | 8865 | "type: 0x%x flags: 0x%x\n", |
|
- | 8866 | mode->crtc_clock, |
|
- | 8867 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
|
- | 8868 | mode->crtc_hsync_end, mode->crtc_htotal, |
|
- | 8869 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
|
- | 8870 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
|
8254 | } |
8871 | } |
8255 | 8872 | ||
8256 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8873 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8257 | struct intel_crtc_config *pipe_config, |
8874 | struct intel_crtc_config *pipe_config, |
8258 | const char *context) |
8875 | const char *context) |
Line 8267... | Line 8884... | ||
8267 | pipe_config->has_pch_encoder, |
8884 | pipe_config->has_pch_encoder, |
8268 | pipe_config->fdi_lanes, |
8885 | pipe_config->fdi_lanes, |
8269 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8886 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8270 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8887 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8271 | pipe_config->fdi_m_n.tu); |
8888 | pipe_config->fdi_m_n.tu); |
- | 8889 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
|
- | 8890 | pipe_config->has_dp_encoder, |
|
- | 8891 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
|
- | 8892 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
|
- | 8893 | pipe_config->dp_m_n.tu); |
|
8272 | DRM_DEBUG_KMS("requested mode:\n"); |
8894 | DRM_DEBUG_KMS("requested mode:\n"); |
8273 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8895 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8274 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8896 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8275 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8897 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
- | 8898 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
|
- | 8899 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
|
- | 8900 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
|
- | 8901 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
|
8276 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8902 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8277 | pipe_config->gmch_pfit.control, |
8903 | pipe_config->gmch_pfit.control, |
8278 | pipe_config->gmch_pfit.pgm_ratios, |
8904 | pipe_config->gmch_pfit.pgm_ratios, |
8279 | pipe_config->gmch_pfit.lvds_border_bits); |
8905 | pipe_config->gmch_pfit.lvds_border_bits); |
8280 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8906 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8281 | pipe_config->pch_pfit.pos, |
8907 | pipe_config->pch_pfit.pos, |
8282 | pipe_config->pch_pfit.size, |
8908 | pipe_config->pch_pfit.size, |
8283 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8909 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8284 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8910 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
- | 8911 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
|
8285 | } |
8912 | } |
Line 8286... | Line 8913... | ||
8286 | 8913 | ||
8287 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8914 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8288 | { |
8915 | { |
Line 8323... | Line 8950... | ||
8323 | if (!pipe_config) |
8950 | if (!pipe_config) |
8324 | return ERR_PTR(-ENOMEM); |
8951 | return ERR_PTR(-ENOMEM); |
Line 8325... | Line 8952... | ||
8325 | 8952 | ||
8326 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8953 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
- | 8954 | drm_mode_copy(&pipe_config->requested_mode, mode); |
|
8327 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8955 | |
8328 | pipe_config->cpu_transcoder = |
8956 | pipe_config->cpu_transcoder = |
8329 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8957 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
Line 8330... | Line 8958... | ||
8330 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8958 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Line 8349... | Line 8977... | ||
8349 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8977 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8350 | fb, pipe_config); |
8978 | fb, pipe_config); |
8351 | if (plane_bpp < 0) |
8979 | if (plane_bpp < 0) |
8352 | goto fail; |
8980 | goto fail; |
Line -... | Line 8981... | ||
- | 8981 | ||
- | 8982 | /* |
|
- | 8983 | * Determine the real pipe dimensions. Note that stereo modes can |
|
- | 8984 | * increase the actual pipe size due to the frame doubling and |
|
- | 8985 | * insertion of additional space for blanks between the frame. This |
|
- | 8986 | * is stored in the crtc timings. We use the requested mode to do this |
|
- | 8987 | * computation to clearly distinguish it from the adjusted mode, which |
|
- | 8988 | * can be changed by the connectors in the below retry loop. |
|
- | 8989 | */ |
|
- | 8990 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
|
- | 8991 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
|
- | 8992 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
|
8353 | 8993 | ||
8354 | encoder_retry: |
8994 | encoder_retry: |
8355 | /* Ensure the port clock defaults are reset when retrying. */ |
8995 | /* Ensure the port clock defaults are reset when retrying. */ |
8356 | pipe_config->port_clock = 0; |
8996 | pipe_config->port_clock = 0; |
Line 8357... | Line 8997... | ||
8357 | pipe_config->pixel_multiplier = 1; |
8997 | pipe_config->pixel_multiplier = 1; |
8358 | 8998 | ||
Line 8359... | Line 8999... | ||
8359 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8999 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8360 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
9000 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
8361 | 9001 | ||
8362 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9002 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
Line 8376... | Line 9016... | ||
8376 | } |
9016 | } |
Line 8377... | Line 9017... | ||
8377 | 9017 | ||
8378 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9018 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8379 | * done afterwards in case the encoder adjusts the mode. */ |
9019 | * done afterwards in case the encoder adjusts the mode. */ |
8380 | if (!pipe_config->port_clock) |
9020 | if (!pipe_config->port_clock) |
- | 9021 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
|
Line 8381... | Line 9022... | ||
8381 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
9022 | * pipe_config->pixel_multiplier; |
8382 | 9023 | ||
8383 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
9024 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8384 | if (ret < 0) { |
9025 | if (ret < 0) { |
Line 8563... | Line 9204... | ||
8563 | } |
9204 | } |
8564 | } |
9205 | } |
Line 8565... | Line 9206... | ||
8565 | 9206 | ||
Line 8566... | Line 9207... | ||
8566 | } |
9207 | } |
8567 | - | ||
8568 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
9208 | |
8569 | struct intel_crtc_config *new) |
9209 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
8570 | { |
- | |
8571 | int clock1, clock2, diff; |
- | |
8572 | - | ||
Line 8573... | Line 9210... | ||
8573 | clock1 = cur->adjusted_mode.clock; |
9210 | { |
8574 | clock2 = new->adjusted_mode.clock; |
9211 | int diff; |
Line 8575... | Line 9212... | ||
8575 | 9212 | ||
Line 8623... | Line 9260... | ||
8623 | current_config->name & (mask), \ |
9260 | current_config->name & (mask), \ |
8624 | pipe_config->name & (mask)); \ |
9261 | pipe_config->name & (mask)); \ |
8625 | return false; \ |
9262 | return false; \ |
8626 | } |
9263 | } |
Line -... | Line 9264... | ||
- | 9264 | ||
- | 9265 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
|
- | 9266 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
|
- | 9267 | DRM_ERROR("mismatch in " #name " " \ |
|
- | 9268 | "(expected %i, found %i)\n", \ |
|
- | 9269 | current_config->name, \ |
|
- | 9270 | pipe_config->name); \ |
|
- | 9271 | return false; \ |
|
- | 9272 | } |
|
8627 | 9273 | ||
8628 | #define PIPE_CONF_QUIRK(quirk) \ |
9274 | #define PIPE_CONF_QUIRK(quirk) \ |
Line 8629... | Line 9275... | ||
8629 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
9275 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
Line 8636... | Line 9282... | ||
8636 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
9282 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
8637 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
9283 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
8638 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
9284 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
8639 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
9285 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
Line -... | Line 9286... | ||
- | 9286 | ||
- | 9287 | PIPE_CONF_CHECK_I(has_dp_encoder); |
|
- | 9288 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
|
- | 9289 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
|
- | 9290 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
|
- | 9291 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
|
- | 9292 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
|
8640 | 9293 | ||
8641 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9294 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8642 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
9295 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
8643 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
9296 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
8644 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
9297 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
Line 8666... | Line 9319... | ||
8666 | DRM_MODE_FLAG_PVSYNC); |
9319 | DRM_MODE_FLAG_PVSYNC); |
8667 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9320 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8668 | DRM_MODE_FLAG_NVSYNC); |
9321 | DRM_MODE_FLAG_NVSYNC); |
8669 | } |
9322 | } |
Line 8670... | Line 9323... | ||
8670 | 9323 | ||
8671 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
9324 | PIPE_CONF_CHECK_I(pipe_src_w); |
Line 8672... | Line 9325... | ||
8672 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
9325 | PIPE_CONF_CHECK_I(pipe_src_h); |
8673 | 9326 | ||
8674 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9327 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8675 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
9328 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
Line 8680... | Line 9333... | ||
8680 | if (current_config->pch_pfit.enabled) { |
9333 | if (current_config->pch_pfit.enabled) { |
8681 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
9334 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
8682 | PIPE_CONF_CHECK_I(pch_pfit.size); |
9335 | PIPE_CONF_CHECK_I(pch_pfit.size); |
8683 | } |
9336 | } |
Line -... | Line 9337... | ||
- | 9337 | ||
- | 9338 | /* BDW+ don't expose a synchronous way to read the state */ |
|
8684 | 9339 | if (IS_HASWELL(dev)) |
|
Line -... | Line 9340... | ||
- | 9340 | PIPE_CONF_CHECK_I(ips_enabled); |
|
- | 9341 | ||
8685 | PIPE_CONF_CHECK_I(ips_enabled); |
9342 | PIPE_CONF_CHECK_I(double_wide); |
8686 | 9343 | ||
8687 | PIPE_CONF_CHECK_I(shared_dpll); |
9344 | PIPE_CONF_CHECK_I(shared_dpll); |
8688 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
9345 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8689 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
9346 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
Line 8690... | Line 9347... | ||
8690 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9347 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8691 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
9348 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Line -... | Line 9349... | ||
- | 9349 | ||
- | 9350 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
|
- | 9351 | PIPE_CONF_CHECK_I(pipe_bpp); |
|
- | 9352 | ||
- | 9353 | if (!HAS_DDI(dev)) { |
|
8692 | 9354 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
|
8693 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9355 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
8694 | PIPE_CONF_CHECK_I(pipe_bpp); |
9356 | } |
- | 9357 | ||
8695 | 9358 | #undef PIPE_CONF_CHECK_X |
|
Line 8696... | Line -... | ||
8696 | #undef PIPE_CONF_CHECK_X |
- | |
8697 | #undef PIPE_CONF_CHECK_I |
- | |
8698 | #undef PIPE_CONF_CHECK_FLAGS |
- | |
8699 | #undef PIPE_CONF_QUIRK |
- | |
8700 | - | ||
8701 | if (!IS_HASWELL(dev)) { |
- | |
8702 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
- | |
8703 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
- | |
8704 | current_config->adjusted_mode.clock, |
- | |
8705 | pipe_config->adjusted_mode.clock); |
9359 | #undef PIPE_CONF_CHECK_I |
8706 | return false; |
9360 | #undef PIPE_CONF_CHECK_FLAGS |
Line 8707... | Line 9361... | ||
8707 | } |
9361 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
8708 | } |
9362 | #undef PIPE_CONF_QUIRK |
Line 8831... | Line 9485... | ||
8831 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9485 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8832 | base.head) { |
9486 | base.head) { |
8833 | enum pipe pipe; |
9487 | enum pipe pipe; |
8834 | if (encoder->base.crtc != &crtc->base) |
9488 | if (encoder->base.crtc != &crtc->base) |
8835 | continue; |
9489 | continue; |
8836 | if (encoder->get_config && |
- | |
8837 | encoder->get_hw_state(encoder, &pipe)) |
9490 | if (encoder->get_hw_state(encoder, &pipe)) |
8838 | encoder->get_config(encoder, &pipe_config); |
9491 | encoder->get_config(encoder, &pipe_config); |
8839 | } |
9492 | } |
Line 8840... | Line -... | ||
8840 | - | ||
8841 | if (dev_priv->display.get_clock) |
- | |
8842 | dev_priv->display.get_clock(crtc, &pipe_config); |
- | |
8843 | 9493 | ||
8844 | WARN(crtc->active != active, |
9494 | WARN(crtc->active != active, |
8845 | "crtc active state doesn't match with hw state " |
9495 | "crtc active state doesn't match with hw state " |
Line 8846... | Line 9496... | ||
8846 | "(expected %i, found %i)\n", crtc->active, active); |
9496 | "(expected %i, found %i)\n", crtc->active, active); |
Line 8913... | Line 9563... | ||
8913 | check_encoder_state(dev); |
9563 | check_encoder_state(dev); |
8914 | check_crtc_state(dev); |
9564 | check_crtc_state(dev); |
8915 | check_shared_dpll_state(dev); |
9565 | check_shared_dpll_state(dev); |
8916 | } |
9566 | } |
Line -... | Line 9567... | ||
- | 9567 | ||
- | 9568 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
|
- | 9569 | int dotclock) |
|
- | 9570 | { |
|
- | 9571 | /* |
|
- | 9572 | * FDI already provided one idea for the dotclock. |
|
- | 9573 | * Yell if the encoder disagrees. |
|
- | 9574 | */ |
|
- | 9575 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
|
- | 9576 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
|
- | 9577 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
|
- | 9578 | } |
|
8917 | 9579 | ||
8918 | static int __intel_set_mode(struct drm_crtc *crtc, |
9580 | static int __intel_set_mode(struct drm_crtc *crtc, |
8919 | struct drm_display_mode *mode, |
9581 | struct drm_display_mode *mode, |
8920 | int x, int y, struct drm_framebuffer *fb) |
9582 | int x, int y, struct drm_framebuffer *fb) |
8921 | { |
9583 | { |
8922 | struct drm_device *dev = crtc->dev; |
9584 | struct drm_device *dev = crtc->dev; |
8923 | drm_i915_private_t *dev_priv = dev->dev_private; |
9585 | drm_i915_private_t *dev_priv = dev->dev_private; |
8924 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9586 | struct drm_display_mode *saved_mode; |
8925 | struct intel_crtc_config *pipe_config = NULL; |
9587 | struct intel_crtc_config *pipe_config = NULL; |
8926 | struct intel_crtc *intel_crtc; |
9588 | struct intel_crtc *intel_crtc; |
8927 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
9589 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
Line 8928... | Line 9590... | ||
8928 | int ret = 0; |
9590 | int ret = 0; |
8929 | 9591 | ||
8930 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
9592 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
8931 | if (!saved_mode) |
- | |
Line 8932... | Line 9593... | ||
8932 | return -ENOMEM; |
9593 | if (!saved_mode) |
8933 | saved_hwmode = saved_mode + 1; |
9594 | return -ENOMEM; |
Line 8934... | Line -... | ||
8934 | - | ||
8935 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
9595 | |
Line 8936... | Line 9596... | ||
8936 | &prepare_pipes, &disable_pipes); |
9596 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8937 | 9597 | &prepare_pipes, &disable_pipes); |
|
8938 | *saved_hwmode = crtc->hwmode; |
9598 | |
Line 8953... | Line 9613... | ||
8953 | } |
9613 | } |
8954 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9614 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8955 | "[modeset]"); |
9615 | "[modeset]"); |
8956 | } |
9616 | } |
Line -... | Line 9617... | ||
- | 9617 | ||
- | 9618 | /* |
|
- | 9619 | * See if the config requires any additional preparation, e.g. |
|
- | 9620 | * to adjust global state with pipes off. We need to do this |
|
- | 9621 | * here so we can get the modeset_pipe updated config for the new |
|
- | 9622 | * mode set on this crtc. For other crtcs we need to use the |
|
- | 9623 | * adjusted_mode bits in the crtc directly. |
|
- | 9624 | */ |
|
- | 9625 | if (IS_VALLEYVIEW(dev)) { |
|
- | 9626 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
|
- | 9627 | modeset_pipes, pipe_config); |
|
- | 9628 | ||
- | 9629 | /* may have added more to prepare_pipes than we should */ |
|
- | 9630 | prepare_pipes &= ~disable_pipes; |
|
- | 9631 | } |
|
8957 | 9632 | ||
8958 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9633 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
Line 8959... | Line 9634... | ||
8959 | intel_crtc_disable(&intel_crtc->base); |
9634 | intel_crtc_disable(&intel_crtc->base); |
8960 | 9635 | ||
Line 8969... | Line 9644... | ||
8969 | if (modeset_pipes) { |
9644 | if (modeset_pipes) { |
8970 | crtc->mode = *mode; |
9645 | crtc->mode = *mode; |
8971 | /* mode_set/enable/disable functions rely on a correct pipe |
9646 | /* mode_set/enable/disable functions rely on a correct pipe |
8972 | * config. */ |
9647 | * config. */ |
8973 | to_intel_crtc(crtc)->config = *pipe_config; |
9648 | to_intel_crtc(crtc)->config = *pipe_config; |
- | 9649 | ||
- | 9650 | /* |
|
- | 9651 | * Calculate and store various constants which |
|
- | 9652 | * are later needed by vblank and swap-completion |
|
- | 9653 | * timestamping. They are derived from true hwmode. |
|
- | 9654 | */ |
|
- | 9655 | drm_calc_timestamping_constants(crtc, |
|
- | 9656 | &pipe_config->adjusted_mode); |
|
8974 | } |
9657 | } |
Line 8975... | Line 9658... | ||
8975 | 9658 | ||
8976 | /* Only after disabling all output pipelines that will be changed can we |
9659 | /* Only after disabling all output pipelines that will be changed can we |
8977 | * update the the output configuration. */ |
9660 | * update the the output configuration. */ |
Line 8992... | Line 9675... | ||
8992 | 9675 | ||
8993 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
9676 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
8994 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9677 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
Line 8995... | Line -... | ||
8995 | dev_priv->display.crtc_enable(&intel_crtc->base); |
- | |
8996 | - | ||
8997 | if (modeset_pipes) { |
- | |
8998 | /* Store real post-adjustment hardware mode. */ |
- | |
8999 | crtc->hwmode = pipe_config->adjusted_mode; |
- | |
9000 | - | ||
9001 | /* Calculate and store various constants which |
- | |
9002 | * are later needed by vblank and swap-completion |
- | |
9003 | * timestamping. They are derived from true hwmode. |
- | |
9004 | */ |
- | |
9005 | drm_calc_timestamping_constants(crtc); |
- | |
9006 | } |
9678 | dev_priv->display.crtc_enable(&intel_crtc->base); |
9007 | 9679 | ||
9008 | /* FIXME: add subpixel order */ |
9680 | /* FIXME: add subpixel order */ |
9009 | done: |
- | |
9010 | if (ret && crtc->enabled) { |
9681 | done: |
9011 | crtc->hwmode = *saved_hwmode; |
- | |
Line 9012... | Line 9682... | ||
9012 | crtc->mode = *saved_mode; |
9682 | if (ret && crtc->enabled) |
9013 | } |
9683 | crtc->mode = *saved_mode; |
9014 | 9684 | ||
9015 | out: |
9685 | out: |
Line 9230... | Line 9900... | ||
9230 | if (set->connectors[ro] == &connector->base) |
9900 | if (set->connectors[ro] == &connector->base) |
9231 | new_crtc = set->crtc; |
9901 | new_crtc = set->crtc; |
9232 | } |
9902 | } |
Line 9233... | Line 9903... | ||
9233 | 9903 | ||
9234 | /* Make sure the new CRTC will work with the encoder */ |
9904 | /* Make sure the new CRTC will work with the encoder */ |
9235 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9905 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9236 | new_crtc)) { |
9906 | new_crtc)) { |
9237 | return -EINVAL; |
9907 | return -EINVAL; |
9238 | } |
9908 | } |
Line 9245... | Line 9915... | ||
9245 | } |
9915 | } |
Line 9246... | Line 9916... | ||
9246 | 9916 | ||
9247 | /* Check for any encoders that needs to be disabled. */ |
9917 | /* Check for any encoders that needs to be disabled. */ |
9248 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9918 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
- | 9919 | base.head) { |
|
9249 | base.head) { |
9920 | int num_connectors = 0; |
9250 | list_for_each_entry(connector, |
9921 | list_for_each_entry(connector, |
9251 | &dev->mode_config.connector_list, |
9922 | &dev->mode_config.connector_list, |
9252 | base.head) { |
9923 | base.head) { |
9253 | if (connector->new_encoder == encoder) { |
9924 | if (connector->new_encoder == encoder) { |
9254 | WARN_ON(!connector->new_encoder->new_crtc); |
- | |
9255 | 9925 | WARN_ON(!connector->new_encoder->new_crtc); |
|
9256 | goto next_encoder; |
9926 | num_connectors++; |
9257 | } |
9927 | } |
- | 9928 | } |
|
- | 9929 | ||
9258 | } |
9930 | if (num_connectors == 0) |
- | 9931 | encoder->new_crtc = NULL; |
|
9259 | encoder->new_crtc = NULL; |
9932 | else if (num_connectors > 1) |
- | 9933 | return -EINVAL; |
|
9260 | next_encoder: |
9934 | |
9261 | /* Only now check for crtc changes so we don't miss encoders |
9935 | /* Only now check for crtc changes so we don't miss encoders |
9262 | * that will be disabled. */ |
9936 | * that will be disabled. */ |
9263 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9937 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9264 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9938 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
Line 9326... | Line 10000... | ||
9326 | } else if (config->fb_changed) { |
10000 | } else if (config->fb_changed) { |
9327 | // intel_crtc_wait_for_pending_flips(set->crtc); |
10001 | // intel_crtc_wait_for_pending_flips(set->crtc); |
Line 9328... | Line 10002... | ||
9328 | 10002 | ||
9329 | ret = intel_pipe_set_base(set->crtc, |
10003 | ret = intel_pipe_set_base(set->crtc, |
- | 10004 | set->x, set->y, set->fb); |
|
- | 10005 | /* |
|
- | 10006 | * In the fastboot case this may be our only check of the |
|
- | 10007 | * state after boot. It would be better to only do it on |
|
- | 10008 | * the first update, but we don't have a nice way of doing that |
|
- | 10009 | * (and really, set_config isn't used much for high freq page |
|
- | 10010 | * flipping, so increasing its cost here shouldn't be a big |
|
- | 10011 | * deal). |
|
- | 10012 | */ |
|
- | 10013 | if (i915_fastboot && ret == 0) |
|
9330 | set->x, set->y, set->fb); |
10014 | intel_modeset_check_state(set->crtc->dev); |
Line 9331... | Line 10015... | ||
9331 | } |
10015 | } |
9332 | 10016 | ||
9333 | if (ret) { |
10017 | if (ret) { |
Line 9386... | Line 10070... | ||
9386 | 10070 | ||
9387 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10071 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9388 | struct intel_shared_dpll *pll) |
10072 | struct intel_shared_dpll *pll) |
9389 | { |
10073 | { |
9390 | /* PCH refclock must be enabled first */ |
10074 | /* PCH refclock must be enabled first */ |
Line 9391... | Line 10075... | ||
9391 | assert_pch_refclk_enabled(dev_priv); |
10075 | ibx_assert_pch_refclk_enabled(dev_priv); |
Line 9392... | Line 10076... | ||
9392 | 10076 | ||
9393 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10077 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
Line 9454... | Line 10138... | ||
9454 | ibx_pch_dpll_init(dev); |
10138 | ibx_pch_dpll_init(dev); |
9455 | else |
10139 | else |
9456 | dev_priv->num_shared_dpll = 0; |
10140 | dev_priv->num_shared_dpll = 0; |
Line 9457... | Line 10141... | ||
9457 | 10141 | ||
9458 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
- | |
9459 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
- | |
9460 | dev_priv->num_shared_dpll); |
10142 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
Line 9461... | Line 10143... | ||
9461 | } |
10143 | } |
9462 | 10144 | ||
9463 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
10145 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9464 | { |
10146 | { |
9465 | drm_i915_private_t *dev_priv = dev->dev_private; |
10147 | drm_i915_private_t *dev_priv = dev->dev_private; |
Line 9466... | Line 10148... | ||
9466 | struct intel_crtc *intel_crtc; |
10148 | struct intel_crtc *intel_crtc; |
9467 | int i; |
10149 | int i; |
9468 | 10150 | ||
Line 9469... | Line 10151... | ||
9469 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
10151 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
Line 9477... | Line 10159... | ||
9477 | intel_crtc->lut_r[i] = i; |
10159 | intel_crtc->lut_r[i] = i; |
9478 | intel_crtc->lut_g[i] = i; |
10160 | intel_crtc->lut_g[i] = i; |
9479 | intel_crtc->lut_b[i] = i; |
10161 | intel_crtc->lut_b[i] = i; |
9480 | } |
10162 | } |
Line -... | Line 10163... | ||
- | 10163 | ||
- | 10164 | /* |
|
9481 | 10165 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
|
- | 10166 | * is hooked to plane B. Hence we want plane A feeding pipe B. |
|
9482 | /* Swap pipes & planes for FBC on pre-965 */ |
10167 | */ |
9483 | intel_crtc->pipe = pipe; |
10168 | intel_crtc->pipe = pipe; |
9484 | intel_crtc->plane = pipe; |
10169 | intel_crtc->plane = pipe; |
9485 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
10170 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
9486 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
10171 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
9487 | intel_crtc->plane = !pipe; |
10172 | intel_crtc->plane = !pipe; |
Line 9488... | Line 10173... | ||
9488 | } |
10173 | } |
Line 9493... | Line 10178... | ||
9493 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
10178 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
Line 9494... | Line 10179... | ||
9494 | 10179 | ||
9495 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
10180 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
Line -... | Line 10181... | ||
- | 10181 | } |
|
- | 10182 | ||
- | 10183 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
|
- | 10184 | { |
|
- | 10185 | struct drm_encoder *encoder = connector->base.encoder; |
|
- | 10186 | ||
- | 10187 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); |
|
- | 10188 | ||
- | 10189 | if (!encoder) |
|
- | 10190 | return INVALID_PIPE; |
|
- | 10191 | ||
- | 10192 | return to_intel_crtc(encoder->crtc)->pipe; |
|
9496 | } |
10193 | } |
9497 | 10194 | ||
9498 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
10195 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9499 | struct drm_file *file) |
10196 | struct drm_file *file) |
9500 | { |
10197 | { |
Line 9508... | Line 10205... | ||
9508 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10205 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9509 | DRM_MODE_OBJECT_CRTC); |
10206 | DRM_MODE_OBJECT_CRTC); |
Line 9510... | Line 10207... | ||
9510 | 10207 | ||
9511 | if (!drmmode_obj) { |
10208 | if (!drmmode_obj) { |
9512 | DRM_ERROR("no such CRTC id\n"); |
10209 | DRM_ERROR("no such CRTC id\n"); |
9513 | return -EINVAL; |
10210 | return -ENOENT; |
Line 9514... | Line 10211... | ||
9514 | } |
10211 | } |
9515 | 10212 | ||
Line 9557... | Line 10254... | ||
9557 | return false; |
10254 | return false; |
Line 9558... | Line 10255... | ||
9558 | 10255 | ||
9559 | return true; |
10256 | return true; |
Line -... | Line 10257... | ||
- | 10257 | } |
|
- | 10258 | ||
- | 10259 | const char *intel_output_name(int output) |
|
- | 10260 | { |
|
- | 10261 | static const char *names[] = { |
|
- | 10262 | [INTEL_OUTPUT_UNUSED] = "Unused", |
|
- | 10263 | [INTEL_OUTPUT_ANALOG] = "Analog", |
|
- | 10264 | [INTEL_OUTPUT_DVO] = "DVO", |
|
- | 10265 | [INTEL_OUTPUT_SDVO] = "SDVO", |
|
- | 10266 | [INTEL_OUTPUT_LVDS] = "LVDS", |
|
- | 10267 | [INTEL_OUTPUT_TVOUT] = "TV", |
|
- | 10268 | [INTEL_OUTPUT_HDMI] = "HDMI", |
|
- | 10269 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
|
- | 10270 | [INTEL_OUTPUT_EDP] = "eDP", |
|
- | 10271 | [INTEL_OUTPUT_DSI] = "DSI", |
|
- | 10272 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", |
|
- | 10273 | }; |
|
- | 10274 | ||
- | 10275 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
|
- | 10276 | return "Invalid"; |
|
- | 10277 | ||
- | 10278 | return names[output]; |
|
9560 | } |
10279 | } |
9561 | 10280 | ||
9562 | static void intel_setup_outputs(struct drm_device *dev) |
10281 | static void intel_setup_outputs(struct drm_device *dev) |
9563 | { |
10282 | { |
9564 | struct drm_i915_private *dev_priv = dev->dev_private; |
10283 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 9589... | Line 10308... | ||
9589 | intel_ddi_init(dev, PORT_C); |
10308 | intel_ddi_init(dev, PORT_C); |
9590 | if (found & SFUSE_STRAP_DDID_DETECTED) |
10309 | if (found & SFUSE_STRAP_DDID_DETECTED) |
9591 | intel_ddi_init(dev, PORT_D); |
10310 | intel_ddi_init(dev, PORT_D); |
9592 | } else if (HAS_PCH_SPLIT(dev)) { |
10311 | } else if (HAS_PCH_SPLIT(dev)) { |
9593 | int found; |
10312 | int found; |
9594 | dpd_is_edp = intel_dpd_is_edp(dev); |
10313 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
Line 9595... | Line 10314... | ||
9595 | 10314 | ||
9596 | if (has_edp_a(dev)) |
10315 | if (has_edp_a(dev)) |
Line 9597... | Line 10316... | ||
9597 | intel_dp_init(dev, DP_A, PORT_A); |
10316 | intel_dp_init(dev, DP_A, PORT_A); |
Line 9615... | Line 10334... | ||
9615 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
10334 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Line 9616... | Line 10335... | ||
9616 | 10335 | ||
9617 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
10336 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
9618 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
10337 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9619 | } else if (IS_VALLEYVIEW(dev)) { |
- | |
9620 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
- | |
9621 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
- | |
9622 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
- | |
9623 | PORT_C); |
- | |
9624 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
- | |
9625 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
- | |
9626 | PORT_C); |
- | |
9627 | } |
- | |
9628 | 10338 | } else if (IS_VALLEYVIEW(dev)) { |
|
9629 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10339 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9630 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
10340 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9631 | PORT_B); |
10341 | PORT_B); |
9632 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
10342 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9633 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
10343 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
- | 10344 | } |
|
- | 10345 | ||
- | 10346 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
|
- | 10347 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
|
- | 10348 | PORT_C); |
|
- | 10349 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
|
- | 10350 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
|
- | 10351 | } |
|
- | 10352 | ||
9634 | } |
10353 | intel_dsi_init(dev); |
9635 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
10354 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Line 9636... | Line 10355... | ||
9636 | bool found = false; |
10355 | bool found = false; |
9637 | 10356 | ||
Line 9694... | Line 10413... | ||
9694 | int intel_framebuffer_init(struct drm_device *dev, |
10413 | int intel_framebuffer_init(struct drm_device *dev, |
9695 | struct intel_framebuffer *intel_fb, |
10414 | struct intel_framebuffer *intel_fb, |
9696 | struct drm_mode_fb_cmd2 *mode_cmd, |
10415 | struct drm_mode_fb_cmd2 *mode_cmd, |
9697 | struct drm_i915_gem_object *obj) |
10416 | struct drm_i915_gem_object *obj) |
9698 | { |
10417 | { |
- | 10418 | int aligned_height, tile_height; |
|
9699 | int pitch_limit; |
10419 | int pitch_limit; |
9700 | int ret; |
10420 | int ret; |
Line -... | Line 10421... | ||
- | 10421 | ||
- | 10422 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
9701 | 10423 | ||
9702 | if (obj->tiling_mode == I915_TILING_Y) { |
10424 | if (obj->tiling_mode == I915_TILING_Y) { |
9703 | DRM_DEBUG("hardware does not support tiling Y\n"); |
10425 | DRM_DEBUG("hardware does not support tiling Y\n"); |
9704 | return -EINVAL; |
10426 | return -EINVAL; |
Line 9785... | Line 10507... | ||
9785 | 10507 | ||
9786 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10508 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9787 | if (mode_cmd->offsets[0] != 0) |
10509 | if (mode_cmd->offsets[0] != 0) |
Line -... | Line 10510... | ||
- | 10510 | return -EINVAL; |
|
- | 10511 | ||
- | 10512 | tile_height = IS_GEN2(dev) ? 16 : 8; |
|
- | 10513 | aligned_height = ALIGN(mode_cmd->height, |
|
- | 10514 | obj->tiling_mode ? tile_height : 1); |
|
- | 10515 | /* FIXME drm helper for size checks (especially planar formats)? */ |
|
- | 10516 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
|
9788 | return -EINVAL; |
10517 | return -EINVAL; |
9789 | 10518 | ||
- | 10519 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
|
Line 9790... | Line 10520... | ||
9790 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10520 | intel_fb->obj = obj; |
9791 | intel_fb->obj = obj; |
10521 | intel_fb->obj->framebuffer_references++; |
9792 | 10522 | ||
9793 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10523 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9794 | if (ret) { |
10524 | if (ret) { |
Line 9795... | Line 10525... | ||
9795 | DRM_ERROR("framebuffer init failed %d\n", ret); |
10525 | DRM_ERROR("framebuffer init failed %d\n", ret); |
9796 | return ret; |
10526 | return ret; |
Line -... | Line 10527... | ||
- | 10527 | } |
|
- | 10528 | ||
- | 10529 | return 0; |
|
- | 10530 | } |
|
- | 10531 | ||
Line 9797... | Line 10532... | ||
9797 | } |
10532 | #ifndef CONFIG_DRM_I915_FBDEV |
9798 | 10533 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
|
9799 | return 0; |
10534 | { |
9800 | } |
10535 | } |
Line 9801... | Line 10536... | ||
9801 | 10536 | #endif |
|
9802 | 10537 | ||
9803 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
10538 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Line 9826... | Line 10561... | ||
9826 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
10561 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
9827 | dev_priv->display.off = haswell_crtc_off; |
10562 | dev_priv->display.off = haswell_crtc_off; |
9828 | dev_priv->display.update_plane = ironlake_update_plane; |
10563 | dev_priv->display.update_plane = ironlake_update_plane; |
9829 | } else if (HAS_PCH_SPLIT(dev)) { |
10564 | } else if (HAS_PCH_SPLIT(dev)) { |
9830 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
10565 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
9831 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
- | |
9832 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
10566 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9833 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10567 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9834 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
10568 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9835 | dev_priv->display.off = ironlake_crtc_off; |
10569 | dev_priv->display.off = ironlake_crtc_off; |
9836 | dev_priv->display.update_plane = ironlake_update_plane; |
10570 | dev_priv->display.update_plane = ironlake_update_plane; |
9837 | } else if (IS_VALLEYVIEW(dev)) { |
10571 | } else if (IS_VALLEYVIEW(dev)) { |
9838 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
10572 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9839 | dev_priv->display.get_clock = vlv_crtc_clock_get; |
- | |
9840 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10573 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9841 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
10574 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9842 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10575 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9843 | dev_priv->display.off = i9xx_crtc_off; |
10576 | dev_priv->display.off = i9xx_crtc_off; |
9844 | dev_priv->display.update_plane = i9xx_update_plane; |
10577 | dev_priv->display.update_plane = i9xx_update_plane; |
9845 | } else { |
10578 | } else { |
9846 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
10579 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9847 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
- | |
9848 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10580 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9849 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10581 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9850 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10582 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9851 | dev_priv->display.off = i9xx_crtc_off; |
10583 | dev_priv->display.off = i9xx_crtc_off; |
9852 | dev_priv->display.update_plane = i9xx_update_plane; |
10584 | dev_priv->display.update_plane = i9xx_update_plane; |
Line 9892... | Line 10624... | ||
9892 | /* FIXME: detect B0+ stepping and use auto training */ |
10624 | /* FIXME: detect B0+ stepping and use auto training */ |
9893 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
10625 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
9894 | dev_priv->display.write_eld = ironlake_write_eld; |
10626 | dev_priv->display.write_eld = ironlake_write_eld; |
9895 | dev_priv->display.modeset_global_resources = |
10627 | dev_priv->display.modeset_global_resources = |
9896 | ivb_modeset_global_resources; |
10628 | ivb_modeset_global_resources; |
9897 | } else if (IS_HASWELL(dev)) { |
10629 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
9898 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
10630 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
9899 | dev_priv->display.write_eld = haswell_write_eld; |
10631 | dev_priv->display.write_eld = haswell_write_eld; |
9900 | dev_priv->display.modeset_global_resources = |
10632 | dev_priv->display.modeset_global_resources = |
9901 | haswell_modeset_global_resources; |
10633 | haswell_modeset_global_resources; |
9902 | } |
10634 | } |
9903 | } else if (IS_G4X(dev)) { |
10635 | } else if (IS_G4X(dev)) { |
9904 | dev_priv->display.write_eld = g4x_write_eld; |
10636 | dev_priv->display.write_eld = g4x_write_eld; |
- | 10637 | } else if (IS_VALLEYVIEW(dev)) { |
|
- | 10638 | dev_priv->display.modeset_global_resources = |
|
- | 10639 | valleyview_modeset_global_resources; |
|
- | 10640 | dev_priv->display.write_eld = ironlake_write_eld; |
|
9905 | } |
10641 | } |
Line 9906... | Line 10642... | ||
9906 | 10642 | ||
9907 | /* Default just returns -ENODEV to indicate unsupported */ |
10643 | /* Default just returns -ENODEV to indicate unsupported */ |
Line -... | Line 10644... | ||
- | 10644 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
|
9908 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
10645 | |
Line 9909... | Line 10646... | ||
9909 | 10646 | ||
9910 | 10647 | ||
9911 | 10648 | ||
Line 9944... | Line 10681... | ||
9944 | struct drm_i915_private *dev_priv = dev->dev_private; |
10681 | struct drm_i915_private *dev_priv = dev->dev_private; |
9945 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
10682 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9946 | DRM_INFO("applying inverted panel brightness quirk\n"); |
10683 | DRM_INFO("applying inverted panel brightness quirk\n"); |
9947 | } |
10684 | } |
Line 9948... | Line -... | ||
9948 | - | ||
9949 | /* |
- | |
9950 | * Some machines (Dell XPS13) suffer broken backlight controls if |
- | |
9951 | * BLM_PCH_PWM_ENABLE is set. |
- | |
9952 | */ |
- | |
9953 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
- | |
9954 | { |
- | |
9955 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
9956 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
- | |
9957 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
- | |
9958 | } |
- | |
9959 | 10685 | ||
9960 | struct intel_quirk { |
10686 | struct intel_quirk { |
9961 | int device; |
10687 | int device; |
9962 | int subsystem_vendor; |
10688 | int subsystem_vendor; |
9963 | int subsystem_device; |
10689 | int subsystem_device; |
Line 10000... | Line 10726... | ||
10000 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
10726 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
Line 10001... | Line 10727... | ||
10001 | 10727 | ||
10002 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10728 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
Line 10003... | Line 10729... | ||
10003 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
10729 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
10004 | - | ||
10005 | /* 830/845 need to leave pipe A & dpll A up */ |
10730 | |
Line 10006... | Line 10731... | ||
10006 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
10731 | /* 830 needs to leave pipe A & dpll A up */ |
10007 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
10732 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
Line 10024... | Line 10749... | ||
10024 | /* Acer/Packard Bell NCL20 */ |
10749 | /* Acer/Packard Bell NCL20 */ |
10025 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
10750 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
Line 10026... | Line 10751... | ||
10026 | 10751 | ||
10027 | /* Acer Aspire 4736Z */ |
10752 | /* Acer Aspire 4736Z */ |
10028 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
- | |
10029 | - | ||
10030 | /* Dell XPS13 HD Sandy Bridge */ |
- | |
10031 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
- | |
10032 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
- | |
10033 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
10753 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
Line 10034... | Line 10754... | ||
10034 | }; |
10754 | }; |
10035 | 10755 | ||
10036 | static void intel_init_quirks(struct drm_device *dev) |
10756 | static void intel_init_quirks(struct drm_device *dev) |
Line 10056... | Line 10776... | ||
10056 | struct drm_i915_private *dev_priv = dev->dev_private; |
10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
10057 | u8 sr1; |
10777 | u8 sr1; |
10058 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10778 | u32 vga_reg = i915_vgacntrl_reg(dev); |
Line 10059... | Line 10779... | ||
10059 | 10779 | ||
10060 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10780 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10061 | out8(SR01, VGA_SR_INDEX); |
10781 | outb(SR01, VGA_SR_INDEX); |
10062 | sr1 = in8(VGA_SR_DATA); |
10782 | sr1 = inb(VGA_SR_DATA); |
10063 | out8(sr1 | 1<<5, VGA_SR_DATA); |
10783 | outb(sr1 | 1<<5, VGA_SR_DATA); |
10064 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
10784 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
Line 10065... | Line 10785... | ||
10065 | udelay(300); |
10785 | udelay(300); |
10066 | 10786 | ||
10067 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10787 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
Line 10068... | Line 10788... | ||
10068 | POSTING_READ(vga_reg); |
10788 | POSTING_READ(vga_reg); |
10069 | } |
10789 | } |
10070 | - | ||
10071 | void intel_modeset_init_hw(struct drm_device *dev) |
- | |
10072 | { |
- | |
10073 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
10074 | 10790 | ||
Line 10075... | Line 10791... | ||
10075 | intel_init_power_well(dev); |
10791 | void intel_modeset_init_hw(struct drm_device *dev) |
Line 10076... | Line -... | ||
10076 | - | ||
10077 | intel_prepare_ddi(dev); |
10792 | { |
10078 | - | ||
10079 | intel_init_clock_gating(dev); |
- | |
Line 10080... | Line 10793... | ||
10080 | 10793 | intel_prepare_ddi(dev); |
|
10081 | /* Enable the CRI clock source so we can get at the display */ |
10794 | |
10082 | if (IS_VALLEYVIEW(dev)) |
10795 | intel_init_clock_gating(dev); |
10083 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
10796 | |
Line 10141... | Line 10854... | ||
10141 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10854 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10142 | pipe_name(i), sprite_name(i, j), ret); |
10855 | pipe_name(i), sprite_name(i, j), ret); |
10143 | } |
10856 | } |
10144 | } |
10857 | } |
Line -... | Line 10858... | ||
- | 10858 | ||
- | 10859 | intel_init_dpio(dev); |
|
- | 10860 | intel_reset_dpio(dev); |
|
10145 | 10861 | ||
10146 | intel_cpu_pll_init(dev); |
10862 | intel_cpu_pll_init(dev); |
Line 10147... | Line 10863... | ||
10147 | intel_shared_dpll_init(dev); |
10863 | intel_shared_dpll_init(dev); |
10148 | 10864 | ||
Line 10344... | Line 11060... | ||
10344 | * structures are not yet restored. Since this function is at a very |
11060 | * structures are not yet restored. Since this function is at a very |
10345 | * paranoid "someone might have enabled VGA while we were not looking" |
11061 | * paranoid "someone might have enabled VGA while we were not looking" |
10346 | * level, just check if the power well is enabled instead of trying to |
11062 | * level, just check if the power well is enabled instead of trying to |
10347 | * follow the "don't touch the power well if we don't need it" policy |
11063 | * follow the "don't touch the power well if we don't need it" policy |
10348 | * the rest of the driver uses. */ |
11064 | * the rest of the driver uses. */ |
10349 | if (HAS_POWER_WELL(dev) && |
11065 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
10350 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
11066 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
10351 | return; |
11067 | return; |
Line 10352... | Line 11068... | ||
10352 | 11068 | ||
10353 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
11069 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
10354 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
11070 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
10355 | i915_disable_vga(dev); |
11071 | i915_disable_vga(dev); |
10356 | } |
11072 | } |
Line 10371... | Line 11087... | ||
10371 | 11087 | ||
10372 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11088 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
Line 10373... | Line 11089... | ||
10373 | &crtc->config); |
11089 | &crtc->config); |
- | 11090 | ||
Line 10374... | Line 11091... | ||
10374 | 11091 | crtc->base.enabled = crtc->active; |
|
10375 | crtc->base.enabled = crtc->active; |
11092 | crtc->primary_enabled = crtc->active; |
10376 | 11093 | ||
10377 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
11094 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
Line 10404... | Line 11121... | ||
10404 | pipe = 0; |
11121 | pipe = 0; |
Line 10405... | Line 11122... | ||
10405 | 11122 | ||
10406 | if (encoder->get_hw_state(encoder, &pipe)) { |
11123 | if (encoder->get_hw_state(encoder, &pipe)) { |
10407 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11124 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10408 | encoder->base.crtc = &crtc->base; |
- | |
10409 | if (encoder->get_config) |
11125 | encoder->base.crtc = &crtc->base; |
10410 | encoder->get_config(encoder, &crtc->config); |
11126 | encoder->get_config(encoder, &crtc->config); |
10411 | } else { |
11127 | } else { |
10412 | encoder->base.crtc = NULL; |
11128 | encoder->base.crtc = NULL; |
Line 10413... | Line 11129... | ||
10413 | } |
11129 | } |
10414 | 11130 | ||
10415 | encoder->connectors_active = false; |
11131 | encoder->connectors_active = false; |
10416 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
11132 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
10417 | encoder->base.base.id, |
11133 | encoder->base.base.id, |
10418 | drm_get_encoder_name(&encoder->base), |
11134 | drm_get_encoder_name(&encoder->base), |
10419 | encoder->base.crtc ? "enabled" : "disabled", |
- | |
10420 | pipe); |
- | |
10421 | } |
- | |
10422 | - | ||
10423 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
- | |
10424 | base.head) { |
- | |
10425 | if (!crtc->active) |
- | |
10426 | continue; |
- | |
10427 | if (dev_priv->display.get_clock) |
- | |
10428 | dev_priv->display.get_clock(crtc, |
11135 | encoder->base.crtc ? "enabled" : "disabled", |
Line 10429... | Line 11136... | ||
10429 | &crtc->config); |
11136 | pipe_name(pipe)); |
10430 | } |
11137 | } |
10431 | 11138 | ||
Line 10451... | Line 11158... | ||
10451 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
11158 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
10452 | bool force_restore) |
11159 | bool force_restore) |
10453 | { |
11160 | { |
10454 | struct drm_i915_private *dev_priv = dev->dev_private; |
11161 | struct drm_i915_private *dev_priv = dev->dev_private; |
10455 | enum pipe pipe; |
11162 | enum pipe pipe; |
10456 | struct drm_plane *plane; |
- | |
10457 | struct intel_crtc *crtc; |
11163 | struct intel_crtc *crtc; |
10458 | struct intel_encoder *encoder; |
11164 | struct intel_encoder *encoder; |
10459 | int i; |
11165 | int i; |
Line 10460... | Line 11166... | ||
10460 | 11166 | ||
Line 10498... | Line 11204... | ||
10498 | 11204 | ||
10499 | pll->disable(dev_priv, pll); |
11205 | pll->disable(dev_priv, pll); |
10500 | pll->on = false; |
11206 | pll->on = false; |
Line -... | Line 11207... | ||
- | 11207 | } |
|
- | 11208 | ||
- | 11209 | if (HAS_PCH_SPLIT(dev)) |
|
10501 | } |
11210 | ilk_wm_get_hw_state(dev); |
- | 11211 | ||
- | 11212 | if (force_restore) { |
|
10502 | 11213 | i915_redisable_vga(dev); |
|
10503 | if (force_restore) { |
11214 | |
10504 | /* |
11215 | /* |
10505 | * We need to use raw interfaces for restoring state to avoid |
11216 | * We need to use raw interfaces for restoring state to avoid |
10506 | * checking (bogus) intermediate states. |
11217 | * checking (bogus) intermediate states. |
Line 10510... | Line 11221... | ||
10510 | dev_priv->pipe_to_crtc_mapping[pipe]; |
11221 | dev_priv->pipe_to_crtc_mapping[pipe]; |
Line 10511... | Line 11222... | ||
10511 | 11222 | ||
10512 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
11223 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
10513 | crtc->fb); |
11224 | crtc->fb); |
10514 | } |
- | |
10515 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
- | |
10516 | intel_plane_restore(plane); |
- | |
10517 | - | ||
10518 | i915_redisable_vga(dev); |
11225 | } |
10519 | } else { |
11226 | } else { |
10520 | intel_modeset_update_staged_output_state(dev); |
11227 | intel_modeset_update_staged_output_state(dev); |
Line 10521... | Line 11228... | ||
10521 | } |
11228 | } |
10522 | - | ||
10523 | intel_modeset_check_state(dev); |
- | |
10524 | 11229 | ||
Line 10525... | Line 11230... | ||
10525 | drm_mode_config_reset(dev); |
11230 | intel_modeset_check_state(dev); |
10526 | } |
11231 | } |
10527 | 11232 | ||
Line 10528... | Line 11233... | ||
10528 | void intel_modeset_gem_init(struct drm_device *dev) |
11233 | void intel_modeset_gem_init(struct drm_device *dev) |
Line 10529... | Line 11234... | ||
10529 | { |
11234 | { |
- | 11235 | intel_modeset_init_hw(dev); |
|
10530 | intel_modeset_init_hw(dev); |
11236 | |
10531 | 11237 | // intel_setup_overlay(dev); |
|
10532 | // intel_setup_overlay(dev); |
11238 | |
Line 10533... | Line 11239... | ||
10533 | 11239 | mutex_lock(&dev->mode_config.mutex); |
|
10534 | mutex_lock(&dev->mode_config.mutex); |
11240 | drm_mode_config_reset(dev); |
10535 | intel_modeset_setup_hw_state(dev, false); |
11241 | intel_modeset_setup_hw_state(dev, false); |
10536 | mutex_unlock(&dev->mode_config.mutex); |
11242 | mutex_unlock(&dev->mode_config.mutex); |
10537 | } |
11243 | } |
- | 11244 | ||
Line 10538... | Line 11245... | ||
10538 | 11245 | void intel_modeset_cleanup(struct drm_device *dev) |
|
10539 | void intel_modeset_cleanup(struct drm_device *dev) |
11246 | { |
10540 | { |
11247 | #if 0 |
10541 | #if 0 |
11248 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10551... | Line 11258... | ||
10551 | cancel_work_sync(&dev_priv->hotplug_work); |
11258 | cancel_work_sync(&dev_priv->hotplug_work); |
10552 | /* |
11259 | /* |
10553 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
11260 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
10554 | * poll handlers. Hence disable polling after hpd handling is shut down. |
11261 | * poll handlers. Hence disable polling after hpd handling is shut down. |
10555 | */ |
11262 | */ |
10556 | // drm_kms_helper_poll_fini(dev); |
11263 | drm_kms_helper_poll_fini(dev); |
Line 10557... | Line 11264... | ||
10557 | 11264 | ||
Line 10558... | Line 11265... | ||
10558 | mutex_lock(&dev->struct_mutex); |
11265 | mutex_lock(&dev->struct_mutex); |
Line 10559... | Line 11266... | ||
10559 | 11266 | ||
10560 | // intel_unregister_dsm_handler(); |
11267 | intel_unregister_dsm_handler(); |
10561 | 11268 | ||
10562 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11269 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Line 10576... | Line 11283... | ||
10576 | mutex_unlock(&dev->struct_mutex); |
11283 | mutex_unlock(&dev->struct_mutex); |
Line 10577... | Line 11284... | ||
10577 | 11284 | ||
10578 | /* flush any delayed tasks or pending work */ |
11285 | /* flush any delayed tasks or pending work */ |
Line 10579... | Line 11286... | ||
10579 | flush_scheduled_work(); |
11286 | flush_scheduled_work(); |
- | 11287 | ||
10580 | 11288 | /* destroy the backlight and sysfs files before encoders/connectors */ |
|
- | 11289 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
- | 11290 | intel_panel_destroy_backlight(connector); |
|
Line 10581... | Line 11291... | ||
10581 | /* destroy backlight, if any, before the connectors */ |
11291 | drm_sysfs_connector_remove(connector); |
10582 | intel_panel_destroy_backlight(dev); |
11292 | } |
10583 | 11293 | ||
Line 10618... | Line 11328... | ||
10618 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
11328 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
10619 | return 0; |
11329 | return 0; |
10620 | } |
11330 | } |
Line 10621... | Line 11331... | ||
10621 | 11331 | ||
10622 | #ifdef CONFIG_DEBUG_FS |
- | |
Line 10623... | Line 11332... | ||
10623 | #include |
11332 | #ifdef CONFIG_DEBUG_FS |
Line 10624... | Line 11333... | ||
10624 | 11333 | ||
Line 10634... | Line 11343... | ||
10634 | u32 base; |
11343 | u32 base; |
10635 | u32 size; |
11344 | u32 size; |
10636 | } cursor[I915_MAX_PIPES]; |
11345 | } cursor[I915_MAX_PIPES]; |
Line 10637... | Line 11346... | ||
10637 | 11346 | ||
- | 11347 | struct intel_pipe_error_state { |
|
10638 | struct intel_pipe_error_state { |
11348 | bool power_domain_on; |
10639 | u32 source; |
11349 | u32 source; |
Line 10640... | Line 11350... | ||
10640 | } pipe[I915_MAX_PIPES]; |
11350 | } pipe[I915_MAX_PIPES]; |
10641 | 11351 | ||
Line 10648... | Line 11358... | ||
10648 | u32 surface; |
11358 | u32 surface; |
10649 | u32 tile_offset; |
11359 | u32 tile_offset; |
10650 | } plane[I915_MAX_PIPES]; |
11360 | } plane[I915_MAX_PIPES]; |
Line 10651... | Line 11361... | ||
10651 | 11361 | ||
- | 11362 | struct intel_transcoder_error_state { |
|
10652 | struct intel_transcoder_error_state { |
11363 | bool power_domain_on; |
Line 10653... | Line 11364... | ||
10653 | enum transcoder cpu_transcoder; |
11364 | enum transcoder cpu_transcoder; |
Line 10654... | Line 11365... | ||
10654 | 11365 | ||
Line 10677... | Line 11388... | ||
10677 | int i; |
11388 | int i; |
Line 10678... | Line 11389... | ||
10678 | 11389 | ||
10679 | if (INTEL_INFO(dev)->num_pipes == 0) |
11390 | if (INTEL_INFO(dev)->num_pipes == 0) |
Line 10680... | Line 11391... | ||
10680 | return NULL; |
11391 | return NULL; |
10681 | 11392 | ||
10682 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
11393 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Line 10683... | Line 11394... | ||
10683 | if (error == NULL) |
11394 | if (error == NULL) |
10684 | return NULL; |
11395 | return NULL; |
Line 10685... | Line 11396... | ||
10685 | 11396 | ||
- | 11397 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
- | 11398 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
|
- | 11399 | ||
- | 11400 | for_each_pipe(i) { |
|
- | 11401 | error->pipe[i].power_domain_on = |
|
10686 | if (HAS_POWER_WELL(dev)) |
11402 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); |
10687 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11403 | if (!error->pipe[i].power_domain_on) |
10688 | 11404 | continue; |
|
10689 | for_each_pipe(i) { |
11405 | |
10690 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11406 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
Line 10718... | Line 11434... | ||
10718 | error->num_transcoders++; /* Account for eDP. */ |
11434 | error->num_transcoders++; /* Account for eDP. */ |
Line 10719... | Line 11435... | ||
10719 | 11435 | ||
10720 | for (i = 0; i < error->num_transcoders; i++) { |
11436 | for (i = 0; i < error->num_transcoders; i++) { |
Line -... | Line 11437... | ||
- | 11437 | enum transcoder cpu_transcoder = transcoders[i]; |
|
- | 11438 | ||
- | 11439 | error->transcoder[i].power_domain_on = |
|
- | 11440 | intel_display_power_enabled_sw(dev, |
|
- | 11441 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
|
- | 11442 | if (!error->transcoder[i].power_domain_on) |
|
10721 | enum transcoder cpu_transcoder = transcoders[i]; |
11443 | continue; |
Line 10722... | Line 11444... | ||
10722 | 11444 | ||
10723 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11445 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
10724 | 11446 | ||
Line 10729... | Line 11451... | ||
10729 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
11451 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
10730 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
11452 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
10731 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
11453 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
10732 | } |
11454 | } |
Line 10733... | Line -... | ||
10733 | - | ||
10734 | /* In the code above we read the registers without checking if the power |
- | |
10735 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
- | |
10736 | * prevent the next I915_WRITE from detecting it and printing an error |
- | |
10737 | * message. */ |
- | |
10738 | intel_uncore_clear_errors(dev); |
- | |
10739 | 11455 | ||
10740 | return error; |
11456 | return error; |
Line 10741... | Line 11457... | ||
10741 | } |
11457 | } |
Line 10751... | Line 11467... | ||
10751 | 11467 | ||
10752 | if (!error) |
11468 | if (!error) |
Line 10753... | Line 11469... | ||
10753 | return; |
11469 | return; |
10754 | 11470 | ||
10755 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
11471 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
10756 | if (HAS_POWER_WELL(dev)) |
11472 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
10757 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
11473 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
10758 | error->power_well_driver); |
11474 | error->power_well_driver); |
- | 11475 | for_each_pipe(i) { |
|
- | 11476 | err_printf(m, "Pipe [%d]:\n", i); |
|
10759 | for_each_pipe(i) { |
11477 | err_printf(m, " Power: %s\n", |
Line 10760... | Line 11478... | ||
10760 | err_printf(m, "Pipe [%d]:\n", i); |
11478 | error->pipe[i].power_domain_on ? "on" : "off"); |
10761 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
11479 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
10762 | 11480 | ||
Line 10781... | Line 11499... | ||
10781 | } |
11499 | } |
Line 10782... | Line 11500... | ||
10782 | 11500 | ||
10783 | for (i = 0; i < error->num_transcoders; i++) { |
11501 | for (i = 0; i < error->num_transcoders; i++) { |
10784 | err_printf(m, " CPU transcoder: %c\n", |
11502 | err_printf(m, "CPU transcoder: %c\n", |
- | 11503 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
|
- | 11504 | err_printf(m, " Power: %s\n", |
|
10785 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
11505 | error->transcoder[i].power_domain_on ? "on" : "off"); |
10786 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11506 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
10787 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
11507 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
10788 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
11508 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
10789 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
11509 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |