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1 | /* |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | */ |
25 | */ |
26 | 26 | ||
27 | //#include |
27 | //#include |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
42 | //#include |
42 | //#include |
43 | 43 | ||
44 | #define MAX_ERRNO 4095 |
44 | #define MAX_ERRNO 4095 |
45 | phys_addr_t get_bus_addr(void); |
45 | phys_addr_t get_bus_addr(void); |
46 | 46 | ||
47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
50 | 50 | ||
51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
52 | struct intel_crtc_config *pipe_config); |
52 | struct intel_crtc_config *pipe_config); |
53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
54 | struct intel_crtc_config *pipe_config); |
54 | struct intel_crtc_config *pipe_config); |
55 | 55 | ||
56 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
56 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
57 | int x, int y, struct drm_framebuffer *old_fb); |
57 | int x, int y, struct drm_framebuffer *old_fb); |
58 | 58 | ||
59 | 59 | ||
60 | typedef struct { |
60 | typedef struct { |
61 | int min, max; |
61 | int min, max; |
62 | } intel_range_t; |
62 | } intel_range_t; |
63 | 63 | ||
64 | typedef struct { |
64 | typedef struct { |
65 | int dot_limit; |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; |
66 | int p2_slow, p2_fast; |
67 | } intel_p2_t; |
67 | } intel_p2_t; |
68 | 68 | ||
69 | typedef struct intel_limit intel_limit_t; |
69 | typedef struct intel_limit intel_limit_t; |
70 | struct intel_limit { |
70 | struct intel_limit { |
71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
72 | intel_p2_t p2; |
72 | intel_p2_t p2; |
73 | }; |
73 | }; |
74 | 74 | ||
75 | /* FDI */ |
75 | /* FDI */ |
76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
77 | 77 | ||
78 | int |
78 | int |
79 | intel_pch_rawclk(struct drm_device *dev) |
79 | intel_pch_rawclk(struct drm_device *dev) |
80 | { |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; |
81 | struct drm_i915_private *dev_priv = dev->dev_private; |
82 | 82 | ||
83 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
83 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
84 | 84 | ||
85 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
85 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
86 | } |
86 | } |
87 | 87 | ||
88 | static inline u32 /* units of 100MHz */ |
88 | static inline u32 /* units of 100MHz */ |
89 | intel_fdi_link_freq(struct drm_device *dev) |
89 | intel_fdi_link_freq(struct drm_device *dev) |
90 | { |
90 | { |
91 | if (IS_GEN5(dev)) { |
91 | if (IS_GEN5(dev)) { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; |
92 | struct drm_i915_private *dev_priv = dev->dev_private; |
93 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
93 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
94 | } else |
94 | } else |
95 | return 27; |
95 | return 27; |
96 | } |
96 | } |
97 | 97 | ||
98 | static const intel_limit_t intel_limits_i8xx_dac = { |
98 | static const intel_limit_t intel_limits_i8xx_dac = { |
99 | .dot = { .min = 25000, .max = 350000 }, |
99 | .dot = { .min = 25000, .max = 350000 }, |
100 | .vco = { .min = 930000, .max = 1400000 }, |
100 | .vco = { .min = 930000, .max = 1400000 }, |
101 | .n = { .min = 3, .max = 16 }, |
101 | .n = { .min = 3, .max = 16 }, |
102 | .m = { .min = 96, .max = 140 }, |
102 | .m = { .min = 96, .max = 140 }, |
103 | .m1 = { .min = 18, .max = 26 }, |
103 | .m1 = { .min = 18, .max = 26 }, |
104 | .m2 = { .min = 6, .max = 16 }, |
104 | .m2 = { .min = 6, .max = 16 }, |
105 | .p = { .min = 4, .max = 128 }, |
105 | .p = { .min = 4, .max = 128 }, |
106 | .p1 = { .min = 2, .max = 33 }, |
106 | .p1 = { .min = 2, .max = 33 }, |
107 | .p2 = { .dot_limit = 165000, |
107 | .p2 = { .dot_limit = 165000, |
108 | .p2_slow = 4, .p2_fast = 2 }, |
108 | .p2_slow = 4, .p2_fast = 2 }, |
109 | }; |
109 | }; |
110 | 110 | ||
111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
112 | .dot = { .min = 25000, .max = 350000 }, |
112 | .dot = { .min = 25000, .max = 350000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, |
114 | .n = { .min = 3, .max = 16 }, |
114 | .n = { .min = 3, .max = 16 }, |
115 | .m = { .min = 96, .max = 140 }, |
115 | .m = { .min = 96, .max = 140 }, |
116 | .m1 = { .min = 18, .max = 26 }, |
116 | .m1 = { .min = 18, .max = 26 }, |
117 | .m2 = { .min = 6, .max = 16 }, |
117 | .m2 = { .min = 6, .max = 16 }, |
118 | .p = { .min = 4, .max = 128 }, |
118 | .p = { .min = 4, .max = 128 }, |
119 | .p1 = { .min = 2, .max = 33 }, |
119 | .p1 = { .min = 2, .max = 33 }, |
120 | .p2 = { .dot_limit = 165000, |
120 | .p2 = { .dot_limit = 165000, |
121 | .p2_slow = 4, .p2_fast = 4 }, |
121 | .p2_slow = 4, .p2_fast = 4 }, |
122 | }; |
122 | }; |
123 | 123 | ||
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
125 | .dot = { .min = 25000, .max = 350000 }, |
125 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, |
127 | .n = { .min = 3, .max = 16 }, |
127 | .n = { .min = 3, .max = 16 }, |
128 | .m = { .min = 96, .max = 140 }, |
128 | .m = { .min = 96, .max = 140 }, |
129 | .m1 = { .min = 18, .max = 26 }, |
129 | .m1 = { .min = 18, .max = 26 }, |
130 | .m2 = { .min = 6, .max = 16 }, |
130 | .m2 = { .min = 6, .max = 16 }, |
131 | .p = { .min = 4, .max = 128 }, |
131 | .p = { .min = 4, .max = 128 }, |
132 | .p1 = { .min = 1, .max = 6 }, |
132 | .p1 = { .min = 1, .max = 6 }, |
133 | .p2 = { .dot_limit = 165000, |
133 | .p2 = { .dot_limit = 165000, |
134 | .p2_slow = 14, .p2_fast = 7 }, |
134 | .p2_slow = 14, .p2_fast = 7 }, |
135 | }; |
135 | }; |
136 | 136 | ||
137 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
137 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
138 | .dot = { .min = 20000, .max = 400000 }, |
138 | .dot = { .min = 20000, .max = 400000 }, |
139 | .vco = { .min = 1400000, .max = 2800000 }, |
139 | .vco = { .min = 1400000, .max = 2800000 }, |
140 | .n = { .min = 1, .max = 6 }, |
140 | .n = { .min = 1, .max = 6 }, |
141 | .m = { .min = 70, .max = 120 }, |
141 | .m = { .min = 70, .max = 120 }, |
142 | .m1 = { .min = 8, .max = 18 }, |
142 | .m1 = { .min = 8, .max = 18 }, |
143 | .m2 = { .min = 3, .max = 7 }, |
143 | .m2 = { .min = 3, .max = 7 }, |
144 | .p = { .min = 5, .max = 80 }, |
144 | .p = { .min = 5, .max = 80 }, |
145 | .p1 = { .min = 1, .max = 8 }, |
145 | .p1 = { .min = 1, .max = 8 }, |
146 | .p2 = { .dot_limit = 200000, |
146 | .p2 = { .dot_limit = 200000, |
147 | .p2_slow = 10, .p2_fast = 5 }, |
147 | .p2_slow = 10, .p2_fast = 5 }, |
148 | }; |
148 | }; |
149 | 149 | ||
150 | static const intel_limit_t intel_limits_i9xx_lvds = { |
150 | static const intel_limit_t intel_limits_i9xx_lvds = { |
151 | .dot = { .min = 20000, .max = 400000 }, |
151 | .dot = { .min = 20000, .max = 400000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, |
153 | .n = { .min = 1, .max = 6 }, |
153 | .n = { .min = 1, .max = 6 }, |
154 | .m = { .min = 70, .max = 120 }, |
154 | .m = { .min = 70, .max = 120 }, |
155 | .m1 = { .min = 8, .max = 18 }, |
155 | .m1 = { .min = 8, .max = 18 }, |
156 | .m2 = { .min = 3, .max = 7 }, |
156 | .m2 = { .min = 3, .max = 7 }, |
157 | .p = { .min = 7, .max = 98 }, |
157 | .p = { .min = 7, .max = 98 }, |
158 | .p1 = { .min = 1, .max = 8 }, |
158 | .p1 = { .min = 1, .max = 8 }, |
159 | .p2 = { .dot_limit = 112000, |
159 | .p2 = { .dot_limit = 112000, |
160 | .p2_slow = 14, .p2_fast = 7 }, |
160 | .p2_slow = 14, .p2_fast = 7 }, |
161 | }; |
161 | }; |
162 | 162 | ||
163 | 163 | ||
164 | static const intel_limit_t intel_limits_g4x_sdvo = { |
164 | static const intel_limit_t intel_limits_g4x_sdvo = { |
165 | .dot = { .min = 25000, .max = 270000 }, |
165 | .dot = { .min = 25000, .max = 270000 }, |
166 | .vco = { .min = 1750000, .max = 3500000}, |
166 | .vco = { .min = 1750000, .max = 3500000}, |
167 | .n = { .min = 1, .max = 4 }, |
167 | .n = { .min = 1, .max = 4 }, |
168 | .m = { .min = 104, .max = 138 }, |
168 | .m = { .min = 104, .max = 138 }, |
169 | .m1 = { .min = 17, .max = 23 }, |
169 | .m1 = { .min = 17, .max = 23 }, |
170 | .m2 = { .min = 5, .max = 11 }, |
170 | .m2 = { .min = 5, .max = 11 }, |
171 | .p = { .min = 10, .max = 30 }, |
171 | .p = { .min = 10, .max = 30 }, |
172 | .p1 = { .min = 1, .max = 3}, |
172 | .p1 = { .min = 1, .max = 3}, |
173 | .p2 = { .dot_limit = 270000, |
173 | .p2 = { .dot_limit = 270000, |
174 | .p2_slow = 10, |
174 | .p2_slow = 10, |
175 | .p2_fast = 10 |
175 | .p2_fast = 10 |
176 | }, |
176 | }, |
177 | }; |
177 | }; |
178 | 178 | ||
179 | static const intel_limit_t intel_limits_g4x_hdmi = { |
179 | static const intel_limit_t intel_limits_g4x_hdmi = { |
180 | .dot = { .min = 22000, .max = 400000 }, |
180 | .dot = { .min = 22000, .max = 400000 }, |
181 | .vco = { .min = 1750000, .max = 3500000}, |
181 | .vco = { .min = 1750000, .max = 3500000}, |
182 | .n = { .min = 1, .max = 4 }, |
182 | .n = { .min = 1, .max = 4 }, |
183 | .m = { .min = 104, .max = 138 }, |
183 | .m = { .min = 104, .max = 138 }, |
184 | .m1 = { .min = 16, .max = 23 }, |
184 | .m1 = { .min = 16, .max = 23 }, |
185 | .m2 = { .min = 5, .max = 11 }, |
185 | .m2 = { .min = 5, .max = 11 }, |
186 | .p = { .min = 5, .max = 80 }, |
186 | .p = { .min = 5, .max = 80 }, |
187 | .p1 = { .min = 1, .max = 8}, |
187 | .p1 = { .min = 1, .max = 8}, |
188 | .p2 = { .dot_limit = 165000, |
188 | .p2 = { .dot_limit = 165000, |
189 | .p2_slow = 10, .p2_fast = 5 }, |
189 | .p2_slow = 10, .p2_fast = 5 }, |
190 | }; |
190 | }; |
191 | 191 | ||
192 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
192 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
193 | .dot = { .min = 20000, .max = 115000 }, |
193 | .dot = { .min = 20000, .max = 115000 }, |
194 | .vco = { .min = 1750000, .max = 3500000 }, |
194 | .vco = { .min = 1750000, .max = 3500000 }, |
195 | .n = { .min = 1, .max = 3 }, |
195 | .n = { .min = 1, .max = 3 }, |
196 | .m = { .min = 104, .max = 138 }, |
196 | .m = { .min = 104, .max = 138 }, |
197 | .m1 = { .min = 17, .max = 23 }, |
197 | .m1 = { .min = 17, .max = 23 }, |
198 | .m2 = { .min = 5, .max = 11 }, |
198 | .m2 = { .min = 5, .max = 11 }, |
199 | .p = { .min = 28, .max = 112 }, |
199 | .p = { .min = 28, .max = 112 }, |
200 | .p1 = { .min = 2, .max = 8 }, |
200 | .p1 = { .min = 2, .max = 8 }, |
201 | .p2 = { .dot_limit = 0, |
201 | .p2 = { .dot_limit = 0, |
202 | .p2_slow = 14, .p2_fast = 14 |
202 | .p2_slow = 14, .p2_fast = 14 |
203 | }, |
203 | }, |
204 | }; |
204 | }; |
205 | 205 | ||
206 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
206 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
207 | .dot = { .min = 80000, .max = 224000 }, |
207 | .dot = { .min = 80000, .max = 224000 }, |
208 | .vco = { .min = 1750000, .max = 3500000 }, |
208 | .vco = { .min = 1750000, .max = 3500000 }, |
209 | .n = { .min = 1, .max = 3 }, |
209 | .n = { .min = 1, .max = 3 }, |
210 | .m = { .min = 104, .max = 138 }, |
210 | .m = { .min = 104, .max = 138 }, |
211 | .m1 = { .min = 17, .max = 23 }, |
211 | .m1 = { .min = 17, .max = 23 }, |
212 | .m2 = { .min = 5, .max = 11 }, |
212 | .m2 = { .min = 5, .max = 11 }, |
213 | .p = { .min = 14, .max = 42 }, |
213 | .p = { .min = 14, .max = 42 }, |
214 | .p1 = { .min = 2, .max = 6 }, |
214 | .p1 = { .min = 2, .max = 6 }, |
215 | .p2 = { .dot_limit = 0, |
215 | .p2 = { .dot_limit = 0, |
216 | .p2_slow = 7, .p2_fast = 7 |
216 | .p2_slow = 7, .p2_fast = 7 |
217 | }, |
217 | }, |
218 | }; |
218 | }; |
219 | 219 | ||
220 | static const intel_limit_t intel_limits_pineview_sdvo = { |
220 | static const intel_limit_t intel_limits_pineview_sdvo = { |
221 | .dot = { .min = 20000, .max = 400000}, |
221 | .dot = { .min = 20000, .max = 400000}, |
222 | .vco = { .min = 1700000, .max = 3500000 }, |
222 | .vco = { .min = 1700000, .max = 3500000 }, |
223 | /* Pineview's Ncounter is a ring counter */ |
223 | /* Pineview's Ncounter is a ring counter */ |
224 | .n = { .min = 3, .max = 6 }, |
224 | .n = { .min = 3, .max = 6 }, |
225 | .m = { .min = 2, .max = 256 }, |
225 | .m = { .min = 2, .max = 256 }, |
226 | /* Pineview only has one combined m divider, which we treat as m2. */ |
226 | /* Pineview only has one combined m divider, which we treat as m2. */ |
227 | .m1 = { .min = 0, .max = 0 }, |
227 | .m1 = { .min = 0, .max = 0 }, |
228 | .m2 = { .min = 0, .max = 254 }, |
228 | .m2 = { .min = 0, .max = 254 }, |
229 | .p = { .min = 5, .max = 80 }, |
229 | .p = { .min = 5, .max = 80 }, |
230 | .p1 = { .min = 1, .max = 8 }, |
230 | .p1 = { .min = 1, .max = 8 }, |
231 | .p2 = { .dot_limit = 200000, |
231 | .p2 = { .dot_limit = 200000, |
232 | .p2_slow = 10, .p2_fast = 5 }, |
232 | .p2_slow = 10, .p2_fast = 5 }, |
233 | }; |
233 | }; |
234 | 234 | ||
235 | static const intel_limit_t intel_limits_pineview_lvds = { |
235 | static const intel_limit_t intel_limits_pineview_lvds = { |
236 | .dot = { .min = 20000, .max = 400000 }, |
236 | .dot = { .min = 20000, .max = 400000 }, |
237 | .vco = { .min = 1700000, .max = 3500000 }, |
237 | .vco = { .min = 1700000, .max = 3500000 }, |
238 | .n = { .min = 3, .max = 6 }, |
238 | .n = { .min = 3, .max = 6 }, |
239 | .m = { .min = 2, .max = 256 }, |
239 | .m = { .min = 2, .max = 256 }, |
240 | .m1 = { .min = 0, .max = 0 }, |
240 | .m1 = { .min = 0, .max = 0 }, |
241 | .m2 = { .min = 0, .max = 254 }, |
241 | .m2 = { .min = 0, .max = 254 }, |
242 | .p = { .min = 7, .max = 112 }, |
242 | .p = { .min = 7, .max = 112 }, |
243 | .p1 = { .min = 1, .max = 8 }, |
243 | .p1 = { .min = 1, .max = 8 }, |
244 | .p2 = { .dot_limit = 112000, |
244 | .p2 = { .dot_limit = 112000, |
245 | .p2_slow = 14, .p2_fast = 14 }, |
245 | .p2_slow = 14, .p2_fast = 14 }, |
246 | }; |
246 | }; |
247 | 247 | ||
248 | /* Ironlake / Sandybridge |
248 | /* Ironlake / Sandybridge |
249 | * |
249 | * |
250 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
250 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
251 | * the range value for them is (actual_value - 2). |
251 | * the range value for them is (actual_value - 2). |
252 | */ |
252 | */ |
253 | static const intel_limit_t intel_limits_ironlake_dac = { |
253 | static const intel_limit_t intel_limits_ironlake_dac = { |
254 | .dot = { .min = 25000, .max = 350000 }, |
254 | .dot = { .min = 25000, .max = 350000 }, |
255 | .vco = { .min = 1760000, .max = 3510000 }, |
255 | .vco = { .min = 1760000, .max = 3510000 }, |
256 | .n = { .min = 1, .max = 5 }, |
256 | .n = { .min = 1, .max = 5 }, |
257 | .m = { .min = 79, .max = 127 }, |
257 | .m = { .min = 79, .max = 127 }, |
258 | .m1 = { .min = 12, .max = 22 }, |
258 | .m1 = { .min = 12, .max = 22 }, |
259 | .m2 = { .min = 5, .max = 9 }, |
259 | .m2 = { .min = 5, .max = 9 }, |
260 | .p = { .min = 5, .max = 80 }, |
260 | .p = { .min = 5, .max = 80 }, |
261 | .p1 = { .min = 1, .max = 8 }, |
261 | .p1 = { .min = 1, .max = 8 }, |
262 | .p2 = { .dot_limit = 225000, |
262 | .p2 = { .dot_limit = 225000, |
263 | .p2_slow = 10, .p2_fast = 5 }, |
263 | .p2_slow = 10, .p2_fast = 5 }, |
264 | }; |
264 | }; |
265 | 265 | ||
266 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
266 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
267 | .dot = { .min = 25000, .max = 350000 }, |
267 | .dot = { .min = 25000, .max = 350000 }, |
268 | .vco = { .min = 1760000, .max = 3510000 }, |
268 | .vco = { .min = 1760000, .max = 3510000 }, |
269 | .n = { .min = 1, .max = 3 }, |
269 | .n = { .min = 1, .max = 3 }, |
270 | .m = { .min = 79, .max = 118 }, |
270 | .m = { .min = 79, .max = 118 }, |
271 | .m1 = { .min = 12, .max = 22 }, |
271 | .m1 = { .min = 12, .max = 22 }, |
272 | .m2 = { .min = 5, .max = 9 }, |
272 | .m2 = { .min = 5, .max = 9 }, |
273 | .p = { .min = 28, .max = 112 }, |
273 | .p = { .min = 28, .max = 112 }, |
274 | .p1 = { .min = 2, .max = 8 }, |
274 | .p1 = { .min = 2, .max = 8 }, |
275 | .p2 = { .dot_limit = 225000, |
275 | .p2 = { .dot_limit = 225000, |
276 | .p2_slow = 14, .p2_fast = 14 }, |
276 | .p2_slow = 14, .p2_fast = 14 }, |
277 | }; |
277 | }; |
278 | 278 | ||
279 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
279 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
280 | .dot = { .min = 25000, .max = 350000 }, |
280 | .dot = { .min = 25000, .max = 350000 }, |
281 | .vco = { .min = 1760000, .max = 3510000 }, |
281 | .vco = { .min = 1760000, .max = 3510000 }, |
282 | .n = { .min = 1, .max = 3 }, |
282 | .n = { .min = 1, .max = 3 }, |
283 | .m = { .min = 79, .max = 127 }, |
283 | .m = { .min = 79, .max = 127 }, |
284 | .m1 = { .min = 12, .max = 22 }, |
284 | .m1 = { .min = 12, .max = 22 }, |
285 | .m2 = { .min = 5, .max = 9 }, |
285 | .m2 = { .min = 5, .max = 9 }, |
286 | .p = { .min = 14, .max = 56 }, |
286 | .p = { .min = 14, .max = 56 }, |
287 | .p1 = { .min = 2, .max = 8 }, |
287 | .p1 = { .min = 2, .max = 8 }, |
288 | .p2 = { .dot_limit = 225000, |
288 | .p2 = { .dot_limit = 225000, |
289 | .p2_slow = 7, .p2_fast = 7 }, |
289 | .p2_slow = 7, .p2_fast = 7 }, |
290 | }; |
290 | }; |
291 | 291 | ||
292 | /* LVDS 100mhz refclk limits. */ |
292 | /* LVDS 100mhz refclk limits. */ |
293 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
293 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
294 | .dot = { .min = 25000, .max = 350000 }, |
294 | .dot = { .min = 25000, .max = 350000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, |
296 | .n = { .min = 1, .max = 2 }, |
296 | .n = { .min = 1, .max = 2 }, |
297 | .m = { .min = 79, .max = 126 }, |
297 | .m = { .min = 79, .max = 126 }, |
298 | .m1 = { .min = 12, .max = 22 }, |
298 | .m1 = { .min = 12, .max = 22 }, |
299 | .m2 = { .min = 5, .max = 9 }, |
299 | .m2 = { .min = 5, .max = 9 }, |
300 | .p = { .min = 28, .max = 112 }, |
300 | .p = { .min = 28, .max = 112 }, |
301 | .p1 = { .min = 2, .max = 8 }, |
301 | .p1 = { .min = 2, .max = 8 }, |
302 | .p2 = { .dot_limit = 225000, |
302 | .p2 = { .dot_limit = 225000, |
303 | .p2_slow = 14, .p2_fast = 14 }, |
303 | .p2_slow = 14, .p2_fast = 14 }, |
304 | }; |
304 | }; |
305 | 305 | ||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
307 | .dot = { .min = 25000, .max = 350000 }, |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, |
309 | .n = { .min = 1, .max = 3 }, |
309 | .n = { .min = 1, .max = 3 }, |
310 | .m = { .min = 79, .max = 126 }, |
310 | .m = { .min = 79, .max = 126 }, |
311 | .m1 = { .min = 12, .max = 22 }, |
311 | .m1 = { .min = 12, .max = 22 }, |
312 | .m2 = { .min = 5, .max = 9 }, |
312 | .m2 = { .min = 5, .max = 9 }, |
313 | .p = { .min = 14, .max = 42 }, |
313 | .p = { .min = 14, .max = 42 }, |
314 | .p1 = { .min = 2, .max = 6 }, |
314 | .p1 = { .min = 2, .max = 6 }, |
315 | .p2 = { .dot_limit = 225000, |
315 | .p2 = { .dot_limit = 225000, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
317 | }; |
317 | }; |
318 | 318 | ||
319 | static const intel_limit_t intel_limits_vlv_dac = { |
319 | static const intel_limit_t intel_limits_vlv_dac = { |
320 | .dot = { .min = 25000, .max = 270000 }, |
320 | .dot = { .min = 25000, .max = 270000 }, |
321 | .vco = { .min = 4000000, .max = 6000000 }, |
321 | .vco = { .min = 4000000, .max = 6000000 }, |
322 | .n = { .min = 1, .max = 7 }, |
322 | .n = { .min = 1, .max = 7 }, |
323 | .m = { .min = 22, .max = 450 }, /* guess */ |
323 | .m = { .min = 22, .max = 450 }, /* guess */ |
324 | .m1 = { .min = 2, .max = 3 }, |
324 | .m1 = { .min = 2, .max = 3 }, |
325 | .m2 = { .min = 11, .max = 156 }, |
325 | .m2 = { .min = 11, .max = 156 }, |
326 | .p = { .min = 10, .max = 30 }, |
326 | .p = { .min = 10, .max = 30 }, |
327 | .p1 = { .min = 1, .max = 3 }, |
327 | .p1 = { .min = 1, .max = 3 }, |
328 | .p2 = { .dot_limit = 270000, |
328 | .p2 = { .dot_limit = 270000, |
329 | .p2_slow = 2, .p2_fast = 20 }, |
329 | .p2_slow = 2, .p2_fast = 20 }, |
330 | }; |
330 | }; |
331 | 331 | ||
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
333 | .dot = { .min = 25000, .max = 270000 }, |
333 | .dot = { .min = 25000, .max = 270000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
335 | .n = { .min = 1, .max = 7 }, |
335 | .n = { .min = 1, .max = 7 }, |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
337 | .m1 = { .min = 2, .max = 3 }, |
337 | .m1 = { .min = 2, .max = 3 }, |
338 | .m2 = { .min = 11, .max = 156 }, |
338 | .m2 = { .min = 11, .max = 156 }, |
339 | .p = { .min = 10, .max = 30 }, |
339 | .p = { .min = 10, .max = 30 }, |
340 | .p1 = { .min = 2, .max = 3 }, |
340 | .p1 = { .min = 2, .max = 3 }, |
341 | .p2 = { .dot_limit = 270000, |
341 | .p2 = { .dot_limit = 270000, |
342 | .p2_slow = 2, .p2_fast = 20 }, |
342 | .p2_slow = 2, .p2_fast = 20 }, |
343 | }; |
343 | }; |
344 | 344 | ||
345 | static const intel_limit_t intel_limits_vlv_dp = { |
345 | static const intel_limit_t intel_limits_vlv_dp = { |
346 | .dot = { .min = 25000, .max = 270000 }, |
346 | .dot = { .min = 25000, .max = 270000 }, |
347 | .vco = { .min = 4000000, .max = 6000000 }, |
347 | .vco = { .min = 4000000, .max = 6000000 }, |
348 | .n = { .min = 1, .max = 7 }, |
348 | .n = { .min = 1, .max = 7 }, |
349 | .m = { .min = 22, .max = 450 }, |
349 | .m = { .min = 22, .max = 450 }, |
350 | .m1 = { .min = 2, .max = 3 }, |
350 | .m1 = { .min = 2, .max = 3 }, |
351 | .m2 = { .min = 11, .max = 156 }, |
351 | .m2 = { .min = 11, .max = 156 }, |
352 | .p = { .min = 10, .max = 30 }, |
352 | .p = { .min = 10, .max = 30 }, |
353 | .p1 = { .min = 1, .max = 3 }, |
353 | .p1 = { .min = 1, .max = 3 }, |
354 | .p2 = { .dot_limit = 270000, |
354 | .p2 = { .dot_limit = 270000, |
355 | .p2_slow = 2, .p2_fast = 20 }, |
355 | .p2_slow = 2, .p2_fast = 20 }, |
356 | }; |
356 | }; |
357 | 357 | ||
358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
359 | int refclk) |
359 | int refclk) |
360 | { |
360 | { |
361 | struct drm_device *dev = crtc->dev; |
361 | struct drm_device *dev = crtc->dev; |
362 | const intel_limit_t *limit; |
362 | const intel_limit_t *limit; |
363 | 363 | ||
364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
365 | if (intel_is_dual_link_lvds(dev)) { |
365 | if (intel_is_dual_link_lvds(dev)) { |
366 | if (refclk == 100000) |
366 | if (refclk == 100000) |
367 | limit = &intel_limits_ironlake_dual_lvds_100m; |
367 | limit = &intel_limits_ironlake_dual_lvds_100m; |
368 | else |
368 | else |
369 | limit = &intel_limits_ironlake_dual_lvds; |
369 | limit = &intel_limits_ironlake_dual_lvds; |
370 | } else { |
370 | } else { |
371 | if (refclk == 100000) |
371 | if (refclk == 100000) |
372 | limit = &intel_limits_ironlake_single_lvds_100m; |
372 | limit = &intel_limits_ironlake_single_lvds_100m; |
373 | else |
373 | else |
374 | limit = &intel_limits_ironlake_single_lvds; |
374 | limit = &intel_limits_ironlake_single_lvds; |
375 | } |
375 | } |
376 | } else |
376 | } else |
377 | limit = &intel_limits_ironlake_dac; |
377 | limit = &intel_limits_ironlake_dac; |
378 | 378 | ||
379 | return limit; |
379 | return limit; |
380 | } |
380 | } |
381 | 381 | ||
382 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
382 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
383 | { |
383 | { |
384 | struct drm_device *dev = crtc->dev; |
384 | struct drm_device *dev = crtc->dev; |
385 | const intel_limit_t *limit; |
385 | const intel_limit_t *limit; |
386 | 386 | ||
387 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
387 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
388 | if (intel_is_dual_link_lvds(dev)) |
388 | if (intel_is_dual_link_lvds(dev)) |
389 | limit = &intel_limits_g4x_dual_channel_lvds; |
389 | limit = &intel_limits_g4x_dual_channel_lvds; |
390 | else |
390 | else |
391 | limit = &intel_limits_g4x_single_channel_lvds; |
391 | limit = &intel_limits_g4x_single_channel_lvds; |
392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
393 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
393 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
394 | limit = &intel_limits_g4x_hdmi; |
394 | limit = &intel_limits_g4x_hdmi; |
395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
396 | limit = &intel_limits_g4x_sdvo; |
396 | limit = &intel_limits_g4x_sdvo; |
397 | } else /* The option is for other outputs */ |
397 | } else /* The option is for other outputs */ |
398 | limit = &intel_limits_i9xx_sdvo; |
398 | limit = &intel_limits_i9xx_sdvo; |
399 | 399 | ||
400 | return limit; |
400 | return limit; |
401 | } |
401 | } |
402 | 402 | ||
403 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
403 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
404 | { |
404 | { |
405 | struct drm_device *dev = crtc->dev; |
405 | struct drm_device *dev = crtc->dev; |
406 | const intel_limit_t *limit; |
406 | const intel_limit_t *limit; |
407 | 407 | ||
408 | if (HAS_PCH_SPLIT(dev)) |
408 | if (HAS_PCH_SPLIT(dev)) |
409 | limit = intel_ironlake_limit(crtc, refclk); |
409 | limit = intel_ironlake_limit(crtc, refclk); |
410 | else if (IS_G4X(dev)) { |
410 | else if (IS_G4X(dev)) { |
411 | limit = intel_g4x_limit(crtc); |
411 | limit = intel_g4x_limit(crtc); |
412 | } else if (IS_PINEVIEW(dev)) { |
412 | } else if (IS_PINEVIEW(dev)) { |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
414 | limit = &intel_limits_pineview_lvds; |
414 | limit = &intel_limits_pineview_lvds; |
415 | else |
415 | else |
416 | limit = &intel_limits_pineview_sdvo; |
416 | limit = &intel_limits_pineview_sdvo; |
417 | } else if (IS_VALLEYVIEW(dev)) { |
417 | } else if (IS_VALLEYVIEW(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
419 | limit = &intel_limits_vlv_dac; |
419 | limit = &intel_limits_vlv_dac; |
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
421 | limit = &intel_limits_vlv_hdmi; |
421 | limit = &intel_limits_vlv_hdmi; |
422 | else |
422 | else |
423 | limit = &intel_limits_vlv_dp; |
423 | limit = &intel_limits_vlv_dp; |
424 | } else if (!IS_GEN2(dev)) { |
424 | } else if (!IS_GEN2(dev)) { |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
426 | limit = &intel_limits_i9xx_lvds; |
426 | limit = &intel_limits_i9xx_lvds; |
427 | else |
427 | else |
428 | limit = &intel_limits_i9xx_sdvo; |
428 | limit = &intel_limits_i9xx_sdvo; |
429 | } else { |
429 | } else { |
430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
431 | limit = &intel_limits_i8xx_lvds; |
431 | limit = &intel_limits_i8xx_lvds; |
432 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
432 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
433 | limit = &intel_limits_i8xx_dvo; |
433 | limit = &intel_limits_i8xx_dvo; |
434 | else |
434 | else |
435 | limit = &intel_limits_i8xx_dac; |
435 | limit = &intel_limits_i8xx_dac; |
436 | } |
436 | } |
437 | return limit; |
437 | return limit; |
438 | } |
438 | } |
439 | 439 | ||
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
442 | { |
442 | { |
443 | clock->m = clock->m2 + 2; |
443 | clock->m = clock->m2 + 2; |
444 | clock->p = clock->p1 * clock->p2; |
444 | clock->p = clock->p1 * clock->p2; |
445 | clock->vco = refclk * clock->m / clock->n; |
445 | clock->vco = refclk * clock->m / clock->n; |
446 | clock->dot = clock->vco / clock->p; |
446 | clock->dot = clock->vco / clock->p; |
447 | } |
447 | } |
448 | 448 | ||
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
450 | { |
450 | { |
451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
452 | } |
452 | } |
453 | 453 | ||
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
455 | { |
455 | { |
456 | clock->m = i9xx_dpll_compute_m(clock); |
456 | clock->m = i9xx_dpll_compute_m(clock); |
457 | clock->p = clock->p1 * clock->p2; |
457 | clock->p = clock->p1 * clock->p2; |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
459 | clock->dot = clock->vco / clock->p; |
459 | clock->dot = clock->vco / clock->p; |
460 | } |
460 | } |
461 | 461 | ||
462 | /** |
462 | /** |
463 | * Returns whether any output on the specified pipe is of the specified type |
463 | * Returns whether any output on the specified pipe is of the specified type |
464 | */ |
464 | */ |
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
466 | { |
466 | { |
467 | struct drm_device *dev = crtc->dev; |
467 | struct drm_device *dev = crtc->dev; |
468 | struct intel_encoder *encoder; |
468 | struct intel_encoder *encoder; |
469 | 469 | ||
470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
471 | if (encoder->type == type) |
471 | if (encoder->type == type) |
472 | return true; |
472 | return true; |
473 | 473 | ||
474 | return false; |
474 | return false; |
475 | } |
475 | } |
476 | 476 | ||
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
478 | /** |
478 | /** |
479 | * Returns whether the given set of divisors are valid for a given refclk with |
479 | * Returns whether the given set of divisors are valid for a given refclk with |
480 | * the given connectors. |
480 | * the given connectors. |
481 | */ |
481 | */ |
482 | 482 | ||
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
484 | const intel_limit_t *limit, |
484 | const intel_limit_t *limit, |
485 | const intel_clock_t *clock) |
485 | const intel_clock_t *clock) |
486 | { |
486 | { |
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
488 | INTELPllInvalid("p1 out of range\n"); |
488 | INTELPllInvalid("p1 out of range\n"); |
489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
490 | INTELPllInvalid("p out of range\n"); |
490 | INTELPllInvalid("p out of range\n"); |
491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
492 | INTELPllInvalid("m2 out of range\n"); |
492 | INTELPllInvalid("m2 out of range\n"); |
493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
494 | INTELPllInvalid("m1 out of range\n"); |
494 | INTELPllInvalid("m1 out of range\n"); |
495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
496 | INTELPllInvalid("m1 <= m2\n"); |
496 | INTELPllInvalid("m1 <= m2\n"); |
497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
498 | INTELPllInvalid("m out of range\n"); |
498 | INTELPllInvalid("m out of range\n"); |
499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
500 | INTELPllInvalid("n out of range\n"); |
500 | INTELPllInvalid("n out of range\n"); |
501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
502 | INTELPllInvalid("vco out of range\n"); |
502 | INTELPllInvalid("vco out of range\n"); |
503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
504 | * connector, etc., rather than just a single range. |
504 | * connector, etc., rather than just a single range. |
505 | */ |
505 | */ |
506 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
506 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
507 | INTELPllInvalid("dot out of range\n"); |
507 | INTELPllInvalid("dot out of range\n"); |
508 | 508 | ||
509 | return true; |
509 | return true; |
510 | } |
510 | } |
511 | 511 | ||
512 | static bool |
512 | static bool |
513 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
513 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
514 | int target, int refclk, intel_clock_t *match_clock, |
514 | int target, int refclk, intel_clock_t *match_clock, |
515 | intel_clock_t *best_clock) |
515 | intel_clock_t *best_clock) |
516 | { |
516 | { |
517 | struct drm_device *dev = crtc->dev; |
517 | struct drm_device *dev = crtc->dev; |
518 | intel_clock_t clock; |
518 | intel_clock_t clock; |
519 | int err = target; |
519 | int err = target; |
520 | 520 | ||
521 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
521 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
522 | /* |
522 | /* |
523 | * For LVDS just rely on its current settings for dual-channel. |
523 | * For LVDS just rely on its current settings for dual-channel. |
524 | * We haven't figured out how to reliably set up different |
524 | * We haven't figured out how to reliably set up different |
525 | * single/dual channel state, if we even can. |
525 | * single/dual channel state, if we even can. |
526 | */ |
526 | */ |
527 | if (intel_is_dual_link_lvds(dev)) |
527 | if (intel_is_dual_link_lvds(dev)) |
528 | clock.p2 = limit->p2.p2_fast; |
528 | clock.p2 = limit->p2.p2_fast; |
529 | else |
529 | else |
530 | clock.p2 = limit->p2.p2_slow; |
530 | clock.p2 = limit->p2.p2_slow; |
531 | } else { |
531 | } else { |
532 | if (target < limit->p2.dot_limit) |
532 | if (target < limit->p2.dot_limit) |
533 | clock.p2 = limit->p2.p2_slow; |
533 | clock.p2 = limit->p2.p2_slow; |
534 | else |
534 | else |
535 | clock.p2 = limit->p2.p2_fast; |
535 | clock.p2 = limit->p2.p2_fast; |
536 | } |
536 | } |
537 | 537 | ||
538 | memset(best_clock, 0, sizeof(*best_clock)); |
538 | memset(best_clock, 0, sizeof(*best_clock)); |
539 | 539 | ||
540 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
540 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
541 | clock.m1++) { |
541 | clock.m1++) { |
542 | for (clock.m2 = limit->m2.min; |
542 | for (clock.m2 = limit->m2.min; |
543 | clock.m2 <= limit->m2.max; clock.m2++) { |
543 | clock.m2 <= limit->m2.max; clock.m2++) { |
544 | if (clock.m2 >= clock.m1) |
544 | if (clock.m2 >= clock.m1) |
545 | break; |
545 | break; |
546 | for (clock.n = limit->n.min; |
546 | for (clock.n = limit->n.min; |
547 | clock.n <= limit->n.max; clock.n++) { |
547 | clock.n <= limit->n.max; clock.n++) { |
548 | for (clock.p1 = limit->p1.min; |
548 | for (clock.p1 = limit->p1.min; |
549 | clock.p1 <= limit->p1.max; clock.p1++) { |
549 | clock.p1 <= limit->p1.max; clock.p1++) { |
550 | int this_err; |
550 | int this_err; |
551 | 551 | ||
552 | i9xx_clock(refclk, &clock); |
552 | i9xx_clock(refclk, &clock); |
553 | if (!intel_PLL_is_valid(dev, limit, |
553 | if (!intel_PLL_is_valid(dev, limit, |
554 | &clock)) |
554 | &clock)) |
555 | continue; |
555 | continue; |
556 | if (match_clock && |
556 | if (match_clock && |
557 | clock.p != match_clock->p) |
557 | clock.p != match_clock->p) |
558 | continue; |
558 | continue; |
559 | 559 | ||
560 | this_err = abs(clock.dot - target); |
560 | this_err = abs(clock.dot - target); |
561 | if (this_err < err) { |
561 | if (this_err < err) { |
562 | *best_clock = clock; |
562 | *best_clock = clock; |
563 | err = this_err; |
563 | err = this_err; |
564 | } |
564 | } |
565 | } |
565 | } |
566 | } |
566 | } |
567 | } |
567 | } |
568 | } |
568 | } |
569 | 569 | ||
570 | return (err != target); |
570 | return (err != target); |
571 | } |
571 | } |
572 | 572 | ||
573 | static bool |
573 | static bool |
574 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
574 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
575 | int target, int refclk, intel_clock_t *match_clock, |
575 | int target, int refclk, intel_clock_t *match_clock, |
576 | intel_clock_t *best_clock) |
576 | intel_clock_t *best_clock) |
577 | { |
577 | { |
578 | struct drm_device *dev = crtc->dev; |
578 | struct drm_device *dev = crtc->dev; |
579 | intel_clock_t clock; |
579 | intel_clock_t clock; |
580 | int err = target; |
580 | int err = target; |
581 | 581 | ||
582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
583 | /* |
583 | /* |
584 | * For LVDS just rely on its current settings for dual-channel. |
584 | * For LVDS just rely on its current settings for dual-channel. |
585 | * We haven't figured out how to reliably set up different |
585 | * We haven't figured out how to reliably set up different |
586 | * single/dual channel state, if we even can. |
586 | * single/dual channel state, if we even can. |
587 | */ |
587 | */ |
588 | if (intel_is_dual_link_lvds(dev)) |
588 | if (intel_is_dual_link_lvds(dev)) |
589 | clock.p2 = limit->p2.p2_fast; |
589 | clock.p2 = limit->p2.p2_fast; |
590 | else |
590 | else |
591 | clock.p2 = limit->p2.p2_slow; |
591 | clock.p2 = limit->p2.p2_slow; |
592 | } else { |
592 | } else { |
593 | if (target < limit->p2.dot_limit) |
593 | if (target < limit->p2.dot_limit) |
594 | clock.p2 = limit->p2.p2_slow; |
594 | clock.p2 = limit->p2.p2_slow; |
595 | else |
595 | else |
596 | clock.p2 = limit->p2.p2_fast; |
596 | clock.p2 = limit->p2.p2_fast; |
597 | } |
597 | } |
598 | 598 | ||
599 | memset(best_clock, 0, sizeof(*best_clock)); |
599 | memset(best_clock, 0, sizeof(*best_clock)); |
600 | 600 | ||
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
602 | clock.m1++) { |
602 | clock.m1++) { |
603 | for (clock.m2 = limit->m2.min; |
603 | for (clock.m2 = limit->m2.min; |
604 | clock.m2 <= limit->m2.max; clock.m2++) { |
604 | clock.m2 <= limit->m2.max; clock.m2++) { |
605 | for (clock.n = limit->n.min; |
605 | for (clock.n = limit->n.min; |
606 | clock.n <= limit->n.max; clock.n++) { |
606 | clock.n <= limit->n.max; clock.n++) { |
607 | for (clock.p1 = limit->p1.min; |
607 | for (clock.p1 = limit->p1.min; |
608 | clock.p1 <= limit->p1.max; clock.p1++) { |
608 | clock.p1 <= limit->p1.max; clock.p1++) { |
609 | int this_err; |
609 | int this_err; |
610 | 610 | ||
611 | pineview_clock(refclk, &clock); |
611 | pineview_clock(refclk, &clock); |
612 | if (!intel_PLL_is_valid(dev, limit, |
612 | if (!intel_PLL_is_valid(dev, limit, |
613 | &clock)) |
613 | &clock)) |
614 | continue; |
614 | continue; |
615 | if (match_clock && |
615 | if (match_clock && |
616 | clock.p != match_clock->p) |
616 | clock.p != match_clock->p) |
617 | continue; |
617 | continue; |
618 | 618 | ||
619 | this_err = abs(clock.dot - target); |
619 | this_err = abs(clock.dot - target); |
620 | if (this_err < err) { |
620 | if (this_err < err) { |
621 | *best_clock = clock; |
621 | *best_clock = clock; |
622 | err = this_err; |
622 | err = this_err; |
623 | } |
623 | } |
624 | } |
624 | } |
625 | } |
625 | } |
626 | } |
626 | } |
627 | } |
627 | } |
628 | 628 | ||
629 | return (err != target); |
629 | return (err != target); |
630 | } |
630 | } |
631 | 631 | ||
632 | static bool |
632 | static bool |
633 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
633 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
634 | int target, int refclk, intel_clock_t *match_clock, |
634 | int target, int refclk, intel_clock_t *match_clock, |
635 | intel_clock_t *best_clock) |
635 | intel_clock_t *best_clock) |
636 | { |
636 | { |
637 | struct drm_device *dev = crtc->dev; |
637 | struct drm_device *dev = crtc->dev; |
638 | intel_clock_t clock; |
638 | intel_clock_t clock; |
639 | int max_n; |
639 | int max_n; |
640 | bool found; |
640 | bool found; |
641 | /* approximately equals target * 0.00585 */ |
641 | /* approximately equals target * 0.00585 */ |
642 | int err_most = (target >> 8) + (target >> 9); |
642 | int err_most = (target >> 8) + (target >> 9); |
643 | found = false; |
643 | found = false; |
644 | 644 | ||
645 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
645 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
646 | if (intel_is_dual_link_lvds(dev)) |
646 | if (intel_is_dual_link_lvds(dev)) |
647 | clock.p2 = limit->p2.p2_fast; |
647 | clock.p2 = limit->p2.p2_fast; |
648 | else |
648 | else |
649 | clock.p2 = limit->p2.p2_slow; |
649 | clock.p2 = limit->p2.p2_slow; |
650 | } else { |
650 | } else { |
651 | if (target < limit->p2.dot_limit) |
651 | if (target < limit->p2.dot_limit) |
652 | clock.p2 = limit->p2.p2_slow; |
652 | clock.p2 = limit->p2.p2_slow; |
653 | else |
653 | else |
654 | clock.p2 = limit->p2.p2_fast; |
654 | clock.p2 = limit->p2.p2_fast; |
655 | } |
655 | } |
656 | 656 | ||
657 | memset(best_clock, 0, sizeof(*best_clock)); |
657 | memset(best_clock, 0, sizeof(*best_clock)); |
658 | max_n = limit->n.max; |
658 | max_n = limit->n.max; |
659 | /* based on hardware requirement, prefer smaller n to precision */ |
659 | /* based on hardware requirement, prefer smaller n to precision */ |
660 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
660 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
661 | /* based on hardware requirement, prefere larger m1,m2 */ |
661 | /* based on hardware requirement, prefere larger m1,m2 */ |
662 | for (clock.m1 = limit->m1.max; |
662 | for (clock.m1 = limit->m1.max; |
663 | clock.m1 >= limit->m1.min; clock.m1--) { |
663 | clock.m1 >= limit->m1.min; clock.m1--) { |
664 | for (clock.m2 = limit->m2.max; |
664 | for (clock.m2 = limit->m2.max; |
665 | clock.m2 >= limit->m2.min; clock.m2--) { |
665 | clock.m2 >= limit->m2.min; clock.m2--) { |
666 | for (clock.p1 = limit->p1.max; |
666 | for (clock.p1 = limit->p1.max; |
667 | clock.p1 >= limit->p1.min; clock.p1--) { |
667 | clock.p1 >= limit->p1.min; clock.p1--) { |
668 | int this_err; |
668 | int this_err; |
669 | 669 | ||
670 | i9xx_clock(refclk, &clock); |
670 | i9xx_clock(refclk, &clock); |
671 | if (!intel_PLL_is_valid(dev, limit, |
671 | if (!intel_PLL_is_valid(dev, limit, |
672 | &clock)) |
672 | &clock)) |
673 | continue; |
673 | continue; |
674 | 674 | ||
675 | this_err = abs(clock.dot - target); |
675 | this_err = abs(clock.dot - target); |
676 | if (this_err < err_most) { |
676 | if (this_err < err_most) { |
677 | *best_clock = clock; |
677 | *best_clock = clock; |
678 | err_most = this_err; |
678 | err_most = this_err; |
679 | max_n = clock.n; |
679 | max_n = clock.n; |
680 | found = true; |
680 | found = true; |
681 | } |
681 | } |
682 | } |
682 | } |
683 | } |
683 | } |
684 | } |
684 | } |
685 | } |
685 | } |
686 | return found; |
686 | return found; |
687 | } |
687 | } |
688 | 688 | ||
689 | static bool |
689 | static bool |
690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
691 | int target, int refclk, intel_clock_t *match_clock, |
691 | int target, int refclk, intel_clock_t *match_clock, |
692 | intel_clock_t *best_clock) |
692 | intel_clock_t *best_clock) |
693 | { |
693 | { |
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
695 | u32 m, n, fastclk; |
695 | u32 m, n, fastclk; |
696 | u32 updrate, minupdate, p; |
696 | u32 updrate, minupdate, p; |
697 | unsigned long bestppm, ppm, absppm; |
697 | unsigned long bestppm, ppm, absppm; |
698 | int dotclk, flag; |
698 | int dotclk, flag; |
699 | 699 | ||
700 | flag = 0; |
700 | flag = 0; |
701 | dotclk = target * 1000; |
701 | dotclk = target * 1000; |
702 | bestppm = 1000000; |
702 | bestppm = 1000000; |
703 | ppm = absppm = 0; |
703 | ppm = absppm = 0; |
704 | fastclk = dotclk / (2*100); |
704 | fastclk = dotclk / (2*100); |
705 | updrate = 0; |
705 | updrate = 0; |
706 | minupdate = 19200; |
706 | minupdate = 19200; |
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
709 | 709 | ||
710 | /* based on hardware requirement, prefer smaller n to precision */ |
710 | /* based on hardware requirement, prefer smaller n to precision */ |
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
712 | updrate = refclk / n; |
712 | updrate = refclk / n; |
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
715 | if (p2 > 10) |
715 | if (p2 > 10) |
716 | p2 = p2 - 1; |
716 | p2 = p2 - 1; |
717 | p = p1 * p2; |
717 | p = p1 * p2; |
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
721 | refclk) / (2*refclk)); |
721 | refclk) / (2*refclk)); |
722 | m = m1 * m2; |
722 | m = m1 * m2; |
723 | vco = updrate * m; |
723 | vco = updrate * m; |
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
728 | bestppm = 0; |
728 | bestppm = 0; |
729 | flag = 1; |
729 | flag = 1; |
730 | } |
730 | } |
731 | if (absppm < bestppm - 10) { |
731 | if (absppm < bestppm - 10) { |
732 | bestppm = absppm; |
732 | bestppm = absppm; |
733 | flag = 1; |
733 | flag = 1; |
734 | } |
734 | } |
735 | if (flag) { |
735 | if (flag) { |
736 | bestn = n; |
736 | bestn = n; |
737 | bestm1 = m1; |
737 | bestm1 = m1; |
738 | bestm2 = m2; |
738 | bestm2 = m2; |
739 | bestp1 = p1; |
739 | bestp1 = p1; |
740 | bestp2 = p2; |
740 | bestp2 = p2; |
741 | flag = 0; |
741 | flag = 0; |
742 | } |
742 | } |
743 | } |
743 | } |
744 | } |
744 | } |
745 | } |
745 | } |
746 | } |
746 | } |
747 | } |
747 | } |
748 | best_clock->n = bestn; |
748 | best_clock->n = bestn; |
749 | best_clock->m1 = bestm1; |
749 | best_clock->m1 = bestm1; |
750 | best_clock->m2 = bestm2; |
750 | best_clock->m2 = bestm2; |
751 | best_clock->p1 = bestp1; |
751 | best_clock->p1 = bestp1; |
752 | best_clock->p2 = bestp2; |
752 | best_clock->p2 = bestp2; |
753 | 753 | ||
754 | return true; |
754 | return true; |
755 | } |
755 | } |
756 | 756 | ||
757 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
757 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
758 | enum pipe pipe) |
758 | enum pipe pipe) |
759 | { |
759 | { |
760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
762 | 762 | ||
763 | return intel_crtc->config.cpu_transcoder; |
763 | return intel_crtc->config.cpu_transcoder; |
764 | } |
764 | } |
765 | 765 | ||
766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
767 | { |
767 | { |
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
770 | 770 | ||
771 | frame = I915_READ(frame_reg); |
771 | frame = I915_READ(frame_reg); |
772 | 772 | ||
773 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
773 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
774 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
774 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
775 | } |
775 | } |
776 | 776 | ||
777 | /** |
777 | /** |
778 | * intel_wait_for_vblank - wait for vblank on a given pipe |
778 | * intel_wait_for_vblank - wait for vblank on a given pipe |
779 | * @dev: drm device |
779 | * @dev: drm device |
780 | * @pipe: pipe to wait for |
780 | * @pipe: pipe to wait for |
781 | * |
781 | * |
782 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
782 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
783 | * mode setting code. |
783 | * mode setting code. |
784 | */ |
784 | */ |
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
786 | { |
786 | { |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
788 | int pipestat_reg = PIPESTAT(pipe); |
788 | int pipestat_reg = PIPESTAT(pipe); |
789 | 789 | ||
790 | if (INTEL_INFO(dev)->gen >= 5) { |
790 | if (INTEL_INFO(dev)->gen >= 5) { |
791 | ironlake_wait_for_vblank(dev, pipe); |
791 | ironlake_wait_for_vblank(dev, pipe); |
792 | return; |
792 | return; |
793 | } |
793 | } |
794 | 794 | ||
795 | /* Clear existing vblank status. Note this will clear any other |
795 | /* Clear existing vblank status. Note this will clear any other |
796 | * sticky status fields as well. |
796 | * sticky status fields as well. |
797 | * |
797 | * |
798 | * This races with i915_driver_irq_handler() with the result |
798 | * This races with i915_driver_irq_handler() with the result |
799 | * that either function could miss a vblank event. Here it is not |
799 | * that either function could miss a vblank event. Here it is not |
800 | * fatal, as we will either wait upon the next vblank interrupt or |
800 | * fatal, as we will either wait upon the next vblank interrupt or |
801 | * timeout. Generally speaking intel_wait_for_vblank() is only |
801 | * timeout. Generally speaking intel_wait_for_vblank() is only |
802 | * called during modeset at which time the GPU should be idle and |
802 | * called during modeset at which time the GPU should be idle and |
803 | * should *not* be performing page flips and thus not waiting on |
803 | * should *not* be performing page flips and thus not waiting on |
804 | * vblanks... |
804 | * vblanks... |
805 | * Currently, the result of us stealing a vblank from the irq |
805 | * Currently, the result of us stealing a vblank from the irq |
806 | * handler is that a single frame will be skipped during swapbuffers. |
806 | * handler is that a single frame will be skipped during swapbuffers. |
807 | */ |
807 | */ |
808 | I915_WRITE(pipestat_reg, |
808 | I915_WRITE(pipestat_reg, |
809 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
809 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
810 | 810 | ||
811 | /* Wait for vblank interrupt bit to set */ |
811 | /* Wait for vblank interrupt bit to set */ |
812 | if (wait_for(I915_READ(pipestat_reg) & |
812 | if (wait_for(I915_READ(pipestat_reg) & |
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
814 | 50)) |
814 | 50)) |
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
816 | } |
816 | } |
817 | 817 | ||
818 | /* |
818 | /* |
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
820 | * @dev: drm device |
820 | * @dev: drm device |
821 | * @pipe: pipe to wait for |
821 | * @pipe: pipe to wait for |
822 | * |
822 | * |
823 | * After disabling a pipe, we can't wait for vblank in the usual way, |
823 | * After disabling a pipe, we can't wait for vblank in the usual way, |
824 | * spinning on the vblank interrupt status bit, since we won't actually |
824 | * spinning on the vblank interrupt status bit, since we won't actually |
825 | * see an interrupt when the pipe is disabled. |
825 | * see an interrupt when the pipe is disabled. |
826 | * |
826 | * |
827 | * On Gen4 and above: |
827 | * On Gen4 and above: |
828 | * wait for the pipe register state bit to turn off |
828 | * wait for the pipe register state bit to turn off |
829 | * |
829 | * |
830 | * Otherwise: |
830 | * Otherwise: |
831 | * wait for the display line value to settle (it usually |
831 | * wait for the display line value to settle (it usually |
832 | * ends up stopping at the start of the next frame). |
832 | * ends up stopping at the start of the next frame). |
833 | * |
833 | * |
834 | */ |
834 | */ |
835 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
835 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
836 | { |
836 | { |
837 | struct drm_i915_private *dev_priv = dev->dev_private; |
837 | struct drm_i915_private *dev_priv = dev->dev_private; |
838 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
838 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
839 | pipe); |
839 | pipe); |
840 | 840 | ||
841 | if (INTEL_INFO(dev)->gen >= 4) { |
841 | if (INTEL_INFO(dev)->gen >= 4) { |
842 | int reg = PIPECONF(cpu_transcoder); |
842 | int reg = PIPECONF(cpu_transcoder); |
843 | 843 | ||
844 | /* Wait for the Pipe State to go off */ |
844 | /* Wait for the Pipe State to go off */ |
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
846 | 100)) |
846 | 100)) |
847 | WARN(1, "pipe_off wait timed out\n"); |
847 | WARN(1, "pipe_off wait timed out\n"); |
848 | } else { |
848 | } else { |
849 | u32 last_line, line_mask; |
849 | u32 last_line, line_mask; |
850 | int reg = PIPEDSL(pipe); |
850 | int reg = PIPEDSL(pipe); |
851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
852 | 852 | ||
853 | if (IS_GEN2(dev)) |
853 | if (IS_GEN2(dev)) |
854 | line_mask = DSL_LINEMASK_GEN2; |
854 | line_mask = DSL_LINEMASK_GEN2; |
855 | else |
855 | else |
856 | line_mask = DSL_LINEMASK_GEN3; |
856 | line_mask = DSL_LINEMASK_GEN3; |
857 | 857 | ||
858 | /* Wait for the display line to settle */ |
858 | /* Wait for the display line to settle */ |
859 | do { |
859 | do { |
860 | last_line = I915_READ(reg) & line_mask; |
860 | last_line = I915_READ(reg) & line_mask; |
861 | mdelay(5); |
861 | mdelay(5); |
862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
863 | time_after(timeout, GetTimerTicks())); |
863 | time_after(timeout, GetTimerTicks())); |
864 | if (time_after(GetTimerTicks(), timeout)) |
864 | if (time_after(GetTimerTicks(), timeout)) |
865 | WARN(1, "pipe_off wait timed out\n"); |
865 | WARN(1, "pipe_off wait timed out\n"); |
866 | } |
866 | } |
867 | } |
867 | } |
868 | 868 | ||
869 | /* |
869 | /* |
870 | * ibx_digital_port_connected - is the specified port connected? |
870 | * ibx_digital_port_connected - is the specified port connected? |
871 | * @dev_priv: i915 private structure |
871 | * @dev_priv: i915 private structure |
872 | * @port: the port to test |
872 | * @port: the port to test |
873 | * |
873 | * |
874 | * Returns true if @port is connected, false otherwise. |
874 | * Returns true if @port is connected, false otherwise. |
875 | */ |
875 | */ |
876 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
876 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
877 | struct intel_digital_port *port) |
877 | struct intel_digital_port *port) |
878 | { |
878 | { |
879 | u32 bit; |
879 | u32 bit; |
880 | 880 | ||
881 | if (HAS_PCH_IBX(dev_priv->dev)) { |
881 | if (HAS_PCH_IBX(dev_priv->dev)) { |
882 | switch(port->port) { |
882 | switch(port->port) { |
883 | case PORT_B: |
883 | case PORT_B: |
884 | bit = SDE_PORTB_HOTPLUG; |
884 | bit = SDE_PORTB_HOTPLUG; |
885 | break; |
885 | break; |
886 | case PORT_C: |
886 | case PORT_C: |
887 | bit = SDE_PORTC_HOTPLUG; |
887 | bit = SDE_PORTC_HOTPLUG; |
888 | break; |
888 | break; |
889 | case PORT_D: |
889 | case PORT_D: |
890 | bit = SDE_PORTD_HOTPLUG; |
890 | bit = SDE_PORTD_HOTPLUG; |
891 | break; |
891 | break; |
892 | default: |
892 | default: |
893 | return true; |
893 | return true; |
894 | } |
894 | } |
895 | } else { |
895 | } else { |
896 | switch(port->port) { |
896 | switch(port->port) { |
897 | case PORT_B: |
897 | case PORT_B: |
898 | bit = SDE_PORTB_HOTPLUG_CPT; |
898 | bit = SDE_PORTB_HOTPLUG_CPT; |
899 | break; |
899 | break; |
900 | case PORT_C: |
900 | case PORT_C: |
901 | bit = SDE_PORTC_HOTPLUG_CPT; |
901 | bit = SDE_PORTC_HOTPLUG_CPT; |
902 | break; |
902 | break; |
903 | case PORT_D: |
903 | case PORT_D: |
904 | bit = SDE_PORTD_HOTPLUG_CPT; |
904 | bit = SDE_PORTD_HOTPLUG_CPT; |
905 | break; |
905 | break; |
906 | default: |
906 | default: |
907 | return true; |
907 | return true; |
908 | } |
908 | } |
909 | } |
909 | } |
910 | 910 | ||
911 | return I915_READ(SDEISR) & bit; |
911 | return I915_READ(SDEISR) & bit; |
912 | } |
912 | } |
913 | 913 | ||
914 | static const char *state_string(bool enabled) |
914 | static const char *state_string(bool enabled) |
915 | { |
915 | { |
916 | return enabled ? "on" : "off"; |
916 | return enabled ? "on" : "off"; |
917 | } |
917 | } |
918 | 918 | ||
919 | /* Only for pre-ILK configs */ |
919 | /* Only for pre-ILK configs */ |
920 | void assert_pll(struct drm_i915_private *dev_priv, |
920 | void assert_pll(struct drm_i915_private *dev_priv, |
921 | enum pipe pipe, bool state) |
921 | enum pipe pipe, bool state) |
922 | { |
922 | { |
923 | int reg; |
923 | int reg; |
924 | u32 val; |
924 | u32 val; |
925 | bool cur_state; |
925 | bool cur_state; |
926 | 926 | ||
927 | reg = DPLL(pipe); |
927 | reg = DPLL(pipe); |
928 | val = I915_READ(reg); |
928 | val = I915_READ(reg); |
929 | cur_state = !!(val & DPLL_VCO_ENABLE); |
929 | cur_state = !!(val & DPLL_VCO_ENABLE); |
930 | WARN(cur_state != state, |
930 | WARN(cur_state != state, |
931 | "PLL state assertion failure (expected %s, current %s)\n", |
931 | "PLL state assertion failure (expected %s, current %s)\n", |
932 | state_string(state), state_string(cur_state)); |
932 | state_string(state), state_string(cur_state)); |
933 | } |
933 | } |
934 | 934 | ||
935 | struct intel_shared_dpll * |
935 | struct intel_shared_dpll * |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
937 | { |
937 | { |
938 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
938 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
939 | 939 | ||
940 | if (crtc->config.shared_dpll < 0) |
940 | if (crtc->config.shared_dpll < 0) |
941 | return NULL; |
941 | return NULL; |
942 | 942 | ||
943 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
943 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
944 | } |
944 | } |
945 | 945 | ||
946 | /* For ILK+ */ |
946 | /* For ILK+ */ |
947 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
947 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
948 | struct intel_shared_dpll *pll, |
948 | struct intel_shared_dpll *pll, |
949 | bool state) |
949 | bool state) |
950 | { |
950 | { |
951 | bool cur_state; |
951 | bool cur_state; |
952 | struct intel_dpll_hw_state hw_state; |
952 | struct intel_dpll_hw_state hw_state; |
953 | 953 | ||
954 | if (HAS_PCH_LPT(dev_priv->dev)) { |
954 | if (HAS_PCH_LPT(dev_priv->dev)) { |
955 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
955 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
956 | return; |
956 | return; |
957 | } |
957 | } |
958 | 958 | ||
959 | if (WARN (!pll, |
959 | if (WARN (!pll, |
960 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
960 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
961 | return; |
961 | return; |
962 | 962 | ||
963 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
963 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
964 | WARN(cur_state != state, |
964 | WARN(cur_state != state, |
965 | "%s assertion failure (expected %s, current %s)\n", |
965 | "%s assertion failure (expected %s, current %s)\n", |
966 | pll->name, state_string(state), state_string(cur_state)); |
966 | pll->name, state_string(state), state_string(cur_state)); |
967 | } |
967 | } |
968 | 968 | ||
969 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
969 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
970 | enum pipe pipe, bool state) |
970 | enum pipe pipe, bool state) |
971 | { |
971 | { |
972 | int reg; |
972 | int reg; |
973 | u32 val; |
973 | u32 val; |
974 | bool cur_state; |
974 | bool cur_state; |
975 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
975 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
976 | pipe); |
976 | pipe); |
977 | 977 | ||
978 | if (HAS_DDI(dev_priv->dev)) { |
978 | if (HAS_DDI(dev_priv->dev)) { |
979 | /* DDI does not have a specific FDI_TX register */ |
979 | /* DDI does not have a specific FDI_TX register */ |
980 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
980 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
981 | val = I915_READ(reg); |
981 | val = I915_READ(reg); |
982 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
982 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
983 | } else { |
983 | } else { |
984 | reg = FDI_TX_CTL(pipe); |
984 | reg = FDI_TX_CTL(pipe); |
985 | val = I915_READ(reg); |
985 | val = I915_READ(reg); |
986 | cur_state = !!(val & FDI_TX_ENABLE); |
986 | cur_state = !!(val & FDI_TX_ENABLE); |
987 | } |
987 | } |
988 | WARN(cur_state != state, |
988 | WARN(cur_state != state, |
989 | "FDI TX state assertion failure (expected %s, current %s)\n", |
989 | "FDI TX state assertion failure (expected %s, current %s)\n", |
990 | state_string(state), state_string(cur_state)); |
990 | state_string(state), state_string(cur_state)); |
991 | } |
991 | } |
992 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
992 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
993 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
993 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
994 | 994 | ||
995 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
995 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe, bool state) |
996 | enum pipe pipe, bool state) |
997 | { |
997 | { |
998 | int reg; |
998 | int reg; |
999 | u32 val; |
999 | u32 val; |
1000 | bool cur_state; |
1000 | bool cur_state; |
1001 | 1001 | ||
1002 | reg = FDI_RX_CTL(pipe); |
1002 | reg = FDI_RX_CTL(pipe); |
1003 | val = I915_READ(reg); |
1003 | val = I915_READ(reg); |
1004 | cur_state = !!(val & FDI_RX_ENABLE); |
1004 | cur_state = !!(val & FDI_RX_ENABLE); |
1005 | WARN(cur_state != state, |
1005 | WARN(cur_state != state, |
1006 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1006 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1007 | state_string(state), state_string(cur_state)); |
1007 | state_string(state), state_string(cur_state)); |
1008 | } |
1008 | } |
1009 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1009 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1010 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1010 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1011 | 1011 | ||
1012 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1012 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1013 | enum pipe pipe) |
1013 | enum pipe pipe) |
1014 | { |
1014 | { |
1015 | int reg; |
1015 | int reg; |
1016 | u32 val; |
1016 | u32 val; |
1017 | 1017 | ||
1018 | /* ILK FDI PLL is always enabled */ |
1018 | /* ILK FDI PLL is always enabled */ |
1019 | if (dev_priv->info->gen == 5) |
1019 | if (dev_priv->info->gen == 5) |
1020 | return; |
1020 | return; |
1021 | 1021 | ||
1022 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1022 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1023 | if (HAS_DDI(dev_priv->dev)) |
1023 | if (HAS_DDI(dev_priv->dev)) |
1024 | return; |
1024 | return; |
1025 | 1025 | ||
1026 | reg = FDI_TX_CTL(pipe); |
1026 | reg = FDI_TX_CTL(pipe); |
1027 | val = I915_READ(reg); |
1027 | val = I915_READ(reg); |
1028 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1028 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1029 | } |
1029 | } |
1030 | 1030 | ||
1031 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1031 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe, bool state) |
1032 | enum pipe pipe, bool state) |
1033 | { |
1033 | { |
1034 | int reg; |
1034 | int reg; |
1035 | u32 val; |
1035 | u32 val; |
1036 | bool cur_state; |
1036 | bool cur_state; |
1037 | 1037 | ||
1038 | reg = FDI_RX_CTL(pipe); |
1038 | reg = FDI_RX_CTL(pipe); |
1039 | val = I915_READ(reg); |
1039 | val = I915_READ(reg); |
1040 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1040 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1041 | WARN(cur_state != state, |
1041 | WARN(cur_state != state, |
1042 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1042 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1043 | state_string(state), state_string(cur_state)); |
1043 | state_string(state), state_string(cur_state)); |
1044 | } |
1044 | } |
1045 | 1045 | ||
1046 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1046 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1047 | enum pipe pipe) |
1047 | enum pipe pipe) |
1048 | { |
1048 | { |
1049 | int pp_reg, lvds_reg; |
1049 | int pp_reg, lvds_reg; |
1050 | u32 val; |
1050 | u32 val; |
1051 | enum pipe panel_pipe = PIPE_A; |
1051 | enum pipe panel_pipe = PIPE_A; |
1052 | bool locked = true; |
1052 | bool locked = true; |
1053 | 1053 | ||
1054 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1054 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1055 | pp_reg = PCH_PP_CONTROL; |
1055 | pp_reg = PCH_PP_CONTROL; |
1056 | lvds_reg = PCH_LVDS; |
1056 | lvds_reg = PCH_LVDS; |
1057 | } else { |
1057 | } else { |
1058 | pp_reg = PP_CONTROL; |
1058 | pp_reg = PP_CONTROL; |
1059 | lvds_reg = LVDS; |
1059 | lvds_reg = LVDS; |
1060 | } |
1060 | } |
1061 | 1061 | ||
1062 | val = I915_READ(pp_reg); |
1062 | val = I915_READ(pp_reg); |
1063 | if (!(val & PANEL_POWER_ON) || |
1063 | if (!(val & PANEL_POWER_ON) || |
1064 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1064 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1065 | locked = false; |
1065 | locked = false; |
1066 | 1066 | ||
1067 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1067 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1068 | panel_pipe = PIPE_B; |
1068 | panel_pipe = PIPE_B; |
1069 | 1069 | ||
1070 | WARN(panel_pipe == pipe && locked, |
1070 | WARN(panel_pipe == pipe && locked, |
1071 | "panel assertion failure, pipe %c regs locked\n", |
1071 | "panel assertion failure, pipe %c regs locked\n", |
1072 | pipe_name(pipe)); |
1072 | pipe_name(pipe)); |
1073 | } |
1073 | } |
1074 | 1074 | ||
1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
1076 | enum pipe pipe, bool state) |
1076 | enum pipe pipe, bool state) |
1077 | { |
1077 | { |
1078 | int reg; |
1078 | int reg; |
1079 | u32 val; |
1079 | u32 val; |
1080 | bool cur_state; |
1080 | bool cur_state; |
1081 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1081 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1082 | pipe); |
1082 | pipe); |
1083 | 1083 | ||
1084 | /* if we need the pipe A quirk it must be always on */ |
1084 | /* if we need the pipe A quirk it must be always on */ |
1085 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1085 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1086 | state = true; |
1086 | state = true; |
1087 | 1087 | ||
1088 | if (!intel_display_power_enabled(dev_priv->dev, |
1088 | if (!intel_display_power_enabled(dev_priv->dev, |
1089 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1089 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1090 | cur_state = false; |
1090 | cur_state = false; |
1091 | } else { |
1091 | } else { |
1092 | reg = PIPECONF(cpu_transcoder); |
1092 | reg = PIPECONF(cpu_transcoder); |
1093 | val = I915_READ(reg); |
1093 | val = I915_READ(reg); |
1094 | cur_state = !!(val & PIPECONF_ENABLE); |
1094 | cur_state = !!(val & PIPECONF_ENABLE); |
1095 | } |
1095 | } |
1096 | 1096 | ||
1097 | WARN(cur_state != state, |
1097 | WARN(cur_state != state, |
1098 | "pipe %c assertion failure (expected %s, current %s)\n", |
1098 | "pipe %c assertion failure (expected %s, current %s)\n", |
1099 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1099 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1100 | } |
1100 | } |
1101 | 1101 | ||
1102 | static void assert_plane(struct drm_i915_private *dev_priv, |
1102 | static void assert_plane(struct drm_i915_private *dev_priv, |
1103 | enum plane plane, bool state) |
1103 | enum plane plane, bool state) |
1104 | { |
1104 | { |
1105 | int reg; |
1105 | int reg; |
1106 | u32 val; |
1106 | u32 val; |
1107 | bool cur_state; |
1107 | bool cur_state; |
1108 | 1108 | ||
1109 | reg = DSPCNTR(plane); |
1109 | reg = DSPCNTR(plane); |
1110 | val = I915_READ(reg); |
1110 | val = I915_READ(reg); |
1111 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1111 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1112 | WARN(cur_state != state, |
1112 | WARN(cur_state != state, |
1113 | "plane %c assertion failure (expected %s, current %s)\n", |
1113 | "plane %c assertion failure (expected %s, current %s)\n", |
1114 | plane_name(plane), state_string(state), state_string(cur_state)); |
1114 | plane_name(plane), state_string(state), state_string(cur_state)); |
1115 | } |
1115 | } |
1116 | 1116 | ||
1117 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1117 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1118 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1118 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1119 | 1119 | ||
1120 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1120 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1121 | enum pipe pipe) |
1121 | enum pipe pipe) |
1122 | { |
1122 | { |
1123 | struct drm_device *dev = dev_priv->dev; |
1123 | struct drm_device *dev = dev_priv->dev; |
1124 | int reg, i; |
1124 | int reg, i; |
1125 | u32 val; |
1125 | u32 val; |
1126 | int cur_pipe; |
1126 | int cur_pipe; |
1127 | 1127 | ||
1128 | /* Primary planes are fixed to pipes on gen4+ */ |
1128 | /* Primary planes are fixed to pipes on gen4+ */ |
1129 | if (INTEL_INFO(dev)->gen >= 4) { |
1129 | if (INTEL_INFO(dev)->gen >= 4) { |
1130 | reg = DSPCNTR(pipe); |
1130 | reg = DSPCNTR(pipe); |
1131 | val = I915_READ(reg); |
1131 | val = I915_READ(reg); |
1132 | WARN((val & DISPLAY_PLANE_ENABLE), |
1132 | WARN((val & DISPLAY_PLANE_ENABLE), |
1133 | "plane %c assertion failure, should be disabled but not\n", |
1133 | "plane %c assertion failure, should be disabled but not\n", |
1134 | plane_name(pipe)); |
1134 | plane_name(pipe)); |
1135 | return; |
1135 | return; |
1136 | } |
1136 | } |
1137 | 1137 | ||
1138 | /* Need to check both planes against the pipe */ |
1138 | /* Need to check both planes against the pipe */ |
1139 | for_each_pipe(i) { |
1139 | for_each_pipe(i) { |
1140 | reg = DSPCNTR(i); |
1140 | reg = DSPCNTR(i); |
1141 | val = I915_READ(reg); |
1141 | val = I915_READ(reg); |
1142 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1142 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1143 | DISPPLANE_SEL_PIPE_SHIFT; |
1143 | DISPPLANE_SEL_PIPE_SHIFT; |
1144 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1144 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1145 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1145 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1146 | plane_name(i), pipe_name(pipe)); |
1146 | plane_name(i), pipe_name(pipe)); |
1147 | } |
1147 | } |
1148 | } |
1148 | } |
1149 | 1149 | ||
1150 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1150 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1151 | enum pipe pipe) |
1151 | enum pipe pipe) |
1152 | { |
1152 | { |
1153 | struct drm_device *dev = dev_priv->dev; |
1153 | struct drm_device *dev = dev_priv->dev; |
1154 | int reg, i; |
1154 | int reg, i; |
1155 | u32 val; |
1155 | u32 val; |
1156 | 1156 | ||
1157 | if (IS_VALLEYVIEW(dev)) { |
1157 | if (IS_VALLEYVIEW(dev)) { |
1158 | for (i = 0; i < dev_priv->num_plane; i++) { |
1158 | for (i = 0; i < dev_priv->num_plane; i++) { |
1159 | reg = SPCNTR(pipe, i); |
1159 | reg = SPCNTR(pipe, i); |
1160 | val = I915_READ(reg); |
1160 | val = I915_READ(reg); |
1161 | WARN((val & SP_ENABLE), |
1161 | WARN((val & SP_ENABLE), |
1162 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1162 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1163 | sprite_name(pipe, i), pipe_name(pipe)); |
1163 | sprite_name(pipe, i), pipe_name(pipe)); |
1164 | } |
1164 | } |
1165 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1165 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1166 | reg = SPRCTL(pipe); |
1166 | reg = SPRCTL(pipe); |
1167 | val = I915_READ(reg); |
1167 | val = I915_READ(reg); |
1168 | WARN((val & SPRITE_ENABLE), |
1168 | WARN((val & SPRITE_ENABLE), |
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1170 | plane_name(pipe), pipe_name(pipe)); |
1170 | plane_name(pipe), pipe_name(pipe)); |
1171 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1171 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1172 | reg = DVSCNTR(pipe); |
1172 | reg = DVSCNTR(pipe); |
1173 | val = I915_READ(reg); |
1173 | val = I915_READ(reg); |
1174 | WARN((val & DVS_ENABLE), |
1174 | WARN((val & DVS_ENABLE), |
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1176 | plane_name(pipe), pipe_name(pipe)); |
1176 | plane_name(pipe), pipe_name(pipe)); |
1177 | } |
1177 | } |
1178 | } |
1178 | } |
1179 | 1179 | ||
1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1181 | { |
1181 | { |
1182 | u32 val; |
1182 | u32 val; |
1183 | bool enabled; |
1183 | bool enabled; |
1184 | 1184 | ||
1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1187 | return; |
1187 | return; |
1188 | } |
1188 | } |
1189 | 1189 | ||
1190 | val = I915_READ(PCH_DREF_CONTROL); |
1190 | val = I915_READ(PCH_DREF_CONTROL); |
1191 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1191 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1192 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1192 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1193 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1193 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1194 | } |
1194 | } |
1195 | 1195 | ||
1196 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1196 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1197 | enum pipe pipe) |
1197 | enum pipe pipe) |
1198 | { |
1198 | { |
1199 | int reg; |
1199 | int reg; |
1200 | u32 val; |
1200 | u32 val; |
1201 | bool enabled; |
1201 | bool enabled; |
1202 | 1202 | ||
1203 | reg = PCH_TRANSCONF(pipe); |
1203 | reg = PCH_TRANSCONF(pipe); |
1204 | val = I915_READ(reg); |
1204 | val = I915_READ(reg); |
1205 | enabled = !!(val & TRANS_ENABLE); |
1205 | enabled = !!(val & TRANS_ENABLE); |
1206 | WARN(enabled, |
1206 | WARN(enabled, |
1207 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1207 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1208 | pipe_name(pipe)); |
1208 | pipe_name(pipe)); |
1209 | } |
1209 | } |
1210 | 1210 | ||
1211 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1211 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1212 | enum pipe pipe, u32 port_sel, u32 val) |
1212 | enum pipe pipe, u32 port_sel, u32 val) |
1213 | { |
1213 | { |
1214 | if ((val & DP_PORT_EN) == 0) |
1214 | if ((val & DP_PORT_EN) == 0) |
1215 | return false; |
1215 | return false; |
1216 | 1216 | ||
1217 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1217 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1218 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1218 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1219 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1219 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1220 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1220 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1221 | return false; |
1221 | return false; |
1222 | } else { |
1222 | } else { |
1223 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1223 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1224 | return false; |
1224 | return false; |
1225 | } |
1225 | } |
1226 | return true; |
1226 | return true; |
1227 | } |
1227 | } |
1228 | 1228 | ||
1229 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1229 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1230 | enum pipe pipe, u32 val) |
1230 | enum pipe pipe, u32 val) |
1231 | { |
1231 | { |
1232 | if ((val & SDVO_ENABLE) == 0) |
1232 | if ((val & SDVO_ENABLE) == 0) |
1233 | return false; |
1233 | return false; |
1234 | 1234 | ||
1235 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1235 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1236 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1236 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1237 | return false; |
1237 | return false; |
1238 | } else { |
1238 | } else { |
1239 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1239 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1240 | return false; |
1240 | return false; |
1241 | } |
1241 | } |
1242 | return true; |
1242 | return true; |
1243 | } |
1243 | } |
1244 | 1244 | ||
1245 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1245 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 val) |
1246 | enum pipe pipe, u32 val) |
1247 | { |
1247 | { |
1248 | if ((val & LVDS_PORT_EN) == 0) |
1248 | if ((val & LVDS_PORT_EN) == 0) |
1249 | return false; |
1249 | return false; |
1250 | 1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1252 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1252 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1253 | return false; |
1253 | return false; |
1254 | } else { |
1254 | } else { |
1255 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1255 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1256 | return false; |
1256 | return false; |
1257 | } |
1257 | } |
1258 | return true; |
1258 | return true; |
1259 | } |
1259 | } |
1260 | 1260 | ||
1261 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1261 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1262 | enum pipe pipe, u32 val) |
1262 | enum pipe pipe, u32 val) |
1263 | { |
1263 | { |
1264 | if ((val & ADPA_DAC_ENABLE) == 0) |
1264 | if ((val & ADPA_DAC_ENABLE) == 0) |
1265 | return false; |
1265 | return false; |
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1267 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1267 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1268 | return false; |
1268 | return false; |
1269 | } else { |
1269 | } else { |
1270 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1270 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1271 | return false; |
1271 | return false; |
1272 | } |
1272 | } |
1273 | return true; |
1273 | return true; |
1274 | } |
1274 | } |
1275 | 1275 | ||
1276 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1276 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1277 | enum pipe pipe, int reg, u32 port_sel) |
1277 | enum pipe pipe, int reg, u32 port_sel) |
1278 | { |
1278 | { |
1279 | u32 val = I915_READ(reg); |
1279 | u32 val = I915_READ(reg); |
1280 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1280 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1281 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1281 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1282 | reg, pipe_name(pipe)); |
1282 | reg, pipe_name(pipe)); |
1283 | 1283 | ||
1284 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1284 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1285 | && (val & DP_PIPEB_SELECT), |
1285 | && (val & DP_PIPEB_SELECT), |
1286 | "IBX PCH dp port still using transcoder B\n"); |
1286 | "IBX PCH dp port still using transcoder B\n"); |
1287 | } |
1287 | } |
1288 | 1288 | ||
1289 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1289 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1290 | enum pipe pipe, int reg) |
1290 | enum pipe pipe, int reg) |
1291 | { |
1291 | { |
1292 | u32 val = I915_READ(reg); |
1292 | u32 val = I915_READ(reg); |
1293 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1293 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1294 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1294 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1295 | reg, pipe_name(pipe)); |
1295 | reg, pipe_name(pipe)); |
1296 | 1296 | ||
1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1298 | && (val & SDVO_PIPE_B_SELECT), |
1298 | && (val & SDVO_PIPE_B_SELECT), |
1299 | "IBX PCH hdmi port still using transcoder B\n"); |
1299 | "IBX PCH hdmi port still using transcoder B\n"); |
1300 | } |
1300 | } |
1301 | 1301 | ||
1302 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1302 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1303 | enum pipe pipe) |
1303 | enum pipe pipe) |
1304 | { |
1304 | { |
1305 | int reg; |
1305 | int reg; |
1306 | u32 val; |
1306 | u32 val; |
1307 | 1307 | ||
1308 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1308 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1309 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1309 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1310 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1310 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1311 | 1311 | ||
1312 | reg = PCH_ADPA; |
1312 | reg = PCH_ADPA; |
1313 | val = I915_READ(reg); |
1313 | val = I915_READ(reg); |
1314 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1314 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1315 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1315 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1316 | pipe_name(pipe)); |
1316 | pipe_name(pipe)); |
1317 | 1317 | ||
1318 | reg = PCH_LVDS; |
1318 | reg = PCH_LVDS; |
1319 | val = I915_READ(reg); |
1319 | val = I915_READ(reg); |
1320 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1320 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1321 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1321 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1322 | pipe_name(pipe)); |
1322 | pipe_name(pipe)); |
1323 | 1323 | ||
1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1327 | } |
1327 | } |
1328 | 1328 | ||
1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1330 | { |
1330 | { |
1331 | struct drm_device *dev = crtc->base.dev; |
1331 | struct drm_device *dev = crtc->base.dev; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
1333 | int reg = DPLL(crtc->pipe); |
1333 | int reg = DPLL(crtc->pipe); |
1334 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1334 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1335 | 1335 | ||
1336 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1336 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1337 | 1337 | ||
1338 | /* No really, not for ILK+ */ |
1338 | /* No really, not for ILK+ */ |
1339 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1339 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1340 | 1340 | ||
1341 | /* PLL is protected by panel, make sure we can write it */ |
1341 | /* PLL is protected by panel, make sure we can write it */ |
1342 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1342 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1343 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1343 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1344 | 1344 | ||
1345 | I915_WRITE(reg, dpll); |
1345 | I915_WRITE(reg, dpll); |
1346 | POSTING_READ(reg); |
1346 | POSTING_READ(reg); |
1347 | udelay(150); |
1347 | udelay(150); |
1348 | 1348 | ||
1349 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1349 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1350 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1350 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1351 | 1351 | ||
1352 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1352 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1353 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1353 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1354 | 1354 | ||
1355 | /* We do this three times for luck */ |
1355 | /* We do this three times for luck */ |
1356 | I915_WRITE(reg, dpll); |
1356 | I915_WRITE(reg, dpll); |
1357 | POSTING_READ(reg); |
1357 | POSTING_READ(reg); |
1358 | udelay(150); /* wait for warmup */ |
1358 | udelay(150); /* wait for warmup */ |
1359 | I915_WRITE(reg, dpll); |
1359 | I915_WRITE(reg, dpll); |
1360 | POSTING_READ(reg); |
1360 | POSTING_READ(reg); |
1361 | udelay(150); /* wait for warmup */ |
1361 | udelay(150); /* wait for warmup */ |
1362 | I915_WRITE(reg, dpll); |
1362 | I915_WRITE(reg, dpll); |
1363 | POSTING_READ(reg); |
1363 | POSTING_READ(reg); |
1364 | udelay(150); /* wait for warmup */ |
1364 | udelay(150); /* wait for warmup */ |
1365 | } |
1365 | } |
1366 | 1366 | ||
1367 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1367 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1368 | { |
1368 | { |
1369 | struct drm_device *dev = crtc->base.dev; |
1369 | struct drm_device *dev = crtc->base.dev; |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1371 | int reg = DPLL(crtc->pipe); |
1371 | int reg = DPLL(crtc->pipe); |
1372 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1372 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1373 | 1373 | ||
1374 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1374 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1375 | 1375 | ||
1376 | /* No really, not for ILK+ */ |
1376 | /* No really, not for ILK+ */ |
1377 | BUG_ON(dev_priv->info->gen >= 5); |
1377 | BUG_ON(dev_priv->info->gen >= 5); |
1378 | 1378 | ||
1379 | /* PLL is protected by panel, make sure we can write it */ |
1379 | /* PLL is protected by panel, make sure we can write it */ |
1380 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1380 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1381 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1381 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1382 | 1382 | ||
1383 | I915_WRITE(reg, dpll); |
1383 | I915_WRITE(reg, dpll); |
1384 | 1384 | ||
1385 | /* Wait for the clocks to stabilize. */ |
1385 | /* Wait for the clocks to stabilize. */ |
1386 | POSTING_READ(reg); |
1386 | POSTING_READ(reg); |
1387 | udelay(150); |
1387 | udelay(150); |
1388 | 1388 | ||
1389 | if (INTEL_INFO(dev)->gen >= 4) { |
1389 | if (INTEL_INFO(dev)->gen >= 4) { |
1390 | I915_WRITE(DPLL_MD(crtc->pipe), |
1390 | I915_WRITE(DPLL_MD(crtc->pipe), |
1391 | crtc->config.dpll_hw_state.dpll_md); |
1391 | crtc->config.dpll_hw_state.dpll_md); |
1392 | } else { |
1392 | } else { |
1393 | /* The pixel multiplier can only be updated once the |
1393 | /* The pixel multiplier can only be updated once the |
1394 | * DPLL is enabled and the clocks are stable. |
1394 | * DPLL is enabled and the clocks are stable. |
1395 | * |
1395 | * |
1396 | * So write it again. |
1396 | * So write it again. |
1397 | */ |
1397 | */ |
1398 | I915_WRITE(reg, dpll); |
1398 | I915_WRITE(reg, dpll); |
1399 | } |
1399 | } |
1400 | 1400 | ||
1401 | /* We do this three times for luck */ |
1401 | /* We do this three times for luck */ |
1402 | I915_WRITE(reg, dpll); |
1402 | I915_WRITE(reg, dpll); |
1403 | POSTING_READ(reg); |
1403 | POSTING_READ(reg); |
1404 | udelay(150); /* wait for warmup */ |
1404 | udelay(150); /* wait for warmup */ |
1405 | I915_WRITE(reg, dpll); |
1405 | I915_WRITE(reg, dpll); |
1406 | POSTING_READ(reg); |
1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ |
1407 | udelay(150); /* wait for warmup */ |
1408 | I915_WRITE(reg, dpll); |
1408 | I915_WRITE(reg, dpll); |
1409 | POSTING_READ(reg); |
1409 | POSTING_READ(reg); |
1410 | udelay(150); /* wait for warmup */ |
1410 | udelay(150); /* wait for warmup */ |
1411 | } |
1411 | } |
1412 | 1412 | ||
1413 | /** |
1413 | /** |
1414 | * i9xx_disable_pll - disable a PLL |
1414 | * i9xx_disable_pll - disable a PLL |
1415 | * @dev_priv: i915 private structure |
1415 | * @dev_priv: i915 private structure |
1416 | * @pipe: pipe PLL to disable |
1416 | * @pipe: pipe PLL to disable |
1417 | * |
1417 | * |
1418 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1418 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1419 | * |
1419 | * |
1420 | * Note! This is for pre-ILK only. |
1420 | * Note! This is for pre-ILK only. |
1421 | */ |
1421 | */ |
1422 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1422 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1423 | { |
1423 | { |
1424 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1424 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1425 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1425 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1426 | return; |
1426 | return; |
1427 | 1427 | ||
1428 | /* Make sure the pipe isn't still relying on us */ |
1428 | /* Make sure the pipe isn't still relying on us */ |
1429 | assert_pipe_disabled(dev_priv, pipe); |
1429 | assert_pipe_disabled(dev_priv, pipe); |
1430 | 1430 | ||
1431 | I915_WRITE(DPLL(pipe), 0); |
1431 | I915_WRITE(DPLL(pipe), 0); |
1432 | POSTING_READ(DPLL(pipe)); |
1432 | POSTING_READ(DPLL(pipe)); |
1433 | } |
1433 | } |
- | 1434 | ||
- | 1435 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
|
- | 1436 | { |
|
- | 1437 | u32 val = 0; |
|
- | 1438 | ||
- | 1439 | /* Make sure the pipe isn't still relying on us */ |
|
- | 1440 | assert_pipe_disabled(dev_priv, pipe); |
|
- | 1441 | ||
- | 1442 | /* Leave integrated clock source enabled */ |
|
- | 1443 | if (pipe == PIPE_B) |
|
- | 1444 | val = DPLL_INTEGRATED_CRI_CLK_VLV; |
|
- | 1445 | I915_WRITE(DPLL(pipe), val); |
|
- | 1446 | POSTING_READ(DPLL(pipe)); |
|
- | 1447 | } |
|
1434 | 1448 | ||
1435 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1449 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1436 | { |
1450 | { |
1437 | u32 port_mask; |
1451 | u32 port_mask; |
1438 | 1452 | ||
1439 | if (!port) |
1453 | if (!port) |
1440 | port_mask = DPLL_PORTB_READY_MASK; |
1454 | port_mask = DPLL_PORTB_READY_MASK; |
1441 | else |
1455 | else |
1442 | port_mask = DPLL_PORTC_READY_MASK; |
1456 | port_mask = DPLL_PORTC_READY_MASK; |
1443 | 1457 | ||
1444 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1458 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1445 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1459 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1446 | 'B' + port, I915_READ(DPLL(0))); |
1460 | 'B' + port, I915_READ(DPLL(0))); |
1447 | } |
1461 | } |
1448 | 1462 | ||
1449 | /** |
1463 | /** |
1450 | * ironlake_enable_shared_dpll - enable PCH PLL |
1464 | * ironlake_enable_shared_dpll - enable PCH PLL |
1451 | * @dev_priv: i915 private structure |
1465 | * @dev_priv: i915 private structure |
1452 | * @pipe: pipe PLL to enable |
1466 | * @pipe: pipe PLL to enable |
1453 | * |
1467 | * |
1454 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1468 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1455 | * drives the transcoder clock. |
1469 | * drives the transcoder clock. |
1456 | */ |
1470 | */ |
1457 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1471 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1458 | { |
1472 | { |
1459 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1473 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1460 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1474 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1461 | 1475 | ||
1462 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1476 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1463 | BUG_ON(dev_priv->info->gen < 5); |
1477 | BUG_ON(dev_priv->info->gen < 5); |
1464 | if (WARN_ON(pll == NULL)) |
1478 | if (WARN_ON(pll == NULL)) |
1465 | return; |
1479 | return; |
1466 | 1480 | ||
1467 | if (WARN_ON(pll->refcount == 0)) |
1481 | if (WARN_ON(pll->refcount == 0)) |
1468 | return; |
1482 | return; |
1469 | 1483 | ||
1470 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1484 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1471 | pll->name, pll->active, pll->on, |
1485 | pll->name, pll->active, pll->on, |
1472 | crtc->base.base.id); |
1486 | crtc->base.base.id); |
1473 | 1487 | ||
1474 | if (pll->active++) { |
1488 | if (pll->active++) { |
1475 | WARN_ON(!pll->on); |
1489 | WARN_ON(!pll->on); |
1476 | assert_shared_dpll_enabled(dev_priv, pll); |
1490 | assert_shared_dpll_enabled(dev_priv, pll); |
1477 | return; |
1491 | return; |
1478 | } |
1492 | } |
1479 | WARN_ON(pll->on); |
1493 | WARN_ON(pll->on); |
1480 | 1494 | ||
1481 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1495 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1482 | pll->enable(dev_priv, pll); |
1496 | pll->enable(dev_priv, pll); |
1483 | pll->on = true; |
1497 | pll->on = true; |
1484 | } |
1498 | } |
1485 | 1499 | ||
1486 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1500 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1487 | { |
1501 | { |
1488 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1502 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1489 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1503 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1490 | 1504 | ||
1491 | /* PCH only available on ILK+ */ |
1505 | /* PCH only available on ILK+ */ |
1492 | BUG_ON(dev_priv->info->gen < 5); |
1506 | BUG_ON(dev_priv->info->gen < 5); |
1493 | if (WARN_ON(pll == NULL)) |
1507 | if (WARN_ON(pll == NULL)) |
1494 | return; |
1508 | return; |
1495 | 1509 | ||
1496 | if (WARN_ON(pll->refcount == 0)) |
1510 | if (WARN_ON(pll->refcount == 0)) |
1497 | return; |
1511 | return; |
1498 | 1512 | ||
1499 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1513 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1500 | pll->name, pll->active, pll->on, |
1514 | pll->name, pll->active, pll->on, |
1501 | crtc->base.base.id); |
1515 | crtc->base.base.id); |
1502 | 1516 | ||
1503 | if (WARN_ON(pll->active == 0)) { |
1517 | if (WARN_ON(pll->active == 0)) { |
1504 | assert_shared_dpll_disabled(dev_priv, pll); |
1518 | assert_shared_dpll_disabled(dev_priv, pll); |
1505 | return; |
1519 | return; |
1506 | } |
1520 | } |
1507 | 1521 | ||
1508 | assert_shared_dpll_enabled(dev_priv, pll); |
1522 | assert_shared_dpll_enabled(dev_priv, pll); |
1509 | WARN_ON(!pll->on); |
1523 | WARN_ON(!pll->on); |
1510 | if (--pll->active) |
1524 | if (--pll->active) |
1511 | return; |
1525 | return; |
1512 | 1526 | ||
1513 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1527 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1514 | pll->disable(dev_priv, pll); |
1528 | pll->disable(dev_priv, pll); |
1515 | pll->on = false; |
1529 | pll->on = false; |
1516 | } |
1530 | } |
1517 | 1531 | ||
1518 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1532 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1519 | enum pipe pipe) |
1533 | enum pipe pipe) |
1520 | { |
1534 | { |
1521 | struct drm_device *dev = dev_priv->dev; |
1535 | struct drm_device *dev = dev_priv->dev; |
1522 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1536 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1524 | uint32_t reg, val, pipeconf_val; |
1538 | uint32_t reg, val, pipeconf_val; |
1525 | 1539 | ||
1526 | /* PCH only available on ILK+ */ |
1540 | /* PCH only available on ILK+ */ |
1527 | BUG_ON(dev_priv->info->gen < 5); |
1541 | BUG_ON(dev_priv->info->gen < 5); |
1528 | 1542 | ||
1529 | /* Make sure PCH DPLL is enabled */ |
1543 | /* Make sure PCH DPLL is enabled */ |
1530 | assert_shared_dpll_enabled(dev_priv, |
1544 | assert_shared_dpll_enabled(dev_priv, |
1531 | intel_crtc_to_shared_dpll(intel_crtc)); |
1545 | intel_crtc_to_shared_dpll(intel_crtc)); |
1532 | 1546 | ||
1533 | /* FDI must be feeding us bits for PCH ports */ |
1547 | /* FDI must be feeding us bits for PCH ports */ |
1534 | assert_fdi_tx_enabled(dev_priv, pipe); |
1548 | assert_fdi_tx_enabled(dev_priv, pipe); |
1535 | assert_fdi_rx_enabled(dev_priv, pipe); |
1549 | assert_fdi_rx_enabled(dev_priv, pipe); |
1536 | 1550 | ||
1537 | if (HAS_PCH_CPT(dev)) { |
1551 | if (HAS_PCH_CPT(dev)) { |
1538 | /* Workaround: Set the timing override bit before enabling the |
1552 | /* Workaround: Set the timing override bit before enabling the |
1539 | * pch transcoder. */ |
1553 | * pch transcoder. */ |
1540 | reg = TRANS_CHICKEN2(pipe); |
1554 | reg = TRANS_CHICKEN2(pipe); |
1541 | val = I915_READ(reg); |
1555 | val = I915_READ(reg); |
1542 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1556 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1543 | I915_WRITE(reg, val); |
1557 | I915_WRITE(reg, val); |
1544 | } |
1558 | } |
1545 | 1559 | ||
1546 | reg = PCH_TRANSCONF(pipe); |
1560 | reg = PCH_TRANSCONF(pipe); |
1547 | val = I915_READ(reg); |
1561 | val = I915_READ(reg); |
1548 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1562 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1549 | 1563 | ||
1550 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1564 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1551 | /* |
1565 | /* |
1552 | * make the BPC in transcoder be consistent with |
1566 | * make the BPC in transcoder be consistent with |
1553 | * that in pipeconf reg. |
1567 | * that in pipeconf reg. |
1554 | */ |
1568 | */ |
1555 | val &= ~PIPECONF_BPC_MASK; |
1569 | val &= ~PIPECONF_BPC_MASK; |
1556 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1570 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1557 | } |
1571 | } |
1558 | 1572 | ||
1559 | val &= ~TRANS_INTERLACE_MASK; |
1573 | val &= ~TRANS_INTERLACE_MASK; |
1560 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1574 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1561 | if (HAS_PCH_IBX(dev_priv->dev) && |
1575 | if (HAS_PCH_IBX(dev_priv->dev) && |
1562 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1576 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1563 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1577 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1564 | else |
1578 | else |
1565 | val |= TRANS_INTERLACED; |
1579 | val |= TRANS_INTERLACED; |
1566 | else |
1580 | else |
1567 | val |= TRANS_PROGRESSIVE; |
1581 | val |= TRANS_PROGRESSIVE; |
1568 | 1582 | ||
1569 | I915_WRITE(reg, val | TRANS_ENABLE); |
1583 | I915_WRITE(reg, val | TRANS_ENABLE); |
1570 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1584 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1571 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1585 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1572 | } |
1586 | } |
1573 | 1587 | ||
1574 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1588 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1575 | enum transcoder cpu_transcoder) |
1589 | enum transcoder cpu_transcoder) |
1576 | { |
1590 | { |
1577 | u32 val, pipeconf_val; |
1591 | u32 val, pipeconf_val; |
1578 | 1592 | ||
1579 | /* PCH only available on ILK+ */ |
1593 | /* PCH only available on ILK+ */ |
1580 | BUG_ON(dev_priv->info->gen < 5); |
1594 | BUG_ON(dev_priv->info->gen < 5); |
1581 | 1595 | ||
1582 | /* FDI must be feeding us bits for PCH ports */ |
1596 | /* FDI must be feeding us bits for PCH ports */ |
1583 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1597 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1584 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1598 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1585 | 1599 | ||
1586 | /* Workaround: set timing override bit. */ |
1600 | /* Workaround: set timing override bit. */ |
1587 | val = I915_READ(_TRANSA_CHICKEN2); |
1601 | val = I915_READ(_TRANSA_CHICKEN2); |
1588 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1602 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1589 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1603 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1590 | 1604 | ||
1591 | val = TRANS_ENABLE; |
1605 | val = TRANS_ENABLE; |
1592 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1606 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1593 | 1607 | ||
1594 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1608 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1595 | PIPECONF_INTERLACED_ILK) |
1609 | PIPECONF_INTERLACED_ILK) |
1596 | val |= TRANS_INTERLACED; |
1610 | val |= TRANS_INTERLACED; |
1597 | else |
1611 | else |
1598 | val |= TRANS_PROGRESSIVE; |
1612 | val |= TRANS_PROGRESSIVE; |
1599 | 1613 | ||
1600 | I915_WRITE(LPT_TRANSCONF, val); |
1614 | I915_WRITE(LPT_TRANSCONF, val); |
1601 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1615 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1602 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1616 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1603 | } |
1617 | } |
1604 | 1618 | ||
1605 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1619 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1606 | enum pipe pipe) |
1620 | enum pipe pipe) |
1607 | { |
1621 | { |
1608 | struct drm_device *dev = dev_priv->dev; |
1622 | struct drm_device *dev = dev_priv->dev; |
1609 | uint32_t reg, val; |
1623 | uint32_t reg, val; |
1610 | 1624 | ||
1611 | /* FDI relies on the transcoder */ |
1625 | /* FDI relies on the transcoder */ |
1612 | assert_fdi_tx_disabled(dev_priv, pipe); |
1626 | assert_fdi_tx_disabled(dev_priv, pipe); |
1613 | assert_fdi_rx_disabled(dev_priv, pipe); |
1627 | assert_fdi_rx_disabled(dev_priv, pipe); |
1614 | 1628 | ||
1615 | /* Ports must be off as well */ |
1629 | /* Ports must be off as well */ |
1616 | assert_pch_ports_disabled(dev_priv, pipe); |
1630 | assert_pch_ports_disabled(dev_priv, pipe); |
1617 | 1631 | ||
1618 | reg = PCH_TRANSCONF(pipe); |
1632 | reg = PCH_TRANSCONF(pipe); |
1619 | val = I915_READ(reg); |
1633 | val = I915_READ(reg); |
1620 | val &= ~TRANS_ENABLE; |
1634 | val &= ~TRANS_ENABLE; |
1621 | I915_WRITE(reg, val); |
1635 | I915_WRITE(reg, val); |
1622 | /* wait for PCH transcoder off, transcoder state */ |
1636 | /* wait for PCH transcoder off, transcoder state */ |
1623 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1637 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1624 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1638 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1625 | 1639 | ||
1626 | if (!HAS_PCH_IBX(dev)) { |
1640 | if (!HAS_PCH_IBX(dev)) { |
1627 | /* Workaround: Clear the timing override chicken bit again. */ |
1641 | /* Workaround: Clear the timing override chicken bit again. */ |
1628 | reg = TRANS_CHICKEN2(pipe); |
1642 | reg = TRANS_CHICKEN2(pipe); |
1629 | val = I915_READ(reg); |
1643 | val = I915_READ(reg); |
1630 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1644 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1631 | I915_WRITE(reg, val); |
1645 | I915_WRITE(reg, val); |
1632 | } |
1646 | } |
1633 | } |
1647 | } |
1634 | 1648 | ||
1635 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1649 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1636 | { |
1650 | { |
1637 | u32 val; |
1651 | u32 val; |
1638 | 1652 | ||
1639 | val = I915_READ(LPT_TRANSCONF); |
1653 | val = I915_READ(LPT_TRANSCONF); |
1640 | val &= ~TRANS_ENABLE; |
1654 | val &= ~TRANS_ENABLE; |
1641 | I915_WRITE(LPT_TRANSCONF, val); |
1655 | I915_WRITE(LPT_TRANSCONF, val); |
1642 | /* wait for PCH transcoder off, transcoder state */ |
1656 | /* wait for PCH transcoder off, transcoder state */ |
1643 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1657 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1644 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1658 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1645 | 1659 | ||
1646 | /* Workaround: clear timing override bit. */ |
1660 | /* Workaround: clear timing override bit. */ |
1647 | val = I915_READ(_TRANSA_CHICKEN2); |
1661 | val = I915_READ(_TRANSA_CHICKEN2); |
1648 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1662 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1649 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1663 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1650 | } |
1664 | } |
1651 | 1665 | ||
1652 | /** |
1666 | /** |
1653 | * intel_enable_pipe - enable a pipe, asserting requirements |
1667 | * intel_enable_pipe - enable a pipe, asserting requirements |
1654 | * @dev_priv: i915 private structure |
1668 | * @dev_priv: i915 private structure |
1655 | * @pipe: pipe to enable |
1669 | * @pipe: pipe to enable |
1656 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1670 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1657 | * |
1671 | * |
1658 | * Enable @pipe, making sure that various hardware specific requirements |
1672 | * Enable @pipe, making sure that various hardware specific requirements |
1659 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1673 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1660 | * |
1674 | * |
1661 | * @pipe should be %PIPE_A or %PIPE_B. |
1675 | * @pipe should be %PIPE_A or %PIPE_B. |
1662 | * |
1676 | * |
1663 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1677 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1664 | * returning. |
1678 | * returning. |
1665 | */ |
1679 | */ |
1666 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1680 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1667 | bool pch_port) |
1681 | bool pch_port) |
1668 | { |
1682 | { |
1669 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1683 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1670 | pipe); |
1684 | pipe); |
1671 | enum pipe pch_transcoder; |
1685 | enum pipe pch_transcoder; |
1672 | int reg; |
1686 | int reg; |
1673 | u32 val; |
1687 | u32 val; |
1674 | 1688 | ||
1675 | assert_planes_disabled(dev_priv, pipe); |
1689 | assert_planes_disabled(dev_priv, pipe); |
1676 | assert_sprites_disabled(dev_priv, pipe); |
1690 | assert_sprites_disabled(dev_priv, pipe); |
1677 | 1691 | ||
1678 | if (HAS_PCH_LPT(dev_priv->dev)) |
1692 | if (HAS_PCH_LPT(dev_priv->dev)) |
1679 | pch_transcoder = TRANSCODER_A; |
1693 | pch_transcoder = TRANSCODER_A; |
1680 | else |
1694 | else |
1681 | pch_transcoder = pipe; |
1695 | pch_transcoder = pipe; |
1682 | 1696 | ||
1683 | /* |
1697 | /* |
1684 | * A pipe without a PLL won't actually be able to drive bits from |
1698 | * A pipe without a PLL won't actually be able to drive bits from |
1685 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1699 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1686 | * need the check. |
1700 | * need the check. |
1687 | */ |
1701 | */ |
1688 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1702 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1689 | assert_pll_enabled(dev_priv, pipe); |
1703 | assert_pll_enabled(dev_priv, pipe); |
1690 | else { |
1704 | else { |
1691 | if (pch_port) { |
1705 | if (pch_port) { |
1692 | /* if driving the PCH, we need FDI enabled */ |
1706 | /* if driving the PCH, we need FDI enabled */ |
1693 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1707 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1694 | assert_fdi_tx_pll_enabled(dev_priv, |
1708 | assert_fdi_tx_pll_enabled(dev_priv, |
1695 | (enum pipe) cpu_transcoder); |
1709 | (enum pipe) cpu_transcoder); |
1696 | } |
1710 | } |
1697 | /* FIXME: assert CPU port conditions for SNB+ */ |
1711 | /* FIXME: assert CPU port conditions for SNB+ */ |
1698 | } |
1712 | } |
1699 | 1713 | ||
1700 | reg = PIPECONF(cpu_transcoder); |
1714 | reg = PIPECONF(cpu_transcoder); |
1701 | val = I915_READ(reg); |
1715 | val = I915_READ(reg); |
1702 | if (val & PIPECONF_ENABLE) |
1716 | if (val & PIPECONF_ENABLE) |
1703 | return; |
1717 | return; |
1704 | 1718 | ||
1705 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1719 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1706 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1720 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1707 | } |
1721 | } |
1708 | 1722 | ||
1709 | /** |
1723 | /** |
1710 | * intel_disable_pipe - disable a pipe, asserting requirements |
1724 | * intel_disable_pipe - disable a pipe, asserting requirements |
1711 | * @dev_priv: i915 private structure |
1725 | * @dev_priv: i915 private structure |
1712 | * @pipe: pipe to disable |
1726 | * @pipe: pipe to disable |
1713 | * |
1727 | * |
1714 | * Disable @pipe, making sure that various hardware specific requirements |
1728 | * Disable @pipe, making sure that various hardware specific requirements |
1715 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1729 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1716 | * |
1730 | * |
1717 | * @pipe should be %PIPE_A or %PIPE_B. |
1731 | * @pipe should be %PIPE_A or %PIPE_B. |
1718 | * |
1732 | * |
1719 | * Will wait until the pipe has shut down before returning. |
1733 | * Will wait until the pipe has shut down before returning. |
1720 | */ |
1734 | */ |
1721 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1735 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1722 | enum pipe pipe) |
1736 | enum pipe pipe) |
1723 | { |
1737 | { |
1724 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1738 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1725 | pipe); |
1739 | pipe); |
1726 | int reg; |
1740 | int reg; |
1727 | u32 val; |
1741 | u32 val; |
1728 | 1742 | ||
1729 | /* |
1743 | /* |
1730 | * Make sure planes won't keep trying to pump pixels to us, |
1744 | * Make sure planes won't keep trying to pump pixels to us, |
1731 | * or we might hang the display. |
1745 | * or we might hang the display. |
1732 | */ |
1746 | */ |
1733 | assert_planes_disabled(dev_priv, pipe); |
1747 | assert_planes_disabled(dev_priv, pipe); |
1734 | assert_sprites_disabled(dev_priv, pipe); |
1748 | assert_sprites_disabled(dev_priv, pipe); |
1735 | 1749 | ||
1736 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1750 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1737 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1751 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1738 | return; |
1752 | return; |
1739 | 1753 | ||
1740 | reg = PIPECONF(cpu_transcoder); |
1754 | reg = PIPECONF(cpu_transcoder); |
1741 | val = I915_READ(reg); |
1755 | val = I915_READ(reg); |
1742 | if ((val & PIPECONF_ENABLE) == 0) |
1756 | if ((val & PIPECONF_ENABLE) == 0) |
1743 | return; |
1757 | return; |
1744 | 1758 | ||
1745 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1759 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1746 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1760 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1747 | } |
1761 | } |
1748 | 1762 | ||
1749 | /* |
1763 | /* |
1750 | * Plane regs are double buffered, going from enabled->disabled needs a |
1764 | * Plane regs are double buffered, going from enabled->disabled needs a |
1751 | * trigger in order to latch. The display address reg provides this. |
1765 | * trigger in order to latch. The display address reg provides this. |
1752 | */ |
1766 | */ |
1753 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1767 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1754 | enum plane plane) |
1768 | enum plane plane) |
1755 | { |
1769 | { |
1756 | if (dev_priv->info->gen >= 4) |
1770 | if (dev_priv->info->gen >= 4) |
1757 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1771 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1758 | else |
1772 | else |
1759 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1773 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1760 | } |
1774 | } |
1761 | 1775 | ||
1762 | /** |
1776 | /** |
1763 | * intel_enable_plane - enable a display plane on a given pipe |
1777 | * intel_enable_plane - enable a display plane on a given pipe |
1764 | * @dev_priv: i915 private structure |
1778 | * @dev_priv: i915 private structure |
1765 | * @plane: plane to enable |
1779 | * @plane: plane to enable |
1766 | * @pipe: pipe being fed |
1780 | * @pipe: pipe being fed |
1767 | * |
1781 | * |
1768 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1782 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1769 | */ |
1783 | */ |
1770 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1784 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1771 | enum plane plane, enum pipe pipe) |
1785 | enum plane plane, enum pipe pipe) |
1772 | { |
1786 | { |
1773 | int reg; |
1787 | int reg; |
1774 | u32 val; |
1788 | u32 val; |
1775 | 1789 | ||
1776 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1790 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1777 | assert_pipe_enabled(dev_priv, pipe); |
1791 | assert_pipe_enabled(dev_priv, pipe); |
1778 | 1792 | ||
1779 | reg = DSPCNTR(plane); |
1793 | reg = DSPCNTR(plane); |
1780 | val = I915_READ(reg); |
1794 | val = I915_READ(reg); |
1781 | if (val & DISPLAY_PLANE_ENABLE) |
1795 | if (val & DISPLAY_PLANE_ENABLE) |
1782 | return; |
1796 | return; |
1783 | 1797 | ||
1784 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1798 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1785 | intel_flush_display_plane(dev_priv, plane); |
1799 | intel_flush_display_plane(dev_priv, plane); |
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1800 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1787 | } |
1801 | } |
1788 | 1802 | ||
1789 | /** |
1803 | /** |
1790 | * intel_disable_plane - disable a display plane |
1804 | * intel_disable_plane - disable a display plane |
1791 | * @dev_priv: i915 private structure |
1805 | * @dev_priv: i915 private structure |
1792 | * @plane: plane to disable |
1806 | * @plane: plane to disable |
1793 | * @pipe: pipe consuming the data |
1807 | * @pipe: pipe consuming the data |
1794 | * |
1808 | * |
1795 | * Disable @plane; should be an independent operation. |
1809 | * Disable @plane; should be an independent operation. |
1796 | */ |
1810 | */ |
1797 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1811 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1798 | enum plane plane, enum pipe pipe) |
1812 | enum plane plane, enum pipe pipe) |
1799 | { |
1813 | { |
1800 | int reg; |
1814 | int reg; |
1801 | u32 val; |
1815 | u32 val; |
1802 | 1816 | ||
1803 | reg = DSPCNTR(plane); |
1817 | reg = DSPCNTR(plane); |
1804 | val = I915_READ(reg); |
1818 | val = I915_READ(reg); |
1805 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1819 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1806 | return; |
1820 | return; |
1807 | 1821 | ||
1808 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1822 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1809 | intel_flush_display_plane(dev_priv, plane); |
1823 | intel_flush_display_plane(dev_priv, plane); |
1810 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1824 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1811 | } |
1825 | } |
1812 | 1826 | ||
1813 | static bool need_vtd_wa(struct drm_device *dev) |
1827 | static bool need_vtd_wa(struct drm_device *dev) |
1814 | { |
1828 | { |
1815 | #ifdef CONFIG_INTEL_IOMMU |
1829 | #ifdef CONFIG_INTEL_IOMMU |
1816 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1830 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1817 | return true; |
1831 | return true; |
1818 | #endif |
1832 | #endif |
1819 | return false; |
1833 | return false; |
1820 | } |
1834 | } |
1821 | 1835 | ||
1822 | int |
1836 | int |
1823 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1837 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1824 | struct drm_i915_gem_object *obj, |
1838 | struct drm_i915_gem_object *obj, |
1825 | struct intel_ring_buffer *pipelined) |
1839 | struct intel_ring_buffer *pipelined) |
1826 | { |
1840 | { |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
1841 | struct drm_i915_private *dev_priv = dev->dev_private; |
1828 | u32 alignment; |
1842 | u32 alignment; |
1829 | int ret; |
1843 | int ret; |
1830 | 1844 | ||
1831 | switch (obj->tiling_mode) { |
1845 | switch (obj->tiling_mode) { |
1832 | case I915_TILING_NONE: |
1846 | case I915_TILING_NONE: |
1833 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1847 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1834 | alignment = 128 * 1024; |
1848 | alignment = 128 * 1024; |
1835 | else if (INTEL_INFO(dev)->gen >= 4) |
1849 | else if (INTEL_INFO(dev)->gen >= 4) |
1836 | alignment = 4 * 1024; |
1850 | alignment = 4 * 1024; |
1837 | else |
1851 | else |
1838 | alignment = 64 * 1024; |
1852 | alignment = 64 * 1024; |
1839 | break; |
1853 | break; |
1840 | case I915_TILING_X: |
1854 | case I915_TILING_X: |
1841 | /* pin() will align the object as required by fence */ |
1855 | /* pin() will align the object as required by fence */ |
1842 | alignment = 0; |
1856 | alignment = 0; |
1843 | break; |
1857 | break; |
1844 | case I915_TILING_Y: |
1858 | case I915_TILING_Y: |
1845 | /* Despite that we check this in framebuffer_init userspace can |
1859 | /* Despite that we check this in framebuffer_init userspace can |
1846 | * screw us over and change the tiling after the fact. Only |
1860 | * screw us over and change the tiling after the fact. Only |
1847 | * pinned buffers can't change their tiling. */ |
1861 | * pinned buffers can't change their tiling. */ |
1848 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
1862 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
1849 | return -EINVAL; |
1863 | return -EINVAL; |
1850 | default: |
1864 | default: |
1851 | BUG(); |
1865 | BUG(); |
1852 | } |
1866 | } |
1853 | 1867 | ||
1854 | /* Note that the w/a also requires 64 PTE of padding following the |
1868 | /* Note that the w/a also requires 64 PTE of padding following the |
1855 | * bo. We currently fill all unused PTE with the shadow page and so |
1869 | * bo. We currently fill all unused PTE with the shadow page and so |
1856 | * we should always have valid PTE following the scanout preventing |
1870 | * we should always have valid PTE following the scanout preventing |
1857 | * the VT-d warning. |
1871 | * the VT-d warning. |
1858 | */ |
1872 | */ |
1859 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1873 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1860 | alignment = 256 * 1024; |
1874 | alignment = 256 * 1024; |
1861 | 1875 | ||
1862 | dev_priv->mm.interruptible = false; |
1876 | dev_priv->mm.interruptible = false; |
1863 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1877 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1864 | if (ret) |
1878 | if (ret) |
1865 | goto err_interruptible; |
1879 | goto err_interruptible; |
1866 | 1880 | ||
1867 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1881 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1868 | * fence, whereas 965+ only requires a fence if using |
1882 | * fence, whereas 965+ only requires a fence if using |
1869 | * framebuffer compression. For simplicity, we always install |
1883 | * framebuffer compression. For simplicity, we always install |
1870 | * a fence as the cost is not that onerous. |
1884 | * a fence as the cost is not that onerous. |
1871 | */ |
1885 | */ |
1872 | ret = i915_gem_object_get_fence(obj); |
1886 | ret = i915_gem_object_get_fence(obj); |
1873 | if (ret) |
1887 | if (ret) |
1874 | goto err_unpin; |
1888 | goto err_unpin; |
1875 | 1889 | ||
1876 | i915_gem_object_pin_fence(obj); |
1890 | i915_gem_object_pin_fence(obj); |
1877 | 1891 | ||
1878 | dev_priv->mm.interruptible = true; |
1892 | dev_priv->mm.interruptible = true; |
1879 | return 0; |
1893 | return 0; |
1880 | 1894 | ||
1881 | err_unpin: |
1895 | err_unpin: |
1882 | i915_gem_object_unpin_from_display_plane(obj); |
1896 | i915_gem_object_unpin_from_display_plane(obj); |
1883 | err_interruptible: |
1897 | err_interruptible: |
1884 | dev_priv->mm.interruptible = true; |
1898 | dev_priv->mm.interruptible = true; |
1885 | return ret; |
1899 | return ret; |
1886 | } |
1900 | } |
1887 | 1901 | ||
1888 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1902 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1889 | { |
1903 | { |
1890 | // i915_gem_object_unpin_fence(obj); |
1904 | // i915_gem_object_unpin_fence(obj); |
1891 | // i915_gem_object_unpin(obj); |
1905 | // i915_gem_object_unpin(obj); |
1892 | } |
1906 | } |
1893 | 1907 | ||
1894 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1908 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1895 | * is assumed to be a power-of-two. */ |
1909 | * is assumed to be a power-of-two. */ |
1896 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1910 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1897 | unsigned int tiling_mode, |
1911 | unsigned int tiling_mode, |
1898 | unsigned int cpp, |
1912 | unsigned int cpp, |
1899 | unsigned int pitch) |
1913 | unsigned int pitch) |
1900 | { |
1914 | { |
1901 | if (tiling_mode != I915_TILING_NONE) { |
1915 | if (tiling_mode != I915_TILING_NONE) { |
1902 | unsigned int tile_rows, tiles; |
1916 | unsigned int tile_rows, tiles; |
1903 | 1917 | ||
1904 | tile_rows = *y / 8; |
1918 | tile_rows = *y / 8; |
1905 | *y %= 8; |
1919 | *y %= 8; |
1906 | 1920 | ||
1907 | tiles = *x / (512/cpp); |
1921 | tiles = *x / (512/cpp); |
1908 | *x %= 512/cpp; |
1922 | *x %= 512/cpp; |
1909 | 1923 | ||
1910 | return tile_rows * pitch * 8 + tiles * 4096; |
1924 | return tile_rows * pitch * 8 + tiles * 4096; |
1911 | } else { |
1925 | } else { |
1912 | unsigned int offset; |
1926 | unsigned int offset; |
1913 | 1927 | ||
1914 | offset = *y * pitch + *x * cpp; |
1928 | offset = *y * pitch + *x * cpp; |
1915 | *y = 0; |
1929 | *y = 0; |
1916 | *x = (offset & 4095) / cpp; |
1930 | *x = (offset & 4095) / cpp; |
1917 | return offset & -4096; |
1931 | return offset & -4096; |
1918 | } |
1932 | } |
1919 | } |
1933 | } |
1920 | 1934 | ||
1921 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1935 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1922 | int x, int y) |
1936 | int x, int y) |
1923 | { |
1937 | { |
1924 | struct drm_device *dev = crtc->dev; |
1938 | struct drm_device *dev = crtc->dev; |
1925 | struct drm_i915_private *dev_priv = dev->dev_private; |
1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
1926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1927 | struct intel_framebuffer *intel_fb; |
1941 | struct intel_framebuffer *intel_fb; |
1928 | struct drm_i915_gem_object *obj; |
1942 | struct drm_i915_gem_object *obj; |
1929 | int plane = intel_crtc->plane; |
1943 | int plane = intel_crtc->plane; |
1930 | unsigned long linear_offset; |
1944 | unsigned long linear_offset; |
1931 | u32 dspcntr; |
1945 | u32 dspcntr; |
1932 | u32 reg; |
1946 | u32 reg; |
1933 | 1947 | ||
1934 | switch (plane) { |
1948 | switch (plane) { |
1935 | case 0: |
1949 | case 0: |
1936 | case 1: |
1950 | case 1: |
1937 | break; |
1951 | break; |
1938 | default: |
1952 | default: |
1939 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
1953 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
1940 | return -EINVAL; |
1954 | return -EINVAL; |
1941 | } |
1955 | } |
1942 | 1956 | ||
1943 | intel_fb = to_intel_framebuffer(fb); |
1957 | intel_fb = to_intel_framebuffer(fb); |
1944 | obj = intel_fb->obj; |
1958 | obj = intel_fb->obj; |
1945 | 1959 | ||
1946 | reg = DSPCNTR(plane); |
1960 | reg = DSPCNTR(plane); |
1947 | dspcntr = I915_READ(reg); |
1961 | dspcntr = I915_READ(reg); |
1948 | /* Mask out pixel format bits in case we change it */ |
1962 | /* Mask out pixel format bits in case we change it */ |
1949 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1963 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1950 | switch (fb->pixel_format) { |
1964 | switch (fb->pixel_format) { |
1951 | case DRM_FORMAT_C8: |
1965 | case DRM_FORMAT_C8: |
1952 | dspcntr |= DISPPLANE_8BPP; |
1966 | dspcntr |= DISPPLANE_8BPP; |
1953 | break; |
1967 | break; |
1954 | case DRM_FORMAT_XRGB1555: |
1968 | case DRM_FORMAT_XRGB1555: |
1955 | case DRM_FORMAT_ARGB1555: |
1969 | case DRM_FORMAT_ARGB1555: |
1956 | dspcntr |= DISPPLANE_BGRX555; |
1970 | dspcntr |= DISPPLANE_BGRX555; |
1957 | break; |
1971 | break; |
1958 | case DRM_FORMAT_RGB565: |
1972 | case DRM_FORMAT_RGB565: |
1959 | dspcntr |= DISPPLANE_BGRX565; |
1973 | dspcntr |= DISPPLANE_BGRX565; |
1960 | break; |
1974 | break; |
1961 | case DRM_FORMAT_XRGB8888: |
1975 | case DRM_FORMAT_XRGB8888: |
1962 | case DRM_FORMAT_ARGB8888: |
1976 | case DRM_FORMAT_ARGB8888: |
1963 | dspcntr |= DISPPLANE_BGRX888; |
1977 | dspcntr |= DISPPLANE_BGRX888; |
1964 | break; |
1978 | break; |
1965 | case DRM_FORMAT_XBGR8888: |
1979 | case DRM_FORMAT_XBGR8888: |
1966 | case DRM_FORMAT_ABGR8888: |
1980 | case DRM_FORMAT_ABGR8888: |
1967 | dspcntr |= DISPPLANE_RGBX888; |
1981 | dspcntr |= DISPPLANE_RGBX888; |
1968 | break; |
1982 | break; |
1969 | case DRM_FORMAT_XRGB2101010: |
1983 | case DRM_FORMAT_XRGB2101010: |
1970 | case DRM_FORMAT_ARGB2101010: |
1984 | case DRM_FORMAT_ARGB2101010: |
1971 | dspcntr |= DISPPLANE_BGRX101010; |
1985 | dspcntr |= DISPPLANE_BGRX101010; |
1972 | break; |
1986 | break; |
1973 | case DRM_FORMAT_XBGR2101010: |
1987 | case DRM_FORMAT_XBGR2101010: |
1974 | case DRM_FORMAT_ABGR2101010: |
1988 | case DRM_FORMAT_ABGR2101010: |
1975 | dspcntr |= DISPPLANE_RGBX101010; |
1989 | dspcntr |= DISPPLANE_RGBX101010; |
1976 | break; |
1990 | break; |
1977 | default: |
1991 | default: |
1978 | BUG(); |
1992 | BUG(); |
1979 | } |
1993 | } |
1980 | 1994 | ||
1981 | if (INTEL_INFO(dev)->gen >= 4) { |
1995 | if (INTEL_INFO(dev)->gen >= 4) { |
1982 | if (obj->tiling_mode != I915_TILING_NONE) |
1996 | if (obj->tiling_mode != I915_TILING_NONE) |
1983 | dspcntr |= DISPPLANE_TILED; |
1997 | dspcntr |= DISPPLANE_TILED; |
1984 | else |
1998 | else |
1985 | dspcntr &= ~DISPPLANE_TILED; |
1999 | dspcntr &= ~DISPPLANE_TILED; |
1986 | } |
2000 | } |
1987 | 2001 | ||
1988 | if (IS_G4X(dev)) |
2002 | if (IS_G4X(dev)) |
1989 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2003 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
1990 | 2004 | ||
1991 | I915_WRITE(reg, dspcntr); |
2005 | I915_WRITE(reg, dspcntr); |
1992 | 2006 | ||
1993 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2007 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
1994 | 2008 | ||
1995 | if (INTEL_INFO(dev)->gen >= 4) { |
2009 | if (INTEL_INFO(dev)->gen >= 4) { |
1996 | intel_crtc->dspaddr_offset = |
2010 | intel_crtc->dspaddr_offset = |
1997 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2011 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
1998 | fb->bits_per_pixel / 8, |
2012 | fb->bits_per_pixel / 8, |
1999 | fb->pitches[0]); |
2013 | fb->pitches[0]); |
2000 | linear_offset -= intel_crtc->dspaddr_offset; |
2014 | linear_offset -= intel_crtc->dspaddr_offset; |
2001 | } else { |
2015 | } else { |
2002 | intel_crtc->dspaddr_offset = linear_offset; |
2016 | intel_crtc->dspaddr_offset = linear_offset; |
2003 | } |
2017 | } |
2004 | 2018 | ||
2005 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2019 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2006 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2020 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2007 | fb->pitches[0]); |
2021 | fb->pitches[0]); |
2008 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2022 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2009 | if (INTEL_INFO(dev)->gen >= 4) { |
2023 | if (INTEL_INFO(dev)->gen >= 4) { |
2010 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2024 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2011 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2025 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2012 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2026 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2013 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2027 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2014 | } else |
2028 | } else |
2015 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2029 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2016 | POSTING_READ(reg); |
2030 | POSTING_READ(reg); |
2017 | 2031 | ||
2018 | return 0; |
2032 | return 0; |
2019 | } |
2033 | } |
2020 | 2034 | ||
2021 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2035 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2022 | struct drm_framebuffer *fb, int x, int y) |
2036 | struct drm_framebuffer *fb, int x, int y) |
2023 | { |
2037 | { |
2024 | struct drm_device *dev = crtc->dev; |
2038 | struct drm_device *dev = crtc->dev; |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
2039 | struct drm_i915_private *dev_priv = dev->dev_private; |
2026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2027 | struct intel_framebuffer *intel_fb; |
2041 | struct intel_framebuffer *intel_fb; |
2028 | struct drm_i915_gem_object *obj; |
2042 | struct drm_i915_gem_object *obj; |
2029 | int plane = intel_crtc->plane; |
2043 | int plane = intel_crtc->plane; |
2030 | unsigned long linear_offset; |
2044 | unsigned long linear_offset; |
2031 | u32 dspcntr; |
2045 | u32 dspcntr; |
2032 | u32 reg; |
2046 | u32 reg; |
2033 | 2047 | ||
2034 | switch (plane) { |
2048 | switch (plane) { |
2035 | case 0: |
2049 | case 0: |
2036 | case 1: |
2050 | case 1: |
2037 | case 2: |
2051 | case 2: |
2038 | break; |
2052 | break; |
2039 | default: |
2053 | default: |
2040 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2054 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2041 | return -EINVAL; |
2055 | return -EINVAL; |
2042 | } |
2056 | } |
2043 | 2057 | ||
2044 | intel_fb = to_intel_framebuffer(fb); |
2058 | intel_fb = to_intel_framebuffer(fb); |
2045 | obj = intel_fb->obj; |
2059 | obj = intel_fb->obj; |
2046 | 2060 | ||
2047 | reg = DSPCNTR(plane); |
2061 | reg = DSPCNTR(plane); |
2048 | dspcntr = I915_READ(reg); |
2062 | dspcntr = I915_READ(reg); |
2049 | /* Mask out pixel format bits in case we change it */ |
2063 | /* Mask out pixel format bits in case we change it */ |
2050 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2064 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2051 | switch (fb->pixel_format) { |
2065 | switch (fb->pixel_format) { |
2052 | case DRM_FORMAT_C8: |
2066 | case DRM_FORMAT_C8: |
2053 | dspcntr |= DISPPLANE_8BPP; |
2067 | dspcntr |= DISPPLANE_8BPP; |
2054 | break; |
2068 | break; |
2055 | case DRM_FORMAT_RGB565: |
2069 | case DRM_FORMAT_RGB565: |
2056 | dspcntr |= DISPPLANE_BGRX565; |
2070 | dspcntr |= DISPPLANE_BGRX565; |
2057 | break; |
2071 | break; |
2058 | case DRM_FORMAT_XRGB8888: |
2072 | case DRM_FORMAT_XRGB8888: |
2059 | case DRM_FORMAT_ARGB8888: |
2073 | case DRM_FORMAT_ARGB8888: |
2060 | dspcntr |= DISPPLANE_BGRX888; |
2074 | dspcntr |= DISPPLANE_BGRX888; |
2061 | break; |
2075 | break; |
2062 | case DRM_FORMAT_XBGR8888: |
2076 | case DRM_FORMAT_XBGR8888: |
2063 | case DRM_FORMAT_ABGR8888: |
2077 | case DRM_FORMAT_ABGR8888: |
2064 | dspcntr |= DISPPLANE_RGBX888; |
2078 | dspcntr |= DISPPLANE_RGBX888; |
2065 | break; |
2079 | break; |
2066 | case DRM_FORMAT_XRGB2101010: |
2080 | case DRM_FORMAT_XRGB2101010: |
2067 | case DRM_FORMAT_ARGB2101010: |
2081 | case DRM_FORMAT_ARGB2101010: |
2068 | dspcntr |= DISPPLANE_BGRX101010; |
2082 | dspcntr |= DISPPLANE_BGRX101010; |
2069 | break; |
2083 | break; |
2070 | case DRM_FORMAT_XBGR2101010: |
2084 | case DRM_FORMAT_XBGR2101010: |
2071 | case DRM_FORMAT_ABGR2101010: |
2085 | case DRM_FORMAT_ABGR2101010: |
2072 | dspcntr |= DISPPLANE_RGBX101010; |
2086 | dspcntr |= DISPPLANE_RGBX101010; |
2073 | break; |
2087 | break; |
2074 | default: |
2088 | default: |
2075 | BUG(); |
2089 | BUG(); |
2076 | } |
2090 | } |
2077 | 2091 | ||
2078 | if (obj->tiling_mode != I915_TILING_NONE) |
2092 | if (obj->tiling_mode != I915_TILING_NONE) |
2079 | dspcntr |= DISPPLANE_TILED; |
2093 | dspcntr |= DISPPLANE_TILED; |
2080 | else |
2094 | else |
2081 | dspcntr &= ~DISPPLANE_TILED; |
2095 | dspcntr &= ~DISPPLANE_TILED; |
2082 | 2096 | ||
2083 | if (IS_HASWELL(dev)) |
2097 | if (IS_HASWELL(dev)) |
2084 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2098 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2085 | else |
2099 | else |
2086 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2100 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2087 | 2101 | ||
2088 | I915_WRITE(reg, dspcntr); |
2102 | I915_WRITE(reg, dspcntr); |
2089 | 2103 | ||
2090 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2104 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2091 | intel_crtc->dspaddr_offset = |
2105 | intel_crtc->dspaddr_offset = |
2092 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2106 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2093 | fb->bits_per_pixel / 8, |
2107 | fb->bits_per_pixel / 8, |
2094 | fb->pitches[0]); |
2108 | fb->pitches[0]); |
2095 | linear_offset -= intel_crtc->dspaddr_offset; |
2109 | linear_offset -= intel_crtc->dspaddr_offset; |
2096 | 2110 | ||
2097 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2111 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2098 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2112 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2099 | fb->pitches[0]); |
2113 | fb->pitches[0]); |
2100 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2114 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2101 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2115 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2102 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2116 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2103 | if (IS_HASWELL(dev)) { |
2117 | if (IS_HASWELL(dev)) { |
2104 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2118 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2105 | } else { |
2119 | } else { |
2106 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2120 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2107 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2121 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2108 | } |
2122 | } |
2109 | POSTING_READ(reg); |
2123 | POSTING_READ(reg); |
2110 | 2124 | ||
2111 | return 0; |
2125 | return 0; |
2112 | } |
2126 | } |
2113 | 2127 | ||
2114 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2128 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2115 | static int |
2129 | static int |
2116 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2130 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2117 | int x, int y, enum mode_set_atomic state) |
2131 | int x, int y, enum mode_set_atomic state) |
2118 | { |
2132 | { |
2119 | struct drm_device *dev = crtc->dev; |
2133 | struct drm_device *dev = crtc->dev; |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
2134 | struct drm_i915_private *dev_priv = dev->dev_private; |
2121 | 2135 | ||
2122 | if (dev_priv->display.disable_fbc) |
2136 | if (dev_priv->display.disable_fbc) |
2123 | dev_priv->display.disable_fbc(dev); |
2137 | dev_priv->display.disable_fbc(dev); |
2124 | intel_increase_pllclock(crtc); |
2138 | intel_increase_pllclock(crtc); |
2125 | 2139 | ||
2126 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2140 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2127 | } |
2141 | } |
2128 | 2142 | ||
2129 | #if 0 |
2143 | #if 0 |
2130 | void intel_display_handle_reset(struct drm_device *dev) |
2144 | void intel_display_handle_reset(struct drm_device *dev) |
2131 | { |
2145 | { |
2132 | struct drm_i915_private *dev_priv = dev->dev_private; |
2146 | struct drm_i915_private *dev_priv = dev->dev_private; |
2133 | struct drm_crtc *crtc; |
2147 | struct drm_crtc *crtc; |
2134 | 2148 | ||
2135 | /* |
2149 | /* |
2136 | * Flips in the rings have been nuked by the reset, |
2150 | * Flips in the rings have been nuked by the reset, |
2137 | * so complete all pending flips so that user space |
2151 | * so complete all pending flips so that user space |
2138 | * will get its events and not get stuck. |
2152 | * will get its events and not get stuck. |
2139 | * |
2153 | * |
2140 | * Also update the base address of all primary |
2154 | * Also update the base address of all primary |
2141 | * planes to the the last fb to make sure we're |
2155 | * planes to the the last fb to make sure we're |
2142 | * showing the correct fb after a reset. |
2156 | * showing the correct fb after a reset. |
2143 | * |
2157 | * |
2144 | * Need to make two loops over the crtcs so that we |
2158 | * Need to make two loops over the crtcs so that we |
2145 | * don't try to grab a crtc mutex before the |
2159 | * don't try to grab a crtc mutex before the |
2146 | * pending_flip_queue really got woken up. |
2160 | * pending_flip_queue really got woken up. |
2147 | */ |
2161 | */ |
2148 | 2162 | ||
2149 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2163 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2151 | enum plane plane = intel_crtc->plane; |
2165 | enum plane plane = intel_crtc->plane; |
2152 | 2166 | ||
2153 | intel_prepare_page_flip(dev, plane); |
2167 | intel_prepare_page_flip(dev, plane); |
2154 | intel_finish_page_flip_plane(dev, plane); |
2168 | intel_finish_page_flip_plane(dev, plane); |
2155 | } |
2169 | } |
2156 | 2170 | ||
2157 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2171 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2159 | 2173 | ||
2160 | mutex_lock(&crtc->mutex); |
2174 | mutex_lock(&crtc->mutex); |
2161 | if (intel_crtc->active) |
2175 | if (intel_crtc->active) |
2162 | dev_priv->display.update_plane(crtc, crtc->fb, |
2176 | dev_priv->display.update_plane(crtc, crtc->fb, |
2163 | crtc->x, crtc->y); |
2177 | crtc->x, crtc->y); |
2164 | mutex_unlock(&crtc->mutex); |
2178 | mutex_unlock(&crtc->mutex); |
2165 | } |
2179 | } |
2166 | } |
2180 | } |
2167 | 2181 | ||
2168 | static int |
2182 | static int |
2169 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2183 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2170 | { |
2184 | { |
2171 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2185 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2172 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2186 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2173 | bool was_interruptible = dev_priv->mm.interruptible; |
2187 | bool was_interruptible = dev_priv->mm.interruptible; |
2174 | int ret; |
2188 | int ret; |
2175 | 2189 | ||
2176 | /* Big Hammer, we also need to ensure that any pending |
2190 | /* Big Hammer, we also need to ensure that any pending |
2177 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2191 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2178 | * current scanout is retired before unpinning the old |
2192 | * current scanout is retired before unpinning the old |
2179 | * framebuffer. |
2193 | * framebuffer. |
2180 | * |
2194 | * |
2181 | * This should only fail upon a hung GPU, in which case we |
2195 | * This should only fail upon a hung GPU, in which case we |
2182 | * can safely continue. |
2196 | * can safely continue. |
2183 | */ |
2197 | */ |
2184 | dev_priv->mm.interruptible = false; |
2198 | dev_priv->mm.interruptible = false; |
2185 | ret = i915_gem_object_finish_gpu(obj); |
2199 | ret = i915_gem_object_finish_gpu(obj); |
2186 | dev_priv->mm.interruptible = was_interruptible; |
2200 | dev_priv->mm.interruptible = was_interruptible; |
2187 | 2201 | ||
2188 | return ret; |
2202 | return ret; |
2189 | } |
2203 | } |
2190 | 2204 | ||
2191 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2205 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2192 | { |
2206 | { |
2193 | struct drm_device *dev = crtc->dev; |
2207 | struct drm_device *dev = crtc->dev; |
2194 | struct drm_i915_master_private *master_priv; |
2208 | struct drm_i915_master_private *master_priv; |
2195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2196 | 2210 | ||
2197 | if (!dev->primary->master) |
2211 | if (!dev->primary->master) |
2198 | return; |
2212 | return; |
2199 | 2213 | ||
2200 | master_priv = dev->primary->master->driver_priv; |
2214 | master_priv = dev->primary->master->driver_priv; |
2201 | if (!master_priv->sarea_priv) |
2215 | if (!master_priv->sarea_priv) |
2202 | return; |
2216 | return; |
2203 | 2217 | ||
2204 | switch (intel_crtc->pipe) { |
2218 | switch (intel_crtc->pipe) { |
2205 | case 0: |
2219 | case 0: |
2206 | master_priv->sarea_priv->pipeA_x = x; |
2220 | master_priv->sarea_priv->pipeA_x = x; |
2207 | master_priv->sarea_priv->pipeA_y = y; |
2221 | master_priv->sarea_priv->pipeA_y = y; |
2208 | break; |
2222 | break; |
2209 | case 1: |
2223 | case 1: |
2210 | master_priv->sarea_priv->pipeB_x = x; |
2224 | master_priv->sarea_priv->pipeB_x = x; |
2211 | master_priv->sarea_priv->pipeB_y = y; |
2225 | master_priv->sarea_priv->pipeB_y = y; |
2212 | break; |
2226 | break; |
2213 | default: |
2227 | default: |
2214 | break; |
2228 | break; |
2215 | } |
2229 | } |
2216 | } |
2230 | } |
2217 | #endif |
2231 | #endif |
2218 | 2232 | ||
2219 | static int |
2233 | static int |
2220 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2234 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2221 | struct drm_framebuffer *fb) |
2235 | struct drm_framebuffer *fb) |
2222 | { |
2236 | { |
2223 | struct drm_device *dev = crtc->dev; |
2237 | struct drm_device *dev = crtc->dev; |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; |
2238 | struct drm_i915_private *dev_priv = dev->dev_private; |
2225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2226 | struct drm_framebuffer *old_fb; |
2240 | struct drm_framebuffer *old_fb; |
2227 | int ret; |
2241 | int ret; |
2228 | 2242 | ||
2229 | /* no fb bound */ |
2243 | /* no fb bound */ |
2230 | if (!fb) { |
2244 | if (!fb) { |
2231 | DRM_ERROR("No FB bound\n"); |
2245 | DRM_ERROR("No FB bound\n"); |
2232 | return 0; |
2246 | return 0; |
2233 | } |
2247 | } |
2234 | 2248 | ||
2235 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2249 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2236 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2250 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2237 | plane_name(intel_crtc->plane), |
2251 | plane_name(intel_crtc->plane), |
2238 | INTEL_INFO(dev)->num_pipes); |
2252 | INTEL_INFO(dev)->num_pipes); |
2239 | return -EINVAL; |
2253 | return -EINVAL; |
2240 | } |
2254 | } |
2241 | 2255 | ||
2242 | mutex_lock(&dev->struct_mutex); |
2256 | mutex_lock(&dev->struct_mutex); |
2243 | ret = intel_pin_and_fence_fb_obj(dev, |
2257 | ret = intel_pin_and_fence_fb_obj(dev, |
2244 | to_intel_framebuffer(fb)->obj, |
2258 | to_intel_framebuffer(fb)->obj, |
2245 | NULL); |
2259 | NULL); |
2246 | if (ret != 0) { |
2260 | if (ret != 0) { |
2247 | mutex_unlock(&dev->struct_mutex); |
2261 | mutex_unlock(&dev->struct_mutex); |
2248 | DRM_ERROR("pin & fence failed\n"); |
2262 | DRM_ERROR("pin & fence failed\n"); |
2249 | return ret; |
2263 | return ret; |
2250 | } |
2264 | } |
2251 | 2265 | ||
2252 | /* Update pipe size and adjust fitter if needed */ |
2266 | /* Update pipe size and adjust fitter if needed */ |
2253 | if (i915_fastboot) { |
2267 | if (i915_fastboot) { |
2254 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2268 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2255 | ((crtc->mode.hdisplay - 1) << 16) | |
2269 | ((crtc->mode.hdisplay - 1) << 16) | |
2256 | (crtc->mode.vdisplay - 1)); |
2270 | (crtc->mode.vdisplay - 1)); |
2257 | if (!intel_crtc->config.pch_pfit.enabled && |
2271 | if (!intel_crtc->config.pch_pfit.enabled && |
2258 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2272 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2259 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2273 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2260 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2274 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2261 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2275 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2262 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2276 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2263 | } |
2277 | } |
2264 | } |
2278 | } |
2265 | 2279 | ||
2266 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2280 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2267 | if (ret) { |
2281 | if (ret) { |
2268 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2282 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2269 | mutex_unlock(&dev->struct_mutex); |
2283 | mutex_unlock(&dev->struct_mutex); |
2270 | DRM_ERROR("failed to update base address\n"); |
2284 | DRM_ERROR("failed to update base address\n"); |
2271 | return ret; |
2285 | return ret; |
2272 | } |
2286 | } |
2273 | 2287 | ||
2274 | old_fb = crtc->fb; |
2288 | old_fb = crtc->fb; |
2275 | crtc->fb = fb; |
2289 | crtc->fb = fb; |
2276 | crtc->x = x; |
2290 | crtc->x = x; |
2277 | crtc->y = y; |
2291 | crtc->y = y; |
2278 | 2292 | ||
2279 | if (old_fb) { |
2293 | if (old_fb) { |
2280 | if (intel_crtc->active && old_fb != fb) |
2294 | if (intel_crtc->active && old_fb != fb) |
2281 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2295 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2282 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2296 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2283 | } |
2297 | } |
2284 | 2298 | ||
2285 | intel_update_fbc(dev); |
2299 | intel_update_fbc(dev); |
2286 | intel_edp_psr_update(dev); |
2300 | intel_edp_psr_update(dev); |
2287 | mutex_unlock(&dev->struct_mutex); |
2301 | mutex_unlock(&dev->struct_mutex); |
2288 | 2302 | ||
2289 | return 0; |
2303 | return 0; |
2290 | } |
2304 | } |
2291 | 2305 | ||
2292 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2306 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2293 | { |
2307 | { |
2294 | struct drm_device *dev = crtc->dev; |
2308 | struct drm_device *dev = crtc->dev; |
2295 | struct drm_i915_private *dev_priv = dev->dev_private; |
2309 | struct drm_i915_private *dev_priv = dev->dev_private; |
2296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2297 | int pipe = intel_crtc->pipe; |
2311 | int pipe = intel_crtc->pipe; |
2298 | u32 reg, temp; |
2312 | u32 reg, temp; |
2299 | 2313 | ||
2300 | /* enable normal train */ |
2314 | /* enable normal train */ |
2301 | reg = FDI_TX_CTL(pipe); |
2315 | reg = FDI_TX_CTL(pipe); |
2302 | temp = I915_READ(reg); |
2316 | temp = I915_READ(reg); |
2303 | if (IS_IVYBRIDGE(dev)) { |
2317 | if (IS_IVYBRIDGE(dev)) { |
2304 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2318 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2305 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2319 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2306 | } else { |
2320 | } else { |
2307 | temp &= ~FDI_LINK_TRAIN_NONE; |
2321 | temp &= ~FDI_LINK_TRAIN_NONE; |
2308 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2322 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2309 | } |
2323 | } |
2310 | I915_WRITE(reg, temp); |
2324 | I915_WRITE(reg, temp); |
2311 | 2325 | ||
2312 | reg = FDI_RX_CTL(pipe); |
2326 | reg = FDI_RX_CTL(pipe); |
2313 | temp = I915_READ(reg); |
2327 | temp = I915_READ(reg); |
2314 | if (HAS_PCH_CPT(dev)) { |
2328 | if (HAS_PCH_CPT(dev)) { |
2315 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2329 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2316 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2330 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2317 | } else { |
2331 | } else { |
2318 | temp &= ~FDI_LINK_TRAIN_NONE; |
2332 | temp &= ~FDI_LINK_TRAIN_NONE; |
2319 | temp |= FDI_LINK_TRAIN_NONE; |
2333 | temp |= FDI_LINK_TRAIN_NONE; |
2320 | } |
2334 | } |
2321 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2335 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2322 | 2336 | ||
2323 | /* wait one idle pattern time */ |
2337 | /* wait one idle pattern time */ |
2324 | POSTING_READ(reg); |
2338 | POSTING_READ(reg); |
2325 | udelay(1000); |
2339 | udelay(1000); |
2326 | 2340 | ||
2327 | /* IVB wants error correction enabled */ |
2341 | /* IVB wants error correction enabled */ |
2328 | if (IS_IVYBRIDGE(dev)) |
2342 | if (IS_IVYBRIDGE(dev)) |
2329 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2343 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2330 | FDI_FE_ERRC_ENABLE); |
2344 | FDI_FE_ERRC_ENABLE); |
2331 | } |
2345 | } |
2332 | 2346 | ||
2333 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2347 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2334 | { |
2348 | { |
2335 | return crtc->base.enabled && crtc->active && |
2349 | return crtc->base.enabled && crtc->active && |
2336 | crtc->config.has_pch_encoder; |
2350 | crtc->config.has_pch_encoder; |
2337 | } |
2351 | } |
2338 | 2352 | ||
2339 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2353 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2340 | { |
2354 | { |
2341 | struct drm_i915_private *dev_priv = dev->dev_private; |
2355 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | struct intel_crtc *pipe_B_crtc = |
2356 | struct intel_crtc *pipe_B_crtc = |
2343 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2357 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2344 | struct intel_crtc *pipe_C_crtc = |
2358 | struct intel_crtc *pipe_C_crtc = |
2345 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2359 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2346 | uint32_t temp; |
2360 | uint32_t temp; |
2347 | 2361 | ||
2348 | /* |
2362 | /* |
2349 | * When everything is off disable fdi C so that we could enable fdi B |
2363 | * When everything is off disable fdi C so that we could enable fdi B |
2350 | * with all lanes. Note that we don't care about enabled pipes without |
2364 | * with all lanes. Note that we don't care about enabled pipes without |
2351 | * an enabled pch encoder. |
2365 | * an enabled pch encoder. |
2352 | */ |
2366 | */ |
2353 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2367 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2354 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2368 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2355 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2369 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2356 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2370 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2357 | 2371 | ||
2358 | temp = I915_READ(SOUTH_CHICKEN1); |
2372 | temp = I915_READ(SOUTH_CHICKEN1); |
2359 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2373 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2360 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2374 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2361 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2375 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2362 | } |
2376 | } |
2363 | } |
2377 | } |
2364 | 2378 | ||
2365 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2379 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2366 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2380 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2367 | { |
2381 | { |
2368 | struct drm_device *dev = crtc->dev; |
2382 | struct drm_device *dev = crtc->dev; |
2369 | struct drm_i915_private *dev_priv = dev->dev_private; |
2383 | struct drm_i915_private *dev_priv = dev->dev_private; |
2370 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2371 | int pipe = intel_crtc->pipe; |
2385 | int pipe = intel_crtc->pipe; |
2372 | int plane = intel_crtc->plane; |
2386 | int plane = intel_crtc->plane; |
2373 | u32 reg, temp, tries; |
2387 | u32 reg, temp, tries; |
2374 | 2388 | ||
2375 | /* FDI needs bits from pipe & plane first */ |
2389 | /* FDI needs bits from pipe & plane first */ |
2376 | assert_pipe_enabled(dev_priv, pipe); |
2390 | assert_pipe_enabled(dev_priv, pipe); |
2377 | assert_plane_enabled(dev_priv, plane); |
2391 | assert_plane_enabled(dev_priv, plane); |
2378 | 2392 | ||
2379 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2393 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2380 | for train result */ |
2394 | for train result */ |
2381 | reg = FDI_RX_IMR(pipe); |
2395 | reg = FDI_RX_IMR(pipe); |
2382 | temp = I915_READ(reg); |
2396 | temp = I915_READ(reg); |
2383 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2397 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2384 | temp &= ~FDI_RX_BIT_LOCK; |
2398 | temp &= ~FDI_RX_BIT_LOCK; |
2385 | I915_WRITE(reg, temp); |
2399 | I915_WRITE(reg, temp); |
2386 | I915_READ(reg); |
2400 | I915_READ(reg); |
2387 | udelay(150); |
2401 | udelay(150); |
2388 | 2402 | ||
2389 | /* enable CPU FDI TX and PCH FDI RX */ |
2403 | /* enable CPU FDI TX and PCH FDI RX */ |
2390 | reg = FDI_TX_CTL(pipe); |
2404 | reg = FDI_TX_CTL(pipe); |
2391 | temp = I915_READ(reg); |
2405 | temp = I915_READ(reg); |
2392 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2406 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2393 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2407 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2394 | temp &= ~FDI_LINK_TRAIN_NONE; |
2408 | temp &= ~FDI_LINK_TRAIN_NONE; |
2395 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2409 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2396 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2410 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2397 | 2411 | ||
2398 | reg = FDI_RX_CTL(pipe); |
2412 | reg = FDI_RX_CTL(pipe); |
2399 | temp = I915_READ(reg); |
2413 | temp = I915_READ(reg); |
2400 | temp &= ~FDI_LINK_TRAIN_NONE; |
2414 | temp &= ~FDI_LINK_TRAIN_NONE; |
2401 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2415 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2402 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2416 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2403 | 2417 | ||
2404 | POSTING_READ(reg); |
2418 | POSTING_READ(reg); |
2405 | udelay(150); |
2419 | udelay(150); |
2406 | 2420 | ||
2407 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2421 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2408 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2422 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2409 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2423 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2410 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2424 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2411 | 2425 | ||
2412 | reg = FDI_RX_IIR(pipe); |
2426 | reg = FDI_RX_IIR(pipe); |
2413 | for (tries = 0; tries < 5; tries++) { |
2427 | for (tries = 0; tries < 5; tries++) { |
2414 | temp = I915_READ(reg); |
2428 | temp = I915_READ(reg); |
2415 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2429 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2416 | 2430 | ||
2417 | if ((temp & FDI_RX_BIT_LOCK)) { |
2431 | if ((temp & FDI_RX_BIT_LOCK)) { |
2418 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2432 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2419 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2433 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2420 | break; |
2434 | break; |
2421 | } |
2435 | } |
2422 | } |
2436 | } |
2423 | if (tries == 5) |
2437 | if (tries == 5) |
2424 | DRM_ERROR("FDI train 1 fail!\n"); |
2438 | DRM_ERROR("FDI train 1 fail!\n"); |
2425 | 2439 | ||
2426 | /* Train 2 */ |
2440 | /* Train 2 */ |
2427 | reg = FDI_TX_CTL(pipe); |
2441 | reg = FDI_TX_CTL(pipe); |
2428 | temp = I915_READ(reg); |
2442 | temp = I915_READ(reg); |
2429 | temp &= ~FDI_LINK_TRAIN_NONE; |
2443 | temp &= ~FDI_LINK_TRAIN_NONE; |
2430 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2444 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2431 | I915_WRITE(reg, temp); |
2445 | I915_WRITE(reg, temp); |
2432 | 2446 | ||
2433 | reg = FDI_RX_CTL(pipe); |
2447 | reg = FDI_RX_CTL(pipe); |
2434 | temp = I915_READ(reg); |
2448 | temp = I915_READ(reg); |
2435 | temp &= ~FDI_LINK_TRAIN_NONE; |
2449 | temp &= ~FDI_LINK_TRAIN_NONE; |
2436 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2450 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2437 | I915_WRITE(reg, temp); |
2451 | I915_WRITE(reg, temp); |
2438 | 2452 | ||
2439 | POSTING_READ(reg); |
2453 | POSTING_READ(reg); |
2440 | udelay(150); |
2454 | udelay(150); |
2441 | 2455 | ||
2442 | reg = FDI_RX_IIR(pipe); |
2456 | reg = FDI_RX_IIR(pipe); |
2443 | for (tries = 0; tries < 5; tries++) { |
2457 | for (tries = 0; tries < 5; tries++) { |
2444 | temp = I915_READ(reg); |
2458 | temp = I915_READ(reg); |
2445 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2459 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2446 | 2460 | ||
2447 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2461 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2448 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2462 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2449 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2463 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2450 | break; |
2464 | break; |
2451 | } |
2465 | } |
2452 | } |
2466 | } |
2453 | if (tries == 5) |
2467 | if (tries == 5) |
2454 | DRM_ERROR("FDI train 2 fail!\n"); |
2468 | DRM_ERROR("FDI train 2 fail!\n"); |
2455 | 2469 | ||
2456 | DRM_DEBUG_KMS("FDI train done\n"); |
2470 | DRM_DEBUG_KMS("FDI train done\n"); |
2457 | 2471 | ||
2458 | } |
2472 | } |
2459 | 2473 | ||
2460 | static const int snb_b_fdi_train_param[] = { |
2474 | static const int snb_b_fdi_train_param[] = { |
2461 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2475 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2462 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2476 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2463 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2477 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2464 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2478 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2465 | }; |
2479 | }; |
2466 | 2480 | ||
2467 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2481 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2468 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2482 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2469 | { |
2483 | { |
2470 | struct drm_device *dev = crtc->dev; |
2484 | struct drm_device *dev = crtc->dev; |
2471 | struct drm_i915_private *dev_priv = dev->dev_private; |
2485 | struct drm_i915_private *dev_priv = dev->dev_private; |
2472 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2473 | int pipe = intel_crtc->pipe; |
2487 | int pipe = intel_crtc->pipe; |
2474 | u32 reg, temp, i, retry; |
2488 | u32 reg, temp, i, retry; |
2475 | 2489 | ||
2476 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2490 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2477 | for train result */ |
2491 | for train result */ |
2478 | reg = FDI_RX_IMR(pipe); |
2492 | reg = FDI_RX_IMR(pipe); |
2479 | temp = I915_READ(reg); |
2493 | temp = I915_READ(reg); |
2480 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2494 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2481 | temp &= ~FDI_RX_BIT_LOCK; |
2495 | temp &= ~FDI_RX_BIT_LOCK; |
2482 | I915_WRITE(reg, temp); |
2496 | I915_WRITE(reg, temp); |
2483 | 2497 | ||
2484 | POSTING_READ(reg); |
2498 | POSTING_READ(reg); |
2485 | udelay(150); |
2499 | udelay(150); |
2486 | 2500 | ||
2487 | /* enable CPU FDI TX and PCH FDI RX */ |
2501 | /* enable CPU FDI TX and PCH FDI RX */ |
2488 | reg = FDI_TX_CTL(pipe); |
2502 | reg = FDI_TX_CTL(pipe); |
2489 | temp = I915_READ(reg); |
2503 | temp = I915_READ(reg); |
2490 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2504 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2491 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2505 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2492 | temp &= ~FDI_LINK_TRAIN_NONE; |
2506 | temp &= ~FDI_LINK_TRAIN_NONE; |
2493 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2507 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2494 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2508 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2495 | /* SNB-B */ |
2509 | /* SNB-B */ |
2496 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2510 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2497 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2511 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2498 | 2512 | ||
2499 | I915_WRITE(FDI_RX_MISC(pipe), |
2513 | I915_WRITE(FDI_RX_MISC(pipe), |
2500 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2514 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2501 | 2515 | ||
2502 | reg = FDI_RX_CTL(pipe); |
2516 | reg = FDI_RX_CTL(pipe); |
2503 | temp = I915_READ(reg); |
2517 | temp = I915_READ(reg); |
2504 | if (HAS_PCH_CPT(dev)) { |
2518 | if (HAS_PCH_CPT(dev)) { |
2505 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2519 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2506 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2520 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2507 | } else { |
2521 | } else { |
2508 | temp &= ~FDI_LINK_TRAIN_NONE; |
2522 | temp &= ~FDI_LINK_TRAIN_NONE; |
2509 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2523 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2510 | } |
2524 | } |
2511 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2525 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2512 | 2526 | ||
2513 | POSTING_READ(reg); |
2527 | POSTING_READ(reg); |
2514 | udelay(150); |
2528 | udelay(150); |
2515 | 2529 | ||
2516 | for (i = 0; i < 4; i++) { |
2530 | for (i = 0; i < 4; i++) { |
2517 | reg = FDI_TX_CTL(pipe); |
2531 | reg = FDI_TX_CTL(pipe); |
2518 | temp = I915_READ(reg); |
2532 | temp = I915_READ(reg); |
2519 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2533 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2520 | temp |= snb_b_fdi_train_param[i]; |
2534 | temp |= snb_b_fdi_train_param[i]; |
2521 | I915_WRITE(reg, temp); |
2535 | I915_WRITE(reg, temp); |
2522 | 2536 | ||
2523 | POSTING_READ(reg); |
2537 | POSTING_READ(reg); |
2524 | udelay(500); |
2538 | udelay(500); |
2525 | 2539 | ||
2526 | for (retry = 0; retry < 5; retry++) { |
2540 | for (retry = 0; retry < 5; retry++) { |
2527 | reg = FDI_RX_IIR(pipe); |
2541 | reg = FDI_RX_IIR(pipe); |
2528 | temp = I915_READ(reg); |
2542 | temp = I915_READ(reg); |
2529 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2543 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2530 | if (temp & FDI_RX_BIT_LOCK) { |
2544 | if (temp & FDI_RX_BIT_LOCK) { |
2531 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2545 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2532 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2546 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2533 | break; |
2547 | break; |
2534 | } |
2548 | } |
2535 | udelay(50); |
2549 | udelay(50); |
2536 | } |
2550 | } |
2537 | if (retry < 5) |
2551 | if (retry < 5) |
2538 | break; |
2552 | break; |
2539 | } |
2553 | } |
2540 | if (i == 4) |
2554 | if (i == 4) |
2541 | DRM_ERROR("FDI train 1 fail!\n"); |
2555 | DRM_ERROR("FDI train 1 fail!\n"); |
2542 | 2556 | ||
2543 | /* Train 2 */ |
2557 | /* Train 2 */ |
2544 | reg = FDI_TX_CTL(pipe); |
2558 | reg = FDI_TX_CTL(pipe); |
2545 | temp = I915_READ(reg); |
2559 | temp = I915_READ(reg); |
2546 | temp &= ~FDI_LINK_TRAIN_NONE; |
2560 | temp &= ~FDI_LINK_TRAIN_NONE; |
2547 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2561 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2548 | if (IS_GEN6(dev)) { |
2562 | if (IS_GEN6(dev)) { |
2549 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2563 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2550 | /* SNB-B */ |
2564 | /* SNB-B */ |
2551 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2565 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2552 | } |
2566 | } |
2553 | I915_WRITE(reg, temp); |
2567 | I915_WRITE(reg, temp); |
2554 | 2568 | ||
2555 | reg = FDI_RX_CTL(pipe); |
2569 | reg = FDI_RX_CTL(pipe); |
2556 | temp = I915_READ(reg); |
2570 | temp = I915_READ(reg); |
2557 | if (HAS_PCH_CPT(dev)) { |
2571 | if (HAS_PCH_CPT(dev)) { |
2558 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2572 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2559 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2573 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2560 | } else { |
2574 | } else { |
2561 | temp &= ~FDI_LINK_TRAIN_NONE; |
2575 | temp &= ~FDI_LINK_TRAIN_NONE; |
2562 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2576 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2563 | } |
2577 | } |
2564 | I915_WRITE(reg, temp); |
2578 | I915_WRITE(reg, temp); |
2565 | 2579 | ||
2566 | POSTING_READ(reg); |
2580 | POSTING_READ(reg); |
2567 | udelay(150); |
2581 | udelay(150); |
2568 | 2582 | ||
2569 | for (i = 0; i < 4; i++) { |
2583 | for (i = 0; i < 4; i++) { |
2570 | reg = FDI_TX_CTL(pipe); |
2584 | reg = FDI_TX_CTL(pipe); |
2571 | temp = I915_READ(reg); |
2585 | temp = I915_READ(reg); |
2572 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2586 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2573 | temp |= snb_b_fdi_train_param[i]; |
2587 | temp |= snb_b_fdi_train_param[i]; |
2574 | I915_WRITE(reg, temp); |
2588 | I915_WRITE(reg, temp); |
2575 | 2589 | ||
2576 | POSTING_READ(reg); |
2590 | POSTING_READ(reg); |
2577 | udelay(500); |
2591 | udelay(500); |
2578 | 2592 | ||
2579 | for (retry = 0; retry < 5; retry++) { |
2593 | for (retry = 0; retry < 5; retry++) { |
2580 | reg = FDI_RX_IIR(pipe); |
2594 | reg = FDI_RX_IIR(pipe); |
2581 | temp = I915_READ(reg); |
2595 | temp = I915_READ(reg); |
2582 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2596 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2583 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2597 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2584 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2598 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2585 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2599 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2586 | break; |
2600 | break; |
2587 | } |
2601 | } |
2588 | udelay(50); |
2602 | udelay(50); |
2589 | } |
2603 | } |
2590 | if (retry < 5) |
2604 | if (retry < 5) |
2591 | break; |
2605 | break; |
2592 | } |
2606 | } |
2593 | if (i == 4) |
2607 | if (i == 4) |
2594 | DRM_ERROR("FDI train 2 fail!\n"); |
2608 | DRM_ERROR("FDI train 2 fail!\n"); |
2595 | 2609 | ||
2596 | DRM_DEBUG_KMS("FDI train done.\n"); |
2610 | DRM_DEBUG_KMS("FDI train done.\n"); |
2597 | } |
2611 | } |
2598 | 2612 | ||
2599 | /* Manual link training for Ivy Bridge A0 parts */ |
2613 | /* Manual link training for Ivy Bridge A0 parts */ |
2600 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2614 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2601 | { |
2615 | { |
2602 | struct drm_device *dev = crtc->dev; |
2616 | struct drm_device *dev = crtc->dev; |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; |
2617 | struct drm_i915_private *dev_priv = dev->dev_private; |
2604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2605 | int pipe = intel_crtc->pipe; |
2619 | int pipe = intel_crtc->pipe; |
2606 | u32 reg, temp, i, j; |
2620 | u32 reg, temp, i, j; |
2607 | 2621 | ||
2608 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2622 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2609 | for train result */ |
2623 | for train result */ |
2610 | reg = FDI_RX_IMR(pipe); |
2624 | reg = FDI_RX_IMR(pipe); |
2611 | temp = I915_READ(reg); |
2625 | temp = I915_READ(reg); |
2612 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2626 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2613 | temp &= ~FDI_RX_BIT_LOCK; |
2627 | temp &= ~FDI_RX_BIT_LOCK; |
2614 | I915_WRITE(reg, temp); |
2628 | I915_WRITE(reg, temp); |
2615 | 2629 | ||
2616 | POSTING_READ(reg); |
2630 | POSTING_READ(reg); |
2617 | udelay(150); |
2631 | udelay(150); |
2618 | 2632 | ||
2619 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2633 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2620 | I915_READ(FDI_RX_IIR(pipe))); |
2634 | I915_READ(FDI_RX_IIR(pipe))); |
2621 | 2635 | ||
2622 | /* Try each vswing and preemphasis setting twice before moving on */ |
2636 | /* Try each vswing and preemphasis setting twice before moving on */ |
2623 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2637 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2624 | /* disable first in case we need to retry */ |
2638 | /* disable first in case we need to retry */ |
2625 | reg = FDI_TX_CTL(pipe); |
2639 | reg = FDI_TX_CTL(pipe); |
2626 | temp = I915_READ(reg); |
2640 | temp = I915_READ(reg); |
2627 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2641 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2628 | temp &= ~FDI_TX_ENABLE; |
2642 | temp &= ~FDI_TX_ENABLE; |
2629 | I915_WRITE(reg, temp); |
2643 | I915_WRITE(reg, temp); |
2630 | 2644 | ||
2631 | reg = FDI_RX_CTL(pipe); |
2645 | reg = FDI_RX_CTL(pipe); |
2632 | temp = I915_READ(reg); |
2646 | temp = I915_READ(reg); |
2633 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2647 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2634 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2648 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2635 | temp &= ~FDI_RX_ENABLE; |
2649 | temp &= ~FDI_RX_ENABLE; |
2636 | I915_WRITE(reg, temp); |
2650 | I915_WRITE(reg, temp); |
2637 | 2651 | ||
2638 | /* enable CPU FDI TX and PCH FDI RX */ |
2652 | /* enable CPU FDI TX and PCH FDI RX */ |
2639 | reg = FDI_TX_CTL(pipe); |
2653 | reg = FDI_TX_CTL(pipe); |
2640 | temp = I915_READ(reg); |
2654 | temp = I915_READ(reg); |
2641 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2655 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2642 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2656 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2643 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2657 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2644 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2658 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2645 | temp |= snb_b_fdi_train_param[j/2]; |
2659 | temp |= snb_b_fdi_train_param[j/2]; |
2646 | temp |= FDI_COMPOSITE_SYNC; |
2660 | temp |= FDI_COMPOSITE_SYNC; |
2647 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2661 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2648 | 2662 | ||
2649 | I915_WRITE(FDI_RX_MISC(pipe), |
2663 | I915_WRITE(FDI_RX_MISC(pipe), |
2650 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2664 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2651 | 2665 | ||
2652 | reg = FDI_RX_CTL(pipe); |
2666 | reg = FDI_RX_CTL(pipe); |
2653 | temp = I915_READ(reg); |
2667 | temp = I915_READ(reg); |
2654 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2668 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2655 | temp |= FDI_COMPOSITE_SYNC; |
2669 | temp |= FDI_COMPOSITE_SYNC; |
2656 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2670 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2657 | 2671 | ||
2658 | POSTING_READ(reg); |
2672 | POSTING_READ(reg); |
2659 | udelay(1); /* should be 0.5us */ |
2673 | udelay(1); /* should be 0.5us */ |
2660 | 2674 | ||
2661 | for (i = 0; i < 4; i++) { |
2675 | for (i = 0; i < 4; i++) { |
2662 | reg = FDI_RX_IIR(pipe); |
2676 | reg = FDI_RX_IIR(pipe); |
2663 | temp = I915_READ(reg); |
2677 | temp = I915_READ(reg); |
2664 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2678 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2665 | 2679 | ||
2666 | if (temp & FDI_RX_BIT_LOCK || |
2680 | if (temp & FDI_RX_BIT_LOCK || |
2667 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2681 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2668 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2682 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2669 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2683 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2670 | i); |
2684 | i); |
2671 | break; |
2685 | break; |
2672 | } |
2686 | } |
2673 | udelay(1); /* should be 0.5us */ |
2687 | udelay(1); /* should be 0.5us */ |
2674 | } |
2688 | } |
2675 | if (i == 4) { |
2689 | if (i == 4) { |
2676 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
2690 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
2677 | continue; |
2691 | continue; |
2678 | } |
2692 | } |
2679 | 2693 | ||
2680 | /* Train 2 */ |
2694 | /* Train 2 */ |
2681 | reg = FDI_TX_CTL(pipe); |
2695 | reg = FDI_TX_CTL(pipe); |
2682 | temp = I915_READ(reg); |
2696 | temp = I915_READ(reg); |
2683 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2697 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2684 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2698 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2685 | I915_WRITE(reg, temp); |
2699 | I915_WRITE(reg, temp); |
2686 | 2700 | ||
2687 | reg = FDI_RX_CTL(pipe); |
2701 | reg = FDI_RX_CTL(pipe); |
2688 | temp = I915_READ(reg); |
2702 | temp = I915_READ(reg); |
2689 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2703 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2690 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2704 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2691 | I915_WRITE(reg, temp); |
2705 | I915_WRITE(reg, temp); |
2692 | 2706 | ||
2693 | POSTING_READ(reg); |
2707 | POSTING_READ(reg); |
2694 | udelay(2); /* should be 1.5us */ |
2708 | udelay(2); /* should be 1.5us */ |
2695 | 2709 | ||
2696 | for (i = 0; i < 4; i++) { |
2710 | for (i = 0; i < 4; i++) { |
2697 | reg = FDI_RX_IIR(pipe); |
2711 | reg = FDI_RX_IIR(pipe); |
2698 | temp = I915_READ(reg); |
2712 | temp = I915_READ(reg); |
2699 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2713 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2700 | 2714 | ||
2701 | if (temp & FDI_RX_SYMBOL_LOCK || |
2715 | if (temp & FDI_RX_SYMBOL_LOCK || |
2702 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2716 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2703 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2717 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2704 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2718 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2705 | i); |
2719 | i); |
2706 | goto train_done; |
2720 | goto train_done; |
2707 | } |
2721 | } |
2708 | udelay(2); /* should be 1.5us */ |
2722 | udelay(2); /* should be 1.5us */ |
2709 | } |
2723 | } |
2710 | if (i == 4) |
2724 | if (i == 4) |
2711 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2725 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2712 | } |
2726 | } |
2713 | 2727 | ||
2714 | train_done: |
2728 | train_done: |
2715 | DRM_DEBUG_KMS("FDI train done.\n"); |
2729 | DRM_DEBUG_KMS("FDI train done.\n"); |
2716 | } |
2730 | } |
2717 | 2731 | ||
2718 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2732 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2719 | { |
2733 | { |
2720 | struct drm_device *dev = intel_crtc->base.dev; |
2734 | struct drm_device *dev = intel_crtc->base.dev; |
2721 | struct drm_i915_private *dev_priv = dev->dev_private; |
2735 | struct drm_i915_private *dev_priv = dev->dev_private; |
2722 | int pipe = intel_crtc->pipe; |
2736 | int pipe = intel_crtc->pipe; |
2723 | u32 reg, temp; |
2737 | u32 reg, temp; |
2724 | 2738 | ||
2725 | 2739 | ||
2726 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2740 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2727 | reg = FDI_RX_CTL(pipe); |
2741 | reg = FDI_RX_CTL(pipe); |
2728 | temp = I915_READ(reg); |
2742 | temp = I915_READ(reg); |
2729 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2743 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2730 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2744 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2731 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2745 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2732 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2746 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2733 | 2747 | ||
2734 | POSTING_READ(reg); |
2748 | POSTING_READ(reg); |
2735 | udelay(200); |
2749 | udelay(200); |
2736 | 2750 | ||
2737 | /* Switch from Rawclk to PCDclk */ |
2751 | /* Switch from Rawclk to PCDclk */ |
2738 | temp = I915_READ(reg); |
2752 | temp = I915_READ(reg); |
2739 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2753 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2740 | 2754 | ||
2741 | POSTING_READ(reg); |
2755 | POSTING_READ(reg); |
2742 | udelay(200); |
2756 | udelay(200); |
2743 | 2757 | ||
2744 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2758 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2745 | reg = FDI_TX_CTL(pipe); |
2759 | reg = FDI_TX_CTL(pipe); |
2746 | temp = I915_READ(reg); |
2760 | temp = I915_READ(reg); |
2747 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2761 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2748 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2762 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2749 | 2763 | ||
2750 | POSTING_READ(reg); |
2764 | POSTING_READ(reg); |
2751 | udelay(100); |
2765 | udelay(100); |
2752 | } |
2766 | } |
2753 | } |
2767 | } |
2754 | 2768 | ||
2755 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2769 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2756 | { |
2770 | { |
2757 | struct drm_device *dev = intel_crtc->base.dev; |
2771 | struct drm_device *dev = intel_crtc->base.dev; |
2758 | struct drm_i915_private *dev_priv = dev->dev_private; |
2772 | struct drm_i915_private *dev_priv = dev->dev_private; |
2759 | int pipe = intel_crtc->pipe; |
2773 | int pipe = intel_crtc->pipe; |
2760 | u32 reg, temp; |
2774 | u32 reg, temp; |
2761 | 2775 | ||
2762 | /* Switch from PCDclk to Rawclk */ |
2776 | /* Switch from PCDclk to Rawclk */ |
2763 | reg = FDI_RX_CTL(pipe); |
2777 | reg = FDI_RX_CTL(pipe); |
2764 | temp = I915_READ(reg); |
2778 | temp = I915_READ(reg); |
2765 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2779 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2766 | 2780 | ||
2767 | /* Disable CPU FDI TX PLL */ |
2781 | /* Disable CPU FDI TX PLL */ |
2768 | reg = FDI_TX_CTL(pipe); |
2782 | reg = FDI_TX_CTL(pipe); |
2769 | temp = I915_READ(reg); |
2783 | temp = I915_READ(reg); |
2770 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2784 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2771 | 2785 | ||
2772 | POSTING_READ(reg); |
2786 | POSTING_READ(reg); |
2773 | udelay(100); |
2787 | udelay(100); |
2774 | 2788 | ||
2775 | reg = FDI_RX_CTL(pipe); |
2789 | reg = FDI_RX_CTL(pipe); |
2776 | temp = I915_READ(reg); |
2790 | temp = I915_READ(reg); |
2777 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2791 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2778 | 2792 | ||
2779 | /* Wait for the clocks to turn off. */ |
2793 | /* Wait for the clocks to turn off. */ |
2780 | POSTING_READ(reg); |
2794 | POSTING_READ(reg); |
2781 | udelay(100); |
2795 | udelay(100); |
2782 | } |
2796 | } |
2783 | 2797 | ||
2784 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2798 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2785 | { |
2799 | { |
2786 | struct drm_device *dev = crtc->dev; |
2800 | struct drm_device *dev = crtc->dev; |
2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
2801 | struct drm_i915_private *dev_priv = dev->dev_private; |
2788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2789 | int pipe = intel_crtc->pipe; |
2803 | int pipe = intel_crtc->pipe; |
2790 | u32 reg, temp; |
2804 | u32 reg, temp; |
2791 | 2805 | ||
2792 | /* disable CPU FDI tx and PCH FDI rx */ |
2806 | /* disable CPU FDI tx and PCH FDI rx */ |
2793 | reg = FDI_TX_CTL(pipe); |
2807 | reg = FDI_TX_CTL(pipe); |
2794 | temp = I915_READ(reg); |
2808 | temp = I915_READ(reg); |
2795 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2809 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2796 | POSTING_READ(reg); |
2810 | POSTING_READ(reg); |
2797 | 2811 | ||
2798 | reg = FDI_RX_CTL(pipe); |
2812 | reg = FDI_RX_CTL(pipe); |
2799 | temp = I915_READ(reg); |
2813 | temp = I915_READ(reg); |
2800 | temp &= ~(0x7 << 16); |
2814 | temp &= ~(0x7 << 16); |
2801 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2815 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2802 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2816 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2803 | 2817 | ||
2804 | POSTING_READ(reg); |
2818 | POSTING_READ(reg); |
2805 | udelay(100); |
2819 | udelay(100); |
2806 | 2820 | ||
2807 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2821 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2808 | if (HAS_PCH_IBX(dev)) { |
2822 | if (HAS_PCH_IBX(dev)) { |
2809 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2823 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2810 | } |
2824 | } |
2811 | 2825 | ||
2812 | /* still set train pattern 1 */ |
2826 | /* still set train pattern 1 */ |
2813 | reg = FDI_TX_CTL(pipe); |
2827 | reg = FDI_TX_CTL(pipe); |
2814 | temp = I915_READ(reg); |
2828 | temp = I915_READ(reg); |
2815 | temp &= ~FDI_LINK_TRAIN_NONE; |
2829 | temp &= ~FDI_LINK_TRAIN_NONE; |
2816 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2830 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2817 | I915_WRITE(reg, temp); |
2831 | I915_WRITE(reg, temp); |
2818 | 2832 | ||
2819 | reg = FDI_RX_CTL(pipe); |
2833 | reg = FDI_RX_CTL(pipe); |
2820 | temp = I915_READ(reg); |
2834 | temp = I915_READ(reg); |
2821 | if (HAS_PCH_CPT(dev)) { |
2835 | if (HAS_PCH_CPT(dev)) { |
2822 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2836 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2823 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2837 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2824 | } else { |
2838 | } else { |
2825 | temp &= ~FDI_LINK_TRAIN_NONE; |
2839 | temp &= ~FDI_LINK_TRAIN_NONE; |
2826 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2840 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2827 | } |
2841 | } |
2828 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2842 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2829 | temp &= ~(0x07 << 16); |
2843 | temp &= ~(0x07 << 16); |
2830 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2844 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2831 | I915_WRITE(reg, temp); |
2845 | I915_WRITE(reg, temp); |
2832 | 2846 | ||
2833 | POSTING_READ(reg); |
2847 | POSTING_READ(reg); |
2834 | udelay(100); |
2848 | udelay(100); |
2835 | } |
2849 | } |
2836 | 2850 | ||
2837 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2851 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2838 | { |
2852 | { |
2839 | struct drm_device *dev = crtc->dev; |
2853 | struct drm_device *dev = crtc->dev; |
2840 | struct drm_i915_private *dev_priv = dev->dev_private; |
2854 | struct drm_i915_private *dev_priv = dev->dev_private; |
2841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2842 | unsigned long flags; |
2856 | unsigned long flags; |
2843 | bool pending; |
2857 | bool pending; |
2844 | 2858 | ||
2845 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2859 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2846 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2860 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2847 | return false; |
2861 | return false; |
2848 | 2862 | ||
2849 | spin_lock_irqsave(&dev->event_lock, flags); |
2863 | spin_lock_irqsave(&dev->event_lock, flags); |
2850 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2864 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2851 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2865 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2852 | 2866 | ||
2853 | return pending; |
2867 | return pending; |
2854 | } |
2868 | } |
2855 | 2869 | ||
2856 | #if 0 |
2870 | #if 0 |
2857 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2871 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2858 | { |
2872 | { |
2859 | struct drm_device *dev = crtc->dev; |
2873 | struct drm_device *dev = crtc->dev; |
2860 | struct drm_i915_private *dev_priv = dev->dev_private; |
2874 | struct drm_i915_private *dev_priv = dev->dev_private; |
2861 | 2875 | ||
2862 | if (crtc->fb == NULL) |
2876 | if (crtc->fb == NULL) |
2863 | return; |
2877 | return; |
2864 | 2878 | ||
2865 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2879 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2866 | 2880 | ||
2867 | wait_event(dev_priv->pending_flip_queue, |
2881 | wait_event(dev_priv->pending_flip_queue, |
2868 | !intel_crtc_has_pending_flip(crtc)); |
2882 | !intel_crtc_has_pending_flip(crtc)); |
2869 | 2883 | ||
2870 | mutex_lock(&dev->struct_mutex); |
2884 | mutex_lock(&dev->struct_mutex); |
2871 | intel_finish_fb(crtc->fb); |
2885 | intel_finish_fb(crtc->fb); |
2872 | mutex_unlock(&dev->struct_mutex); |
2886 | mutex_unlock(&dev->struct_mutex); |
2873 | } |
2887 | } |
2874 | #endif |
2888 | #endif |
2875 | 2889 | ||
2876 | /* Program iCLKIP clock to the desired frequency */ |
2890 | /* Program iCLKIP clock to the desired frequency */ |
2877 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2891 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2878 | { |
2892 | { |
2879 | struct drm_device *dev = crtc->dev; |
2893 | struct drm_device *dev = crtc->dev; |
2880 | struct drm_i915_private *dev_priv = dev->dev_private; |
2894 | struct drm_i915_private *dev_priv = dev->dev_private; |
2881 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2895 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2882 | u32 temp; |
2896 | u32 temp; |
2883 | 2897 | ||
2884 | mutex_lock(&dev_priv->dpio_lock); |
2898 | mutex_lock(&dev_priv->dpio_lock); |
2885 | 2899 | ||
2886 | /* It is necessary to ungate the pixclk gate prior to programming |
2900 | /* It is necessary to ungate the pixclk gate prior to programming |
2887 | * the divisors, and gate it back when it is done. |
2901 | * the divisors, and gate it back when it is done. |
2888 | */ |
2902 | */ |
2889 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2903 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2890 | 2904 | ||
2891 | /* Disable SSCCTL */ |
2905 | /* Disable SSCCTL */ |
2892 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2906 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2893 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2907 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2894 | SBI_SSCCTL_DISABLE, |
2908 | SBI_SSCCTL_DISABLE, |
2895 | SBI_ICLK); |
2909 | SBI_ICLK); |
2896 | 2910 | ||
2897 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2911 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2898 | if (crtc->mode.clock == 20000) { |
2912 | if (crtc->mode.clock == 20000) { |
2899 | auxdiv = 1; |
2913 | auxdiv = 1; |
2900 | divsel = 0x41; |
2914 | divsel = 0x41; |
2901 | phaseinc = 0x20; |
2915 | phaseinc = 0x20; |
2902 | } else { |
2916 | } else { |
2903 | /* The iCLK virtual clock root frequency is in MHz, |
2917 | /* The iCLK virtual clock root frequency is in MHz, |
2904 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2918 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2905 | * it is necessary to divide one by another, so we |
2919 | * it is necessary to divide one by another, so we |
2906 | * convert the virtual clock precision to KHz here for higher |
2920 | * convert the virtual clock precision to KHz here for higher |
2907 | * precision. |
2921 | * precision. |
2908 | */ |
2922 | */ |
2909 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2923 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2910 | u32 iclk_pi_range = 64; |
2924 | u32 iclk_pi_range = 64; |
2911 | u32 desired_divisor, msb_divisor_value, pi_value; |
2925 | u32 desired_divisor, msb_divisor_value, pi_value; |
2912 | 2926 | ||
2913 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2927 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2914 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2928 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2915 | pi_value = desired_divisor % iclk_pi_range; |
2929 | pi_value = desired_divisor % iclk_pi_range; |
2916 | 2930 | ||
2917 | auxdiv = 0; |
2931 | auxdiv = 0; |
2918 | divsel = msb_divisor_value - 2; |
2932 | divsel = msb_divisor_value - 2; |
2919 | phaseinc = pi_value; |
2933 | phaseinc = pi_value; |
2920 | } |
2934 | } |
2921 | 2935 | ||
2922 | /* This should not happen with any sane values */ |
2936 | /* This should not happen with any sane values */ |
2923 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2937 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2924 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2938 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2925 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2939 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2926 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2940 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2927 | 2941 | ||
2928 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2942 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2929 | crtc->mode.clock, |
2943 | crtc->mode.clock, |
2930 | auxdiv, |
2944 | auxdiv, |
2931 | divsel, |
2945 | divsel, |
2932 | phasedir, |
2946 | phasedir, |
2933 | phaseinc); |
2947 | phaseinc); |
2934 | 2948 | ||
2935 | /* Program SSCDIVINTPHASE6 */ |
2949 | /* Program SSCDIVINTPHASE6 */ |
2936 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
2950 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
2937 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2951 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2938 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2952 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2939 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2953 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2940 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2954 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2941 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2955 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2942 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2956 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2943 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
2957 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
2944 | 2958 | ||
2945 | /* Program SSCAUXDIV */ |
2959 | /* Program SSCAUXDIV */ |
2946 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
2960 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
2947 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2961 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2948 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2962 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2949 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
2963 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
2950 | 2964 | ||
2951 | /* Enable modulator and associated divider */ |
2965 | /* Enable modulator and associated divider */ |
2952 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
2966 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
2953 | temp &= ~SBI_SSCCTL_DISABLE; |
2967 | temp &= ~SBI_SSCCTL_DISABLE; |
2954 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
2968 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
2955 | 2969 | ||
2956 | /* Wait for initialization time */ |
2970 | /* Wait for initialization time */ |
2957 | udelay(24); |
2971 | udelay(24); |
2958 | 2972 | ||
2959 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2973 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2960 | 2974 | ||
2961 | mutex_unlock(&dev_priv->dpio_lock); |
2975 | mutex_unlock(&dev_priv->dpio_lock); |
2962 | } |
2976 | } |
2963 | 2977 | ||
2964 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2978 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2965 | enum pipe pch_transcoder) |
2979 | enum pipe pch_transcoder) |
2966 | { |
2980 | { |
2967 | struct drm_device *dev = crtc->base.dev; |
2981 | struct drm_device *dev = crtc->base.dev; |
2968 | struct drm_i915_private *dev_priv = dev->dev_private; |
2982 | struct drm_i915_private *dev_priv = dev->dev_private; |
2969 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
2983 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
2970 | 2984 | ||
2971 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
2985 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
2972 | I915_READ(HTOTAL(cpu_transcoder))); |
2986 | I915_READ(HTOTAL(cpu_transcoder))); |
2973 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
2987 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
2974 | I915_READ(HBLANK(cpu_transcoder))); |
2988 | I915_READ(HBLANK(cpu_transcoder))); |
2975 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
2989 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
2976 | I915_READ(HSYNC(cpu_transcoder))); |
2990 | I915_READ(HSYNC(cpu_transcoder))); |
2977 | 2991 | ||
2978 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
2992 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
2979 | I915_READ(VTOTAL(cpu_transcoder))); |
2993 | I915_READ(VTOTAL(cpu_transcoder))); |
2980 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
2994 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
2981 | I915_READ(VBLANK(cpu_transcoder))); |
2995 | I915_READ(VBLANK(cpu_transcoder))); |
2982 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
2996 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
2983 | I915_READ(VSYNC(cpu_transcoder))); |
2997 | I915_READ(VSYNC(cpu_transcoder))); |
2984 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2998 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2985 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2999 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2986 | } |
3000 | } |
2987 | 3001 | ||
2988 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3002 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
2989 | { |
3003 | { |
2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
3004 | struct drm_i915_private *dev_priv = dev->dev_private; |
2991 | uint32_t temp; |
3005 | uint32_t temp; |
2992 | 3006 | ||
2993 | temp = I915_READ(SOUTH_CHICKEN1); |
3007 | temp = I915_READ(SOUTH_CHICKEN1); |
2994 | if (temp & FDI_BC_BIFURCATION_SELECT) |
3008 | if (temp & FDI_BC_BIFURCATION_SELECT) |
2995 | return; |
3009 | return; |
2996 | 3010 | ||
2997 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3011 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2998 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
3012 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2999 | 3013 | ||
3000 | temp |= FDI_BC_BIFURCATION_SELECT; |
3014 | temp |= FDI_BC_BIFURCATION_SELECT; |
3001 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
3015 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
3002 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3016 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3003 | POSTING_READ(SOUTH_CHICKEN1); |
3017 | POSTING_READ(SOUTH_CHICKEN1); |
3004 | } |
3018 | } |
3005 | 3019 | ||
3006 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
3020 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
3007 | { |
3021 | { |
3008 | struct drm_device *dev = intel_crtc->base.dev; |
3022 | struct drm_device *dev = intel_crtc->base.dev; |
3009 | struct drm_i915_private *dev_priv = dev->dev_private; |
3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
3010 | 3024 | ||
3011 | switch (intel_crtc->pipe) { |
3025 | switch (intel_crtc->pipe) { |
3012 | case PIPE_A: |
3026 | case PIPE_A: |
3013 | break; |
3027 | break; |
3014 | case PIPE_B: |
3028 | case PIPE_B: |
3015 | if (intel_crtc->config.fdi_lanes > 2) |
3029 | if (intel_crtc->config.fdi_lanes > 2) |
3016 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3030 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3017 | else |
3031 | else |
3018 | cpt_enable_fdi_bc_bifurcation(dev); |
3032 | cpt_enable_fdi_bc_bifurcation(dev); |
3019 | 3033 | ||
3020 | break; |
3034 | break; |
3021 | case PIPE_C: |
3035 | case PIPE_C: |
3022 | cpt_enable_fdi_bc_bifurcation(dev); |
3036 | cpt_enable_fdi_bc_bifurcation(dev); |
3023 | 3037 | ||
3024 | break; |
3038 | break; |
3025 | default: |
3039 | default: |
3026 | BUG(); |
3040 | BUG(); |
3027 | } |
3041 | } |
3028 | } |
3042 | } |
3029 | 3043 | ||
3030 | /* |
3044 | /* |
3031 | * Enable PCH resources required for PCH ports: |
3045 | * Enable PCH resources required for PCH ports: |
3032 | * - PCH PLLs |
3046 | * - PCH PLLs |
3033 | * - FDI training & RX/TX |
3047 | * - FDI training & RX/TX |
3034 | * - update transcoder timings |
3048 | * - update transcoder timings |
3035 | * - DP transcoding bits |
3049 | * - DP transcoding bits |
3036 | * - transcoder |
3050 | * - transcoder |
3037 | */ |
3051 | */ |
3038 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3052 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3039 | { |
3053 | { |
3040 | struct drm_device *dev = crtc->dev; |
3054 | struct drm_device *dev = crtc->dev; |
3041 | struct drm_i915_private *dev_priv = dev->dev_private; |
3055 | struct drm_i915_private *dev_priv = dev->dev_private; |
3042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3043 | int pipe = intel_crtc->pipe; |
3057 | int pipe = intel_crtc->pipe; |
3044 | u32 reg, temp; |
3058 | u32 reg, temp; |
3045 | 3059 | ||
3046 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3060 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3047 | 3061 | ||
3048 | if (IS_IVYBRIDGE(dev)) |
3062 | if (IS_IVYBRIDGE(dev)) |
3049 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
3063 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
3050 | 3064 | ||
3051 | /* Write the TU size bits before fdi link training, so that error |
3065 | /* Write the TU size bits before fdi link training, so that error |
3052 | * detection works. */ |
3066 | * detection works. */ |
3053 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3067 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3054 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3068 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3055 | 3069 | ||
3056 | /* For PCH output, training FDI link */ |
3070 | /* For PCH output, training FDI link */ |
3057 | dev_priv->display.fdi_link_train(crtc); |
3071 | dev_priv->display.fdi_link_train(crtc); |
3058 | 3072 | ||
3059 | /* We need to program the right clock selection before writing the pixel |
3073 | /* We need to program the right clock selection before writing the pixel |
3060 | * mutliplier into the DPLL. */ |
3074 | * mutliplier into the DPLL. */ |
3061 | if (HAS_PCH_CPT(dev)) { |
3075 | if (HAS_PCH_CPT(dev)) { |
3062 | u32 sel; |
3076 | u32 sel; |
3063 | 3077 | ||
3064 | temp = I915_READ(PCH_DPLL_SEL); |
3078 | temp = I915_READ(PCH_DPLL_SEL); |
3065 | temp |= TRANS_DPLL_ENABLE(pipe); |
3079 | temp |= TRANS_DPLL_ENABLE(pipe); |
3066 | sel = TRANS_DPLLB_SEL(pipe); |
3080 | sel = TRANS_DPLLB_SEL(pipe); |
3067 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3081 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3068 | temp |= sel; |
3082 | temp |= sel; |
3069 | else |
3083 | else |
3070 | temp &= ~sel; |
3084 | temp &= ~sel; |
3071 | I915_WRITE(PCH_DPLL_SEL, temp); |
3085 | I915_WRITE(PCH_DPLL_SEL, temp); |
3072 | } |
3086 | } |
3073 | 3087 | ||
3074 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3088 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3075 | * transcoder, and we actually should do this to not upset any PCH |
3089 | * transcoder, and we actually should do this to not upset any PCH |
3076 | * transcoder that already use the clock when we share it. |
3090 | * transcoder that already use the clock when we share it. |
3077 | * |
3091 | * |
3078 | * Note that enable_shared_dpll tries to do the right thing, but |
3092 | * Note that enable_shared_dpll tries to do the right thing, but |
3079 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3093 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3080 | * the right LVDS enable sequence. */ |
3094 | * the right LVDS enable sequence. */ |
3081 | ironlake_enable_shared_dpll(intel_crtc); |
3095 | ironlake_enable_shared_dpll(intel_crtc); |
3082 | 3096 | ||
3083 | /* set transcoder timing, panel must allow it */ |
3097 | /* set transcoder timing, panel must allow it */ |
3084 | assert_panel_unlocked(dev_priv, pipe); |
3098 | assert_panel_unlocked(dev_priv, pipe); |
3085 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3099 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3086 | 3100 | ||
3087 | intel_fdi_normal_train(crtc); |
3101 | intel_fdi_normal_train(crtc); |
3088 | 3102 | ||
3089 | /* For PCH DP, enable TRANS_DP_CTL */ |
3103 | /* For PCH DP, enable TRANS_DP_CTL */ |
3090 | if (HAS_PCH_CPT(dev) && |
3104 | if (HAS_PCH_CPT(dev) && |
3091 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3105 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3092 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3106 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3093 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3107 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3094 | reg = TRANS_DP_CTL(pipe); |
3108 | reg = TRANS_DP_CTL(pipe); |
3095 | temp = I915_READ(reg); |
3109 | temp = I915_READ(reg); |
3096 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3110 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3097 | TRANS_DP_SYNC_MASK | |
3111 | TRANS_DP_SYNC_MASK | |
3098 | TRANS_DP_BPC_MASK); |
3112 | TRANS_DP_BPC_MASK); |
3099 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3113 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3100 | TRANS_DP_ENH_FRAMING); |
3114 | TRANS_DP_ENH_FRAMING); |
3101 | temp |= bpc << 9; /* same format but at 11:9 */ |
3115 | temp |= bpc << 9; /* same format but at 11:9 */ |
3102 | 3116 | ||
3103 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3117 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3104 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3118 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3105 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3119 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3106 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3120 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3107 | 3121 | ||
3108 | switch (intel_trans_dp_port_sel(crtc)) { |
3122 | switch (intel_trans_dp_port_sel(crtc)) { |
3109 | case PCH_DP_B: |
3123 | case PCH_DP_B: |
3110 | temp |= TRANS_DP_PORT_SEL_B; |
3124 | temp |= TRANS_DP_PORT_SEL_B; |
3111 | break; |
3125 | break; |
3112 | case PCH_DP_C: |
3126 | case PCH_DP_C: |
3113 | temp |= TRANS_DP_PORT_SEL_C; |
3127 | temp |= TRANS_DP_PORT_SEL_C; |
3114 | break; |
3128 | break; |
3115 | case PCH_DP_D: |
3129 | case PCH_DP_D: |
3116 | temp |= TRANS_DP_PORT_SEL_D; |
3130 | temp |= TRANS_DP_PORT_SEL_D; |
3117 | break; |
3131 | break; |
3118 | default: |
3132 | default: |
3119 | BUG(); |
3133 | BUG(); |
3120 | } |
3134 | } |
3121 | 3135 | ||
3122 | I915_WRITE(reg, temp); |
3136 | I915_WRITE(reg, temp); |
3123 | } |
3137 | } |
3124 | 3138 | ||
3125 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3139 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3126 | } |
3140 | } |
3127 | 3141 | ||
3128 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3142 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3129 | { |
3143 | { |
3130 | struct drm_device *dev = crtc->dev; |
3144 | struct drm_device *dev = crtc->dev; |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; |
3145 | struct drm_i915_private *dev_priv = dev->dev_private; |
3132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3133 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3147 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3134 | 3148 | ||
3135 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3149 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3136 | 3150 | ||
3137 | lpt_program_iclkip(crtc); |
3151 | lpt_program_iclkip(crtc); |
3138 | 3152 | ||
3139 | /* Set transcoder timing. */ |
3153 | /* Set transcoder timing. */ |
3140 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3154 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3141 | 3155 | ||
3142 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3156 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3143 | } |
3157 | } |
3144 | 3158 | ||
3145 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3159 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3146 | { |
3160 | { |
3147 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3161 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3148 | 3162 | ||
3149 | if (pll == NULL) |
3163 | if (pll == NULL) |
3150 | return; |
3164 | return; |
3151 | 3165 | ||
3152 | if (pll->refcount == 0) { |
3166 | if (pll->refcount == 0) { |
3153 | WARN(1, "bad %s refcount\n", pll->name); |
3167 | WARN(1, "bad %s refcount\n", pll->name); |
3154 | return; |
3168 | return; |
3155 | } |
3169 | } |
3156 | 3170 | ||
3157 | if (--pll->refcount == 0) { |
3171 | if (--pll->refcount == 0) { |
3158 | WARN_ON(pll->on); |
3172 | WARN_ON(pll->on); |
3159 | WARN_ON(pll->active); |
3173 | WARN_ON(pll->active); |
3160 | } |
3174 | } |
3161 | 3175 | ||
3162 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3176 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3163 | } |
3177 | } |
3164 | 3178 | ||
3165 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3179 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3166 | { |
3180 | { |
3167 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3181 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3168 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3182 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3169 | enum intel_dpll_id i; |
3183 | enum intel_dpll_id i; |
3170 | 3184 | ||
3171 | if (pll) { |
3185 | if (pll) { |
3172 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3186 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3173 | crtc->base.base.id, pll->name); |
3187 | crtc->base.base.id, pll->name); |
3174 | intel_put_shared_dpll(crtc); |
3188 | intel_put_shared_dpll(crtc); |
3175 | } |
3189 | } |
3176 | 3190 | ||
3177 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3191 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3178 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3192 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3179 | i = (enum intel_dpll_id) crtc->pipe; |
3193 | i = (enum intel_dpll_id) crtc->pipe; |
3180 | pll = &dev_priv->shared_dplls[i]; |
3194 | pll = &dev_priv->shared_dplls[i]; |
3181 | 3195 | ||
3182 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3196 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3183 | crtc->base.base.id, pll->name); |
3197 | crtc->base.base.id, pll->name); |
3184 | 3198 | ||
3185 | goto found; |
3199 | goto found; |
3186 | } |
3200 | } |
3187 | 3201 | ||
3188 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3202 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3189 | pll = &dev_priv->shared_dplls[i]; |
3203 | pll = &dev_priv->shared_dplls[i]; |
3190 | 3204 | ||
3191 | /* Only want to check enabled timings first */ |
3205 | /* Only want to check enabled timings first */ |
3192 | if (pll->refcount == 0) |
3206 | if (pll->refcount == 0) |
3193 | continue; |
3207 | continue; |
3194 | 3208 | ||
3195 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3209 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3196 | sizeof(pll->hw_state)) == 0) { |
3210 | sizeof(pll->hw_state)) == 0) { |
3197 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3211 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3198 | crtc->base.base.id, |
3212 | crtc->base.base.id, |
3199 | pll->name, pll->refcount, pll->active); |
3213 | pll->name, pll->refcount, pll->active); |
3200 | 3214 | ||
3201 | goto found; |
3215 | goto found; |
3202 | } |
3216 | } |
3203 | } |
3217 | } |
3204 | 3218 | ||
3205 | /* Ok no matching timings, maybe there's a free one? */ |
3219 | /* Ok no matching timings, maybe there's a free one? */ |
3206 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3220 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3207 | pll = &dev_priv->shared_dplls[i]; |
3221 | pll = &dev_priv->shared_dplls[i]; |
3208 | if (pll->refcount == 0) { |
3222 | if (pll->refcount == 0) { |
3209 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3223 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3210 | crtc->base.base.id, pll->name); |
3224 | crtc->base.base.id, pll->name); |
3211 | goto found; |
3225 | goto found; |
3212 | } |
3226 | } |
3213 | } |
3227 | } |
3214 | 3228 | ||
3215 | return NULL; |
3229 | return NULL; |
3216 | 3230 | ||
3217 | found: |
3231 | found: |
3218 | crtc->config.shared_dpll = i; |
3232 | crtc->config.shared_dpll = i; |
3219 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3233 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3220 | pipe_name(crtc->pipe)); |
3234 | pipe_name(crtc->pipe)); |
3221 | 3235 | ||
3222 | if (pll->active == 0) { |
3236 | if (pll->active == 0) { |
3223 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3237 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3224 | sizeof(pll->hw_state)); |
3238 | sizeof(pll->hw_state)); |
3225 | 3239 | ||
3226 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
3240 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
3227 | WARN_ON(pll->on); |
3241 | WARN_ON(pll->on); |
3228 | assert_shared_dpll_disabled(dev_priv, pll); |
3242 | assert_shared_dpll_disabled(dev_priv, pll); |
3229 | 3243 | ||
3230 | pll->mode_set(dev_priv, pll); |
3244 | pll->mode_set(dev_priv, pll); |
3231 | } |
3245 | } |
3232 | pll->refcount++; |
3246 | pll->refcount++; |
3233 | 3247 | ||
3234 | return pll; |
3248 | return pll; |
3235 | } |
3249 | } |
3236 | 3250 | ||
3237 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3251 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3238 | { |
3252 | { |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; |
3253 | struct drm_i915_private *dev_priv = dev->dev_private; |
3240 | int dslreg = PIPEDSL(pipe); |
3254 | int dslreg = PIPEDSL(pipe); |
3241 | u32 temp; |
3255 | u32 temp; |
3242 | 3256 | ||
3243 | temp = I915_READ(dslreg); |
3257 | temp = I915_READ(dslreg); |
3244 | udelay(500); |
3258 | udelay(500); |
3245 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3259 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3246 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3260 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3247 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3261 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3248 | } |
3262 | } |
3249 | } |
3263 | } |
3250 | 3264 | ||
3251 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3265 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3252 | { |
3266 | { |
3253 | struct drm_device *dev = crtc->base.dev; |
3267 | struct drm_device *dev = crtc->base.dev; |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
3268 | struct drm_i915_private *dev_priv = dev->dev_private; |
3255 | int pipe = crtc->pipe; |
3269 | int pipe = crtc->pipe; |
3256 | 3270 | ||
3257 | if (crtc->config.pch_pfit.enabled) { |
3271 | if (crtc->config.pch_pfit.enabled) { |
3258 | /* Force use of hard-coded filter coefficients |
3272 | /* Force use of hard-coded filter coefficients |
3259 | * as some pre-programmed values are broken, |
3273 | * as some pre-programmed values are broken, |
3260 | * e.g. x201. |
3274 | * e.g. x201. |
3261 | */ |
3275 | */ |
3262 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3276 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3263 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3277 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3264 | PF_PIPE_SEL_IVB(pipe)); |
3278 | PF_PIPE_SEL_IVB(pipe)); |
3265 | else |
3279 | else |
3266 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3280 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3267 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3281 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3268 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3282 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3269 | } |
3283 | } |
3270 | } |
3284 | } |
3271 | 3285 | ||
3272 | static void intel_enable_planes(struct drm_crtc *crtc) |
3286 | static void intel_enable_planes(struct drm_crtc *crtc) |
3273 | { |
3287 | { |
3274 | struct drm_device *dev = crtc->dev; |
3288 | struct drm_device *dev = crtc->dev; |
3275 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3289 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3276 | struct intel_plane *intel_plane; |
3290 | struct intel_plane *intel_plane; |
3277 | 3291 | ||
3278 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3292 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3279 | if (intel_plane->pipe == pipe) |
3293 | if (intel_plane->pipe == pipe) |
3280 | intel_plane_restore(&intel_plane->base); |
3294 | intel_plane_restore(&intel_plane->base); |
3281 | } |
3295 | } |
3282 | 3296 | ||
3283 | static void intel_disable_planes(struct drm_crtc *crtc) |
3297 | static void intel_disable_planes(struct drm_crtc *crtc) |
3284 | { |
3298 | { |
3285 | struct drm_device *dev = crtc->dev; |
3299 | struct drm_device *dev = crtc->dev; |
3286 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3300 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3287 | struct intel_plane *intel_plane; |
3301 | struct intel_plane *intel_plane; |
3288 | 3302 | ||
3289 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3303 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3290 | if (intel_plane->pipe == pipe) |
3304 | if (intel_plane->pipe == pipe) |
3291 | intel_plane_disable(&intel_plane->base); |
3305 | intel_plane_disable(&intel_plane->base); |
3292 | } |
3306 | } |
3293 | 3307 | ||
3294 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3308 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3295 | { |
3309 | { |
3296 | struct drm_device *dev = crtc->dev; |
3310 | struct drm_device *dev = crtc->dev; |
3297 | struct drm_i915_private *dev_priv = dev->dev_private; |
3311 | struct drm_i915_private *dev_priv = dev->dev_private; |
3298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3299 | struct intel_encoder *encoder; |
3313 | struct intel_encoder *encoder; |
3300 | int pipe = intel_crtc->pipe; |
3314 | int pipe = intel_crtc->pipe; |
3301 | int plane = intel_crtc->plane; |
3315 | int plane = intel_crtc->plane; |
3302 | 3316 | ||
3303 | WARN_ON(!crtc->enabled); |
3317 | WARN_ON(!crtc->enabled); |
3304 | 3318 | ||
3305 | if (intel_crtc->active) |
3319 | if (intel_crtc->active) |
3306 | return; |
3320 | return; |
3307 | 3321 | ||
3308 | intel_crtc->active = true; |
3322 | intel_crtc->active = true; |
3309 | 3323 | ||
3310 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3324 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3311 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3325 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3312 | 3326 | ||
3313 | intel_update_watermarks(dev); |
3327 | intel_update_watermarks(dev); |
3314 | 3328 | ||
3315 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3329 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3316 | if (encoder->pre_enable) |
3330 | if (encoder->pre_enable) |
3317 | encoder->pre_enable(encoder); |
3331 | encoder->pre_enable(encoder); |
3318 | 3332 | ||
3319 | if (intel_crtc->config.has_pch_encoder) { |
3333 | if (intel_crtc->config.has_pch_encoder) { |
3320 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3334 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3321 | * cpu pipes, hence this is separate from all the other fdi/pch |
3335 | * cpu pipes, hence this is separate from all the other fdi/pch |
3322 | * enabling. */ |
3336 | * enabling. */ |
3323 | ironlake_fdi_pll_enable(intel_crtc); |
3337 | ironlake_fdi_pll_enable(intel_crtc); |
3324 | } else { |
3338 | } else { |
3325 | assert_fdi_tx_disabled(dev_priv, pipe); |
3339 | assert_fdi_tx_disabled(dev_priv, pipe); |
3326 | assert_fdi_rx_disabled(dev_priv, pipe); |
3340 | assert_fdi_rx_disabled(dev_priv, pipe); |
3327 | } |
3341 | } |
3328 | 3342 | ||
3329 | ironlake_pfit_enable(intel_crtc); |
3343 | ironlake_pfit_enable(intel_crtc); |
3330 | 3344 | ||
3331 | /* |
3345 | /* |
3332 | * On ILK+ LUT must be loaded before the pipe is running but with |
3346 | * On ILK+ LUT must be loaded before the pipe is running but with |
3333 | * clocks enabled |
3347 | * clocks enabled |
3334 | */ |
3348 | */ |
3335 | intel_crtc_load_lut(crtc); |
3349 | intel_crtc_load_lut(crtc); |
3336 | 3350 | ||
3337 | intel_enable_pipe(dev_priv, pipe, |
3351 | intel_enable_pipe(dev_priv, pipe, |
3338 | intel_crtc->config.has_pch_encoder); |
3352 | intel_crtc->config.has_pch_encoder); |
3339 | intel_enable_plane(dev_priv, plane, pipe); |
3353 | intel_enable_plane(dev_priv, plane, pipe); |
3340 | intel_enable_planes(crtc); |
3354 | intel_enable_planes(crtc); |
3341 | // intel_crtc_update_cursor(crtc, true); |
3355 | // intel_crtc_update_cursor(crtc, true); |
3342 | 3356 | ||
3343 | if (intel_crtc->config.has_pch_encoder) |
3357 | if (intel_crtc->config.has_pch_encoder) |
3344 | ironlake_pch_enable(crtc); |
3358 | ironlake_pch_enable(crtc); |
3345 | 3359 | ||
3346 | mutex_lock(&dev->struct_mutex); |
3360 | mutex_lock(&dev->struct_mutex); |
3347 | intel_update_fbc(dev); |
3361 | intel_update_fbc(dev); |
3348 | mutex_unlock(&dev->struct_mutex); |
3362 | mutex_unlock(&dev->struct_mutex); |
3349 | 3363 | ||
3350 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3364 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3351 | encoder->enable(encoder); |
3365 | encoder->enable(encoder); |
3352 | 3366 | ||
3353 | if (HAS_PCH_CPT(dev)) |
3367 | if (HAS_PCH_CPT(dev)) |
3354 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3368 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3355 | 3369 | ||
3356 | /* |
3370 | /* |
3357 | * There seems to be a race in PCH platform hw (at least on some |
3371 | * There seems to be a race in PCH platform hw (at least on some |
3358 | * outputs) where an enabled pipe still completes any pageflip right |
3372 | * outputs) where an enabled pipe still completes any pageflip right |
3359 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3373 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3360 | * as the first vblank happend, everything works as expected. Hence just |
3374 | * as the first vblank happend, everything works as expected. Hence just |
3361 | * wait for one vblank before returning to avoid strange things |
3375 | * wait for one vblank before returning to avoid strange things |
3362 | * happening. |
3376 | * happening. |
3363 | */ |
3377 | */ |
3364 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3378 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3365 | } |
3379 | } |
3366 | 3380 | ||
3367 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3381 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3368 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3382 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3369 | { |
3383 | { |
3370 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3384 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3371 | } |
3385 | } |
3372 | 3386 | ||
3373 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3387 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3374 | { |
3388 | { |
3375 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3389 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3376 | 3390 | ||
3377 | if (!crtc->config.ips_enabled) |
3391 | if (!crtc->config.ips_enabled) |
3378 | return; |
3392 | return; |
3379 | 3393 | ||
3380 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3394 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3381 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3395 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3382 | * only after intel_enable_plane. And intel_enable_plane already waits |
3396 | * only after intel_enable_plane. And intel_enable_plane already waits |
3383 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3397 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3384 | assert_plane_enabled(dev_priv, crtc->plane); |
3398 | assert_plane_enabled(dev_priv, crtc->plane); |
3385 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3399 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3386 | } |
3400 | } |
3387 | 3401 | ||
3388 | static void hsw_disable_ips(struct intel_crtc *crtc) |
3402 | static void hsw_disable_ips(struct intel_crtc *crtc) |
3389 | { |
3403 | { |
3390 | struct drm_device *dev = crtc->base.dev; |
3404 | struct drm_device *dev = crtc->base.dev; |
3391 | struct drm_i915_private *dev_priv = dev->dev_private; |
3405 | struct drm_i915_private *dev_priv = dev->dev_private; |
3392 | 3406 | ||
3393 | if (!crtc->config.ips_enabled) |
3407 | if (!crtc->config.ips_enabled) |
3394 | return; |
3408 | return; |
3395 | 3409 | ||
3396 | assert_plane_enabled(dev_priv, crtc->plane); |
3410 | assert_plane_enabled(dev_priv, crtc->plane); |
3397 | I915_WRITE(IPS_CTL, 0); |
3411 | I915_WRITE(IPS_CTL, 0); |
3398 | 3412 | ||
3399 | /* We need to wait for a vblank before we can disable the plane. */ |
3413 | /* We need to wait for a vblank before we can disable the plane. */ |
3400 | intel_wait_for_vblank(dev, crtc->pipe); |
3414 | intel_wait_for_vblank(dev, crtc->pipe); |
3401 | } |
3415 | } |
3402 | 3416 | ||
3403 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3417 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3404 | { |
3418 | { |
3405 | struct drm_device *dev = crtc->dev; |
3419 | struct drm_device *dev = crtc->dev; |
3406 | struct drm_i915_private *dev_priv = dev->dev_private; |
3420 | struct drm_i915_private *dev_priv = dev->dev_private; |
3407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3408 | struct intel_encoder *encoder; |
3422 | struct intel_encoder *encoder; |
3409 | int pipe = intel_crtc->pipe; |
3423 | int pipe = intel_crtc->pipe; |
3410 | int plane = intel_crtc->plane; |
3424 | int plane = intel_crtc->plane; |
3411 | 3425 | ||
3412 | WARN_ON(!crtc->enabled); |
3426 | WARN_ON(!crtc->enabled); |
3413 | 3427 | ||
3414 | if (intel_crtc->active) |
3428 | if (intel_crtc->active) |
3415 | return; |
3429 | return; |
3416 | 3430 | ||
3417 | intel_crtc->active = true; |
3431 | intel_crtc->active = true; |
3418 | 3432 | ||
3419 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3433 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3420 | if (intel_crtc->config.has_pch_encoder) |
3434 | if (intel_crtc->config.has_pch_encoder) |
3421 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3435 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3422 | 3436 | ||
3423 | intel_update_watermarks(dev); |
3437 | intel_update_watermarks(dev); |
3424 | 3438 | ||
3425 | if (intel_crtc->config.has_pch_encoder) |
3439 | if (intel_crtc->config.has_pch_encoder) |
3426 | dev_priv->display.fdi_link_train(crtc); |
3440 | dev_priv->display.fdi_link_train(crtc); |
3427 | 3441 | ||
3428 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3442 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3429 | if (encoder->pre_enable) |
3443 | if (encoder->pre_enable) |
3430 | encoder->pre_enable(encoder); |
3444 | encoder->pre_enable(encoder); |
3431 | 3445 | ||
3432 | intel_ddi_enable_pipe_clock(intel_crtc); |
3446 | intel_ddi_enable_pipe_clock(intel_crtc); |
3433 | 3447 | ||
3434 | ironlake_pfit_enable(intel_crtc); |
3448 | ironlake_pfit_enable(intel_crtc); |
3435 | 3449 | ||
3436 | /* |
3450 | /* |
3437 | * On ILK+ LUT must be loaded before the pipe is running but with |
3451 | * On ILK+ LUT must be loaded before the pipe is running but with |
3438 | * clocks enabled |
3452 | * clocks enabled |
3439 | */ |
3453 | */ |
3440 | intel_crtc_load_lut(crtc); |
3454 | intel_crtc_load_lut(crtc); |
3441 | 3455 | ||
3442 | intel_ddi_set_pipe_settings(crtc); |
3456 | intel_ddi_set_pipe_settings(crtc); |
3443 | intel_ddi_enable_transcoder_func(crtc); |
3457 | intel_ddi_enable_transcoder_func(crtc); |
3444 | 3458 | ||
3445 | intel_enable_pipe(dev_priv, pipe, |
3459 | intel_enable_pipe(dev_priv, pipe, |
3446 | intel_crtc->config.has_pch_encoder); |
3460 | intel_crtc->config.has_pch_encoder); |
3447 | intel_enable_plane(dev_priv, plane, pipe); |
3461 | intel_enable_plane(dev_priv, plane, pipe); |
3448 | intel_enable_planes(crtc); |
3462 | intel_enable_planes(crtc); |
3449 | // intel_crtc_update_cursor(crtc, true); |
3463 | // intel_crtc_update_cursor(crtc, true); |
3450 | 3464 | ||
3451 | hsw_enable_ips(intel_crtc); |
3465 | hsw_enable_ips(intel_crtc); |
3452 | 3466 | ||
3453 | if (intel_crtc->config.has_pch_encoder) |
3467 | if (intel_crtc->config.has_pch_encoder) |
3454 | lpt_pch_enable(crtc); |
3468 | lpt_pch_enable(crtc); |
3455 | 3469 | ||
3456 | mutex_lock(&dev->struct_mutex); |
3470 | mutex_lock(&dev->struct_mutex); |
3457 | intel_update_fbc(dev); |
3471 | intel_update_fbc(dev); |
3458 | mutex_unlock(&dev->struct_mutex); |
3472 | mutex_unlock(&dev->struct_mutex); |
3459 | 3473 | ||
3460 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3474 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3461 | encoder->enable(encoder); |
3475 | encoder->enable(encoder); |
3462 | 3476 | ||
3463 | /* |
3477 | /* |
3464 | * There seems to be a race in PCH platform hw (at least on some |
3478 | * There seems to be a race in PCH platform hw (at least on some |
3465 | * outputs) where an enabled pipe still completes any pageflip right |
3479 | * outputs) where an enabled pipe still completes any pageflip right |
3466 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3480 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3467 | * as the first vblank happend, everything works as expected. Hence just |
3481 | * as the first vblank happend, everything works as expected. Hence just |
3468 | * wait for one vblank before returning to avoid strange things |
3482 | * wait for one vblank before returning to avoid strange things |
3469 | * happening. |
3483 | * happening. |
3470 | */ |
3484 | */ |
3471 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3485 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3472 | } |
3486 | } |
3473 | 3487 | ||
3474 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3488 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3475 | { |
3489 | { |
3476 | struct drm_device *dev = crtc->base.dev; |
3490 | struct drm_device *dev = crtc->base.dev; |
3477 | struct drm_i915_private *dev_priv = dev->dev_private; |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; |
3478 | int pipe = crtc->pipe; |
3492 | int pipe = crtc->pipe; |
3479 | 3493 | ||
3480 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3494 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3481 | * it's in use. The hw state code will make sure we get this right. */ |
3495 | * it's in use. The hw state code will make sure we get this right. */ |
3482 | if (crtc->config.pch_pfit.enabled) { |
3496 | if (crtc->config.pch_pfit.enabled) { |
3483 | I915_WRITE(PF_CTL(pipe), 0); |
3497 | I915_WRITE(PF_CTL(pipe), 0); |
3484 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3498 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3485 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3499 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3486 | } |
3500 | } |
3487 | } |
3501 | } |
3488 | 3502 | ||
3489 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3503 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3490 | { |
3504 | { |
3491 | struct drm_device *dev = crtc->dev; |
3505 | struct drm_device *dev = crtc->dev; |
3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
3506 | struct drm_i915_private *dev_priv = dev->dev_private; |
3493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3494 | struct intel_encoder *encoder; |
3508 | struct intel_encoder *encoder; |
3495 | int pipe = intel_crtc->pipe; |
3509 | int pipe = intel_crtc->pipe; |
3496 | int plane = intel_crtc->plane; |
3510 | int plane = intel_crtc->plane; |
3497 | u32 reg, temp; |
3511 | u32 reg, temp; |
3498 | 3512 | ||
3499 | 3513 | ||
3500 | if (!intel_crtc->active) |
3514 | if (!intel_crtc->active) |
3501 | return; |
3515 | return; |
3502 | 3516 | ||
3503 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3517 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3504 | encoder->disable(encoder); |
3518 | encoder->disable(encoder); |
3505 | 3519 | ||
3506 | // intel_crtc_wait_for_pending_flips(crtc); |
3520 | // intel_crtc_wait_for_pending_flips(crtc); |
3507 | // drm_vblank_off(dev, pipe); |
3521 | // drm_vblank_off(dev, pipe); |
3508 | 3522 | ||
3509 | if (dev_priv->fbc.plane == plane) |
3523 | if (dev_priv->fbc.plane == plane) |
3510 | intel_disable_fbc(dev); |
3524 | intel_disable_fbc(dev); |
3511 | 3525 | ||
3512 | // intel_crtc_update_cursor(crtc, false); |
3526 | // intel_crtc_update_cursor(crtc, false); |
3513 | intel_disable_planes(crtc); |
3527 | intel_disable_planes(crtc); |
3514 | intel_disable_plane(dev_priv, plane, pipe); |
3528 | intel_disable_plane(dev_priv, plane, pipe); |
3515 | 3529 | ||
3516 | if (intel_crtc->config.has_pch_encoder) |
3530 | if (intel_crtc->config.has_pch_encoder) |
3517 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3531 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3518 | 3532 | ||
3519 | intel_disable_pipe(dev_priv, pipe); |
3533 | intel_disable_pipe(dev_priv, pipe); |
3520 | 3534 | ||
3521 | ironlake_pfit_disable(intel_crtc); |
3535 | ironlake_pfit_disable(intel_crtc); |
3522 | 3536 | ||
3523 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3537 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3524 | if (encoder->post_disable) |
3538 | if (encoder->post_disable) |
3525 | encoder->post_disable(encoder); |
3539 | encoder->post_disable(encoder); |
3526 | 3540 | ||
3527 | if (intel_crtc->config.has_pch_encoder) { |
3541 | if (intel_crtc->config.has_pch_encoder) { |
3528 | ironlake_fdi_disable(crtc); |
3542 | ironlake_fdi_disable(crtc); |
3529 | 3543 | ||
3530 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3544 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3531 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3545 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3532 | 3546 | ||
3533 | if (HAS_PCH_CPT(dev)) { |
3547 | if (HAS_PCH_CPT(dev)) { |
3534 | /* disable TRANS_DP_CTL */ |
3548 | /* disable TRANS_DP_CTL */ |
3535 | reg = TRANS_DP_CTL(pipe); |
3549 | reg = TRANS_DP_CTL(pipe); |
3536 | temp = I915_READ(reg); |
3550 | temp = I915_READ(reg); |
3537 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3551 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3538 | TRANS_DP_PORT_SEL_MASK); |
3552 | TRANS_DP_PORT_SEL_MASK); |
3539 | temp |= TRANS_DP_PORT_SEL_NONE; |
3553 | temp |= TRANS_DP_PORT_SEL_NONE; |
3540 | I915_WRITE(reg, temp); |
3554 | I915_WRITE(reg, temp); |
3541 | 3555 | ||
3542 | /* disable DPLL_SEL */ |
3556 | /* disable DPLL_SEL */ |
3543 | temp = I915_READ(PCH_DPLL_SEL); |
3557 | temp = I915_READ(PCH_DPLL_SEL); |
3544 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3558 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3545 | I915_WRITE(PCH_DPLL_SEL, temp); |
3559 | I915_WRITE(PCH_DPLL_SEL, temp); |
3546 | } |
3560 | } |
3547 | 3561 | ||
3548 | /* disable PCH DPLL */ |
3562 | /* disable PCH DPLL */ |
3549 | intel_disable_shared_dpll(intel_crtc); |
3563 | intel_disable_shared_dpll(intel_crtc); |
3550 | 3564 | ||
3551 | ironlake_fdi_pll_disable(intel_crtc); |
3565 | ironlake_fdi_pll_disable(intel_crtc); |
3552 | } |
3566 | } |
3553 | 3567 | ||
3554 | intel_crtc->active = false; |
3568 | intel_crtc->active = false; |
3555 | intel_update_watermarks(dev); |
3569 | intel_update_watermarks(dev); |
3556 | 3570 | ||
3557 | mutex_lock(&dev->struct_mutex); |
3571 | mutex_lock(&dev->struct_mutex); |
3558 | intel_update_fbc(dev); |
3572 | intel_update_fbc(dev); |
3559 | mutex_unlock(&dev->struct_mutex); |
3573 | mutex_unlock(&dev->struct_mutex); |
3560 | } |
3574 | } |
3561 | 3575 | ||
3562 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3576 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3563 | { |
3577 | { |
3564 | struct drm_device *dev = crtc->dev; |
3578 | struct drm_device *dev = crtc->dev; |
3565 | struct drm_i915_private *dev_priv = dev->dev_private; |
3579 | struct drm_i915_private *dev_priv = dev->dev_private; |
3566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3567 | struct intel_encoder *encoder; |
3581 | struct intel_encoder *encoder; |
3568 | int pipe = intel_crtc->pipe; |
3582 | int pipe = intel_crtc->pipe; |
3569 | int plane = intel_crtc->plane; |
3583 | int plane = intel_crtc->plane; |
3570 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3584 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3571 | 3585 | ||
3572 | if (!intel_crtc->active) |
3586 | if (!intel_crtc->active) |
3573 | return; |
3587 | return; |
3574 | 3588 | ||
3575 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3589 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3576 | encoder->disable(encoder); |
3590 | encoder->disable(encoder); |
3577 | 3591 | ||
3578 | 3592 | ||
3579 | /* FBC must be disabled before disabling the plane on HSW. */ |
3593 | /* FBC must be disabled before disabling the plane on HSW. */ |
3580 | if (dev_priv->fbc.plane == plane) |
3594 | if (dev_priv->fbc.plane == plane) |
3581 | intel_disable_fbc(dev); |
3595 | intel_disable_fbc(dev); |
3582 | 3596 | ||
3583 | hsw_disable_ips(intel_crtc); |
3597 | hsw_disable_ips(intel_crtc); |
3584 | 3598 | ||
3585 | // intel_crtc_update_cursor(crtc, false); |
3599 | // intel_crtc_update_cursor(crtc, false); |
3586 | intel_disable_planes(crtc); |
3600 | intel_disable_planes(crtc); |
3587 | intel_disable_plane(dev_priv, plane, pipe); |
3601 | intel_disable_plane(dev_priv, plane, pipe); |
3588 | 3602 | ||
3589 | if (intel_crtc->config.has_pch_encoder) |
3603 | if (intel_crtc->config.has_pch_encoder) |
3590 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3604 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3591 | intel_disable_pipe(dev_priv, pipe); |
3605 | intel_disable_pipe(dev_priv, pipe); |
3592 | 3606 | ||
3593 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
3607 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
3594 | 3608 | ||
3595 | ironlake_pfit_disable(intel_crtc); |
3609 | ironlake_pfit_disable(intel_crtc); |
3596 | 3610 | ||
3597 | intel_ddi_disable_pipe_clock(intel_crtc); |
3611 | intel_ddi_disable_pipe_clock(intel_crtc); |
3598 | 3612 | ||
3599 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3613 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3600 | if (encoder->post_disable) |
3614 | if (encoder->post_disable) |
3601 | encoder->post_disable(encoder); |
3615 | encoder->post_disable(encoder); |
3602 | 3616 | ||
3603 | if (intel_crtc->config.has_pch_encoder) { |
3617 | if (intel_crtc->config.has_pch_encoder) { |
3604 | lpt_disable_pch_transcoder(dev_priv); |
3618 | lpt_disable_pch_transcoder(dev_priv); |
3605 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3619 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3606 | intel_ddi_fdi_disable(crtc); |
3620 | intel_ddi_fdi_disable(crtc); |
3607 | } |
3621 | } |
3608 | 3622 | ||
3609 | intel_crtc->active = false; |
3623 | intel_crtc->active = false; |
3610 | intel_update_watermarks(dev); |
3624 | intel_update_watermarks(dev); |
3611 | 3625 | ||
3612 | mutex_lock(&dev->struct_mutex); |
3626 | mutex_lock(&dev->struct_mutex); |
3613 | intel_update_fbc(dev); |
3627 | intel_update_fbc(dev); |
3614 | mutex_unlock(&dev->struct_mutex); |
3628 | mutex_unlock(&dev->struct_mutex); |
3615 | } |
3629 | } |
3616 | 3630 | ||
3617 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3631 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3618 | { |
3632 | { |
3619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3620 | intel_put_shared_dpll(intel_crtc); |
3634 | intel_put_shared_dpll(intel_crtc); |
3621 | } |
3635 | } |
3622 | 3636 | ||
3623 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3637 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3624 | { |
3638 | { |
3625 | intel_ddi_put_crtc_pll(crtc); |
3639 | intel_ddi_put_crtc_pll(crtc); |
3626 | } |
3640 | } |
3627 | 3641 | ||
3628 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3642 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3629 | { |
3643 | { |
3630 | if (!enable && intel_crtc->overlay) { |
3644 | if (!enable && intel_crtc->overlay) { |
3631 | struct drm_device *dev = intel_crtc->base.dev; |
3645 | struct drm_device *dev = intel_crtc->base.dev; |
3632 | struct drm_i915_private *dev_priv = dev->dev_private; |
3646 | struct drm_i915_private *dev_priv = dev->dev_private; |
3633 | 3647 | ||
3634 | mutex_lock(&dev->struct_mutex); |
3648 | mutex_lock(&dev->struct_mutex); |
3635 | dev_priv->mm.interruptible = false; |
3649 | dev_priv->mm.interruptible = false; |
3636 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3650 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3637 | dev_priv->mm.interruptible = true; |
3651 | dev_priv->mm.interruptible = true; |
3638 | mutex_unlock(&dev->struct_mutex); |
3652 | mutex_unlock(&dev->struct_mutex); |
3639 | } |
3653 | } |
3640 | 3654 | ||
3641 | /* Let userspace switch the overlay on again. In most cases userspace |
3655 | /* Let userspace switch the overlay on again. In most cases userspace |
3642 | * has to recompute where to put it anyway. |
3656 | * has to recompute where to put it anyway. |
3643 | */ |
3657 | */ |
3644 | } |
3658 | } |
3645 | 3659 | ||
3646 | /** |
3660 | /** |
3647 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
3661 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
3648 | * cursor plane briefly if not already running after enabling the display |
3662 | * cursor plane briefly if not already running after enabling the display |
3649 | * plane. |
3663 | * plane. |
3650 | * This workaround avoids occasional blank screens when self refresh is |
3664 | * This workaround avoids occasional blank screens when self refresh is |
3651 | * enabled. |
3665 | * enabled. |
3652 | */ |
3666 | */ |
3653 | static void |
3667 | static void |
3654 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
3668 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
3655 | { |
3669 | { |
3656 | u32 cntl = I915_READ(CURCNTR(pipe)); |
3670 | u32 cntl = I915_READ(CURCNTR(pipe)); |
3657 | 3671 | ||
3658 | if ((cntl & CURSOR_MODE) == 0) { |
3672 | if ((cntl & CURSOR_MODE) == 0) { |
3659 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
3673 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
3660 | 3674 | ||
3661 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
3675 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
3662 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
3676 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
3663 | intel_wait_for_vblank(dev_priv->dev, pipe); |
3677 | intel_wait_for_vblank(dev_priv->dev, pipe); |
3664 | I915_WRITE(CURCNTR(pipe), cntl); |
3678 | I915_WRITE(CURCNTR(pipe), cntl); |
3665 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3679 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3666 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
3680 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
3667 | } |
3681 | } |
3668 | } |
3682 | } |
3669 | 3683 | ||
3670 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3684 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3671 | { |
3685 | { |
3672 | struct drm_device *dev = crtc->base.dev; |
3686 | struct drm_device *dev = crtc->base.dev; |
3673 | struct drm_i915_private *dev_priv = dev->dev_private; |
3687 | struct drm_i915_private *dev_priv = dev->dev_private; |
3674 | struct intel_crtc_config *pipe_config = &crtc->config; |
3688 | struct intel_crtc_config *pipe_config = &crtc->config; |
3675 | 3689 | ||
3676 | if (!crtc->config.gmch_pfit.control) |
3690 | if (!crtc->config.gmch_pfit.control) |
3677 | return; |
3691 | return; |
3678 | 3692 | ||
3679 | /* |
3693 | /* |
3680 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3694 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3681 | * according to register description and PRM. |
3695 | * according to register description and PRM. |
3682 | */ |
3696 | */ |
3683 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3697 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3684 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3698 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3685 | 3699 | ||
3686 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3700 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3687 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
3701 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
3688 | 3702 | ||
3689 | /* Border color in case we don't scale up to the full screen. Black by |
3703 | /* Border color in case we don't scale up to the full screen. Black by |
3690 | * default, change to something else for debugging. */ |
3704 | * default, change to something else for debugging. */ |
3691 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3705 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3692 | } |
3706 | } |
3693 | 3707 | ||
3694 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3708 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3695 | { |
3709 | { |
3696 | struct drm_device *dev = crtc->dev; |
3710 | struct drm_device *dev = crtc->dev; |
3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
3711 | struct drm_i915_private *dev_priv = dev->dev_private; |
3698 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3699 | struct intel_encoder *encoder; |
3713 | struct intel_encoder *encoder; |
3700 | int pipe = intel_crtc->pipe; |
3714 | int pipe = intel_crtc->pipe; |
3701 | int plane = intel_crtc->plane; |
3715 | int plane = intel_crtc->plane; |
3702 | 3716 | ||
3703 | WARN_ON(!crtc->enabled); |
3717 | WARN_ON(!crtc->enabled); |
3704 | 3718 | ||
3705 | if (intel_crtc->active) |
3719 | if (intel_crtc->active) |
3706 | return; |
3720 | return; |
3707 | 3721 | ||
3708 | intel_crtc->active = true; |
3722 | intel_crtc->active = true; |
3709 | intel_update_watermarks(dev); |
3723 | intel_update_watermarks(dev); |
3710 | 3724 | ||
3711 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3725 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3712 | if (encoder->pre_pll_enable) |
3726 | if (encoder->pre_pll_enable) |
3713 | encoder->pre_pll_enable(encoder); |
3727 | encoder->pre_pll_enable(encoder); |
3714 | 3728 | ||
3715 | vlv_enable_pll(intel_crtc); |
3729 | vlv_enable_pll(intel_crtc); |
3716 | 3730 | ||
3717 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3731 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3718 | if (encoder->pre_enable) |
3732 | if (encoder->pre_enable) |
3719 | encoder->pre_enable(encoder); |
3733 | encoder->pre_enable(encoder); |
3720 | 3734 | ||
3721 | i9xx_pfit_enable(intel_crtc); |
3735 | i9xx_pfit_enable(intel_crtc); |
3722 | 3736 | ||
3723 | intel_crtc_load_lut(crtc); |
3737 | intel_crtc_load_lut(crtc); |
3724 | 3738 | ||
3725 | intel_enable_pipe(dev_priv, pipe, false); |
3739 | intel_enable_pipe(dev_priv, pipe, false); |
3726 | intel_enable_plane(dev_priv, plane, pipe); |
3740 | intel_enable_plane(dev_priv, plane, pipe); |
3727 | intel_enable_planes(crtc); |
3741 | intel_enable_planes(crtc); |
3728 | // intel_crtc_update_cursor(crtc, true); |
3742 | // intel_crtc_update_cursor(crtc, true); |
3729 | 3743 | ||
3730 | intel_update_fbc(dev); |
3744 | intel_update_fbc(dev); |
3731 | 3745 | ||
3732 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3746 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3733 | encoder->enable(encoder); |
3747 | encoder->enable(encoder); |
3734 | } |
3748 | } |
3735 | 3749 | ||
3736 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3750 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3737 | { |
3751 | { |
3738 | struct drm_device *dev = crtc->dev; |
3752 | struct drm_device *dev = crtc->dev; |
3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
3753 | struct drm_i915_private *dev_priv = dev->dev_private; |
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3741 | struct intel_encoder *encoder; |
3755 | struct intel_encoder *encoder; |
3742 | int pipe = intel_crtc->pipe; |
3756 | int pipe = intel_crtc->pipe; |
3743 | int plane = intel_crtc->plane; |
3757 | int plane = intel_crtc->plane; |
3744 | 3758 | ||
3745 | WARN_ON(!crtc->enabled); |
3759 | WARN_ON(!crtc->enabled); |
3746 | 3760 | ||
3747 | if (intel_crtc->active) |
3761 | if (intel_crtc->active) |
3748 | return; |
3762 | return; |
3749 | 3763 | ||
3750 | intel_crtc->active = true; |
3764 | intel_crtc->active = true; |
3751 | intel_update_watermarks(dev); |
3765 | intel_update_watermarks(dev); |
3752 | 3766 | ||
3753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3767 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3754 | if (encoder->pre_enable) |
3768 | if (encoder->pre_enable) |
3755 | encoder->pre_enable(encoder); |
3769 | encoder->pre_enable(encoder); |
3756 | 3770 | ||
3757 | i9xx_enable_pll(intel_crtc); |
3771 | i9xx_enable_pll(intel_crtc); |
3758 | 3772 | ||
3759 | i9xx_pfit_enable(intel_crtc); |
3773 | i9xx_pfit_enable(intel_crtc); |
3760 | 3774 | ||
3761 | intel_crtc_load_lut(crtc); |
3775 | intel_crtc_load_lut(crtc); |
3762 | 3776 | ||
3763 | intel_enable_pipe(dev_priv, pipe, false); |
3777 | intel_enable_pipe(dev_priv, pipe, false); |
3764 | intel_enable_plane(dev_priv, plane, pipe); |
3778 | intel_enable_plane(dev_priv, plane, pipe); |
3765 | intel_enable_planes(crtc); |
3779 | intel_enable_planes(crtc); |
3766 | /* The fixup needs to happen before cursor is enabled */ |
3780 | /* The fixup needs to happen before cursor is enabled */ |
3767 | if (IS_G4X(dev)) |
3781 | if (IS_G4X(dev)) |
3768 | g4x_fixup_plane(dev_priv, pipe); |
3782 | g4x_fixup_plane(dev_priv, pipe); |
3769 | // intel_crtc_update_cursor(crtc, true); |
3783 | // intel_crtc_update_cursor(crtc, true); |
3770 | 3784 | ||
3771 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3785 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3772 | intel_crtc_dpms_overlay(intel_crtc, true); |
3786 | intel_crtc_dpms_overlay(intel_crtc, true); |
3773 | 3787 | ||
3774 | intel_update_fbc(dev); |
3788 | intel_update_fbc(dev); |
3775 | 3789 | ||
3776 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3790 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3777 | encoder->enable(encoder); |
3791 | encoder->enable(encoder); |
3778 | } |
3792 | } |
3779 | 3793 | ||
3780 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3794 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3781 | { |
3795 | { |
3782 | struct drm_device *dev = crtc->base.dev; |
3796 | struct drm_device *dev = crtc->base.dev; |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
3784 | 3798 | ||
3785 | if (!crtc->config.gmch_pfit.control) |
3799 | if (!crtc->config.gmch_pfit.control) |
3786 | return; |
3800 | return; |
3787 | 3801 | ||
3788 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3802 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3789 | 3803 | ||
3790 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3804 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3791 | I915_READ(PFIT_CONTROL)); |
3805 | I915_READ(PFIT_CONTROL)); |
3792 | I915_WRITE(PFIT_CONTROL, 0); |
3806 | I915_WRITE(PFIT_CONTROL, 0); |
3793 | } |
3807 | } |
3794 | 3808 | ||
3795 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3809 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3796 | { |
3810 | { |
3797 | struct drm_device *dev = crtc->dev; |
3811 | struct drm_device *dev = crtc->dev; |
3798 | struct drm_i915_private *dev_priv = dev->dev_private; |
3812 | struct drm_i915_private *dev_priv = dev->dev_private; |
3799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3800 | struct intel_encoder *encoder; |
3814 | struct intel_encoder *encoder; |
3801 | int pipe = intel_crtc->pipe; |
3815 | int pipe = intel_crtc->pipe; |
3802 | int plane = intel_crtc->plane; |
3816 | int plane = intel_crtc->plane; |
3803 | 3817 | ||
3804 | if (!intel_crtc->active) |
3818 | if (!intel_crtc->active) |
3805 | return; |
3819 | return; |
3806 | 3820 | ||
3807 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3821 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3808 | encoder->disable(encoder); |
3822 | encoder->disable(encoder); |
3809 | 3823 | ||
3810 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3824 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3811 | // intel_crtc_wait_for_pending_flips(crtc); |
3825 | // intel_crtc_wait_for_pending_flips(crtc); |
3812 | // drm_vblank_off(dev, pipe); |
3826 | // drm_vblank_off(dev, pipe); |
3813 | 3827 | ||
3814 | if (dev_priv->fbc.plane == plane) |
3828 | if (dev_priv->fbc.plane == plane) |
3815 | intel_disable_fbc(dev); |
3829 | intel_disable_fbc(dev); |
3816 | 3830 | ||
3817 | intel_crtc_dpms_overlay(intel_crtc, false); |
3831 | intel_crtc_dpms_overlay(intel_crtc, false); |
3818 | // intel_crtc_update_cursor(crtc, false); |
3832 | // intel_crtc_update_cursor(crtc, false); |
3819 | intel_disable_planes(crtc); |
3833 | intel_disable_planes(crtc); |
3820 | intel_disable_plane(dev_priv, plane, pipe); |
3834 | intel_disable_plane(dev_priv, plane, pipe); |
3821 | 3835 | ||
3822 | intel_disable_pipe(dev_priv, pipe); |
3836 | intel_disable_pipe(dev_priv, pipe); |
3823 | 3837 | ||
3824 | i9xx_pfit_disable(intel_crtc); |
3838 | i9xx_pfit_disable(intel_crtc); |
3825 | 3839 | ||
3826 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3840 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3827 | if (encoder->post_disable) |
3841 | if (encoder->post_disable) |
3828 | encoder->post_disable(encoder); |
3842 | encoder->post_disable(encoder); |
3829 | 3843 | ||
3830 | i9xx_disable_pll(dev_priv, pipe); |
3844 | i9xx_disable_pll(dev_priv, pipe); |
3831 | 3845 | ||
3832 | intel_crtc->active = false; |
3846 | intel_crtc->active = false; |
3833 | intel_update_fbc(dev); |
3847 | intel_update_fbc(dev); |
3834 | intel_update_watermarks(dev); |
3848 | intel_update_watermarks(dev); |
3835 | } |
3849 | } |
3836 | 3850 | ||
3837 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3851 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3838 | { |
3852 | { |
3839 | } |
3853 | } |
3840 | 3854 | ||
3841 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3855 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3842 | bool enabled) |
3856 | bool enabled) |
3843 | { |
3857 | { |
3844 | struct drm_device *dev = crtc->dev; |
3858 | struct drm_device *dev = crtc->dev; |
3845 | struct drm_i915_master_private *master_priv; |
3859 | struct drm_i915_master_private *master_priv; |
3846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3847 | int pipe = intel_crtc->pipe; |
3861 | int pipe = intel_crtc->pipe; |
3848 | 3862 | ||
3849 | 3863 | ||
3850 | #if 0 |
3864 | #if 0 |
3851 | if (!dev->primary->master) |
3865 | if (!dev->primary->master) |
3852 | return; |
3866 | return; |
3853 | 3867 | ||
3854 | master_priv = dev->primary->master->driver_priv; |
3868 | master_priv = dev->primary->master->driver_priv; |
3855 | if (!master_priv->sarea_priv) |
3869 | if (!master_priv->sarea_priv) |
3856 | return; |
3870 | return; |
3857 | 3871 | ||
3858 | switch (pipe) { |
3872 | switch (pipe) { |
3859 | case 0: |
3873 | case 0: |
3860 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3874 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3861 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3875 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3862 | break; |
3876 | break; |
3863 | case 1: |
3877 | case 1: |
3864 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3878 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3865 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3879 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3866 | break; |
3880 | break; |
3867 | default: |
3881 | default: |
3868 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3882 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3869 | break; |
3883 | break; |
3870 | } |
3884 | } |
3871 | #endif |
3885 | #endif |
3872 | 3886 | ||
3873 | } |
3887 | } |
3874 | 3888 | ||
3875 | /** |
3889 | /** |
3876 | * Sets the power management mode of the pipe and plane. |
3890 | * Sets the power management mode of the pipe and plane. |
3877 | */ |
3891 | */ |
3878 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3892 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3879 | { |
3893 | { |
3880 | struct drm_device *dev = crtc->dev; |
3894 | struct drm_device *dev = crtc->dev; |
3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
3895 | struct drm_i915_private *dev_priv = dev->dev_private; |
3882 | struct intel_encoder *intel_encoder; |
3896 | struct intel_encoder *intel_encoder; |
3883 | bool enable = false; |
3897 | bool enable = false; |
3884 | 3898 | ||
3885 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3899 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3886 | enable |= intel_encoder->connectors_active; |
3900 | enable |= intel_encoder->connectors_active; |
3887 | 3901 | ||
3888 | if (enable) |
3902 | if (enable) |
3889 | dev_priv->display.crtc_enable(crtc); |
3903 | dev_priv->display.crtc_enable(crtc); |
3890 | else |
3904 | else |
3891 | dev_priv->display.crtc_disable(crtc); |
3905 | dev_priv->display.crtc_disable(crtc); |
3892 | 3906 | ||
3893 | intel_crtc_update_sarea(crtc, enable); |
3907 | intel_crtc_update_sarea(crtc, enable); |
3894 | } |
3908 | } |
3895 | 3909 | ||
3896 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3910 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3897 | { |
3911 | { |
3898 | struct drm_device *dev = crtc->dev; |
3912 | struct drm_device *dev = crtc->dev; |
3899 | struct drm_connector *connector; |
3913 | struct drm_connector *connector; |
3900 | struct drm_i915_private *dev_priv = dev->dev_private; |
3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
3901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3902 | 3916 | ||
3903 | /* crtc should still be enabled when we disable it. */ |
3917 | /* crtc should still be enabled when we disable it. */ |
3904 | WARN_ON(!crtc->enabled); |
3918 | WARN_ON(!crtc->enabled); |
3905 | 3919 | ||
3906 | dev_priv->display.crtc_disable(crtc); |
3920 | dev_priv->display.crtc_disable(crtc); |
3907 | intel_crtc->eld_vld = false; |
3921 | intel_crtc->eld_vld = false; |
3908 | intel_crtc_update_sarea(crtc, false); |
3922 | intel_crtc_update_sarea(crtc, false); |
3909 | dev_priv->display.off(crtc); |
3923 | dev_priv->display.off(crtc); |
3910 | 3924 | ||
3911 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3925 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3912 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3926 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3913 | 3927 | ||
3914 | if (crtc->fb) { |
3928 | if (crtc->fb) { |
3915 | mutex_lock(&dev->struct_mutex); |
3929 | mutex_lock(&dev->struct_mutex); |
3916 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3930 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3917 | mutex_unlock(&dev->struct_mutex); |
3931 | mutex_unlock(&dev->struct_mutex); |
3918 | crtc->fb = NULL; |
3932 | crtc->fb = NULL; |
3919 | } |
3933 | } |
3920 | 3934 | ||
3921 | /* Update computed state. */ |
3935 | /* Update computed state. */ |
3922 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3936 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3923 | if (!connector->encoder || !connector->encoder->crtc) |
3937 | if (!connector->encoder || !connector->encoder->crtc) |
3924 | continue; |
3938 | continue; |
3925 | 3939 | ||
3926 | if (connector->encoder->crtc != crtc) |
3940 | if (connector->encoder->crtc != crtc) |
3927 | continue; |
3941 | continue; |
3928 | 3942 | ||
3929 | connector->dpms = DRM_MODE_DPMS_OFF; |
3943 | connector->dpms = DRM_MODE_DPMS_OFF; |
3930 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3944 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3931 | } |
3945 | } |
3932 | } |
3946 | } |
3933 | 3947 | ||
3934 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3948 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3935 | { |
3949 | { |
3936 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3950 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3937 | 3951 | ||
3938 | drm_encoder_cleanup(encoder); |
3952 | drm_encoder_cleanup(encoder); |
3939 | kfree(intel_encoder); |
3953 | kfree(intel_encoder); |
3940 | } |
3954 | } |
3941 | 3955 | ||
3942 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
3956 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
3943 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3957 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3944 | * state of the entire output pipe. */ |
3958 | * state of the entire output pipe. */ |
3945 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3959 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3946 | { |
3960 | { |
3947 | if (mode == DRM_MODE_DPMS_ON) { |
3961 | if (mode == DRM_MODE_DPMS_ON) { |
3948 | encoder->connectors_active = true; |
3962 | encoder->connectors_active = true; |
3949 | 3963 | ||
3950 | intel_crtc_update_dpms(encoder->base.crtc); |
3964 | intel_crtc_update_dpms(encoder->base.crtc); |
3951 | } else { |
3965 | } else { |
3952 | encoder->connectors_active = false; |
3966 | encoder->connectors_active = false; |
3953 | 3967 | ||
3954 | intel_crtc_update_dpms(encoder->base.crtc); |
3968 | intel_crtc_update_dpms(encoder->base.crtc); |
3955 | } |
3969 | } |
3956 | } |
3970 | } |
3957 | 3971 | ||
3958 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3972 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3959 | * internal consistency). */ |
3973 | * internal consistency). */ |
3960 | static void intel_connector_check_state(struct intel_connector *connector) |
3974 | static void intel_connector_check_state(struct intel_connector *connector) |
3961 | { |
3975 | { |
3962 | if (connector->get_hw_state(connector)) { |
3976 | if (connector->get_hw_state(connector)) { |
3963 | struct intel_encoder *encoder = connector->encoder; |
3977 | struct intel_encoder *encoder = connector->encoder; |
3964 | struct drm_crtc *crtc; |
3978 | struct drm_crtc *crtc; |
3965 | bool encoder_enabled; |
3979 | bool encoder_enabled; |
3966 | enum pipe pipe; |
3980 | enum pipe pipe; |
3967 | 3981 | ||
3968 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3982 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3969 | connector->base.base.id, |
3983 | connector->base.base.id, |
3970 | drm_get_connector_name(&connector->base)); |
3984 | drm_get_connector_name(&connector->base)); |
3971 | 3985 | ||
3972 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3986 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3973 | "wrong connector dpms state\n"); |
3987 | "wrong connector dpms state\n"); |
3974 | WARN(connector->base.encoder != &encoder->base, |
3988 | WARN(connector->base.encoder != &encoder->base, |
3975 | "active connector not linked to encoder\n"); |
3989 | "active connector not linked to encoder\n"); |
3976 | WARN(!encoder->connectors_active, |
3990 | WARN(!encoder->connectors_active, |
3977 | "encoder->connectors_active not set\n"); |
3991 | "encoder->connectors_active not set\n"); |
3978 | 3992 | ||
3979 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3993 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3980 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3994 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3981 | if (WARN_ON(!encoder->base.crtc)) |
3995 | if (WARN_ON(!encoder->base.crtc)) |
3982 | return; |
3996 | return; |
3983 | 3997 | ||
3984 | crtc = encoder->base.crtc; |
3998 | crtc = encoder->base.crtc; |
3985 | 3999 | ||
3986 | WARN(!crtc->enabled, "crtc not enabled\n"); |
4000 | WARN(!crtc->enabled, "crtc not enabled\n"); |
3987 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
4001 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
3988 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
4002 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
3989 | "encoder active on the wrong pipe\n"); |
4003 | "encoder active on the wrong pipe\n"); |
3990 | } |
4004 | } |
3991 | } |
4005 | } |
3992 | 4006 | ||
3993 | /* Even simpler default implementation, if there's really no special case to |
4007 | /* Even simpler default implementation, if there's really no special case to |
3994 | * consider. */ |
4008 | * consider. */ |
3995 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
4009 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
3996 | { |
4010 | { |
3997 | /* All the simple cases only support two dpms states. */ |
4011 | /* All the simple cases only support two dpms states. */ |
3998 | if (mode != DRM_MODE_DPMS_ON) |
4012 | if (mode != DRM_MODE_DPMS_ON) |
3999 | mode = DRM_MODE_DPMS_OFF; |
4013 | mode = DRM_MODE_DPMS_OFF; |
4000 | 4014 | ||
4001 | if (mode == connector->dpms) |
4015 | if (mode == connector->dpms) |
4002 | return; |
4016 | return; |
4003 | 4017 | ||
4004 | connector->dpms = mode; |
4018 | connector->dpms = mode; |
4005 | 4019 | ||
4006 | /* Only need to change hw state when actually enabled */ |
4020 | /* Only need to change hw state when actually enabled */ |
4007 | if (connector->encoder) |
4021 | if (connector->encoder) |
4008 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
4022 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
4009 | 4023 | ||
4010 | intel_modeset_check_state(connector->dev); |
4024 | intel_modeset_check_state(connector->dev); |
4011 | } |
4025 | } |
4012 | 4026 | ||
4013 | /* Simple connector->get_hw_state implementation for encoders that support only |
4027 | /* Simple connector->get_hw_state implementation for encoders that support only |
4014 | * one connector and no cloning and hence the encoder state determines the state |
4028 | * one connector and no cloning and hence the encoder state determines the state |
4015 | * of the connector. */ |
4029 | * of the connector. */ |
4016 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
4030 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
4017 | { |
4031 | { |
4018 | enum pipe pipe = 0; |
4032 | enum pipe pipe = 0; |
4019 | struct intel_encoder *encoder = connector->encoder; |
4033 | struct intel_encoder *encoder = connector->encoder; |
4020 | 4034 | ||
4021 | return encoder->get_hw_state(encoder, &pipe); |
4035 | return encoder->get_hw_state(encoder, &pipe); |
4022 | } |
4036 | } |
4023 | 4037 | ||
4024 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4038 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4025 | struct intel_crtc_config *pipe_config) |
4039 | struct intel_crtc_config *pipe_config) |
4026 | { |
4040 | { |
4027 | struct drm_i915_private *dev_priv = dev->dev_private; |
4041 | struct drm_i915_private *dev_priv = dev->dev_private; |
4028 | struct intel_crtc *pipe_B_crtc = |
4042 | struct intel_crtc *pipe_B_crtc = |
4029 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
4043 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
4030 | 4044 | ||
4031 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
4045 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
4032 | pipe_name(pipe), pipe_config->fdi_lanes); |
4046 | pipe_name(pipe), pipe_config->fdi_lanes); |
4033 | if (pipe_config->fdi_lanes > 4) { |
4047 | if (pipe_config->fdi_lanes > 4) { |
4034 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4048 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4035 | pipe_name(pipe), pipe_config->fdi_lanes); |
4049 | pipe_name(pipe), pipe_config->fdi_lanes); |
4036 | return false; |
4050 | return false; |
4037 | } |
4051 | } |
4038 | 4052 | ||
4039 | if (IS_HASWELL(dev)) { |
4053 | if (IS_HASWELL(dev)) { |
4040 | if (pipe_config->fdi_lanes > 2) { |
4054 | if (pipe_config->fdi_lanes > 2) { |
4041 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4055 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4042 | pipe_config->fdi_lanes); |
4056 | pipe_config->fdi_lanes); |
4043 | return false; |
4057 | return false; |
4044 | } else { |
4058 | } else { |
4045 | return true; |
4059 | return true; |
4046 | } |
4060 | } |
4047 | } |
4061 | } |
4048 | 4062 | ||
4049 | if (INTEL_INFO(dev)->num_pipes == 2) |
4063 | if (INTEL_INFO(dev)->num_pipes == 2) |
4050 | return true; |
4064 | return true; |
4051 | 4065 | ||
4052 | /* Ivybridge 3 pipe is really complicated */ |
4066 | /* Ivybridge 3 pipe is really complicated */ |
4053 | switch (pipe) { |
4067 | switch (pipe) { |
4054 | case PIPE_A: |
4068 | case PIPE_A: |
4055 | return true; |
4069 | return true; |
4056 | case PIPE_B: |
4070 | case PIPE_B: |
4057 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
4071 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
4058 | pipe_config->fdi_lanes > 2) { |
4072 | pipe_config->fdi_lanes > 2) { |
4059 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4073 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4060 | pipe_name(pipe), pipe_config->fdi_lanes); |
4074 | pipe_name(pipe), pipe_config->fdi_lanes); |
4061 | return false; |
4075 | return false; |
4062 | } |
4076 | } |
4063 | return true; |
4077 | return true; |
4064 | case PIPE_C: |
4078 | case PIPE_C: |
4065 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4079 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4066 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4080 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4067 | if (pipe_config->fdi_lanes > 2) { |
4081 | if (pipe_config->fdi_lanes > 2) { |
4068 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4082 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4069 | pipe_name(pipe), pipe_config->fdi_lanes); |
4083 | pipe_name(pipe), pipe_config->fdi_lanes); |
4070 | return false; |
4084 | return false; |
4071 | } |
4085 | } |
4072 | } else { |
4086 | } else { |
4073 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
4087 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
4074 | return false; |
4088 | return false; |
4075 | } |
4089 | } |
4076 | return true; |
4090 | return true; |
4077 | default: |
4091 | default: |
4078 | BUG(); |
4092 | BUG(); |
4079 | } |
4093 | } |
4080 | } |
4094 | } |
4081 | 4095 | ||
4082 | #define RETRY 1 |
4096 | #define RETRY 1 |
4083 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4097 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4084 | struct intel_crtc_config *pipe_config) |
4098 | struct intel_crtc_config *pipe_config) |
4085 | { |
4099 | { |
4086 | struct drm_device *dev = intel_crtc->base.dev; |
4100 | struct drm_device *dev = intel_crtc->base.dev; |
4087 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4101 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4088 | int lane, link_bw, fdi_dotclock; |
4102 | int lane, link_bw, fdi_dotclock; |
4089 | bool setup_ok, needs_recompute = false; |
4103 | bool setup_ok, needs_recompute = false; |
4090 | 4104 | ||
4091 | retry: |
4105 | retry: |
4092 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4106 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4093 | * each output octet as 10 bits. The actual frequency |
4107 | * each output octet as 10 bits. The actual frequency |
4094 | * is stored as a divider into a 100MHz clock, and the |
4108 | * is stored as a divider into a 100MHz clock, and the |
4095 | * mode pixel clock is stored in units of 1KHz. |
4109 | * mode pixel clock is stored in units of 1KHz. |
4096 | * Hence the bw of each lane in terms of the mode signal |
4110 | * Hence the bw of each lane in terms of the mode signal |
4097 | * is: |
4111 | * is: |
4098 | */ |
4112 | */ |
4099 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4113 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4100 | 4114 | ||
4101 | fdi_dotclock = adjusted_mode->clock; |
4115 | fdi_dotclock = adjusted_mode->clock; |
4102 | fdi_dotclock /= pipe_config->pixel_multiplier; |
4116 | fdi_dotclock /= pipe_config->pixel_multiplier; |
4103 | 4117 | ||
4104 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4118 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4105 | pipe_config->pipe_bpp); |
4119 | pipe_config->pipe_bpp); |
4106 | 4120 | ||
4107 | pipe_config->fdi_lanes = lane; |
4121 | pipe_config->fdi_lanes = lane; |
4108 | 4122 | ||
4109 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4123 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4110 | link_bw, &pipe_config->fdi_m_n); |
4124 | link_bw, &pipe_config->fdi_m_n); |
4111 | 4125 | ||
4112 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4126 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4113 | intel_crtc->pipe, pipe_config); |
4127 | intel_crtc->pipe, pipe_config); |
4114 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4128 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4115 | pipe_config->pipe_bpp -= 2*3; |
4129 | pipe_config->pipe_bpp -= 2*3; |
4116 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
4130 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
4117 | pipe_config->pipe_bpp); |
4131 | pipe_config->pipe_bpp); |
4118 | needs_recompute = true; |
4132 | needs_recompute = true; |
4119 | pipe_config->bw_constrained = true; |
4133 | pipe_config->bw_constrained = true; |
4120 | 4134 | ||
4121 | goto retry; |
4135 | goto retry; |
4122 | } |
4136 | } |
4123 | 4137 | ||
4124 | if (needs_recompute) |
4138 | if (needs_recompute) |
4125 | return RETRY; |
4139 | return RETRY; |
4126 | 4140 | ||
4127 | return setup_ok ? 0 : -EINVAL; |
4141 | return setup_ok ? 0 : -EINVAL; |
4128 | } |
4142 | } |
4129 | 4143 | ||
4130 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4144 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4131 | struct intel_crtc_config *pipe_config) |
4145 | struct intel_crtc_config *pipe_config) |
4132 | { |
4146 | { |
4133 | pipe_config->ips_enabled = i915_enable_ips && |
4147 | pipe_config->ips_enabled = i915_enable_ips && |
4134 | hsw_crtc_supports_ips(crtc) && |
4148 | hsw_crtc_supports_ips(crtc) && |
4135 | pipe_config->pipe_bpp <= 24; |
4149 | pipe_config->pipe_bpp <= 24; |
4136 | } |
4150 | } |
4137 | 4151 | ||
4138 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4152 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4139 | struct intel_crtc_config *pipe_config) |
4153 | struct intel_crtc_config *pipe_config) |
4140 | { |
4154 | { |
4141 | struct drm_device *dev = crtc->base.dev; |
4155 | struct drm_device *dev = crtc->base.dev; |
4142 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4156 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4143 | 4157 | ||
4144 | if (HAS_PCH_SPLIT(dev)) { |
4158 | if (HAS_PCH_SPLIT(dev)) { |
4145 | /* FDI link clock is fixed at 2.7G */ |
4159 | /* FDI link clock is fixed at 2.7G */ |
4146 | if (pipe_config->requested_mode.clock * 3 |
4160 | if (pipe_config->requested_mode.clock * 3 |
4147 | > IRONLAKE_FDI_FREQ * 4) |
4161 | > IRONLAKE_FDI_FREQ * 4) |
4148 | return -EINVAL; |
4162 | return -EINVAL; |
4149 | } |
4163 | } |
4150 | 4164 | ||
4151 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4165 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4152 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4166 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4153 | */ |
4167 | */ |
4154 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4168 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4155 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4169 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4156 | return -EINVAL; |
4170 | return -EINVAL; |
4157 | 4171 | ||
4158 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4172 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4159 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4173 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4160 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4174 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4161 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4175 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4162 | * for lvds. */ |
4176 | * for lvds. */ |
4163 | pipe_config->pipe_bpp = 8*3; |
4177 | pipe_config->pipe_bpp = 8*3; |
4164 | } |
4178 | } |
4165 | 4179 | ||
4166 | if (HAS_IPS(dev)) |
4180 | if (HAS_IPS(dev)) |
4167 | hsw_compute_ips_config(crtc, pipe_config); |
4181 | hsw_compute_ips_config(crtc, pipe_config); |
4168 | 4182 | ||
4169 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
4183 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
4170 | * clock survives for now. */ |
4184 | * clock survives for now. */ |
4171 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
4185 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
4172 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4186 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4173 | 4187 | ||
4174 | if (pipe_config->has_pch_encoder) |
4188 | if (pipe_config->has_pch_encoder) |
4175 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4189 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4176 | 4190 | ||
4177 | return 0; |
4191 | return 0; |
4178 | } |
4192 | } |
4179 | 4193 | ||
4180 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4194 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4181 | { |
4195 | { |
4182 | return 400000; /* FIXME */ |
4196 | return 400000; /* FIXME */ |
4183 | } |
4197 | } |
4184 | 4198 | ||
4185 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4199 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4186 | { |
4200 | { |
4187 | return 400000; |
4201 | return 400000; |
4188 | } |
4202 | } |
4189 | 4203 | ||
4190 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4204 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4191 | { |
4205 | { |
4192 | return 333000; |
4206 | return 333000; |
4193 | } |
4207 | } |
4194 | 4208 | ||
4195 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4209 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4196 | { |
4210 | { |
4197 | return 200000; |
4211 | return 200000; |
4198 | } |
4212 | } |
4199 | 4213 | ||
4200 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4214 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4201 | { |
4215 | { |
4202 | u16 gcfgc = 0; |
4216 | u16 gcfgc = 0; |
4203 | 4217 | ||
4204 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4218 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4205 | 4219 | ||
4206 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4220 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4207 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4221 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4208 | return 267000; |
4222 | return 267000; |
4209 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4223 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4210 | return 333000; |
4224 | return 333000; |
4211 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4225 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4212 | return 444000; |
4226 | return 444000; |
4213 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4227 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4214 | return 200000; |
4228 | return 200000; |
4215 | default: |
4229 | default: |
4216 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
4230 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
4217 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4231 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4218 | return 133000; |
4232 | return 133000; |
4219 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4233 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4220 | return 167000; |
4234 | return 167000; |
4221 | } |
4235 | } |
4222 | } |
4236 | } |
4223 | 4237 | ||
4224 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4238 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4225 | { |
4239 | { |
4226 | u16 gcfgc = 0; |
4240 | u16 gcfgc = 0; |
4227 | 4241 | ||
4228 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4242 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4229 | 4243 | ||
4230 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4244 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4231 | return 133000; |
4245 | return 133000; |
4232 | else { |
4246 | else { |
4233 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4247 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4234 | case GC_DISPLAY_CLOCK_333_MHZ: |
4248 | case GC_DISPLAY_CLOCK_333_MHZ: |
4235 | return 333000; |
4249 | return 333000; |
4236 | default: |
4250 | default: |
4237 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4251 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4238 | return 190000; |
4252 | return 190000; |
4239 | } |
4253 | } |
4240 | } |
4254 | } |
4241 | } |
4255 | } |
4242 | 4256 | ||
4243 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4257 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4244 | { |
4258 | { |
4245 | return 266000; |
4259 | return 266000; |
4246 | } |
4260 | } |
4247 | 4261 | ||
4248 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4262 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4249 | { |
4263 | { |
4250 | u16 hpllcc = 0; |
4264 | u16 hpllcc = 0; |
4251 | /* Assume that the hardware is in the high speed state. This |
4265 | /* Assume that the hardware is in the high speed state. This |
4252 | * should be the default. |
4266 | * should be the default. |
4253 | */ |
4267 | */ |
4254 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4268 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4255 | case GC_CLOCK_133_200: |
4269 | case GC_CLOCK_133_200: |
4256 | case GC_CLOCK_100_200: |
4270 | case GC_CLOCK_100_200: |
4257 | return 200000; |
4271 | return 200000; |
4258 | case GC_CLOCK_166_250: |
4272 | case GC_CLOCK_166_250: |
4259 | return 250000; |
4273 | return 250000; |
4260 | case GC_CLOCK_100_133: |
4274 | case GC_CLOCK_100_133: |
4261 | return 133000; |
4275 | return 133000; |
4262 | } |
4276 | } |
4263 | 4277 | ||
4264 | /* Shouldn't happen */ |
4278 | /* Shouldn't happen */ |
4265 | return 0; |
4279 | return 0; |
4266 | } |
4280 | } |
4267 | 4281 | ||
4268 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4282 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4269 | { |
4283 | { |
4270 | return 133000; |
4284 | return 133000; |
4271 | } |
4285 | } |
4272 | 4286 | ||
4273 | static void |
4287 | static void |
4274 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4288 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4275 | { |
4289 | { |
4276 | while (*num > DATA_LINK_M_N_MASK || |
4290 | while (*num > DATA_LINK_M_N_MASK || |
4277 | *den > DATA_LINK_M_N_MASK) { |
4291 | *den > DATA_LINK_M_N_MASK) { |
4278 | *num >>= 1; |
4292 | *num >>= 1; |
4279 | *den >>= 1; |
4293 | *den >>= 1; |
4280 | } |
4294 | } |
4281 | } |
4295 | } |
4282 | 4296 | ||
4283 | static void compute_m_n(unsigned int m, unsigned int n, |
4297 | static void compute_m_n(unsigned int m, unsigned int n, |
4284 | uint32_t *ret_m, uint32_t *ret_n) |
4298 | uint32_t *ret_m, uint32_t *ret_n) |
4285 | { |
4299 | { |
4286 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
4300 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
4287 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
4301 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
4288 | intel_reduce_m_n_ratio(ret_m, ret_n); |
4302 | intel_reduce_m_n_ratio(ret_m, ret_n); |
4289 | } |
4303 | } |
4290 | 4304 | ||
4291 | void |
4305 | void |
4292 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
4306 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
4293 | int pixel_clock, int link_clock, |
4307 | int pixel_clock, int link_clock, |
4294 | struct intel_link_m_n *m_n) |
4308 | struct intel_link_m_n *m_n) |
4295 | { |
4309 | { |
4296 | m_n->tu = 64; |
4310 | m_n->tu = 64; |
4297 | 4311 | ||
4298 | compute_m_n(bits_per_pixel * pixel_clock, |
4312 | compute_m_n(bits_per_pixel * pixel_clock, |
4299 | link_clock * nlanes * 8, |
4313 | link_clock * nlanes * 8, |
4300 | &m_n->gmch_m, &m_n->gmch_n); |
4314 | &m_n->gmch_m, &m_n->gmch_n); |
4301 | 4315 | ||
4302 | compute_m_n(pixel_clock, link_clock, |
4316 | compute_m_n(pixel_clock, link_clock, |
4303 | &m_n->link_m, &m_n->link_n); |
4317 | &m_n->link_m, &m_n->link_n); |
4304 | } |
4318 | } |
4305 | 4319 | ||
4306 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4320 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4307 | { |
4321 | { |
4308 | if (i915_panel_use_ssc >= 0) |
4322 | if (i915_panel_use_ssc >= 0) |
4309 | return i915_panel_use_ssc != 0; |
4323 | return i915_panel_use_ssc != 0; |
4310 | return dev_priv->vbt.lvds_use_ssc |
4324 | return dev_priv->vbt.lvds_use_ssc |
4311 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4325 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4312 | } |
4326 | } |
4313 | 4327 | ||
4314 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4328 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4315 | { |
4329 | { |
4316 | struct drm_device *dev = crtc->dev; |
4330 | struct drm_device *dev = crtc->dev; |
4317 | struct drm_i915_private *dev_priv = dev->dev_private; |
4331 | struct drm_i915_private *dev_priv = dev->dev_private; |
4318 | int refclk = 27000; /* for DP & HDMI */ |
4332 | int refclk = 27000; /* for DP & HDMI */ |
4319 | 4333 | ||
4320 | return 100000; /* only one validated so far */ |
4334 | return 100000; /* only one validated so far */ |
4321 | 4335 | ||
4322 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
4336 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
4323 | refclk = 96000; |
4337 | refclk = 96000; |
4324 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4338 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4325 | if (intel_panel_use_ssc(dev_priv)) |
4339 | if (intel_panel_use_ssc(dev_priv)) |
4326 | refclk = 100000; |
4340 | refclk = 100000; |
4327 | else |
4341 | else |
4328 | refclk = 96000; |
4342 | refclk = 96000; |
4329 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4343 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4330 | refclk = 100000; |
4344 | refclk = 100000; |
4331 | } |
4345 | } |
4332 | 4346 | ||
4333 | return refclk; |
4347 | return refclk; |
4334 | } |
4348 | } |
4335 | 4349 | ||
4336 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4350 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4337 | { |
4351 | { |
4338 | struct drm_device *dev = crtc->dev; |
4352 | struct drm_device *dev = crtc->dev; |
4339 | struct drm_i915_private *dev_priv = dev->dev_private; |
4353 | struct drm_i915_private *dev_priv = dev->dev_private; |
4340 | int refclk; |
4354 | int refclk; |
4341 | 4355 | ||
4342 | if (IS_VALLEYVIEW(dev)) { |
4356 | if (IS_VALLEYVIEW(dev)) { |
4343 | refclk = vlv_get_refclk(crtc); |
4357 | refclk = vlv_get_refclk(crtc); |
4344 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4358 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4345 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4359 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4346 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
4360 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
4347 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4361 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4348 | refclk / 1000); |
4362 | refclk / 1000); |
4349 | } else if (!IS_GEN2(dev)) { |
4363 | } else if (!IS_GEN2(dev)) { |
4350 | refclk = 96000; |
4364 | refclk = 96000; |
4351 | } else { |
4365 | } else { |
4352 | refclk = 48000; |
4366 | refclk = 48000; |
4353 | } |
4367 | } |
4354 | 4368 | ||
4355 | return refclk; |
4369 | return refclk; |
4356 | } |
4370 | } |
4357 | 4371 | ||
4358 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4372 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4359 | { |
4373 | { |
4360 | return (1 << dpll->n) << 16 | dpll->m2; |
4374 | return (1 << dpll->n) << 16 | dpll->m2; |
4361 | } |
4375 | } |
4362 | 4376 | ||
4363 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4377 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4364 | { |
4378 | { |
4365 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
4379 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
4366 | } |
4380 | } |
4367 | 4381 | ||
4368 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4382 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4369 | intel_clock_t *reduced_clock) |
4383 | intel_clock_t *reduced_clock) |
4370 | { |
4384 | { |
4371 | struct drm_device *dev = crtc->base.dev; |
4385 | struct drm_device *dev = crtc->base.dev; |
4372 | struct drm_i915_private *dev_priv = dev->dev_private; |
4386 | struct drm_i915_private *dev_priv = dev->dev_private; |
4373 | int pipe = crtc->pipe; |
4387 | int pipe = crtc->pipe; |
4374 | u32 fp, fp2 = 0; |
4388 | u32 fp, fp2 = 0; |
4375 | 4389 | ||
4376 | if (IS_PINEVIEW(dev)) { |
4390 | if (IS_PINEVIEW(dev)) { |
4377 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
4391 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
4378 | if (reduced_clock) |
4392 | if (reduced_clock) |
4379 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
4393 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
4380 | } else { |
4394 | } else { |
4381 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4395 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4382 | if (reduced_clock) |
4396 | if (reduced_clock) |
4383 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4397 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4384 | } |
4398 | } |
4385 | 4399 | ||
4386 | I915_WRITE(FP0(pipe), fp); |
4400 | I915_WRITE(FP0(pipe), fp); |
4387 | crtc->config.dpll_hw_state.fp0 = fp; |
4401 | crtc->config.dpll_hw_state.fp0 = fp; |
4388 | 4402 | ||
4389 | crtc->lowfreq_avail = false; |
4403 | crtc->lowfreq_avail = false; |
4390 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4404 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4391 | reduced_clock && i915_powersave) { |
4405 | reduced_clock && i915_powersave) { |
4392 | I915_WRITE(FP1(pipe), fp2); |
4406 | I915_WRITE(FP1(pipe), fp2); |
4393 | crtc->config.dpll_hw_state.fp1 = fp2; |
4407 | crtc->config.dpll_hw_state.fp1 = fp2; |
4394 | crtc->lowfreq_avail = true; |
4408 | crtc->lowfreq_avail = true; |
4395 | } else { |
4409 | } else { |
4396 | I915_WRITE(FP1(pipe), fp); |
4410 | I915_WRITE(FP1(pipe), fp); |
4397 | crtc->config.dpll_hw_state.fp1 = fp; |
4411 | crtc->config.dpll_hw_state.fp1 = fp; |
4398 | } |
4412 | } |
4399 | } |
4413 | } |
4400 | 4414 | ||
4401 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4415 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4402 | { |
4416 | { |
4403 | u32 reg_val; |
4417 | u32 reg_val; |
4404 | 4418 | ||
4405 | /* |
4419 | /* |
4406 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4420 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4407 | * and set it to a reasonable value instead. |
4421 | * and set it to a reasonable value instead. |
4408 | */ |
4422 | */ |
4409 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4423 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4410 | reg_val &= 0xffffff00; |
4424 | reg_val &= 0xffffff00; |
4411 | reg_val |= 0x00000030; |
4425 | reg_val |= 0x00000030; |
4412 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4426 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4413 | 4427 | ||
4414 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4428 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4415 | reg_val &= 0x8cffffff; |
4429 | reg_val &= 0x8cffffff; |
4416 | reg_val = 0x8c000000; |
4430 | reg_val = 0x8c000000; |
4417 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4431 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4418 | 4432 | ||
4419 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4433 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4420 | reg_val &= 0xffffff00; |
4434 | reg_val &= 0xffffff00; |
4421 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4435 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4422 | 4436 | ||
4423 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4437 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4424 | reg_val &= 0x00ffffff; |
4438 | reg_val &= 0x00ffffff; |
4425 | reg_val |= 0xb0000000; |
4439 | reg_val |= 0xb0000000; |
4426 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4440 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4427 | } |
4441 | } |
4428 | 4442 | ||
4429 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4443 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4430 | struct intel_link_m_n *m_n) |
4444 | struct intel_link_m_n *m_n) |
4431 | { |
4445 | { |
4432 | struct drm_device *dev = crtc->base.dev; |
4446 | struct drm_device *dev = crtc->base.dev; |
4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
4447 | struct drm_i915_private *dev_priv = dev->dev_private; |
4434 | int pipe = crtc->pipe; |
4448 | int pipe = crtc->pipe; |
4435 | 4449 | ||
4436 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4450 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4437 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
4451 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
4438 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
4452 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
4439 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
4453 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
4440 | } |
4454 | } |
4441 | 4455 | ||
4442 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
4456 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
4443 | struct intel_link_m_n *m_n) |
4457 | struct intel_link_m_n *m_n) |
4444 | { |
4458 | { |
4445 | struct drm_device *dev = crtc->base.dev; |
4459 | struct drm_device *dev = crtc->base.dev; |
4446 | struct drm_i915_private *dev_priv = dev->dev_private; |
4460 | struct drm_i915_private *dev_priv = dev->dev_private; |
4447 | int pipe = crtc->pipe; |
4461 | int pipe = crtc->pipe; |
4448 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
4462 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
4449 | 4463 | ||
4450 | if (INTEL_INFO(dev)->gen >= 5) { |
4464 | if (INTEL_INFO(dev)->gen >= 5) { |
4451 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4465 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4452 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
4466 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
4453 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
4467 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
4454 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
4468 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
4455 | } else { |
4469 | } else { |
4456 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4470 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4457 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
4471 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
4458 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
4472 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
4459 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
4473 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
4460 | } |
4474 | } |
4461 | } |
4475 | } |
4462 | 4476 | ||
4463 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4477 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4464 | { |
4478 | { |
4465 | if (crtc->config.has_pch_encoder) |
4479 | if (crtc->config.has_pch_encoder) |
4466 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4480 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4467 | else |
4481 | else |
4468 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4482 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4469 | } |
4483 | } |
4470 | 4484 | ||
4471 | static void vlv_update_pll(struct intel_crtc *crtc) |
4485 | static void vlv_update_pll(struct intel_crtc *crtc) |
4472 | { |
4486 | { |
4473 | struct drm_device *dev = crtc->base.dev; |
4487 | struct drm_device *dev = crtc->base.dev; |
4474 | struct drm_i915_private *dev_priv = dev->dev_private; |
4488 | struct drm_i915_private *dev_priv = dev->dev_private; |
4475 | int pipe = crtc->pipe; |
4489 | int pipe = crtc->pipe; |
4476 | u32 dpll, mdiv; |
4490 | u32 dpll, mdiv; |
4477 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4491 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4478 | u32 coreclk, reg_val, dpll_md; |
4492 | u32 coreclk, reg_val, dpll_md; |
4479 | 4493 | ||
4480 | mutex_lock(&dev_priv->dpio_lock); |
4494 | mutex_lock(&dev_priv->dpio_lock); |
4481 | 4495 | ||
4482 | bestn = crtc->config.dpll.n; |
4496 | bestn = crtc->config.dpll.n; |
4483 | bestm1 = crtc->config.dpll.m1; |
4497 | bestm1 = crtc->config.dpll.m1; |
4484 | bestm2 = crtc->config.dpll.m2; |
4498 | bestm2 = crtc->config.dpll.m2; |
4485 | bestp1 = crtc->config.dpll.p1; |
4499 | bestp1 = crtc->config.dpll.p1; |
4486 | bestp2 = crtc->config.dpll.p2; |
4500 | bestp2 = crtc->config.dpll.p2; |
4487 | 4501 | ||
4488 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4502 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4489 | 4503 | ||
4490 | /* PLL B needs special handling */ |
4504 | /* PLL B needs special handling */ |
4491 | if (pipe) |
4505 | if (pipe) |
4492 | vlv_pllb_recal_opamp(dev_priv); |
4506 | vlv_pllb_recal_opamp(dev_priv); |
4493 | 4507 | ||
4494 | /* Set up Tx target for periodic Rcomp update */ |
4508 | /* Set up Tx target for periodic Rcomp update */ |
4495 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
4509 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
4496 | 4510 | ||
4497 | /* Disable target IRef on PLL */ |
4511 | /* Disable target IRef on PLL */ |
4498 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
4512 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
4499 | reg_val &= 0x00ffffff; |
4513 | reg_val &= 0x00ffffff; |
4500 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
4514 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
4501 | 4515 | ||
4502 | /* Disable fast lock */ |
4516 | /* Disable fast lock */ |
4503 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
4517 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
4504 | 4518 | ||
4505 | /* Set idtafcrecal before PLL is enabled */ |
4519 | /* Set idtafcrecal before PLL is enabled */ |
4506 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4520 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4507 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4521 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4508 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4522 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4509 | mdiv |= (1 << DPIO_K_SHIFT); |
4523 | mdiv |= (1 << DPIO_K_SHIFT); |
4510 | 4524 | ||
4511 | /* |
4525 | /* |
4512 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4526 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4513 | * but we don't support that). |
4527 | * but we don't support that). |
4514 | * Note: don't use the DAC post divider as it seems unstable. |
4528 | * Note: don't use the DAC post divider as it seems unstable. |
4515 | */ |
4529 | */ |
4516 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4530 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4517 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4531 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4518 | 4532 | ||
4519 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4533 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4520 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4534 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4521 | 4535 | ||
4522 | /* Set HBR and RBR LPF coefficients */ |
4536 | /* Set HBR and RBR LPF coefficients */ |
4523 | if (crtc->config.port_clock == 162000 || |
4537 | if (crtc->config.port_clock == 162000 || |
4524 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4538 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4525 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4539 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4526 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4540 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4527 | 0x009f0003); |
4541 | 0x009f0003); |
4528 | else |
4542 | else |
4529 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4543 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4530 | 0x00d0000f); |
4544 | 0x00d0000f); |
4531 | 4545 | ||
4532 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4546 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4533 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4547 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4534 | /* Use SSC source */ |
4548 | /* Use SSC source */ |
4535 | if (!pipe) |
4549 | if (!pipe) |
4536 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4550 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4537 | 0x0df40000); |
4551 | 0x0df40000); |
4538 | else |
4552 | else |
4539 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4553 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4540 | 0x0df70000); |
4554 | 0x0df70000); |
4541 | } else { /* HDMI or VGA */ |
4555 | } else { /* HDMI or VGA */ |
4542 | /* Use bend source */ |
4556 | /* Use bend source */ |
4543 | if (!pipe) |
4557 | if (!pipe) |
4544 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4558 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4545 | 0x0df70000); |
4559 | 0x0df70000); |
4546 | else |
4560 | else |
4547 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4561 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4548 | 0x0df40000); |
4562 | 0x0df40000); |
4549 | } |
4563 | } |
4550 | 4564 | ||
4551 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4565 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4552 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4566 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4553 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
4567 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
4554 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
4568 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
4555 | coreclk |= 0x01000000; |
4569 | coreclk |= 0x01000000; |
4556 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
4570 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
4557 | 4571 | ||
4558 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4572 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4559 | 4573 | ||
4560 | /* Enable DPIO clock input */ |
4574 | /* Enable DPIO clock input */ |
4561 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4575 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4562 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4576 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4563 | /* We should never disable this, set it here for state tracking */ |
4577 | /* We should never disable this, set it here for state tracking */ |
4564 | if (pipe == PIPE_B) |
4578 | if (pipe == PIPE_B) |
4565 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
4579 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
4566 | dpll |= DPLL_VCO_ENABLE; |
4580 | dpll |= DPLL_VCO_ENABLE; |
4567 | crtc->config.dpll_hw_state.dpll = dpll; |
4581 | crtc->config.dpll_hw_state.dpll = dpll; |
4568 | 4582 | ||
4569 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4583 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4570 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4584 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4571 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4585 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4572 | 4586 | ||
4573 | if (crtc->config.has_dp_encoder) |
4587 | if (crtc->config.has_dp_encoder) |
4574 | intel_dp_set_m_n(crtc); |
4588 | intel_dp_set_m_n(crtc); |
4575 | 4589 | ||
4576 | mutex_unlock(&dev_priv->dpio_lock); |
4590 | mutex_unlock(&dev_priv->dpio_lock); |
4577 | } |
4591 | } |
4578 | 4592 | ||
4579 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4593 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4580 | intel_clock_t *reduced_clock, |
4594 | intel_clock_t *reduced_clock, |
4581 | int num_connectors) |
4595 | int num_connectors) |
4582 | { |
4596 | { |
4583 | struct drm_device *dev = crtc->base.dev; |
4597 | struct drm_device *dev = crtc->base.dev; |
4584 | struct drm_i915_private *dev_priv = dev->dev_private; |
4598 | struct drm_i915_private *dev_priv = dev->dev_private; |
4585 | u32 dpll; |
4599 | u32 dpll; |
4586 | bool is_sdvo; |
4600 | bool is_sdvo; |
4587 | struct dpll *clock = &crtc->config.dpll; |
4601 | struct dpll *clock = &crtc->config.dpll; |
4588 | 4602 | ||
4589 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4603 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4590 | 4604 | ||
4591 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4605 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4592 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
4606 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
4593 | 4607 | ||
4594 | dpll = DPLL_VGA_MODE_DIS; |
4608 | dpll = DPLL_VGA_MODE_DIS; |
4595 | 4609 | ||
4596 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
4610 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
4597 | dpll |= DPLLB_MODE_LVDS; |
4611 | dpll |= DPLLB_MODE_LVDS; |
4598 | else |
4612 | else |
4599 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4613 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4600 | 4614 | ||
4601 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4615 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4602 | dpll |= (crtc->config.pixel_multiplier - 1) |
4616 | dpll |= (crtc->config.pixel_multiplier - 1) |
4603 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
4617 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
4604 | } |
4618 | } |
4605 | 4619 | ||
4606 | if (is_sdvo) |
4620 | if (is_sdvo) |
4607 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4621 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4608 | 4622 | ||
4609 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4623 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4610 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4624 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4611 | 4625 | ||
4612 | /* compute bitmask from p1 value */ |
4626 | /* compute bitmask from p1 value */ |
4613 | if (IS_PINEVIEW(dev)) |
4627 | if (IS_PINEVIEW(dev)) |
4614 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4628 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4615 | else { |
4629 | else { |
4616 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4630 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4617 | if (IS_G4X(dev) && reduced_clock) |
4631 | if (IS_G4X(dev) && reduced_clock) |
4618 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4632 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4619 | } |
4633 | } |
4620 | switch (clock->p2) { |
4634 | switch (clock->p2) { |
4621 | case 5: |
4635 | case 5: |
4622 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4636 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4623 | break; |
4637 | break; |
4624 | case 7: |
4638 | case 7: |
4625 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4639 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4626 | break; |
4640 | break; |
4627 | case 10: |
4641 | case 10: |
4628 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4642 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4629 | break; |
4643 | break; |
4630 | case 14: |
4644 | case 14: |
4631 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4645 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4632 | break; |
4646 | break; |
4633 | } |
4647 | } |
4634 | if (INTEL_INFO(dev)->gen >= 4) |
4648 | if (INTEL_INFO(dev)->gen >= 4) |
4635 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4649 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4636 | 4650 | ||
4637 | if (crtc->config.sdvo_tv_clock) |
4651 | if (crtc->config.sdvo_tv_clock) |
4638 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4652 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4639 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4653 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4640 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4654 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4641 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4655 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4642 | else |
4656 | else |
4643 | dpll |= PLL_REF_INPUT_DREFCLK; |
4657 | dpll |= PLL_REF_INPUT_DREFCLK; |
4644 | 4658 | ||
4645 | dpll |= DPLL_VCO_ENABLE; |
4659 | dpll |= DPLL_VCO_ENABLE; |
4646 | crtc->config.dpll_hw_state.dpll = dpll; |
4660 | crtc->config.dpll_hw_state.dpll = dpll; |
4647 | 4661 | ||
4648 | if (INTEL_INFO(dev)->gen >= 4) { |
4662 | if (INTEL_INFO(dev)->gen >= 4) { |
4649 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4663 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4650 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4664 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4651 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4665 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4652 | } |
4666 | } |
4653 | 4667 | ||
4654 | if (crtc->config.has_dp_encoder) |
4668 | if (crtc->config.has_dp_encoder) |
4655 | intel_dp_set_m_n(crtc); |
4669 | intel_dp_set_m_n(crtc); |
4656 | } |
4670 | } |
4657 | 4671 | ||
4658 | static void i8xx_update_pll(struct intel_crtc *crtc, |
4672 | static void i8xx_update_pll(struct intel_crtc *crtc, |
4659 | intel_clock_t *reduced_clock, |
4673 | intel_clock_t *reduced_clock, |
4660 | int num_connectors) |
4674 | int num_connectors) |
4661 | { |
4675 | { |
4662 | struct drm_device *dev = crtc->base.dev; |
4676 | struct drm_device *dev = crtc->base.dev; |
4663 | struct drm_i915_private *dev_priv = dev->dev_private; |
4677 | struct drm_i915_private *dev_priv = dev->dev_private; |
4664 | u32 dpll; |
4678 | u32 dpll; |
4665 | struct dpll *clock = &crtc->config.dpll; |
4679 | struct dpll *clock = &crtc->config.dpll; |
4666 | 4680 | ||
4667 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4681 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4668 | 4682 | ||
4669 | dpll = DPLL_VGA_MODE_DIS; |
4683 | dpll = DPLL_VGA_MODE_DIS; |
4670 | 4684 | ||
4671 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
4685 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
4672 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4686 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4673 | } else { |
4687 | } else { |
4674 | if (clock->p1 == 2) |
4688 | if (clock->p1 == 2) |
4675 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4689 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4676 | else |
4690 | else |
4677 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4691 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4678 | if (clock->p2 == 4) |
4692 | if (clock->p2 == 4) |
4679 | dpll |= PLL_P2_DIVIDE_BY_4; |
4693 | dpll |= PLL_P2_DIVIDE_BY_4; |
4680 | } |
4694 | } |
4681 | 4695 | ||
4682 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4696 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4683 | dpll |= DPLL_DVO_2X_MODE; |
4697 | dpll |= DPLL_DVO_2X_MODE; |
4684 | 4698 | ||
4685 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4699 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4686 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4700 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4687 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4701 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4688 | else |
4702 | else |
4689 | dpll |= PLL_REF_INPUT_DREFCLK; |
4703 | dpll |= PLL_REF_INPUT_DREFCLK; |
4690 | 4704 | ||
4691 | dpll |= DPLL_VCO_ENABLE; |
4705 | dpll |= DPLL_VCO_ENABLE; |
4692 | crtc->config.dpll_hw_state.dpll = dpll; |
4706 | crtc->config.dpll_hw_state.dpll = dpll; |
4693 | } |
4707 | } |
4694 | 4708 | ||
4695 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
4709 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
4696 | { |
4710 | { |
4697 | struct drm_device *dev = intel_crtc->base.dev; |
4711 | struct drm_device *dev = intel_crtc->base.dev; |
4698 | struct drm_i915_private *dev_priv = dev->dev_private; |
4712 | struct drm_i915_private *dev_priv = dev->dev_private; |
4699 | enum pipe pipe = intel_crtc->pipe; |
4713 | enum pipe pipe = intel_crtc->pipe; |
4700 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4714 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4701 | struct drm_display_mode *adjusted_mode = |
4715 | struct drm_display_mode *adjusted_mode = |
4702 | &intel_crtc->config.adjusted_mode; |
4716 | &intel_crtc->config.adjusted_mode; |
4703 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4717 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4704 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4718 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4705 | 4719 | ||
4706 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4720 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4707 | * the hw state checker will get angry at the mismatch. */ |
4721 | * the hw state checker will get angry at the mismatch. */ |
4708 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
4722 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
4709 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
4723 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
4710 | 4724 | ||
4711 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4725 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4712 | /* the chip adds 2 halflines automatically */ |
4726 | /* the chip adds 2 halflines automatically */ |
4713 | crtc_vtotal -= 1; |
4727 | crtc_vtotal -= 1; |
4714 | crtc_vblank_end -= 1; |
4728 | crtc_vblank_end -= 1; |
4715 | vsyncshift = adjusted_mode->crtc_hsync_start |
4729 | vsyncshift = adjusted_mode->crtc_hsync_start |
4716 | - adjusted_mode->crtc_htotal / 2; |
4730 | - adjusted_mode->crtc_htotal / 2; |
4717 | } else { |
4731 | } else { |
4718 | vsyncshift = 0; |
4732 | vsyncshift = 0; |
4719 | } |
4733 | } |
4720 | 4734 | ||
4721 | if (INTEL_INFO(dev)->gen > 3) |
4735 | if (INTEL_INFO(dev)->gen > 3) |
4722 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
4736 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
4723 | 4737 | ||
4724 | I915_WRITE(HTOTAL(cpu_transcoder), |
4738 | I915_WRITE(HTOTAL(cpu_transcoder), |
4725 | (adjusted_mode->crtc_hdisplay - 1) | |
4739 | (adjusted_mode->crtc_hdisplay - 1) | |
4726 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4740 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4727 | I915_WRITE(HBLANK(cpu_transcoder), |
4741 | I915_WRITE(HBLANK(cpu_transcoder), |
4728 | (adjusted_mode->crtc_hblank_start - 1) | |
4742 | (adjusted_mode->crtc_hblank_start - 1) | |
4729 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4743 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4730 | I915_WRITE(HSYNC(cpu_transcoder), |
4744 | I915_WRITE(HSYNC(cpu_transcoder), |
4731 | (adjusted_mode->crtc_hsync_start - 1) | |
4745 | (adjusted_mode->crtc_hsync_start - 1) | |
4732 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4746 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4733 | 4747 | ||
4734 | I915_WRITE(VTOTAL(cpu_transcoder), |
4748 | I915_WRITE(VTOTAL(cpu_transcoder), |
4735 | (adjusted_mode->crtc_vdisplay - 1) | |
4749 | (adjusted_mode->crtc_vdisplay - 1) | |
4736 | ((crtc_vtotal - 1) << 16)); |
4750 | ((crtc_vtotal - 1) << 16)); |
4737 | I915_WRITE(VBLANK(cpu_transcoder), |
4751 | I915_WRITE(VBLANK(cpu_transcoder), |
4738 | (adjusted_mode->crtc_vblank_start - 1) | |
4752 | (adjusted_mode->crtc_vblank_start - 1) | |
4739 | ((crtc_vblank_end - 1) << 16)); |
4753 | ((crtc_vblank_end - 1) << 16)); |
4740 | I915_WRITE(VSYNC(cpu_transcoder), |
4754 | I915_WRITE(VSYNC(cpu_transcoder), |
4741 | (adjusted_mode->crtc_vsync_start - 1) | |
4755 | (adjusted_mode->crtc_vsync_start - 1) | |
4742 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4756 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4743 | 4757 | ||
4744 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4758 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4745 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
4759 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
4746 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
4760 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
4747 | * bits. */ |
4761 | * bits. */ |
4748 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
4762 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
4749 | (pipe == PIPE_B || pipe == PIPE_C)) |
4763 | (pipe == PIPE_B || pipe == PIPE_C)) |
4750 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
4764 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
4751 | 4765 | ||
4752 | /* pipesrc controls the size that is scaled from, which should |
4766 | /* pipesrc controls the size that is scaled from, which should |
4753 | * always be the user's requested size. |
4767 | * always be the user's requested size. |
4754 | */ |
4768 | */ |
4755 | I915_WRITE(PIPESRC(pipe), |
4769 | I915_WRITE(PIPESRC(pipe), |
4756 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4770 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4757 | } |
4771 | } |
4758 | 4772 | ||
4759 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4773 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4760 | struct intel_crtc_config *pipe_config) |
4774 | struct intel_crtc_config *pipe_config) |
4761 | { |
4775 | { |
4762 | struct drm_device *dev = crtc->base.dev; |
4776 | struct drm_device *dev = crtc->base.dev; |
4763 | struct drm_i915_private *dev_priv = dev->dev_private; |
4777 | struct drm_i915_private *dev_priv = dev->dev_private; |
4764 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
4778 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
4765 | uint32_t tmp; |
4779 | uint32_t tmp; |
4766 | 4780 | ||
4767 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
4781 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
4768 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
4782 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
4769 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
4783 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
4770 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
4784 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
4771 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
4785 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
4772 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
4786 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
4773 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
4787 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
4774 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
4788 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
4775 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
4789 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
4776 | 4790 | ||
4777 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
4791 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
4778 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
4792 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
4779 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
4793 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
4780 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
4794 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
4781 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
4795 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
4782 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
4796 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
4783 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
4797 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
4784 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
4798 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
4785 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
4799 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
4786 | 4800 | ||
4787 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
4801 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
4788 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
4802 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
4789 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
4803 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
4790 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
4804 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
4791 | } |
4805 | } |
4792 | 4806 | ||
4793 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
4807 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
4794 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
4808 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
4795 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
4809 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
4796 | } |
4810 | } |
4797 | 4811 | ||
4798 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4812 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4799 | struct intel_crtc_config *pipe_config) |
4813 | struct intel_crtc_config *pipe_config) |
4800 | { |
4814 | { |
4801 | struct drm_crtc *crtc = &intel_crtc->base; |
4815 | struct drm_crtc *crtc = &intel_crtc->base; |
4802 | 4816 | ||
4803 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
4817 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
4804 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
4818 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
4805 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
4819 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
4806 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
4820 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
4807 | 4821 | ||
4808 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
4822 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
4809 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
4823 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
4810 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
4824 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
4811 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
4825 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
4812 | 4826 | ||
4813 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
4827 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
4814 | 4828 | ||
4815 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
4829 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
4816 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4830 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4817 | } |
4831 | } |
4818 | 4832 | ||
4819 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4833 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4820 | { |
4834 | { |
4821 | struct drm_device *dev = intel_crtc->base.dev; |
4835 | struct drm_device *dev = intel_crtc->base.dev; |
4822 | struct drm_i915_private *dev_priv = dev->dev_private; |
4836 | struct drm_i915_private *dev_priv = dev->dev_private; |
4823 | uint32_t pipeconf; |
4837 | uint32_t pipeconf; |
4824 | 4838 | ||
4825 | pipeconf = 0; |
4839 | pipeconf = 0; |
4826 | 4840 | ||
4827 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4841 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4828 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
4842 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
4829 | pipeconf |= PIPECONF_ENABLE; |
4843 | pipeconf |= PIPECONF_ENABLE; |
4830 | 4844 | ||
4831 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4845 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4832 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4846 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4833 | * core speed. |
4847 | * core speed. |
4834 | * |
4848 | * |
4835 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4849 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4836 | * pipe == 0 check? |
4850 | * pipe == 0 check? |
4837 | */ |
4851 | */ |
4838 | if (intel_crtc->config.requested_mode.clock > |
4852 | if (intel_crtc->config.requested_mode.clock > |
4839 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4853 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4840 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4854 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4841 | } |
4855 | } |
4842 | 4856 | ||
4843 | /* only g4x and later have fancy bpc/dither controls */ |
4857 | /* only g4x and later have fancy bpc/dither controls */ |
4844 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
4858 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
4845 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4859 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4846 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
4860 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
4847 | pipeconf |= PIPECONF_DITHER_EN | |
4861 | pipeconf |= PIPECONF_DITHER_EN | |
4848 | PIPECONF_DITHER_TYPE_SP; |
4862 | PIPECONF_DITHER_TYPE_SP; |
4849 | 4863 | ||
4850 | switch (intel_crtc->config.pipe_bpp) { |
4864 | switch (intel_crtc->config.pipe_bpp) { |
4851 | case 18: |
4865 | case 18: |
4852 | pipeconf |= PIPECONF_6BPC; |
4866 | pipeconf |= PIPECONF_6BPC; |
4853 | break; |
4867 | break; |
4854 | case 24: |
4868 | case 24: |
4855 | pipeconf |= PIPECONF_8BPC; |
4869 | pipeconf |= PIPECONF_8BPC; |
4856 | break; |
4870 | break; |
4857 | case 30: |
4871 | case 30: |
4858 | pipeconf |= PIPECONF_10BPC; |
4872 | pipeconf |= PIPECONF_10BPC; |
4859 | break; |
4873 | break; |
4860 | default: |
4874 | default: |
4861 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
4875 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
4862 | BUG(); |
4876 | BUG(); |
4863 | } |
4877 | } |
4864 | } |
4878 | } |
4865 | 4879 | ||
4866 | if (HAS_PIPE_CXSR(dev)) { |
4880 | if (HAS_PIPE_CXSR(dev)) { |
4867 | if (intel_crtc->lowfreq_avail) { |
4881 | if (intel_crtc->lowfreq_avail) { |
4868 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4882 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4869 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4883 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4870 | } else { |
4884 | } else { |
4871 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4885 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4872 | } |
4886 | } |
4873 | } |
4887 | } |
4874 | 4888 | ||
4875 | if (!IS_GEN2(dev) && |
4889 | if (!IS_GEN2(dev) && |
4876 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
4890 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
4877 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4891 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4878 | else |
4892 | else |
4879 | pipeconf |= PIPECONF_PROGRESSIVE; |
4893 | pipeconf |= PIPECONF_PROGRESSIVE; |
4880 | 4894 | ||
4881 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4895 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4882 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
4896 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
4883 | 4897 | ||
4884 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4898 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4885 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
4899 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
4886 | } |
4900 | } |
4887 | 4901 | ||
4888 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4902 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4889 | int x, int y, |
4903 | int x, int y, |
4890 | struct drm_framebuffer *fb) |
4904 | struct drm_framebuffer *fb) |
4891 | { |
4905 | { |
4892 | struct drm_device *dev = crtc->dev; |
4906 | struct drm_device *dev = crtc->dev; |
4893 | struct drm_i915_private *dev_priv = dev->dev_private; |
4907 | struct drm_i915_private *dev_priv = dev->dev_private; |
4894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4895 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4909 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4896 | int pipe = intel_crtc->pipe; |
4910 | int pipe = intel_crtc->pipe; |
4897 | int plane = intel_crtc->plane; |
4911 | int plane = intel_crtc->plane; |
4898 | int refclk, num_connectors = 0; |
4912 | int refclk, num_connectors = 0; |
4899 | intel_clock_t clock, reduced_clock; |
4913 | intel_clock_t clock, reduced_clock; |
4900 | u32 dspcntr; |
4914 | u32 dspcntr; |
4901 | bool ok, has_reduced_clock = false; |
4915 | bool ok, has_reduced_clock = false; |
4902 | bool is_lvds = false; |
4916 | bool is_lvds = false; |
4903 | struct intel_encoder *encoder; |
4917 | struct intel_encoder *encoder; |
4904 | const intel_limit_t *limit; |
4918 | const intel_limit_t *limit; |
4905 | int ret; |
4919 | int ret; |
4906 | 4920 | ||
4907 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4921 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4908 | switch (encoder->type) { |
4922 | switch (encoder->type) { |
4909 | case INTEL_OUTPUT_LVDS: |
4923 | case INTEL_OUTPUT_LVDS: |
4910 | is_lvds = true; |
4924 | is_lvds = true; |
4911 | break; |
4925 | break; |
4912 | } |
4926 | } |
4913 | 4927 | ||
4914 | num_connectors++; |
4928 | num_connectors++; |
4915 | } |
4929 | } |
4916 | 4930 | ||
4917 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4931 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4918 | 4932 | ||
4919 | /* |
4933 | /* |
4920 | * Returns a set of divisors for the desired target clock with the given |
4934 | * Returns a set of divisors for the desired target clock with the given |
4921 | * refclk, or FALSE. The returned values represent the clock equation: |
4935 | * refclk, or FALSE. The returned values represent the clock equation: |
4922 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4923 | */ |
4937 | */ |
4924 | limit = intel_limit(crtc, refclk); |
4938 | limit = intel_limit(crtc, refclk); |
4925 | ok = dev_priv->display.find_dpll(limit, crtc, |
4939 | ok = dev_priv->display.find_dpll(limit, crtc, |
4926 | intel_crtc->config.port_clock, |
4940 | intel_crtc->config.port_clock, |
4927 | refclk, NULL, &clock); |
4941 | refclk, NULL, &clock); |
4928 | if (!ok && !intel_crtc->config.clock_set) { |
4942 | if (!ok && !intel_crtc->config.clock_set) { |
4929 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4943 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4930 | return -EINVAL; |
4944 | return -EINVAL; |
4931 | } |
4945 | } |
4932 | 4946 | ||
4933 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4947 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4934 | /* |
4948 | /* |
4935 | * Ensure we match the reduced clock's P to the target clock. |
4949 | * Ensure we match the reduced clock's P to the target clock. |
4936 | * If the clocks don't match, we can't switch the display clock |
4950 | * If the clocks don't match, we can't switch the display clock |
4937 | * by using the FP0/FP1. In such case we will disable the LVDS |
4951 | * by using the FP0/FP1. In such case we will disable the LVDS |
4938 | * downclock feature. |
4952 | * downclock feature. |
4939 | */ |
4953 | */ |
4940 | has_reduced_clock = |
4954 | has_reduced_clock = |
4941 | dev_priv->display.find_dpll(limit, crtc, |
4955 | dev_priv->display.find_dpll(limit, crtc, |
4942 | dev_priv->lvds_downclock, |
4956 | dev_priv->lvds_downclock, |
4943 | refclk, &clock, |
4957 | refclk, &clock, |
4944 | &reduced_clock); |
4958 | &reduced_clock); |
4945 | } |
4959 | } |
4946 | /* Compat-code for transition, will disappear. */ |
4960 | /* Compat-code for transition, will disappear. */ |
4947 | if (!intel_crtc->config.clock_set) { |
4961 | if (!intel_crtc->config.clock_set) { |
4948 | intel_crtc->config.dpll.n = clock.n; |
4962 | intel_crtc->config.dpll.n = clock.n; |
4949 | intel_crtc->config.dpll.m1 = clock.m1; |
4963 | intel_crtc->config.dpll.m1 = clock.m1; |
4950 | intel_crtc->config.dpll.m2 = clock.m2; |
4964 | intel_crtc->config.dpll.m2 = clock.m2; |
4951 | intel_crtc->config.dpll.p1 = clock.p1; |
4965 | intel_crtc->config.dpll.p1 = clock.p1; |
4952 | intel_crtc->config.dpll.p2 = clock.p2; |
4966 | intel_crtc->config.dpll.p2 = clock.p2; |
4953 | } |
4967 | } |
4954 | 4968 | ||
4955 | if (IS_GEN2(dev)) |
4969 | if (IS_GEN2(dev)) |
4956 | i8xx_update_pll(intel_crtc, |
4970 | i8xx_update_pll(intel_crtc, |
4957 | has_reduced_clock ? &reduced_clock : NULL, |
4971 | has_reduced_clock ? &reduced_clock : NULL, |
4958 | num_connectors); |
4972 | num_connectors); |
4959 | else if (IS_VALLEYVIEW(dev)) |
4973 | else if (IS_VALLEYVIEW(dev)) |
4960 | vlv_update_pll(intel_crtc); |
4974 | vlv_update_pll(intel_crtc); |
4961 | else |
4975 | else |
4962 | i9xx_update_pll(intel_crtc, |
4976 | i9xx_update_pll(intel_crtc, |
4963 | has_reduced_clock ? &reduced_clock : NULL, |
4977 | has_reduced_clock ? &reduced_clock : NULL, |
4964 | num_connectors); |
4978 | num_connectors); |
4965 | 4979 | ||
4966 | /* Set up the display plane register */ |
4980 | /* Set up the display plane register */ |
4967 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4981 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4968 | 4982 | ||
4969 | if (!IS_VALLEYVIEW(dev)) { |
4983 | if (!IS_VALLEYVIEW(dev)) { |
4970 | if (pipe == 0) |
4984 | if (pipe == 0) |
4971 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4985 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4972 | else |
4986 | else |
4973 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4987 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4974 | } |
4988 | } |
4975 | 4989 | ||
4976 | intel_set_pipe_timings(intel_crtc); |
4990 | intel_set_pipe_timings(intel_crtc); |
4977 | 4991 | ||
4978 | /* pipesrc and dspsize control the size that is scaled from, |
4992 | /* pipesrc and dspsize control the size that is scaled from, |
4979 | * which should always be the user's requested size. |
4993 | * which should always be the user's requested size. |
4980 | */ |
4994 | */ |
4981 | I915_WRITE(DSPSIZE(plane), |
4995 | I915_WRITE(DSPSIZE(plane), |
4982 | ((mode->vdisplay - 1) << 16) | |
4996 | ((mode->vdisplay - 1) << 16) | |
4983 | (mode->hdisplay - 1)); |
4997 | (mode->hdisplay - 1)); |
4984 | I915_WRITE(DSPPOS(plane), 0); |
4998 | I915_WRITE(DSPPOS(plane), 0); |
4985 | 4999 | ||
4986 | i9xx_set_pipeconf(intel_crtc); |
5000 | i9xx_set_pipeconf(intel_crtc); |
4987 | 5001 | ||
4988 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5002 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4989 | POSTING_READ(DSPCNTR(plane)); |
5003 | POSTING_READ(DSPCNTR(plane)); |
4990 | 5004 | ||
4991 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5005 | ret = intel_pipe_set_base(crtc, x, y, fb); |
4992 | 5006 | ||
4993 | intel_update_watermarks(dev); |
5007 | intel_update_watermarks(dev); |
4994 | 5008 | ||
4995 | return ret; |
5009 | return ret; |
4996 | } |
5010 | } |
4997 | 5011 | ||
4998 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5012 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
4999 | struct intel_crtc_config *pipe_config) |
5013 | struct intel_crtc_config *pipe_config) |
5000 | { |
5014 | { |
5001 | struct drm_device *dev = crtc->base.dev; |
5015 | struct drm_device *dev = crtc->base.dev; |
5002 | struct drm_i915_private *dev_priv = dev->dev_private; |
5016 | struct drm_i915_private *dev_priv = dev->dev_private; |
5003 | uint32_t tmp; |
5017 | uint32_t tmp; |
5004 | 5018 | ||
5005 | tmp = I915_READ(PFIT_CONTROL); |
5019 | tmp = I915_READ(PFIT_CONTROL); |
5006 | if (!(tmp & PFIT_ENABLE)) |
5020 | if (!(tmp & PFIT_ENABLE)) |
5007 | return; |
5021 | return; |
5008 | 5022 | ||
5009 | /* Check whether the pfit is attached to our pipe. */ |
5023 | /* Check whether the pfit is attached to our pipe. */ |
5010 | if (INTEL_INFO(dev)->gen < 4) { |
5024 | if (INTEL_INFO(dev)->gen < 4) { |
5011 | if (crtc->pipe != PIPE_B) |
5025 | if (crtc->pipe != PIPE_B) |
5012 | return; |
5026 | return; |
5013 | } else { |
5027 | } else { |
5014 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
5028 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
5015 | return; |
5029 | return; |
5016 | } |
5030 | } |
5017 | 5031 | ||
5018 | pipe_config->gmch_pfit.control = tmp; |
5032 | pipe_config->gmch_pfit.control = tmp; |
5019 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5033 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5020 | if (INTEL_INFO(dev)->gen < 5) |
5034 | if (INTEL_INFO(dev)->gen < 5) |
5021 | pipe_config->gmch_pfit.lvds_border_bits = |
5035 | pipe_config->gmch_pfit.lvds_border_bits = |
5022 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5036 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5023 | } |
5037 | } |
5024 | 5038 | ||
5025 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5039 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5026 | struct intel_crtc_config *pipe_config) |
5040 | struct intel_crtc_config *pipe_config) |
5027 | { |
5041 | { |
5028 | struct drm_device *dev = crtc->base.dev; |
5042 | struct drm_device *dev = crtc->base.dev; |
5029 | struct drm_i915_private *dev_priv = dev->dev_private; |
5043 | struct drm_i915_private *dev_priv = dev->dev_private; |
5030 | int pipe = pipe_config->cpu_transcoder; |
5044 | int pipe = pipe_config->cpu_transcoder; |
5031 | intel_clock_t clock; |
5045 | intel_clock_t clock; |
5032 | u32 mdiv; |
5046 | u32 mdiv; |
5033 | int refclk = 100000; |
5047 | int refclk = 100000; |
5034 | 5048 | ||
5035 | mutex_lock(&dev_priv->dpio_lock); |
5049 | mutex_lock(&dev_priv->dpio_lock); |
5036 | mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
5050 | mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
5037 | mutex_unlock(&dev_priv->dpio_lock); |
5051 | mutex_unlock(&dev_priv->dpio_lock); |
5038 | 5052 | ||
5039 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5053 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5040 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5054 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5041 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
5055 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
5042 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
5056 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
5043 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
5057 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
5044 | 5058 | ||
5045 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
5059 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
5046 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
5060 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
5047 | 5061 | ||
5048 | pipe_config->adjusted_mode.clock = clock.dot / 10; |
5062 | pipe_config->adjusted_mode.clock = clock.dot / 10; |
5049 | } |
5063 | } |
5050 | 5064 | ||
5051 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5065 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5052 | struct intel_crtc_config *pipe_config) |
5066 | struct intel_crtc_config *pipe_config) |
5053 | { |
5067 | { |
5054 | struct drm_device *dev = crtc->base.dev; |
5068 | struct drm_device *dev = crtc->base.dev; |
5055 | struct drm_i915_private *dev_priv = dev->dev_private; |
5069 | struct drm_i915_private *dev_priv = dev->dev_private; |
5056 | uint32_t tmp; |
5070 | uint32_t tmp; |
5057 | 5071 | ||
5058 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5072 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5059 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5073 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5060 | 5074 | ||
5061 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5075 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5062 | if (!(tmp & PIPECONF_ENABLE)) |
5076 | if (!(tmp & PIPECONF_ENABLE)) |
5063 | return false; |
5077 | return false; |
5064 | 5078 | ||
5065 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5079 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5066 | switch (tmp & PIPECONF_BPC_MASK) { |
5080 | switch (tmp & PIPECONF_BPC_MASK) { |
5067 | case PIPECONF_6BPC: |
5081 | case PIPECONF_6BPC: |
5068 | pipe_config->pipe_bpp = 18; |
5082 | pipe_config->pipe_bpp = 18; |
5069 | break; |
5083 | break; |
5070 | case PIPECONF_8BPC: |
5084 | case PIPECONF_8BPC: |
5071 | pipe_config->pipe_bpp = 24; |
5085 | pipe_config->pipe_bpp = 24; |
5072 | break; |
5086 | break; |
5073 | case PIPECONF_10BPC: |
5087 | case PIPECONF_10BPC: |
5074 | pipe_config->pipe_bpp = 30; |
5088 | pipe_config->pipe_bpp = 30; |
5075 | break; |
5089 | break; |
5076 | default: |
5090 | default: |
5077 | break; |
5091 | break; |
5078 | } |
5092 | } |
5079 | } |
5093 | } |
5080 | 5094 | ||
5081 | intel_get_pipe_timings(crtc, pipe_config); |
5095 | intel_get_pipe_timings(crtc, pipe_config); |
5082 | 5096 | ||
5083 | i9xx_get_pfit_config(crtc, pipe_config); |
5097 | i9xx_get_pfit_config(crtc, pipe_config); |
5084 | 5098 | ||
5085 | if (INTEL_INFO(dev)->gen >= 4) { |
5099 | if (INTEL_INFO(dev)->gen >= 4) { |
5086 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
5100 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
5087 | pipe_config->pixel_multiplier = |
5101 | pipe_config->pixel_multiplier = |
5088 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
5102 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
5089 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
5103 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
5090 | pipe_config->dpll_hw_state.dpll_md = tmp; |
5104 | pipe_config->dpll_hw_state.dpll_md = tmp; |
5091 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5105 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5092 | tmp = I915_READ(DPLL(crtc->pipe)); |
5106 | tmp = I915_READ(DPLL(crtc->pipe)); |
5093 | pipe_config->pixel_multiplier = |
5107 | pipe_config->pixel_multiplier = |
5094 | ((tmp & SDVO_MULTIPLIER_MASK) |
5108 | ((tmp & SDVO_MULTIPLIER_MASK) |
5095 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
5109 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
5096 | } else { |
5110 | } else { |
5097 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
5111 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
5098 | * port and will be fixed up in the encoder->get_config |
5112 | * port and will be fixed up in the encoder->get_config |
5099 | * function. */ |
5113 | * function. */ |
5100 | pipe_config->pixel_multiplier = 1; |
5114 | pipe_config->pixel_multiplier = 1; |
5101 | } |
5115 | } |
5102 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5116 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5103 | if (!IS_VALLEYVIEW(dev)) { |
5117 | if (!IS_VALLEYVIEW(dev)) { |
5104 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5118 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5105 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5119 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5106 | } else { |
5120 | } else { |
5107 | /* Mask out read-only status bits. */ |
5121 | /* Mask out read-only status bits. */ |
5108 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5122 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5109 | DPLL_PORTC_READY_MASK | |
5123 | DPLL_PORTC_READY_MASK | |
5110 | DPLL_PORTB_READY_MASK); |
5124 | DPLL_PORTB_READY_MASK); |
5111 | } |
5125 | } |
5112 | 5126 | ||
5113 | return true; |
5127 | return true; |
5114 | } |
5128 | } |
5115 | 5129 | ||
5116 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5130 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5117 | { |
5131 | { |
5118 | struct drm_i915_private *dev_priv = dev->dev_private; |
5132 | struct drm_i915_private *dev_priv = dev->dev_private; |
5119 | struct drm_mode_config *mode_config = &dev->mode_config; |
5133 | struct drm_mode_config *mode_config = &dev->mode_config; |
5120 | struct intel_encoder *encoder; |
5134 | struct intel_encoder *encoder; |
5121 | u32 val, final; |
5135 | u32 val, final; |
5122 | bool has_lvds = false; |
5136 | bool has_lvds = false; |
5123 | bool has_cpu_edp = false; |
5137 | bool has_cpu_edp = false; |
5124 | bool has_panel = false; |
5138 | bool has_panel = false; |
5125 | bool has_ck505 = false; |
5139 | bool has_ck505 = false; |
5126 | bool can_ssc = false; |
5140 | bool can_ssc = false; |
5127 | 5141 | ||
5128 | /* We need to take the global config into account */ |
5142 | /* We need to take the global config into account */ |
5129 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5143 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5130 | base.head) { |
5144 | base.head) { |
5131 | switch (encoder->type) { |
5145 | switch (encoder->type) { |
5132 | case INTEL_OUTPUT_LVDS: |
5146 | case INTEL_OUTPUT_LVDS: |
5133 | has_panel = true; |
5147 | has_panel = true; |
5134 | has_lvds = true; |
5148 | has_lvds = true; |
5135 | break; |
5149 | break; |
5136 | case INTEL_OUTPUT_EDP: |
5150 | case INTEL_OUTPUT_EDP: |
5137 | has_panel = true; |
5151 | has_panel = true; |
5138 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5152 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5139 | has_cpu_edp = true; |
5153 | has_cpu_edp = true; |
5140 | break; |
5154 | break; |
5141 | } |
5155 | } |
5142 | } |
5156 | } |
5143 | 5157 | ||
5144 | if (HAS_PCH_IBX(dev)) { |
5158 | if (HAS_PCH_IBX(dev)) { |
5145 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5159 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5146 | can_ssc = has_ck505; |
5160 | can_ssc = has_ck505; |
5147 | } else { |
5161 | } else { |
5148 | has_ck505 = false; |
5162 | has_ck505 = false; |
5149 | can_ssc = true; |
5163 | can_ssc = true; |
5150 | } |
5164 | } |
5151 | 5165 | ||
5152 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5166 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5153 | has_panel, has_lvds, has_ck505); |
5167 | has_panel, has_lvds, has_ck505); |
5154 | 5168 | ||
5155 | /* Ironlake: try to setup display ref clock before DPLL |
5169 | /* Ironlake: try to setup display ref clock before DPLL |
5156 | * enabling. This is only under driver's control after |
5170 | * enabling. This is only under driver's control after |
5157 | * PCH B stepping, previous chipset stepping should be |
5171 | * PCH B stepping, previous chipset stepping should be |
5158 | * ignoring this setting. |
5172 | * ignoring this setting. |
5159 | */ |
5173 | */ |
5160 | val = I915_READ(PCH_DREF_CONTROL); |
5174 | val = I915_READ(PCH_DREF_CONTROL); |
5161 | 5175 | ||
5162 | /* As we must carefully and slowly disable/enable each source in turn, |
5176 | /* As we must carefully and slowly disable/enable each source in turn, |
5163 | * compute the final state we want first and check if we need to |
5177 | * compute the final state we want first and check if we need to |
5164 | * make any changes at all. |
5178 | * make any changes at all. |
5165 | */ |
5179 | */ |
5166 | final = val; |
5180 | final = val; |
5167 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5181 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5168 | if (has_ck505) |
5182 | if (has_ck505) |
5169 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5183 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5170 | else |
5184 | else |
5171 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5185 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5172 | 5186 | ||
5173 | final &= ~DREF_SSC_SOURCE_MASK; |
5187 | final &= ~DREF_SSC_SOURCE_MASK; |
5174 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5188 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5175 | final &= ~DREF_SSC1_ENABLE; |
5189 | final &= ~DREF_SSC1_ENABLE; |
5176 | 5190 | ||
5177 | if (has_panel) { |
5191 | if (has_panel) { |
5178 | final |= DREF_SSC_SOURCE_ENABLE; |
5192 | final |= DREF_SSC_SOURCE_ENABLE; |
5179 | 5193 | ||
5180 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5194 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5181 | final |= DREF_SSC1_ENABLE; |
5195 | final |= DREF_SSC1_ENABLE; |
5182 | 5196 | ||
5183 | if (has_cpu_edp) { |
5197 | if (has_cpu_edp) { |
5184 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5198 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5185 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5199 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5186 | else |
5200 | else |
5187 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5201 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5188 | } else |
5202 | } else |
5189 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5203 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5190 | } else { |
5204 | } else { |
5191 | final |= DREF_SSC_SOURCE_DISABLE; |
5205 | final |= DREF_SSC_SOURCE_DISABLE; |
5192 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5206 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5193 | } |
5207 | } |
5194 | 5208 | ||
5195 | if (final == val) |
5209 | if (final == val) |
5196 | return; |
5210 | return; |
5197 | 5211 | ||
5198 | /* Always enable nonspread source */ |
5212 | /* Always enable nonspread source */ |
5199 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5213 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5200 | 5214 | ||
5201 | if (has_ck505) |
5215 | if (has_ck505) |
5202 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5216 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5203 | else |
5217 | else |
5204 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5218 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5205 | 5219 | ||
5206 | if (has_panel) { |
5220 | if (has_panel) { |
5207 | val &= ~DREF_SSC_SOURCE_MASK; |
5221 | val &= ~DREF_SSC_SOURCE_MASK; |
5208 | val |= DREF_SSC_SOURCE_ENABLE; |
5222 | val |= DREF_SSC_SOURCE_ENABLE; |
5209 | 5223 | ||
5210 | /* SSC must be turned on before enabling the CPU output */ |
5224 | /* SSC must be turned on before enabling the CPU output */ |
5211 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5225 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5212 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5226 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5213 | val |= DREF_SSC1_ENABLE; |
5227 | val |= DREF_SSC1_ENABLE; |
5214 | } else |
5228 | } else |
5215 | val &= ~DREF_SSC1_ENABLE; |
5229 | val &= ~DREF_SSC1_ENABLE; |
5216 | 5230 | ||
5217 | /* Get SSC going before enabling the outputs */ |
5231 | /* Get SSC going before enabling the outputs */ |
5218 | I915_WRITE(PCH_DREF_CONTROL, val); |
5232 | I915_WRITE(PCH_DREF_CONTROL, val); |
5219 | POSTING_READ(PCH_DREF_CONTROL); |
5233 | POSTING_READ(PCH_DREF_CONTROL); |
5220 | udelay(200); |
5234 | udelay(200); |
5221 | 5235 | ||
5222 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5236 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5223 | 5237 | ||
5224 | /* Enable CPU source on CPU attached eDP */ |
5238 | /* Enable CPU source on CPU attached eDP */ |
5225 | if (has_cpu_edp) { |
5239 | if (has_cpu_edp) { |
5226 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5240 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5227 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5241 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5228 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5242 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5229 | } |
5243 | } |
5230 | else |
5244 | else |
5231 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5245 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5232 | } else |
5246 | } else |
5233 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5247 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5234 | 5248 | ||
5235 | I915_WRITE(PCH_DREF_CONTROL, val); |
5249 | I915_WRITE(PCH_DREF_CONTROL, val); |
5236 | POSTING_READ(PCH_DREF_CONTROL); |
5250 | POSTING_READ(PCH_DREF_CONTROL); |
5237 | udelay(200); |
5251 | udelay(200); |
5238 | } else { |
5252 | } else { |
5239 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5253 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5240 | 5254 | ||
5241 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5255 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5242 | 5256 | ||
5243 | /* Turn off CPU output */ |
5257 | /* Turn off CPU output */ |
5244 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5258 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5245 | 5259 | ||
5246 | I915_WRITE(PCH_DREF_CONTROL, val); |
5260 | I915_WRITE(PCH_DREF_CONTROL, val); |
5247 | POSTING_READ(PCH_DREF_CONTROL); |
5261 | POSTING_READ(PCH_DREF_CONTROL); |
5248 | udelay(200); |
5262 | udelay(200); |
5249 | 5263 | ||
5250 | /* Turn off the SSC source */ |
5264 | /* Turn off the SSC source */ |
5251 | val &= ~DREF_SSC_SOURCE_MASK; |
5265 | val &= ~DREF_SSC_SOURCE_MASK; |
5252 | val |= DREF_SSC_SOURCE_DISABLE; |
5266 | val |= DREF_SSC_SOURCE_DISABLE; |
5253 | 5267 | ||
5254 | /* Turn off SSC1 */ |
5268 | /* Turn off SSC1 */ |
5255 | val &= ~DREF_SSC1_ENABLE; |
5269 | val &= ~DREF_SSC1_ENABLE; |
5256 | 5270 | ||
5257 | I915_WRITE(PCH_DREF_CONTROL, val); |
5271 | I915_WRITE(PCH_DREF_CONTROL, val); |
5258 | POSTING_READ(PCH_DREF_CONTROL); |
5272 | POSTING_READ(PCH_DREF_CONTROL); |
5259 | udelay(200); |
5273 | udelay(200); |
5260 | } |
5274 | } |
5261 | 5275 | ||
5262 | BUG_ON(val != final); |
5276 | BUG_ON(val != final); |
5263 | } |
5277 | } |
5264 | 5278 | ||
5265 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
5279 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
5266 | { |
5280 | { |
5267 | uint32_t tmp; |
5281 | uint32_t tmp; |
5268 | 5282 | ||
5269 | tmp = I915_READ(SOUTH_CHICKEN2); |
5283 | tmp = I915_READ(SOUTH_CHICKEN2); |
5270 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
5284 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
5271 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5285 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5272 | 5286 | ||
5273 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5287 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5274 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
5288 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
5275 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
5289 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
5276 | 5290 | ||
5277 | tmp = I915_READ(SOUTH_CHICKEN2); |
5291 | tmp = I915_READ(SOUTH_CHICKEN2); |
5278 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
5292 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
5279 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5293 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5280 | 5294 | ||
5281 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5295 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5282 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
5296 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
5283 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5297 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5284 | } |
5298 | } |
5285 | 5299 | ||
5286 | /* WaMPhyProgramming:hsw */ |
5300 | /* WaMPhyProgramming:hsw */ |
5287 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
5301 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
5288 | { |
5302 | { |
5289 | uint32_t tmp; |
5303 | uint32_t tmp; |
5290 | 5304 | ||
5291 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5305 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5292 | tmp &= ~(0xFF << 24); |
5306 | tmp &= ~(0xFF << 24); |
5293 | tmp |= (0x12 << 24); |
5307 | tmp |= (0x12 << 24); |
5294 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
5308 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
5295 | 5309 | ||
5296 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5310 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5297 | tmp |= (1 << 11); |
5311 | tmp |= (1 << 11); |
5298 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
5312 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
5299 | 5313 | ||
5300 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
5314 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
5301 | tmp |= (1 << 11); |
5315 | tmp |= (1 << 11); |
5302 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
5316 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
5303 | 5317 | ||
5304 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5318 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5305 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5319 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5306 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
5320 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
5307 | 5321 | ||
5308 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
5322 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
5309 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5323 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5310 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
5324 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
5311 | 5325 | ||
5312 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5326 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5313 | tmp &= ~(7 << 13); |
5327 | tmp &= ~(7 << 13); |
5314 | tmp |= (5 << 13); |
5328 | tmp |= (5 << 13); |
5315 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
5329 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
5316 | 5330 | ||
5317 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5331 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5318 | tmp &= ~(7 << 13); |
5332 | tmp &= ~(7 << 13); |
5319 | tmp |= (5 << 13); |
5333 | tmp |= (5 << 13); |
5320 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
5334 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
5321 | 5335 | ||
5322 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
5336 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
5323 | tmp &= ~0xFF; |
5337 | tmp &= ~0xFF; |
5324 | tmp |= 0x1C; |
5338 | tmp |= 0x1C; |
5325 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
5339 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
5326 | 5340 | ||
5327 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
5341 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
5328 | tmp &= ~0xFF; |
5342 | tmp &= ~0xFF; |
5329 | tmp |= 0x1C; |
5343 | tmp |= 0x1C; |
5330 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
5344 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
5331 | 5345 | ||
5332 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
5346 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
5333 | tmp &= ~(0xFF << 16); |
5347 | tmp &= ~(0xFF << 16); |
5334 | tmp |= (0x1C << 16); |
5348 | tmp |= (0x1C << 16); |
5335 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
5349 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
5336 | 5350 | ||
5337 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
5351 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
5338 | tmp &= ~(0xFF << 16); |
5352 | tmp &= ~(0xFF << 16); |
5339 | tmp |= (0x1C << 16); |
5353 | tmp |= (0x1C << 16); |
5340 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
5354 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
5341 | 5355 | ||
5342 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5356 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5343 | tmp |= (1 << 27); |
5357 | tmp |= (1 << 27); |
5344 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
5358 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
5345 | 5359 | ||
5346 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5360 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5347 | tmp |= (1 << 27); |
5361 | tmp |= (1 << 27); |
5348 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
5362 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
5349 | 5363 | ||
5350 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5364 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5351 | tmp &= ~(0xF << 28); |
5365 | tmp &= ~(0xF << 28); |
5352 | tmp |= (4 << 28); |
5366 | tmp |= (4 << 28); |
5353 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
5367 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
5354 | 5368 | ||
5355 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5369 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5356 | tmp &= ~(0xF << 28); |
5370 | tmp &= ~(0xF << 28); |
5357 | tmp |= (4 << 28); |
5371 | tmp |= (4 << 28); |
5358 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
5372 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
5359 | } |
5373 | } |
5360 | 5374 | ||
5361 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5375 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5362 | * Programming" based on the parameters passed: |
5376 | * Programming" based on the parameters passed: |
5363 | * - Sequence to enable CLKOUT_DP |
5377 | * - Sequence to enable CLKOUT_DP |
5364 | * - Sequence to enable CLKOUT_DP without spread |
5378 | * - Sequence to enable CLKOUT_DP without spread |
5365 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
5379 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
5366 | */ |
5380 | */ |
5367 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
5381 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
5368 | bool with_fdi) |
5382 | bool with_fdi) |
5369 | { |
5383 | { |
5370 | struct drm_i915_private *dev_priv = dev->dev_private; |
5384 | struct drm_i915_private *dev_priv = dev->dev_private; |
5371 | uint32_t reg, tmp; |
5385 | uint32_t reg, tmp; |
5372 | 5386 | ||
5373 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5387 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5374 | with_spread = true; |
5388 | with_spread = true; |
5375 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
5389 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
5376 | with_fdi, "LP PCH doesn't have FDI\n")) |
5390 | with_fdi, "LP PCH doesn't have FDI\n")) |
5377 | with_fdi = false; |
5391 | with_fdi = false; |
5378 | 5392 | ||
5379 | mutex_lock(&dev_priv->dpio_lock); |
5393 | mutex_lock(&dev_priv->dpio_lock); |
5380 | 5394 | ||
5381 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5395 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5382 | tmp &= ~SBI_SSCCTL_DISABLE; |
5396 | tmp &= ~SBI_SSCCTL_DISABLE; |
5383 | tmp |= SBI_SSCCTL_PATHALT; |
5397 | tmp |= SBI_SSCCTL_PATHALT; |
5384 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5398 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5385 | 5399 | ||
5386 | udelay(24); |
5400 | udelay(24); |
5387 | 5401 | ||
5388 | if (with_spread) { |
5402 | if (with_spread) { |
5389 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5403 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5390 | tmp &= ~SBI_SSCCTL_PATHALT; |
5404 | tmp &= ~SBI_SSCCTL_PATHALT; |
5391 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5405 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5392 | 5406 | ||
5393 | if (with_fdi) { |
5407 | if (with_fdi) { |
5394 | lpt_reset_fdi_mphy(dev_priv); |
5408 | lpt_reset_fdi_mphy(dev_priv); |
5395 | lpt_program_fdi_mphy(dev_priv); |
5409 | lpt_program_fdi_mphy(dev_priv); |
5396 | } |
5410 | } |
5397 | } |
5411 | } |
5398 | 5412 | ||
5399 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5413 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5400 | SBI_GEN0 : SBI_DBUFF0; |
5414 | SBI_GEN0 : SBI_DBUFF0; |
5401 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5415 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5402 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5416 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5403 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5417 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5404 | 5418 | ||
5405 | mutex_unlock(&dev_priv->dpio_lock); |
5419 | mutex_unlock(&dev_priv->dpio_lock); |
5406 | } |
5420 | } |
5407 | 5421 | ||
5408 | /* Sequence to disable CLKOUT_DP */ |
5422 | /* Sequence to disable CLKOUT_DP */ |
5409 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
5423 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
5410 | { |
5424 | { |
5411 | struct drm_i915_private *dev_priv = dev->dev_private; |
5425 | struct drm_i915_private *dev_priv = dev->dev_private; |
5412 | uint32_t reg, tmp; |
5426 | uint32_t reg, tmp; |
5413 | 5427 | ||
5414 | mutex_lock(&dev_priv->dpio_lock); |
5428 | mutex_lock(&dev_priv->dpio_lock); |
5415 | 5429 | ||
5416 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5430 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5417 | SBI_GEN0 : SBI_DBUFF0; |
5431 | SBI_GEN0 : SBI_DBUFF0; |
5418 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5432 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5419 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5433 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5420 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5434 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5421 | 5435 | ||
5422 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5436 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5423 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
5437 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
5424 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
5438 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
5425 | tmp |= SBI_SSCCTL_PATHALT; |
5439 | tmp |= SBI_SSCCTL_PATHALT; |
5426 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5440 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5427 | udelay(32); |
5441 | udelay(32); |
5428 | } |
5442 | } |
5429 | tmp |= SBI_SSCCTL_DISABLE; |
5443 | tmp |= SBI_SSCCTL_DISABLE; |
5430 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5444 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5431 | } |
5445 | } |
5432 | 5446 | ||
5433 | mutex_unlock(&dev_priv->dpio_lock); |
5447 | mutex_unlock(&dev_priv->dpio_lock); |
5434 | } |
5448 | } |
5435 | 5449 | ||
5436 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5450 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5437 | { |
5451 | { |
5438 | struct drm_mode_config *mode_config = &dev->mode_config; |
5452 | struct drm_mode_config *mode_config = &dev->mode_config; |
5439 | struct intel_encoder *encoder; |
5453 | struct intel_encoder *encoder; |
5440 | bool has_vga = false; |
5454 | bool has_vga = false; |
5441 | 5455 | ||
5442 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5456 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5443 | switch (encoder->type) { |
5457 | switch (encoder->type) { |
5444 | case INTEL_OUTPUT_ANALOG: |
5458 | case INTEL_OUTPUT_ANALOG: |
5445 | has_vga = true; |
5459 | has_vga = true; |
5446 | break; |
5460 | break; |
5447 | } |
5461 | } |
5448 | } |
5462 | } |
5449 | 5463 | ||
5450 | if (has_vga) |
5464 | if (has_vga) |
5451 | lpt_enable_clkout_dp(dev, true, true); |
5465 | lpt_enable_clkout_dp(dev, true, true); |
5452 | else |
5466 | else |
5453 | lpt_disable_clkout_dp(dev); |
5467 | lpt_disable_clkout_dp(dev); |
5454 | } |
5468 | } |
5455 | 5469 | ||
5456 | /* |
5470 | /* |
5457 | * Initialize reference clocks when the driver loads |
5471 | * Initialize reference clocks when the driver loads |
5458 | */ |
5472 | */ |
5459 | void intel_init_pch_refclk(struct drm_device *dev) |
5473 | void intel_init_pch_refclk(struct drm_device *dev) |
5460 | { |
5474 | { |
5461 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5475 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5462 | ironlake_init_pch_refclk(dev); |
5476 | ironlake_init_pch_refclk(dev); |
5463 | else if (HAS_PCH_LPT(dev)) |
5477 | else if (HAS_PCH_LPT(dev)) |
5464 | lpt_init_pch_refclk(dev); |
5478 | lpt_init_pch_refclk(dev); |
5465 | } |
5479 | } |
5466 | 5480 | ||
5467 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5481 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5468 | { |
5482 | { |
5469 | struct drm_device *dev = crtc->dev; |
5483 | struct drm_device *dev = crtc->dev; |
5470 | struct drm_i915_private *dev_priv = dev->dev_private; |
5484 | struct drm_i915_private *dev_priv = dev->dev_private; |
5471 | struct intel_encoder *encoder; |
5485 | struct intel_encoder *encoder; |
5472 | int num_connectors = 0; |
5486 | int num_connectors = 0; |
5473 | bool is_lvds = false; |
5487 | bool is_lvds = false; |
5474 | 5488 | ||
5475 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5489 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5476 | switch (encoder->type) { |
5490 | switch (encoder->type) { |
5477 | case INTEL_OUTPUT_LVDS: |
5491 | case INTEL_OUTPUT_LVDS: |
5478 | is_lvds = true; |
5492 | is_lvds = true; |
5479 | break; |
5493 | break; |
5480 | } |
5494 | } |
5481 | num_connectors++; |
5495 | num_connectors++; |
5482 | } |
5496 | } |
5483 | 5497 | ||
5484 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5498 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5485 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5499 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5486 | dev_priv->vbt.lvds_ssc_freq); |
5500 | dev_priv->vbt.lvds_ssc_freq); |
5487 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
5501 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
5488 | } |
5502 | } |
5489 | 5503 | ||
5490 | return 120000; |
5504 | return 120000; |
5491 | } |
5505 | } |
5492 | 5506 | ||
5493 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
5507 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
5494 | { |
5508 | { |
5495 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5509 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5497 | int pipe = intel_crtc->pipe; |
5511 | int pipe = intel_crtc->pipe; |
5498 | uint32_t val; |
5512 | uint32_t val; |
5499 | 5513 | ||
5500 | val = 0; |
5514 | val = 0; |
5501 | 5515 | ||
5502 | switch (intel_crtc->config.pipe_bpp) { |
5516 | switch (intel_crtc->config.pipe_bpp) { |
5503 | case 18: |
5517 | case 18: |
5504 | val |= PIPECONF_6BPC; |
5518 | val |= PIPECONF_6BPC; |
5505 | break; |
5519 | break; |
5506 | case 24: |
5520 | case 24: |
5507 | val |= PIPECONF_8BPC; |
5521 | val |= PIPECONF_8BPC; |
5508 | break; |
5522 | break; |
5509 | case 30: |
5523 | case 30: |
5510 | val |= PIPECONF_10BPC; |
5524 | val |= PIPECONF_10BPC; |
5511 | break; |
5525 | break; |
5512 | case 36: |
5526 | case 36: |
5513 | val |= PIPECONF_12BPC; |
5527 | val |= PIPECONF_12BPC; |
5514 | break; |
5528 | break; |
5515 | default: |
5529 | default: |
5516 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5530 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5517 | BUG(); |
5531 | BUG(); |
5518 | } |
5532 | } |
5519 | 5533 | ||
5520 | if (intel_crtc->config.dither) |
5534 | if (intel_crtc->config.dither) |
5521 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5535 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5522 | 5536 | ||
5523 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5537 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5524 | val |= PIPECONF_INTERLACED_ILK; |
5538 | val |= PIPECONF_INTERLACED_ILK; |
5525 | else |
5539 | else |
5526 | val |= PIPECONF_PROGRESSIVE; |
5540 | val |= PIPECONF_PROGRESSIVE; |
5527 | 5541 | ||
5528 | if (intel_crtc->config.limited_color_range) |
5542 | if (intel_crtc->config.limited_color_range) |
5529 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5543 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5530 | 5544 | ||
5531 | I915_WRITE(PIPECONF(pipe), val); |
5545 | I915_WRITE(PIPECONF(pipe), val); |
5532 | POSTING_READ(PIPECONF(pipe)); |
5546 | POSTING_READ(PIPECONF(pipe)); |
5533 | } |
5547 | } |
5534 | 5548 | ||
5535 | /* |
5549 | /* |
5536 | * Set up the pipe CSC unit. |
5550 | * Set up the pipe CSC unit. |
5537 | * |
5551 | * |
5538 | * Currently only full range RGB to limited range RGB conversion |
5552 | * Currently only full range RGB to limited range RGB conversion |
5539 | * is supported, but eventually this should handle various |
5553 | * is supported, but eventually this should handle various |
5540 | * RGB<->YCbCr scenarios as well. |
5554 | * RGB<->YCbCr scenarios as well. |
5541 | */ |
5555 | */ |
5542 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
5556 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
5543 | { |
5557 | { |
5544 | struct drm_device *dev = crtc->dev; |
5558 | struct drm_device *dev = crtc->dev; |
5545 | struct drm_i915_private *dev_priv = dev->dev_private; |
5559 | struct drm_i915_private *dev_priv = dev->dev_private; |
5546 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5547 | int pipe = intel_crtc->pipe; |
5561 | int pipe = intel_crtc->pipe; |
5548 | uint16_t coeff = 0x7800; /* 1.0 */ |
5562 | uint16_t coeff = 0x7800; /* 1.0 */ |
5549 | 5563 | ||
5550 | /* |
5564 | /* |
5551 | * TODO: Check what kind of values actually come out of the pipe |
5565 | * TODO: Check what kind of values actually come out of the pipe |
5552 | * with these coeff/postoff values and adjust to get the best |
5566 | * with these coeff/postoff values and adjust to get the best |
5553 | * accuracy. Perhaps we even need to take the bpc value into |
5567 | * accuracy. Perhaps we even need to take the bpc value into |
5554 | * consideration. |
5568 | * consideration. |
5555 | */ |
5569 | */ |
5556 | 5570 | ||
5557 | if (intel_crtc->config.limited_color_range) |
5571 | if (intel_crtc->config.limited_color_range) |
5558 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5572 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5559 | 5573 | ||
5560 | /* |
5574 | /* |
5561 | * GY/GU and RY/RU should be the other way around according |
5575 | * GY/GU and RY/RU should be the other way around according |
5562 | * to BSpec, but reality doesn't agree. Just set them up in |
5576 | * to BSpec, but reality doesn't agree. Just set them up in |
5563 | * a way that results in the correct picture. |
5577 | * a way that results in the correct picture. |
5564 | */ |
5578 | */ |
5565 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
5579 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
5566 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
5580 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
5567 | 5581 | ||
5568 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
5582 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
5569 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
5583 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
5570 | 5584 | ||
5571 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
5585 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
5572 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
5586 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
5573 | 5587 | ||
5574 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
5588 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
5575 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
5589 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
5576 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
5590 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
5577 | 5591 | ||
5578 | if (INTEL_INFO(dev)->gen > 6) { |
5592 | if (INTEL_INFO(dev)->gen > 6) { |
5579 | uint16_t postoff = 0; |
5593 | uint16_t postoff = 0; |
5580 | 5594 | ||
5581 | if (intel_crtc->config.limited_color_range) |
5595 | if (intel_crtc->config.limited_color_range) |
5582 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
5596 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
5583 | 5597 | ||
5584 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5598 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5585 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
5599 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
5586 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
5600 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
5587 | 5601 | ||
5588 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
5602 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
5589 | } else { |
5603 | } else { |
5590 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
5604 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
5591 | 5605 | ||
5592 | if (intel_crtc->config.limited_color_range) |
5606 | if (intel_crtc->config.limited_color_range) |
5593 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5607 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5594 | 5608 | ||
5595 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
5609 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
5596 | } |
5610 | } |
5597 | } |
5611 | } |
5598 | 5612 | ||
5599 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
5613 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
5600 | { |
5614 | { |
5601 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5615 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5603 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5617 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5604 | uint32_t val; |
5618 | uint32_t val; |
5605 | 5619 | ||
5606 | val = 0; |
5620 | val = 0; |
5607 | 5621 | ||
5608 | if (intel_crtc->config.dither) |
5622 | if (intel_crtc->config.dither) |
5609 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5623 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5610 | 5624 | ||
5611 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5625 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5612 | val |= PIPECONF_INTERLACED_ILK; |
5626 | val |= PIPECONF_INTERLACED_ILK; |
5613 | else |
5627 | else |
5614 | val |= PIPECONF_PROGRESSIVE; |
5628 | val |= PIPECONF_PROGRESSIVE; |
5615 | 5629 | ||
5616 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5630 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5617 | POSTING_READ(PIPECONF(cpu_transcoder)); |
5631 | POSTING_READ(PIPECONF(cpu_transcoder)); |
5618 | 5632 | ||
5619 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
5633 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
5620 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
5634 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
5621 | } |
5635 | } |
5622 | 5636 | ||
5623 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5637 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5624 | intel_clock_t *clock, |
5638 | intel_clock_t *clock, |
5625 | bool *has_reduced_clock, |
5639 | bool *has_reduced_clock, |
5626 | intel_clock_t *reduced_clock) |
5640 | intel_clock_t *reduced_clock) |
5627 | { |
5641 | { |
5628 | struct drm_device *dev = crtc->dev; |
5642 | struct drm_device *dev = crtc->dev; |
5629 | struct drm_i915_private *dev_priv = dev->dev_private; |
5643 | struct drm_i915_private *dev_priv = dev->dev_private; |
5630 | struct intel_encoder *intel_encoder; |
5644 | struct intel_encoder *intel_encoder; |
5631 | int refclk; |
5645 | int refclk; |
5632 | const intel_limit_t *limit; |
5646 | const intel_limit_t *limit; |
5633 | bool ret, is_lvds = false; |
5647 | bool ret, is_lvds = false; |
5634 | 5648 | ||
5635 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5649 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5636 | switch (intel_encoder->type) { |
5650 | switch (intel_encoder->type) { |
5637 | case INTEL_OUTPUT_LVDS: |
5651 | case INTEL_OUTPUT_LVDS: |
5638 | is_lvds = true; |
5652 | is_lvds = true; |
5639 | break; |
5653 | break; |
5640 | } |
5654 | } |
5641 | } |
5655 | } |
5642 | 5656 | ||
5643 | refclk = ironlake_get_refclk(crtc); |
5657 | refclk = ironlake_get_refclk(crtc); |
5644 | 5658 | ||
5645 | /* |
5659 | /* |
5646 | * Returns a set of divisors for the desired target clock with the given |
5660 | * Returns a set of divisors for the desired target clock with the given |
5647 | * refclk, or FALSE. The returned values represent the clock equation: |
5661 | * refclk, or FALSE. The returned values represent the clock equation: |
5648 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
5662 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
5649 | */ |
5663 | */ |
5650 | limit = intel_limit(crtc, refclk); |
5664 | limit = intel_limit(crtc, refclk); |
5651 | ret = dev_priv->display.find_dpll(limit, crtc, |
5665 | ret = dev_priv->display.find_dpll(limit, crtc, |
5652 | to_intel_crtc(crtc)->config.port_clock, |
5666 | to_intel_crtc(crtc)->config.port_clock, |
5653 | refclk, NULL, clock); |
5667 | refclk, NULL, clock); |
5654 | if (!ret) |
5668 | if (!ret) |
5655 | return false; |
5669 | return false; |
5656 | 5670 | ||
5657 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5671 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5658 | /* |
5672 | /* |
5659 | * Ensure we match the reduced clock's P to the target clock. |
5673 | * Ensure we match the reduced clock's P to the target clock. |
5660 | * If the clocks don't match, we can't switch the display clock |
5674 | * If the clocks don't match, we can't switch the display clock |
5661 | * by using the FP0/FP1. In such case we will disable the LVDS |
5675 | * by using the FP0/FP1. In such case we will disable the LVDS |
5662 | * downclock feature. |
5676 | * downclock feature. |
5663 | */ |
5677 | */ |
5664 | *has_reduced_clock = |
5678 | *has_reduced_clock = |
5665 | dev_priv->display.find_dpll(limit, crtc, |
5679 | dev_priv->display.find_dpll(limit, crtc, |
5666 | dev_priv->lvds_downclock, |
5680 | dev_priv->lvds_downclock, |
5667 | refclk, clock, |
5681 | refclk, clock, |
5668 | reduced_clock); |
5682 | reduced_clock); |
5669 | } |
5683 | } |
5670 | 5684 | ||
5671 | return true; |
5685 | return true; |
5672 | } |
5686 | } |
5673 | 5687 | ||
5674 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5688 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5675 | { |
5689 | { |
5676 | /* |
5690 | /* |
5677 | * Account for spread spectrum to avoid |
5691 | * Account for spread spectrum to avoid |
5678 | * oversubscribing the link. Max center spread |
5692 | * oversubscribing the link. Max center spread |
5679 | * is 2.5%; use 5% for safety's sake. |
5693 | * is 2.5%; use 5% for safety's sake. |
5680 | */ |
5694 | */ |
5681 | u32 bps = target_clock * bpp * 21 / 20; |
5695 | u32 bps = target_clock * bpp * 21 / 20; |
5682 | return bps / (link_bw * 8) + 1; |
5696 | return bps / (link_bw * 8) + 1; |
5683 | } |
5697 | } |
5684 | 5698 | ||
5685 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
5699 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
5686 | { |
5700 | { |
5687 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
5701 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
5688 | } |
5702 | } |
5689 | 5703 | ||
5690 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5704 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5691 | u32 *fp, |
5705 | u32 *fp, |
5692 | intel_clock_t *reduced_clock, u32 *fp2) |
5706 | intel_clock_t *reduced_clock, u32 *fp2) |
5693 | { |
5707 | { |
5694 | struct drm_crtc *crtc = &intel_crtc->base; |
5708 | struct drm_crtc *crtc = &intel_crtc->base; |
5695 | struct drm_device *dev = crtc->dev; |
5709 | struct drm_device *dev = crtc->dev; |
5696 | struct drm_i915_private *dev_priv = dev->dev_private; |
5710 | struct drm_i915_private *dev_priv = dev->dev_private; |
5697 | struct intel_encoder *intel_encoder; |
5711 | struct intel_encoder *intel_encoder; |
5698 | uint32_t dpll; |
5712 | uint32_t dpll; |
5699 | int factor, num_connectors = 0; |
5713 | int factor, num_connectors = 0; |
5700 | bool is_lvds = false, is_sdvo = false; |
5714 | bool is_lvds = false, is_sdvo = false; |
5701 | 5715 | ||
5702 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5716 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5703 | switch (intel_encoder->type) { |
5717 | switch (intel_encoder->type) { |
5704 | case INTEL_OUTPUT_LVDS: |
5718 | case INTEL_OUTPUT_LVDS: |
5705 | is_lvds = true; |
5719 | is_lvds = true; |
5706 | break; |
5720 | break; |
5707 | case INTEL_OUTPUT_SDVO: |
5721 | case INTEL_OUTPUT_SDVO: |
5708 | case INTEL_OUTPUT_HDMI: |
5722 | case INTEL_OUTPUT_HDMI: |
5709 | is_sdvo = true; |
5723 | is_sdvo = true; |
5710 | break; |
5724 | break; |
5711 | } |
5725 | } |
5712 | 5726 | ||
5713 | num_connectors++; |
5727 | num_connectors++; |
5714 | } |
5728 | } |
5715 | 5729 | ||
5716 | /* Enable autotuning of the PLL clock (if permissible) */ |
5730 | /* Enable autotuning of the PLL clock (if permissible) */ |
5717 | factor = 21; |
5731 | factor = 21; |
5718 | if (is_lvds) { |
5732 | if (is_lvds) { |
5719 | if ((intel_panel_use_ssc(dev_priv) && |
5733 | if ((intel_panel_use_ssc(dev_priv) && |
5720 | dev_priv->vbt.lvds_ssc_freq == 100) || |
5734 | dev_priv->vbt.lvds_ssc_freq == 100) || |
5721 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
5735 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
5722 | factor = 25; |
5736 | factor = 25; |
5723 | } else if (intel_crtc->config.sdvo_tv_clock) |
5737 | } else if (intel_crtc->config.sdvo_tv_clock) |
5724 | factor = 20; |
5738 | factor = 20; |
5725 | 5739 | ||
5726 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
5740 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
5727 | *fp |= FP_CB_TUNE; |
5741 | *fp |= FP_CB_TUNE; |
5728 | 5742 | ||
5729 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5743 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5730 | *fp2 |= FP_CB_TUNE; |
5744 | *fp2 |= FP_CB_TUNE; |
5731 | 5745 | ||
5732 | dpll = 0; |
5746 | dpll = 0; |
5733 | 5747 | ||
5734 | if (is_lvds) |
5748 | if (is_lvds) |
5735 | dpll |= DPLLB_MODE_LVDS; |
5749 | dpll |= DPLLB_MODE_LVDS; |
5736 | else |
5750 | else |
5737 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5751 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5738 | 5752 | ||
5739 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5753 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5740 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
5754 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
5741 | 5755 | ||
5742 | if (is_sdvo) |
5756 | if (is_sdvo) |
5743 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5757 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5744 | if (intel_crtc->config.has_dp_encoder) |
5758 | if (intel_crtc->config.has_dp_encoder) |
5745 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5759 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5746 | 5760 | ||
5747 | /* compute bitmask from p1 value */ |
5761 | /* compute bitmask from p1 value */ |
5748 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5762 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5749 | /* also FPA1 */ |
5763 | /* also FPA1 */ |
5750 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5764 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5751 | 5765 | ||
5752 | switch (intel_crtc->config.dpll.p2) { |
5766 | switch (intel_crtc->config.dpll.p2) { |
5753 | case 5: |
5767 | case 5: |
5754 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5768 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5755 | break; |
5769 | break; |
5756 | case 7: |
5770 | case 7: |
5757 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5771 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5758 | break; |
5772 | break; |
5759 | case 10: |
5773 | case 10: |
5760 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5774 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5761 | break; |
5775 | break; |
5762 | case 14: |
5776 | case 14: |
5763 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5777 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5764 | break; |
5778 | break; |
5765 | } |
5779 | } |
5766 | 5780 | ||
5767 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5781 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5768 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5782 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5769 | else |
5783 | else |
5770 | dpll |= PLL_REF_INPUT_DREFCLK; |
5784 | dpll |= PLL_REF_INPUT_DREFCLK; |
5771 | 5785 | ||
5772 | return dpll | DPLL_VCO_ENABLE; |
5786 | return dpll | DPLL_VCO_ENABLE; |
5773 | } |
5787 | } |
5774 | 5788 | ||
5775 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5789 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5776 | int x, int y, |
5790 | int x, int y, |
5777 | struct drm_framebuffer *fb) |
5791 | struct drm_framebuffer *fb) |
5778 | { |
5792 | { |
5779 | struct drm_device *dev = crtc->dev; |
5793 | struct drm_device *dev = crtc->dev; |
5780 | struct drm_i915_private *dev_priv = dev->dev_private; |
5794 | struct drm_i915_private *dev_priv = dev->dev_private; |
5781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5782 | int pipe = intel_crtc->pipe; |
5796 | int pipe = intel_crtc->pipe; |
5783 | int plane = intel_crtc->plane; |
5797 | int plane = intel_crtc->plane; |
5784 | int num_connectors = 0; |
5798 | int num_connectors = 0; |
5785 | intel_clock_t clock, reduced_clock; |
5799 | intel_clock_t clock, reduced_clock; |
5786 | u32 dpll = 0, fp = 0, fp2 = 0; |
5800 | u32 dpll = 0, fp = 0, fp2 = 0; |
5787 | bool ok, has_reduced_clock = false; |
5801 | bool ok, has_reduced_clock = false; |
5788 | bool is_lvds = false; |
5802 | bool is_lvds = false; |
5789 | struct intel_encoder *encoder; |
5803 | struct intel_encoder *encoder; |
5790 | struct intel_shared_dpll *pll; |
5804 | struct intel_shared_dpll *pll; |
5791 | int ret; |
5805 | int ret; |
5792 | 5806 | ||
5793 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5807 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5794 | switch (encoder->type) { |
5808 | switch (encoder->type) { |
5795 | case INTEL_OUTPUT_LVDS: |
5809 | case INTEL_OUTPUT_LVDS: |
5796 | is_lvds = true; |
5810 | is_lvds = true; |
5797 | break; |
5811 | break; |
5798 | } |
5812 | } |
5799 | 5813 | ||
5800 | num_connectors++; |
5814 | num_connectors++; |
5801 | } |
5815 | } |
5802 | 5816 | ||
5803 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5817 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5804 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
5818 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
5805 | 5819 | ||
5806 | ok = ironlake_compute_clocks(crtc, &clock, |
5820 | ok = ironlake_compute_clocks(crtc, &clock, |
5807 | &has_reduced_clock, &reduced_clock); |
5821 | &has_reduced_clock, &reduced_clock); |
5808 | if (!ok && !intel_crtc->config.clock_set) { |
5822 | if (!ok && !intel_crtc->config.clock_set) { |
5809 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5823 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5810 | return -EINVAL; |
5824 | return -EINVAL; |
5811 | } |
5825 | } |
5812 | /* Compat-code for transition, will disappear. */ |
5826 | /* Compat-code for transition, will disappear. */ |
5813 | if (!intel_crtc->config.clock_set) { |
5827 | if (!intel_crtc->config.clock_set) { |
5814 | intel_crtc->config.dpll.n = clock.n; |
5828 | intel_crtc->config.dpll.n = clock.n; |
5815 | intel_crtc->config.dpll.m1 = clock.m1; |
5829 | intel_crtc->config.dpll.m1 = clock.m1; |
5816 | intel_crtc->config.dpll.m2 = clock.m2; |
5830 | intel_crtc->config.dpll.m2 = clock.m2; |
5817 | intel_crtc->config.dpll.p1 = clock.p1; |
5831 | intel_crtc->config.dpll.p1 = clock.p1; |
5818 | intel_crtc->config.dpll.p2 = clock.p2; |
5832 | intel_crtc->config.dpll.p2 = clock.p2; |
5819 | } |
5833 | } |
5820 | 5834 | ||
5821 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5835 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5822 | if (intel_crtc->config.has_pch_encoder) { |
5836 | if (intel_crtc->config.has_pch_encoder) { |
5823 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
5837 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
5824 | if (has_reduced_clock) |
5838 | if (has_reduced_clock) |
5825 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
5839 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
5826 | 5840 | ||
5827 | dpll = ironlake_compute_dpll(intel_crtc, |
5841 | dpll = ironlake_compute_dpll(intel_crtc, |
5828 | &fp, &reduced_clock, |
5842 | &fp, &reduced_clock, |
5829 | has_reduced_clock ? &fp2 : NULL); |
5843 | has_reduced_clock ? &fp2 : NULL); |
5830 | 5844 | ||
5831 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
5845 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
5832 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5846 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5833 | if (has_reduced_clock) |
5847 | if (has_reduced_clock) |
5834 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
5848 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
5835 | else |
5849 | else |
5836 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
5850 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
5837 | 5851 | ||
5838 | pll = intel_get_shared_dpll(intel_crtc); |
5852 | pll = intel_get_shared_dpll(intel_crtc); |
5839 | if (pll == NULL) { |
5853 | if (pll == NULL) { |
5840 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5854 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5841 | pipe_name(pipe)); |
5855 | pipe_name(pipe)); |
5842 | return -EINVAL; |
5856 | return -EINVAL; |
5843 | } |
5857 | } |
5844 | } else |
5858 | } else |
5845 | intel_put_shared_dpll(intel_crtc); |
5859 | intel_put_shared_dpll(intel_crtc); |
5846 | 5860 | ||
5847 | if (intel_crtc->config.has_dp_encoder) |
5861 | if (intel_crtc->config.has_dp_encoder) |
5848 | intel_dp_set_m_n(intel_crtc); |
5862 | intel_dp_set_m_n(intel_crtc); |
5849 | 5863 | ||
5850 | if (is_lvds && has_reduced_clock && i915_powersave) |
5864 | if (is_lvds && has_reduced_clock && i915_powersave) |
5851 | intel_crtc->lowfreq_avail = true; |
5865 | intel_crtc->lowfreq_avail = true; |
5852 | else |
5866 | else |
5853 | intel_crtc->lowfreq_avail = false; |
5867 | intel_crtc->lowfreq_avail = false; |
5854 | 5868 | ||
5855 | if (intel_crtc->config.has_pch_encoder) { |
5869 | if (intel_crtc->config.has_pch_encoder) { |
5856 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
5870 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
5857 | 5871 | ||
5858 | } |
5872 | } |
5859 | 5873 | ||
5860 | intel_set_pipe_timings(intel_crtc); |
5874 | intel_set_pipe_timings(intel_crtc); |
5861 | 5875 | ||
5862 | if (intel_crtc->config.has_pch_encoder) { |
5876 | if (intel_crtc->config.has_pch_encoder) { |
5863 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5877 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5864 | &intel_crtc->config.fdi_m_n); |
5878 | &intel_crtc->config.fdi_m_n); |
5865 | } |
5879 | } |
5866 | 5880 | ||
5867 | ironlake_set_pipeconf(crtc); |
5881 | ironlake_set_pipeconf(crtc); |
5868 | 5882 | ||
5869 | /* Set up the display plane register */ |
5883 | /* Set up the display plane register */ |
5870 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5884 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5871 | POSTING_READ(DSPCNTR(plane)); |
5885 | POSTING_READ(DSPCNTR(plane)); |
5872 | 5886 | ||
5873 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5887 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5874 | 5888 | ||
5875 | intel_update_watermarks(dev); |
5889 | intel_update_watermarks(dev); |
5876 | 5890 | ||
5877 | return ret; |
5891 | return ret; |
5878 | } |
5892 | } |
5879 | 5893 | ||
5880 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5894 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5881 | struct intel_crtc_config *pipe_config) |
5895 | struct intel_crtc_config *pipe_config) |
5882 | { |
5896 | { |
5883 | struct drm_device *dev = crtc->base.dev; |
5897 | struct drm_device *dev = crtc->base.dev; |
5884 | struct drm_i915_private *dev_priv = dev->dev_private; |
5898 | struct drm_i915_private *dev_priv = dev->dev_private; |
5885 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
5899 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
5886 | 5900 | ||
5887 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
5901 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
5888 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
5902 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
5889 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
5903 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
5890 | & ~TU_SIZE_MASK; |
5904 | & ~TU_SIZE_MASK; |
5891 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
5905 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
5892 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
5906 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
5893 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
5907 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
5894 | } |
5908 | } |
5895 | 5909 | ||
5896 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5910 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5897 | struct intel_crtc_config *pipe_config) |
5911 | struct intel_crtc_config *pipe_config) |
5898 | { |
5912 | { |
5899 | struct drm_device *dev = crtc->base.dev; |
5913 | struct drm_device *dev = crtc->base.dev; |
5900 | struct drm_i915_private *dev_priv = dev->dev_private; |
5914 | struct drm_i915_private *dev_priv = dev->dev_private; |
5901 | uint32_t tmp; |
5915 | uint32_t tmp; |
5902 | 5916 | ||
5903 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
5917 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
5904 | 5918 | ||
5905 | if (tmp & PF_ENABLE) { |
5919 | if (tmp & PF_ENABLE) { |
5906 | pipe_config->pch_pfit.enabled = true; |
5920 | pipe_config->pch_pfit.enabled = true; |
5907 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5921 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5908 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
5922 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
5909 | 5923 | ||
5910 | /* We currently do not free assignements of panel fitters on |
5924 | /* We currently do not free assignements of panel fitters on |
5911 | * ivb/hsw (since we don't use the higher upscaling modes which |
5925 | * ivb/hsw (since we don't use the higher upscaling modes which |
5912 | * differentiates them) so just WARN about this case for now. */ |
5926 | * differentiates them) so just WARN about this case for now. */ |
5913 | if (IS_GEN7(dev)) { |
5927 | if (IS_GEN7(dev)) { |
5914 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
5928 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
5915 | PF_PIPE_SEL_IVB(crtc->pipe)); |
5929 | PF_PIPE_SEL_IVB(crtc->pipe)); |
5916 | } |
5930 | } |
5917 | } |
5931 | } |
5918 | } |
5932 | } |
5919 | 5933 | ||
5920 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5934 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5921 | struct intel_crtc_config *pipe_config) |
5935 | struct intel_crtc_config *pipe_config) |
5922 | { |
5936 | { |
5923 | struct drm_device *dev = crtc->base.dev; |
5937 | struct drm_device *dev = crtc->base.dev; |
5924 | struct drm_i915_private *dev_priv = dev->dev_private; |
5938 | struct drm_i915_private *dev_priv = dev->dev_private; |
5925 | uint32_t tmp; |
5939 | uint32_t tmp; |
5926 | 5940 | ||
5927 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5941 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5928 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5942 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5929 | 5943 | ||
5930 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5944 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5931 | if (!(tmp & PIPECONF_ENABLE)) |
5945 | if (!(tmp & PIPECONF_ENABLE)) |
5932 | return false; |
5946 | return false; |
5933 | 5947 | ||
5934 | switch (tmp & PIPECONF_BPC_MASK) { |
5948 | switch (tmp & PIPECONF_BPC_MASK) { |
5935 | case PIPECONF_6BPC: |
5949 | case PIPECONF_6BPC: |
5936 | pipe_config->pipe_bpp = 18; |
5950 | pipe_config->pipe_bpp = 18; |
5937 | break; |
5951 | break; |
5938 | case PIPECONF_8BPC: |
5952 | case PIPECONF_8BPC: |
5939 | pipe_config->pipe_bpp = 24; |
5953 | pipe_config->pipe_bpp = 24; |
5940 | break; |
5954 | break; |
5941 | case PIPECONF_10BPC: |
5955 | case PIPECONF_10BPC: |
5942 | pipe_config->pipe_bpp = 30; |
5956 | pipe_config->pipe_bpp = 30; |
5943 | break; |
5957 | break; |
5944 | case PIPECONF_12BPC: |
5958 | case PIPECONF_12BPC: |
5945 | pipe_config->pipe_bpp = 36; |
5959 | pipe_config->pipe_bpp = 36; |
5946 | break; |
5960 | break; |
5947 | default: |
5961 | default: |
5948 | break; |
5962 | break; |
5949 | } |
5963 | } |
5950 | 5964 | ||
5951 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5965 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5952 | struct intel_shared_dpll *pll; |
5966 | struct intel_shared_dpll *pll; |
5953 | 5967 | ||
5954 | pipe_config->has_pch_encoder = true; |
5968 | pipe_config->has_pch_encoder = true; |
5955 | 5969 | ||
5956 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5970 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5957 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
5971 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
5958 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
5972 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
5959 | 5973 | ||
5960 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
5974 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
5961 | 5975 | ||
5962 | if (HAS_PCH_IBX(dev_priv->dev)) { |
5976 | if (HAS_PCH_IBX(dev_priv->dev)) { |
5963 | pipe_config->shared_dpll = |
5977 | pipe_config->shared_dpll = |
5964 | (enum intel_dpll_id) crtc->pipe; |
5978 | (enum intel_dpll_id) crtc->pipe; |
5965 | } else { |
5979 | } else { |
5966 | tmp = I915_READ(PCH_DPLL_SEL); |
5980 | tmp = I915_READ(PCH_DPLL_SEL); |
5967 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
5981 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
5968 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
5982 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
5969 | else |
5983 | else |
5970 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
5984 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
5971 | } |
5985 | } |
5972 | 5986 | ||
5973 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
5987 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
5974 | 5988 | ||
5975 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
5989 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
5976 | &pipe_config->dpll_hw_state)); |
5990 | &pipe_config->dpll_hw_state)); |
5977 | 5991 | ||
5978 | tmp = pipe_config->dpll_hw_state.dpll; |
5992 | tmp = pipe_config->dpll_hw_state.dpll; |
5979 | pipe_config->pixel_multiplier = |
5993 | pipe_config->pixel_multiplier = |
5980 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
5994 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
5981 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
5995 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
5982 | } else { |
5996 | } else { |
5983 | pipe_config->pixel_multiplier = 1; |
5997 | pipe_config->pixel_multiplier = 1; |
5984 | } |
5998 | } |
5985 | 5999 | ||
5986 | intel_get_pipe_timings(crtc, pipe_config); |
6000 | intel_get_pipe_timings(crtc, pipe_config); |
5987 | 6001 | ||
5988 | ironlake_get_pfit_config(crtc, pipe_config); |
6002 | ironlake_get_pfit_config(crtc, pipe_config); |
5989 | 6003 | ||
5990 | return true; |
6004 | return true; |
5991 | } |
6005 | } |
5992 | 6006 | ||
5993 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6007 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
5994 | { |
6008 | { |
5995 | struct drm_device *dev = dev_priv->dev; |
6009 | struct drm_device *dev = dev_priv->dev; |
5996 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
6010 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
5997 | struct intel_crtc *crtc; |
6011 | struct intel_crtc *crtc; |
5998 | unsigned long irqflags; |
6012 | unsigned long irqflags; |
5999 | uint32_t val; |
6013 | uint32_t val; |
6000 | 6014 | ||
6001 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6015 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6002 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", |
6016 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
6003 | pipe_name(crtc->pipe)); |
6017 | pipe_name(crtc->pipe)); |
6004 | 6018 | ||
6005 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
6019 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
6006 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
6020 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
6007 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
6021 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
6008 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
6022 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
6009 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
6023 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
6010 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
6024 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
6011 | "CPU PWM1 enabled\n"); |
6025 | "CPU PWM1 enabled\n"); |
6012 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
6026 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
6013 | "CPU PWM2 enabled\n"); |
6027 | "CPU PWM2 enabled\n"); |
6014 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
6028 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
6015 | "PCH PWM1 enabled\n"); |
6029 | "PCH PWM1 enabled\n"); |
6016 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
6030 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
6017 | "Utility pin enabled\n"); |
6031 | "Utility pin enabled\n"); |
6018 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
6032 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
6019 | 6033 | ||
6020 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
6034 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
6021 | val = I915_READ(DEIMR); |
6035 | val = I915_READ(DEIMR); |
6022 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
6036 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
6023 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6037 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6024 | val = I915_READ(SDEIMR); |
6038 | val = I915_READ(SDEIMR); |
6025 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6039 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6026 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6040 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6027 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
6041 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
6028 | } |
6042 | } |
6029 | 6043 | ||
6030 | /* |
6044 | /* |
6031 | * This function implements pieces of two sequences from BSpec: |
6045 | * This function implements pieces of two sequences from BSpec: |
6032 | * - Sequence for display software to disable LCPLL |
6046 | * - Sequence for display software to disable LCPLL |
6033 | * - Sequence for display software to allow package C8+ |
6047 | * - Sequence for display software to allow package C8+ |
6034 | * The steps implemented here are just the steps that actually touch the LCPLL |
6048 | * The steps implemented here are just the steps that actually touch the LCPLL |
6035 | * register. Callers should take care of disabling all the display engine |
6049 | * register. Callers should take care of disabling all the display engine |
6036 | * functions, doing the mode unset, fixing interrupts, etc. |
6050 | * functions, doing the mode unset, fixing interrupts, etc. |
6037 | */ |
6051 | */ |
6038 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6052 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6039 | bool switch_to_fclk, bool allow_power_down) |
6053 | bool switch_to_fclk, bool allow_power_down) |
6040 | { |
6054 | { |
6041 | uint32_t val; |
6055 | uint32_t val; |
6042 | 6056 | ||
6043 | assert_can_disable_lcpll(dev_priv); |
6057 | assert_can_disable_lcpll(dev_priv); |
6044 | 6058 | ||
6045 | val = I915_READ(LCPLL_CTL); |
6059 | val = I915_READ(LCPLL_CTL); |
6046 | 6060 | ||
6047 | if (switch_to_fclk) { |
6061 | if (switch_to_fclk) { |
6048 | val |= LCPLL_CD_SOURCE_FCLK; |
6062 | val |= LCPLL_CD_SOURCE_FCLK; |
6049 | I915_WRITE(LCPLL_CTL, val); |
6063 | I915_WRITE(LCPLL_CTL, val); |
6050 | 6064 | ||
6051 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
6065 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
6052 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
6066 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
6053 | DRM_ERROR("Switching to FCLK failed\n"); |
6067 | DRM_ERROR("Switching to FCLK failed\n"); |
6054 | 6068 | ||
6055 | val = I915_READ(LCPLL_CTL); |
6069 | val = I915_READ(LCPLL_CTL); |
6056 | } |
6070 | } |
6057 | 6071 | ||
6058 | val |= LCPLL_PLL_DISABLE; |
6072 | val |= LCPLL_PLL_DISABLE; |
6059 | I915_WRITE(LCPLL_CTL, val); |
6073 | I915_WRITE(LCPLL_CTL, val); |
6060 | POSTING_READ(LCPLL_CTL); |
6074 | POSTING_READ(LCPLL_CTL); |
6061 | 6075 | ||
6062 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6076 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6063 | DRM_ERROR("LCPLL still locked\n"); |
6077 | DRM_ERROR("LCPLL still locked\n"); |
6064 | 6078 | ||
6065 | val = I915_READ(D_COMP); |
6079 | val = I915_READ(D_COMP); |
6066 | val |= D_COMP_COMP_DISABLE; |
6080 | val |= D_COMP_COMP_DISABLE; |
6067 | I915_WRITE(D_COMP, val); |
6081 | I915_WRITE(D_COMP, val); |
6068 | POSTING_READ(D_COMP); |
6082 | POSTING_READ(D_COMP); |
6069 | udelay(100); |
6083 | udelay(100); |
6070 | 6084 | ||
6071 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
6085 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
6072 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
6086 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
6073 | 6087 | ||
6074 | if (allow_power_down) { |
6088 | if (allow_power_down) { |
6075 | val = I915_READ(LCPLL_CTL); |
6089 | val = I915_READ(LCPLL_CTL); |
6076 | val |= LCPLL_POWER_DOWN_ALLOW; |
6090 | val |= LCPLL_POWER_DOWN_ALLOW; |
6077 | I915_WRITE(LCPLL_CTL, val); |
6091 | I915_WRITE(LCPLL_CTL, val); |
6078 | POSTING_READ(LCPLL_CTL); |
6092 | POSTING_READ(LCPLL_CTL); |
6079 | } |
6093 | } |
6080 | } |
6094 | } |
6081 | 6095 | ||
6082 | /* |
6096 | /* |
6083 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6097 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6084 | * source. |
6098 | * source. |
6085 | */ |
6099 | */ |
6086 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6100 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6087 | { |
6101 | { |
6088 | uint32_t val; |
6102 | uint32_t val; |
6089 | 6103 | ||
6090 | val = I915_READ(LCPLL_CTL); |
6104 | val = I915_READ(LCPLL_CTL); |
6091 | 6105 | ||
6092 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
6106 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
6093 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6107 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6094 | return; |
6108 | return; |
6095 | 6109 | ||
6096 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6110 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6097 | * we'll hang the machine! */ |
6111 | * we'll hang the machine! */ |
6098 | gen6_gt_force_wake_get(dev_priv); |
6112 | gen6_gt_force_wake_get(dev_priv); |
6099 | 6113 | ||
6100 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6114 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6101 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6115 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6102 | I915_WRITE(LCPLL_CTL, val); |
6116 | I915_WRITE(LCPLL_CTL, val); |
6103 | POSTING_READ(LCPLL_CTL); |
6117 | POSTING_READ(LCPLL_CTL); |
6104 | } |
6118 | } |
6105 | 6119 | ||
6106 | val = I915_READ(D_COMP); |
6120 | val = I915_READ(D_COMP); |
6107 | val |= D_COMP_COMP_FORCE; |
6121 | val |= D_COMP_COMP_FORCE; |
6108 | val &= ~D_COMP_COMP_DISABLE; |
6122 | val &= ~D_COMP_COMP_DISABLE; |
6109 | I915_WRITE(D_COMP, val); |
6123 | I915_WRITE(D_COMP, val); |
6110 | POSTING_READ(D_COMP); |
6124 | POSTING_READ(D_COMP); |
6111 | 6125 | ||
6112 | val = I915_READ(LCPLL_CTL); |
6126 | val = I915_READ(LCPLL_CTL); |
6113 | val &= ~LCPLL_PLL_DISABLE; |
6127 | val &= ~LCPLL_PLL_DISABLE; |
6114 | I915_WRITE(LCPLL_CTL, val); |
6128 | I915_WRITE(LCPLL_CTL, val); |
6115 | 6129 | ||
6116 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
6130 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
6117 | DRM_ERROR("LCPLL not locked yet\n"); |
6131 | DRM_ERROR("LCPLL not locked yet\n"); |
6118 | 6132 | ||
6119 | if (val & LCPLL_CD_SOURCE_FCLK) { |
6133 | if (val & LCPLL_CD_SOURCE_FCLK) { |
6120 | val = I915_READ(LCPLL_CTL); |
6134 | val = I915_READ(LCPLL_CTL); |
6121 | val &= ~LCPLL_CD_SOURCE_FCLK; |
6135 | val &= ~LCPLL_CD_SOURCE_FCLK; |
6122 | I915_WRITE(LCPLL_CTL, val); |
6136 | I915_WRITE(LCPLL_CTL, val); |
6123 | 6137 | ||
6124 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6138 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6125 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6139 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6126 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6140 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6127 | } |
6141 | } |
6128 | 6142 | ||
6129 | gen6_gt_force_wake_put(dev_priv); |
6143 | gen6_gt_force_wake_put(dev_priv); |
6130 | } |
6144 | } |
6131 | 6145 | ||
6132 | void hsw_enable_pc8_work(struct work_struct *__work) |
6146 | void hsw_enable_pc8_work(struct work_struct *__work) |
6133 | { |
6147 | { |
6134 | struct drm_i915_private *dev_priv = |
6148 | struct drm_i915_private *dev_priv = |
6135 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6149 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6136 | pc8.enable_work); |
6150 | pc8.enable_work); |
6137 | struct drm_device *dev = dev_priv->dev; |
6151 | struct drm_device *dev = dev_priv->dev; |
6138 | uint32_t val; |
6152 | uint32_t val; |
6139 | 6153 | ||
6140 | if (dev_priv->pc8.enabled) |
6154 | if (dev_priv->pc8.enabled) |
6141 | return; |
6155 | return; |
6142 | 6156 | ||
6143 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6157 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6144 | 6158 | ||
6145 | dev_priv->pc8.enabled = true; |
6159 | dev_priv->pc8.enabled = true; |
6146 | 6160 | ||
6147 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6161 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6148 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6162 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6149 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6163 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6150 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6164 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6151 | } |
6165 | } |
6152 | 6166 | ||
6153 | lpt_disable_clkout_dp(dev); |
6167 | lpt_disable_clkout_dp(dev); |
6154 | hsw_pc8_disable_interrupts(dev); |
6168 | hsw_pc8_disable_interrupts(dev); |
6155 | hsw_disable_lcpll(dev_priv, true, true); |
6169 | hsw_disable_lcpll(dev_priv, true, true); |
6156 | } |
6170 | } |
6157 | 6171 | ||
6158 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6172 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6159 | { |
6173 | { |
6160 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6174 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6161 | WARN(dev_priv->pc8.disable_count < 1, |
6175 | WARN(dev_priv->pc8.disable_count < 1, |
6162 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6176 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6163 | 6177 | ||
6164 | dev_priv->pc8.disable_count--; |
6178 | dev_priv->pc8.disable_count--; |
6165 | if (dev_priv->pc8.disable_count != 0) |
6179 | if (dev_priv->pc8.disable_count != 0) |
6166 | return; |
6180 | return; |
6167 | 6181 | ||
6168 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
6182 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
6169 | msecs_to_jiffies(i915_pc8_timeout)); |
6183 | msecs_to_jiffies(i915_pc8_timeout)); |
6170 | } |
6184 | } |
6171 | 6185 | ||
6172 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6186 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6173 | { |
6187 | { |
6174 | struct drm_device *dev = dev_priv->dev; |
6188 | struct drm_device *dev = dev_priv->dev; |
6175 | uint32_t val; |
6189 | uint32_t val; |
6176 | 6190 | ||
6177 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6191 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6178 | WARN(dev_priv->pc8.disable_count < 0, |
6192 | WARN(dev_priv->pc8.disable_count < 0, |
6179 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6193 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6180 | 6194 | ||
6181 | dev_priv->pc8.disable_count++; |
6195 | dev_priv->pc8.disable_count++; |
6182 | if (dev_priv->pc8.disable_count != 1) |
6196 | if (dev_priv->pc8.disable_count != 1) |
6183 | return; |
6197 | return; |
6184 | 6198 | ||
6185 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6199 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6186 | if (!dev_priv->pc8.enabled) |
6200 | if (!dev_priv->pc8.enabled) |
6187 | return; |
6201 | return; |
6188 | 6202 | ||
6189 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6203 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6190 | 6204 | ||
6191 | hsw_restore_lcpll(dev_priv); |
6205 | hsw_restore_lcpll(dev_priv); |
6192 | hsw_pc8_restore_interrupts(dev); |
6206 | hsw_pc8_restore_interrupts(dev); |
6193 | lpt_init_pch_refclk(dev); |
6207 | lpt_init_pch_refclk(dev); |
6194 | 6208 | ||
6195 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6209 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6196 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6210 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6197 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6211 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6198 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6212 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6199 | } |
6213 | } |
6200 | 6214 | ||
6201 | intel_prepare_ddi(dev); |
6215 | intel_prepare_ddi(dev); |
6202 | i915_gem_init_swizzling(dev); |
6216 | i915_gem_init_swizzling(dev); |
6203 | mutex_lock(&dev_priv->rps.hw_lock); |
6217 | mutex_lock(&dev_priv->rps.hw_lock); |
6204 | gen6_update_ring_freq(dev); |
6218 | gen6_update_ring_freq(dev); |
6205 | mutex_unlock(&dev_priv->rps.hw_lock); |
6219 | mutex_unlock(&dev_priv->rps.hw_lock); |
6206 | dev_priv->pc8.enabled = false; |
6220 | dev_priv->pc8.enabled = false; |
6207 | } |
6221 | } |
6208 | 6222 | ||
6209 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6223 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6210 | { |
6224 | { |
6211 | mutex_lock(&dev_priv->pc8.lock); |
6225 | mutex_lock(&dev_priv->pc8.lock); |
6212 | __hsw_enable_package_c8(dev_priv); |
6226 | __hsw_enable_package_c8(dev_priv); |
6213 | mutex_unlock(&dev_priv->pc8.lock); |
6227 | mutex_unlock(&dev_priv->pc8.lock); |
6214 | } |
6228 | } |
6215 | 6229 | ||
6216 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6230 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6217 | { |
6231 | { |
6218 | mutex_lock(&dev_priv->pc8.lock); |
6232 | mutex_lock(&dev_priv->pc8.lock); |
6219 | __hsw_disable_package_c8(dev_priv); |
6233 | __hsw_disable_package_c8(dev_priv); |
6220 | mutex_unlock(&dev_priv->pc8.lock); |
6234 | mutex_unlock(&dev_priv->pc8.lock); |
6221 | } |
6235 | } |
6222 | 6236 | ||
6223 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
6237 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
6224 | { |
6238 | { |
6225 | struct drm_device *dev = dev_priv->dev; |
6239 | struct drm_device *dev = dev_priv->dev; |
6226 | struct intel_crtc *crtc; |
6240 | struct intel_crtc *crtc; |
6227 | uint32_t val; |
6241 | uint32_t val; |
6228 | 6242 | ||
6229 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6243 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6230 | if (crtc->base.enabled) |
6244 | if (crtc->base.enabled) |
6231 | return false; |
6245 | return false; |
6232 | 6246 | ||
6233 | /* This case is still possible since we have the i915.disable_power_well |
6247 | /* This case is still possible since we have the i915.disable_power_well |
6234 | * parameter and also the KVMr or something else might be requesting the |
6248 | * parameter and also the KVMr or something else might be requesting the |
6235 | * power well. */ |
6249 | * power well. */ |
6236 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
6250 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
6237 | if (val != 0) { |
6251 | if (val != 0) { |
6238 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
6252 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
6239 | return false; |
6253 | return false; |
6240 | } |
6254 | } |
6241 | 6255 | ||
6242 | return true; |
6256 | return true; |
6243 | } |
6257 | } |
6244 | 6258 | ||
6245 | /* Since we're called from modeset_global_resources there's no way to |
6259 | /* Since we're called from modeset_global_resources there's no way to |
6246 | * symmetrically increase and decrease the refcount, so we use |
6260 | * symmetrically increase and decrease the refcount, so we use |
6247 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
6261 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
6248 | * or not. |
6262 | * or not. |
6249 | */ |
6263 | */ |
6250 | static void hsw_update_package_c8(struct drm_device *dev) |
6264 | static void hsw_update_package_c8(struct drm_device *dev) |
6251 | { |
6265 | { |
6252 | struct drm_i915_private *dev_priv = dev->dev_private; |
6266 | struct drm_i915_private *dev_priv = dev->dev_private; |
6253 | bool allow; |
6267 | bool allow; |
6254 | 6268 | ||
6255 | if (!i915_enable_pc8) |
6269 | if (!i915_enable_pc8) |
6256 | return; |
6270 | return; |
6257 | 6271 | ||
6258 | mutex_lock(&dev_priv->pc8.lock); |
6272 | mutex_lock(&dev_priv->pc8.lock); |
6259 | 6273 | ||
6260 | allow = hsw_can_enable_package_c8(dev_priv); |
6274 | allow = hsw_can_enable_package_c8(dev_priv); |
6261 | 6275 | ||
6262 | if (allow == dev_priv->pc8.requirements_met) |
6276 | if (allow == dev_priv->pc8.requirements_met) |
6263 | goto done; |
6277 | goto done; |
6264 | 6278 | ||
6265 | dev_priv->pc8.requirements_met = allow; |
6279 | dev_priv->pc8.requirements_met = allow; |
6266 | 6280 | ||
6267 | if (allow) |
6281 | if (allow) |
6268 | __hsw_enable_package_c8(dev_priv); |
6282 | __hsw_enable_package_c8(dev_priv); |
6269 | else |
6283 | else |
6270 | __hsw_disable_package_c8(dev_priv); |
6284 | __hsw_disable_package_c8(dev_priv); |
6271 | 6285 | ||
6272 | done: |
6286 | done: |
6273 | mutex_unlock(&dev_priv->pc8.lock); |
6287 | mutex_unlock(&dev_priv->pc8.lock); |
6274 | } |
6288 | } |
6275 | 6289 | ||
6276 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
6290 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
6277 | { |
6291 | { |
6278 | if (!dev_priv->pc8.gpu_idle) { |
6292 | if (!dev_priv->pc8.gpu_idle) { |
6279 | dev_priv->pc8.gpu_idle = true; |
6293 | dev_priv->pc8.gpu_idle = true; |
6280 | hsw_enable_package_c8(dev_priv); |
6294 | hsw_enable_package_c8(dev_priv); |
6281 | } |
6295 | } |
6282 | } |
6296 | } |
6283 | 6297 | ||
6284 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
6298 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
6285 | { |
6299 | { |
6286 | if (dev_priv->pc8.gpu_idle) { |
6300 | if (dev_priv->pc8.gpu_idle) { |
6287 | dev_priv->pc8.gpu_idle = false; |
6301 | dev_priv->pc8.gpu_idle = false; |
6288 | hsw_disable_package_c8(dev_priv); |
6302 | hsw_disable_package_c8(dev_priv); |
6289 | } |
6303 | } |
6290 | } |
6304 | } |
6291 | 6305 | ||
6292 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6306 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6293 | { |
6307 | { |
6294 | bool enable = false; |
6308 | bool enable = false; |
6295 | struct intel_crtc *crtc; |
6309 | struct intel_crtc *crtc; |
6296 | 6310 | ||
6297 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6311 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6298 | if (!crtc->base.enabled) |
6312 | if (!crtc->base.enabled) |
6299 | continue; |
6313 | continue; |
6300 | 6314 | ||
6301 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6315 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6302 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
6316 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
6303 | enable = true; |
6317 | enable = true; |
6304 | } |
6318 | } |
6305 | 6319 | ||
6306 | intel_set_power_well(dev, enable); |
6320 | intel_set_power_well(dev, enable); |
6307 | 6321 | ||
6308 | hsw_update_package_c8(dev); |
6322 | hsw_update_package_c8(dev); |
6309 | } |
6323 | } |
6310 | 6324 | ||
6311 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6325 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6312 | int x, int y, |
6326 | int x, int y, |
6313 | struct drm_framebuffer *fb) |
6327 | struct drm_framebuffer *fb) |
6314 | { |
6328 | { |
6315 | struct drm_device *dev = crtc->dev; |
6329 | struct drm_device *dev = crtc->dev; |
6316 | struct drm_i915_private *dev_priv = dev->dev_private; |
6330 | struct drm_i915_private *dev_priv = dev->dev_private; |
6317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6318 | int plane = intel_crtc->plane; |
6332 | int plane = intel_crtc->plane; |
6319 | int ret; |
6333 | int ret; |
6320 | 6334 | ||
6321 | if (!intel_ddi_pll_mode_set(crtc)) |
6335 | if (!intel_ddi_pll_mode_set(crtc)) |
6322 | return -EINVAL; |
6336 | return -EINVAL; |
6323 | 6337 | ||
6324 | if (intel_crtc->config.has_dp_encoder) |
6338 | if (intel_crtc->config.has_dp_encoder) |
6325 | intel_dp_set_m_n(intel_crtc); |
6339 | intel_dp_set_m_n(intel_crtc); |
6326 | 6340 | ||
6327 | intel_crtc->lowfreq_avail = false; |
6341 | intel_crtc->lowfreq_avail = false; |
6328 | 6342 | ||
6329 | intel_set_pipe_timings(intel_crtc); |
6343 | intel_set_pipe_timings(intel_crtc); |
6330 | 6344 | ||
6331 | if (intel_crtc->config.has_pch_encoder) { |
6345 | if (intel_crtc->config.has_pch_encoder) { |
6332 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6346 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6333 | &intel_crtc->config.fdi_m_n); |
6347 | &intel_crtc->config.fdi_m_n); |
6334 | } |
6348 | } |
6335 | 6349 | ||
6336 | haswell_set_pipeconf(crtc); |
6350 | haswell_set_pipeconf(crtc); |
6337 | 6351 | ||
6338 | intel_set_pipe_csc(crtc); |
6352 | intel_set_pipe_csc(crtc); |
6339 | 6353 | ||
6340 | /* Set up the display plane register */ |
6354 | /* Set up the display plane register */ |
6341 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6355 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6342 | POSTING_READ(DSPCNTR(plane)); |
6356 | POSTING_READ(DSPCNTR(plane)); |
6343 | 6357 | ||
6344 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6358 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6345 | 6359 | ||
6346 | intel_update_watermarks(dev); |
6360 | intel_update_watermarks(dev); |
6347 | 6361 | ||
6348 | return ret; |
6362 | return ret; |
6349 | } |
6363 | } |
6350 | 6364 | ||
6351 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6365 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6352 | struct intel_crtc_config *pipe_config) |
6366 | struct intel_crtc_config *pipe_config) |
6353 | { |
6367 | { |
6354 | struct drm_device *dev = crtc->base.dev; |
6368 | struct drm_device *dev = crtc->base.dev; |
6355 | struct drm_i915_private *dev_priv = dev->dev_private; |
6369 | struct drm_i915_private *dev_priv = dev->dev_private; |
6356 | enum intel_display_power_domain pfit_domain; |
6370 | enum intel_display_power_domain pfit_domain; |
6357 | uint32_t tmp; |
6371 | uint32_t tmp; |
6358 | 6372 | ||
6359 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6373 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6360 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6374 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6361 | 6375 | ||
6362 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6376 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6363 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
6377 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
6364 | enum pipe trans_edp_pipe; |
6378 | enum pipe trans_edp_pipe; |
6365 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
6379 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
6366 | default: |
6380 | default: |
6367 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
6381 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
6368 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
6382 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
6369 | case TRANS_DDI_EDP_INPUT_A_ON: |
6383 | case TRANS_DDI_EDP_INPUT_A_ON: |
6370 | trans_edp_pipe = PIPE_A; |
6384 | trans_edp_pipe = PIPE_A; |
6371 | break; |
6385 | break; |
6372 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
6386 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
6373 | trans_edp_pipe = PIPE_B; |
6387 | trans_edp_pipe = PIPE_B; |
6374 | break; |
6388 | break; |
6375 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
6389 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
6376 | trans_edp_pipe = PIPE_C; |
6390 | trans_edp_pipe = PIPE_C; |
6377 | break; |
6391 | break; |
6378 | } |
6392 | } |
6379 | 6393 | ||
6380 | if (trans_edp_pipe == crtc->pipe) |
6394 | if (trans_edp_pipe == crtc->pipe) |
6381 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
6395 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
6382 | } |
6396 | } |
6383 | 6397 | ||
6384 | if (!intel_display_power_enabled(dev, |
6398 | if (!intel_display_power_enabled(dev, |
6385 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
6399 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
6386 | return false; |
6400 | return false; |
6387 | 6401 | ||
6388 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
6402 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
6389 | if (!(tmp & PIPECONF_ENABLE)) |
6403 | if (!(tmp & PIPECONF_ENABLE)) |
6390 | return false; |
6404 | return false; |
6391 | 6405 | ||
6392 | /* |
6406 | /* |
6393 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
6407 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
6394 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6408 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6395 | * the PCH transcoder is on. |
6409 | * the PCH transcoder is on. |
6396 | */ |
6410 | */ |
6397 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
6411 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
6398 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
6412 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
6399 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
6413 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
6400 | pipe_config->has_pch_encoder = true; |
6414 | pipe_config->has_pch_encoder = true; |
6401 | 6415 | ||
6402 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6416 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6403 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6417 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6404 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6418 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6405 | 6419 | ||
6406 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6420 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6407 | } |
6421 | } |
6408 | 6422 | ||
6409 | intel_get_pipe_timings(crtc, pipe_config); |
6423 | intel_get_pipe_timings(crtc, pipe_config); |
6410 | 6424 | ||
6411 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6425 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6412 | if (intel_display_power_enabled(dev, pfit_domain)) |
6426 | if (intel_display_power_enabled(dev, pfit_domain)) |
6413 | ironlake_get_pfit_config(crtc, pipe_config); |
6427 | ironlake_get_pfit_config(crtc, pipe_config); |
6414 | 6428 | ||
6415 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6429 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6416 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
6430 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
6417 | 6431 | ||
6418 | pipe_config->pixel_multiplier = 1; |
6432 | pipe_config->pixel_multiplier = 1; |
6419 | 6433 | ||
6420 | return true; |
6434 | return true; |
6421 | } |
6435 | } |
6422 | 6436 | ||
6423 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6437 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6424 | int x, int y, |
6438 | int x, int y, |
6425 | struct drm_framebuffer *fb) |
6439 | struct drm_framebuffer *fb) |
6426 | { |
6440 | { |
6427 | struct drm_device *dev = crtc->dev; |
6441 | struct drm_device *dev = crtc->dev; |
6428 | struct drm_i915_private *dev_priv = dev->dev_private; |
6442 | struct drm_i915_private *dev_priv = dev->dev_private; |
6429 | struct intel_encoder *encoder; |
6443 | struct intel_encoder *encoder; |
6430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6431 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
6445 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
6432 | int pipe = intel_crtc->pipe; |
6446 | int pipe = intel_crtc->pipe; |
6433 | int ret; |
6447 | int ret; |
6434 | 6448 | ||
6435 | drm_vblank_pre_modeset(dev, pipe); |
6449 | drm_vblank_pre_modeset(dev, pipe); |
6436 | 6450 | ||
6437 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6451 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6438 | 6452 | ||
6439 | drm_vblank_post_modeset(dev, pipe); |
6453 | drm_vblank_post_modeset(dev, pipe); |
6440 | 6454 | ||
6441 | if (ret != 0) |
6455 | if (ret != 0) |
6442 | return ret; |
6456 | return ret; |
6443 | 6457 | ||
6444 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6458 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6445 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
6459 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
6446 | encoder->base.base.id, |
6460 | encoder->base.base.id, |
6447 | drm_get_encoder_name(&encoder->base), |
6461 | drm_get_encoder_name(&encoder->base), |
6448 | mode->base.id, mode->name); |
6462 | mode->base.id, mode->name); |
6449 | encoder->mode_set(encoder); |
6463 | encoder->mode_set(encoder); |
6450 | } |
6464 | } |
6451 | 6465 | ||
6452 | return 0; |
6466 | return 0; |
6453 | } |
6467 | } |
6454 | 6468 | ||
6455 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6469 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6456 | int reg_eldv, uint32_t bits_eldv, |
6470 | int reg_eldv, uint32_t bits_eldv, |
6457 | int reg_elda, uint32_t bits_elda, |
6471 | int reg_elda, uint32_t bits_elda, |
6458 | int reg_edid) |
6472 | int reg_edid) |
6459 | { |
6473 | { |
6460 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6474 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6461 | uint8_t *eld = connector->eld; |
6475 | uint8_t *eld = connector->eld; |
6462 | uint32_t i; |
6476 | uint32_t i; |
6463 | 6477 | ||
6464 | i = I915_READ(reg_eldv); |
6478 | i = I915_READ(reg_eldv); |
6465 | i &= bits_eldv; |
6479 | i &= bits_eldv; |
6466 | 6480 | ||
6467 | if (!eld[0]) |
6481 | if (!eld[0]) |
6468 | return !i; |
6482 | return !i; |
6469 | 6483 | ||
6470 | if (!i) |
6484 | if (!i) |
6471 | return false; |
6485 | return false; |
6472 | 6486 | ||
6473 | i = I915_READ(reg_elda); |
6487 | i = I915_READ(reg_elda); |
6474 | i &= ~bits_elda; |
6488 | i &= ~bits_elda; |
6475 | I915_WRITE(reg_elda, i); |
6489 | I915_WRITE(reg_elda, i); |
6476 | 6490 | ||
6477 | for (i = 0; i < eld[2]; i++) |
6491 | for (i = 0; i < eld[2]; i++) |
6478 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
6492 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
6479 | return false; |
6493 | return false; |
6480 | 6494 | ||
6481 | return true; |
6495 | return true; |
6482 | } |
6496 | } |
6483 | 6497 | ||
6484 | static void g4x_write_eld(struct drm_connector *connector, |
6498 | static void g4x_write_eld(struct drm_connector *connector, |
6485 | struct drm_crtc *crtc) |
6499 | struct drm_crtc *crtc) |
6486 | { |
6500 | { |
6487 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6501 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6488 | uint8_t *eld = connector->eld; |
6502 | uint8_t *eld = connector->eld; |
6489 | uint32_t eldv; |
6503 | uint32_t eldv; |
6490 | uint32_t len; |
6504 | uint32_t len; |
6491 | uint32_t i; |
6505 | uint32_t i; |
6492 | 6506 | ||
6493 | i = I915_READ(G4X_AUD_VID_DID); |
6507 | i = I915_READ(G4X_AUD_VID_DID); |
6494 | 6508 | ||
6495 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
6509 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
6496 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
6510 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
6497 | else |
6511 | else |
6498 | eldv = G4X_ELDV_DEVCTG; |
6512 | eldv = G4X_ELDV_DEVCTG; |
6499 | 6513 | ||
6500 | if (intel_eld_uptodate(connector, |
6514 | if (intel_eld_uptodate(connector, |
6501 | G4X_AUD_CNTL_ST, eldv, |
6515 | G4X_AUD_CNTL_ST, eldv, |
6502 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
6516 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
6503 | G4X_HDMIW_HDMIEDID)) |
6517 | G4X_HDMIW_HDMIEDID)) |
6504 | return; |
6518 | return; |
6505 | 6519 | ||
6506 | i = I915_READ(G4X_AUD_CNTL_ST); |
6520 | i = I915_READ(G4X_AUD_CNTL_ST); |
6507 | i &= ~(eldv | G4X_ELD_ADDR); |
6521 | i &= ~(eldv | G4X_ELD_ADDR); |
6508 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
6522 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
6509 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6523 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6510 | 6524 | ||
6511 | if (!eld[0]) |
6525 | if (!eld[0]) |
6512 | return; |
6526 | return; |
6513 | 6527 | ||
6514 | len = min_t(uint8_t, eld[2], len); |
6528 | len = min_t(uint8_t, eld[2], len); |
6515 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6529 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6516 | for (i = 0; i < len; i++) |
6530 | for (i = 0; i < len; i++) |
6517 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
6531 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
6518 | 6532 | ||
6519 | i = I915_READ(G4X_AUD_CNTL_ST); |
6533 | i = I915_READ(G4X_AUD_CNTL_ST); |
6520 | i |= eldv; |
6534 | i |= eldv; |
6521 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6535 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6522 | } |
6536 | } |
6523 | 6537 | ||
6524 | static void haswell_write_eld(struct drm_connector *connector, |
6538 | static void haswell_write_eld(struct drm_connector *connector, |
6525 | struct drm_crtc *crtc) |
6539 | struct drm_crtc *crtc) |
6526 | { |
6540 | { |
6527 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6541 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6528 | uint8_t *eld = connector->eld; |
6542 | uint8_t *eld = connector->eld; |
6529 | struct drm_device *dev = crtc->dev; |
6543 | struct drm_device *dev = crtc->dev; |
6530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6544 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6531 | uint32_t eldv; |
6545 | uint32_t eldv; |
6532 | uint32_t i; |
6546 | uint32_t i; |
6533 | int len; |
6547 | int len; |
6534 | int pipe = to_intel_crtc(crtc)->pipe; |
6548 | int pipe = to_intel_crtc(crtc)->pipe; |
6535 | int tmp; |
6549 | int tmp; |
6536 | 6550 | ||
6537 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
6551 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
6538 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
6552 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
6539 | int aud_config = HSW_AUD_CFG(pipe); |
6553 | int aud_config = HSW_AUD_CFG(pipe); |
6540 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
6554 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
6541 | 6555 | ||
6542 | 6556 | ||
6543 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
6557 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
6544 | 6558 | ||
6545 | /* Audio output enable */ |
6559 | /* Audio output enable */ |
6546 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
6560 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
6547 | tmp = I915_READ(aud_cntrl_st2); |
6561 | tmp = I915_READ(aud_cntrl_st2); |
6548 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
6562 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
6549 | I915_WRITE(aud_cntrl_st2, tmp); |
6563 | I915_WRITE(aud_cntrl_st2, tmp); |
6550 | 6564 | ||
6551 | /* Wait for 1 vertical blank */ |
6565 | /* Wait for 1 vertical blank */ |
6552 | intel_wait_for_vblank(dev, pipe); |
6566 | intel_wait_for_vblank(dev, pipe); |
6553 | 6567 | ||
6554 | /* Set ELD valid state */ |
6568 | /* Set ELD valid state */ |
6555 | tmp = I915_READ(aud_cntrl_st2); |
6569 | tmp = I915_READ(aud_cntrl_st2); |
6556 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
6570 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
6557 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6571 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6558 | I915_WRITE(aud_cntrl_st2, tmp); |
6572 | I915_WRITE(aud_cntrl_st2, tmp); |
6559 | tmp = I915_READ(aud_cntrl_st2); |
6573 | tmp = I915_READ(aud_cntrl_st2); |
6560 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
6574 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
6561 | 6575 | ||
6562 | /* Enable HDMI mode */ |
6576 | /* Enable HDMI mode */ |
6563 | tmp = I915_READ(aud_config); |
6577 | tmp = I915_READ(aud_config); |
6564 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
6578 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
6565 | /* clear N_programing_enable and N_value_index */ |
6579 | /* clear N_programing_enable and N_value_index */ |
6566 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
6580 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
6567 | I915_WRITE(aud_config, tmp); |
6581 | I915_WRITE(aud_config, tmp); |
6568 | 6582 | ||
6569 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6583 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6570 | 6584 | ||
6571 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
6585 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
6572 | intel_crtc->eld_vld = true; |
6586 | intel_crtc->eld_vld = true; |
6573 | 6587 | ||
6574 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6588 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6575 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6589 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6576 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6590 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6577 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6591 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6578 | } else |
6592 | } else |
6579 | I915_WRITE(aud_config, 0); |
6593 | I915_WRITE(aud_config, 0); |
6580 | 6594 | ||
6581 | if (intel_eld_uptodate(connector, |
6595 | if (intel_eld_uptodate(connector, |
6582 | aud_cntrl_st2, eldv, |
6596 | aud_cntrl_st2, eldv, |
6583 | aud_cntl_st, IBX_ELD_ADDRESS, |
6597 | aud_cntl_st, IBX_ELD_ADDRESS, |
6584 | hdmiw_hdmiedid)) |
6598 | hdmiw_hdmiedid)) |
6585 | return; |
6599 | return; |
6586 | 6600 | ||
6587 | i = I915_READ(aud_cntrl_st2); |
6601 | i = I915_READ(aud_cntrl_st2); |
6588 | i &= ~eldv; |
6602 | i &= ~eldv; |
6589 | I915_WRITE(aud_cntrl_st2, i); |
6603 | I915_WRITE(aud_cntrl_st2, i); |
6590 | 6604 | ||
6591 | if (!eld[0]) |
6605 | if (!eld[0]) |
6592 | return; |
6606 | return; |
6593 | 6607 | ||
6594 | i = I915_READ(aud_cntl_st); |
6608 | i = I915_READ(aud_cntl_st); |
6595 | i &= ~IBX_ELD_ADDRESS; |
6609 | i &= ~IBX_ELD_ADDRESS; |
6596 | I915_WRITE(aud_cntl_st, i); |
6610 | I915_WRITE(aud_cntl_st, i); |
6597 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6611 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6598 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
6612 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
6599 | 6613 | ||
6600 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6614 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6601 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6615 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6602 | for (i = 0; i < len; i++) |
6616 | for (i = 0; i < len; i++) |
6603 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6617 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6604 | 6618 | ||
6605 | i = I915_READ(aud_cntrl_st2); |
6619 | i = I915_READ(aud_cntrl_st2); |
6606 | i |= eldv; |
6620 | i |= eldv; |
6607 | I915_WRITE(aud_cntrl_st2, i); |
6621 | I915_WRITE(aud_cntrl_st2, i); |
6608 | 6622 | ||
6609 | } |
6623 | } |
6610 | 6624 | ||
6611 | static void ironlake_write_eld(struct drm_connector *connector, |
6625 | static void ironlake_write_eld(struct drm_connector *connector, |
6612 | struct drm_crtc *crtc) |
6626 | struct drm_crtc *crtc) |
6613 | { |
6627 | { |
6614 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6628 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6615 | uint8_t *eld = connector->eld; |
6629 | uint8_t *eld = connector->eld; |
6616 | uint32_t eldv; |
6630 | uint32_t eldv; |
6617 | uint32_t i; |
6631 | uint32_t i; |
6618 | int len; |
6632 | int len; |
6619 | int hdmiw_hdmiedid; |
6633 | int hdmiw_hdmiedid; |
6620 | int aud_config; |
6634 | int aud_config; |
6621 | int aud_cntl_st; |
6635 | int aud_cntl_st; |
6622 | int aud_cntrl_st2; |
6636 | int aud_cntrl_st2; |
6623 | int pipe = to_intel_crtc(crtc)->pipe; |
6637 | int pipe = to_intel_crtc(crtc)->pipe; |
6624 | 6638 | ||
6625 | if (HAS_PCH_IBX(connector->dev)) { |
6639 | if (HAS_PCH_IBX(connector->dev)) { |
6626 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6640 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6627 | aud_config = IBX_AUD_CFG(pipe); |
6641 | aud_config = IBX_AUD_CFG(pipe); |
6628 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
6642 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
6629 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
6643 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
6630 | } else { |
6644 | } else { |
6631 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6645 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6632 | aud_config = CPT_AUD_CFG(pipe); |
6646 | aud_config = CPT_AUD_CFG(pipe); |
6633 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
6647 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
6634 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6648 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6635 | } |
6649 | } |
6636 | 6650 | ||
6637 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6651 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6638 | 6652 | ||
6639 | i = I915_READ(aud_cntl_st); |
6653 | i = I915_READ(aud_cntl_st); |
6640 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6654 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6641 | if (!i) { |
6655 | if (!i) { |
6642 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
6656 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
6643 | /* operate blindly on all ports */ |
6657 | /* operate blindly on all ports */ |
6644 | eldv = IBX_ELD_VALIDB; |
6658 | eldv = IBX_ELD_VALIDB; |
6645 | eldv |= IBX_ELD_VALIDB << 4; |
6659 | eldv |= IBX_ELD_VALIDB << 4; |
6646 | eldv |= IBX_ELD_VALIDB << 8; |
6660 | eldv |= IBX_ELD_VALIDB << 8; |
6647 | } else { |
6661 | } else { |
6648 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
6662 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
6649 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
6663 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
6650 | } |
6664 | } |
6651 | 6665 | ||
6652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6666 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6653 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6667 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6654 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6668 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6655 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6669 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6656 | } else |
6670 | } else |
6657 | I915_WRITE(aud_config, 0); |
6671 | I915_WRITE(aud_config, 0); |
6658 | 6672 | ||
6659 | if (intel_eld_uptodate(connector, |
6673 | if (intel_eld_uptodate(connector, |
6660 | aud_cntrl_st2, eldv, |
6674 | aud_cntrl_st2, eldv, |
6661 | aud_cntl_st, IBX_ELD_ADDRESS, |
6675 | aud_cntl_st, IBX_ELD_ADDRESS, |
6662 | hdmiw_hdmiedid)) |
6676 | hdmiw_hdmiedid)) |
6663 | return; |
6677 | return; |
6664 | 6678 | ||
6665 | i = I915_READ(aud_cntrl_st2); |
6679 | i = I915_READ(aud_cntrl_st2); |
6666 | i &= ~eldv; |
6680 | i &= ~eldv; |
6667 | I915_WRITE(aud_cntrl_st2, i); |
6681 | I915_WRITE(aud_cntrl_st2, i); |
6668 | 6682 | ||
6669 | if (!eld[0]) |
6683 | if (!eld[0]) |
6670 | return; |
6684 | return; |
6671 | 6685 | ||
6672 | i = I915_READ(aud_cntl_st); |
6686 | i = I915_READ(aud_cntl_st); |
6673 | i &= ~IBX_ELD_ADDRESS; |
6687 | i &= ~IBX_ELD_ADDRESS; |
6674 | I915_WRITE(aud_cntl_st, i); |
6688 | I915_WRITE(aud_cntl_st, i); |
6675 | 6689 | ||
6676 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6690 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6677 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6691 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6678 | for (i = 0; i < len; i++) |
6692 | for (i = 0; i < len; i++) |
6679 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6693 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6680 | 6694 | ||
6681 | i = I915_READ(aud_cntrl_st2); |
6695 | i = I915_READ(aud_cntrl_st2); |
6682 | i |= eldv; |
6696 | i |= eldv; |
6683 | I915_WRITE(aud_cntrl_st2, i); |
6697 | I915_WRITE(aud_cntrl_st2, i); |
6684 | } |
6698 | } |
6685 | 6699 | ||
6686 | void intel_write_eld(struct drm_encoder *encoder, |
6700 | void intel_write_eld(struct drm_encoder *encoder, |
6687 | struct drm_display_mode *mode) |
6701 | struct drm_display_mode *mode) |
6688 | { |
6702 | { |
6689 | struct drm_crtc *crtc = encoder->crtc; |
6703 | struct drm_crtc *crtc = encoder->crtc; |
6690 | struct drm_connector *connector; |
6704 | struct drm_connector *connector; |
6691 | struct drm_device *dev = encoder->dev; |
6705 | struct drm_device *dev = encoder->dev; |
6692 | struct drm_i915_private *dev_priv = dev->dev_private; |
6706 | struct drm_i915_private *dev_priv = dev->dev_private; |
6693 | 6707 | ||
6694 | connector = drm_select_eld(encoder, mode); |
6708 | connector = drm_select_eld(encoder, mode); |
6695 | if (!connector) |
6709 | if (!connector) |
6696 | return; |
6710 | return; |
6697 | 6711 | ||
6698 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6712 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6699 | connector->base.id, |
6713 | connector->base.id, |
6700 | drm_get_connector_name(connector), |
6714 | drm_get_connector_name(connector), |
6701 | connector->encoder->base.id, |
6715 | connector->encoder->base.id, |
6702 | drm_get_encoder_name(connector->encoder)); |
6716 | drm_get_encoder_name(connector->encoder)); |
6703 | 6717 | ||
6704 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
6718 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
6705 | 6719 | ||
6706 | if (dev_priv->display.write_eld) |
6720 | if (dev_priv->display.write_eld) |
6707 | dev_priv->display.write_eld(connector, crtc); |
6721 | dev_priv->display.write_eld(connector, crtc); |
6708 | } |
6722 | } |
6709 | 6723 | ||
6710 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6724 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6711 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
6725 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
6712 | { |
6726 | { |
6713 | struct drm_device *dev = crtc->dev; |
6727 | struct drm_device *dev = crtc->dev; |
6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
6728 | struct drm_i915_private *dev_priv = dev->dev_private; |
6715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6716 | enum pipe pipe = intel_crtc->pipe; |
6730 | enum pipe pipe = intel_crtc->pipe; |
6717 | int palreg = PALETTE(pipe); |
6731 | int palreg = PALETTE(pipe); |
6718 | int i; |
6732 | int i; |
6719 | bool reenable_ips = false; |
6733 | bool reenable_ips = false; |
6720 | 6734 | ||
6721 | /* The clocks have to be on to load the palette. */ |
6735 | /* The clocks have to be on to load the palette. */ |
6722 | if (!crtc->enabled || !intel_crtc->active) |
6736 | if (!crtc->enabled || !intel_crtc->active) |
6723 | return; |
6737 | return; |
6724 | 6738 | ||
6725 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6739 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6726 | assert_pll_enabled(dev_priv, pipe); |
6740 | assert_pll_enabled(dev_priv, pipe); |
6727 | 6741 | ||
6728 | /* use legacy palette for Ironlake */ |
6742 | /* use legacy palette for Ironlake */ |
6729 | if (HAS_PCH_SPLIT(dev)) |
6743 | if (HAS_PCH_SPLIT(dev)) |
6730 | palreg = LGC_PALETTE(pipe); |
6744 | palreg = LGC_PALETTE(pipe); |
6731 | 6745 | ||
6732 | /* Workaround : Do not read or write the pipe palette/gamma data while |
6746 | /* Workaround : Do not read or write the pipe palette/gamma data while |
6733 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
6747 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
6734 | */ |
6748 | */ |
6735 | if (intel_crtc->config.ips_enabled && |
6749 | if (intel_crtc->config.ips_enabled && |
6736 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
6750 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
6737 | GAMMA_MODE_MODE_SPLIT)) { |
6751 | GAMMA_MODE_MODE_SPLIT)) { |
6738 | hsw_disable_ips(intel_crtc); |
6752 | hsw_disable_ips(intel_crtc); |
6739 | reenable_ips = true; |
6753 | reenable_ips = true; |
6740 | } |
6754 | } |
6741 | 6755 | ||
6742 | for (i = 0; i < 256; i++) { |
6756 | for (i = 0; i < 256; i++) { |
6743 | I915_WRITE(palreg + 4 * i, |
6757 | I915_WRITE(palreg + 4 * i, |
6744 | (intel_crtc->lut_r[i] << 16) | |
6758 | (intel_crtc->lut_r[i] << 16) | |
6745 | (intel_crtc->lut_g[i] << 8) | |
6759 | (intel_crtc->lut_g[i] << 8) | |
6746 | intel_crtc->lut_b[i]); |
6760 | intel_crtc->lut_b[i]); |
6747 | } |
6761 | } |
6748 | 6762 | ||
6749 | if (reenable_ips) |
6763 | if (reenable_ips) |
6750 | hsw_enable_ips(intel_crtc); |
6764 | hsw_enable_ips(intel_crtc); |
6751 | } |
6765 | } |
6752 | 6766 | ||
6753 | #if 0 |
6767 | #if 0 |
6754 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6768 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6755 | { |
6769 | { |
6756 | struct drm_device *dev = crtc->dev; |
6770 | struct drm_device *dev = crtc->dev; |
6757 | struct drm_i915_private *dev_priv = dev->dev_private; |
6771 | struct drm_i915_private *dev_priv = dev->dev_private; |
6758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6759 | bool visible = base != 0; |
6773 | bool visible = base != 0; |
6760 | u32 cntl; |
6774 | u32 cntl; |
6761 | 6775 | ||
6762 | if (intel_crtc->cursor_visible == visible) |
6776 | if (intel_crtc->cursor_visible == visible) |
6763 | return; |
6777 | return; |
6764 | 6778 | ||
6765 | cntl = I915_READ(_CURACNTR); |
6779 | cntl = I915_READ(_CURACNTR); |
6766 | if (visible) { |
6780 | if (visible) { |
6767 | /* On these chipsets we can only modify the base whilst |
6781 | /* On these chipsets we can only modify the base whilst |
6768 | * the cursor is disabled. |
6782 | * the cursor is disabled. |
6769 | */ |
6783 | */ |
6770 | I915_WRITE(_CURABASE, base); |
6784 | I915_WRITE(_CURABASE, base); |
6771 | 6785 | ||
6772 | cntl &= ~(CURSOR_FORMAT_MASK); |
6786 | cntl &= ~(CURSOR_FORMAT_MASK); |
6773 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
6787 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
6774 | cntl |= CURSOR_ENABLE | |
6788 | cntl |= CURSOR_ENABLE | |
6775 | CURSOR_GAMMA_ENABLE | |
6789 | CURSOR_GAMMA_ENABLE | |
6776 | CURSOR_FORMAT_ARGB; |
6790 | CURSOR_FORMAT_ARGB; |
6777 | } else |
6791 | } else |
6778 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
6792 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
6779 | I915_WRITE(_CURACNTR, cntl); |
6793 | I915_WRITE(_CURACNTR, cntl); |
6780 | 6794 | ||
6781 | intel_crtc->cursor_visible = visible; |
6795 | intel_crtc->cursor_visible = visible; |
6782 | } |
6796 | } |
6783 | 6797 | ||
6784 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6798 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6785 | { |
6799 | { |
6786 | struct drm_device *dev = crtc->dev; |
6800 | struct drm_device *dev = crtc->dev; |
6787 | struct drm_i915_private *dev_priv = dev->dev_private; |
6801 | struct drm_i915_private *dev_priv = dev->dev_private; |
6788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6789 | int pipe = intel_crtc->pipe; |
6803 | int pipe = intel_crtc->pipe; |
6790 | bool visible = base != 0; |
6804 | bool visible = base != 0; |
6791 | 6805 | ||
6792 | if (intel_crtc->cursor_visible != visible) { |
6806 | if (intel_crtc->cursor_visible != visible) { |
6793 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
6807 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
6794 | if (base) { |
6808 | if (base) { |
6795 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
6809 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
6796 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6810 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6797 | cntl |= pipe << 28; /* Connect to correct pipe */ |
6811 | cntl |= pipe << 28; /* Connect to correct pipe */ |
6798 | } else { |
6812 | } else { |
6799 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6813 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6800 | cntl |= CURSOR_MODE_DISABLE; |
6814 | cntl |= CURSOR_MODE_DISABLE; |
6801 | } |
6815 | } |
6802 | I915_WRITE(CURCNTR(pipe), cntl); |
6816 | I915_WRITE(CURCNTR(pipe), cntl); |
6803 | 6817 | ||
6804 | intel_crtc->cursor_visible = visible; |
6818 | intel_crtc->cursor_visible = visible; |
6805 | } |
6819 | } |
6806 | /* and commit changes on next vblank */ |
6820 | /* and commit changes on next vblank */ |
6807 | POSTING_READ(CURCNTR(pipe)); |
6821 | POSTING_READ(CURCNTR(pipe)); |
6808 | I915_WRITE(CURBASE(pipe), base); |
6822 | I915_WRITE(CURBASE(pipe), base); |
6809 | POSTING_READ(CURBASE(pipe)); |
6823 | POSTING_READ(CURBASE(pipe)); |
6810 | } |
6824 | } |
6811 | 6825 | ||
6812 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6826 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6813 | { |
6827 | { |
6814 | struct drm_device *dev = crtc->dev; |
6828 | struct drm_device *dev = crtc->dev; |
6815 | struct drm_i915_private *dev_priv = dev->dev_private; |
6829 | struct drm_i915_private *dev_priv = dev->dev_private; |
6816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6817 | int pipe = intel_crtc->pipe; |
6831 | int pipe = intel_crtc->pipe; |
6818 | bool visible = base != 0; |
6832 | bool visible = base != 0; |
6819 | 6833 | ||
6820 | if (intel_crtc->cursor_visible != visible) { |
6834 | if (intel_crtc->cursor_visible != visible) { |
6821 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
6835 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
6822 | if (base) { |
6836 | if (base) { |
6823 | cntl &= ~CURSOR_MODE; |
6837 | cntl &= ~CURSOR_MODE; |
6824 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6838 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6825 | } else { |
6839 | } else { |
6826 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6840 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6827 | cntl |= CURSOR_MODE_DISABLE; |
6841 | cntl |= CURSOR_MODE_DISABLE; |
6828 | } |
6842 | } |
6829 | if (IS_HASWELL(dev)) { |
6843 | if (IS_HASWELL(dev)) { |
6830 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
6844 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
6831 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6845 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6832 | } |
6846 | } |
6833 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6847 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6834 | 6848 | ||
6835 | intel_crtc->cursor_visible = visible; |
6849 | intel_crtc->cursor_visible = visible; |
6836 | } |
6850 | } |
6837 | /* and commit changes on next vblank */ |
6851 | /* and commit changes on next vblank */ |
6838 | POSTING_READ(CURCNTR_IVB(pipe)); |
6852 | POSTING_READ(CURCNTR_IVB(pipe)); |
6839 | I915_WRITE(CURBASE_IVB(pipe), base); |
6853 | I915_WRITE(CURBASE_IVB(pipe), base); |
6840 | POSTING_READ(CURBASE_IVB(pipe)); |
6854 | POSTING_READ(CURBASE_IVB(pipe)); |
6841 | } |
6855 | } |
6842 | 6856 | ||
6843 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6857 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6844 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6858 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6845 | bool on) |
6859 | bool on) |
6846 | { |
6860 | { |
6847 | struct drm_device *dev = crtc->dev; |
6861 | struct drm_device *dev = crtc->dev; |
6848 | struct drm_i915_private *dev_priv = dev->dev_private; |
6862 | struct drm_i915_private *dev_priv = dev->dev_private; |
6849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6863 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6850 | int pipe = intel_crtc->pipe; |
6864 | int pipe = intel_crtc->pipe; |
6851 | int x = intel_crtc->cursor_x; |
6865 | int x = intel_crtc->cursor_x; |
6852 | int y = intel_crtc->cursor_y; |
6866 | int y = intel_crtc->cursor_y; |
6853 | u32 base, pos; |
6867 | u32 base, pos; |
6854 | bool visible; |
6868 | bool visible; |
6855 | 6869 | ||
6856 | pos = 0; |
6870 | pos = 0; |
6857 | 6871 | ||
6858 | if (on && crtc->enabled && crtc->fb) { |
6872 | if (on && crtc->enabled && crtc->fb) { |
6859 | base = intel_crtc->cursor_addr; |
6873 | base = intel_crtc->cursor_addr; |
6860 | if (x > (int) crtc->fb->width) |
6874 | if (x > (int) crtc->fb->width) |
6861 | base = 0; |
6875 | base = 0; |
6862 | 6876 | ||
6863 | if (y > (int) crtc->fb->height) |
6877 | if (y > (int) crtc->fb->height) |
6864 | base = 0; |
6878 | base = 0; |
6865 | } else |
6879 | } else |
6866 | base = 0; |
6880 | base = 0; |
6867 | 6881 | ||
6868 | if (x < 0) { |
6882 | if (x < 0) { |
6869 | if (x + intel_crtc->cursor_width < 0) |
6883 | if (x + intel_crtc->cursor_width < 0) |
6870 | base = 0; |
6884 | base = 0; |
6871 | 6885 | ||
6872 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6886 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6873 | x = -x; |
6887 | x = -x; |
6874 | } |
6888 | } |
6875 | pos |= x << CURSOR_X_SHIFT; |
6889 | pos |= x << CURSOR_X_SHIFT; |
6876 | 6890 | ||
6877 | if (y < 0) { |
6891 | if (y < 0) { |
6878 | if (y + intel_crtc->cursor_height < 0) |
6892 | if (y + intel_crtc->cursor_height < 0) |
6879 | base = 0; |
6893 | base = 0; |
6880 | 6894 | ||
6881 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
6895 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
6882 | y = -y; |
6896 | y = -y; |
6883 | } |
6897 | } |
6884 | pos |= y << CURSOR_Y_SHIFT; |
6898 | pos |= y << CURSOR_Y_SHIFT; |
6885 | 6899 | ||
6886 | visible = base != 0; |
6900 | visible = base != 0; |
6887 | if (!visible && !intel_crtc->cursor_visible) |
6901 | if (!visible && !intel_crtc->cursor_visible) |
6888 | return; |
6902 | return; |
6889 | 6903 | ||
6890 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
6904 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
6891 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6905 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6892 | ivb_update_cursor(crtc, base); |
6906 | ivb_update_cursor(crtc, base); |
6893 | } else { |
6907 | } else { |
6894 | I915_WRITE(CURPOS(pipe), pos); |
6908 | I915_WRITE(CURPOS(pipe), pos); |
6895 | if (IS_845G(dev) || IS_I865G(dev)) |
6909 | if (IS_845G(dev) || IS_I865G(dev)) |
6896 | i845_update_cursor(crtc, base); |
6910 | i845_update_cursor(crtc, base); |
6897 | else |
6911 | else |
6898 | i9xx_update_cursor(crtc, base); |
6912 | i9xx_update_cursor(crtc, base); |
6899 | } |
6913 | } |
6900 | } |
6914 | } |
6901 | 6915 | ||
6902 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
6916 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
6903 | struct drm_file *file, |
6917 | struct drm_file *file, |
6904 | uint32_t handle, |
6918 | uint32_t handle, |
6905 | uint32_t width, uint32_t height) |
6919 | uint32_t width, uint32_t height) |
6906 | { |
6920 | { |
6907 | struct drm_device *dev = crtc->dev; |
6921 | struct drm_device *dev = crtc->dev; |
6908 | struct drm_i915_private *dev_priv = dev->dev_private; |
6922 | struct drm_i915_private *dev_priv = dev->dev_private; |
6909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6910 | struct drm_i915_gem_object *obj; |
6924 | struct drm_i915_gem_object *obj; |
6911 | uint32_t addr; |
6925 | uint32_t addr; |
6912 | int ret; |
6926 | int ret; |
6913 | 6927 | ||
6914 | /* if we want to turn off the cursor ignore width and height */ |
6928 | /* if we want to turn off the cursor ignore width and height */ |
6915 | if (!handle) { |
6929 | if (!handle) { |
6916 | DRM_DEBUG_KMS("cursor off\n"); |
6930 | DRM_DEBUG_KMS("cursor off\n"); |
6917 | addr = 0; |
6931 | addr = 0; |
6918 | obj = NULL; |
6932 | obj = NULL; |
6919 | mutex_lock(&dev->struct_mutex); |
6933 | mutex_lock(&dev->struct_mutex); |
6920 | goto finish; |
6934 | goto finish; |
6921 | } |
6935 | } |
6922 | 6936 | ||
6923 | /* Currently we only support 64x64 cursors */ |
6937 | /* Currently we only support 64x64 cursors */ |
6924 | if (width != 64 || height != 64) { |
6938 | if (width != 64 || height != 64) { |
6925 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
6939 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
6926 | return -EINVAL; |
6940 | return -EINVAL; |
6927 | } |
6941 | } |
6928 | 6942 | ||
6929 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
6943 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
6930 | if (&obj->base == NULL) |
6944 | if (&obj->base == NULL) |
6931 | return -ENOENT; |
6945 | return -ENOENT; |
6932 | 6946 | ||
6933 | if (obj->base.size < width * height * 4) { |
6947 | if (obj->base.size < width * height * 4) { |
6934 | DRM_ERROR("buffer is to small\n"); |
6948 | DRM_ERROR("buffer is to small\n"); |
6935 | ret = -ENOMEM; |
6949 | ret = -ENOMEM; |
6936 | goto fail; |
6950 | goto fail; |
6937 | } |
6951 | } |
6938 | 6952 | ||
6939 | /* we only need to pin inside GTT if cursor is non-phy */ |
6953 | /* we only need to pin inside GTT if cursor is non-phy */ |
6940 | mutex_lock(&dev->struct_mutex); |
6954 | mutex_lock(&dev->struct_mutex); |
6941 | if (!dev_priv->info->cursor_needs_physical) { |
6955 | if (!dev_priv->info->cursor_needs_physical) { |
6942 | unsigned alignment; |
6956 | unsigned alignment; |
6943 | 6957 | ||
6944 | if (obj->tiling_mode) { |
6958 | if (obj->tiling_mode) { |
6945 | DRM_ERROR("cursor cannot be tiled\n"); |
6959 | DRM_ERROR("cursor cannot be tiled\n"); |
6946 | ret = -EINVAL; |
6960 | ret = -EINVAL; |
6947 | goto fail_locked; |
6961 | goto fail_locked; |
6948 | } |
6962 | } |
6949 | 6963 | ||
6950 | /* Note that the w/a also requires 2 PTE of padding following |
6964 | /* Note that the w/a also requires 2 PTE of padding following |
6951 | * the bo. We currently fill all unused PTE with the shadow |
6965 | * the bo. We currently fill all unused PTE with the shadow |
6952 | * page and so we should always have valid PTE following the |
6966 | * page and so we should always have valid PTE following the |
6953 | * cursor preventing the VT-d warning. |
6967 | * cursor preventing the VT-d warning. |
6954 | */ |
6968 | */ |
6955 | alignment = 0; |
6969 | alignment = 0; |
6956 | if (need_vtd_wa(dev)) |
6970 | if (need_vtd_wa(dev)) |
6957 | alignment = 64*1024; |
6971 | alignment = 64*1024; |
6958 | 6972 | ||
6959 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
6973 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
6960 | if (ret) { |
6974 | if (ret) { |
6961 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
6975 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
6962 | goto fail_locked; |
6976 | goto fail_locked; |
6963 | } |
6977 | } |
6964 | 6978 | ||
6965 | ret = i915_gem_object_put_fence(obj); |
6979 | ret = i915_gem_object_put_fence(obj); |
6966 | if (ret) { |
6980 | if (ret) { |
6967 | DRM_ERROR("failed to release fence for cursor"); |
6981 | DRM_ERROR("failed to release fence for cursor"); |
6968 | goto fail_unpin; |
6982 | goto fail_unpin; |
6969 | } |
6983 | } |
6970 | 6984 | ||
6971 | addr = i915_gem_obj_ggtt_offset(obj); |
6985 | addr = i915_gem_obj_ggtt_offset(obj); |
6972 | } else { |
6986 | } else { |
6973 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
6987 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
6974 | ret = i915_gem_attach_phys_object(dev, obj, |
6988 | ret = i915_gem_attach_phys_object(dev, obj, |
6975 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6989 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6976 | align); |
6990 | align); |
6977 | if (ret) { |
6991 | if (ret) { |
6978 | DRM_ERROR("failed to attach phys object\n"); |
6992 | DRM_ERROR("failed to attach phys object\n"); |
6979 | goto fail_locked; |
6993 | goto fail_locked; |
6980 | } |
6994 | } |
6981 | addr = obj->phys_obj->handle->busaddr; |
6995 | addr = obj->phys_obj->handle->busaddr; |
6982 | } |
6996 | } |
6983 | 6997 | ||
6984 | if (IS_GEN2(dev)) |
6998 | if (IS_GEN2(dev)) |
6985 | I915_WRITE(CURSIZE, (height << 12) | width); |
6999 | I915_WRITE(CURSIZE, (height << 12) | width); |
6986 | 7000 | ||
6987 | finish: |
7001 | finish: |
6988 | if (intel_crtc->cursor_bo) { |
7002 | if (intel_crtc->cursor_bo) { |
6989 | if (dev_priv->info->cursor_needs_physical) { |
7003 | if (dev_priv->info->cursor_needs_physical) { |
6990 | if (intel_crtc->cursor_bo != obj) |
7004 | if (intel_crtc->cursor_bo != obj) |
6991 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7005 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6992 | } else |
7006 | } else |
6993 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
7007 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
6994 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
7008 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
6995 | } |
7009 | } |
6996 | 7010 | ||
6997 | mutex_unlock(&dev->struct_mutex); |
7011 | mutex_unlock(&dev->struct_mutex); |
6998 | 7012 | ||
6999 | intel_crtc->cursor_addr = addr; |
7013 | intel_crtc->cursor_addr = addr; |
7000 | intel_crtc->cursor_bo = obj; |
7014 | intel_crtc->cursor_bo = obj; |
7001 | intel_crtc->cursor_width = width; |
7015 | intel_crtc->cursor_width = width; |
7002 | intel_crtc->cursor_height = height; |
7016 | intel_crtc->cursor_height = height; |
7003 | 7017 | ||
7004 | if (intel_crtc->active) |
7018 | if (intel_crtc->active) |
7005 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7019 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7006 | 7020 | ||
7007 | return 0; |
7021 | return 0; |
7008 | fail_unpin: |
7022 | fail_unpin: |
7009 | i915_gem_object_unpin_from_display_plane(obj); |
7023 | i915_gem_object_unpin_from_display_plane(obj); |
7010 | fail_locked: |
7024 | fail_locked: |
7011 | mutex_unlock(&dev->struct_mutex); |
7025 | mutex_unlock(&dev->struct_mutex); |
7012 | fail: |
7026 | fail: |
7013 | drm_gem_object_unreference_unlocked(&obj->base); |
7027 | drm_gem_object_unreference_unlocked(&obj->base); |
7014 | return ret; |
7028 | return ret; |
7015 | } |
7029 | } |
7016 | 7030 | ||
7017 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7031 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7018 | { |
7032 | { |
7019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7033 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7020 | 7034 | ||
7021 | intel_crtc->cursor_x = x; |
7035 | intel_crtc->cursor_x = x; |
7022 | intel_crtc->cursor_y = y; |
7036 | intel_crtc->cursor_y = y; |
7023 | 7037 | ||
7024 | if (intel_crtc->active) |
7038 | if (intel_crtc->active) |
7025 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7039 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7026 | 7040 | ||
7027 | return 0; |
7041 | return 0; |
7028 | } |
7042 | } |
7029 | #endif |
7043 | #endif |
7030 | 7044 | ||
7031 | /** Sets the color ramps on behalf of RandR */ |
7045 | /** Sets the color ramps on behalf of RandR */ |
7032 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
7046 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
7033 | u16 blue, int regno) |
7047 | u16 blue, int regno) |
7034 | { |
7048 | { |
7035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7036 | 7050 | ||
7037 | intel_crtc->lut_r[regno] = red >> 8; |
7051 | intel_crtc->lut_r[regno] = red >> 8; |
7038 | intel_crtc->lut_g[regno] = green >> 8; |
7052 | intel_crtc->lut_g[regno] = green >> 8; |
7039 | intel_crtc->lut_b[regno] = blue >> 8; |
7053 | intel_crtc->lut_b[regno] = blue >> 8; |
7040 | } |
7054 | } |
7041 | 7055 | ||
7042 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
7056 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
7043 | u16 *blue, int regno) |
7057 | u16 *blue, int regno) |
7044 | { |
7058 | { |
7045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7046 | 7060 | ||
7047 | *red = intel_crtc->lut_r[regno] << 8; |
7061 | *red = intel_crtc->lut_r[regno] << 8; |
7048 | *green = intel_crtc->lut_g[regno] << 8; |
7062 | *green = intel_crtc->lut_g[regno] << 8; |
7049 | *blue = intel_crtc->lut_b[regno] << 8; |
7063 | *blue = intel_crtc->lut_b[regno] << 8; |
7050 | } |
7064 | } |
7051 | 7065 | ||
7052 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7066 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7053 | u16 *blue, uint32_t start, uint32_t size) |
7067 | u16 *blue, uint32_t start, uint32_t size) |
7054 | { |
7068 | { |
7055 | int end = (start + size > 256) ? 256 : start + size, i; |
7069 | int end = (start + size > 256) ? 256 : start + size, i; |
7056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7057 | 7071 | ||
7058 | for (i = start; i < end; i++) { |
7072 | for (i = start; i < end; i++) { |
7059 | intel_crtc->lut_r[i] = red[i] >> 8; |
7073 | intel_crtc->lut_r[i] = red[i] >> 8; |
7060 | intel_crtc->lut_g[i] = green[i] >> 8; |
7074 | intel_crtc->lut_g[i] = green[i] >> 8; |
7061 | intel_crtc->lut_b[i] = blue[i] >> 8; |
7075 | intel_crtc->lut_b[i] = blue[i] >> 8; |
7062 | } |
7076 | } |
7063 | 7077 | ||
7064 | intel_crtc_load_lut(crtc); |
7078 | intel_crtc_load_lut(crtc); |
7065 | } |
7079 | } |
7066 | 7080 | ||
7067 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7081 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7068 | static struct drm_display_mode load_detect_mode = { |
7082 | static struct drm_display_mode load_detect_mode = { |
7069 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7083 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7070 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7084 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7071 | }; |
7085 | }; |
7072 | 7086 | ||
7073 | static struct drm_framebuffer * |
7087 | static struct drm_framebuffer * |
7074 | intel_framebuffer_create(struct drm_device *dev, |
7088 | intel_framebuffer_create(struct drm_device *dev, |
7075 | struct drm_mode_fb_cmd2 *mode_cmd, |
7089 | struct drm_mode_fb_cmd2 *mode_cmd, |
7076 | struct drm_i915_gem_object *obj) |
7090 | struct drm_i915_gem_object *obj) |
7077 | { |
7091 | { |
7078 | struct intel_framebuffer *intel_fb; |
7092 | struct intel_framebuffer *intel_fb; |
7079 | int ret; |
7093 | int ret; |
7080 | 7094 | ||
7081 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7095 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7082 | if (!intel_fb) { |
7096 | if (!intel_fb) { |
7083 | drm_gem_object_unreference_unlocked(&obj->base); |
7097 | drm_gem_object_unreference_unlocked(&obj->base); |
7084 | return ERR_PTR(-ENOMEM); |
7098 | return ERR_PTR(-ENOMEM); |
7085 | } |
7099 | } |
7086 | 7100 | ||
7087 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7101 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7088 | if (ret) { |
7102 | if (ret) { |
7089 | drm_gem_object_unreference_unlocked(&obj->base); |
7103 | drm_gem_object_unreference_unlocked(&obj->base); |
7090 | kfree(intel_fb); |
7104 | kfree(intel_fb); |
7091 | return ERR_PTR(ret); |
7105 | return ERR_PTR(ret); |
7092 | } |
7106 | } |
7093 | 7107 | ||
7094 | return &intel_fb->base; |
7108 | return &intel_fb->base; |
7095 | } |
7109 | } |
7096 | 7110 | ||
7097 | static u32 |
7111 | static u32 |
7098 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7112 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7099 | { |
7113 | { |
7100 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7114 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7101 | return ALIGN(pitch, 64); |
7115 | return ALIGN(pitch, 64); |
7102 | } |
7116 | } |
7103 | 7117 | ||
7104 | static u32 |
7118 | static u32 |
7105 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7119 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7106 | { |
7120 | { |
7107 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7121 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7108 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
7122 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
7109 | } |
7123 | } |
7110 | 7124 | ||
7111 | static struct drm_framebuffer * |
7125 | static struct drm_framebuffer * |
7112 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7126 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7113 | struct drm_display_mode *mode, |
7127 | struct drm_display_mode *mode, |
7114 | int depth, int bpp) |
7128 | int depth, int bpp) |
7115 | { |
7129 | { |
7116 | struct drm_i915_gem_object *obj; |
7130 | struct drm_i915_gem_object *obj; |
7117 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
7131 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
7118 | 7132 | ||
7119 | return NULL; |
7133 | return NULL; |
7120 | } |
7134 | } |
7121 | 7135 | ||
7122 | static struct drm_framebuffer * |
7136 | static struct drm_framebuffer * |
7123 | mode_fits_in_fbdev(struct drm_device *dev, |
7137 | mode_fits_in_fbdev(struct drm_device *dev, |
7124 | struct drm_display_mode *mode) |
7138 | struct drm_display_mode *mode) |
7125 | { |
7139 | { |
7126 | struct drm_i915_private *dev_priv = dev->dev_private; |
7140 | struct drm_i915_private *dev_priv = dev->dev_private; |
7127 | struct drm_i915_gem_object *obj; |
7141 | struct drm_i915_gem_object *obj; |
7128 | struct drm_framebuffer *fb; |
7142 | struct drm_framebuffer *fb; |
7129 | 7143 | ||
7130 | if (dev_priv->fbdev == NULL) |
7144 | if (dev_priv->fbdev == NULL) |
7131 | return NULL; |
7145 | return NULL; |
7132 | 7146 | ||
7133 | obj = dev_priv->fbdev->ifb.obj; |
7147 | obj = dev_priv->fbdev->ifb.obj; |
7134 | if (obj == NULL) |
7148 | if (obj == NULL) |
7135 | return NULL; |
7149 | return NULL; |
7136 | 7150 | ||
7137 | fb = &dev_priv->fbdev->ifb.base; |
7151 | fb = &dev_priv->fbdev->ifb.base; |
7138 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7152 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7139 | fb->bits_per_pixel)) |
7153 | fb->bits_per_pixel)) |
7140 | return NULL; |
7154 | return NULL; |
7141 | 7155 | ||
7142 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7156 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7143 | return NULL; |
7157 | return NULL; |
7144 | 7158 | ||
7145 | return fb; |
7159 | return fb; |
7146 | } |
7160 | } |
7147 | 7161 | ||
7148 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7162 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7149 | struct drm_display_mode *mode, |
7163 | struct drm_display_mode *mode, |
7150 | struct intel_load_detect_pipe *old) |
7164 | struct intel_load_detect_pipe *old) |
7151 | { |
7165 | { |
7152 | struct intel_crtc *intel_crtc; |
7166 | struct intel_crtc *intel_crtc; |
7153 | struct intel_encoder *intel_encoder = |
7167 | struct intel_encoder *intel_encoder = |
7154 | intel_attached_encoder(connector); |
7168 | intel_attached_encoder(connector); |
7155 | struct drm_crtc *possible_crtc; |
7169 | struct drm_crtc *possible_crtc; |
7156 | struct drm_encoder *encoder = &intel_encoder->base; |
7170 | struct drm_encoder *encoder = &intel_encoder->base; |
7157 | struct drm_crtc *crtc = NULL; |
7171 | struct drm_crtc *crtc = NULL; |
7158 | struct drm_device *dev = encoder->dev; |
7172 | struct drm_device *dev = encoder->dev; |
7159 | struct drm_framebuffer *fb; |
7173 | struct drm_framebuffer *fb; |
7160 | int i = -1; |
7174 | int i = -1; |
7161 | 7175 | ||
7162 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7176 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7163 | connector->base.id, drm_get_connector_name(connector), |
7177 | connector->base.id, drm_get_connector_name(connector), |
7164 | encoder->base.id, drm_get_encoder_name(encoder)); |
7178 | encoder->base.id, drm_get_encoder_name(encoder)); |
7165 | 7179 | ||
7166 | /* |
7180 | /* |
7167 | * Algorithm gets a little messy: |
7181 | * Algorithm gets a little messy: |
7168 | * |
7182 | * |
7169 | * - if the connector already has an assigned crtc, use it (but make |
7183 | * - if the connector already has an assigned crtc, use it (but make |
7170 | * sure it's on first) |
7184 | * sure it's on first) |
7171 | * |
7185 | * |
7172 | * - try to find the first unused crtc that can drive this connector, |
7186 | * - try to find the first unused crtc that can drive this connector, |
7173 | * and use that if we find one |
7187 | * and use that if we find one |
7174 | */ |
7188 | */ |
7175 | 7189 | ||
7176 | /* See if we already have a CRTC for this connector */ |
7190 | /* See if we already have a CRTC for this connector */ |
7177 | if (encoder->crtc) { |
7191 | if (encoder->crtc) { |
7178 | crtc = encoder->crtc; |
7192 | crtc = encoder->crtc; |
7179 | 7193 | ||
7180 | mutex_lock(&crtc->mutex); |
7194 | mutex_lock(&crtc->mutex); |
7181 | 7195 | ||
7182 | old->dpms_mode = connector->dpms; |
7196 | old->dpms_mode = connector->dpms; |
7183 | old->load_detect_temp = false; |
7197 | old->load_detect_temp = false; |
7184 | 7198 | ||
7185 | /* Make sure the crtc and connector are running */ |
7199 | /* Make sure the crtc and connector are running */ |
7186 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7200 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7187 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
7201 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
7188 | 7202 | ||
7189 | return true; |
7203 | return true; |
7190 | } |
7204 | } |
7191 | 7205 | ||
7192 | /* Find an unused one (if possible) */ |
7206 | /* Find an unused one (if possible) */ |
7193 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
7207 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
7194 | i++; |
7208 | i++; |
7195 | if (!(encoder->possible_crtcs & (1 << i))) |
7209 | if (!(encoder->possible_crtcs & (1 << i))) |
7196 | continue; |
7210 | continue; |
7197 | if (!possible_crtc->enabled) { |
7211 | if (!possible_crtc->enabled) { |
7198 | crtc = possible_crtc; |
7212 | crtc = possible_crtc; |
7199 | break; |
7213 | break; |
7200 | } |
7214 | } |
7201 | } |
7215 | } |
7202 | 7216 | ||
7203 | /* |
7217 | /* |
7204 | * If we didn't find an unused CRTC, don't use any. |
7218 | * If we didn't find an unused CRTC, don't use any. |
7205 | */ |
7219 | */ |
7206 | if (!crtc) { |
7220 | if (!crtc) { |
7207 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7221 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7208 | return false; |
7222 | return false; |
7209 | } |
7223 | } |
7210 | 7224 | ||
7211 | mutex_lock(&crtc->mutex); |
7225 | mutex_lock(&crtc->mutex); |
7212 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7226 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7213 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7227 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7214 | 7228 | ||
7215 | intel_crtc = to_intel_crtc(crtc); |
7229 | intel_crtc = to_intel_crtc(crtc); |
7216 | old->dpms_mode = connector->dpms; |
7230 | old->dpms_mode = connector->dpms; |
7217 | old->load_detect_temp = true; |
7231 | old->load_detect_temp = true; |
7218 | old->release_fb = NULL; |
7232 | old->release_fb = NULL; |
7219 | 7233 | ||
7220 | if (!mode) |
7234 | if (!mode) |
7221 | mode = &load_detect_mode; |
7235 | mode = &load_detect_mode; |
7222 | 7236 | ||
7223 | /* We need a framebuffer large enough to accommodate all accesses |
7237 | /* We need a framebuffer large enough to accommodate all accesses |
7224 | * that the plane may generate whilst we perform load detection. |
7238 | * that the plane may generate whilst we perform load detection. |
7225 | * We can not rely on the fbcon either being present (we get called |
7239 | * We can not rely on the fbcon either being present (we get called |
7226 | * during its initialisation to detect all boot displays, or it may |
7240 | * during its initialisation to detect all boot displays, or it may |
7227 | * not even exist) or that it is large enough to satisfy the |
7241 | * not even exist) or that it is large enough to satisfy the |
7228 | * requested mode. |
7242 | * requested mode. |
7229 | */ |
7243 | */ |
7230 | fb = mode_fits_in_fbdev(dev, mode); |
7244 | fb = mode_fits_in_fbdev(dev, mode); |
7231 | if (fb == NULL) { |
7245 | if (fb == NULL) { |
7232 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
7246 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
7233 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7247 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7234 | old->release_fb = fb; |
7248 | old->release_fb = fb; |
7235 | } else |
7249 | } else |
7236 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7250 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7237 | if (IS_ERR(fb)) { |
7251 | if (IS_ERR(fb)) { |
7238 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7252 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7239 | mutex_unlock(&crtc->mutex); |
7253 | mutex_unlock(&crtc->mutex); |
7240 | return false; |
7254 | return false; |
7241 | } |
7255 | } |
7242 | 7256 | ||
7243 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7257 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7244 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7258 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7245 | if (old->release_fb) |
7259 | if (old->release_fb) |
7246 | old->release_fb->funcs->destroy(old->release_fb); |
7260 | old->release_fb->funcs->destroy(old->release_fb); |
7247 | mutex_unlock(&crtc->mutex); |
7261 | mutex_unlock(&crtc->mutex); |
7248 | return false; |
7262 | return false; |
7249 | } |
7263 | } |
7250 | 7264 | ||
7251 | /* let the connector get through one full cycle before testing */ |
7265 | /* let the connector get through one full cycle before testing */ |
7252 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7266 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7253 | return true; |
7267 | return true; |
7254 | } |
7268 | } |
7255 | 7269 | ||
7256 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7270 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7257 | struct intel_load_detect_pipe *old) |
7271 | struct intel_load_detect_pipe *old) |
7258 | { |
7272 | { |
7259 | struct intel_encoder *intel_encoder = |
7273 | struct intel_encoder *intel_encoder = |
7260 | intel_attached_encoder(connector); |
7274 | intel_attached_encoder(connector); |
7261 | struct drm_encoder *encoder = &intel_encoder->base; |
7275 | struct drm_encoder *encoder = &intel_encoder->base; |
7262 | struct drm_crtc *crtc = encoder->crtc; |
7276 | struct drm_crtc *crtc = encoder->crtc; |
7263 | 7277 | ||
7264 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7278 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7265 | connector->base.id, drm_get_connector_name(connector), |
7279 | connector->base.id, drm_get_connector_name(connector), |
7266 | encoder->base.id, drm_get_encoder_name(encoder)); |
7280 | encoder->base.id, drm_get_encoder_name(encoder)); |
7267 | 7281 | ||
7268 | if (old->load_detect_temp) { |
7282 | if (old->load_detect_temp) { |
7269 | to_intel_connector(connector)->new_encoder = NULL; |
7283 | to_intel_connector(connector)->new_encoder = NULL; |
7270 | intel_encoder->new_crtc = NULL; |
7284 | intel_encoder->new_crtc = NULL; |
7271 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
7285 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
7272 | 7286 | ||
7273 | if (old->release_fb) { |
7287 | if (old->release_fb) { |
7274 | drm_framebuffer_unregister_private(old->release_fb); |
7288 | drm_framebuffer_unregister_private(old->release_fb); |
7275 | drm_framebuffer_unreference(old->release_fb); |
7289 | drm_framebuffer_unreference(old->release_fb); |
7276 | } |
7290 | } |
7277 | 7291 | ||
7278 | mutex_unlock(&crtc->mutex); |
7292 | mutex_unlock(&crtc->mutex); |
7279 | return; |
7293 | return; |
7280 | } |
7294 | } |
7281 | 7295 | ||
7282 | /* Switch crtc and encoder back off if necessary */ |
7296 | /* Switch crtc and encoder back off if necessary */ |
7283 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7297 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7284 | connector->funcs->dpms(connector, old->dpms_mode); |
7298 | connector->funcs->dpms(connector, old->dpms_mode); |
7285 | 7299 | ||
7286 | mutex_unlock(&crtc->mutex); |
7300 | mutex_unlock(&crtc->mutex); |
7287 | } |
7301 | } |
7288 | 7302 | ||
7289 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7303 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7290 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7304 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7291 | struct intel_crtc_config *pipe_config) |
7305 | struct intel_crtc_config *pipe_config) |
7292 | { |
7306 | { |
7293 | struct drm_device *dev = crtc->base.dev; |
7307 | struct drm_device *dev = crtc->base.dev; |
7294 | struct drm_i915_private *dev_priv = dev->dev_private; |
7308 | struct drm_i915_private *dev_priv = dev->dev_private; |
7295 | int pipe = pipe_config->cpu_transcoder; |
7309 | int pipe = pipe_config->cpu_transcoder; |
7296 | u32 dpll = I915_READ(DPLL(pipe)); |
7310 | u32 dpll = I915_READ(DPLL(pipe)); |
7297 | u32 fp; |
7311 | u32 fp; |
7298 | intel_clock_t clock; |
7312 | intel_clock_t clock; |
7299 | 7313 | ||
7300 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7314 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7301 | fp = I915_READ(FP0(pipe)); |
7315 | fp = I915_READ(FP0(pipe)); |
7302 | else |
7316 | else |
7303 | fp = I915_READ(FP1(pipe)); |
7317 | fp = I915_READ(FP1(pipe)); |
7304 | 7318 | ||
7305 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7319 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7306 | if (IS_PINEVIEW(dev)) { |
7320 | if (IS_PINEVIEW(dev)) { |
7307 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
7321 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
7308 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7322 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7309 | } else { |
7323 | } else { |
7310 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
7324 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
7311 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7325 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7312 | } |
7326 | } |
7313 | 7327 | ||
7314 | if (!IS_GEN2(dev)) { |
7328 | if (!IS_GEN2(dev)) { |
7315 | if (IS_PINEVIEW(dev)) |
7329 | if (IS_PINEVIEW(dev)) |
7316 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
7330 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
7317 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
7331 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
7318 | else |
7332 | else |
7319 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
7333 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
7320 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7334 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7321 | 7335 | ||
7322 | switch (dpll & DPLL_MODE_MASK) { |
7336 | switch (dpll & DPLL_MODE_MASK) { |
7323 | case DPLLB_MODE_DAC_SERIAL: |
7337 | case DPLLB_MODE_DAC_SERIAL: |
7324 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
7338 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
7325 | 5 : 10; |
7339 | 5 : 10; |
7326 | break; |
7340 | break; |
7327 | case DPLLB_MODE_LVDS: |
7341 | case DPLLB_MODE_LVDS: |
7328 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
7342 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
7329 | 7 : 14; |
7343 | 7 : 14; |
7330 | break; |
7344 | break; |
7331 | default: |
7345 | default: |
7332 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7346 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7333 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7347 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7334 | pipe_config->adjusted_mode.clock = 0; |
7348 | pipe_config->adjusted_mode.clock = 0; |
7335 | return; |
7349 | return; |
7336 | } |
7350 | } |
7337 | 7351 | ||
7338 | if (IS_PINEVIEW(dev)) |
7352 | if (IS_PINEVIEW(dev)) |
7339 | pineview_clock(96000, &clock); |
7353 | pineview_clock(96000, &clock); |
7340 | else |
7354 | else |
7341 | i9xx_clock(96000, &clock); |
7355 | i9xx_clock(96000, &clock); |
7342 | } else { |
7356 | } else { |
7343 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
7357 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
7344 | 7358 | ||
7345 | if (is_lvds) { |
7359 | if (is_lvds) { |
7346 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7360 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7347 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7361 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7348 | clock.p2 = 14; |
7362 | clock.p2 = 14; |
7349 | 7363 | ||
7350 | if ((dpll & PLL_REF_INPUT_MASK) == |
7364 | if ((dpll & PLL_REF_INPUT_MASK) == |
7351 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
7365 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
7352 | /* XXX: might not be 66MHz */ |
7366 | /* XXX: might not be 66MHz */ |
7353 | i9xx_clock(66000, &clock); |
7367 | i9xx_clock(66000, &clock); |
7354 | } else |
7368 | } else |
7355 | i9xx_clock(48000, &clock); |
7369 | i9xx_clock(48000, &clock); |
7356 | } else { |
7370 | } else { |
7357 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7371 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7358 | clock.p1 = 2; |
7372 | clock.p1 = 2; |
7359 | else { |
7373 | else { |
7360 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
7374 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
7361 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
7375 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
7362 | } |
7376 | } |
7363 | if (dpll & PLL_P2_DIVIDE_BY_4) |
7377 | if (dpll & PLL_P2_DIVIDE_BY_4) |
7364 | clock.p2 = 4; |
7378 | clock.p2 = 4; |
7365 | else |
7379 | else |
7366 | clock.p2 = 2; |
7380 | clock.p2 = 2; |
7367 | 7381 | ||
7368 | i9xx_clock(48000, &clock); |
7382 | i9xx_clock(48000, &clock); |
7369 | } |
7383 | } |
7370 | } |
7384 | } |
7371 | 7385 | ||
7372 | pipe_config->adjusted_mode.clock = clock.dot; |
7386 | pipe_config->adjusted_mode.clock = clock.dot; |
7373 | } |
7387 | } |
7374 | 7388 | ||
7375 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
7389 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
7376 | struct intel_crtc_config *pipe_config) |
7390 | struct intel_crtc_config *pipe_config) |
7377 | { |
7391 | { |
7378 | struct drm_device *dev = crtc->base.dev; |
7392 | struct drm_device *dev = crtc->base.dev; |
7379 | struct drm_i915_private *dev_priv = dev->dev_private; |
7393 | struct drm_i915_private *dev_priv = dev->dev_private; |
7380 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7394 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7381 | int link_freq, repeat; |
7395 | int link_freq, repeat; |
7382 | u64 clock; |
7396 | u64 clock; |
7383 | u32 link_m, link_n; |
7397 | u32 link_m, link_n; |
7384 | 7398 | ||
7385 | repeat = pipe_config->pixel_multiplier; |
7399 | repeat = pipe_config->pixel_multiplier; |
7386 | 7400 | ||
7387 | /* |
7401 | /* |
7388 | * The calculation for the data clock is: |
7402 | * The calculation for the data clock is: |
7389 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
7403 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
7390 | * But we want to avoid losing precison if possible, so: |
7404 | * But we want to avoid losing precison if possible, so: |
7391 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
7405 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
7392 | * |
7406 | * |
7393 | * and the link clock is simpler: |
7407 | * and the link clock is simpler: |
7394 | * link_clock = (m * link_clock * repeat) / n |
7408 | * link_clock = (m * link_clock * repeat) / n |
7395 | */ |
7409 | */ |
7396 | 7410 | ||
7397 | /* |
7411 | /* |
7398 | * We need to get the FDI or DP link clock here to derive |
7412 | * We need to get the FDI or DP link clock here to derive |
7399 | * the M/N dividers. |
7413 | * the M/N dividers. |
7400 | * |
7414 | * |
7401 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
7415 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
7402 | * For DP, it's either 1.62GHz or 2.7GHz. |
7416 | * For DP, it's either 1.62GHz or 2.7GHz. |
7403 | * We do our calculations in 10*MHz since we don't need much precison. |
7417 | * We do our calculations in 10*MHz since we don't need much precison. |
7404 | */ |
7418 | */ |
7405 | if (pipe_config->has_pch_encoder) |
7419 | if (pipe_config->has_pch_encoder) |
7406 | link_freq = intel_fdi_link_freq(dev) * 10000; |
7420 | link_freq = intel_fdi_link_freq(dev) * 10000; |
7407 | else |
7421 | else |
7408 | link_freq = pipe_config->port_clock; |
7422 | link_freq = pipe_config->port_clock; |
7409 | 7423 | ||
7410 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
7424 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
7411 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
7425 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
7412 | 7426 | ||
7413 | if (!link_m || !link_n) |
7427 | if (!link_m || !link_n) |
7414 | return; |
7428 | return; |
7415 | 7429 | ||
7416 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
7430 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
7417 | do_div(clock, link_n); |
7431 | do_div(clock, link_n); |
7418 | 7432 | ||
7419 | pipe_config->adjusted_mode.clock = clock; |
7433 | pipe_config->adjusted_mode.clock = clock; |
7420 | } |
7434 | } |
7421 | 7435 | ||
7422 | /** Returns the currently programmed mode of the given pipe. */ |
7436 | /** Returns the currently programmed mode of the given pipe. */ |
7423 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
7437 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
7424 | struct drm_crtc *crtc) |
7438 | struct drm_crtc *crtc) |
7425 | { |
7439 | { |
7426 | struct drm_i915_private *dev_priv = dev->dev_private; |
7440 | struct drm_i915_private *dev_priv = dev->dev_private; |
7427 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7428 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
7442 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
7429 | struct drm_display_mode *mode; |
7443 | struct drm_display_mode *mode; |
7430 | struct intel_crtc_config pipe_config; |
7444 | struct intel_crtc_config pipe_config; |
7431 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7445 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7432 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
7446 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
7433 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
7447 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
7434 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
7448 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
7435 | 7449 | ||
7436 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7450 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7437 | if (!mode) |
7451 | if (!mode) |
7438 | return NULL; |
7452 | return NULL; |
7439 | 7453 | ||
7440 | /* |
7454 | /* |
7441 | * Construct a pipe_config sufficient for getting the clock info |
7455 | * Construct a pipe_config sufficient for getting the clock info |
7442 | * back out of crtc_clock_get. |
7456 | * back out of crtc_clock_get. |
7443 | * |
7457 | * |
7444 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
7458 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
7445 | * to use a real value here instead. |
7459 | * to use a real value here instead. |
7446 | */ |
7460 | */ |
7447 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
7461 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
7448 | pipe_config.pixel_multiplier = 1; |
7462 | pipe_config.pixel_multiplier = 1; |
7449 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7463 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7450 | 7464 | ||
7451 | mode->clock = pipe_config.adjusted_mode.clock; |
7465 | mode->clock = pipe_config.adjusted_mode.clock; |
7452 | mode->hdisplay = (htot & 0xffff) + 1; |
7466 | mode->hdisplay = (htot & 0xffff) + 1; |
7453 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
7467 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
7454 | mode->hsync_start = (hsync & 0xffff) + 1; |
7468 | mode->hsync_start = (hsync & 0xffff) + 1; |
7455 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
7469 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
7456 | mode->vdisplay = (vtot & 0xffff) + 1; |
7470 | mode->vdisplay = (vtot & 0xffff) + 1; |
7457 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
7471 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
7458 | mode->vsync_start = (vsync & 0xffff) + 1; |
7472 | mode->vsync_start = (vsync & 0xffff) + 1; |
7459 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
7473 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
7460 | 7474 | ||
7461 | drm_mode_set_name(mode); |
7475 | drm_mode_set_name(mode); |
7462 | 7476 | ||
7463 | return mode; |
7477 | return mode; |
7464 | } |
7478 | } |
7465 | 7479 | ||
7466 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
7480 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
7467 | { |
7481 | { |
7468 | struct drm_device *dev = crtc->dev; |
7482 | struct drm_device *dev = crtc->dev; |
7469 | drm_i915_private_t *dev_priv = dev->dev_private; |
7483 | drm_i915_private_t *dev_priv = dev->dev_private; |
7470 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7484 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7471 | int pipe = intel_crtc->pipe; |
7485 | int pipe = intel_crtc->pipe; |
7472 | int dpll_reg = DPLL(pipe); |
7486 | int dpll_reg = DPLL(pipe); |
7473 | int dpll; |
7487 | int dpll; |
7474 | 7488 | ||
7475 | if (HAS_PCH_SPLIT(dev)) |
7489 | if (HAS_PCH_SPLIT(dev)) |
7476 | return; |
7490 | return; |
7477 | 7491 | ||
7478 | if (!dev_priv->lvds_downclock_avail) |
7492 | if (!dev_priv->lvds_downclock_avail) |
7479 | return; |
7493 | return; |
7480 | 7494 | ||
7481 | dpll = I915_READ(dpll_reg); |
7495 | dpll = I915_READ(dpll_reg); |
7482 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
7496 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
7483 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
7497 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
7484 | 7498 | ||
7485 | assert_panel_unlocked(dev_priv, pipe); |
7499 | assert_panel_unlocked(dev_priv, pipe); |
7486 | 7500 | ||
7487 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
7501 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
7488 | I915_WRITE(dpll_reg, dpll); |
7502 | I915_WRITE(dpll_reg, dpll); |
7489 | intel_wait_for_vblank(dev, pipe); |
7503 | intel_wait_for_vblank(dev, pipe); |
7490 | 7504 | ||
7491 | dpll = I915_READ(dpll_reg); |
7505 | dpll = I915_READ(dpll_reg); |
7492 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
7506 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
7493 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
7507 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
7494 | } |
7508 | } |
7495 | } |
7509 | } |
7496 | 7510 | ||
7497 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
7511 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
7498 | { |
7512 | { |
7499 | struct drm_device *dev = crtc->dev; |
7513 | struct drm_device *dev = crtc->dev; |
7500 | drm_i915_private_t *dev_priv = dev->dev_private; |
7514 | drm_i915_private_t *dev_priv = dev->dev_private; |
7501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7502 | 7516 | ||
7503 | if (HAS_PCH_SPLIT(dev)) |
7517 | if (HAS_PCH_SPLIT(dev)) |
7504 | return; |
7518 | return; |
7505 | 7519 | ||
7506 | if (!dev_priv->lvds_downclock_avail) |
7520 | if (!dev_priv->lvds_downclock_avail) |
7507 | return; |
7521 | return; |
7508 | 7522 | ||
7509 | /* |
7523 | /* |
7510 | * Since this is called by a timer, we should never get here in |
7524 | * Since this is called by a timer, we should never get here in |
7511 | * the manual case. |
7525 | * the manual case. |
7512 | */ |
7526 | */ |
7513 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
7527 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
7514 | int pipe = intel_crtc->pipe; |
7528 | int pipe = intel_crtc->pipe; |
7515 | int dpll_reg = DPLL(pipe); |
7529 | int dpll_reg = DPLL(pipe); |
7516 | int dpll; |
7530 | int dpll; |
7517 | 7531 | ||
7518 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
7532 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
7519 | 7533 | ||
7520 | assert_panel_unlocked(dev_priv, pipe); |
7534 | assert_panel_unlocked(dev_priv, pipe); |
7521 | 7535 | ||
7522 | dpll = I915_READ(dpll_reg); |
7536 | dpll = I915_READ(dpll_reg); |
7523 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7537 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7524 | I915_WRITE(dpll_reg, dpll); |
7538 | I915_WRITE(dpll_reg, dpll); |
7525 | intel_wait_for_vblank(dev, pipe); |
7539 | intel_wait_for_vblank(dev, pipe); |
7526 | dpll = I915_READ(dpll_reg); |
7540 | dpll = I915_READ(dpll_reg); |
7527 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
7541 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
7528 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
7542 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
7529 | } |
7543 | } |
7530 | 7544 | ||
7531 | } |
7545 | } |
7532 | 7546 | ||
7533 | void intel_mark_busy(struct drm_device *dev) |
7547 | void intel_mark_busy(struct drm_device *dev) |
7534 | { |
7548 | { |
7535 | struct drm_i915_private *dev_priv = dev->dev_private; |
7549 | struct drm_i915_private *dev_priv = dev->dev_private; |
7536 | 7550 | ||
7537 | hsw_package_c8_gpu_busy(dev_priv); |
7551 | hsw_package_c8_gpu_busy(dev_priv); |
7538 | i915_update_gfx_val(dev_priv); |
7552 | i915_update_gfx_val(dev_priv); |
7539 | } |
7553 | } |
7540 | 7554 | ||
7541 | void intel_mark_idle(struct drm_device *dev) |
7555 | void intel_mark_idle(struct drm_device *dev) |
7542 | { |
7556 | { |
7543 | struct drm_i915_private *dev_priv = dev->dev_private; |
7557 | struct drm_i915_private *dev_priv = dev->dev_private; |
7544 | struct drm_crtc *crtc; |
7558 | struct drm_crtc *crtc; |
7545 | 7559 | ||
7546 | hsw_package_c8_gpu_idle(dev_priv); |
7560 | hsw_package_c8_gpu_idle(dev_priv); |
7547 | 7561 | ||
7548 | if (!i915_powersave) |
7562 | if (!i915_powersave) |
7549 | return; |
7563 | return; |
7550 | 7564 | ||
7551 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7565 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7552 | if (!crtc->fb) |
7566 | if (!crtc->fb) |
7553 | continue; |
7567 | continue; |
7554 | 7568 | ||
7555 | intel_decrease_pllclock(crtc); |
7569 | intel_decrease_pllclock(crtc); |
7556 | } |
7570 | } |
7557 | } |
7571 | } |
7558 | 7572 | ||
7559 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7573 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7560 | struct intel_ring_buffer *ring) |
7574 | struct intel_ring_buffer *ring) |
7561 | { |
7575 | { |
7562 | struct drm_device *dev = obj->base.dev; |
7576 | struct drm_device *dev = obj->base.dev; |
7563 | struct drm_crtc *crtc; |
7577 | struct drm_crtc *crtc; |
7564 | 7578 | ||
7565 | if (!i915_powersave) |
7579 | if (!i915_powersave) |
7566 | return; |
7580 | return; |
7567 | 7581 | ||
7568 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7582 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7569 | if (!crtc->fb) |
7583 | if (!crtc->fb) |
7570 | continue; |
7584 | continue; |
7571 | 7585 | ||
7572 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7586 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7573 | continue; |
7587 | continue; |
7574 | 7588 | ||
7575 | intel_increase_pllclock(crtc); |
7589 | intel_increase_pllclock(crtc); |
7576 | if (ring && intel_fbc_enabled(dev)) |
7590 | if (ring && intel_fbc_enabled(dev)) |
7577 | ring->fbc_dirty = true; |
7591 | ring->fbc_dirty = true; |
7578 | } |
7592 | } |
7579 | } |
7593 | } |
7580 | 7594 | ||
7581 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7595 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7582 | { |
7596 | { |
7583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7584 | struct drm_device *dev = crtc->dev; |
7598 | struct drm_device *dev = crtc->dev; |
7585 | struct intel_unpin_work *work; |
7599 | struct intel_unpin_work *work; |
7586 | unsigned long flags; |
7600 | unsigned long flags; |
7587 | 7601 | ||
7588 | spin_lock_irqsave(&dev->event_lock, flags); |
7602 | spin_lock_irqsave(&dev->event_lock, flags); |
7589 | work = intel_crtc->unpin_work; |
7603 | work = intel_crtc->unpin_work; |
7590 | intel_crtc->unpin_work = NULL; |
7604 | intel_crtc->unpin_work = NULL; |
7591 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7605 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7592 | 7606 | ||
7593 | if (work) { |
7607 | if (work) { |
7594 | cancel_work_sync(&work->work); |
7608 | cancel_work_sync(&work->work); |
7595 | kfree(work); |
7609 | kfree(work); |
7596 | } |
7610 | } |
7597 | 7611 | ||
7598 | drm_crtc_cleanup(crtc); |
7612 | drm_crtc_cleanup(crtc); |
7599 | 7613 | ||
7600 | kfree(intel_crtc); |
7614 | kfree(intel_crtc); |
7601 | } |
7615 | } |
7602 | 7616 | ||
7603 | #if 0 |
7617 | #if 0 |
7604 | static void intel_unpin_work_fn(struct work_struct *__work) |
7618 | static void intel_unpin_work_fn(struct work_struct *__work) |
7605 | { |
7619 | { |
7606 | struct intel_unpin_work *work = |
7620 | struct intel_unpin_work *work = |
7607 | container_of(__work, struct intel_unpin_work, work); |
7621 | container_of(__work, struct intel_unpin_work, work); |
7608 | struct drm_device *dev = work->crtc->dev; |
7622 | struct drm_device *dev = work->crtc->dev; |
7609 | 7623 | ||
7610 | mutex_lock(&dev->struct_mutex); |
7624 | mutex_lock(&dev->struct_mutex); |
7611 | intel_unpin_fb_obj(work->old_fb_obj); |
7625 | intel_unpin_fb_obj(work->old_fb_obj); |
7612 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7626 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7613 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7627 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7614 | 7628 | ||
7615 | intel_update_fbc(dev); |
7629 | intel_update_fbc(dev); |
7616 | mutex_unlock(&dev->struct_mutex); |
7630 | mutex_unlock(&dev->struct_mutex); |
7617 | 7631 | ||
7618 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
7632 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
7619 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
7633 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
7620 | 7634 | ||
7621 | kfree(work); |
7635 | kfree(work); |
7622 | } |
7636 | } |
7623 | 7637 | ||
7624 | static void do_intel_finish_page_flip(struct drm_device *dev, |
7638 | static void do_intel_finish_page_flip(struct drm_device *dev, |
7625 | struct drm_crtc *crtc) |
7639 | struct drm_crtc *crtc) |
7626 | { |
7640 | { |
7627 | drm_i915_private_t *dev_priv = dev->dev_private; |
7641 | drm_i915_private_t *dev_priv = dev->dev_private; |
7628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7629 | struct intel_unpin_work *work; |
7643 | struct intel_unpin_work *work; |
7630 | unsigned long flags; |
7644 | unsigned long flags; |
7631 | 7645 | ||
7632 | /* Ignore early vblank irqs */ |
7646 | /* Ignore early vblank irqs */ |
7633 | if (intel_crtc == NULL) |
7647 | if (intel_crtc == NULL) |
7634 | return; |
7648 | return; |
7635 | 7649 | ||
7636 | spin_lock_irqsave(&dev->event_lock, flags); |
7650 | spin_lock_irqsave(&dev->event_lock, flags); |
7637 | work = intel_crtc->unpin_work; |
7651 | work = intel_crtc->unpin_work; |
7638 | 7652 | ||
7639 | /* Ensure we don't miss a work->pending update ... */ |
7653 | /* Ensure we don't miss a work->pending update ... */ |
7640 | smp_rmb(); |
7654 | smp_rmb(); |
7641 | 7655 | ||
7642 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
7656 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
7643 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7657 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7644 | return; |
7658 | return; |
7645 | } |
7659 | } |
7646 | 7660 | ||
7647 | /* and that the unpin work is consistent wrt ->pending. */ |
7661 | /* and that the unpin work is consistent wrt ->pending. */ |
7648 | smp_rmb(); |
7662 | smp_rmb(); |
7649 | 7663 | ||
7650 | intel_crtc->unpin_work = NULL; |
7664 | intel_crtc->unpin_work = NULL; |
7651 | 7665 | ||
7652 | if (work->event) |
7666 | if (work->event) |
7653 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
7667 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
7654 | 7668 | ||
7655 | drm_vblank_put(dev, intel_crtc->pipe); |
7669 | drm_vblank_put(dev, intel_crtc->pipe); |
7656 | 7670 | ||
7657 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7671 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7658 | 7672 | ||
7659 | wake_up_all(&dev_priv->pending_flip_queue); |
7673 | wake_up_all(&dev_priv->pending_flip_queue); |
7660 | 7674 | ||
7661 | queue_work(dev_priv->wq, &work->work); |
7675 | queue_work(dev_priv->wq, &work->work); |
7662 | 7676 | ||
7663 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
7677 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
7664 | } |
7678 | } |
7665 | 7679 | ||
7666 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7680 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7667 | { |
7681 | { |
7668 | drm_i915_private_t *dev_priv = dev->dev_private; |
7682 | drm_i915_private_t *dev_priv = dev->dev_private; |
7669 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
7683 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
7670 | 7684 | ||
7671 | do_intel_finish_page_flip(dev, crtc); |
7685 | do_intel_finish_page_flip(dev, crtc); |
7672 | } |
7686 | } |
7673 | 7687 | ||
7674 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
7688 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
7675 | { |
7689 | { |
7676 | drm_i915_private_t *dev_priv = dev->dev_private; |
7690 | drm_i915_private_t *dev_priv = dev->dev_private; |
7677 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
7691 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
7678 | 7692 | ||
7679 | do_intel_finish_page_flip(dev, crtc); |
7693 | do_intel_finish_page_flip(dev, crtc); |
7680 | } |
7694 | } |
7681 | 7695 | ||
7682 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7696 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7683 | { |
7697 | { |
7684 | drm_i915_private_t *dev_priv = dev->dev_private; |
7698 | drm_i915_private_t *dev_priv = dev->dev_private; |
7685 | struct intel_crtc *intel_crtc = |
7699 | struct intel_crtc *intel_crtc = |
7686 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
7700 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
7687 | unsigned long flags; |
7701 | unsigned long flags; |
7688 | 7702 | ||
7689 | /* NB: An MMIO update of the plane base pointer will also |
7703 | /* NB: An MMIO update of the plane base pointer will also |
7690 | * generate a page-flip completion irq, i.e. every modeset |
7704 | * generate a page-flip completion irq, i.e. every modeset |
7691 | * is also accompanied by a spurious intel_prepare_page_flip(). |
7705 | * is also accompanied by a spurious intel_prepare_page_flip(). |
7692 | */ |
7706 | */ |
7693 | spin_lock_irqsave(&dev->event_lock, flags); |
7707 | spin_lock_irqsave(&dev->event_lock, flags); |
7694 | if (intel_crtc->unpin_work) |
7708 | if (intel_crtc->unpin_work) |
7695 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
7709 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
7696 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7710 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7697 | } |
7711 | } |
7698 | 7712 | ||
7699 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7713 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7700 | { |
7714 | { |
7701 | /* Ensure that the work item is consistent when activating it ... */ |
7715 | /* Ensure that the work item is consistent when activating it ... */ |
7702 | smp_wmb(); |
7716 | smp_wmb(); |
7703 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
7717 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
7704 | /* and that it is marked active as soon as the irq could fire. */ |
7718 | /* and that it is marked active as soon as the irq could fire. */ |
7705 | smp_wmb(); |
7719 | smp_wmb(); |
7706 | } |
7720 | } |
7707 | 7721 | ||
7708 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7722 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7709 | struct drm_crtc *crtc, |
7723 | struct drm_crtc *crtc, |
7710 | struct drm_framebuffer *fb, |
7724 | struct drm_framebuffer *fb, |
7711 | struct drm_i915_gem_object *obj, |
7725 | struct drm_i915_gem_object *obj, |
7712 | uint32_t flags) |
7726 | uint32_t flags) |
7713 | { |
7727 | { |
7714 | struct drm_i915_private *dev_priv = dev->dev_private; |
7728 | struct drm_i915_private *dev_priv = dev->dev_private; |
7715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7716 | u32 flip_mask; |
7730 | u32 flip_mask; |
7717 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7731 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7718 | int ret; |
7732 | int ret; |
7719 | 7733 | ||
7720 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7734 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7721 | if (ret) |
7735 | if (ret) |
7722 | goto err; |
7736 | goto err; |
7723 | 7737 | ||
7724 | ret = intel_ring_begin(ring, 6); |
7738 | ret = intel_ring_begin(ring, 6); |
7725 | if (ret) |
7739 | if (ret) |
7726 | goto err_unpin; |
7740 | goto err_unpin; |
7727 | 7741 | ||
7728 | /* Can't queue multiple flips, so wait for the previous |
7742 | /* Can't queue multiple flips, so wait for the previous |
7729 | * one to finish before executing the next. |
7743 | * one to finish before executing the next. |
7730 | */ |
7744 | */ |
7731 | if (intel_crtc->plane) |
7745 | if (intel_crtc->plane) |
7732 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7746 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7733 | else |
7747 | else |
7734 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7748 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7735 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7749 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7736 | intel_ring_emit(ring, MI_NOOP); |
7750 | intel_ring_emit(ring, MI_NOOP); |
7737 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7751 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7738 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7752 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7739 | intel_ring_emit(ring, fb->pitches[0]); |
7753 | intel_ring_emit(ring, fb->pitches[0]); |
7740 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7754 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7741 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
7755 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
7742 | 7756 | ||
7743 | intel_mark_page_flip_active(intel_crtc); |
7757 | intel_mark_page_flip_active(intel_crtc); |
7744 | intel_ring_advance(ring); |
7758 | intel_ring_advance(ring); |
7745 | return 0; |
7759 | return 0; |
7746 | 7760 | ||
7747 | err_unpin: |
7761 | err_unpin: |
7748 | intel_unpin_fb_obj(obj); |
7762 | intel_unpin_fb_obj(obj); |
7749 | err: |
7763 | err: |
7750 | return ret; |
7764 | return ret; |
7751 | } |
7765 | } |
7752 | 7766 | ||
7753 | static int intel_gen3_queue_flip(struct drm_device *dev, |
7767 | static int intel_gen3_queue_flip(struct drm_device *dev, |
7754 | struct drm_crtc *crtc, |
7768 | struct drm_crtc *crtc, |
7755 | struct drm_framebuffer *fb, |
7769 | struct drm_framebuffer *fb, |
7756 | struct drm_i915_gem_object *obj, |
7770 | struct drm_i915_gem_object *obj, |
7757 | uint32_t flags) |
7771 | uint32_t flags) |
7758 | { |
7772 | { |
7759 | struct drm_i915_private *dev_priv = dev->dev_private; |
7773 | struct drm_i915_private *dev_priv = dev->dev_private; |
7760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7761 | u32 flip_mask; |
7775 | u32 flip_mask; |
7762 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7776 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7763 | int ret; |
7777 | int ret; |
7764 | 7778 | ||
7765 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7779 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7766 | if (ret) |
7780 | if (ret) |
7767 | goto err; |
7781 | goto err; |
7768 | 7782 | ||
7769 | ret = intel_ring_begin(ring, 6); |
7783 | ret = intel_ring_begin(ring, 6); |
7770 | if (ret) |
7784 | if (ret) |
7771 | goto err_unpin; |
7785 | goto err_unpin; |
7772 | 7786 | ||
7773 | if (intel_crtc->plane) |
7787 | if (intel_crtc->plane) |
7774 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7788 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7775 | else |
7789 | else |
7776 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7790 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7777 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7791 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7778 | intel_ring_emit(ring, MI_NOOP); |
7792 | intel_ring_emit(ring, MI_NOOP); |
7779 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
7793 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
7780 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7794 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7781 | intel_ring_emit(ring, fb->pitches[0]); |
7795 | intel_ring_emit(ring, fb->pitches[0]); |
7782 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7796 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7783 | intel_ring_emit(ring, MI_NOOP); |
7797 | intel_ring_emit(ring, MI_NOOP); |
7784 | 7798 | ||
7785 | intel_mark_page_flip_active(intel_crtc); |
7799 | intel_mark_page_flip_active(intel_crtc); |
7786 | intel_ring_advance(ring); |
7800 | intel_ring_advance(ring); |
7787 | return 0; |
7801 | return 0; |
7788 | 7802 | ||
7789 | err_unpin: |
7803 | err_unpin: |
7790 | intel_unpin_fb_obj(obj); |
7804 | intel_unpin_fb_obj(obj); |
7791 | err: |
7805 | err: |
7792 | return ret; |
7806 | return ret; |
7793 | } |
7807 | } |
7794 | 7808 | ||
7795 | static int intel_gen4_queue_flip(struct drm_device *dev, |
7809 | static int intel_gen4_queue_flip(struct drm_device *dev, |
7796 | struct drm_crtc *crtc, |
7810 | struct drm_crtc *crtc, |
7797 | struct drm_framebuffer *fb, |
7811 | struct drm_framebuffer *fb, |
7798 | struct drm_i915_gem_object *obj, |
7812 | struct drm_i915_gem_object *obj, |
7799 | uint32_t flags) |
7813 | uint32_t flags) |
7800 | { |
7814 | { |
7801 | struct drm_i915_private *dev_priv = dev->dev_private; |
7815 | struct drm_i915_private *dev_priv = dev->dev_private; |
7802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7803 | uint32_t pf, pipesrc; |
7817 | uint32_t pf, pipesrc; |
7804 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7818 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7805 | int ret; |
7819 | int ret; |
7806 | 7820 | ||
7807 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7821 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7808 | if (ret) |
7822 | if (ret) |
7809 | goto err; |
7823 | goto err; |
7810 | 7824 | ||
7811 | ret = intel_ring_begin(ring, 4); |
7825 | ret = intel_ring_begin(ring, 4); |
7812 | if (ret) |
7826 | if (ret) |
7813 | goto err_unpin; |
7827 | goto err_unpin; |
7814 | 7828 | ||
7815 | /* i965+ uses the linear or tiled offsets from the |
7829 | /* i965+ uses the linear or tiled offsets from the |
7816 | * Display Registers (which do not change across a page-flip) |
7830 | * Display Registers (which do not change across a page-flip) |
7817 | * so we need only reprogram the base address. |
7831 | * so we need only reprogram the base address. |
7818 | */ |
7832 | */ |
7819 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7833 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7820 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7834 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7821 | intel_ring_emit(ring, fb->pitches[0]); |
7835 | intel_ring_emit(ring, fb->pitches[0]); |
7822 | intel_ring_emit(ring, |
7836 | intel_ring_emit(ring, |
7823 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
7837 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
7824 | obj->tiling_mode); |
7838 | obj->tiling_mode); |
7825 | 7839 | ||
7826 | /* XXX Enabling the panel-fitter across page-flip is so far |
7840 | /* XXX Enabling the panel-fitter across page-flip is so far |
7827 | * untested on non-native modes, so ignore it for now. |
7841 | * untested on non-native modes, so ignore it for now. |
7828 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
7842 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
7829 | */ |
7843 | */ |
7830 | pf = 0; |
7844 | pf = 0; |
7831 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7845 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7832 | intel_ring_emit(ring, pf | pipesrc); |
7846 | intel_ring_emit(ring, pf | pipesrc); |
7833 | 7847 | ||
7834 | intel_mark_page_flip_active(intel_crtc); |
7848 | intel_mark_page_flip_active(intel_crtc); |
7835 | intel_ring_advance(ring); |
7849 | intel_ring_advance(ring); |
7836 | return 0; |
7850 | return 0; |
7837 | 7851 | ||
7838 | err_unpin: |
7852 | err_unpin: |
7839 | intel_unpin_fb_obj(obj); |
7853 | intel_unpin_fb_obj(obj); |
7840 | err: |
7854 | err: |
7841 | return ret; |
7855 | return ret; |
7842 | } |
7856 | } |
7843 | 7857 | ||
7844 | static int intel_gen6_queue_flip(struct drm_device *dev, |
7858 | static int intel_gen6_queue_flip(struct drm_device *dev, |
7845 | struct drm_crtc *crtc, |
7859 | struct drm_crtc *crtc, |
7846 | struct drm_framebuffer *fb, |
7860 | struct drm_framebuffer *fb, |
7847 | struct drm_i915_gem_object *obj, |
7861 | struct drm_i915_gem_object *obj, |
7848 | uint32_t flags) |
7862 | uint32_t flags) |
7849 | { |
7863 | { |
7850 | struct drm_i915_private *dev_priv = dev->dev_private; |
7864 | struct drm_i915_private *dev_priv = dev->dev_private; |
7851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7852 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7866 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7853 | uint32_t pf, pipesrc; |
7867 | uint32_t pf, pipesrc; |
7854 | int ret; |
7868 | int ret; |
7855 | 7869 | ||
7856 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7870 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7857 | if (ret) |
7871 | if (ret) |
7858 | goto err; |
7872 | goto err; |
7859 | 7873 | ||
7860 | ret = intel_ring_begin(ring, 4); |
7874 | ret = intel_ring_begin(ring, 4); |
7861 | if (ret) |
7875 | if (ret) |
7862 | goto err_unpin; |
7876 | goto err_unpin; |
7863 | 7877 | ||
7864 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7878 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7865 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7879 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7866 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
7880 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
7867 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7881 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7868 | 7882 | ||
7869 | /* Contrary to the suggestions in the documentation, |
7883 | /* Contrary to the suggestions in the documentation, |
7870 | * "Enable Panel Fitter" does not seem to be required when page |
7884 | * "Enable Panel Fitter" does not seem to be required when page |
7871 | * flipping with a non-native mode, and worse causes a normal |
7885 | * flipping with a non-native mode, and worse causes a normal |
7872 | * modeset to fail. |
7886 | * modeset to fail. |
7873 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
7887 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
7874 | */ |
7888 | */ |
7875 | pf = 0; |
7889 | pf = 0; |
7876 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7890 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7877 | intel_ring_emit(ring, pf | pipesrc); |
7891 | intel_ring_emit(ring, pf | pipesrc); |
7878 | 7892 | ||
7879 | intel_mark_page_flip_active(intel_crtc); |
7893 | intel_mark_page_flip_active(intel_crtc); |
7880 | intel_ring_advance(ring); |
7894 | intel_ring_advance(ring); |
7881 | return 0; |
7895 | return 0; |
7882 | 7896 | ||
7883 | err_unpin: |
7897 | err_unpin: |
7884 | intel_unpin_fb_obj(obj); |
7898 | intel_unpin_fb_obj(obj); |
7885 | err: |
7899 | err: |
7886 | return ret; |
7900 | return ret; |
7887 | } |
7901 | } |
7888 | 7902 | ||
7889 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7903 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7890 | struct drm_crtc *crtc, |
7904 | struct drm_crtc *crtc, |
7891 | struct drm_framebuffer *fb, |
7905 | struct drm_framebuffer *fb, |
7892 | struct drm_i915_gem_object *obj, |
7906 | struct drm_i915_gem_object *obj, |
7893 | uint32_t flags) |
7907 | uint32_t flags) |
7894 | { |
7908 | { |
7895 | struct drm_i915_private *dev_priv = dev->dev_private; |
7909 | struct drm_i915_private *dev_priv = dev->dev_private; |
7896 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7897 | struct intel_ring_buffer *ring; |
7911 | struct intel_ring_buffer *ring; |
7898 | uint32_t plane_bit = 0; |
7912 | uint32_t plane_bit = 0; |
7899 | int len, ret; |
7913 | int len, ret; |
7900 | 7914 | ||
7901 | ring = obj->ring; |
7915 | ring = obj->ring; |
7902 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
7916 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
7903 | ring = &dev_priv->ring[BCS]; |
7917 | ring = &dev_priv->ring[BCS]; |
7904 | 7918 | ||
7905 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7919 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7906 | if (ret) |
7920 | if (ret) |
7907 | goto err; |
7921 | goto err; |
7908 | 7922 | ||
7909 | switch(intel_crtc->plane) { |
7923 | switch(intel_crtc->plane) { |
7910 | case PLANE_A: |
7924 | case PLANE_A: |
7911 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
7925 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
7912 | break; |
7926 | break; |
7913 | case PLANE_B: |
7927 | case PLANE_B: |
7914 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
7928 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
7915 | break; |
7929 | break; |
7916 | case PLANE_C: |
7930 | case PLANE_C: |
7917 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
7931 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
7918 | break; |
7932 | break; |
7919 | default: |
7933 | default: |
7920 | WARN_ONCE(1, "unknown plane in flip command\n"); |
7934 | WARN_ONCE(1, "unknown plane in flip command\n"); |
7921 | ret = -ENODEV; |
7935 | ret = -ENODEV; |
7922 | goto err_unpin; |
7936 | goto err_unpin; |
7923 | } |
7937 | } |
7924 | 7938 | ||
7925 | len = 4; |
7939 | len = 4; |
7926 | if (ring->id == RCS) |
7940 | if (ring->id == RCS) |
7927 | len += 6; |
7941 | len += 6; |
7928 | 7942 | ||
7929 | ret = intel_ring_begin(ring, len); |
7943 | ret = intel_ring_begin(ring, len); |
7930 | if (ret) |
7944 | if (ret) |
7931 | goto err_unpin; |
7945 | goto err_unpin; |
7932 | 7946 | ||
7933 | /* Unmask the flip-done completion message. Note that the bspec says that |
7947 | /* Unmask the flip-done completion message. Note that the bspec says that |
7934 | * we should do this for both the BCS and RCS, and that we must not unmask |
7948 | * we should do this for both the BCS and RCS, and that we must not unmask |
7935 | * more than one flip event at any time (or ensure that one flip message |
7949 | * more than one flip event at any time (or ensure that one flip message |
7936 | * can be sent by waiting for flip-done prior to queueing new flips). |
7950 | * can be sent by waiting for flip-done prior to queueing new flips). |
7937 | * Experimentation says that BCS works despite DERRMR masking all |
7951 | * Experimentation says that BCS works despite DERRMR masking all |
7938 | * flip-done completion events and that unmasking all planes at once |
7952 | * flip-done completion events and that unmasking all planes at once |
7939 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
7953 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
7940 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
7954 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
7941 | */ |
7955 | */ |
7942 | if (ring->id == RCS) { |
7956 | if (ring->id == RCS) { |
7943 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
7957 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
7944 | intel_ring_emit(ring, DERRMR); |
7958 | intel_ring_emit(ring, DERRMR); |
7945 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
7959 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
7946 | DERRMR_PIPEB_PRI_FLIP_DONE | |
7960 | DERRMR_PIPEB_PRI_FLIP_DONE | |
7947 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
7961 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
7948 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
7962 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
7949 | intel_ring_emit(ring, DERRMR); |
7963 | intel_ring_emit(ring, DERRMR); |
7950 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
7964 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
7951 | } |
7965 | } |
7952 | 7966 | ||
7953 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7967 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7954 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7968 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7955 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7969 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7956 | intel_ring_emit(ring, (MI_NOOP)); |
7970 | intel_ring_emit(ring, (MI_NOOP)); |
7957 | 7971 | ||
7958 | intel_mark_page_flip_active(intel_crtc); |
7972 | intel_mark_page_flip_active(intel_crtc); |
7959 | intel_ring_advance(ring); |
7973 | intel_ring_advance(ring); |
7960 | return 0; |
7974 | return 0; |
7961 | 7975 | ||
7962 | err_unpin: |
7976 | err_unpin: |
7963 | intel_unpin_fb_obj(obj); |
7977 | intel_unpin_fb_obj(obj); |
7964 | err: |
7978 | err: |
7965 | return ret; |
7979 | return ret; |
7966 | } |
7980 | } |
7967 | 7981 | ||
7968 | static int intel_default_queue_flip(struct drm_device *dev, |
7982 | static int intel_default_queue_flip(struct drm_device *dev, |
7969 | struct drm_crtc *crtc, |
7983 | struct drm_crtc *crtc, |
7970 | struct drm_framebuffer *fb, |
7984 | struct drm_framebuffer *fb, |
7971 | struct drm_i915_gem_object *obj, |
7985 | struct drm_i915_gem_object *obj, |
7972 | uint32_t flags) |
7986 | uint32_t flags) |
7973 | { |
7987 | { |
7974 | return -ENODEV; |
7988 | return -ENODEV; |
7975 | } |
7989 | } |
7976 | 7990 | ||
7977 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7991 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7978 | struct drm_framebuffer *fb, |
7992 | struct drm_framebuffer *fb, |
7979 | struct drm_pending_vblank_event *event, |
7993 | struct drm_pending_vblank_event *event, |
7980 | uint32_t page_flip_flags) |
7994 | uint32_t page_flip_flags) |
7981 | { |
7995 | { |
7982 | struct drm_device *dev = crtc->dev; |
7996 | struct drm_device *dev = crtc->dev; |
7983 | struct drm_i915_private *dev_priv = dev->dev_private; |
7997 | struct drm_i915_private *dev_priv = dev->dev_private; |
7984 | struct drm_framebuffer *old_fb = crtc->fb; |
7998 | struct drm_framebuffer *old_fb = crtc->fb; |
7985 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
7999 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
7986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8000 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7987 | struct intel_unpin_work *work; |
8001 | struct intel_unpin_work *work; |
7988 | unsigned long flags; |
8002 | unsigned long flags; |
7989 | int ret; |
8003 | int ret; |
7990 | 8004 | ||
7991 | /* Can't change pixel format via MI display flips. */ |
8005 | /* Can't change pixel format via MI display flips. */ |
7992 | if (fb->pixel_format != crtc->fb->pixel_format) |
8006 | if (fb->pixel_format != crtc->fb->pixel_format) |
7993 | return -EINVAL; |
8007 | return -EINVAL; |
7994 | 8008 | ||
7995 | /* |
8009 | /* |
7996 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
8010 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
7997 | * Note that pitch changes could also affect these register. |
8011 | * Note that pitch changes could also affect these register. |
7998 | */ |
8012 | */ |
7999 | if (INTEL_INFO(dev)->gen > 3 && |
8013 | if (INTEL_INFO(dev)->gen > 3 && |
8000 | (fb->offsets[0] != crtc->fb->offsets[0] || |
8014 | (fb->offsets[0] != crtc->fb->offsets[0] || |
8001 | fb->pitches[0] != crtc->fb->pitches[0])) |
8015 | fb->pitches[0] != crtc->fb->pitches[0])) |
8002 | return -EINVAL; |
8016 | return -EINVAL; |
8003 | 8017 | ||
8004 | work = kzalloc(sizeof *work, GFP_KERNEL); |
8018 | work = kzalloc(sizeof *work, GFP_KERNEL); |
8005 | if (work == NULL) |
8019 | if (work == NULL) |
8006 | return -ENOMEM; |
8020 | return -ENOMEM; |
8007 | 8021 | ||
8008 | work->event = event; |
8022 | work->event = event; |
8009 | work->crtc = crtc; |
8023 | work->crtc = crtc; |
8010 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
8024 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
8011 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8025 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8012 | 8026 | ||
8013 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8027 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8014 | if (ret) |
8028 | if (ret) |
8015 | goto free_work; |
8029 | goto free_work; |
8016 | 8030 | ||
8017 | /* We borrow the event spin lock for protecting unpin_work */ |
8031 | /* We borrow the event spin lock for protecting unpin_work */ |
8018 | spin_lock_irqsave(&dev->event_lock, flags); |
8032 | spin_lock_irqsave(&dev->event_lock, flags); |
8019 | if (intel_crtc->unpin_work) { |
8033 | if (intel_crtc->unpin_work) { |
8020 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8034 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8021 | kfree(work); |
8035 | kfree(work); |
8022 | drm_vblank_put(dev, intel_crtc->pipe); |
8036 | drm_vblank_put(dev, intel_crtc->pipe); |
8023 | 8037 | ||
8024 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
8038 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
8025 | return -EBUSY; |
8039 | return -EBUSY; |
8026 | } |
8040 | } |
8027 | intel_crtc->unpin_work = work; |
8041 | intel_crtc->unpin_work = work; |
8028 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8042 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8029 | 8043 | ||
8030 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8044 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8031 | flush_workqueue(dev_priv->wq); |
8045 | flush_workqueue(dev_priv->wq); |
8032 | 8046 | ||
8033 | ret = i915_mutex_lock_interruptible(dev); |
8047 | ret = i915_mutex_lock_interruptible(dev); |
8034 | if (ret) |
8048 | if (ret) |
8035 | goto cleanup; |
8049 | goto cleanup; |
8036 | 8050 | ||
8037 | /* Reference the objects for the scheduled work. */ |
8051 | /* Reference the objects for the scheduled work. */ |
8038 | drm_gem_object_reference(&work->old_fb_obj->base); |
8052 | drm_gem_object_reference(&work->old_fb_obj->base); |
8039 | drm_gem_object_reference(&obj->base); |
8053 | drm_gem_object_reference(&obj->base); |
8040 | 8054 | ||
8041 | crtc->fb = fb; |
8055 | crtc->fb = fb; |
8042 | 8056 | ||
8043 | work->pending_flip_obj = obj; |
8057 | work->pending_flip_obj = obj; |
8044 | 8058 | ||
8045 | work->enable_stall_check = true; |
8059 | work->enable_stall_check = true; |
8046 | 8060 | ||
8047 | atomic_inc(&intel_crtc->unpin_work_count); |
8061 | atomic_inc(&intel_crtc->unpin_work_count); |
8048 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
8062 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
8049 | 8063 | ||
8050 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8064 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8051 | if (ret) |
8065 | if (ret) |
8052 | goto cleanup_pending; |
8066 | goto cleanup_pending; |
8053 | 8067 | ||
8054 | intel_disable_fbc(dev); |
8068 | intel_disable_fbc(dev); |
8055 | intel_mark_fb_busy(obj, NULL); |
8069 | intel_mark_fb_busy(obj, NULL); |
8056 | mutex_unlock(&dev->struct_mutex); |
8070 | mutex_unlock(&dev->struct_mutex); |
8057 | 8071 | ||
8058 | trace_i915_flip_request(intel_crtc->plane, obj); |
8072 | trace_i915_flip_request(intel_crtc->plane, obj); |
8059 | 8073 | ||
8060 | return 0; |
8074 | return 0; |
8061 | 8075 | ||
8062 | cleanup_pending: |
8076 | cleanup_pending: |
8063 | atomic_dec(&intel_crtc->unpin_work_count); |
8077 | atomic_dec(&intel_crtc->unpin_work_count); |
8064 | crtc->fb = old_fb; |
8078 | crtc->fb = old_fb; |
8065 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8079 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8066 | drm_gem_object_unreference(&obj->base); |
8080 | drm_gem_object_unreference(&obj->base); |
8067 | mutex_unlock(&dev->struct_mutex); |
8081 | mutex_unlock(&dev->struct_mutex); |
8068 | 8082 | ||
8069 | cleanup: |
8083 | cleanup: |
8070 | spin_lock_irqsave(&dev->event_lock, flags); |
8084 | spin_lock_irqsave(&dev->event_lock, flags); |
8071 | intel_crtc->unpin_work = NULL; |
8085 | intel_crtc->unpin_work = NULL; |
8072 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8086 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8073 | 8087 | ||
8074 | drm_vblank_put(dev, intel_crtc->pipe); |
8088 | drm_vblank_put(dev, intel_crtc->pipe); |
8075 | free_work: |
8089 | free_work: |
8076 | kfree(work); |
8090 | kfree(work); |
8077 | 8091 | ||
8078 | return ret; |
8092 | return ret; |
8079 | } |
8093 | } |
8080 | #endif |
8094 | #endif |
8081 | 8095 | ||
8082 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8096 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8083 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8097 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8084 | .load_lut = intel_crtc_load_lut, |
8098 | .load_lut = intel_crtc_load_lut, |
8085 | }; |
8099 | }; |
8086 | 8100 | ||
8087 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8101 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8088 | struct drm_crtc *crtc) |
8102 | struct drm_crtc *crtc) |
8089 | { |
8103 | { |
8090 | struct drm_device *dev; |
8104 | struct drm_device *dev; |
8091 | struct drm_crtc *tmp; |
8105 | struct drm_crtc *tmp; |
8092 | int crtc_mask = 1; |
8106 | int crtc_mask = 1; |
8093 | 8107 | ||
8094 | WARN(!crtc, "checking null crtc?\n"); |
8108 | WARN(!crtc, "checking null crtc?\n"); |
8095 | 8109 | ||
8096 | dev = crtc->dev; |
8110 | dev = crtc->dev; |
8097 | 8111 | ||
8098 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8112 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8099 | if (tmp == crtc) |
8113 | if (tmp == crtc) |
8100 | break; |
8114 | break; |
8101 | crtc_mask <<= 1; |
8115 | crtc_mask <<= 1; |
8102 | } |
8116 | } |
8103 | 8117 | ||
8104 | if (encoder->possible_crtcs & crtc_mask) |
8118 | if (encoder->possible_crtcs & crtc_mask) |
8105 | return true; |
8119 | return true; |
8106 | return false; |
8120 | return false; |
8107 | } |
8121 | } |
8108 | 8122 | ||
8109 | /** |
8123 | /** |
8110 | * intel_modeset_update_staged_output_state |
8124 | * intel_modeset_update_staged_output_state |
8111 | * |
8125 | * |
8112 | * Updates the staged output configuration state, e.g. after we've read out the |
8126 | * Updates the staged output configuration state, e.g. after we've read out the |
8113 | * current hw state. |
8127 | * current hw state. |
8114 | */ |
8128 | */ |
8115 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8129 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8116 | { |
8130 | { |
8117 | struct intel_encoder *encoder; |
8131 | struct intel_encoder *encoder; |
8118 | struct intel_connector *connector; |
8132 | struct intel_connector *connector; |
8119 | 8133 | ||
8120 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8134 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8121 | base.head) { |
8135 | base.head) { |
8122 | connector->new_encoder = |
8136 | connector->new_encoder = |
8123 | to_intel_encoder(connector->base.encoder); |
8137 | to_intel_encoder(connector->base.encoder); |
8124 | } |
8138 | } |
8125 | 8139 | ||
8126 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8140 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8127 | base.head) { |
8141 | base.head) { |
8128 | encoder->new_crtc = |
8142 | encoder->new_crtc = |
8129 | to_intel_crtc(encoder->base.crtc); |
8143 | to_intel_crtc(encoder->base.crtc); |
8130 | } |
8144 | } |
8131 | } |
8145 | } |
8132 | 8146 | ||
8133 | /** |
8147 | /** |
8134 | * intel_modeset_commit_output_state |
8148 | * intel_modeset_commit_output_state |
8135 | * |
8149 | * |
8136 | * This function copies the stage display pipe configuration to the real one. |
8150 | * This function copies the stage display pipe configuration to the real one. |
8137 | */ |
8151 | */ |
8138 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
8152 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
8139 | { |
8153 | { |
8140 | struct intel_encoder *encoder; |
8154 | struct intel_encoder *encoder; |
8141 | struct intel_connector *connector; |
8155 | struct intel_connector *connector; |
8142 | 8156 | ||
8143 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8157 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8144 | base.head) { |
8158 | base.head) { |
8145 | connector->base.encoder = &connector->new_encoder->base; |
8159 | connector->base.encoder = &connector->new_encoder->base; |
8146 | } |
8160 | } |
8147 | 8161 | ||
8148 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8162 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8149 | base.head) { |
8163 | base.head) { |
8150 | encoder->base.crtc = &encoder->new_crtc->base; |
8164 | encoder->base.crtc = &encoder->new_crtc->base; |
8151 | } |
8165 | } |
8152 | } |
8166 | } |
8153 | 8167 | ||
8154 | static void |
8168 | static void |
8155 | connected_sink_compute_bpp(struct intel_connector * connector, |
8169 | connected_sink_compute_bpp(struct intel_connector * connector, |
8156 | struct intel_crtc_config *pipe_config) |
8170 | struct intel_crtc_config *pipe_config) |
8157 | { |
8171 | { |
8158 | int bpp = pipe_config->pipe_bpp; |
8172 | int bpp = pipe_config->pipe_bpp; |
8159 | 8173 | ||
8160 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8174 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8161 | connector->base.base.id, |
8175 | connector->base.base.id, |
8162 | drm_get_connector_name(&connector->base)); |
8176 | drm_get_connector_name(&connector->base)); |
8163 | 8177 | ||
8164 | /* Don't use an invalid EDID bpc value */ |
8178 | /* Don't use an invalid EDID bpc value */ |
8165 | if (connector->base.display_info.bpc && |
8179 | if (connector->base.display_info.bpc && |
8166 | connector->base.display_info.bpc * 3 < bpp) { |
8180 | connector->base.display_info.bpc * 3 < bpp) { |
8167 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
8181 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
8168 | bpp, connector->base.display_info.bpc*3); |
8182 | bpp, connector->base.display_info.bpc*3); |
8169 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
8183 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
8170 | } |
8184 | } |
8171 | 8185 | ||
8172 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
8186 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
8173 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
8187 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
8174 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
8188 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
8175 | bpp); |
8189 | bpp); |
8176 | pipe_config->pipe_bpp = 24; |
8190 | pipe_config->pipe_bpp = 24; |
8177 | } |
8191 | } |
8178 | } |
8192 | } |
8179 | 8193 | ||
8180 | static int |
8194 | static int |
8181 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8195 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8182 | struct drm_framebuffer *fb, |
8196 | struct drm_framebuffer *fb, |
8183 | struct intel_crtc_config *pipe_config) |
8197 | struct intel_crtc_config *pipe_config) |
8184 | { |
8198 | { |
8185 | struct drm_device *dev = crtc->base.dev; |
8199 | struct drm_device *dev = crtc->base.dev; |
8186 | struct intel_connector *connector; |
8200 | struct intel_connector *connector; |
8187 | int bpp; |
8201 | int bpp; |
8188 | 8202 | ||
8189 | switch (fb->pixel_format) { |
8203 | switch (fb->pixel_format) { |
8190 | case DRM_FORMAT_C8: |
8204 | case DRM_FORMAT_C8: |
8191 | bpp = 8*3; /* since we go through a colormap */ |
8205 | bpp = 8*3; /* since we go through a colormap */ |
8192 | break; |
8206 | break; |
8193 | case DRM_FORMAT_XRGB1555: |
8207 | case DRM_FORMAT_XRGB1555: |
8194 | case DRM_FORMAT_ARGB1555: |
8208 | case DRM_FORMAT_ARGB1555: |
8195 | /* checked in intel_framebuffer_init already */ |
8209 | /* checked in intel_framebuffer_init already */ |
8196 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
8210 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
8197 | return -EINVAL; |
8211 | return -EINVAL; |
8198 | case DRM_FORMAT_RGB565: |
8212 | case DRM_FORMAT_RGB565: |
8199 | bpp = 6*3; /* min is 18bpp */ |
8213 | bpp = 6*3; /* min is 18bpp */ |
8200 | break; |
8214 | break; |
8201 | case DRM_FORMAT_XBGR8888: |
8215 | case DRM_FORMAT_XBGR8888: |
8202 | case DRM_FORMAT_ABGR8888: |
8216 | case DRM_FORMAT_ABGR8888: |
8203 | /* checked in intel_framebuffer_init already */ |
8217 | /* checked in intel_framebuffer_init already */ |
8204 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8218 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8205 | return -EINVAL; |
8219 | return -EINVAL; |
8206 | case DRM_FORMAT_XRGB8888: |
8220 | case DRM_FORMAT_XRGB8888: |
8207 | case DRM_FORMAT_ARGB8888: |
8221 | case DRM_FORMAT_ARGB8888: |
8208 | bpp = 8*3; |
8222 | bpp = 8*3; |
8209 | break; |
8223 | break; |
8210 | case DRM_FORMAT_XRGB2101010: |
8224 | case DRM_FORMAT_XRGB2101010: |
8211 | case DRM_FORMAT_ARGB2101010: |
8225 | case DRM_FORMAT_ARGB2101010: |
8212 | case DRM_FORMAT_XBGR2101010: |
8226 | case DRM_FORMAT_XBGR2101010: |
8213 | case DRM_FORMAT_ABGR2101010: |
8227 | case DRM_FORMAT_ABGR2101010: |
8214 | /* checked in intel_framebuffer_init already */ |
8228 | /* checked in intel_framebuffer_init already */ |
8215 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8229 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8216 | return -EINVAL; |
8230 | return -EINVAL; |
8217 | bpp = 10*3; |
8231 | bpp = 10*3; |
8218 | break; |
8232 | break; |
8219 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
8233 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
8220 | default: |
8234 | default: |
8221 | DRM_DEBUG_KMS("unsupported depth\n"); |
8235 | DRM_DEBUG_KMS("unsupported depth\n"); |
8222 | return -EINVAL; |
8236 | return -EINVAL; |
8223 | } |
8237 | } |
8224 | 8238 | ||
8225 | pipe_config->pipe_bpp = bpp; |
8239 | pipe_config->pipe_bpp = bpp; |
8226 | 8240 | ||
8227 | /* Clamp display bpp to EDID value */ |
8241 | /* Clamp display bpp to EDID value */ |
8228 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8242 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8229 | base.head) { |
8243 | base.head) { |
8230 | if (!connector->new_encoder || |
8244 | if (!connector->new_encoder || |
8231 | connector->new_encoder->new_crtc != crtc) |
8245 | connector->new_encoder->new_crtc != crtc) |
8232 | continue; |
8246 | continue; |
8233 | 8247 | ||
8234 | connected_sink_compute_bpp(connector, pipe_config); |
8248 | connected_sink_compute_bpp(connector, pipe_config); |
8235 | } |
8249 | } |
8236 | 8250 | ||
8237 | return bpp; |
8251 | return bpp; |
8238 | } |
8252 | } |
8239 | 8253 | ||
8240 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8254 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8241 | struct intel_crtc_config *pipe_config, |
8255 | struct intel_crtc_config *pipe_config, |
8242 | const char *context) |
8256 | const char *context) |
8243 | { |
8257 | { |
8244 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
8258 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
8245 | context, pipe_name(crtc->pipe)); |
8259 | context, pipe_name(crtc->pipe)); |
8246 | 8260 | ||
8247 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
8261 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
8248 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
8262 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
8249 | pipe_config->pipe_bpp, pipe_config->dither); |
8263 | pipe_config->pipe_bpp, pipe_config->dither); |
8250 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8264 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8251 | pipe_config->has_pch_encoder, |
8265 | pipe_config->has_pch_encoder, |
8252 | pipe_config->fdi_lanes, |
8266 | pipe_config->fdi_lanes, |
8253 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8267 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8254 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8268 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8255 | pipe_config->fdi_m_n.tu); |
8269 | pipe_config->fdi_m_n.tu); |
8256 | DRM_DEBUG_KMS("requested mode:\n"); |
8270 | DRM_DEBUG_KMS("requested mode:\n"); |
8257 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8271 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8258 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8272 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8259 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8273 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8260 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8274 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8261 | pipe_config->gmch_pfit.control, |
8275 | pipe_config->gmch_pfit.control, |
8262 | pipe_config->gmch_pfit.pgm_ratios, |
8276 | pipe_config->gmch_pfit.pgm_ratios, |
8263 | pipe_config->gmch_pfit.lvds_border_bits); |
8277 | pipe_config->gmch_pfit.lvds_border_bits); |
8264 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8278 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8265 | pipe_config->pch_pfit.pos, |
8279 | pipe_config->pch_pfit.pos, |
8266 | pipe_config->pch_pfit.size, |
8280 | pipe_config->pch_pfit.size, |
8267 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8281 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8268 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8282 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8269 | } |
8283 | } |
8270 | 8284 | ||
8271 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8285 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8272 | { |
8286 | { |
8273 | int num_encoders = 0; |
8287 | int num_encoders = 0; |
8274 | bool uncloneable_encoders = false; |
8288 | bool uncloneable_encoders = false; |
8275 | struct intel_encoder *encoder; |
8289 | struct intel_encoder *encoder; |
8276 | 8290 | ||
8277 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
8291 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
8278 | base.head) { |
8292 | base.head) { |
8279 | if (&encoder->new_crtc->base != crtc) |
8293 | if (&encoder->new_crtc->base != crtc) |
8280 | continue; |
8294 | continue; |
8281 | 8295 | ||
8282 | num_encoders++; |
8296 | num_encoders++; |
8283 | if (!encoder->cloneable) |
8297 | if (!encoder->cloneable) |
8284 | uncloneable_encoders = true; |
8298 | uncloneable_encoders = true; |
8285 | } |
8299 | } |
8286 | 8300 | ||
8287 | return !(num_encoders > 1 && uncloneable_encoders); |
8301 | return !(num_encoders > 1 && uncloneable_encoders); |
8288 | } |
8302 | } |
8289 | 8303 | ||
8290 | static struct intel_crtc_config * |
8304 | static struct intel_crtc_config * |
8291 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
8305 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
8292 | struct drm_framebuffer *fb, |
8306 | struct drm_framebuffer *fb, |
8293 | struct drm_display_mode *mode) |
8307 | struct drm_display_mode *mode) |
8294 | { |
8308 | { |
8295 | struct drm_device *dev = crtc->dev; |
8309 | struct drm_device *dev = crtc->dev; |
8296 | struct intel_encoder *encoder; |
8310 | struct intel_encoder *encoder; |
8297 | struct intel_crtc_config *pipe_config; |
8311 | struct intel_crtc_config *pipe_config; |
8298 | int plane_bpp, ret = -EINVAL; |
8312 | int plane_bpp, ret = -EINVAL; |
8299 | bool retry = true; |
8313 | bool retry = true; |
8300 | 8314 | ||
8301 | if (!check_encoder_cloning(crtc)) { |
8315 | if (!check_encoder_cloning(crtc)) { |
8302 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8316 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8303 | return ERR_PTR(-EINVAL); |
8317 | return ERR_PTR(-EINVAL); |
8304 | } |
8318 | } |
8305 | 8319 | ||
8306 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8320 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8307 | if (!pipe_config) |
8321 | if (!pipe_config) |
8308 | return ERR_PTR(-ENOMEM); |
8322 | return ERR_PTR(-ENOMEM); |
8309 | 8323 | ||
8310 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8324 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8311 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8325 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8312 | pipe_config->cpu_transcoder = |
8326 | pipe_config->cpu_transcoder = |
8313 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8327 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8314 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8328 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8315 | 8329 | ||
8316 | /* |
8330 | /* |
8317 | * Sanitize sync polarity flags based on requested ones. If neither |
8331 | * Sanitize sync polarity flags based on requested ones. If neither |
8318 | * positive or negative polarity is requested, treat this as meaning |
8332 | * positive or negative polarity is requested, treat this as meaning |
8319 | * negative polarity. |
8333 | * negative polarity. |
8320 | */ |
8334 | */ |
8321 | if (!(pipe_config->adjusted_mode.flags & |
8335 | if (!(pipe_config->adjusted_mode.flags & |
8322 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
8336 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
8323 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
8337 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
8324 | 8338 | ||
8325 | if (!(pipe_config->adjusted_mode.flags & |
8339 | if (!(pipe_config->adjusted_mode.flags & |
8326 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
8340 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
8327 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
8341 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
8328 | 8342 | ||
8329 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8343 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8330 | * plane pixel format and any sink constraints into account. Returns the |
8344 | * plane pixel format and any sink constraints into account. Returns the |
8331 | * source plane bpp so that dithering can be selected on mismatches |
8345 | * source plane bpp so that dithering can be selected on mismatches |
8332 | * after encoders and crtc also have had their say. */ |
8346 | * after encoders and crtc also have had their say. */ |
8333 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8347 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8334 | fb, pipe_config); |
8348 | fb, pipe_config); |
8335 | if (plane_bpp < 0) |
8349 | if (plane_bpp < 0) |
8336 | goto fail; |
8350 | goto fail; |
8337 | 8351 | ||
8338 | encoder_retry: |
8352 | encoder_retry: |
8339 | /* Ensure the port clock defaults are reset when retrying. */ |
8353 | /* Ensure the port clock defaults are reset when retrying. */ |
8340 | pipe_config->port_clock = 0; |
8354 | pipe_config->port_clock = 0; |
8341 | pipe_config->pixel_multiplier = 1; |
8355 | pipe_config->pixel_multiplier = 1; |
8342 | 8356 | ||
8343 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8357 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8344 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
8358 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
8345 | 8359 | ||
8346 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8360 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8347 | * adjust it according to limitations or connector properties, and also |
8361 | * adjust it according to limitations or connector properties, and also |
8348 | * a chance to reject the mode entirely. |
8362 | * a chance to reject the mode entirely. |
8349 | */ |
8363 | */ |
8350 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8364 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8351 | base.head) { |
8365 | base.head) { |
8352 | 8366 | ||
8353 | if (&encoder->new_crtc->base != crtc) |
8367 | if (&encoder->new_crtc->base != crtc) |
8354 | continue; |
8368 | continue; |
8355 | 8369 | ||
8356 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8370 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8357 | DRM_DEBUG_KMS("Encoder config failure\n"); |
8371 | DRM_DEBUG_KMS("Encoder config failure\n"); |
8358 | goto fail; |
8372 | goto fail; |
8359 | } |
8373 | } |
8360 | } |
8374 | } |
8361 | 8375 | ||
8362 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8376 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8363 | * done afterwards in case the encoder adjusts the mode. */ |
8377 | * done afterwards in case the encoder adjusts the mode. */ |
8364 | if (!pipe_config->port_clock) |
8378 | if (!pipe_config->port_clock) |
8365 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
8379 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
8366 | 8380 | ||
8367 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8381 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8368 | if (ret < 0) { |
8382 | if (ret < 0) { |
8369 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8383 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8370 | goto fail; |
8384 | goto fail; |
8371 | } |
8385 | } |
8372 | 8386 | ||
8373 | if (ret == RETRY) { |
8387 | if (ret == RETRY) { |
8374 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
8388 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
8375 | ret = -EINVAL; |
8389 | ret = -EINVAL; |
8376 | goto fail; |
8390 | goto fail; |
8377 | } |
8391 | } |
8378 | 8392 | ||
8379 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
8393 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
8380 | retry = false; |
8394 | retry = false; |
8381 | goto encoder_retry; |
8395 | goto encoder_retry; |
8382 | } |
8396 | } |
8383 | 8397 | ||
8384 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8398 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8385 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
8399 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
8386 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
8400 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
8387 | 8401 | ||
8388 | return pipe_config; |
8402 | return pipe_config; |
8389 | fail: |
8403 | fail: |
8390 | kfree(pipe_config); |
8404 | kfree(pipe_config); |
8391 | return ERR_PTR(ret); |
8405 | return ERR_PTR(ret); |
8392 | } |
8406 | } |
8393 | 8407 | ||
8394 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8408 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8395 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
8409 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
8396 | static void |
8410 | static void |
8397 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
8411 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
8398 | unsigned *prepare_pipes, unsigned *disable_pipes) |
8412 | unsigned *prepare_pipes, unsigned *disable_pipes) |
8399 | { |
8413 | { |
8400 | struct intel_crtc *intel_crtc; |
8414 | struct intel_crtc *intel_crtc; |
8401 | struct drm_device *dev = crtc->dev; |
8415 | struct drm_device *dev = crtc->dev; |
8402 | struct intel_encoder *encoder; |
8416 | struct intel_encoder *encoder; |
8403 | struct intel_connector *connector; |
8417 | struct intel_connector *connector; |
8404 | struct drm_crtc *tmp_crtc; |
8418 | struct drm_crtc *tmp_crtc; |
8405 | 8419 | ||
8406 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
8420 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
8407 | 8421 | ||
8408 | /* Check which crtcs have changed outputs connected to them, these need |
8422 | /* Check which crtcs have changed outputs connected to them, these need |
8409 | * to be part of the prepare_pipes mask. We don't (yet) support global |
8423 | * to be part of the prepare_pipes mask. We don't (yet) support global |
8410 | * modeset across multiple crtcs, so modeset_pipes will only have one |
8424 | * modeset across multiple crtcs, so modeset_pipes will only have one |
8411 | * bit set at most. */ |
8425 | * bit set at most. */ |
8412 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8426 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8413 | base.head) { |
8427 | base.head) { |
8414 | if (connector->base.encoder == &connector->new_encoder->base) |
8428 | if (connector->base.encoder == &connector->new_encoder->base) |
8415 | continue; |
8429 | continue; |
8416 | 8430 | ||
8417 | if (connector->base.encoder) { |
8431 | if (connector->base.encoder) { |
8418 | tmp_crtc = connector->base.encoder->crtc; |
8432 | tmp_crtc = connector->base.encoder->crtc; |
8419 | 8433 | ||
8420 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8434 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8421 | } |
8435 | } |
8422 | 8436 | ||
8423 | if (connector->new_encoder) |
8437 | if (connector->new_encoder) |
8424 | *prepare_pipes |= |
8438 | *prepare_pipes |= |
8425 | 1 << connector->new_encoder->new_crtc->pipe; |
8439 | 1 << connector->new_encoder->new_crtc->pipe; |
8426 | } |
8440 | } |
8427 | 8441 | ||
8428 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8442 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8429 | base.head) { |
8443 | base.head) { |
8430 | if (encoder->base.crtc == &encoder->new_crtc->base) |
8444 | if (encoder->base.crtc == &encoder->new_crtc->base) |
8431 | continue; |
8445 | continue; |
8432 | 8446 | ||
8433 | if (encoder->base.crtc) { |
8447 | if (encoder->base.crtc) { |
8434 | tmp_crtc = encoder->base.crtc; |
8448 | tmp_crtc = encoder->base.crtc; |
8435 | 8449 | ||
8436 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8450 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8437 | } |
8451 | } |
8438 | 8452 | ||
8439 | if (encoder->new_crtc) |
8453 | if (encoder->new_crtc) |
8440 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
8454 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
8441 | } |
8455 | } |
8442 | 8456 | ||
8443 | /* Check for any pipes that will be fully disabled ... */ |
8457 | /* Check for any pipes that will be fully disabled ... */ |
8444 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8458 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8445 | base.head) { |
8459 | base.head) { |
8446 | bool used = false; |
8460 | bool used = false; |
8447 | 8461 | ||
8448 | /* Don't try to disable disabled crtcs. */ |
8462 | /* Don't try to disable disabled crtcs. */ |
8449 | if (!intel_crtc->base.enabled) |
8463 | if (!intel_crtc->base.enabled) |
8450 | continue; |
8464 | continue; |
8451 | 8465 | ||
8452 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8466 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8453 | base.head) { |
8467 | base.head) { |
8454 | if (encoder->new_crtc == intel_crtc) |
8468 | if (encoder->new_crtc == intel_crtc) |
8455 | used = true; |
8469 | used = true; |
8456 | } |
8470 | } |
8457 | 8471 | ||
8458 | if (!used) |
8472 | if (!used) |
8459 | *disable_pipes |= 1 << intel_crtc->pipe; |
8473 | *disable_pipes |= 1 << intel_crtc->pipe; |
8460 | } |
8474 | } |
8461 | 8475 | ||
8462 | 8476 | ||
8463 | /* set_mode is also used to update properties on life display pipes. */ |
8477 | /* set_mode is also used to update properties on life display pipes. */ |
8464 | intel_crtc = to_intel_crtc(crtc); |
8478 | intel_crtc = to_intel_crtc(crtc); |
8465 | if (crtc->enabled) |
8479 | if (crtc->enabled) |
8466 | *prepare_pipes |= 1 << intel_crtc->pipe; |
8480 | *prepare_pipes |= 1 << intel_crtc->pipe; |
8467 | 8481 | ||
8468 | /* |
8482 | /* |
8469 | * For simplicity do a full modeset on any pipe where the output routing |
8483 | * For simplicity do a full modeset on any pipe where the output routing |
8470 | * changed. We could be more clever, but that would require us to be |
8484 | * changed. We could be more clever, but that would require us to be |
8471 | * more careful with calling the relevant encoder->mode_set functions. |
8485 | * more careful with calling the relevant encoder->mode_set functions. |
8472 | */ |
8486 | */ |
8473 | if (*prepare_pipes) |
8487 | if (*prepare_pipes) |
8474 | *modeset_pipes = *prepare_pipes; |
8488 | *modeset_pipes = *prepare_pipes; |
8475 | 8489 | ||
8476 | /* ... and mask these out. */ |
8490 | /* ... and mask these out. */ |
8477 | *modeset_pipes &= ~(*disable_pipes); |
8491 | *modeset_pipes &= ~(*disable_pipes); |
8478 | *prepare_pipes &= ~(*disable_pipes); |
8492 | *prepare_pipes &= ~(*disable_pipes); |
8479 | 8493 | ||
8480 | /* |
8494 | /* |
8481 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
8495 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
8482 | * obies this rule, but the modeset restore mode of |
8496 | * obies this rule, but the modeset restore mode of |
8483 | * intel_modeset_setup_hw_state does not. |
8497 | * intel_modeset_setup_hw_state does not. |
8484 | */ |
8498 | */ |
8485 | *modeset_pipes &= 1 << intel_crtc->pipe; |
8499 | *modeset_pipes &= 1 << intel_crtc->pipe; |
8486 | *prepare_pipes &= 1 << intel_crtc->pipe; |
8500 | *prepare_pipes &= 1 << intel_crtc->pipe; |
8487 | 8501 | ||
8488 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
8502 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
8489 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
8503 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
8490 | } |
8504 | } |
8491 | 8505 | ||
8492 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
8506 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
8493 | { |
8507 | { |
8494 | struct drm_encoder *encoder; |
8508 | struct drm_encoder *encoder; |
8495 | struct drm_device *dev = crtc->dev; |
8509 | struct drm_device *dev = crtc->dev; |
8496 | 8510 | ||
8497 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8511 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8498 | if (encoder->crtc == crtc) |
8512 | if (encoder->crtc == crtc) |
8499 | return true; |
8513 | return true; |
8500 | 8514 | ||
8501 | return false; |
8515 | return false; |
8502 | } |
8516 | } |
8503 | 8517 | ||
8504 | static void |
8518 | static void |
8505 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
8519 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
8506 | { |
8520 | { |
8507 | struct intel_encoder *intel_encoder; |
8521 | struct intel_encoder *intel_encoder; |
8508 | struct intel_crtc *intel_crtc; |
8522 | struct intel_crtc *intel_crtc; |
8509 | struct drm_connector *connector; |
8523 | struct drm_connector *connector; |
8510 | 8524 | ||
8511 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
8525 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
8512 | base.head) { |
8526 | base.head) { |
8513 | if (!intel_encoder->base.crtc) |
8527 | if (!intel_encoder->base.crtc) |
8514 | continue; |
8528 | continue; |
8515 | 8529 | ||
8516 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
8530 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
8517 | 8531 | ||
8518 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
8532 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
8519 | intel_encoder->connectors_active = false; |
8533 | intel_encoder->connectors_active = false; |
8520 | } |
8534 | } |
8521 | 8535 | ||
8522 | intel_modeset_commit_output_state(dev); |
8536 | intel_modeset_commit_output_state(dev); |
8523 | 8537 | ||
8524 | /* Update computed state. */ |
8538 | /* Update computed state. */ |
8525 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8539 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8526 | base.head) { |
8540 | base.head) { |
8527 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
8541 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
8528 | } |
8542 | } |
8529 | 8543 | ||
8530 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
8544 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
8531 | if (!connector->encoder || !connector->encoder->crtc) |
8545 | if (!connector->encoder || !connector->encoder->crtc) |
8532 | continue; |
8546 | continue; |
8533 | 8547 | ||
8534 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
8548 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
8535 | 8549 | ||
8536 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
8550 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
8537 | struct drm_property *dpms_property = |
8551 | struct drm_property *dpms_property = |
8538 | dev->mode_config.dpms_property; |
8552 | dev->mode_config.dpms_property; |
8539 | 8553 | ||
8540 | connector->dpms = DRM_MODE_DPMS_ON; |
8554 | connector->dpms = DRM_MODE_DPMS_ON; |
8541 | drm_object_property_set_value(&connector->base, |
8555 | drm_object_property_set_value(&connector->base, |
8542 | dpms_property, |
8556 | dpms_property, |
8543 | DRM_MODE_DPMS_ON); |
8557 | DRM_MODE_DPMS_ON); |
8544 | 8558 | ||
8545 | intel_encoder = to_intel_encoder(connector->encoder); |
8559 | intel_encoder = to_intel_encoder(connector->encoder); |
8546 | intel_encoder->connectors_active = true; |
8560 | intel_encoder->connectors_active = true; |
8547 | } |
8561 | } |
8548 | } |
8562 | } |
8549 | 8563 | ||
8550 | } |
8564 | } |
8551 | 8565 | ||
8552 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8566 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8553 | struct intel_crtc_config *new) |
8567 | struct intel_crtc_config *new) |
8554 | { |
8568 | { |
8555 | int clock1, clock2, diff; |
8569 | int clock1, clock2, diff; |
8556 | 8570 | ||
8557 | clock1 = cur->adjusted_mode.clock; |
8571 | clock1 = cur->adjusted_mode.clock; |
8558 | clock2 = new->adjusted_mode.clock; |
8572 | clock2 = new->adjusted_mode.clock; |
8559 | 8573 | ||
8560 | if (clock1 == clock2) |
8574 | if (clock1 == clock2) |
8561 | return true; |
8575 | return true; |
8562 | 8576 | ||
8563 | if (!clock1 || !clock2) |
8577 | if (!clock1 || !clock2) |
8564 | return false; |
8578 | return false; |
8565 | 8579 | ||
8566 | diff = abs(clock1 - clock2); |
8580 | diff = abs(clock1 - clock2); |
8567 | 8581 | ||
8568 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
8582 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
8569 | return true; |
8583 | return true; |
8570 | 8584 | ||
8571 | return false; |
8585 | return false; |
8572 | } |
8586 | } |
8573 | 8587 | ||
8574 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8588 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8575 | list_for_each_entry((intel_crtc), \ |
8589 | list_for_each_entry((intel_crtc), \ |
8576 | &(dev)->mode_config.crtc_list, \ |
8590 | &(dev)->mode_config.crtc_list, \ |
8577 | base.head) \ |
8591 | base.head) \ |
8578 | if (mask & (1 <<(intel_crtc)->pipe)) |
8592 | if (mask & (1 <<(intel_crtc)->pipe)) |
8579 | 8593 | ||
8580 | static bool |
8594 | static bool |
8581 | intel_pipe_config_compare(struct drm_device *dev, |
8595 | intel_pipe_config_compare(struct drm_device *dev, |
8582 | struct intel_crtc_config *current_config, |
8596 | struct intel_crtc_config *current_config, |
8583 | struct intel_crtc_config *pipe_config) |
8597 | struct intel_crtc_config *pipe_config) |
8584 | { |
8598 | { |
8585 | #define PIPE_CONF_CHECK_X(name) \ |
8599 | #define PIPE_CONF_CHECK_X(name) \ |
8586 | if (current_config->name != pipe_config->name) { \ |
8600 | if (current_config->name != pipe_config->name) { \ |
8587 | DRM_ERROR("mismatch in " #name " " \ |
8601 | DRM_ERROR("mismatch in " #name " " \ |
8588 | "(expected 0x%08x, found 0x%08x)\n", \ |
8602 | "(expected 0x%08x, found 0x%08x)\n", \ |
8589 | current_config->name, \ |
8603 | current_config->name, \ |
8590 | pipe_config->name); \ |
8604 | pipe_config->name); \ |
8591 | return false; \ |
8605 | return false; \ |
8592 | } |
8606 | } |
8593 | 8607 | ||
8594 | #define PIPE_CONF_CHECK_I(name) \ |
8608 | #define PIPE_CONF_CHECK_I(name) \ |
8595 | if (current_config->name != pipe_config->name) { \ |
8609 | if (current_config->name != pipe_config->name) { \ |
8596 | DRM_ERROR("mismatch in " #name " " \ |
8610 | DRM_ERROR("mismatch in " #name " " \ |
8597 | "(expected %i, found %i)\n", \ |
8611 | "(expected %i, found %i)\n", \ |
8598 | current_config->name, \ |
8612 | current_config->name, \ |
8599 | pipe_config->name); \ |
8613 | pipe_config->name); \ |
8600 | return false; \ |
8614 | return false; \ |
8601 | } |
8615 | } |
8602 | 8616 | ||
8603 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8617 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8604 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
8618 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
8605 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
8619 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
8606 | "(expected %i, found %i)\n", \ |
8620 | "(expected %i, found %i)\n", \ |
8607 | current_config->name & (mask), \ |
8621 | current_config->name & (mask), \ |
8608 | pipe_config->name & (mask)); \ |
8622 | pipe_config->name & (mask)); \ |
8609 | return false; \ |
8623 | return false; \ |
8610 | } |
8624 | } |
8611 | 8625 | ||
8612 | #define PIPE_CONF_QUIRK(quirk) \ |
8626 | #define PIPE_CONF_QUIRK(quirk) \ |
8613 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
8627 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
8614 | 8628 | ||
8615 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8629 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8616 | 8630 | ||
8617 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8631 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8618 | PIPE_CONF_CHECK_I(fdi_lanes); |
8632 | PIPE_CONF_CHECK_I(fdi_lanes); |
8619 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8633 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8620 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
8634 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
8621 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
8635 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
8622 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
8636 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
8623 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
8637 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
8624 | 8638 | ||
8625 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8639 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8626 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
8640 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
8627 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
8641 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
8628 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
8642 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
8629 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
8643 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
8630 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
8644 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
8631 | 8645 | ||
8632 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
8646 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
8633 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
8647 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
8634 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
8648 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
8635 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
8649 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
8636 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
8650 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
8637 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
8651 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
8638 | 8652 | ||
8639 | PIPE_CONF_CHECK_I(pixel_multiplier); |
8653 | PIPE_CONF_CHECK_I(pixel_multiplier); |
8640 | 8654 | ||
8641 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8655 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8642 | DRM_MODE_FLAG_INTERLACE); |
8656 | DRM_MODE_FLAG_INTERLACE); |
8643 | 8657 | ||
8644 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8658 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8645 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8659 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8646 | DRM_MODE_FLAG_PHSYNC); |
8660 | DRM_MODE_FLAG_PHSYNC); |
8647 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8661 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8648 | DRM_MODE_FLAG_NHSYNC); |
8662 | DRM_MODE_FLAG_NHSYNC); |
8649 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8663 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8650 | DRM_MODE_FLAG_PVSYNC); |
8664 | DRM_MODE_FLAG_PVSYNC); |
8651 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8665 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8652 | DRM_MODE_FLAG_NVSYNC); |
8666 | DRM_MODE_FLAG_NVSYNC); |
8653 | } |
8667 | } |
8654 | 8668 | ||
8655 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
8669 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
8656 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
8670 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
8657 | 8671 | ||
8658 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8672 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8659 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
8673 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
8660 | if (INTEL_INFO(dev)->gen < 4) |
8674 | if (INTEL_INFO(dev)->gen < 4) |
8661 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
8675 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
8662 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
8676 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
8663 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8677 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8664 | if (current_config->pch_pfit.enabled) { |
8678 | if (current_config->pch_pfit.enabled) { |
8665 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
8679 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
8666 | PIPE_CONF_CHECK_I(pch_pfit.size); |
8680 | PIPE_CONF_CHECK_I(pch_pfit.size); |
8667 | } |
8681 | } |
8668 | 8682 | ||
8669 | PIPE_CONF_CHECK_I(ips_enabled); |
8683 | PIPE_CONF_CHECK_I(ips_enabled); |
8670 | 8684 | ||
8671 | PIPE_CONF_CHECK_I(shared_dpll); |
8685 | PIPE_CONF_CHECK_I(shared_dpll); |
8672 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8686 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8673 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8687 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8674 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8688 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8675 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
8689 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
8676 | 8690 | ||
8677 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
8691 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
8678 | PIPE_CONF_CHECK_I(pipe_bpp); |
8692 | PIPE_CONF_CHECK_I(pipe_bpp); |
8679 | 8693 | ||
8680 | #undef PIPE_CONF_CHECK_X |
8694 | #undef PIPE_CONF_CHECK_X |
8681 | #undef PIPE_CONF_CHECK_I |
8695 | #undef PIPE_CONF_CHECK_I |
8682 | #undef PIPE_CONF_CHECK_FLAGS |
8696 | #undef PIPE_CONF_CHECK_FLAGS |
8683 | #undef PIPE_CONF_QUIRK |
8697 | #undef PIPE_CONF_QUIRK |
8684 | 8698 | ||
8685 | if (!IS_HASWELL(dev)) { |
8699 | if (!IS_HASWELL(dev)) { |
8686 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
8700 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
8687 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
8701 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
8688 | current_config->adjusted_mode.clock, |
8702 | current_config->adjusted_mode.clock, |
8689 | pipe_config->adjusted_mode.clock); |
8703 | pipe_config->adjusted_mode.clock); |
8690 | return false; |
8704 | return false; |
8691 | } |
8705 | } |
8692 | } |
8706 | } |
8693 | 8707 | ||
8694 | return true; |
8708 | return true; |
8695 | } |
8709 | } |
8696 | 8710 | ||
8697 | static void |
8711 | static void |
8698 | check_connector_state(struct drm_device *dev) |
8712 | check_connector_state(struct drm_device *dev) |
8699 | { |
8713 | { |
8700 | struct intel_connector *connector; |
8714 | struct intel_connector *connector; |
8701 | 8715 | ||
8702 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8716 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8703 | base.head) { |
8717 | base.head) { |
8704 | /* This also checks the encoder/connector hw state with the |
8718 | /* This also checks the encoder/connector hw state with the |
8705 | * ->get_hw_state callbacks. */ |
8719 | * ->get_hw_state callbacks. */ |
8706 | intel_connector_check_state(connector); |
8720 | intel_connector_check_state(connector); |
8707 | 8721 | ||
8708 | WARN(&connector->new_encoder->base != connector->base.encoder, |
8722 | WARN(&connector->new_encoder->base != connector->base.encoder, |
8709 | "connector's staged encoder doesn't match current encoder\n"); |
8723 | "connector's staged encoder doesn't match current encoder\n"); |
8710 | } |
8724 | } |
8711 | } |
8725 | } |
8712 | 8726 | ||
8713 | static void |
8727 | static void |
8714 | check_encoder_state(struct drm_device *dev) |
8728 | check_encoder_state(struct drm_device *dev) |
8715 | { |
8729 | { |
8716 | struct intel_encoder *encoder; |
8730 | struct intel_encoder *encoder; |
8717 | struct intel_connector *connector; |
8731 | struct intel_connector *connector; |
8718 | 8732 | ||
8719 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8733 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8720 | base.head) { |
8734 | base.head) { |
8721 | bool enabled = false; |
8735 | bool enabled = false; |
8722 | bool active = false; |
8736 | bool active = false; |
8723 | enum pipe pipe, tracked_pipe; |
8737 | enum pipe pipe, tracked_pipe; |
8724 | 8738 | ||
8725 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
8739 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
8726 | encoder->base.base.id, |
8740 | encoder->base.base.id, |
8727 | drm_get_encoder_name(&encoder->base)); |
8741 | drm_get_encoder_name(&encoder->base)); |
8728 | 8742 | ||
8729 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8743 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8730 | "encoder's stage crtc doesn't match current crtc\n"); |
8744 | "encoder's stage crtc doesn't match current crtc\n"); |
8731 | WARN(encoder->connectors_active && !encoder->base.crtc, |
8745 | WARN(encoder->connectors_active && !encoder->base.crtc, |
8732 | "encoder's active_connectors set, but no crtc\n"); |
8746 | "encoder's active_connectors set, but no crtc\n"); |
8733 | 8747 | ||
8734 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8748 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8735 | base.head) { |
8749 | base.head) { |
8736 | if (connector->base.encoder != &encoder->base) |
8750 | if (connector->base.encoder != &encoder->base) |
8737 | continue; |
8751 | continue; |
8738 | enabled = true; |
8752 | enabled = true; |
8739 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
8753 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
8740 | active = true; |
8754 | active = true; |
8741 | } |
8755 | } |
8742 | WARN(!!encoder->base.crtc != enabled, |
8756 | WARN(!!encoder->base.crtc != enabled, |
8743 | "encoder's enabled state mismatch " |
8757 | "encoder's enabled state mismatch " |
8744 | "(expected %i, found %i)\n", |
8758 | "(expected %i, found %i)\n", |
8745 | !!encoder->base.crtc, enabled); |
8759 | !!encoder->base.crtc, enabled); |
8746 | WARN(active && !encoder->base.crtc, |
8760 | WARN(active && !encoder->base.crtc, |
8747 | "active encoder with no crtc\n"); |
8761 | "active encoder with no crtc\n"); |
8748 | 8762 | ||
8749 | WARN(encoder->connectors_active != active, |
8763 | WARN(encoder->connectors_active != active, |
8750 | "encoder's computed active state doesn't match tracked active state " |
8764 | "encoder's computed active state doesn't match tracked active state " |
8751 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
8765 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
8752 | 8766 | ||
8753 | active = encoder->get_hw_state(encoder, &pipe); |
8767 | active = encoder->get_hw_state(encoder, &pipe); |
8754 | WARN(active != encoder->connectors_active, |
8768 | WARN(active != encoder->connectors_active, |
8755 | "encoder's hw state doesn't match sw tracking " |
8769 | "encoder's hw state doesn't match sw tracking " |
8756 | "(expected %i, found %i)\n", |
8770 | "(expected %i, found %i)\n", |
8757 | encoder->connectors_active, active); |
8771 | encoder->connectors_active, active); |
8758 | 8772 | ||
8759 | if (!encoder->base.crtc) |
8773 | if (!encoder->base.crtc) |
8760 | continue; |
8774 | continue; |
8761 | 8775 | ||
8762 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
8776 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
8763 | WARN(active && pipe != tracked_pipe, |
8777 | WARN(active && pipe != tracked_pipe, |
8764 | "active encoder's pipe doesn't match" |
8778 | "active encoder's pipe doesn't match" |
8765 | "(expected %i, found %i)\n", |
8779 | "(expected %i, found %i)\n", |
8766 | tracked_pipe, pipe); |
8780 | tracked_pipe, pipe); |
8767 | 8781 | ||
8768 | } |
8782 | } |
8769 | } |
8783 | } |
8770 | 8784 | ||
8771 | static void |
8785 | static void |
8772 | check_crtc_state(struct drm_device *dev) |
8786 | check_crtc_state(struct drm_device *dev) |
8773 | { |
8787 | { |
8774 | drm_i915_private_t *dev_priv = dev->dev_private; |
8788 | drm_i915_private_t *dev_priv = dev->dev_private; |
8775 | struct intel_crtc *crtc; |
8789 | struct intel_crtc *crtc; |
8776 | struct intel_encoder *encoder; |
8790 | struct intel_encoder *encoder; |
8777 | struct intel_crtc_config pipe_config; |
8791 | struct intel_crtc_config pipe_config; |
8778 | 8792 | ||
8779 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8793 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8780 | base.head) { |
8794 | base.head) { |
8781 | bool enabled = false; |
8795 | bool enabled = false; |
8782 | bool active = false; |
8796 | bool active = false; |
8783 | 8797 | ||
8784 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8798 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8785 | 8799 | ||
8786 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8800 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8787 | crtc->base.base.id); |
8801 | crtc->base.base.id); |
8788 | 8802 | ||
8789 | WARN(crtc->active && !crtc->base.enabled, |
8803 | WARN(crtc->active && !crtc->base.enabled, |
8790 | "active crtc, but not enabled in sw tracking\n"); |
8804 | "active crtc, but not enabled in sw tracking\n"); |
8791 | 8805 | ||
8792 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8806 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8793 | base.head) { |
8807 | base.head) { |
8794 | if (encoder->base.crtc != &crtc->base) |
8808 | if (encoder->base.crtc != &crtc->base) |
8795 | continue; |
8809 | continue; |
8796 | enabled = true; |
8810 | enabled = true; |
8797 | if (encoder->connectors_active) |
8811 | if (encoder->connectors_active) |
8798 | active = true; |
8812 | active = true; |
8799 | } |
8813 | } |
8800 | 8814 | ||
8801 | WARN(active != crtc->active, |
8815 | WARN(active != crtc->active, |
8802 | "crtc's computed active state doesn't match tracked active state " |
8816 | "crtc's computed active state doesn't match tracked active state " |
8803 | "(expected %i, found %i)\n", active, crtc->active); |
8817 | "(expected %i, found %i)\n", active, crtc->active); |
8804 | WARN(enabled != crtc->base.enabled, |
8818 | WARN(enabled != crtc->base.enabled, |
8805 | "crtc's computed enabled state doesn't match tracked enabled state " |
8819 | "crtc's computed enabled state doesn't match tracked enabled state " |
8806 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
8820 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
8807 | 8821 | ||
8808 | active = dev_priv->display.get_pipe_config(crtc, |
8822 | active = dev_priv->display.get_pipe_config(crtc, |
8809 | &pipe_config); |
8823 | &pipe_config); |
8810 | 8824 | ||
8811 | /* hw state is inconsistent with the pipe A quirk */ |
8825 | /* hw state is inconsistent with the pipe A quirk */ |
8812 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
8826 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
8813 | active = crtc->active; |
8827 | active = crtc->active; |
8814 | 8828 | ||
8815 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8829 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8816 | base.head) { |
8830 | base.head) { |
8817 | enum pipe pipe; |
8831 | enum pipe pipe; |
8818 | if (encoder->base.crtc != &crtc->base) |
8832 | if (encoder->base.crtc != &crtc->base) |
8819 | continue; |
8833 | continue; |
8820 | if (encoder->get_config && |
8834 | if (encoder->get_config && |
8821 | encoder->get_hw_state(encoder, &pipe)) |
8835 | encoder->get_hw_state(encoder, &pipe)) |
8822 | encoder->get_config(encoder, &pipe_config); |
8836 | encoder->get_config(encoder, &pipe_config); |
8823 | } |
8837 | } |
8824 | 8838 | ||
8825 | if (dev_priv->display.get_clock) |
8839 | if (dev_priv->display.get_clock) |
8826 | dev_priv->display.get_clock(crtc, &pipe_config); |
8840 | dev_priv->display.get_clock(crtc, &pipe_config); |
8827 | 8841 | ||
8828 | WARN(crtc->active != active, |
8842 | WARN(crtc->active != active, |
8829 | "crtc active state doesn't match with hw state " |
8843 | "crtc active state doesn't match with hw state " |
8830 | "(expected %i, found %i)\n", crtc->active, active); |
8844 | "(expected %i, found %i)\n", crtc->active, active); |
8831 | 8845 | ||
8832 | if (active && |
8846 | if (active && |
8833 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
8847 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
8834 | WARN(1, "pipe state doesn't match!\n"); |
8848 | WARN(1, "pipe state doesn't match!\n"); |
8835 | intel_dump_pipe_config(crtc, &pipe_config, |
8849 | intel_dump_pipe_config(crtc, &pipe_config, |
8836 | "[hw state]"); |
8850 | "[hw state]"); |
8837 | intel_dump_pipe_config(crtc, &crtc->config, |
8851 | intel_dump_pipe_config(crtc, &crtc->config, |
8838 | "[sw state]"); |
8852 | "[sw state]"); |
8839 | } |
8853 | } |
8840 | } |
8854 | } |
8841 | } |
8855 | } |
8842 | 8856 | ||
8843 | static void |
8857 | static void |
8844 | check_shared_dpll_state(struct drm_device *dev) |
8858 | check_shared_dpll_state(struct drm_device *dev) |
8845 | { |
8859 | { |
8846 | drm_i915_private_t *dev_priv = dev->dev_private; |
8860 | drm_i915_private_t *dev_priv = dev->dev_private; |
8847 | struct intel_crtc *crtc; |
8861 | struct intel_crtc *crtc; |
8848 | struct intel_dpll_hw_state dpll_hw_state; |
8862 | struct intel_dpll_hw_state dpll_hw_state; |
8849 | int i; |
8863 | int i; |
8850 | 8864 | ||
8851 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
8865 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
8852 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
8866 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
8853 | int enabled_crtcs = 0, active_crtcs = 0; |
8867 | int enabled_crtcs = 0, active_crtcs = 0; |
8854 | bool active; |
8868 | bool active; |
8855 | 8869 | ||
8856 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
8870 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
8857 | 8871 | ||
8858 | DRM_DEBUG_KMS("%s\n", pll->name); |
8872 | DRM_DEBUG_KMS("%s\n", pll->name); |
8859 | 8873 | ||
8860 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
8874 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
8861 | 8875 | ||
8862 | WARN(pll->active > pll->refcount, |
8876 | WARN(pll->active > pll->refcount, |
8863 | "more active pll users than references: %i vs %i\n", |
8877 | "more active pll users than references: %i vs %i\n", |
8864 | pll->active, pll->refcount); |
8878 | pll->active, pll->refcount); |
8865 | WARN(pll->active && !pll->on, |
8879 | WARN(pll->active && !pll->on, |
8866 | "pll in active use but not on in sw tracking\n"); |
8880 | "pll in active use but not on in sw tracking\n"); |
8867 | WARN(pll->on && !pll->active, |
8881 | WARN(pll->on && !pll->active, |
8868 | "pll in on but not on in use in sw tracking\n"); |
8882 | "pll in on but not on in use in sw tracking\n"); |
8869 | WARN(pll->on != active, |
8883 | WARN(pll->on != active, |
8870 | "pll on state mismatch (expected %i, found %i)\n", |
8884 | "pll on state mismatch (expected %i, found %i)\n", |
8871 | pll->on, active); |
8885 | pll->on, active); |
8872 | 8886 | ||
8873 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8887 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8874 | base.head) { |
8888 | base.head) { |
8875 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
8889 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
8876 | enabled_crtcs++; |
8890 | enabled_crtcs++; |
8877 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
8891 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
8878 | active_crtcs++; |
8892 | active_crtcs++; |
8879 | } |
8893 | } |
8880 | WARN(pll->active != active_crtcs, |
8894 | WARN(pll->active != active_crtcs, |
8881 | "pll active crtcs mismatch (expected %i, found %i)\n", |
8895 | "pll active crtcs mismatch (expected %i, found %i)\n", |
8882 | pll->active, active_crtcs); |
8896 | pll->active, active_crtcs); |
8883 | WARN(pll->refcount != enabled_crtcs, |
8897 | WARN(pll->refcount != enabled_crtcs, |
8884 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
8898 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
8885 | pll->refcount, enabled_crtcs); |
8899 | pll->refcount, enabled_crtcs); |
8886 | 8900 | ||
8887 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
8901 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
8888 | sizeof(dpll_hw_state)), |
8902 | sizeof(dpll_hw_state)), |
8889 | "pll hw state mismatch\n"); |
8903 | "pll hw state mismatch\n"); |
8890 | } |
8904 | } |
8891 | } |
8905 | } |
8892 | 8906 | ||
8893 | void |
8907 | void |
8894 | intel_modeset_check_state(struct drm_device *dev) |
8908 | intel_modeset_check_state(struct drm_device *dev) |
8895 | { |
8909 | { |
8896 | check_connector_state(dev); |
8910 | check_connector_state(dev); |
8897 | check_encoder_state(dev); |
8911 | check_encoder_state(dev); |
8898 | check_crtc_state(dev); |
8912 | check_crtc_state(dev); |
8899 | check_shared_dpll_state(dev); |
8913 | check_shared_dpll_state(dev); |
8900 | } |
8914 | } |
8901 | 8915 | ||
8902 | static int __intel_set_mode(struct drm_crtc *crtc, |
8916 | static int __intel_set_mode(struct drm_crtc *crtc, |
8903 | struct drm_display_mode *mode, |
8917 | struct drm_display_mode *mode, |
8904 | int x, int y, struct drm_framebuffer *fb) |
8918 | int x, int y, struct drm_framebuffer *fb) |
8905 | { |
8919 | { |
8906 | struct drm_device *dev = crtc->dev; |
8920 | struct drm_device *dev = crtc->dev; |
8907 | drm_i915_private_t *dev_priv = dev->dev_private; |
8921 | drm_i915_private_t *dev_priv = dev->dev_private; |
8908 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8922 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8909 | struct intel_crtc_config *pipe_config = NULL; |
8923 | struct intel_crtc_config *pipe_config = NULL; |
8910 | struct intel_crtc *intel_crtc; |
8924 | struct intel_crtc *intel_crtc; |
8911 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
8925 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
8912 | int ret = 0; |
8926 | int ret = 0; |
8913 | 8927 | ||
8914 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
8928 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
8915 | if (!saved_mode) |
8929 | if (!saved_mode) |
8916 | return -ENOMEM; |
8930 | return -ENOMEM; |
8917 | saved_hwmode = saved_mode + 1; |
8931 | saved_hwmode = saved_mode + 1; |
8918 | 8932 | ||
8919 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8933 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8920 | &prepare_pipes, &disable_pipes); |
8934 | &prepare_pipes, &disable_pipes); |
8921 | 8935 | ||
8922 | *saved_hwmode = crtc->hwmode; |
8936 | *saved_hwmode = crtc->hwmode; |
8923 | *saved_mode = crtc->mode; |
8937 | *saved_mode = crtc->mode; |
8924 | 8938 | ||
8925 | /* Hack: Because we don't (yet) support global modeset on multiple |
8939 | /* Hack: Because we don't (yet) support global modeset on multiple |
8926 | * crtcs, we don't keep track of the new mode for more than one crtc. |
8940 | * crtcs, we don't keep track of the new mode for more than one crtc. |
8927 | * Hence simply check whether any bit is set in modeset_pipes in all the |
8941 | * Hence simply check whether any bit is set in modeset_pipes in all the |
8928 | * pieces of code that are not yet converted to deal with mutliple crtcs |
8942 | * pieces of code that are not yet converted to deal with mutliple crtcs |
8929 | * changing their mode at the same time. */ |
8943 | * changing their mode at the same time. */ |
8930 | if (modeset_pipes) { |
8944 | if (modeset_pipes) { |
8931 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
8945 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
8932 | if (IS_ERR(pipe_config)) { |
8946 | if (IS_ERR(pipe_config)) { |
8933 | ret = PTR_ERR(pipe_config); |
8947 | ret = PTR_ERR(pipe_config); |
8934 | pipe_config = NULL; |
8948 | pipe_config = NULL; |
8935 | 8949 | ||
8936 | goto out; |
8950 | goto out; |
8937 | } |
8951 | } |
8938 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8952 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8939 | "[modeset]"); |
8953 | "[modeset]"); |
8940 | } |
8954 | } |
8941 | 8955 | ||
8942 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8956 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8943 | intel_crtc_disable(&intel_crtc->base); |
8957 | intel_crtc_disable(&intel_crtc->base); |
8944 | 8958 | ||
8945 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8959 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8946 | if (intel_crtc->base.enabled) |
8960 | if (intel_crtc->base.enabled) |
8947 | dev_priv->display.crtc_disable(&intel_crtc->base); |
8961 | dev_priv->display.crtc_disable(&intel_crtc->base); |
8948 | } |
8962 | } |
8949 | 8963 | ||
8950 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8964 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8951 | * to set it here already despite that we pass it down the callchain. |
8965 | * to set it here already despite that we pass it down the callchain. |
8952 | */ |
8966 | */ |
8953 | if (modeset_pipes) { |
8967 | if (modeset_pipes) { |
8954 | crtc->mode = *mode; |
8968 | crtc->mode = *mode; |
8955 | /* mode_set/enable/disable functions rely on a correct pipe |
8969 | /* mode_set/enable/disable functions rely on a correct pipe |
8956 | * config. */ |
8970 | * config. */ |
8957 | to_intel_crtc(crtc)->config = *pipe_config; |
8971 | to_intel_crtc(crtc)->config = *pipe_config; |
8958 | } |
8972 | } |
8959 | 8973 | ||
8960 | /* Only after disabling all output pipelines that will be changed can we |
8974 | /* Only after disabling all output pipelines that will be changed can we |
8961 | * update the the output configuration. */ |
8975 | * update the the output configuration. */ |
8962 | intel_modeset_update_state(dev, prepare_pipes); |
8976 | intel_modeset_update_state(dev, prepare_pipes); |
8963 | 8977 | ||
8964 | if (dev_priv->display.modeset_global_resources) |
8978 | if (dev_priv->display.modeset_global_resources) |
8965 | dev_priv->display.modeset_global_resources(dev); |
8979 | dev_priv->display.modeset_global_resources(dev); |
8966 | 8980 | ||
8967 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8981 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8968 | * on the DPLL. |
8982 | * on the DPLL. |
8969 | */ |
8983 | */ |
8970 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
8984 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
8971 | ret = intel_crtc_mode_set(&intel_crtc->base, |
8985 | ret = intel_crtc_mode_set(&intel_crtc->base, |
8972 | x, y, fb); |
8986 | x, y, fb); |
8973 | if (ret) |
8987 | if (ret) |
8974 | goto done; |
8988 | goto done; |
8975 | } |
8989 | } |
8976 | 8990 | ||
8977 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
8991 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
8978 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8992 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8979 | dev_priv->display.crtc_enable(&intel_crtc->base); |
8993 | dev_priv->display.crtc_enable(&intel_crtc->base); |
8980 | 8994 | ||
8981 | if (modeset_pipes) { |
8995 | if (modeset_pipes) { |
8982 | /* Store real post-adjustment hardware mode. */ |
8996 | /* Store real post-adjustment hardware mode. */ |
8983 | crtc->hwmode = pipe_config->adjusted_mode; |
8997 | crtc->hwmode = pipe_config->adjusted_mode; |
8984 | 8998 | ||
8985 | /* Calculate and store various constants which |
8999 | /* Calculate and store various constants which |
8986 | * are later needed by vblank and swap-completion |
9000 | * are later needed by vblank and swap-completion |
8987 | * timestamping. They are derived from true hwmode. |
9001 | * timestamping. They are derived from true hwmode. |
8988 | */ |
9002 | */ |
8989 | drm_calc_timestamping_constants(crtc); |
9003 | drm_calc_timestamping_constants(crtc); |
8990 | } |
9004 | } |
8991 | 9005 | ||
8992 | /* FIXME: add subpixel order */ |
9006 | /* FIXME: add subpixel order */ |
8993 | done: |
9007 | done: |
8994 | if (ret && crtc->enabled) { |
9008 | if (ret && crtc->enabled) { |
8995 | crtc->hwmode = *saved_hwmode; |
9009 | crtc->hwmode = *saved_hwmode; |
8996 | crtc->mode = *saved_mode; |
9010 | crtc->mode = *saved_mode; |
8997 | } |
9011 | } |
8998 | 9012 | ||
8999 | out: |
9013 | out: |
9000 | kfree(pipe_config); |
9014 | kfree(pipe_config); |
9001 | kfree(saved_mode); |
9015 | kfree(saved_mode); |
9002 | return ret; |
9016 | return ret; |
9003 | } |
9017 | } |
9004 | 9018 | ||
9005 | static int intel_set_mode(struct drm_crtc *crtc, |
9019 | static int intel_set_mode(struct drm_crtc *crtc, |
9006 | struct drm_display_mode *mode, |
9020 | struct drm_display_mode *mode, |
9007 | int x, int y, struct drm_framebuffer *fb) |
9021 | int x, int y, struct drm_framebuffer *fb) |
9008 | { |
9022 | { |
9009 | int ret; |
9023 | int ret; |
9010 | 9024 | ||
9011 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
9025 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
9012 | 9026 | ||
9013 | if (ret == 0) |
9027 | if (ret == 0) |
9014 | intel_modeset_check_state(crtc->dev); |
9028 | intel_modeset_check_state(crtc->dev); |
9015 | 9029 | ||
9016 | return ret; |
9030 | return ret; |
9017 | } |
9031 | } |
9018 | 9032 | ||
9019 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9033 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9020 | { |
9034 | { |
9021 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
9035 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
9022 | } |
9036 | } |
9023 | 9037 | ||
9024 | #undef for_each_intel_crtc_masked |
9038 | #undef for_each_intel_crtc_masked |
9025 | 9039 | ||
9026 | static void intel_set_config_free(struct intel_set_config *config) |
9040 | static void intel_set_config_free(struct intel_set_config *config) |
9027 | { |
9041 | { |
9028 | if (!config) |
9042 | if (!config) |
9029 | return; |
9043 | return; |
9030 | 9044 | ||
9031 | kfree(config->save_connector_encoders); |
9045 | kfree(config->save_connector_encoders); |
9032 | kfree(config->save_encoder_crtcs); |
9046 | kfree(config->save_encoder_crtcs); |
9033 | kfree(config); |
9047 | kfree(config); |
9034 | } |
9048 | } |
9035 | 9049 | ||
9036 | static int intel_set_config_save_state(struct drm_device *dev, |
9050 | static int intel_set_config_save_state(struct drm_device *dev, |
9037 | struct intel_set_config *config) |
9051 | struct intel_set_config *config) |
9038 | { |
9052 | { |
9039 | struct drm_encoder *encoder; |
9053 | struct drm_encoder *encoder; |
9040 | struct drm_connector *connector; |
9054 | struct drm_connector *connector; |
9041 | int count; |
9055 | int count; |
9042 | 9056 | ||
9043 | config->save_encoder_crtcs = |
9057 | config->save_encoder_crtcs = |
9044 | kcalloc(dev->mode_config.num_encoder, |
9058 | kcalloc(dev->mode_config.num_encoder, |
9045 | sizeof(struct drm_crtc *), GFP_KERNEL); |
9059 | sizeof(struct drm_crtc *), GFP_KERNEL); |
9046 | if (!config->save_encoder_crtcs) |
9060 | if (!config->save_encoder_crtcs) |
9047 | return -ENOMEM; |
9061 | return -ENOMEM; |
9048 | 9062 | ||
9049 | config->save_connector_encoders = |
9063 | config->save_connector_encoders = |
9050 | kcalloc(dev->mode_config.num_connector, |
9064 | kcalloc(dev->mode_config.num_connector, |
9051 | sizeof(struct drm_encoder *), GFP_KERNEL); |
9065 | sizeof(struct drm_encoder *), GFP_KERNEL); |
9052 | if (!config->save_connector_encoders) |
9066 | if (!config->save_connector_encoders) |
9053 | return -ENOMEM; |
9067 | return -ENOMEM; |
9054 | 9068 | ||
9055 | /* Copy data. Note that driver private data is not affected. |
9069 | /* Copy data. Note that driver private data is not affected. |
9056 | * Should anything bad happen only the expected state is |
9070 | * Should anything bad happen only the expected state is |
9057 | * restored, not the drivers personal bookkeeping. |
9071 | * restored, not the drivers personal bookkeeping. |
9058 | */ |
9072 | */ |
9059 | count = 0; |
9073 | count = 0; |
9060 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
9074 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
9061 | config->save_encoder_crtcs[count++] = encoder->crtc; |
9075 | config->save_encoder_crtcs[count++] = encoder->crtc; |
9062 | } |
9076 | } |
9063 | 9077 | ||
9064 | count = 0; |
9078 | count = 0; |
9065 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9079 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9066 | config->save_connector_encoders[count++] = connector->encoder; |
9080 | config->save_connector_encoders[count++] = connector->encoder; |
9067 | } |
9081 | } |
9068 | 9082 | ||
9069 | return 0; |
9083 | return 0; |
9070 | } |
9084 | } |
9071 | 9085 | ||
9072 | static void intel_set_config_restore_state(struct drm_device *dev, |
9086 | static void intel_set_config_restore_state(struct drm_device *dev, |
9073 | struct intel_set_config *config) |
9087 | struct intel_set_config *config) |
9074 | { |
9088 | { |
9075 | struct intel_encoder *encoder; |
9089 | struct intel_encoder *encoder; |
9076 | struct intel_connector *connector; |
9090 | struct intel_connector *connector; |
9077 | int count; |
9091 | int count; |
9078 | 9092 | ||
9079 | count = 0; |
9093 | count = 0; |
9080 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9094 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9081 | encoder->new_crtc = |
9095 | encoder->new_crtc = |
9082 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
9096 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
9083 | } |
9097 | } |
9084 | 9098 | ||
9085 | count = 0; |
9099 | count = 0; |
9086 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9100 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9087 | connector->new_encoder = |
9101 | connector->new_encoder = |
9088 | to_intel_encoder(config->save_connector_encoders[count++]); |
9102 | to_intel_encoder(config->save_connector_encoders[count++]); |
9089 | } |
9103 | } |
9090 | } |
9104 | } |
9091 | 9105 | ||
9092 | static bool |
9106 | static bool |
9093 | is_crtc_connector_off(struct drm_mode_set *set) |
9107 | is_crtc_connector_off(struct drm_mode_set *set) |
9094 | { |
9108 | { |
9095 | int i; |
9109 | int i; |
9096 | 9110 | ||
9097 | if (set->num_connectors == 0) |
9111 | if (set->num_connectors == 0) |
9098 | return false; |
9112 | return false; |
9099 | 9113 | ||
9100 | if (WARN_ON(set->connectors == NULL)) |
9114 | if (WARN_ON(set->connectors == NULL)) |
9101 | return false; |
9115 | return false; |
9102 | 9116 | ||
9103 | for (i = 0; i < set->num_connectors; i++) |
9117 | for (i = 0; i < set->num_connectors; i++) |
9104 | if (set->connectors[i]->encoder && |
9118 | if (set->connectors[i]->encoder && |
9105 | set->connectors[i]->encoder->crtc == set->crtc && |
9119 | set->connectors[i]->encoder->crtc == set->crtc && |
9106 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
9120 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
9107 | return true; |
9121 | return true; |
9108 | 9122 | ||
9109 | return false; |
9123 | return false; |
9110 | } |
9124 | } |
9111 | 9125 | ||
9112 | static void |
9126 | static void |
9113 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
9127 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
9114 | struct intel_set_config *config) |
9128 | struct intel_set_config *config) |
9115 | { |
9129 | { |
9116 | 9130 | ||
9117 | /* We should be able to check here if the fb has the same properties |
9131 | /* We should be able to check here if the fb has the same properties |
9118 | * and then just flip_or_move it */ |
9132 | * and then just flip_or_move it */ |
9119 | if (is_crtc_connector_off(set)) { |
9133 | if (is_crtc_connector_off(set)) { |
9120 | config->mode_changed = true; |
9134 | config->mode_changed = true; |
9121 | } else if (set->crtc->fb != set->fb) { |
9135 | } else if (set->crtc->fb != set->fb) { |
9122 | /* If we have no fb then treat it as a full mode set */ |
9136 | /* If we have no fb then treat it as a full mode set */ |
9123 | if (set->crtc->fb == NULL) { |
9137 | if (set->crtc->fb == NULL) { |
9124 | struct intel_crtc *intel_crtc = |
9138 | struct intel_crtc *intel_crtc = |
9125 | to_intel_crtc(set->crtc); |
9139 | to_intel_crtc(set->crtc); |
9126 | 9140 | ||
9127 | if (intel_crtc->active && i915_fastboot) { |
9141 | if (intel_crtc->active && i915_fastboot) { |
9128 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9142 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9129 | config->fb_changed = true; |
9143 | config->fb_changed = true; |
9130 | } else { |
9144 | } else { |
9131 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9145 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9132 | config->mode_changed = true; |
9146 | config->mode_changed = true; |
9133 | } |
9147 | } |
9134 | } else if (set->fb == NULL) { |
9148 | } else if (set->fb == NULL) { |
9135 | config->mode_changed = true; |
9149 | config->mode_changed = true; |
9136 | } else if (set->fb->pixel_format != |
9150 | } else if (set->fb->pixel_format != |
9137 | set->crtc->fb->pixel_format) { |
9151 | set->crtc->fb->pixel_format) { |
9138 | config->mode_changed = true; |
9152 | config->mode_changed = true; |
9139 | } else { |
9153 | } else { |
9140 | config->fb_changed = true; |
9154 | config->fb_changed = true; |
9141 | } |
9155 | } |
9142 | } |
9156 | } |
9143 | 9157 | ||
9144 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
9158 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
9145 | config->fb_changed = true; |
9159 | config->fb_changed = true; |
9146 | 9160 | ||
9147 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
9161 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
9148 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
9162 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
9149 | drm_mode_debug_printmodeline(&set->crtc->mode); |
9163 | drm_mode_debug_printmodeline(&set->crtc->mode); |
9150 | drm_mode_debug_printmodeline(set->mode); |
9164 | drm_mode_debug_printmodeline(set->mode); |
9151 | config->mode_changed = true; |
9165 | config->mode_changed = true; |
9152 | } |
9166 | } |
9153 | 9167 | ||
9154 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
9168 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
9155 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
9169 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
9156 | } |
9170 | } |
9157 | 9171 | ||
9158 | static int |
9172 | static int |
9159 | intel_modeset_stage_output_state(struct drm_device *dev, |
9173 | intel_modeset_stage_output_state(struct drm_device *dev, |
9160 | struct drm_mode_set *set, |
9174 | struct drm_mode_set *set, |
9161 | struct intel_set_config *config) |
9175 | struct intel_set_config *config) |
9162 | { |
9176 | { |
9163 | struct drm_crtc *new_crtc; |
9177 | struct drm_crtc *new_crtc; |
9164 | struct intel_connector *connector; |
9178 | struct intel_connector *connector; |
9165 | struct intel_encoder *encoder; |
9179 | struct intel_encoder *encoder; |
9166 | int ro; |
9180 | int ro; |
9167 | 9181 | ||
9168 | /* The upper layers ensure that we either disable a crtc or have a list |
9182 | /* The upper layers ensure that we either disable a crtc or have a list |
9169 | * of connectors. For paranoia, double-check this. */ |
9183 | * of connectors. For paranoia, double-check this. */ |
9170 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
9184 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
9171 | WARN_ON(set->fb && (set->num_connectors == 0)); |
9185 | WARN_ON(set->fb && (set->num_connectors == 0)); |
9172 | 9186 | ||
9173 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9187 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9174 | base.head) { |
9188 | base.head) { |
9175 | /* Otherwise traverse passed in connector list and get encoders |
9189 | /* Otherwise traverse passed in connector list and get encoders |
9176 | * for them. */ |
9190 | * for them. */ |
9177 | for (ro = 0; ro < set->num_connectors; ro++) { |
9191 | for (ro = 0; ro < set->num_connectors; ro++) { |
9178 | if (set->connectors[ro] == &connector->base) { |
9192 | if (set->connectors[ro] == &connector->base) { |
9179 | connector->new_encoder = connector->encoder; |
9193 | connector->new_encoder = connector->encoder; |
9180 | break; |
9194 | break; |
9181 | } |
9195 | } |
9182 | } |
9196 | } |
9183 | 9197 | ||
9184 | /* If we disable the crtc, disable all its connectors. Also, if |
9198 | /* If we disable the crtc, disable all its connectors. Also, if |
9185 | * the connector is on the changing crtc but not on the new |
9199 | * the connector is on the changing crtc but not on the new |
9186 | * connector list, disable it. */ |
9200 | * connector list, disable it. */ |
9187 | if ((!set->fb || ro == set->num_connectors) && |
9201 | if ((!set->fb || ro == set->num_connectors) && |
9188 | connector->base.encoder && |
9202 | connector->base.encoder && |
9189 | connector->base.encoder->crtc == set->crtc) { |
9203 | connector->base.encoder->crtc == set->crtc) { |
9190 | connector->new_encoder = NULL; |
9204 | connector->new_encoder = NULL; |
9191 | 9205 | ||
9192 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9206 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9193 | connector->base.base.id, |
9207 | connector->base.base.id, |
9194 | drm_get_connector_name(&connector->base)); |
9208 | drm_get_connector_name(&connector->base)); |
9195 | } |
9209 | } |
9196 | 9210 | ||
9197 | 9211 | ||
9198 | if (&connector->new_encoder->base != connector->base.encoder) { |
9212 | if (&connector->new_encoder->base != connector->base.encoder) { |
9199 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
9213 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
9200 | config->mode_changed = true; |
9214 | config->mode_changed = true; |
9201 | } |
9215 | } |
9202 | } |
9216 | } |
9203 | /* connector->new_encoder is now updated for all connectors. */ |
9217 | /* connector->new_encoder is now updated for all connectors. */ |
9204 | 9218 | ||
9205 | /* Update crtc of enabled connectors. */ |
9219 | /* Update crtc of enabled connectors. */ |
9206 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9220 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9207 | base.head) { |
9221 | base.head) { |
9208 | if (!connector->new_encoder) |
9222 | if (!connector->new_encoder) |
9209 | continue; |
9223 | continue; |
9210 | 9224 | ||
9211 | new_crtc = connector->new_encoder->base.crtc; |
9225 | new_crtc = connector->new_encoder->base.crtc; |
9212 | 9226 | ||
9213 | for (ro = 0; ro < set->num_connectors; ro++) { |
9227 | for (ro = 0; ro < set->num_connectors; ro++) { |
9214 | if (set->connectors[ro] == &connector->base) |
9228 | if (set->connectors[ro] == &connector->base) |
9215 | new_crtc = set->crtc; |
9229 | new_crtc = set->crtc; |
9216 | } |
9230 | } |
9217 | 9231 | ||
9218 | /* Make sure the new CRTC will work with the encoder */ |
9232 | /* Make sure the new CRTC will work with the encoder */ |
9219 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9233 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9220 | new_crtc)) { |
9234 | new_crtc)) { |
9221 | return -EINVAL; |
9235 | return -EINVAL; |
9222 | } |
9236 | } |
9223 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9237 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9224 | 9238 | ||
9225 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9239 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9226 | connector->base.base.id, |
9240 | connector->base.base.id, |
9227 | drm_get_connector_name(&connector->base), |
9241 | drm_get_connector_name(&connector->base), |
9228 | new_crtc->base.id); |
9242 | new_crtc->base.id); |
9229 | } |
9243 | } |
9230 | 9244 | ||
9231 | /* Check for any encoders that needs to be disabled. */ |
9245 | /* Check for any encoders that needs to be disabled. */ |
9232 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9246 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9233 | base.head) { |
9247 | base.head) { |
9234 | list_for_each_entry(connector, |
9248 | list_for_each_entry(connector, |
9235 | &dev->mode_config.connector_list, |
9249 | &dev->mode_config.connector_list, |
9236 | base.head) { |
9250 | base.head) { |
9237 | if (connector->new_encoder == encoder) { |
9251 | if (connector->new_encoder == encoder) { |
9238 | WARN_ON(!connector->new_encoder->new_crtc); |
9252 | WARN_ON(!connector->new_encoder->new_crtc); |
9239 | 9253 | ||
9240 | goto next_encoder; |
9254 | goto next_encoder; |
9241 | } |
9255 | } |
9242 | } |
9256 | } |
9243 | encoder->new_crtc = NULL; |
9257 | encoder->new_crtc = NULL; |
9244 | next_encoder: |
9258 | next_encoder: |
9245 | /* Only now check for crtc changes so we don't miss encoders |
9259 | /* Only now check for crtc changes so we don't miss encoders |
9246 | * that will be disabled. */ |
9260 | * that will be disabled. */ |
9247 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9261 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9248 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9262 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9249 | config->mode_changed = true; |
9263 | config->mode_changed = true; |
9250 | } |
9264 | } |
9251 | } |
9265 | } |
9252 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
9266 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
9253 | 9267 | ||
9254 | return 0; |
9268 | return 0; |
9255 | } |
9269 | } |
9256 | 9270 | ||
9257 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9271 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9258 | { |
9272 | { |
9259 | struct drm_device *dev; |
9273 | struct drm_device *dev; |
9260 | struct drm_mode_set save_set; |
9274 | struct drm_mode_set save_set; |
9261 | struct intel_set_config *config; |
9275 | struct intel_set_config *config; |
9262 | int ret; |
9276 | int ret; |
9263 | 9277 | ||
9264 | BUG_ON(!set); |
9278 | BUG_ON(!set); |
9265 | BUG_ON(!set->crtc); |
9279 | BUG_ON(!set->crtc); |
9266 | BUG_ON(!set->crtc->helper_private); |
9280 | BUG_ON(!set->crtc->helper_private); |
9267 | 9281 | ||
9268 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9282 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9269 | BUG_ON(!set->mode && set->fb); |
9283 | BUG_ON(!set->mode && set->fb); |
9270 | BUG_ON(set->fb && set->num_connectors == 0); |
9284 | BUG_ON(set->fb && set->num_connectors == 0); |
9271 | 9285 | ||
9272 | if (set->fb) { |
9286 | if (set->fb) { |
9273 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
9287 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
9274 | set->crtc->base.id, set->fb->base.id, |
9288 | set->crtc->base.id, set->fb->base.id, |
9275 | (int)set->num_connectors, set->x, set->y); |
9289 | (int)set->num_connectors, set->x, set->y); |
9276 | } else { |
9290 | } else { |
9277 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
9291 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
9278 | } |
9292 | } |
9279 | 9293 | ||
9280 | dev = set->crtc->dev; |
9294 | dev = set->crtc->dev; |
9281 | 9295 | ||
9282 | ret = -ENOMEM; |
9296 | ret = -ENOMEM; |
9283 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
9297 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
9284 | if (!config) |
9298 | if (!config) |
9285 | goto out_config; |
9299 | goto out_config; |
9286 | 9300 | ||
9287 | ret = intel_set_config_save_state(dev, config); |
9301 | ret = intel_set_config_save_state(dev, config); |
9288 | if (ret) |
9302 | if (ret) |
9289 | goto out_config; |
9303 | goto out_config; |
9290 | 9304 | ||
9291 | save_set.crtc = set->crtc; |
9305 | save_set.crtc = set->crtc; |
9292 | save_set.mode = &set->crtc->mode; |
9306 | save_set.mode = &set->crtc->mode; |
9293 | save_set.x = set->crtc->x; |
9307 | save_set.x = set->crtc->x; |
9294 | save_set.y = set->crtc->y; |
9308 | save_set.y = set->crtc->y; |
9295 | save_set.fb = set->crtc->fb; |
9309 | save_set.fb = set->crtc->fb; |
9296 | 9310 | ||
9297 | /* Compute whether we need a full modeset, only an fb base update or no |
9311 | /* Compute whether we need a full modeset, only an fb base update or no |
9298 | * change at all. In the future we might also check whether only the |
9312 | * change at all. In the future we might also check whether only the |
9299 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
9313 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
9300 | * such cases. */ |
9314 | * such cases. */ |
9301 | intel_set_config_compute_mode_changes(set, config); |
9315 | intel_set_config_compute_mode_changes(set, config); |
9302 | 9316 | ||
9303 | ret = intel_modeset_stage_output_state(dev, set, config); |
9317 | ret = intel_modeset_stage_output_state(dev, set, config); |
9304 | if (ret) |
9318 | if (ret) |
9305 | goto fail; |
9319 | goto fail; |
9306 | 9320 | ||
9307 | if (config->mode_changed) { |
9321 | if (config->mode_changed) { |
9308 | ret = intel_set_mode(set->crtc, set->mode, |
9322 | ret = intel_set_mode(set->crtc, set->mode, |
9309 | set->x, set->y, set->fb); |
9323 | set->x, set->y, set->fb); |
9310 | } else if (config->fb_changed) { |
9324 | } else if (config->fb_changed) { |
9311 | // intel_crtc_wait_for_pending_flips(set->crtc); |
9325 | // intel_crtc_wait_for_pending_flips(set->crtc); |
9312 | 9326 | ||
9313 | ret = intel_pipe_set_base(set->crtc, |
9327 | ret = intel_pipe_set_base(set->crtc, |
9314 | set->x, set->y, set->fb); |
9328 | set->x, set->y, set->fb); |
9315 | } |
9329 | } |
9316 | 9330 | ||
9317 | if (ret) { |
9331 | if (ret) { |
9318 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9332 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9319 | set->crtc->base.id, ret); |
9333 | set->crtc->base.id, ret); |
9320 | fail: |
9334 | fail: |
9321 | intel_set_config_restore_state(dev, config); |
9335 | intel_set_config_restore_state(dev, config); |
9322 | 9336 | ||
9323 | /* Try to restore the config */ |
9337 | /* Try to restore the config */ |
9324 | if (config->mode_changed && |
9338 | if (config->mode_changed && |
9325 | intel_set_mode(save_set.crtc, save_set.mode, |
9339 | intel_set_mode(save_set.crtc, save_set.mode, |
9326 | save_set.x, save_set.y, save_set.fb)) |
9340 | save_set.x, save_set.y, save_set.fb)) |
9327 | DRM_ERROR("failed to restore config after modeset failure\n"); |
9341 | DRM_ERROR("failed to restore config after modeset failure\n"); |
9328 | } |
9342 | } |
9329 | 9343 | ||
9330 | out_config: |
9344 | out_config: |
9331 | intel_set_config_free(config); |
9345 | intel_set_config_free(config); |
9332 | return ret; |
9346 | return ret; |
9333 | } |
9347 | } |
9334 | 9348 | ||
9335 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
9349 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
9336 | // .cursor_set = intel_crtc_cursor_set, |
9350 | // .cursor_set = intel_crtc_cursor_set, |
9337 | // .cursor_move = intel_crtc_cursor_move, |
9351 | // .cursor_move = intel_crtc_cursor_move, |
9338 | .gamma_set = intel_crtc_gamma_set, |
9352 | .gamma_set = intel_crtc_gamma_set, |
9339 | .set_config = intel_crtc_set_config, |
9353 | .set_config = intel_crtc_set_config, |
9340 | .destroy = intel_crtc_destroy, |
9354 | .destroy = intel_crtc_destroy, |
9341 | // .page_flip = intel_crtc_page_flip, |
9355 | // .page_flip = intel_crtc_page_flip, |
9342 | }; |
9356 | }; |
9343 | 9357 | ||
9344 | static void intel_cpu_pll_init(struct drm_device *dev) |
9358 | static void intel_cpu_pll_init(struct drm_device *dev) |
9345 | { |
9359 | { |
9346 | if (HAS_DDI(dev)) |
9360 | if (HAS_DDI(dev)) |
9347 | intel_ddi_pll_init(dev); |
9361 | intel_ddi_pll_init(dev); |
9348 | } |
9362 | } |
9349 | 9363 | ||
9350 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9364 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9351 | struct intel_shared_dpll *pll, |
9365 | struct intel_shared_dpll *pll, |
9352 | struct intel_dpll_hw_state *hw_state) |
9366 | struct intel_dpll_hw_state *hw_state) |
9353 | { |
9367 | { |
9354 | uint32_t val; |
9368 | uint32_t val; |
9355 | 9369 | ||
9356 | val = I915_READ(PCH_DPLL(pll->id)); |
9370 | val = I915_READ(PCH_DPLL(pll->id)); |
9357 | hw_state->dpll = val; |
9371 | hw_state->dpll = val; |
9358 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
9372 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
9359 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
9373 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
9360 | 9374 | ||
9361 | return val & DPLL_VCO_ENABLE; |
9375 | return val & DPLL_VCO_ENABLE; |
9362 | } |
9376 | } |
9363 | 9377 | ||
9364 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9378 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9365 | struct intel_shared_dpll *pll) |
9379 | struct intel_shared_dpll *pll) |
9366 | { |
9380 | { |
9367 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
9381 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
9368 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
9382 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
9369 | } |
9383 | } |
9370 | 9384 | ||
9371 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9385 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9372 | struct intel_shared_dpll *pll) |
9386 | struct intel_shared_dpll *pll) |
9373 | { |
9387 | { |
9374 | /* PCH refclock must be enabled first */ |
9388 | /* PCH refclock must be enabled first */ |
9375 | assert_pch_refclk_enabled(dev_priv); |
9389 | assert_pch_refclk_enabled(dev_priv); |
9376 | 9390 | ||
9377 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9391 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9378 | 9392 | ||
9379 | /* Wait for the clocks to stabilize. */ |
9393 | /* Wait for the clocks to stabilize. */ |
9380 | POSTING_READ(PCH_DPLL(pll->id)); |
9394 | POSTING_READ(PCH_DPLL(pll->id)); |
9381 | udelay(150); |
9395 | udelay(150); |
9382 | 9396 | ||
9383 | /* The pixel multiplier can only be updated once the |
9397 | /* The pixel multiplier can only be updated once the |
9384 | * DPLL is enabled and the clocks are stable. |
9398 | * DPLL is enabled and the clocks are stable. |
9385 | * |
9399 | * |
9386 | * So write it again. |
9400 | * So write it again. |
9387 | */ |
9401 | */ |
9388 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9402 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9389 | POSTING_READ(PCH_DPLL(pll->id)); |
9403 | POSTING_READ(PCH_DPLL(pll->id)); |
9390 | udelay(200); |
9404 | udelay(200); |
9391 | } |
9405 | } |
9392 | 9406 | ||
9393 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
9407 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
9394 | struct intel_shared_dpll *pll) |
9408 | struct intel_shared_dpll *pll) |
9395 | { |
9409 | { |
9396 | struct drm_device *dev = dev_priv->dev; |
9410 | struct drm_device *dev = dev_priv->dev; |
9397 | struct intel_crtc *crtc; |
9411 | struct intel_crtc *crtc; |
9398 | 9412 | ||
9399 | /* Make sure no transcoder isn't still depending on us. */ |
9413 | /* Make sure no transcoder isn't still depending on us. */ |
9400 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
9414 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
9401 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
9415 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
9402 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
9416 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
9403 | } |
9417 | } |
9404 | 9418 | ||
9405 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9419 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9406 | POSTING_READ(PCH_DPLL(pll->id)); |
9420 | POSTING_READ(PCH_DPLL(pll->id)); |
9407 | udelay(200); |
9421 | udelay(200); |
9408 | } |
9422 | } |
9409 | 9423 | ||
9410 | static char *ibx_pch_dpll_names[] = { |
9424 | static char *ibx_pch_dpll_names[] = { |
9411 | "PCH DPLL A", |
9425 | "PCH DPLL A", |
9412 | "PCH DPLL B", |
9426 | "PCH DPLL B", |
9413 | }; |
9427 | }; |
9414 | 9428 | ||
9415 | static void ibx_pch_dpll_init(struct drm_device *dev) |
9429 | static void ibx_pch_dpll_init(struct drm_device *dev) |
9416 | { |
9430 | { |
9417 | struct drm_i915_private *dev_priv = dev->dev_private; |
9431 | struct drm_i915_private *dev_priv = dev->dev_private; |
9418 | int i; |
9432 | int i; |
9419 | 9433 | ||
9420 | dev_priv->num_shared_dpll = 2; |
9434 | dev_priv->num_shared_dpll = 2; |
9421 | 9435 | ||
9422 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9436 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9423 | dev_priv->shared_dplls[i].id = i; |
9437 | dev_priv->shared_dplls[i].id = i; |
9424 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
9438 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
9425 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
9439 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
9426 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9440 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9427 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
9441 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
9428 | dev_priv->shared_dplls[i].get_hw_state = |
9442 | dev_priv->shared_dplls[i].get_hw_state = |
9429 | ibx_pch_dpll_get_hw_state; |
9443 | ibx_pch_dpll_get_hw_state; |
9430 | } |
9444 | } |
9431 | } |
9445 | } |
9432 | 9446 | ||
9433 | static void intel_shared_dpll_init(struct drm_device *dev) |
9447 | static void intel_shared_dpll_init(struct drm_device *dev) |
9434 | { |
9448 | { |
9435 | struct drm_i915_private *dev_priv = dev->dev_private; |
9449 | struct drm_i915_private *dev_priv = dev->dev_private; |
9436 | 9450 | ||
9437 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9451 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9438 | ibx_pch_dpll_init(dev); |
9452 | ibx_pch_dpll_init(dev); |
9439 | else |
9453 | else |
9440 | dev_priv->num_shared_dpll = 0; |
9454 | dev_priv->num_shared_dpll = 0; |
9441 | 9455 | ||
9442 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
9456 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
9443 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
9457 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
9444 | dev_priv->num_shared_dpll); |
9458 | dev_priv->num_shared_dpll); |
9445 | } |
9459 | } |
9446 | 9460 | ||
9447 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9461 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9448 | { |
9462 | { |
9449 | drm_i915_private_t *dev_priv = dev->dev_private; |
9463 | drm_i915_private_t *dev_priv = dev->dev_private; |
9450 | struct intel_crtc *intel_crtc; |
9464 | struct intel_crtc *intel_crtc; |
9451 | int i; |
9465 | int i; |
9452 | 9466 | ||
9453 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
9467 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
9454 | if (intel_crtc == NULL) |
9468 | if (intel_crtc == NULL) |
9455 | return; |
9469 | return; |
9456 | 9470 | ||
9457 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
9471 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
9458 | 9472 | ||
9459 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
9473 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
9460 | for (i = 0; i < 256; i++) { |
9474 | for (i = 0; i < 256; i++) { |
9461 | intel_crtc->lut_r[i] = i; |
9475 | intel_crtc->lut_r[i] = i; |
9462 | intel_crtc->lut_g[i] = i; |
9476 | intel_crtc->lut_g[i] = i; |
9463 | intel_crtc->lut_b[i] = i; |
9477 | intel_crtc->lut_b[i] = i; |
9464 | } |
9478 | } |
9465 | 9479 | ||
9466 | /* Swap pipes & planes for FBC on pre-965 */ |
9480 | /* Swap pipes & planes for FBC on pre-965 */ |
9467 | intel_crtc->pipe = pipe; |
9481 | intel_crtc->pipe = pipe; |
9468 | intel_crtc->plane = pipe; |
9482 | intel_crtc->plane = pipe; |
9469 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
9483 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
9470 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
9484 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
9471 | intel_crtc->plane = !pipe; |
9485 | intel_crtc->plane = !pipe; |
9472 | } |
9486 | } |
9473 | 9487 | ||
9474 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9488 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9475 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
9489 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
9476 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
9490 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
9477 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
9491 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
9478 | 9492 | ||
9479 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
9493 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
9480 | } |
9494 | } |
9481 | 9495 | ||
9482 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9496 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9483 | struct drm_file *file) |
9497 | struct drm_file *file) |
9484 | { |
9498 | { |
9485 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
9499 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
9486 | struct drm_mode_object *drmmode_obj; |
9500 | struct drm_mode_object *drmmode_obj; |
9487 | struct intel_crtc *crtc; |
9501 | struct intel_crtc *crtc; |
9488 | 9502 | ||
9489 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9503 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9490 | return -ENODEV; |
9504 | return -ENODEV; |
9491 | 9505 | ||
9492 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9506 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9493 | DRM_MODE_OBJECT_CRTC); |
9507 | DRM_MODE_OBJECT_CRTC); |
9494 | 9508 | ||
9495 | if (!drmmode_obj) { |
9509 | if (!drmmode_obj) { |
9496 | DRM_ERROR("no such CRTC id\n"); |
9510 | DRM_ERROR("no such CRTC id\n"); |
9497 | return -EINVAL; |
9511 | return -EINVAL; |
9498 | } |
9512 | } |
9499 | 9513 | ||
9500 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9514 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9501 | pipe_from_crtc_id->pipe = crtc->pipe; |
9515 | pipe_from_crtc_id->pipe = crtc->pipe; |
9502 | 9516 | ||
9503 | return 0; |
9517 | return 0; |
9504 | } |
9518 | } |
9505 | 9519 | ||
9506 | static int intel_encoder_clones(struct intel_encoder *encoder) |
9520 | static int intel_encoder_clones(struct intel_encoder *encoder) |
9507 | { |
9521 | { |
9508 | struct drm_device *dev = encoder->base.dev; |
9522 | struct drm_device *dev = encoder->base.dev; |
9509 | struct intel_encoder *source_encoder; |
9523 | struct intel_encoder *source_encoder; |
9510 | int index_mask = 0; |
9524 | int index_mask = 0; |
9511 | int entry = 0; |
9525 | int entry = 0; |
9512 | 9526 | ||
9513 | list_for_each_entry(source_encoder, |
9527 | list_for_each_entry(source_encoder, |
9514 | &dev->mode_config.encoder_list, base.head) { |
9528 | &dev->mode_config.encoder_list, base.head) { |
9515 | 9529 | ||
9516 | if (encoder == source_encoder) |
9530 | if (encoder == source_encoder) |
9517 | index_mask |= (1 << entry); |
9531 | index_mask |= (1 << entry); |
9518 | 9532 | ||
9519 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
9533 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
9520 | if (encoder->cloneable && source_encoder->cloneable) |
9534 | if (encoder->cloneable && source_encoder->cloneable) |
9521 | index_mask |= (1 << entry); |
9535 | index_mask |= (1 << entry); |
9522 | 9536 | ||
9523 | entry++; |
9537 | entry++; |
9524 | } |
9538 | } |
9525 | 9539 | ||
9526 | return index_mask; |
9540 | return index_mask; |
9527 | } |
9541 | } |
9528 | 9542 | ||
9529 | static bool has_edp_a(struct drm_device *dev) |
9543 | static bool has_edp_a(struct drm_device *dev) |
9530 | { |
9544 | { |
9531 | struct drm_i915_private *dev_priv = dev->dev_private; |
9545 | struct drm_i915_private *dev_priv = dev->dev_private; |
9532 | 9546 | ||
9533 | if (!IS_MOBILE(dev)) |
9547 | if (!IS_MOBILE(dev)) |
9534 | return false; |
9548 | return false; |
9535 | 9549 | ||
9536 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
9550 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
9537 | return false; |
9551 | return false; |
9538 | 9552 | ||
9539 | if (IS_GEN5(dev) && |
9553 | if (IS_GEN5(dev) && |
9540 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
9554 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
9541 | return false; |
9555 | return false; |
9542 | 9556 | ||
9543 | return true; |
9557 | return true; |
9544 | } |
9558 | } |
9545 | 9559 | ||
9546 | static void intel_setup_outputs(struct drm_device *dev) |
9560 | static void intel_setup_outputs(struct drm_device *dev) |
9547 | { |
9561 | { |
9548 | struct drm_i915_private *dev_priv = dev->dev_private; |
9562 | struct drm_i915_private *dev_priv = dev->dev_private; |
9549 | struct intel_encoder *encoder; |
9563 | struct intel_encoder *encoder; |
9550 | bool dpd_is_edp = false; |
9564 | bool dpd_is_edp = false; |
9551 | 9565 | ||
9552 | intel_lvds_init(dev); |
9566 | intel_lvds_init(dev); |
9553 | 9567 | ||
9554 | if (!IS_ULT(dev)) |
9568 | if (!IS_ULT(dev)) |
9555 | intel_crt_init(dev); |
9569 | intel_crt_init(dev); |
9556 | 9570 | ||
9557 | if (HAS_DDI(dev)) { |
9571 | if (HAS_DDI(dev)) { |
9558 | int found; |
9572 | int found; |
9559 | 9573 | ||
9560 | /* Haswell uses DDI functions to detect digital outputs */ |
9574 | /* Haswell uses DDI functions to detect digital outputs */ |
9561 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
9575 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
9562 | /* DDI A only supports eDP */ |
9576 | /* DDI A only supports eDP */ |
9563 | if (found) |
9577 | if (found) |
9564 | intel_ddi_init(dev, PORT_A); |
9578 | intel_ddi_init(dev, PORT_A); |
9565 | 9579 | ||
9566 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
9580 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
9567 | * register */ |
9581 | * register */ |
9568 | found = I915_READ(SFUSE_STRAP); |
9582 | found = I915_READ(SFUSE_STRAP); |
9569 | 9583 | ||
9570 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
9584 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
9571 | intel_ddi_init(dev, PORT_B); |
9585 | intel_ddi_init(dev, PORT_B); |
9572 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
9586 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
9573 | intel_ddi_init(dev, PORT_C); |
9587 | intel_ddi_init(dev, PORT_C); |
9574 | if (found & SFUSE_STRAP_DDID_DETECTED) |
9588 | if (found & SFUSE_STRAP_DDID_DETECTED) |
9575 | intel_ddi_init(dev, PORT_D); |
9589 | intel_ddi_init(dev, PORT_D); |
9576 | } else if (HAS_PCH_SPLIT(dev)) { |
9590 | } else if (HAS_PCH_SPLIT(dev)) { |
9577 | int found; |
9591 | int found; |
9578 | dpd_is_edp = intel_dpd_is_edp(dev); |
9592 | dpd_is_edp = intel_dpd_is_edp(dev); |
9579 | 9593 | ||
9580 | if (has_edp_a(dev)) |
9594 | if (has_edp_a(dev)) |
9581 | intel_dp_init(dev, DP_A, PORT_A); |
9595 | intel_dp_init(dev, DP_A, PORT_A); |
9582 | 9596 | ||
9583 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
9597 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
9584 | /* PCH SDVOB multiplex with HDMIB */ |
9598 | /* PCH SDVOB multiplex with HDMIB */ |
9585 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
9599 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
9586 | if (!found) |
9600 | if (!found) |
9587 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
9601 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
9588 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
9602 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
9589 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
9603 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
9590 | } |
9604 | } |
9591 | 9605 | ||
9592 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
9606 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
9593 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
9607 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
9594 | 9608 | ||
9595 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
9609 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
9596 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
9610 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
9597 | 9611 | ||
9598 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
9612 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
9599 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
9613 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
9600 | 9614 | ||
9601 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
9615 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
9602 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9616 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9603 | } else if (IS_VALLEYVIEW(dev)) { |
9617 | } else if (IS_VALLEYVIEW(dev)) { |
9604 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
9618 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
9605 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9619 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9606 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
9620 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
9607 | PORT_C); |
9621 | PORT_C); |
9608 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
9622 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
9609 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
9623 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
9610 | PORT_C); |
9624 | PORT_C); |
9611 | } |
9625 | } |
9612 | 9626 | ||
9613 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9627 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9614 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9628 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9615 | PORT_B); |
9629 | PORT_B); |
9616 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9630 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9617 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
9631 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
9618 | } |
9632 | } |
9619 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
9633 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
9620 | bool found = false; |
9634 | bool found = false; |
9621 | 9635 | ||
9622 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9636 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9623 | DRM_DEBUG_KMS("probing SDVOB\n"); |
9637 | DRM_DEBUG_KMS("probing SDVOB\n"); |
9624 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
9638 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
9625 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9639 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9626 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
9640 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
9627 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
9641 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
9628 | } |
9642 | } |
9629 | 9643 | ||
9630 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
9644 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
9631 | intel_dp_init(dev, DP_B, PORT_B); |
9645 | intel_dp_init(dev, DP_B, PORT_B); |
9632 | } |
9646 | } |
9633 | 9647 | ||
9634 | /* Before G4X SDVOC doesn't have its own detect register */ |
9648 | /* Before G4X SDVOC doesn't have its own detect register */ |
9635 | 9649 | ||
9636 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9650 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9637 | DRM_DEBUG_KMS("probing SDVOC\n"); |
9651 | DRM_DEBUG_KMS("probing SDVOC\n"); |
9638 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
9652 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
9639 | } |
9653 | } |
9640 | 9654 | ||
9641 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
9655 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
9642 | 9656 | ||
9643 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9657 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9644 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
9658 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
9645 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
9659 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
9646 | } |
9660 | } |
9647 | if (SUPPORTS_INTEGRATED_DP(dev)) |
9661 | if (SUPPORTS_INTEGRATED_DP(dev)) |
9648 | intel_dp_init(dev, DP_C, PORT_C); |
9662 | intel_dp_init(dev, DP_C, PORT_C); |
9649 | } |
9663 | } |
9650 | 9664 | ||
9651 | if (SUPPORTS_INTEGRATED_DP(dev) && |
9665 | if (SUPPORTS_INTEGRATED_DP(dev) && |
9652 | (I915_READ(DP_D) & DP_DETECTED)) |
9666 | (I915_READ(DP_D) & DP_DETECTED)) |
9653 | intel_dp_init(dev, DP_D, PORT_D); |
9667 | intel_dp_init(dev, DP_D, PORT_D); |
9654 | } else if (IS_GEN2(dev)) |
9668 | } else if (IS_GEN2(dev)) |
9655 | intel_dvo_init(dev); |
9669 | intel_dvo_init(dev); |
9656 | 9670 | ||
9657 | // if (SUPPORTS_TV(dev)) |
9671 | // if (SUPPORTS_TV(dev)) |
9658 | // intel_tv_init(dev); |
9672 | // intel_tv_init(dev); |
9659 | 9673 | ||
9660 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9674 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9661 | encoder->base.possible_crtcs = encoder->crtc_mask; |
9675 | encoder->base.possible_crtcs = encoder->crtc_mask; |
9662 | encoder->base.possible_clones = |
9676 | encoder->base.possible_clones = |
9663 | intel_encoder_clones(encoder); |
9677 | intel_encoder_clones(encoder); |
9664 | } |
9678 | } |
9665 | 9679 | ||
9666 | intel_init_pch_refclk(dev); |
9680 | intel_init_pch_refclk(dev); |
9667 | 9681 | ||
9668 | drm_helper_move_panel_connectors_to_head(dev); |
9682 | drm_helper_move_panel_connectors_to_head(dev); |
9669 | } |
9683 | } |
9670 | 9684 | ||
9671 | 9685 | ||
9672 | 9686 | ||
9673 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
9687 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
9674 | // .destroy = intel_user_framebuffer_destroy, |
9688 | // .destroy = intel_user_framebuffer_destroy, |
9675 | // .create_handle = intel_user_framebuffer_create_handle, |
9689 | // .create_handle = intel_user_framebuffer_create_handle, |
9676 | }; |
9690 | }; |
9677 | 9691 | ||
9678 | int intel_framebuffer_init(struct drm_device *dev, |
9692 | int intel_framebuffer_init(struct drm_device *dev, |
9679 | struct intel_framebuffer *intel_fb, |
9693 | struct intel_framebuffer *intel_fb, |
9680 | struct drm_mode_fb_cmd2 *mode_cmd, |
9694 | struct drm_mode_fb_cmd2 *mode_cmd, |
9681 | struct drm_i915_gem_object *obj) |
9695 | struct drm_i915_gem_object *obj) |
9682 | { |
9696 | { |
9683 | int pitch_limit; |
9697 | int pitch_limit; |
9684 | int ret; |
9698 | int ret; |
9685 | 9699 | ||
9686 | if (obj->tiling_mode == I915_TILING_Y) { |
9700 | if (obj->tiling_mode == I915_TILING_Y) { |
9687 | DRM_DEBUG("hardware does not support tiling Y\n"); |
9701 | DRM_DEBUG("hardware does not support tiling Y\n"); |
9688 | return -EINVAL; |
9702 | return -EINVAL; |
9689 | } |
9703 | } |
9690 | 9704 | ||
9691 | if (mode_cmd->pitches[0] & 63) { |
9705 | if (mode_cmd->pitches[0] & 63) { |
9692 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
9706 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
9693 | mode_cmd->pitches[0]); |
9707 | mode_cmd->pitches[0]); |
9694 | return -EINVAL; |
9708 | return -EINVAL; |
9695 | } |
9709 | } |
9696 | 9710 | ||
9697 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9711 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9698 | pitch_limit = 32*1024; |
9712 | pitch_limit = 32*1024; |
9699 | } else if (INTEL_INFO(dev)->gen >= 4) { |
9713 | } else if (INTEL_INFO(dev)->gen >= 4) { |
9700 | if (obj->tiling_mode) |
9714 | if (obj->tiling_mode) |
9701 | pitch_limit = 16*1024; |
9715 | pitch_limit = 16*1024; |
9702 | else |
9716 | else |
9703 | pitch_limit = 32*1024; |
9717 | pitch_limit = 32*1024; |
9704 | } else if (INTEL_INFO(dev)->gen >= 3) { |
9718 | } else if (INTEL_INFO(dev)->gen >= 3) { |
9705 | if (obj->tiling_mode) |
9719 | if (obj->tiling_mode) |
9706 | pitch_limit = 8*1024; |
9720 | pitch_limit = 8*1024; |
9707 | else |
9721 | else |
9708 | pitch_limit = 16*1024; |
9722 | pitch_limit = 16*1024; |
9709 | } else |
9723 | } else |
9710 | /* XXX DSPC is limited to 4k tiled */ |
9724 | /* XXX DSPC is limited to 4k tiled */ |
9711 | pitch_limit = 8*1024; |
9725 | pitch_limit = 8*1024; |
9712 | 9726 | ||
9713 | if (mode_cmd->pitches[0] > pitch_limit) { |
9727 | if (mode_cmd->pitches[0] > pitch_limit) { |
9714 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
9728 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
9715 | obj->tiling_mode ? "tiled" : "linear", |
9729 | obj->tiling_mode ? "tiled" : "linear", |
9716 | mode_cmd->pitches[0], pitch_limit); |
9730 | mode_cmd->pitches[0], pitch_limit); |
9717 | return -EINVAL; |
9731 | return -EINVAL; |
9718 | } |
9732 | } |
9719 | 9733 | ||
9720 | if (obj->tiling_mode != I915_TILING_NONE && |
9734 | if (obj->tiling_mode != I915_TILING_NONE && |
9721 | mode_cmd->pitches[0] != obj->stride) { |
9735 | mode_cmd->pitches[0] != obj->stride) { |
9722 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
9736 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
9723 | mode_cmd->pitches[0], obj->stride); |
9737 | mode_cmd->pitches[0], obj->stride); |
9724 | return -EINVAL; |
9738 | return -EINVAL; |
9725 | } |
9739 | } |
9726 | 9740 | ||
9727 | /* Reject formats not supported by any plane early. */ |
9741 | /* Reject formats not supported by any plane early. */ |
9728 | switch (mode_cmd->pixel_format) { |
9742 | switch (mode_cmd->pixel_format) { |
9729 | case DRM_FORMAT_C8: |
9743 | case DRM_FORMAT_C8: |
9730 | case DRM_FORMAT_RGB565: |
9744 | case DRM_FORMAT_RGB565: |
9731 | case DRM_FORMAT_XRGB8888: |
9745 | case DRM_FORMAT_XRGB8888: |
9732 | case DRM_FORMAT_ARGB8888: |
9746 | case DRM_FORMAT_ARGB8888: |
9733 | break; |
9747 | break; |
9734 | case DRM_FORMAT_XRGB1555: |
9748 | case DRM_FORMAT_XRGB1555: |
9735 | case DRM_FORMAT_ARGB1555: |
9749 | case DRM_FORMAT_ARGB1555: |
9736 | if (INTEL_INFO(dev)->gen > 3) { |
9750 | if (INTEL_INFO(dev)->gen > 3) { |
9737 | DRM_DEBUG("unsupported pixel format: %s\n", |
9751 | DRM_DEBUG("unsupported pixel format: %s\n", |
9738 | drm_get_format_name(mode_cmd->pixel_format)); |
9752 | drm_get_format_name(mode_cmd->pixel_format)); |
9739 | return -EINVAL; |
9753 | return -EINVAL; |
9740 | } |
9754 | } |
9741 | break; |
9755 | break; |
9742 | case DRM_FORMAT_XBGR8888: |
9756 | case DRM_FORMAT_XBGR8888: |
9743 | case DRM_FORMAT_ABGR8888: |
9757 | case DRM_FORMAT_ABGR8888: |
9744 | case DRM_FORMAT_XRGB2101010: |
9758 | case DRM_FORMAT_XRGB2101010: |
9745 | case DRM_FORMAT_ARGB2101010: |
9759 | case DRM_FORMAT_ARGB2101010: |
9746 | case DRM_FORMAT_XBGR2101010: |
9760 | case DRM_FORMAT_XBGR2101010: |
9747 | case DRM_FORMAT_ABGR2101010: |
9761 | case DRM_FORMAT_ABGR2101010: |
9748 | if (INTEL_INFO(dev)->gen < 4) { |
9762 | if (INTEL_INFO(dev)->gen < 4) { |
9749 | DRM_DEBUG("unsupported pixel format: %s\n", |
9763 | DRM_DEBUG("unsupported pixel format: %s\n", |
9750 | drm_get_format_name(mode_cmd->pixel_format)); |
9764 | drm_get_format_name(mode_cmd->pixel_format)); |
9751 | return -EINVAL; |
9765 | return -EINVAL; |
9752 | } |
9766 | } |
9753 | break; |
9767 | break; |
9754 | case DRM_FORMAT_YUYV: |
9768 | case DRM_FORMAT_YUYV: |
9755 | case DRM_FORMAT_UYVY: |
9769 | case DRM_FORMAT_UYVY: |
9756 | case DRM_FORMAT_YVYU: |
9770 | case DRM_FORMAT_YVYU: |
9757 | case DRM_FORMAT_VYUY: |
9771 | case DRM_FORMAT_VYUY: |
9758 | if (INTEL_INFO(dev)->gen < 5) { |
9772 | if (INTEL_INFO(dev)->gen < 5) { |
9759 | DRM_DEBUG("unsupported pixel format: %s\n", |
9773 | DRM_DEBUG("unsupported pixel format: %s\n", |
9760 | drm_get_format_name(mode_cmd->pixel_format)); |
9774 | drm_get_format_name(mode_cmd->pixel_format)); |
9761 | return -EINVAL; |
9775 | return -EINVAL; |
9762 | } |
9776 | } |
9763 | break; |
9777 | break; |
9764 | default: |
9778 | default: |
9765 | DRM_DEBUG("unsupported pixel format: %s\n", |
9779 | DRM_DEBUG("unsupported pixel format: %s\n", |
9766 | drm_get_format_name(mode_cmd->pixel_format)); |
9780 | drm_get_format_name(mode_cmd->pixel_format)); |
9767 | return -EINVAL; |
9781 | return -EINVAL; |
9768 | } |
9782 | } |
9769 | 9783 | ||
9770 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9784 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9771 | if (mode_cmd->offsets[0] != 0) |
9785 | if (mode_cmd->offsets[0] != 0) |
9772 | return -EINVAL; |
9786 | return -EINVAL; |
9773 | 9787 | ||
9774 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9788 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9775 | intel_fb->obj = obj; |
9789 | intel_fb->obj = obj; |
9776 | 9790 | ||
9777 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9791 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9778 | if (ret) { |
9792 | if (ret) { |
9779 | DRM_ERROR("framebuffer init failed %d\n", ret); |
9793 | DRM_ERROR("framebuffer init failed %d\n", ret); |
9780 | return ret; |
9794 | return ret; |
9781 | } |
9795 | } |
9782 | 9796 | ||
9783 | return 0; |
9797 | return 0; |
9784 | } |
9798 | } |
9785 | 9799 | ||
9786 | 9800 | ||
9787 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
9801 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
9788 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
9802 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
9789 | .output_poll_changed = intel_fb_output_poll_changed, |
9803 | .output_poll_changed = intel_fb_output_poll_changed, |
9790 | }; |
9804 | }; |
9791 | 9805 | ||
9792 | /* Set up chip specific display functions */ |
9806 | /* Set up chip specific display functions */ |
9793 | static void intel_init_display(struct drm_device *dev) |
9807 | static void intel_init_display(struct drm_device *dev) |
9794 | { |
9808 | { |
9795 | struct drm_i915_private *dev_priv = dev->dev_private; |
9809 | struct drm_i915_private *dev_priv = dev->dev_private; |
9796 | 9810 | ||
9797 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9811 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9798 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
9812 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
9799 | else if (IS_VALLEYVIEW(dev)) |
9813 | else if (IS_VALLEYVIEW(dev)) |
9800 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
9814 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
9801 | else if (IS_PINEVIEW(dev)) |
9815 | else if (IS_PINEVIEW(dev)) |
9802 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
9816 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
9803 | else |
9817 | else |
9804 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
9818 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
9805 | 9819 | ||
9806 | if (HAS_DDI(dev)) { |
9820 | if (HAS_DDI(dev)) { |
9807 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
9821 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
9808 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
9822 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
9809 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9823 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9810 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
9824 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
9811 | dev_priv->display.off = haswell_crtc_off; |
9825 | dev_priv->display.off = haswell_crtc_off; |
9812 | dev_priv->display.update_plane = ironlake_update_plane; |
9826 | dev_priv->display.update_plane = ironlake_update_plane; |
9813 | } else if (HAS_PCH_SPLIT(dev)) { |
9827 | } else if (HAS_PCH_SPLIT(dev)) { |
9814 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
9828 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
9815 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
9829 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
9816 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9830 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9817 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9831 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9818 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9832 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9819 | dev_priv->display.off = ironlake_crtc_off; |
9833 | dev_priv->display.off = ironlake_crtc_off; |
9820 | dev_priv->display.update_plane = ironlake_update_plane; |
9834 | dev_priv->display.update_plane = ironlake_update_plane; |
9821 | } else if (IS_VALLEYVIEW(dev)) { |
9835 | } else if (IS_VALLEYVIEW(dev)) { |
9822 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9836 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9823 | dev_priv->display.get_clock = vlv_crtc_clock_get; |
9837 | dev_priv->display.get_clock = vlv_crtc_clock_get; |
9824 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9838 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9825 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9839 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9826 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9840 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9827 | dev_priv->display.off = i9xx_crtc_off; |
9841 | dev_priv->display.off = i9xx_crtc_off; |
9828 | dev_priv->display.update_plane = i9xx_update_plane; |
9842 | dev_priv->display.update_plane = i9xx_update_plane; |
9829 | } else { |
9843 | } else { |
9830 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9844 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9831 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9845 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9832 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9846 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9833 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9847 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9834 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9848 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9835 | dev_priv->display.off = i9xx_crtc_off; |
9849 | dev_priv->display.off = i9xx_crtc_off; |
9836 | dev_priv->display.update_plane = i9xx_update_plane; |
9850 | dev_priv->display.update_plane = i9xx_update_plane; |
9837 | } |
9851 | } |
9838 | 9852 | ||
9839 | /* Returns the core display clock speed */ |
9853 | /* Returns the core display clock speed */ |
9840 | if (IS_VALLEYVIEW(dev)) |
9854 | if (IS_VALLEYVIEW(dev)) |
9841 | dev_priv->display.get_display_clock_speed = |
9855 | dev_priv->display.get_display_clock_speed = |
9842 | valleyview_get_display_clock_speed; |
9856 | valleyview_get_display_clock_speed; |
9843 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
9857 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
9844 | dev_priv->display.get_display_clock_speed = |
9858 | dev_priv->display.get_display_clock_speed = |
9845 | i945_get_display_clock_speed; |
9859 | i945_get_display_clock_speed; |
9846 | else if (IS_I915G(dev)) |
9860 | else if (IS_I915G(dev)) |
9847 | dev_priv->display.get_display_clock_speed = |
9861 | dev_priv->display.get_display_clock_speed = |
9848 | i915_get_display_clock_speed; |
9862 | i915_get_display_clock_speed; |
9849 | else if (IS_I945GM(dev) || IS_845G(dev)) |
9863 | else if (IS_I945GM(dev) || IS_845G(dev)) |
9850 | dev_priv->display.get_display_clock_speed = |
9864 | dev_priv->display.get_display_clock_speed = |
9851 | i9xx_misc_get_display_clock_speed; |
9865 | i9xx_misc_get_display_clock_speed; |
9852 | else if (IS_PINEVIEW(dev)) |
9866 | else if (IS_PINEVIEW(dev)) |
9853 | dev_priv->display.get_display_clock_speed = |
9867 | dev_priv->display.get_display_clock_speed = |
9854 | pnv_get_display_clock_speed; |
9868 | pnv_get_display_clock_speed; |
9855 | else if (IS_I915GM(dev)) |
9869 | else if (IS_I915GM(dev)) |
9856 | dev_priv->display.get_display_clock_speed = |
9870 | dev_priv->display.get_display_clock_speed = |
9857 | i915gm_get_display_clock_speed; |
9871 | i915gm_get_display_clock_speed; |
9858 | else if (IS_I865G(dev)) |
9872 | else if (IS_I865G(dev)) |
9859 | dev_priv->display.get_display_clock_speed = |
9873 | dev_priv->display.get_display_clock_speed = |
9860 | i865_get_display_clock_speed; |
9874 | i865_get_display_clock_speed; |
9861 | else if (IS_I85X(dev)) |
9875 | else if (IS_I85X(dev)) |
9862 | dev_priv->display.get_display_clock_speed = |
9876 | dev_priv->display.get_display_clock_speed = |
9863 | i855_get_display_clock_speed; |
9877 | i855_get_display_clock_speed; |
9864 | else /* 852, 830 */ |
9878 | else /* 852, 830 */ |
9865 | dev_priv->display.get_display_clock_speed = |
9879 | dev_priv->display.get_display_clock_speed = |
9866 | i830_get_display_clock_speed; |
9880 | i830_get_display_clock_speed; |
9867 | 9881 | ||
9868 | if (HAS_PCH_SPLIT(dev)) { |
9882 | if (HAS_PCH_SPLIT(dev)) { |
9869 | if (IS_GEN5(dev)) { |
9883 | if (IS_GEN5(dev)) { |
9870 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
9884 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
9871 | dev_priv->display.write_eld = ironlake_write_eld; |
9885 | dev_priv->display.write_eld = ironlake_write_eld; |
9872 | } else if (IS_GEN6(dev)) { |
9886 | } else if (IS_GEN6(dev)) { |
9873 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
9887 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
9874 | dev_priv->display.write_eld = ironlake_write_eld; |
9888 | dev_priv->display.write_eld = ironlake_write_eld; |
9875 | } else if (IS_IVYBRIDGE(dev)) { |
9889 | } else if (IS_IVYBRIDGE(dev)) { |
9876 | /* FIXME: detect B0+ stepping and use auto training */ |
9890 | /* FIXME: detect B0+ stepping and use auto training */ |
9877 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
9891 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
9878 | dev_priv->display.write_eld = ironlake_write_eld; |
9892 | dev_priv->display.write_eld = ironlake_write_eld; |
9879 | dev_priv->display.modeset_global_resources = |
9893 | dev_priv->display.modeset_global_resources = |
9880 | ivb_modeset_global_resources; |
9894 | ivb_modeset_global_resources; |
9881 | } else if (IS_HASWELL(dev)) { |
9895 | } else if (IS_HASWELL(dev)) { |
9882 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
9896 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
9883 | dev_priv->display.write_eld = haswell_write_eld; |
9897 | dev_priv->display.write_eld = haswell_write_eld; |
9884 | dev_priv->display.modeset_global_resources = |
9898 | dev_priv->display.modeset_global_resources = |
9885 | haswell_modeset_global_resources; |
9899 | haswell_modeset_global_resources; |
9886 | } |
9900 | } |
9887 | } else if (IS_G4X(dev)) { |
9901 | } else if (IS_G4X(dev)) { |
9888 | dev_priv->display.write_eld = g4x_write_eld; |
9902 | dev_priv->display.write_eld = g4x_write_eld; |
9889 | } |
9903 | } |
9890 | 9904 | ||
9891 | /* Default just returns -ENODEV to indicate unsupported */ |
9905 | /* Default just returns -ENODEV to indicate unsupported */ |
9892 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
9906 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
9893 | 9907 | ||
9894 | 9908 | ||
9895 | 9909 | ||
9896 | 9910 | ||
9897 | } |
9911 | } |
9898 | 9912 | ||
9899 | /* |
9913 | /* |
9900 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
9914 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
9901 | * resume, or other times. This quirk makes sure that's the case for |
9915 | * resume, or other times. This quirk makes sure that's the case for |
9902 | * affected systems. |
9916 | * affected systems. |
9903 | */ |
9917 | */ |
9904 | static void quirk_pipea_force(struct drm_device *dev) |
9918 | static void quirk_pipea_force(struct drm_device *dev) |
9905 | { |
9919 | { |
9906 | struct drm_i915_private *dev_priv = dev->dev_private; |
9920 | struct drm_i915_private *dev_priv = dev->dev_private; |
9907 | 9921 | ||
9908 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
9922 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
9909 | DRM_INFO("applying pipe a force quirk\n"); |
9923 | DRM_INFO("applying pipe a force quirk\n"); |
9910 | } |
9924 | } |
9911 | 9925 | ||
9912 | /* |
9926 | /* |
9913 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
9927 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
9914 | */ |
9928 | */ |
9915 | static void quirk_ssc_force_disable(struct drm_device *dev) |
9929 | static void quirk_ssc_force_disable(struct drm_device *dev) |
9916 | { |
9930 | { |
9917 | struct drm_i915_private *dev_priv = dev->dev_private; |
9931 | struct drm_i915_private *dev_priv = dev->dev_private; |
9918 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
9932 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
9919 | DRM_INFO("applying lvds SSC disable quirk\n"); |
9933 | DRM_INFO("applying lvds SSC disable quirk\n"); |
9920 | } |
9934 | } |
9921 | 9935 | ||
9922 | /* |
9936 | /* |
9923 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9937 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9924 | * brightness value |
9938 | * brightness value |
9925 | */ |
9939 | */ |
9926 | static void quirk_invert_brightness(struct drm_device *dev) |
9940 | static void quirk_invert_brightness(struct drm_device *dev) |
9927 | { |
9941 | { |
9928 | struct drm_i915_private *dev_priv = dev->dev_private; |
9942 | struct drm_i915_private *dev_priv = dev->dev_private; |
9929 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9943 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9930 | DRM_INFO("applying inverted panel brightness quirk\n"); |
9944 | DRM_INFO("applying inverted panel brightness quirk\n"); |
9931 | } |
9945 | } |
9932 | 9946 | ||
9933 | /* |
9947 | /* |
9934 | * Some machines (Dell XPS13) suffer broken backlight controls if |
9948 | * Some machines (Dell XPS13) suffer broken backlight controls if |
9935 | * BLM_PCH_PWM_ENABLE is set. |
9949 | * BLM_PCH_PWM_ENABLE is set. |
9936 | */ |
9950 | */ |
9937 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
9951 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
9938 | { |
9952 | { |
9939 | struct drm_i915_private *dev_priv = dev->dev_private; |
9953 | struct drm_i915_private *dev_priv = dev->dev_private; |
9940 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
9954 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
9941 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
9955 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
9942 | } |
9956 | } |
9943 | 9957 | ||
9944 | struct intel_quirk { |
9958 | struct intel_quirk { |
9945 | int device; |
9959 | int device; |
9946 | int subsystem_vendor; |
9960 | int subsystem_vendor; |
9947 | int subsystem_device; |
9961 | int subsystem_device; |
9948 | void (*hook)(struct drm_device *dev); |
9962 | void (*hook)(struct drm_device *dev); |
9949 | }; |
9963 | }; |
9950 | 9964 | ||
9951 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9965 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9952 | struct intel_dmi_quirk { |
9966 | struct intel_dmi_quirk { |
9953 | void (*hook)(struct drm_device *dev); |
9967 | void (*hook)(struct drm_device *dev); |
9954 | const struct dmi_system_id (*dmi_id_list)[]; |
9968 | const struct dmi_system_id (*dmi_id_list)[]; |
9955 | }; |
9969 | }; |
9956 | 9970 | ||
9957 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
9971 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
9958 | { |
9972 | { |
9959 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
9973 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
9960 | return 1; |
9974 | return 1; |
9961 | } |
9975 | } |
9962 | 9976 | ||
9963 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
9977 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
9964 | { |
9978 | { |
9965 | .dmi_id_list = &(const struct dmi_system_id[]) { |
9979 | .dmi_id_list = &(const struct dmi_system_id[]) { |
9966 | { |
9980 | { |
9967 | .callback = intel_dmi_reverse_brightness, |
9981 | .callback = intel_dmi_reverse_brightness, |
9968 | .ident = "NCR Corporation", |
9982 | .ident = "NCR Corporation", |
9969 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
9983 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
9970 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
9984 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
9971 | }, |
9985 | }, |
9972 | }, |
9986 | }, |
9973 | { } /* terminating entry */ |
9987 | { } /* terminating entry */ |
9974 | }, |
9988 | }, |
9975 | .hook = quirk_invert_brightness, |
9989 | .hook = quirk_invert_brightness, |
9976 | }, |
9990 | }, |
9977 | }; |
9991 | }; |
9978 | 9992 | ||
9979 | static struct intel_quirk intel_quirks[] = { |
9993 | static struct intel_quirk intel_quirks[] = { |
9980 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
9994 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
9981 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
9995 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
9982 | 9996 | ||
9983 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9997 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9984 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
9998 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
9985 | 9999 | ||
9986 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10000 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9987 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
10001 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
9988 | 10002 | ||
9989 | /* 830/845 need to leave pipe A & dpll A up */ |
10003 | /* 830/845 need to leave pipe A & dpll A up */ |
9990 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
10004 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9991 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
10005 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9992 | 10006 | ||
9993 | /* Lenovo U160 cannot use SSC on LVDS */ |
10007 | /* Lenovo U160 cannot use SSC on LVDS */ |
9994 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
10008 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
9995 | 10009 | ||
9996 | /* Sony Vaio Y cannot use SSC on LVDS */ |
10010 | /* Sony Vaio Y cannot use SSC on LVDS */ |
9997 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
10011 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
9998 | 10012 | ||
9999 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10013 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10000 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
10014 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
10001 | 10015 | ||
10002 | /* Acer/eMachines G725 */ |
10016 | /* Acer/eMachines G725 */ |
10003 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
10017 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
10004 | 10018 | ||
10005 | /* Acer/eMachines e725 */ |
10019 | /* Acer/eMachines e725 */ |
10006 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
10020 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
10007 | 10021 | ||
10008 | /* Acer/Packard Bell NCL20 */ |
10022 | /* Acer/Packard Bell NCL20 */ |
10009 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
10023 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
10010 | 10024 | ||
10011 | /* Acer Aspire 4736Z */ |
10025 | /* Acer Aspire 4736Z */ |
10012 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
10026 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
10013 | 10027 | ||
10014 | /* Dell XPS13 HD Sandy Bridge */ |
10028 | /* Dell XPS13 HD Sandy Bridge */ |
10015 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
10029 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
10016 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
10030 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
10017 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
10031 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
10018 | }; |
10032 | }; |
10019 | 10033 | ||
10020 | static void intel_init_quirks(struct drm_device *dev) |
10034 | static void intel_init_quirks(struct drm_device *dev) |
10021 | { |
10035 | { |
10022 | struct pci_dev *d = dev->pdev; |
10036 | struct pci_dev *d = dev->pdev; |
10023 | int i; |
10037 | int i; |
10024 | 10038 | ||
10025 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
10039 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
10026 | struct intel_quirk *q = &intel_quirks[i]; |
10040 | struct intel_quirk *q = &intel_quirks[i]; |
10027 | 10041 | ||
10028 | if (d->device == q->device && |
10042 | if (d->device == q->device && |
10029 | (d->subsystem_vendor == q->subsystem_vendor || |
10043 | (d->subsystem_vendor == q->subsystem_vendor || |
10030 | q->subsystem_vendor == PCI_ANY_ID) && |
10044 | q->subsystem_vendor == PCI_ANY_ID) && |
10031 | (d->subsystem_device == q->subsystem_device || |
10045 | (d->subsystem_device == q->subsystem_device || |
10032 | q->subsystem_device == PCI_ANY_ID)) |
10046 | q->subsystem_device == PCI_ANY_ID)) |
10033 | q->hook(dev); |
10047 | q->hook(dev); |
10034 | } |
10048 | } |
10035 | } |
10049 | } |
10036 | 10050 | ||
10037 | /* Disable the VGA plane that we never use */ |
10051 | /* Disable the VGA plane that we never use */ |
10038 | static void i915_disable_vga(struct drm_device *dev) |
10052 | static void i915_disable_vga(struct drm_device *dev) |
10039 | { |
10053 | { |
10040 | struct drm_i915_private *dev_priv = dev->dev_private; |
10054 | struct drm_i915_private *dev_priv = dev->dev_private; |
10041 | u8 sr1; |
10055 | u8 sr1; |
10042 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10056 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10043 | 10057 | ||
10044 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10058 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10045 | out8(SR01, VGA_SR_INDEX); |
10059 | out8(SR01, VGA_SR_INDEX); |
10046 | sr1 = in8(VGA_SR_DATA); |
10060 | sr1 = in8(VGA_SR_DATA); |
10047 | out8(sr1 | 1<<5, VGA_SR_DATA); |
10061 | out8(sr1 | 1<<5, VGA_SR_DATA); |
10048 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
10062 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
10049 | udelay(300); |
10063 | udelay(300); |
10050 | 10064 | ||
10051 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10065 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10052 | POSTING_READ(vga_reg); |
10066 | POSTING_READ(vga_reg); |
10053 | } |
10067 | } |
10054 | 10068 | ||
10055 | void intel_modeset_init_hw(struct drm_device *dev) |
10069 | void intel_modeset_init_hw(struct drm_device *dev) |
10056 | { |
10070 | { |
10057 | struct drm_i915_private *dev_priv = dev->dev_private; |
10071 | struct drm_i915_private *dev_priv = dev->dev_private; |
10058 | 10072 | ||
10059 | intel_init_power_well(dev); |
10073 | intel_init_power_well(dev); |
10060 | 10074 | ||
10061 | intel_prepare_ddi(dev); |
10075 | intel_prepare_ddi(dev); |
10062 | 10076 | ||
10063 | intel_init_clock_gating(dev); |
10077 | intel_init_clock_gating(dev); |
10064 | 10078 | ||
10065 | /* Enable the CRI clock source so we can get at the display */ |
10079 | /* Enable the CRI clock source so we can get at the display */ |
10066 | if (IS_VALLEYVIEW(dev)) |
10080 | if (IS_VALLEYVIEW(dev)) |
10067 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
10081 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
10068 | DPLL_INTEGRATED_CRI_CLK_VLV); |
10082 | DPLL_INTEGRATED_CRI_CLK_VLV); |
10069 | 10083 | ||
10070 | mutex_lock(&dev->struct_mutex); |
10084 | mutex_lock(&dev->struct_mutex); |
10071 | intel_enable_gt_powersave(dev); |
10085 | intel_enable_gt_powersave(dev); |
10072 | mutex_unlock(&dev->struct_mutex); |
10086 | mutex_unlock(&dev->struct_mutex); |
10073 | } |
10087 | } |
10074 | 10088 | ||
10075 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10089 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10076 | { |
10090 | { |
10077 | intel_suspend_hw(dev); |
10091 | intel_suspend_hw(dev); |
10078 | } |
10092 | } |
10079 | 10093 | ||
10080 | void intel_modeset_init(struct drm_device *dev) |
10094 | void intel_modeset_init(struct drm_device *dev) |
10081 | { |
10095 | { |
10082 | struct drm_i915_private *dev_priv = dev->dev_private; |
10096 | struct drm_i915_private *dev_priv = dev->dev_private; |
10083 | int i, j, ret; |
10097 | int i, j, ret; |
10084 | 10098 | ||
10085 | drm_mode_config_init(dev); |
10099 | drm_mode_config_init(dev); |
10086 | 10100 | ||
10087 | dev->mode_config.min_width = 0; |
10101 | dev->mode_config.min_width = 0; |
10088 | dev->mode_config.min_height = 0; |
10102 | dev->mode_config.min_height = 0; |
10089 | 10103 | ||
10090 | dev->mode_config.preferred_depth = 24; |
10104 | dev->mode_config.preferred_depth = 24; |
10091 | dev->mode_config.prefer_shadow = 1; |
10105 | dev->mode_config.prefer_shadow = 1; |
10092 | 10106 | ||
10093 | dev->mode_config.funcs = &intel_mode_funcs; |
10107 | dev->mode_config.funcs = &intel_mode_funcs; |
10094 | 10108 | ||
10095 | intel_init_quirks(dev); |
10109 | intel_init_quirks(dev); |
10096 | 10110 | ||
10097 | intel_init_pm(dev); |
10111 | intel_init_pm(dev); |
10098 | 10112 | ||
10099 | if (INTEL_INFO(dev)->num_pipes == 0) |
10113 | if (INTEL_INFO(dev)->num_pipes == 0) |
10100 | return; |
10114 | return; |
10101 | 10115 | ||
10102 | intel_init_display(dev); |
10116 | intel_init_display(dev); |
10103 | 10117 | ||
10104 | if (IS_GEN2(dev)) { |
10118 | if (IS_GEN2(dev)) { |
10105 | dev->mode_config.max_width = 2048; |
10119 | dev->mode_config.max_width = 2048; |
10106 | dev->mode_config.max_height = 2048; |
10120 | dev->mode_config.max_height = 2048; |
10107 | } else if (IS_GEN3(dev)) { |
10121 | } else if (IS_GEN3(dev)) { |
10108 | dev->mode_config.max_width = 4096; |
10122 | dev->mode_config.max_width = 4096; |
10109 | dev->mode_config.max_height = 4096; |
10123 | dev->mode_config.max_height = 4096; |
10110 | } else { |
10124 | } else { |
10111 | dev->mode_config.max_width = 8192; |
10125 | dev->mode_config.max_width = 8192; |
10112 | dev->mode_config.max_height = 8192; |
10126 | dev->mode_config.max_height = 8192; |
10113 | } |
10127 | } |
10114 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
10128 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
10115 | 10129 | ||
10116 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10130 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10117 | INTEL_INFO(dev)->num_pipes, |
10131 | INTEL_INFO(dev)->num_pipes, |
10118 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10132 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10119 | 10133 | ||
10120 | for_each_pipe(i) { |
10134 | for_each_pipe(i) { |
10121 | intel_crtc_init(dev, i); |
10135 | intel_crtc_init(dev, i); |
10122 | for (j = 0; j < dev_priv->num_plane; j++) { |
10136 | for (j = 0; j < dev_priv->num_plane; j++) { |
10123 | ret = intel_plane_init(dev, i, j); |
10137 | ret = intel_plane_init(dev, i, j); |
10124 | if (ret) |
10138 | if (ret) |
10125 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10139 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10126 | pipe_name(i), sprite_name(i, j), ret); |
10140 | pipe_name(i), sprite_name(i, j), ret); |
10127 | } |
10141 | } |
10128 | } |
10142 | } |
10129 | 10143 | ||
10130 | intel_cpu_pll_init(dev); |
10144 | intel_cpu_pll_init(dev); |
10131 | intel_shared_dpll_init(dev); |
10145 | intel_shared_dpll_init(dev); |
10132 | 10146 | ||
10133 | /* Just disable it once at startup */ |
10147 | /* Just disable it once at startup */ |
10134 | i915_disable_vga(dev); |
10148 | i915_disable_vga(dev); |
10135 | intel_setup_outputs(dev); |
10149 | intel_setup_outputs(dev); |
10136 | 10150 | ||
10137 | /* Just in case the BIOS is doing something questionable. */ |
10151 | /* Just in case the BIOS is doing something questionable. */ |
10138 | intel_disable_fbc(dev); |
10152 | intel_disable_fbc(dev); |
10139 | } |
10153 | } |
10140 | 10154 | ||
10141 | static void |
10155 | static void |
10142 | intel_connector_break_all_links(struct intel_connector *connector) |
10156 | intel_connector_break_all_links(struct intel_connector *connector) |
10143 | { |
10157 | { |
10144 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10158 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10145 | connector->base.encoder = NULL; |
10159 | connector->base.encoder = NULL; |
10146 | connector->encoder->connectors_active = false; |
10160 | connector->encoder->connectors_active = false; |
10147 | connector->encoder->base.crtc = NULL; |
10161 | connector->encoder->base.crtc = NULL; |
10148 | } |
10162 | } |
10149 | 10163 | ||
10150 | static void intel_enable_pipe_a(struct drm_device *dev) |
10164 | static void intel_enable_pipe_a(struct drm_device *dev) |
10151 | { |
10165 | { |
10152 | struct intel_connector *connector; |
10166 | struct intel_connector *connector; |
10153 | struct drm_connector *crt = NULL; |
10167 | struct drm_connector *crt = NULL; |
10154 | struct intel_load_detect_pipe load_detect_temp; |
10168 | struct intel_load_detect_pipe load_detect_temp; |
10155 | 10169 | ||
10156 | /* We can't just switch on the pipe A, we need to set things up with a |
10170 | /* We can't just switch on the pipe A, we need to set things up with a |
10157 | * proper mode and output configuration. As a gross hack, enable pipe A |
10171 | * proper mode and output configuration. As a gross hack, enable pipe A |
10158 | * by enabling the load detect pipe once. */ |
10172 | * by enabling the load detect pipe once. */ |
10159 | list_for_each_entry(connector, |
10173 | list_for_each_entry(connector, |
10160 | &dev->mode_config.connector_list, |
10174 | &dev->mode_config.connector_list, |
10161 | base.head) { |
10175 | base.head) { |
10162 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
10176 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
10163 | crt = &connector->base; |
10177 | crt = &connector->base; |
10164 | break; |
10178 | break; |
10165 | } |
10179 | } |
10166 | } |
10180 | } |
10167 | 10181 | ||
10168 | if (!crt) |
10182 | if (!crt) |
10169 | return; |
10183 | return; |
10170 | 10184 | ||
10171 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
10185 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
10172 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
10186 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
10173 | 10187 | ||
10174 | 10188 | ||
10175 | } |
10189 | } |
10176 | 10190 | ||
10177 | static bool |
10191 | static bool |
10178 | intel_check_plane_mapping(struct intel_crtc *crtc) |
10192 | intel_check_plane_mapping(struct intel_crtc *crtc) |
10179 | { |
10193 | { |
10180 | struct drm_device *dev = crtc->base.dev; |
10194 | struct drm_device *dev = crtc->base.dev; |
10181 | struct drm_i915_private *dev_priv = dev->dev_private; |
10195 | struct drm_i915_private *dev_priv = dev->dev_private; |
10182 | u32 reg, val; |
10196 | u32 reg, val; |
10183 | 10197 | ||
10184 | if (INTEL_INFO(dev)->num_pipes == 1) |
10198 | if (INTEL_INFO(dev)->num_pipes == 1) |
10185 | return true; |
10199 | return true; |
10186 | 10200 | ||
10187 | reg = DSPCNTR(!crtc->plane); |
10201 | reg = DSPCNTR(!crtc->plane); |
10188 | val = I915_READ(reg); |
10202 | val = I915_READ(reg); |
10189 | 10203 | ||
10190 | if ((val & DISPLAY_PLANE_ENABLE) && |
10204 | if ((val & DISPLAY_PLANE_ENABLE) && |
10191 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
10205 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
10192 | return false; |
10206 | return false; |
10193 | 10207 | ||
10194 | return true; |
10208 | return true; |
10195 | } |
10209 | } |
10196 | 10210 | ||
10197 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10211 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10198 | { |
10212 | { |
10199 | struct drm_device *dev = crtc->base.dev; |
10213 | struct drm_device *dev = crtc->base.dev; |
10200 | struct drm_i915_private *dev_priv = dev->dev_private; |
10214 | struct drm_i915_private *dev_priv = dev->dev_private; |
10201 | u32 reg; |
10215 | u32 reg; |
10202 | 10216 | ||
10203 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10217 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10204 | reg = PIPECONF(crtc->config.cpu_transcoder); |
10218 | reg = PIPECONF(crtc->config.cpu_transcoder); |
10205 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10219 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10206 | 10220 | ||
10207 | /* We need to sanitize the plane -> pipe mapping first because this will |
10221 | /* We need to sanitize the plane -> pipe mapping first because this will |
10208 | * disable the crtc (and hence change the state) if it is wrong. Note |
10222 | * disable the crtc (and hence change the state) if it is wrong. Note |
10209 | * that gen4+ has a fixed plane -> pipe mapping. */ |
10223 | * that gen4+ has a fixed plane -> pipe mapping. */ |
10210 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
10224 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
10211 | struct intel_connector *connector; |
10225 | struct intel_connector *connector; |
10212 | bool plane; |
10226 | bool plane; |
10213 | 10227 | ||
10214 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10228 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10215 | crtc->base.base.id); |
10229 | crtc->base.base.id); |
10216 | 10230 | ||
10217 | /* Pipe has the wrong plane attached and the plane is active. |
10231 | /* Pipe has the wrong plane attached and the plane is active. |
10218 | * Temporarily change the plane mapping and disable everything |
10232 | * Temporarily change the plane mapping and disable everything |
10219 | * ... */ |
10233 | * ... */ |
10220 | plane = crtc->plane; |
10234 | plane = crtc->plane; |
10221 | crtc->plane = !plane; |
10235 | crtc->plane = !plane; |
10222 | dev_priv->display.crtc_disable(&crtc->base); |
10236 | dev_priv->display.crtc_disable(&crtc->base); |
10223 | crtc->plane = plane; |
10237 | crtc->plane = plane; |
10224 | 10238 | ||
10225 | /* ... and break all links. */ |
10239 | /* ... and break all links. */ |
10226 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10240 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10227 | base.head) { |
10241 | base.head) { |
10228 | if (connector->encoder->base.crtc != &crtc->base) |
10242 | if (connector->encoder->base.crtc != &crtc->base) |
10229 | continue; |
10243 | continue; |
10230 | 10244 | ||
10231 | intel_connector_break_all_links(connector); |
10245 | intel_connector_break_all_links(connector); |
10232 | } |
10246 | } |
10233 | 10247 | ||
10234 | WARN_ON(crtc->active); |
10248 | WARN_ON(crtc->active); |
10235 | crtc->base.enabled = false; |
10249 | crtc->base.enabled = false; |
10236 | } |
10250 | } |
10237 | 10251 | ||
10238 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10252 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10239 | crtc->pipe == PIPE_A && !crtc->active) { |
10253 | crtc->pipe == PIPE_A && !crtc->active) { |
10240 | /* BIOS forgot to enable pipe A, this mostly happens after |
10254 | /* BIOS forgot to enable pipe A, this mostly happens after |
10241 | * resume. Force-enable the pipe to fix this, the update_dpms |
10255 | * resume. Force-enable the pipe to fix this, the update_dpms |
10242 | * call below we restore the pipe to the right state, but leave |
10256 | * call below we restore the pipe to the right state, but leave |
10243 | * the required bits on. */ |
10257 | * the required bits on. */ |
10244 | intel_enable_pipe_a(dev); |
10258 | intel_enable_pipe_a(dev); |
10245 | } |
10259 | } |
10246 | 10260 | ||
10247 | /* Adjust the state of the output pipe according to whether we |
10261 | /* Adjust the state of the output pipe according to whether we |
10248 | * have active connectors/encoders. */ |
10262 | * have active connectors/encoders. */ |
10249 | intel_crtc_update_dpms(&crtc->base); |
10263 | intel_crtc_update_dpms(&crtc->base); |
10250 | 10264 | ||
10251 | if (crtc->active != crtc->base.enabled) { |
10265 | if (crtc->active != crtc->base.enabled) { |
10252 | struct intel_encoder *encoder; |
10266 | struct intel_encoder *encoder; |
10253 | 10267 | ||
10254 | /* This can happen either due to bugs in the get_hw_state |
10268 | /* This can happen either due to bugs in the get_hw_state |
10255 | * functions or because the pipe is force-enabled due to the |
10269 | * functions or because the pipe is force-enabled due to the |
10256 | * pipe A quirk. */ |
10270 | * pipe A quirk. */ |
10257 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
10271 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
10258 | crtc->base.base.id, |
10272 | crtc->base.base.id, |
10259 | crtc->base.enabled ? "enabled" : "disabled", |
10273 | crtc->base.enabled ? "enabled" : "disabled", |
10260 | crtc->active ? "enabled" : "disabled"); |
10274 | crtc->active ? "enabled" : "disabled"); |
10261 | 10275 | ||
10262 | crtc->base.enabled = crtc->active; |
10276 | crtc->base.enabled = crtc->active; |
10263 | 10277 | ||
10264 | /* Because we only establish the connector -> encoder -> |
10278 | /* Because we only establish the connector -> encoder -> |
10265 | * crtc links if something is active, this means the |
10279 | * crtc links if something is active, this means the |
10266 | * crtc is now deactivated. Break the links. connector |
10280 | * crtc is now deactivated. Break the links. connector |
10267 | * -> encoder links are only establish when things are |
10281 | * -> encoder links are only establish when things are |
10268 | * actually up, hence no need to break them. */ |
10282 | * actually up, hence no need to break them. */ |
10269 | WARN_ON(crtc->active); |
10283 | WARN_ON(crtc->active); |
10270 | 10284 | ||
10271 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
10285 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
10272 | WARN_ON(encoder->connectors_active); |
10286 | WARN_ON(encoder->connectors_active); |
10273 | encoder->base.crtc = NULL; |
10287 | encoder->base.crtc = NULL; |
10274 | } |
10288 | } |
10275 | } |
10289 | } |
10276 | } |
10290 | } |
10277 | 10291 | ||
10278 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
10292 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
10279 | { |
10293 | { |
10280 | struct intel_connector *connector; |
10294 | struct intel_connector *connector; |
10281 | struct drm_device *dev = encoder->base.dev; |
10295 | struct drm_device *dev = encoder->base.dev; |
10282 | 10296 | ||
10283 | /* We need to check both for a crtc link (meaning that the |
10297 | /* We need to check both for a crtc link (meaning that the |
10284 | * encoder is active and trying to read from a pipe) and the |
10298 | * encoder is active and trying to read from a pipe) and the |
10285 | * pipe itself being active. */ |
10299 | * pipe itself being active. */ |
10286 | bool has_active_crtc = encoder->base.crtc && |
10300 | bool has_active_crtc = encoder->base.crtc && |
10287 | to_intel_crtc(encoder->base.crtc)->active; |
10301 | to_intel_crtc(encoder->base.crtc)->active; |
10288 | 10302 | ||
10289 | if (encoder->connectors_active && !has_active_crtc) { |
10303 | if (encoder->connectors_active && !has_active_crtc) { |
10290 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
10304 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
10291 | encoder->base.base.id, |
10305 | encoder->base.base.id, |
10292 | drm_get_encoder_name(&encoder->base)); |
10306 | drm_get_encoder_name(&encoder->base)); |
10293 | 10307 | ||
10294 | /* Connector is active, but has no active pipe. This is |
10308 | /* Connector is active, but has no active pipe. This is |
10295 | * fallout from our resume register restoring. Disable |
10309 | * fallout from our resume register restoring. Disable |
10296 | * the encoder manually again. */ |
10310 | * the encoder manually again. */ |
10297 | if (encoder->base.crtc) { |
10311 | if (encoder->base.crtc) { |
10298 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
10312 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
10299 | encoder->base.base.id, |
10313 | encoder->base.base.id, |
10300 | drm_get_encoder_name(&encoder->base)); |
10314 | drm_get_encoder_name(&encoder->base)); |
10301 | encoder->disable(encoder); |
10315 | encoder->disable(encoder); |
10302 | } |
10316 | } |
10303 | 10317 | ||
10304 | /* Inconsistent output/port/pipe state happens presumably due to |
10318 | /* Inconsistent output/port/pipe state happens presumably due to |
10305 | * a bug in one of the get_hw_state functions. Or someplace else |
10319 | * a bug in one of the get_hw_state functions. Or someplace else |
10306 | * in our code, like the register restore mess on resume. Clamp |
10320 | * in our code, like the register restore mess on resume. Clamp |
10307 | * things to off as a safer default. */ |
10321 | * things to off as a safer default. */ |
10308 | list_for_each_entry(connector, |
10322 | list_for_each_entry(connector, |
10309 | &dev->mode_config.connector_list, |
10323 | &dev->mode_config.connector_list, |
10310 | base.head) { |
10324 | base.head) { |
10311 | if (connector->encoder != encoder) |
10325 | if (connector->encoder != encoder) |
10312 | continue; |
10326 | continue; |
10313 | 10327 | ||
10314 | intel_connector_break_all_links(connector); |
10328 | intel_connector_break_all_links(connector); |
10315 | } |
10329 | } |
10316 | } |
10330 | } |
10317 | /* Enabled encoders without active connectors will be fixed in |
10331 | /* Enabled encoders without active connectors will be fixed in |
10318 | * the crtc fixup. */ |
10332 | * the crtc fixup. */ |
10319 | } |
10333 | } |
10320 | 10334 | ||
10321 | void i915_redisable_vga(struct drm_device *dev) |
10335 | void i915_redisable_vga(struct drm_device *dev) |
10322 | { |
10336 | { |
10323 | struct drm_i915_private *dev_priv = dev->dev_private; |
10337 | struct drm_i915_private *dev_priv = dev->dev_private; |
10324 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10338 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10325 | 10339 | ||
10326 | /* This function can be called both from intel_modeset_setup_hw_state or |
10340 | /* This function can be called both from intel_modeset_setup_hw_state or |
10327 | * at a very early point in our resume sequence, where the power well |
10341 | * at a very early point in our resume sequence, where the power well |
10328 | * structures are not yet restored. Since this function is at a very |
10342 | * structures are not yet restored. Since this function is at a very |
10329 | * paranoid "someone might have enabled VGA while we were not looking" |
10343 | * paranoid "someone might have enabled VGA while we were not looking" |
10330 | * level, just check if the power well is enabled instead of trying to |
10344 | * level, just check if the power well is enabled instead of trying to |
10331 | * follow the "don't touch the power well if we don't need it" policy |
10345 | * follow the "don't touch the power well if we don't need it" policy |
10332 | * the rest of the driver uses. */ |
10346 | * the rest of the driver uses. */ |
10333 | if (HAS_POWER_WELL(dev) && |
10347 | if (HAS_POWER_WELL(dev) && |
10334 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
10348 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
10335 | return; |
10349 | return; |
10336 | 10350 | ||
10337 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10351 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10338 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
10352 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
10339 | i915_disable_vga(dev); |
10353 | i915_disable_vga(dev); |
10340 | } |
10354 | } |
10341 | } |
10355 | } |
10342 | 10356 | ||
10343 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
10357 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
10344 | { |
10358 | { |
10345 | struct drm_i915_private *dev_priv = dev->dev_private; |
10359 | struct drm_i915_private *dev_priv = dev->dev_private; |
10346 | enum pipe pipe; |
10360 | enum pipe pipe; |
10347 | struct intel_crtc *crtc; |
10361 | struct intel_crtc *crtc; |
10348 | struct intel_encoder *encoder; |
10362 | struct intel_encoder *encoder; |
10349 | struct intel_connector *connector; |
10363 | struct intel_connector *connector; |
10350 | int i; |
10364 | int i; |
10351 | 10365 | ||
10352 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10366 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10353 | base.head) { |
10367 | base.head) { |
10354 | memset(&crtc->config, 0, sizeof(crtc->config)); |
10368 | memset(&crtc->config, 0, sizeof(crtc->config)); |
10355 | 10369 | ||
10356 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10370 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10357 | &crtc->config); |
10371 | &crtc->config); |
10358 | 10372 | ||
10359 | crtc->base.enabled = crtc->active; |
10373 | crtc->base.enabled = crtc->active; |
10360 | 10374 | ||
10361 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
10375 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
10362 | crtc->base.base.id, |
10376 | crtc->base.base.id, |
10363 | crtc->active ? "enabled" : "disabled"); |
10377 | crtc->active ? "enabled" : "disabled"); |
10364 | } |
10378 | } |
10365 | 10379 | ||
10366 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
10380 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
10367 | if (HAS_DDI(dev)) |
10381 | if (HAS_DDI(dev)) |
10368 | intel_ddi_setup_hw_pll_state(dev); |
10382 | intel_ddi_setup_hw_pll_state(dev); |
10369 | 10383 | ||
10370 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10384 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10371 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10385 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10372 | 10386 | ||
10373 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
10387 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
10374 | pll->active = 0; |
10388 | pll->active = 0; |
10375 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10389 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10376 | base.head) { |
10390 | base.head) { |
10377 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10391 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10378 | pll->active++; |
10392 | pll->active++; |
10379 | } |
10393 | } |
10380 | pll->refcount = pll->active; |
10394 | pll->refcount = pll->active; |
10381 | 10395 | ||
10382 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10396 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10383 | pll->name, pll->refcount, pll->on); |
10397 | pll->name, pll->refcount, pll->on); |
10384 | } |
10398 | } |
10385 | 10399 | ||
10386 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10400 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10387 | base.head) { |
10401 | base.head) { |
10388 | pipe = 0; |
10402 | pipe = 0; |
10389 | 10403 | ||
10390 | if (encoder->get_hw_state(encoder, &pipe)) { |
10404 | if (encoder->get_hw_state(encoder, &pipe)) { |
10391 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10405 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10392 | encoder->base.crtc = &crtc->base; |
10406 | encoder->base.crtc = &crtc->base; |
10393 | if (encoder->get_config) |
10407 | if (encoder->get_config) |
10394 | encoder->get_config(encoder, &crtc->config); |
10408 | encoder->get_config(encoder, &crtc->config); |
10395 | } else { |
10409 | } else { |
10396 | encoder->base.crtc = NULL; |
10410 | encoder->base.crtc = NULL; |
10397 | } |
10411 | } |
10398 | 10412 | ||
10399 | encoder->connectors_active = false; |
10413 | encoder->connectors_active = false; |
10400 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
10414 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
10401 | encoder->base.base.id, |
10415 | encoder->base.base.id, |
10402 | drm_get_encoder_name(&encoder->base), |
10416 | drm_get_encoder_name(&encoder->base), |
10403 | encoder->base.crtc ? "enabled" : "disabled", |
10417 | encoder->base.crtc ? "enabled" : "disabled", |
10404 | pipe); |
10418 | pipe); |
10405 | } |
10419 | } |
10406 | 10420 | ||
10407 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10421 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10408 | base.head) { |
10422 | base.head) { |
10409 | if (!crtc->active) |
10423 | if (!crtc->active) |
10410 | continue; |
10424 | continue; |
10411 | if (dev_priv->display.get_clock) |
10425 | if (dev_priv->display.get_clock) |
10412 | dev_priv->display.get_clock(crtc, |
10426 | dev_priv->display.get_clock(crtc, |
10413 | &crtc->config); |
10427 | &crtc->config); |
10414 | } |
10428 | } |
10415 | 10429 | ||
10416 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10430 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10417 | base.head) { |
10431 | base.head) { |
10418 | if (connector->get_hw_state(connector)) { |
10432 | if (connector->get_hw_state(connector)) { |
10419 | connector->base.dpms = DRM_MODE_DPMS_ON; |
10433 | connector->base.dpms = DRM_MODE_DPMS_ON; |
10420 | connector->encoder->connectors_active = true; |
10434 | connector->encoder->connectors_active = true; |
10421 | connector->base.encoder = &connector->encoder->base; |
10435 | connector->base.encoder = &connector->encoder->base; |
10422 | } else { |
10436 | } else { |
10423 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10437 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10424 | connector->base.encoder = NULL; |
10438 | connector->base.encoder = NULL; |
10425 | } |
10439 | } |
10426 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
10440 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
10427 | connector->base.base.id, |
10441 | connector->base.base.id, |
10428 | drm_get_connector_name(&connector->base), |
10442 | drm_get_connector_name(&connector->base), |
10429 | connector->base.encoder ? "enabled" : "disabled"); |
10443 | connector->base.encoder ? "enabled" : "disabled"); |
10430 | } |
10444 | } |
10431 | } |
10445 | } |
10432 | 10446 | ||
10433 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
10447 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
10434 | * and i915 state tracking structures. */ |
10448 | * and i915 state tracking structures. */ |
10435 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
10449 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
10436 | bool force_restore) |
10450 | bool force_restore) |
10437 | { |
10451 | { |
10438 | struct drm_i915_private *dev_priv = dev->dev_private; |
10452 | struct drm_i915_private *dev_priv = dev->dev_private; |
10439 | enum pipe pipe; |
10453 | enum pipe pipe; |
10440 | struct drm_plane *plane; |
10454 | struct drm_plane *plane; |
10441 | struct intel_crtc *crtc; |
10455 | struct intel_crtc *crtc; |
10442 | struct intel_encoder *encoder; |
10456 | struct intel_encoder *encoder; |
10443 | int i; |
10457 | int i; |
10444 | 10458 | ||
10445 | intel_modeset_readout_hw_state(dev); |
10459 | intel_modeset_readout_hw_state(dev); |
10446 | 10460 | ||
10447 | /* |
10461 | /* |
10448 | * Now that we have the config, copy it to each CRTC struct |
10462 | * Now that we have the config, copy it to each CRTC struct |
10449 | * Note that this could go away if we move to using crtc_config |
10463 | * Note that this could go away if we move to using crtc_config |
10450 | * checking everywhere. |
10464 | * checking everywhere. |
10451 | */ |
10465 | */ |
10452 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10466 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10453 | base.head) { |
10467 | base.head) { |
10454 | if (crtc->active && i915_fastboot) { |
10468 | if (crtc->active && i915_fastboot) { |
10455 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
10469 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
10456 | 10470 | ||
10457 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
10471 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
10458 | crtc->base.base.id); |
10472 | crtc->base.base.id); |
10459 | drm_mode_debug_printmodeline(&crtc->base.mode); |
10473 | drm_mode_debug_printmodeline(&crtc->base.mode); |
10460 | } |
10474 | } |
10461 | } |
10475 | } |
10462 | 10476 | ||
10463 | /* HW state is read out, now we need to sanitize this mess. */ |
10477 | /* HW state is read out, now we need to sanitize this mess. */ |
10464 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10478 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10465 | base.head) { |
10479 | base.head) { |
10466 | intel_sanitize_encoder(encoder); |
10480 | intel_sanitize_encoder(encoder); |
10467 | } |
10481 | } |
10468 | 10482 | ||
10469 | for_each_pipe(pipe) { |
10483 | for_each_pipe(pipe) { |
10470 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10484 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10471 | intel_sanitize_crtc(crtc); |
10485 | intel_sanitize_crtc(crtc); |
10472 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
10486 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
10473 | } |
10487 | } |
10474 | 10488 | ||
10475 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10489 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10476 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10490 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10477 | 10491 | ||
10478 | if (!pll->on || pll->active) |
10492 | if (!pll->on || pll->active) |
10479 | continue; |
10493 | continue; |
10480 | 10494 | ||
10481 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
10495 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
10482 | 10496 | ||
10483 | pll->disable(dev_priv, pll); |
10497 | pll->disable(dev_priv, pll); |
10484 | pll->on = false; |
10498 | pll->on = false; |
10485 | } |
10499 | } |
10486 | 10500 | ||
10487 | if (force_restore) { |
10501 | if (force_restore) { |
10488 | /* |
10502 | /* |
10489 | * We need to use raw interfaces for restoring state to avoid |
10503 | * We need to use raw interfaces for restoring state to avoid |
10490 | * checking (bogus) intermediate states. |
10504 | * checking (bogus) intermediate states. |
10491 | */ |
10505 | */ |
10492 | for_each_pipe(pipe) { |
10506 | for_each_pipe(pipe) { |
10493 | struct drm_crtc *crtc = |
10507 | struct drm_crtc *crtc = |
10494 | dev_priv->pipe_to_crtc_mapping[pipe]; |
10508 | dev_priv->pipe_to_crtc_mapping[pipe]; |
10495 | 10509 | ||
10496 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
10510 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
10497 | crtc->fb); |
10511 | crtc->fb); |
10498 | } |
10512 | } |
10499 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10513 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10500 | intel_plane_restore(plane); |
10514 | intel_plane_restore(plane); |
10501 | 10515 | ||
10502 | i915_redisable_vga(dev); |
10516 | i915_redisable_vga(dev); |
10503 | } else { |
10517 | } else { |
10504 | intel_modeset_update_staged_output_state(dev); |
10518 | intel_modeset_update_staged_output_state(dev); |
10505 | } |
10519 | } |
10506 | 10520 | ||
10507 | intel_modeset_check_state(dev); |
10521 | intel_modeset_check_state(dev); |
10508 | 10522 | ||
10509 | drm_mode_config_reset(dev); |
10523 | drm_mode_config_reset(dev); |
10510 | } |
10524 | } |
10511 | 10525 | ||
10512 | void intel_modeset_gem_init(struct drm_device *dev) |
10526 | void intel_modeset_gem_init(struct drm_device *dev) |
10513 | { |
10527 | { |
10514 | intel_modeset_init_hw(dev); |
10528 | intel_modeset_init_hw(dev); |
10515 | 10529 | ||
10516 | // intel_setup_overlay(dev); |
10530 | // intel_setup_overlay(dev); |
- | 10531 | ||
10517 | 10532 | mutex_lock(&dev->mode_config.mutex); |
|
- | 10533 | intel_modeset_setup_hw_state(dev, false); |
|
10518 | intel_modeset_setup_hw_state(dev, false); |
10534 | mutex_unlock(&dev->mode_config.mutex); |
10519 | } |
10535 | } |
10520 | 10536 | ||
10521 | void intel_modeset_cleanup(struct drm_device *dev) |
10537 | void intel_modeset_cleanup(struct drm_device *dev) |
10522 | { |
10538 | { |
10523 | #if 0 |
10539 | #if 0 |
10524 | struct drm_i915_private *dev_priv = dev->dev_private; |
10540 | struct drm_i915_private *dev_priv = dev->dev_private; |
10525 | struct drm_crtc *crtc; |
10541 | struct drm_crtc *crtc; |
10526 | 10542 | ||
10527 | /* |
10543 | /* |
10528 | * Interrupts and polling as the first thing to avoid creating havoc. |
10544 | * Interrupts and polling as the first thing to avoid creating havoc. |
10529 | * Too much stuff here (turning of rps, connectors, ...) would |
10545 | * Too much stuff here (turning of rps, connectors, ...) would |
10530 | * experience fancy races otherwise. |
10546 | * experience fancy races otherwise. |
10531 | */ |
10547 | */ |
10532 | drm_irq_uninstall(dev); |
10548 | drm_irq_uninstall(dev); |
10533 | cancel_work_sync(&dev_priv->hotplug_work); |
10549 | cancel_work_sync(&dev_priv->hotplug_work); |
10534 | /* |
10550 | /* |
10535 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
10551 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
10536 | * poll handlers. Hence disable polling after hpd handling is shut down. |
10552 | * poll handlers. Hence disable polling after hpd handling is shut down. |
10537 | */ |
10553 | */ |
10538 | // drm_kms_helper_poll_fini(dev); |
10554 | // drm_kms_helper_poll_fini(dev); |
10539 | 10555 | ||
10540 | mutex_lock(&dev->struct_mutex); |
10556 | mutex_lock(&dev->struct_mutex); |
10541 | 10557 | ||
10542 | // intel_unregister_dsm_handler(); |
10558 | // intel_unregister_dsm_handler(); |
10543 | 10559 | ||
10544 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10560 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10545 | /* Skip inactive CRTCs */ |
10561 | /* Skip inactive CRTCs */ |
10546 | if (!crtc->fb) |
10562 | if (!crtc->fb) |
10547 | continue; |
10563 | continue; |
10548 | 10564 | ||
10549 | intel_increase_pllclock(crtc); |
10565 | intel_increase_pllclock(crtc); |
10550 | } |
10566 | } |
10551 | 10567 | ||
10552 | intel_disable_fbc(dev); |
10568 | intel_disable_fbc(dev); |
10553 | 10569 | ||
10554 | intel_disable_gt_powersave(dev); |
10570 | intel_disable_gt_powersave(dev); |
10555 | 10571 | ||
10556 | ironlake_teardown_rc6(dev); |
10572 | ironlake_teardown_rc6(dev); |
10557 | 10573 | ||
10558 | mutex_unlock(&dev->struct_mutex); |
10574 | mutex_unlock(&dev->struct_mutex); |
10559 | 10575 | ||
10560 | /* flush any delayed tasks or pending work */ |
10576 | /* flush any delayed tasks or pending work */ |
10561 | flush_scheduled_work(); |
10577 | flush_scheduled_work(); |
10562 | 10578 | ||
10563 | /* destroy backlight, if any, before the connectors */ |
10579 | /* destroy backlight, if any, before the connectors */ |
10564 | intel_panel_destroy_backlight(dev); |
10580 | intel_panel_destroy_backlight(dev); |
10565 | 10581 | ||
10566 | drm_mode_config_cleanup(dev); |
10582 | drm_mode_config_cleanup(dev); |
10567 | #endif |
10583 | #endif |
10568 | } |
10584 | } |
10569 | 10585 | ||
10570 | /* |
10586 | /* |
10571 | * Return which encoder is currently attached for connector. |
10587 | * Return which encoder is currently attached for connector. |
10572 | */ |
10588 | */ |
10573 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
10589 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
10574 | { |
10590 | { |
10575 | return &intel_attached_encoder(connector)->base; |
10591 | return &intel_attached_encoder(connector)->base; |
10576 | } |
10592 | } |
10577 | 10593 | ||
10578 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10594 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10579 | struct intel_encoder *encoder) |
10595 | struct intel_encoder *encoder) |
10580 | { |
10596 | { |
10581 | connector->encoder = encoder; |
10597 | connector->encoder = encoder; |
10582 | drm_mode_connector_attach_encoder(&connector->base, |
10598 | drm_mode_connector_attach_encoder(&connector->base, |
10583 | &encoder->base); |
10599 | &encoder->base); |
10584 | } |
10600 | } |
10585 | 10601 | ||
10586 | /* |
10602 | /* |
10587 | * set vga decode state - true == enable VGA decode |
10603 | * set vga decode state - true == enable VGA decode |
10588 | */ |
10604 | */ |
10589 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
10605 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
10590 | { |
10606 | { |
10591 | struct drm_i915_private *dev_priv = dev->dev_private; |
10607 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 10608 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
|
10592 | u16 gmch_ctrl; |
10609 | u16 gmch_ctrl; |
10593 | 10610 | ||
10594 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
10611 | pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); |
10595 | if (state) |
10612 | if (state) |
10596 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
10613 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
10597 | else |
10614 | else |
10598 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10615 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10599 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
10616 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
10600 | return 0; |
10617 | return 0; |
10601 | } |
10618 | } |
10602 | 10619 | ||
10603 | #ifdef CONFIG_DEBUG_FS |
10620 | #ifdef CONFIG_DEBUG_FS |
10604 | #include |
10621 | #include |
10605 | 10622 | ||
10606 | struct intel_display_error_state { |
10623 | struct intel_display_error_state { |
10607 | 10624 | ||
10608 | u32 power_well_driver; |
10625 | u32 power_well_driver; |
10609 | 10626 | ||
10610 | int num_transcoders; |
10627 | int num_transcoders; |
10611 | 10628 | ||
10612 | struct intel_cursor_error_state { |
10629 | struct intel_cursor_error_state { |
10613 | u32 control; |
10630 | u32 control; |
10614 | u32 position; |
10631 | u32 position; |
10615 | u32 base; |
10632 | u32 base; |
10616 | u32 size; |
10633 | u32 size; |
10617 | } cursor[I915_MAX_PIPES]; |
10634 | } cursor[I915_MAX_PIPES]; |
10618 | 10635 | ||
10619 | struct intel_pipe_error_state { |
10636 | struct intel_pipe_error_state { |
10620 | u32 source; |
10637 | u32 source; |
10621 | } pipe[I915_MAX_PIPES]; |
10638 | } pipe[I915_MAX_PIPES]; |
10622 | 10639 | ||
10623 | struct intel_plane_error_state { |
10640 | struct intel_plane_error_state { |
10624 | u32 control; |
10641 | u32 control; |
10625 | u32 stride; |
10642 | u32 stride; |
10626 | u32 size; |
10643 | u32 size; |
10627 | u32 pos; |
10644 | u32 pos; |
10628 | u32 addr; |
10645 | u32 addr; |
10629 | u32 surface; |
10646 | u32 surface; |
10630 | u32 tile_offset; |
10647 | u32 tile_offset; |
10631 | } plane[I915_MAX_PIPES]; |
10648 | } plane[I915_MAX_PIPES]; |
10632 | 10649 | ||
10633 | struct intel_transcoder_error_state { |
10650 | struct intel_transcoder_error_state { |
10634 | enum transcoder cpu_transcoder; |
10651 | enum transcoder cpu_transcoder; |
10635 | 10652 | ||
10636 | u32 conf; |
10653 | u32 conf; |
10637 | 10654 | ||
10638 | u32 htotal; |
10655 | u32 htotal; |
10639 | u32 hblank; |
10656 | u32 hblank; |
10640 | u32 hsync; |
10657 | u32 hsync; |
10641 | u32 vtotal; |
10658 | u32 vtotal; |
10642 | u32 vblank; |
10659 | u32 vblank; |
10643 | u32 vsync; |
10660 | u32 vsync; |
10644 | } transcoder[4]; |
10661 | } transcoder[4]; |
10645 | }; |
10662 | }; |
10646 | 10663 | ||
10647 | struct intel_display_error_state * |
10664 | struct intel_display_error_state * |
10648 | intel_display_capture_error_state(struct drm_device *dev) |
10665 | intel_display_capture_error_state(struct drm_device *dev) |
10649 | { |
10666 | { |
10650 | drm_i915_private_t *dev_priv = dev->dev_private; |
10667 | drm_i915_private_t *dev_priv = dev->dev_private; |
10651 | struct intel_display_error_state *error; |
10668 | struct intel_display_error_state *error; |
10652 | int transcoders[] = { |
10669 | int transcoders[] = { |
10653 | TRANSCODER_A, |
10670 | TRANSCODER_A, |
10654 | TRANSCODER_B, |
10671 | TRANSCODER_B, |
10655 | TRANSCODER_C, |
10672 | TRANSCODER_C, |
10656 | TRANSCODER_EDP, |
10673 | TRANSCODER_EDP, |
10657 | }; |
10674 | }; |
10658 | int i; |
10675 | int i; |
10659 | 10676 | ||
10660 | if (INTEL_INFO(dev)->num_pipes == 0) |
10677 | if (INTEL_INFO(dev)->num_pipes == 0) |
10661 | return NULL; |
10678 | return NULL; |
10662 | 10679 | ||
10663 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10680 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10664 | if (error == NULL) |
10681 | if (error == NULL) |
10665 | return NULL; |
10682 | return NULL; |
10666 | 10683 | ||
10667 | if (HAS_POWER_WELL(dev)) |
10684 | if (HAS_POWER_WELL(dev)) |
10668 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
10685 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
10669 | 10686 | ||
10670 | for_each_pipe(i) { |
10687 | for_each_pipe(i) { |
10671 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10688 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10672 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
10689 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
10673 | error->cursor[i].position = I915_READ(CURPOS(i)); |
10690 | error->cursor[i].position = I915_READ(CURPOS(i)); |
10674 | error->cursor[i].base = I915_READ(CURBASE(i)); |
10691 | error->cursor[i].base = I915_READ(CURBASE(i)); |
10675 | } else { |
10692 | } else { |
10676 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
10693 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
10677 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
10694 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
10678 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
10695 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
10679 | } |
10696 | } |
10680 | 10697 | ||
10681 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
10698 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
10682 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
10699 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
10683 | if (INTEL_INFO(dev)->gen <= 3) { |
10700 | if (INTEL_INFO(dev)->gen <= 3) { |
10684 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
10701 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
10685 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10702 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10686 | } |
10703 | } |
10687 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10704 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10688 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
10705 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
10689 | if (INTEL_INFO(dev)->gen >= 4) { |
10706 | if (INTEL_INFO(dev)->gen >= 4) { |
10690 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
10707 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
10691 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
10708 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
10692 | } |
10709 | } |
10693 | 10710 | ||
10694 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
10711 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
10695 | } |
10712 | } |
10696 | 10713 | ||
10697 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
10714 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
10698 | if (HAS_DDI(dev_priv->dev)) |
10715 | if (HAS_DDI(dev_priv->dev)) |
10699 | error->num_transcoders++; /* Account for eDP. */ |
10716 | error->num_transcoders++; /* Account for eDP. */ |
10700 | 10717 | ||
10701 | for (i = 0; i < error->num_transcoders; i++) { |
10718 | for (i = 0; i < error->num_transcoders; i++) { |
10702 | enum transcoder cpu_transcoder = transcoders[i]; |
10719 | enum transcoder cpu_transcoder = transcoders[i]; |
10703 | 10720 | ||
10704 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
10721 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
10705 | 10722 | ||
10706 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
10723 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
10707 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
10724 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
10708 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
10725 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
10709 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
10726 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
10710 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
10727 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
10711 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
10728 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
10712 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
10729 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
10713 | } |
10730 | } |
10714 | 10731 | ||
10715 | /* In the code above we read the registers without checking if the power |
10732 | /* In the code above we read the registers without checking if the power |
10716 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
10733 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
10717 | * prevent the next I915_WRITE from detecting it and printing an error |
10734 | * prevent the next I915_WRITE from detecting it and printing an error |
10718 | * message. */ |
10735 | * message. */ |
10719 | intel_uncore_clear_errors(dev); |
10736 | intel_uncore_clear_errors(dev); |
10720 | 10737 | ||
10721 | return error; |
10738 | return error; |
10722 | } |
10739 | } |
10723 | 10740 | ||
10724 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10741 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10725 | 10742 | ||
10726 | void |
10743 | void |
10727 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
10744 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
10728 | struct drm_device *dev, |
10745 | struct drm_device *dev, |
10729 | struct intel_display_error_state *error) |
10746 | struct intel_display_error_state *error) |
10730 | { |
10747 | { |
10731 | int i; |
10748 | int i; |
10732 | 10749 | ||
10733 | if (!error) |
10750 | if (!error) |
10734 | return; |
10751 | return; |
10735 | 10752 | ||
10736 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
10753 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
10737 | if (HAS_POWER_WELL(dev)) |
10754 | if (HAS_POWER_WELL(dev)) |
10738 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
10755 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
10739 | error->power_well_driver); |
10756 | error->power_well_driver); |
10740 | for_each_pipe(i) { |
10757 | for_each_pipe(i) { |
10741 | err_printf(m, "Pipe [%d]:\n", i); |
10758 | err_printf(m, "Pipe [%d]:\n", i); |
10742 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
10759 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
10743 | 10760 | ||
10744 | err_printf(m, "Plane [%d]:\n", i); |
10761 | err_printf(m, "Plane [%d]:\n", i); |
10745 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
10762 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
10746 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
10763 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
10747 | if (INTEL_INFO(dev)->gen <= 3) { |
10764 | if (INTEL_INFO(dev)->gen <= 3) { |
10748 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10765 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10749 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
10766 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
10750 | } |
10767 | } |
10751 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10768 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10752 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
10769 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
10753 | if (INTEL_INFO(dev)->gen >= 4) { |
10770 | if (INTEL_INFO(dev)->gen >= 4) { |
10754 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10771 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10755 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
10772 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
10756 | } |
10773 | } |
10757 | 10774 | ||
10758 | err_printf(m, "Cursor [%d]:\n", i); |
10775 | err_printf(m, "Cursor [%d]:\n", i); |
10759 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
10776 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
10760 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
10777 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
10761 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
10778 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
10762 | } |
10779 | } |
10763 | 10780 | ||
10764 | for (i = 0; i < error->num_transcoders; i++) { |
10781 | for (i = 0; i < error->num_transcoders; i++) { |
10765 | err_printf(m, " CPU transcoder: %c\n", |
10782 | err_printf(m, " CPU transcoder: %c\n", |
10766 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
10783 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
10767 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
10784 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
10768 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
10785 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
10769 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
10786 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
10770 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
10787 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
10771 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
10788 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
10772 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
10789 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
10773 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
10790 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
10774 | } |
10791 | } |
10775 | } |
10792 | } |
10776 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>><>><>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>=><=>>><>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>=>=>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |
10793 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>><>><>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>=><=>>><>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>=>=>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |