Rev 4392 | Rev 4557 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4392 | Rev 4398 | ||
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Line 4558... | Line 4558... | ||
4558 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4558 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
Line 4559... | Line 4559... | ||
4559 | 4559 | ||
4560 | /* Enable DPIO clock input */ |
4560 | /* Enable DPIO clock input */ |
4561 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4561 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
- | 4562 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
|
4562 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4563 | /* We should never disable this, set it here for state tracking */ |
4563 | if (pipe) |
4564 | if (pipe == PIPE_B) |
4564 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
- | |
4565 | 4565 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
4566 | dpll |= DPLL_VCO_ENABLE; |
4566 | dpll |= DPLL_VCO_ENABLE; |
Line 4567... | Line 4567... | ||
4567 | crtc->config.dpll_hw_state.dpll = dpll; |
4567 | crtc->config.dpll_hw_state.dpll = dpll; |
4568 | 4568 | ||
Line 5020... | Line 5020... | ||
5020 | if (INTEL_INFO(dev)->gen < 5) |
5020 | if (INTEL_INFO(dev)->gen < 5) |
5021 | pipe_config->gmch_pfit.lvds_border_bits = |
5021 | pipe_config->gmch_pfit.lvds_border_bits = |
5022 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5022 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5023 | } |
5023 | } |
Line -... | Line 5024... | ||
- | 5024 | ||
- | 5025 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
|
- | 5026 | struct intel_crtc_config *pipe_config) |
|
- | 5027 | { |
|
- | 5028 | struct drm_device *dev = crtc->base.dev; |
|
- | 5029 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5030 | int pipe = pipe_config->cpu_transcoder; |
|
- | 5031 | intel_clock_t clock; |
|
- | 5032 | u32 mdiv; |
|
- | 5033 | int refclk = 100000; |
|
- | 5034 | ||
- | 5035 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 5036 | mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
|
- | 5037 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 5038 | ||
- | 5039 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
|
- | 5040 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
|
- | 5041 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
|
- | 5042 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
|
- | 5043 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
|
- | 5044 | ||
- | 5045 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
|
- | 5046 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
|
- | 5047 | ||
- | 5048 | pipe_config->adjusted_mode.clock = clock.dot / 10; |
|
- | 5049 | } |
|
5024 | 5050 | ||
5025 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5051 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5026 | struct intel_crtc_config *pipe_config) |
5052 | struct intel_crtc_config *pipe_config) |
5027 | { |
5053 | { |
5028 | struct drm_device *dev = crtc->base.dev; |
5054 | struct drm_device *dev = crtc->base.dev; |
Line 5551... | Line 5577... | ||
5551 | 5577 | ||
5552 | if (INTEL_INFO(dev)->gen > 6) { |
5578 | if (INTEL_INFO(dev)->gen > 6) { |
Line 5553... | Line 5579... | ||
5553 | uint16_t postoff = 0; |
5579 | uint16_t postoff = 0; |
5554 | 5580 | ||
Line 5555... | Line 5581... | ||
5555 | if (intel_crtc->config.limited_color_range) |
5581 | if (intel_crtc->config.limited_color_range) |
5556 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5582 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
5557 | 5583 | ||
Line 6067... | Line 6093... | ||
6067 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6093 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6068 | return; |
6094 | return; |
Line 6069... | Line 6095... | ||
6069 | 6095 | ||
6070 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6096 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6071 | * we'll hang the machine! */ |
6097 | * we'll hang the machine! */ |
Line 6072... | Line 6098... | ||
6072 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
6098 | gen6_gt_force_wake_get(dev_priv); |
6073 | 6099 | ||
6074 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6100 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6075 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6101 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
Line 6098... | Line 6124... | ||
6098 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6124 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6099 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6125 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6100 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6126 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6101 | } |
6127 | } |
Line 6102... | Line 6128... | ||
6102 | 6128 | ||
6103 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
6129 | gen6_gt_force_wake_put(dev_priv); |
Line 6104... | Line 6130... | ||
6104 | } |
6130 | } |
6105 | 6131 | ||
6106 | void hsw_enable_pc8_work(struct work_struct *__work) |
6132 | void hsw_enable_pc8_work(struct work_struct *__work) |
Line 9792... | Line 9818... | ||
9792 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9818 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9793 | dev_priv->display.off = ironlake_crtc_off; |
9819 | dev_priv->display.off = ironlake_crtc_off; |
9794 | dev_priv->display.update_plane = ironlake_update_plane; |
9820 | dev_priv->display.update_plane = ironlake_update_plane; |
9795 | } else if (IS_VALLEYVIEW(dev)) { |
9821 | } else if (IS_VALLEYVIEW(dev)) { |
9796 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9822 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9797 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9823 | dev_priv->display.get_clock = vlv_crtc_clock_get; |
9798 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9824 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9799 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9825 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9800 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9826 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9801 | dev_priv->display.off = i9xx_crtc_off; |
9827 | dev_priv->display.off = i9xx_crtc_off; |
9802 | dev_priv->display.update_plane = i9xx_update_plane; |
9828 | dev_priv->display.update_plane = i9xx_update_plane; |
Line 10026... | Line 10052... | ||
10026 | POSTING_READ(vga_reg); |
10052 | POSTING_READ(vga_reg); |
10027 | } |
10053 | } |
Line 10028... | Line 10054... | ||
10028 | 10054 | ||
10029 | void intel_modeset_init_hw(struct drm_device *dev) |
10055 | void intel_modeset_init_hw(struct drm_device *dev) |
- | 10056 | { |
|
- | 10057 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
10030 | { |
10058 | |
Line 10031... | Line 10059... | ||
10031 | intel_init_power_well(dev); |
10059 | intel_init_power_well(dev); |
Line 10032... | Line 10060... | ||
10032 | 10060 | ||
Line -... | Line 10061... | ||
- | 10061 | intel_prepare_ddi(dev); |
|
- | 10062 | ||
- | 10063 | intel_init_clock_gating(dev); |
|
- | 10064 | ||
- | 10065 | /* Enable the CRI clock source so we can get at the display */ |
|
10033 | intel_prepare_ddi(dev); |
10066 | if (IS_VALLEYVIEW(dev)) |
10034 | 10067 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
|
10035 | intel_init_clock_gating(dev); |
10068 | DPLL_INTEGRATED_CRI_CLK_VLV); |
10036 | 10069 | ||
Line -... | Line 10070... | ||
- | 10070 | mutex_lock(&dev->struct_mutex); |
|
- | 10071 | intel_enable_gt_powersave(dev); |
|
- | 10072 | mutex_unlock(&dev->struct_mutex); |
|
- | 10073 | } |
|
- | 10074 | ||
10037 | mutex_lock(&dev->struct_mutex); |
10075 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10038 | intel_enable_gt_powersave(dev); |
10076 | { |
10039 | mutex_unlock(&dev->struct_mutex); |
10077 | intel_suspend_hw(dev); |
10040 | } |
10078 | } |