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1 | /* |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | */ |
25 | */ |
26 | 26 | ||
27 | //#include |
27 | //#include |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | //#include |
33 | //#include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
42 | //#include |
42 | //#include |
43 | 43 | ||
44 | phys_addr_t get_bus_addr(void); |
44 | phys_addr_t get_bus_addr(void); |
45 | 45 | ||
46 | static inline __attribute__((const)) |
46 | static inline __attribute__((const)) |
47 | bool is_power_of_2(unsigned long n) |
47 | bool is_power_of_2(unsigned long n) |
48 | { |
48 | { |
49 | return (n != 0 && ((n & (n - 1)) == 0)); |
49 | return (n != 0 && ((n & (n - 1)) == 0)); |
50 | } |
50 | } |
51 | 51 | ||
52 | #define MAX_ERRNO 4095 |
52 | #define MAX_ERRNO 4095 |
53 | 53 | ||
54 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
54 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
55 | 55 | ||
56 | static inline long IS_ERR(const void *ptr) |
56 | static inline long IS_ERR(const void *ptr) |
57 | { |
57 | { |
58 | return IS_ERR_VALUE((unsigned long)ptr); |
58 | return IS_ERR_VALUE((unsigned long)ptr); |
59 | } |
59 | } |
60 | 60 | ||
61 | static inline void *ERR_PTR(long error) |
61 | static inline void *ERR_PTR(long error) |
62 | { |
62 | { |
63 | return (void *) error; |
63 | return (void *) error; |
64 | } |
64 | } |
65 | 65 | ||
66 | 66 | ||
67 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
67 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
68 | 68 | ||
69 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
69 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
70 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
70 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
71 | //static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
71 | //static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
72 | 72 | ||
73 | typedef struct { |
73 | typedef struct { |
74 | /* given values */ |
74 | /* given values */ |
75 | int n; |
75 | int n; |
76 | int m1, m2; |
76 | int m1, m2; |
77 | int p1, p2; |
77 | int p1, p2; |
78 | /* derived values */ |
78 | /* derived values */ |
79 | int dot; |
79 | int dot; |
80 | int vco; |
80 | int vco; |
81 | int m; |
81 | int m; |
82 | int p; |
82 | int p; |
83 | } intel_clock_t; |
83 | } intel_clock_t; |
84 | 84 | ||
85 | typedef struct { |
85 | typedef struct { |
86 | int min, max; |
86 | int min, max; |
87 | } intel_range_t; |
87 | } intel_range_t; |
88 | 88 | ||
89 | typedef struct { |
89 | typedef struct { |
90 | int dot_limit; |
90 | int dot_limit; |
91 | int p2_slow, p2_fast; |
91 | int p2_slow, p2_fast; |
92 | } intel_p2_t; |
92 | } intel_p2_t; |
93 | 93 | ||
94 | #define INTEL_P2_NUM 2 |
94 | #define INTEL_P2_NUM 2 |
95 | typedef struct intel_limit intel_limit_t; |
95 | typedef struct intel_limit intel_limit_t; |
96 | struct intel_limit { |
96 | struct intel_limit { |
97 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
97 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
98 | intel_p2_t p2; |
98 | intel_p2_t p2; |
99 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
99 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
100 | int, int, intel_clock_t *, intel_clock_t *); |
100 | int, int, intel_clock_t *, intel_clock_t *); |
101 | }; |
101 | }; |
102 | 102 | ||
103 | /* FDI */ |
103 | /* FDI */ |
104 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
104 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
105 | 105 | ||
106 | static bool |
106 | static bool |
107 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
107 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
108 | int target, int refclk, intel_clock_t *match_clock, |
108 | int target, int refclk, intel_clock_t *match_clock, |
109 | intel_clock_t *best_clock); |
109 | intel_clock_t *best_clock); |
110 | static bool |
110 | static bool |
111 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
111 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
112 | int target, int refclk, intel_clock_t *match_clock, |
112 | int target, int refclk, intel_clock_t *match_clock, |
113 | intel_clock_t *best_clock); |
113 | intel_clock_t *best_clock); |
114 | 114 | ||
115 | static bool |
115 | static bool |
116 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
116 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
117 | int target, int refclk, intel_clock_t *match_clock, |
117 | int target, int refclk, intel_clock_t *match_clock, |
118 | intel_clock_t *best_clock); |
118 | intel_clock_t *best_clock); |
119 | static bool |
119 | static bool |
120 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
120 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
121 | int target, int refclk, intel_clock_t *match_clock, |
121 | int target, int refclk, intel_clock_t *match_clock, |
122 | intel_clock_t *best_clock); |
122 | intel_clock_t *best_clock); |
123 | 123 | ||
124 | static bool |
124 | static bool |
125 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
125 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
126 | int target, int refclk, intel_clock_t *match_clock, |
126 | int target, int refclk, intel_clock_t *match_clock, |
127 | intel_clock_t *best_clock); |
127 | intel_clock_t *best_clock); |
128 | 128 | ||
129 | static inline u32 /* units of 100MHz */ |
129 | static inline u32 /* units of 100MHz */ |
130 | intel_fdi_link_freq(struct drm_device *dev) |
130 | intel_fdi_link_freq(struct drm_device *dev) |
131 | { |
131 | { |
132 | if (IS_GEN5(dev)) { |
132 | if (IS_GEN5(dev)) { |
133 | struct drm_i915_private *dev_priv = dev->dev_private; |
133 | struct drm_i915_private *dev_priv = dev->dev_private; |
134 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
134 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
135 | } else |
135 | } else |
136 | return 27; |
136 | return 27; |
137 | } |
137 | } |
138 | 138 | ||
139 | static const intel_limit_t intel_limits_i8xx_dvo = { |
139 | static const intel_limit_t intel_limits_i8xx_dvo = { |
140 | .dot = { .min = 25000, .max = 350000 }, |
140 | .dot = { .min = 25000, .max = 350000 }, |
141 | .vco = { .min = 930000, .max = 1400000 }, |
141 | .vco = { .min = 930000, .max = 1400000 }, |
142 | .n = { .min = 3, .max = 16 }, |
142 | .n = { .min = 3, .max = 16 }, |
143 | .m = { .min = 96, .max = 140 }, |
143 | .m = { .min = 96, .max = 140 }, |
144 | .m1 = { .min = 18, .max = 26 }, |
144 | .m1 = { .min = 18, .max = 26 }, |
145 | .m2 = { .min = 6, .max = 16 }, |
145 | .m2 = { .min = 6, .max = 16 }, |
146 | .p = { .min = 4, .max = 128 }, |
146 | .p = { .min = 4, .max = 128 }, |
147 | .p1 = { .min = 2, .max = 33 }, |
147 | .p1 = { .min = 2, .max = 33 }, |
148 | .p2 = { .dot_limit = 165000, |
148 | .p2 = { .dot_limit = 165000, |
149 | .p2_slow = 4, .p2_fast = 2 }, |
149 | .p2_slow = 4, .p2_fast = 2 }, |
150 | .find_pll = intel_find_best_PLL, |
150 | .find_pll = intel_find_best_PLL, |
151 | }; |
151 | }; |
152 | 152 | ||
153 | static const intel_limit_t intel_limits_i8xx_lvds = { |
153 | static const intel_limit_t intel_limits_i8xx_lvds = { |
154 | .dot = { .min = 25000, .max = 350000 }, |
154 | .dot = { .min = 25000, .max = 350000 }, |
155 | .vco = { .min = 930000, .max = 1400000 }, |
155 | .vco = { .min = 930000, .max = 1400000 }, |
156 | .n = { .min = 3, .max = 16 }, |
156 | .n = { .min = 3, .max = 16 }, |
157 | .m = { .min = 96, .max = 140 }, |
157 | .m = { .min = 96, .max = 140 }, |
158 | .m1 = { .min = 18, .max = 26 }, |
158 | .m1 = { .min = 18, .max = 26 }, |
159 | .m2 = { .min = 6, .max = 16 }, |
159 | .m2 = { .min = 6, .max = 16 }, |
160 | .p = { .min = 4, .max = 128 }, |
160 | .p = { .min = 4, .max = 128 }, |
161 | .p1 = { .min = 1, .max = 6 }, |
161 | .p1 = { .min = 1, .max = 6 }, |
162 | .p2 = { .dot_limit = 165000, |
162 | .p2 = { .dot_limit = 165000, |
163 | .p2_slow = 14, .p2_fast = 7 }, |
163 | .p2_slow = 14, .p2_fast = 7 }, |
164 | .find_pll = intel_find_best_PLL, |
164 | .find_pll = intel_find_best_PLL, |
165 | }; |
165 | }; |
166 | 166 | ||
167 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
167 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
168 | .dot = { .min = 20000, .max = 400000 }, |
168 | .dot = { .min = 20000, .max = 400000 }, |
169 | .vco = { .min = 1400000, .max = 2800000 }, |
169 | .vco = { .min = 1400000, .max = 2800000 }, |
170 | .n = { .min = 1, .max = 6 }, |
170 | .n = { .min = 1, .max = 6 }, |
171 | .m = { .min = 70, .max = 120 }, |
171 | .m = { .min = 70, .max = 120 }, |
172 | .m1 = { .min = 10, .max = 22 }, |
172 | .m1 = { .min = 10, .max = 22 }, |
173 | .m2 = { .min = 5, .max = 9 }, |
173 | .m2 = { .min = 5, .max = 9 }, |
174 | .p = { .min = 5, .max = 80 }, |
174 | .p = { .min = 5, .max = 80 }, |
175 | .p1 = { .min = 1, .max = 8 }, |
175 | .p1 = { .min = 1, .max = 8 }, |
176 | .p2 = { .dot_limit = 200000, |
176 | .p2 = { .dot_limit = 200000, |
177 | .p2_slow = 10, .p2_fast = 5 }, |
177 | .p2_slow = 10, .p2_fast = 5 }, |
178 | .find_pll = intel_find_best_PLL, |
178 | .find_pll = intel_find_best_PLL, |
179 | }; |
179 | }; |
180 | 180 | ||
181 | static const intel_limit_t intel_limits_i9xx_lvds = { |
181 | static const intel_limit_t intel_limits_i9xx_lvds = { |
182 | .dot = { .min = 20000, .max = 400000 }, |
182 | .dot = { .min = 20000, .max = 400000 }, |
183 | .vco = { .min = 1400000, .max = 2800000 }, |
183 | .vco = { .min = 1400000, .max = 2800000 }, |
184 | .n = { .min = 1, .max = 6 }, |
184 | .n = { .min = 1, .max = 6 }, |
185 | .m = { .min = 70, .max = 120 }, |
185 | .m = { .min = 70, .max = 120 }, |
186 | .m1 = { .min = 10, .max = 22 }, |
186 | .m1 = { .min = 10, .max = 22 }, |
187 | .m2 = { .min = 5, .max = 9 }, |
187 | .m2 = { .min = 5, .max = 9 }, |
188 | .p = { .min = 7, .max = 98 }, |
188 | .p = { .min = 7, .max = 98 }, |
189 | .p1 = { .min = 1, .max = 8 }, |
189 | .p1 = { .min = 1, .max = 8 }, |
190 | .p2 = { .dot_limit = 112000, |
190 | .p2 = { .dot_limit = 112000, |
191 | .p2_slow = 14, .p2_fast = 7 }, |
191 | .p2_slow = 14, .p2_fast = 7 }, |
192 | .find_pll = intel_find_best_PLL, |
192 | .find_pll = intel_find_best_PLL, |
193 | }; |
193 | }; |
194 | 194 | ||
195 | 195 | ||
196 | static const intel_limit_t intel_limits_g4x_sdvo = { |
196 | static const intel_limit_t intel_limits_g4x_sdvo = { |
197 | .dot = { .min = 25000, .max = 270000 }, |
197 | .dot = { .min = 25000, .max = 270000 }, |
198 | .vco = { .min = 1750000, .max = 3500000}, |
198 | .vco = { .min = 1750000, .max = 3500000}, |
199 | .n = { .min = 1, .max = 4 }, |
199 | .n = { .min = 1, .max = 4 }, |
200 | .m = { .min = 104, .max = 138 }, |
200 | .m = { .min = 104, .max = 138 }, |
201 | .m1 = { .min = 17, .max = 23 }, |
201 | .m1 = { .min = 17, .max = 23 }, |
202 | .m2 = { .min = 5, .max = 11 }, |
202 | .m2 = { .min = 5, .max = 11 }, |
203 | .p = { .min = 10, .max = 30 }, |
203 | .p = { .min = 10, .max = 30 }, |
204 | .p1 = { .min = 1, .max = 3}, |
204 | .p1 = { .min = 1, .max = 3}, |
205 | .p2 = { .dot_limit = 270000, |
205 | .p2 = { .dot_limit = 270000, |
206 | .p2_slow = 10, |
206 | .p2_slow = 10, |
207 | .p2_fast = 10 |
207 | .p2_fast = 10 |
208 | }, |
208 | }, |
209 | .find_pll = intel_g4x_find_best_PLL, |
209 | .find_pll = intel_g4x_find_best_PLL, |
210 | }; |
210 | }; |
211 | 211 | ||
212 | static const intel_limit_t intel_limits_g4x_hdmi = { |
212 | static const intel_limit_t intel_limits_g4x_hdmi = { |
213 | .dot = { .min = 22000, .max = 400000 }, |
213 | .dot = { .min = 22000, .max = 400000 }, |
214 | .vco = { .min = 1750000, .max = 3500000}, |
214 | .vco = { .min = 1750000, .max = 3500000}, |
215 | .n = { .min = 1, .max = 4 }, |
215 | .n = { .min = 1, .max = 4 }, |
216 | .m = { .min = 104, .max = 138 }, |
216 | .m = { .min = 104, .max = 138 }, |
217 | .m1 = { .min = 16, .max = 23 }, |
217 | .m1 = { .min = 16, .max = 23 }, |
218 | .m2 = { .min = 5, .max = 11 }, |
218 | .m2 = { .min = 5, .max = 11 }, |
219 | .p = { .min = 5, .max = 80 }, |
219 | .p = { .min = 5, .max = 80 }, |
220 | .p1 = { .min = 1, .max = 8}, |
220 | .p1 = { .min = 1, .max = 8}, |
221 | .p2 = { .dot_limit = 165000, |
221 | .p2 = { .dot_limit = 165000, |
222 | .p2_slow = 10, .p2_fast = 5 }, |
222 | .p2_slow = 10, .p2_fast = 5 }, |
223 | .find_pll = intel_g4x_find_best_PLL, |
223 | .find_pll = intel_g4x_find_best_PLL, |
224 | }; |
224 | }; |
225 | 225 | ||
226 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
226 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
227 | .dot = { .min = 20000, .max = 115000 }, |
227 | .dot = { .min = 20000, .max = 115000 }, |
228 | .vco = { .min = 1750000, .max = 3500000 }, |
228 | .vco = { .min = 1750000, .max = 3500000 }, |
229 | .n = { .min = 1, .max = 3 }, |
229 | .n = { .min = 1, .max = 3 }, |
230 | .m = { .min = 104, .max = 138 }, |
230 | .m = { .min = 104, .max = 138 }, |
231 | .m1 = { .min = 17, .max = 23 }, |
231 | .m1 = { .min = 17, .max = 23 }, |
232 | .m2 = { .min = 5, .max = 11 }, |
232 | .m2 = { .min = 5, .max = 11 }, |
233 | .p = { .min = 28, .max = 112 }, |
233 | .p = { .min = 28, .max = 112 }, |
234 | .p1 = { .min = 2, .max = 8 }, |
234 | .p1 = { .min = 2, .max = 8 }, |
235 | .p2 = { .dot_limit = 0, |
235 | .p2 = { .dot_limit = 0, |
236 | .p2_slow = 14, .p2_fast = 14 |
236 | .p2_slow = 14, .p2_fast = 14 |
237 | }, |
237 | }, |
238 | .find_pll = intel_g4x_find_best_PLL, |
238 | .find_pll = intel_g4x_find_best_PLL, |
239 | }; |
239 | }; |
240 | 240 | ||
241 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
241 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
242 | .dot = { .min = 80000, .max = 224000 }, |
242 | .dot = { .min = 80000, .max = 224000 }, |
243 | .vco = { .min = 1750000, .max = 3500000 }, |
243 | .vco = { .min = 1750000, .max = 3500000 }, |
244 | .n = { .min = 1, .max = 3 }, |
244 | .n = { .min = 1, .max = 3 }, |
245 | .m = { .min = 104, .max = 138 }, |
245 | .m = { .min = 104, .max = 138 }, |
246 | .m1 = { .min = 17, .max = 23 }, |
246 | .m1 = { .min = 17, .max = 23 }, |
247 | .m2 = { .min = 5, .max = 11 }, |
247 | .m2 = { .min = 5, .max = 11 }, |
248 | .p = { .min = 14, .max = 42 }, |
248 | .p = { .min = 14, .max = 42 }, |
249 | .p1 = { .min = 2, .max = 6 }, |
249 | .p1 = { .min = 2, .max = 6 }, |
250 | .p2 = { .dot_limit = 0, |
250 | .p2 = { .dot_limit = 0, |
251 | .p2_slow = 7, .p2_fast = 7 |
251 | .p2_slow = 7, .p2_fast = 7 |
252 | }, |
252 | }, |
253 | .find_pll = intel_g4x_find_best_PLL, |
253 | .find_pll = intel_g4x_find_best_PLL, |
254 | }; |
254 | }; |
255 | 255 | ||
256 | static const intel_limit_t intel_limits_g4x_display_port = { |
256 | static const intel_limit_t intel_limits_g4x_display_port = { |
257 | .dot = { .min = 161670, .max = 227000 }, |
257 | .dot = { .min = 161670, .max = 227000 }, |
258 | .vco = { .min = 1750000, .max = 3500000}, |
258 | .vco = { .min = 1750000, .max = 3500000}, |
259 | .n = { .min = 1, .max = 2 }, |
259 | .n = { .min = 1, .max = 2 }, |
260 | .m = { .min = 97, .max = 108 }, |
260 | .m = { .min = 97, .max = 108 }, |
261 | .m1 = { .min = 0x10, .max = 0x12 }, |
261 | .m1 = { .min = 0x10, .max = 0x12 }, |
262 | .m2 = { .min = 0x05, .max = 0x06 }, |
262 | .m2 = { .min = 0x05, .max = 0x06 }, |
263 | .p = { .min = 10, .max = 20 }, |
263 | .p = { .min = 10, .max = 20 }, |
264 | .p1 = { .min = 1, .max = 2}, |
264 | .p1 = { .min = 1, .max = 2}, |
265 | .p2 = { .dot_limit = 0, |
265 | .p2 = { .dot_limit = 0, |
266 | .p2_slow = 10, .p2_fast = 10 }, |
266 | .p2_slow = 10, .p2_fast = 10 }, |
267 | .find_pll = intel_find_pll_g4x_dp, |
267 | .find_pll = intel_find_pll_g4x_dp, |
268 | }; |
268 | }; |
269 | 269 | ||
270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
271 | .dot = { .min = 20000, .max = 400000}, |
271 | .dot = { .min = 20000, .max = 400000}, |
272 | .vco = { .min = 1700000, .max = 3500000 }, |
272 | .vco = { .min = 1700000, .max = 3500000 }, |
273 | /* Pineview's Ncounter is a ring counter */ |
273 | /* Pineview's Ncounter is a ring counter */ |
274 | .n = { .min = 3, .max = 6 }, |
274 | .n = { .min = 3, .max = 6 }, |
275 | .m = { .min = 2, .max = 256 }, |
275 | .m = { .min = 2, .max = 256 }, |
276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
277 | .m1 = { .min = 0, .max = 0 }, |
277 | .m1 = { .min = 0, .max = 0 }, |
278 | .m2 = { .min = 0, .max = 254 }, |
278 | .m2 = { .min = 0, .max = 254 }, |
279 | .p = { .min = 5, .max = 80 }, |
279 | .p = { .min = 5, .max = 80 }, |
280 | .p1 = { .min = 1, .max = 8 }, |
280 | .p1 = { .min = 1, .max = 8 }, |
281 | .p2 = { .dot_limit = 200000, |
281 | .p2 = { .dot_limit = 200000, |
282 | .p2_slow = 10, .p2_fast = 5 }, |
282 | .p2_slow = 10, .p2_fast = 5 }, |
283 | .find_pll = intel_find_best_PLL, |
283 | .find_pll = intel_find_best_PLL, |
284 | }; |
284 | }; |
285 | 285 | ||
286 | static const intel_limit_t intel_limits_pineview_lvds = { |
286 | static const intel_limit_t intel_limits_pineview_lvds = { |
287 | .dot = { .min = 20000, .max = 400000 }, |
287 | .dot = { .min = 20000, .max = 400000 }, |
288 | .vco = { .min = 1700000, .max = 3500000 }, |
288 | .vco = { .min = 1700000, .max = 3500000 }, |
289 | .n = { .min = 3, .max = 6 }, |
289 | .n = { .min = 3, .max = 6 }, |
290 | .m = { .min = 2, .max = 256 }, |
290 | .m = { .min = 2, .max = 256 }, |
291 | .m1 = { .min = 0, .max = 0 }, |
291 | .m1 = { .min = 0, .max = 0 }, |
292 | .m2 = { .min = 0, .max = 254 }, |
292 | .m2 = { .min = 0, .max = 254 }, |
293 | .p = { .min = 7, .max = 112 }, |
293 | .p = { .min = 7, .max = 112 }, |
294 | .p1 = { .min = 1, .max = 8 }, |
294 | .p1 = { .min = 1, .max = 8 }, |
295 | .p2 = { .dot_limit = 112000, |
295 | .p2 = { .dot_limit = 112000, |
296 | .p2_slow = 14, .p2_fast = 14 }, |
296 | .p2_slow = 14, .p2_fast = 14 }, |
297 | .find_pll = intel_find_best_PLL, |
297 | .find_pll = intel_find_best_PLL, |
298 | }; |
298 | }; |
299 | 299 | ||
300 | /* Ironlake / Sandybridge |
300 | /* Ironlake / Sandybridge |
301 | * |
301 | * |
302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
303 | * the range value for them is (actual_value - 2). |
303 | * the range value for them is (actual_value - 2). |
304 | */ |
304 | */ |
305 | static const intel_limit_t intel_limits_ironlake_dac = { |
305 | static const intel_limit_t intel_limits_ironlake_dac = { |
306 | .dot = { .min = 25000, .max = 350000 }, |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, |
308 | .n = { .min = 1, .max = 5 }, |
308 | .n = { .min = 1, .max = 5 }, |
309 | .m = { .min = 79, .max = 127 }, |
309 | .m = { .min = 79, .max = 127 }, |
310 | .m1 = { .min = 12, .max = 22 }, |
310 | .m1 = { .min = 12, .max = 22 }, |
311 | .m2 = { .min = 5, .max = 9 }, |
311 | .m2 = { .min = 5, .max = 9 }, |
312 | .p = { .min = 5, .max = 80 }, |
312 | .p = { .min = 5, .max = 80 }, |
313 | .p1 = { .min = 1, .max = 8 }, |
313 | .p1 = { .min = 1, .max = 8 }, |
314 | .p2 = { .dot_limit = 225000, |
314 | .p2 = { .dot_limit = 225000, |
315 | .p2_slow = 10, .p2_fast = 5 }, |
315 | .p2_slow = 10, .p2_fast = 5 }, |
316 | .find_pll = intel_g4x_find_best_PLL, |
316 | .find_pll = intel_g4x_find_best_PLL, |
317 | }; |
317 | }; |
318 | 318 | ||
319 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
319 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
320 | .dot = { .min = 25000, .max = 350000 }, |
320 | .dot = { .min = 25000, .max = 350000 }, |
321 | .vco = { .min = 1760000, .max = 3510000 }, |
321 | .vco = { .min = 1760000, .max = 3510000 }, |
322 | .n = { .min = 1, .max = 3 }, |
322 | .n = { .min = 1, .max = 3 }, |
323 | .m = { .min = 79, .max = 118 }, |
323 | .m = { .min = 79, .max = 118 }, |
324 | .m1 = { .min = 12, .max = 22 }, |
324 | .m1 = { .min = 12, .max = 22 }, |
325 | .m2 = { .min = 5, .max = 9 }, |
325 | .m2 = { .min = 5, .max = 9 }, |
326 | .p = { .min = 28, .max = 112 }, |
326 | .p = { .min = 28, .max = 112 }, |
327 | .p1 = { .min = 2, .max = 8 }, |
327 | .p1 = { .min = 2, .max = 8 }, |
328 | .p2 = { .dot_limit = 225000, |
328 | .p2 = { .dot_limit = 225000, |
329 | .p2_slow = 14, .p2_fast = 14 }, |
329 | .p2_slow = 14, .p2_fast = 14 }, |
330 | .find_pll = intel_g4x_find_best_PLL, |
330 | .find_pll = intel_g4x_find_best_PLL, |
331 | }; |
331 | }; |
332 | 332 | ||
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
334 | .dot = { .min = 25000, .max = 350000 }, |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, |
336 | .n = { .min = 1, .max = 3 }, |
336 | .n = { .min = 1, .max = 3 }, |
337 | .m = { .min = 79, .max = 127 }, |
337 | .m = { .min = 79, .max = 127 }, |
338 | .m1 = { .min = 12, .max = 22 }, |
338 | .m1 = { .min = 12, .max = 22 }, |
339 | .m2 = { .min = 5, .max = 9 }, |
339 | .m2 = { .min = 5, .max = 9 }, |
340 | .p = { .min = 14, .max = 56 }, |
340 | .p = { .min = 14, .max = 56 }, |
341 | .p1 = { .min = 2, .max = 8 }, |
341 | .p1 = { .min = 2, .max = 8 }, |
342 | .p2 = { .dot_limit = 225000, |
342 | .p2 = { .dot_limit = 225000, |
343 | .p2_slow = 7, .p2_fast = 7 }, |
343 | .p2_slow = 7, .p2_fast = 7 }, |
344 | .find_pll = intel_g4x_find_best_PLL, |
344 | .find_pll = intel_g4x_find_best_PLL, |
345 | }; |
345 | }; |
346 | 346 | ||
347 | /* LVDS 100mhz refclk limits. */ |
347 | /* LVDS 100mhz refclk limits. */ |
348 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
348 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
349 | .dot = { .min = 25000, .max = 350000 }, |
349 | .dot = { .min = 25000, .max = 350000 }, |
350 | .vco = { .min = 1760000, .max = 3510000 }, |
350 | .vco = { .min = 1760000, .max = 3510000 }, |
351 | .n = { .min = 1, .max = 2 }, |
351 | .n = { .min = 1, .max = 2 }, |
352 | .m = { .min = 79, .max = 126 }, |
352 | .m = { .min = 79, .max = 126 }, |
353 | .m1 = { .min = 12, .max = 22 }, |
353 | .m1 = { .min = 12, .max = 22 }, |
354 | .m2 = { .min = 5, .max = 9 }, |
354 | .m2 = { .min = 5, .max = 9 }, |
355 | .p = { .min = 28, .max = 112 }, |
355 | .p = { .min = 28, .max = 112 }, |
356 | .p1 = { .min = 2, .max = 8 }, |
356 | .p1 = { .min = 2, .max = 8 }, |
357 | .p2 = { .dot_limit = 225000, |
357 | .p2 = { .dot_limit = 225000, |
358 | .p2_slow = 14, .p2_fast = 14 }, |
358 | .p2_slow = 14, .p2_fast = 14 }, |
359 | .find_pll = intel_g4x_find_best_PLL, |
359 | .find_pll = intel_g4x_find_best_PLL, |
360 | }; |
360 | }; |
361 | 361 | ||
362 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
362 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
363 | .dot = { .min = 25000, .max = 350000 }, |
363 | .dot = { .min = 25000, .max = 350000 }, |
364 | .vco = { .min = 1760000, .max = 3510000 }, |
364 | .vco = { .min = 1760000, .max = 3510000 }, |
365 | .n = { .min = 1, .max = 3 }, |
365 | .n = { .min = 1, .max = 3 }, |
366 | .m = { .min = 79, .max = 126 }, |
366 | .m = { .min = 79, .max = 126 }, |
367 | .m1 = { .min = 12, .max = 22 }, |
367 | .m1 = { .min = 12, .max = 22 }, |
368 | .m2 = { .min = 5, .max = 9 }, |
368 | .m2 = { .min = 5, .max = 9 }, |
369 | .p = { .min = 14, .max = 42 }, |
369 | .p = { .min = 14, .max = 42 }, |
370 | .p1 = { .min = 2, .max = 6 }, |
370 | .p1 = { .min = 2, .max = 6 }, |
371 | .p2 = { .dot_limit = 225000, |
371 | .p2 = { .dot_limit = 225000, |
372 | .p2_slow = 7, .p2_fast = 7 }, |
372 | .p2_slow = 7, .p2_fast = 7 }, |
373 | .find_pll = intel_g4x_find_best_PLL, |
373 | .find_pll = intel_g4x_find_best_PLL, |
374 | }; |
374 | }; |
375 | 375 | ||
376 | static const intel_limit_t intel_limits_ironlake_display_port = { |
376 | static const intel_limit_t intel_limits_ironlake_display_port = { |
377 | .dot = { .min = 25000, .max = 350000 }, |
377 | .dot = { .min = 25000, .max = 350000 }, |
378 | .vco = { .min = 1760000, .max = 3510000}, |
378 | .vco = { .min = 1760000, .max = 3510000}, |
379 | .n = { .min = 1, .max = 2 }, |
379 | .n = { .min = 1, .max = 2 }, |
380 | .m = { .min = 81, .max = 90 }, |
380 | .m = { .min = 81, .max = 90 }, |
381 | .m1 = { .min = 12, .max = 22 }, |
381 | .m1 = { .min = 12, .max = 22 }, |
382 | .m2 = { .min = 5, .max = 9 }, |
382 | .m2 = { .min = 5, .max = 9 }, |
383 | .p = { .min = 10, .max = 20 }, |
383 | .p = { .min = 10, .max = 20 }, |
384 | .p1 = { .min = 1, .max = 2}, |
384 | .p1 = { .min = 1, .max = 2}, |
385 | .p2 = { .dot_limit = 0, |
385 | .p2 = { .dot_limit = 0, |
386 | .p2_slow = 10, .p2_fast = 10 }, |
386 | .p2_slow = 10, .p2_fast = 10 }, |
387 | .find_pll = intel_find_pll_ironlake_dp, |
387 | .find_pll = intel_find_pll_ironlake_dp, |
388 | }; |
388 | }; |
389 | 389 | ||
390 | static const intel_limit_t intel_limits_vlv_dac = { |
390 | static const intel_limit_t intel_limits_vlv_dac = { |
391 | .dot = { .min = 25000, .max = 270000 }, |
391 | .dot = { .min = 25000, .max = 270000 }, |
392 | .vco = { .min = 4000000, .max = 6000000 }, |
392 | .vco = { .min = 4000000, .max = 6000000 }, |
393 | .n = { .min = 1, .max = 7 }, |
393 | .n = { .min = 1, .max = 7 }, |
394 | .m = { .min = 22, .max = 450 }, /* guess */ |
394 | .m = { .min = 22, .max = 450 }, /* guess */ |
395 | .m1 = { .min = 2, .max = 3 }, |
395 | .m1 = { .min = 2, .max = 3 }, |
396 | .m2 = { .min = 11, .max = 156 }, |
396 | .m2 = { .min = 11, .max = 156 }, |
397 | .p = { .min = 10, .max = 30 }, |
397 | .p = { .min = 10, .max = 30 }, |
398 | .p1 = { .min = 2, .max = 3 }, |
398 | .p1 = { .min = 2, .max = 3 }, |
399 | .p2 = { .dot_limit = 270000, |
399 | .p2 = { .dot_limit = 270000, |
400 | .p2_slow = 2, .p2_fast = 20 }, |
400 | .p2_slow = 2, .p2_fast = 20 }, |
401 | .find_pll = intel_vlv_find_best_pll, |
401 | .find_pll = intel_vlv_find_best_pll, |
402 | }; |
402 | }; |
403 | 403 | ||
404 | static const intel_limit_t intel_limits_vlv_hdmi = { |
404 | static const intel_limit_t intel_limits_vlv_hdmi = { |
405 | .dot = { .min = 20000, .max = 165000 }, |
405 | .dot = { .min = 20000, .max = 165000 }, |
406 | .vco = { .min = 5994000, .max = 4000000 }, |
406 | .vco = { .min = 5994000, .max = 4000000 }, |
407 | .n = { .min = 1, .max = 7 }, |
407 | .n = { .min = 1, .max = 7 }, |
408 | .m = { .min = 60, .max = 300 }, /* guess */ |
408 | .m = { .min = 60, .max = 300 }, /* guess */ |
409 | .m1 = { .min = 2, .max = 3 }, |
409 | .m1 = { .min = 2, .max = 3 }, |
410 | .m2 = { .min = 11, .max = 156 }, |
410 | .m2 = { .min = 11, .max = 156 }, |
411 | .p = { .min = 10, .max = 30 }, |
411 | .p = { .min = 10, .max = 30 }, |
412 | .p1 = { .min = 2, .max = 3 }, |
412 | .p1 = { .min = 2, .max = 3 }, |
413 | .p2 = { .dot_limit = 270000, |
413 | .p2 = { .dot_limit = 270000, |
414 | .p2_slow = 2, .p2_fast = 20 }, |
414 | .p2_slow = 2, .p2_fast = 20 }, |
415 | .find_pll = intel_vlv_find_best_pll, |
415 | .find_pll = intel_vlv_find_best_pll, |
416 | }; |
416 | }; |
417 | 417 | ||
418 | static const intel_limit_t intel_limits_vlv_dp = { |
418 | static const intel_limit_t intel_limits_vlv_dp = { |
419 | .dot = { .min = 162000, .max = 270000 }, |
419 | .dot = { .min = 162000, .max = 270000 }, |
420 | .vco = { .min = 5994000, .max = 4000000 }, |
420 | .vco = { .min = 5994000, .max = 4000000 }, |
421 | .n = { .min = 1, .max = 7 }, |
421 | .n = { .min = 1, .max = 7 }, |
422 | .m = { .min = 60, .max = 300 }, /* guess */ |
422 | .m = { .min = 60, .max = 300 }, /* guess */ |
423 | .m1 = { .min = 2, .max = 3 }, |
423 | .m1 = { .min = 2, .max = 3 }, |
424 | .m2 = { .min = 11, .max = 156 }, |
424 | .m2 = { .min = 11, .max = 156 }, |
425 | .p = { .min = 10, .max = 30 }, |
425 | .p = { .min = 10, .max = 30 }, |
426 | .p1 = { .min = 2, .max = 3 }, |
426 | .p1 = { .min = 2, .max = 3 }, |
427 | .p2 = { .dot_limit = 270000, |
427 | .p2 = { .dot_limit = 270000, |
428 | .p2_slow = 2, .p2_fast = 20 }, |
428 | .p2_slow = 2, .p2_fast = 20 }, |
429 | .find_pll = intel_vlv_find_best_pll, |
429 | .find_pll = intel_vlv_find_best_pll, |
430 | }; |
430 | }; |
431 | 431 | ||
432 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
432 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
433 | { |
433 | { |
434 | unsigned long flags; |
434 | unsigned long flags; |
435 | u32 val = 0; |
435 | u32 val = 0; |
436 | 436 | ||
437 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
437 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
438 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
438 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
439 | DRM_ERROR("DPIO idle wait timed out\n"); |
439 | DRM_ERROR("DPIO idle wait timed out\n"); |
440 | goto out_unlock; |
440 | goto out_unlock; |
441 | } |
441 | } |
442 | 442 | ||
443 | I915_WRITE(DPIO_REG, reg); |
443 | I915_WRITE(DPIO_REG, reg); |
444 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | |
444 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | |
445 | DPIO_BYTE); |
445 | DPIO_BYTE); |
446 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
446 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
447 | DRM_ERROR("DPIO read wait timed out\n"); |
447 | DRM_ERROR("DPIO read wait timed out\n"); |
448 | goto out_unlock; |
448 | goto out_unlock; |
449 | } |
449 | } |
450 | val = I915_READ(DPIO_DATA); |
450 | val = I915_READ(DPIO_DATA); |
451 | 451 | ||
452 | out_unlock: |
452 | out_unlock: |
453 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
453 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
454 | return val; |
454 | return val; |
455 | } |
455 | } |
456 | 456 | ||
457 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
457 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
458 | u32 val) |
458 | u32 val) |
459 | { |
459 | { |
460 | unsigned long flags; |
460 | unsigned long flags; |
461 | 461 | ||
462 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
462 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
463 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
463 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
464 | DRM_ERROR("DPIO idle wait timed out\n"); |
464 | DRM_ERROR("DPIO idle wait timed out\n"); |
465 | goto out_unlock; |
465 | goto out_unlock; |
466 | } |
466 | } |
467 | 467 | ||
468 | I915_WRITE(DPIO_DATA, val); |
468 | I915_WRITE(DPIO_DATA, val); |
469 | I915_WRITE(DPIO_REG, reg); |
469 | I915_WRITE(DPIO_REG, reg); |
470 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | |
470 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | |
471 | DPIO_BYTE); |
471 | DPIO_BYTE); |
472 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) |
472 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) |
473 | DRM_ERROR("DPIO write wait timed out\n"); |
473 | DRM_ERROR("DPIO write wait timed out\n"); |
474 | 474 | ||
475 | out_unlock: |
475 | out_unlock: |
476 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
476 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
477 | } |
477 | } |
478 | 478 | ||
479 | static void vlv_init_dpio(struct drm_device *dev) |
479 | static void vlv_init_dpio(struct drm_device *dev) |
480 | { |
480 | { |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
482 | 482 | ||
483 | /* Reset the DPIO config */ |
483 | /* Reset the DPIO config */ |
484 | I915_WRITE(DPIO_CTL, 0); |
484 | I915_WRITE(DPIO_CTL, 0); |
485 | POSTING_READ(DPIO_CTL); |
485 | POSTING_READ(DPIO_CTL); |
486 | I915_WRITE(DPIO_CTL, 1); |
486 | I915_WRITE(DPIO_CTL, 1); |
487 | POSTING_READ(DPIO_CTL); |
487 | POSTING_READ(DPIO_CTL); |
488 | } |
488 | } |
489 | 489 | ||
490 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
490 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
491 | { |
491 | { |
492 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
492 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
493 | return 1; |
493 | return 1; |
494 | } |
494 | } |
495 | 495 | ||
496 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
496 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
497 | { |
497 | { |
498 | .callback = intel_dual_link_lvds_callback, |
498 | .callback = intel_dual_link_lvds_callback, |
499 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", |
499 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", |
500 | .matches = { |
500 | .matches = { |
501 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
501 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
502 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
502 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
503 | }, |
503 | }, |
504 | }, |
504 | }, |
505 | { } /* terminating entry */ |
505 | { } /* terminating entry */ |
506 | }; |
506 | }; |
507 | 507 | ||
508 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
508 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
509 | unsigned int reg) |
509 | unsigned int reg) |
510 | { |
510 | { |
511 | unsigned int val; |
511 | unsigned int val; |
512 | 512 | ||
513 | /* use the module option value if specified */ |
513 | /* use the module option value if specified */ |
514 | if (i915_lvds_channel_mode > 0) |
514 | if (i915_lvds_channel_mode > 0) |
515 | return i915_lvds_channel_mode == 2; |
515 | return i915_lvds_channel_mode == 2; |
516 | 516 | ||
517 | // if (dmi_check_system(intel_dual_link_lvds)) |
517 | // if (dmi_check_system(intel_dual_link_lvds)) |
518 | // return true; |
518 | // return true; |
519 | 519 | ||
520 | if (dev_priv->lvds_val) |
520 | if (dev_priv->lvds_val) |
521 | val = dev_priv->lvds_val; |
521 | val = dev_priv->lvds_val; |
522 | else { |
522 | else { |
523 | /* BIOS should set the proper LVDS register value at boot, but |
523 | /* BIOS should set the proper LVDS register value at boot, but |
524 | * in reality, it doesn't set the value when the lid is closed; |
524 | * in reality, it doesn't set the value when the lid is closed; |
525 | * we need to check "the value to be set" in VBT when LVDS |
525 | * we need to check "the value to be set" in VBT when LVDS |
526 | * register is uninitialized. |
526 | * register is uninitialized. |
527 | */ |
527 | */ |
528 | val = I915_READ(reg); |
528 | val = I915_READ(reg); |
529 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
529 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
530 | val = dev_priv->bios_lvds_val; |
530 | val = dev_priv->bios_lvds_val; |
531 | dev_priv->lvds_val = val; |
531 | dev_priv->lvds_val = val; |
532 | } |
532 | } |
533 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
533 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
534 | } |
534 | } |
535 | 535 | ||
536 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
536 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
537 | int refclk) |
537 | int refclk) |
538 | { |
538 | { |
539 | struct drm_device *dev = crtc->dev; |
539 | struct drm_device *dev = crtc->dev; |
540 | struct drm_i915_private *dev_priv = dev->dev_private; |
540 | struct drm_i915_private *dev_priv = dev->dev_private; |
541 | const intel_limit_t *limit; |
541 | const intel_limit_t *limit; |
542 | 542 | ||
543 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
543 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
544 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
544 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
545 | /* LVDS dual channel */ |
545 | /* LVDS dual channel */ |
546 | if (refclk == 100000) |
546 | if (refclk == 100000) |
547 | limit = &intel_limits_ironlake_dual_lvds_100m; |
547 | limit = &intel_limits_ironlake_dual_lvds_100m; |
548 | else |
548 | else |
549 | limit = &intel_limits_ironlake_dual_lvds; |
549 | limit = &intel_limits_ironlake_dual_lvds; |
550 | } else { |
550 | } else { |
551 | if (refclk == 100000) |
551 | if (refclk == 100000) |
552 | limit = &intel_limits_ironlake_single_lvds_100m; |
552 | limit = &intel_limits_ironlake_single_lvds_100m; |
553 | else |
553 | else |
554 | limit = &intel_limits_ironlake_single_lvds; |
554 | limit = &intel_limits_ironlake_single_lvds; |
555 | } |
555 | } |
556 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
556 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
557 | HAS_eDP) |
557 | HAS_eDP) |
558 | limit = &intel_limits_ironlake_display_port; |
558 | limit = &intel_limits_ironlake_display_port; |
559 | else |
559 | else |
560 | limit = &intel_limits_ironlake_dac; |
560 | limit = &intel_limits_ironlake_dac; |
561 | 561 | ||
562 | return limit; |
562 | return limit; |
563 | } |
563 | } |
564 | 564 | ||
565 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
565 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
566 | { |
566 | { |
567 | struct drm_device *dev = crtc->dev; |
567 | struct drm_device *dev = crtc->dev; |
568 | struct drm_i915_private *dev_priv = dev->dev_private; |
568 | struct drm_i915_private *dev_priv = dev->dev_private; |
569 | const intel_limit_t *limit; |
569 | const intel_limit_t *limit; |
570 | 570 | ||
571 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
571 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
572 | if (is_dual_link_lvds(dev_priv, LVDS)) |
572 | if (is_dual_link_lvds(dev_priv, LVDS)) |
573 | /* LVDS with dual channel */ |
573 | /* LVDS with dual channel */ |
574 | limit = &intel_limits_g4x_dual_channel_lvds; |
574 | limit = &intel_limits_g4x_dual_channel_lvds; |
575 | else |
575 | else |
576 | /* LVDS with dual channel */ |
576 | /* LVDS with dual channel */ |
577 | limit = &intel_limits_g4x_single_channel_lvds; |
577 | limit = &intel_limits_g4x_single_channel_lvds; |
578 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
578 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
579 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
579 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
580 | limit = &intel_limits_g4x_hdmi; |
580 | limit = &intel_limits_g4x_hdmi; |
581 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
581 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
582 | limit = &intel_limits_g4x_sdvo; |
582 | limit = &intel_limits_g4x_sdvo; |
583 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
583 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
584 | limit = &intel_limits_g4x_display_port; |
584 | limit = &intel_limits_g4x_display_port; |
585 | } else /* The option is for other outputs */ |
585 | } else /* The option is for other outputs */ |
586 | limit = &intel_limits_i9xx_sdvo; |
586 | limit = &intel_limits_i9xx_sdvo; |
587 | 587 | ||
588 | return limit; |
588 | return limit; |
589 | } |
589 | } |
590 | 590 | ||
591 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
591 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
592 | { |
592 | { |
593 | struct drm_device *dev = crtc->dev; |
593 | struct drm_device *dev = crtc->dev; |
594 | const intel_limit_t *limit; |
594 | const intel_limit_t *limit; |
595 | 595 | ||
596 | if (HAS_PCH_SPLIT(dev)) |
596 | if (HAS_PCH_SPLIT(dev)) |
597 | limit = intel_ironlake_limit(crtc, refclk); |
597 | limit = intel_ironlake_limit(crtc, refclk); |
598 | else if (IS_G4X(dev)) { |
598 | else if (IS_G4X(dev)) { |
599 | limit = intel_g4x_limit(crtc); |
599 | limit = intel_g4x_limit(crtc); |
600 | } else if (IS_PINEVIEW(dev)) { |
600 | } else if (IS_PINEVIEW(dev)) { |
601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
602 | limit = &intel_limits_pineview_lvds; |
602 | limit = &intel_limits_pineview_lvds; |
603 | else |
603 | else |
604 | limit = &intel_limits_pineview_sdvo; |
604 | limit = &intel_limits_pineview_sdvo; |
605 | } else if (IS_VALLEYVIEW(dev)) { |
605 | } else if (IS_VALLEYVIEW(dev)) { |
606 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
606 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
607 | limit = &intel_limits_vlv_dac; |
607 | limit = &intel_limits_vlv_dac; |
608 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
608 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
609 | limit = &intel_limits_vlv_hdmi; |
609 | limit = &intel_limits_vlv_hdmi; |
610 | else |
610 | else |
611 | limit = &intel_limits_vlv_dp; |
611 | limit = &intel_limits_vlv_dp; |
612 | } else if (!IS_GEN2(dev)) { |
612 | } else if (!IS_GEN2(dev)) { |
613 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
613 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
614 | limit = &intel_limits_i9xx_lvds; |
614 | limit = &intel_limits_i9xx_lvds; |
615 | else |
615 | else |
616 | limit = &intel_limits_i9xx_sdvo; |
616 | limit = &intel_limits_i9xx_sdvo; |
617 | } else { |
617 | } else { |
618 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
618 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
619 | limit = &intel_limits_i8xx_lvds; |
619 | limit = &intel_limits_i8xx_lvds; |
620 | else |
620 | else |
621 | limit = &intel_limits_i8xx_dvo; |
621 | limit = &intel_limits_i8xx_dvo; |
622 | } |
622 | } |
623 | return limit; |
623 | return limit; |
624 | } |
624 | } |
625 | 625 | ||
626 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
626 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
627 | static void pineview_clock(int refclk, intel_clock_t *clock) |
627 | static void pineview_clock(int refclk, intel_clock_t *clock) |
628 | { |
628 | { |
629 | clock->m = clock->m2 + 2; |
629 | clock->m = clock->m2 + 2; |
630 | clock->p = clock->p1 * clock->p2; |
630 | clock->p = clock->p1 * clock->p2; |
631 | clock->vco = refclk * clock->m / clock->n; |
631 | clock->vco = refclk * clock->m / clock->n; |
632 | clock->dot = clock->vco / clock->p; |
632 | clock->dot = clock->vco / clock->p; |
633 | } |
633 | } |
634 | 634 | ||
635 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
635 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
636 | { |
636 | { |
637 | if (IS_PINEVIEW(dev)) { |
637 | if (IS_PINEVIEW(dev)) { |
638 | pineview_clock(refclk, clock); |
638 | pineview_clock(refclk, clock); |
639 | return; |
639 | return; |
640 | } |
640 | } |
641 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
641 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
642 | clock->p = clock->p1 * clock->p2; |
642 | clock->p = clock->p1 * clock->p2; |
643 | clock->vco = refclk * clock->m / (clock->n + 2); |
643 | clock->vco = refclk * clock->m / (clock->n + 2); |
644 | clock->dot = clock->vco / clock->p; |
644 | clock->dot = clock->vco / clock->p; |
645 | } |
645 | } |
646 | 646 | ||
647 | /** |
647 | /** |
648 | * Returns whether any output on the specified pipe is of the specified type |
648 | * Returns whether any output on the specified pipe is of the specified type |
649 | */ |
649 | */ |
650 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
650 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
651 | { |
651 | { |
652 | struct drm_device *dev = crtc->dev; |
652 | struct drm_device *dev = crtc->dev; |
653 | struct intel_encoder *encoder; |
653 | struct intel_encoder *encoder; |
654 | 654 | ||
655 | for_each_encoder_on_crtc(dev, crtc, encoder) |
655 | for_each_encoder_on_crtc(dev, crtc, encoder) |
656 | if (encoder->type == type) |
656 | if (encoder->type == type) |
657 | return true; |
657 | return true; |
658 | 658 | ||
659 | return false; |
659 | return false; |
660 | } |
660 | } |
661 | 661 | ||
662 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
662 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
663 | /** |
663 | /** |
664 | * Returns whether the given set of divisors are valid for a given refclk with |
664 | * Returns whether the given set of divisors are valid for a given refclk with |
665 | * the given connectors. |
665 | * the given connectors. |
666 | */ |
666 | */ |
667 | 667 | ||
668 | static bool intel_PLL_is_valid(struct drm_device *dev, |
668 | static bool intel_PLL_is_valid(struct drm_device *dev, |
669 | const intel_limit_t *limit, |
669 | const intel_limit_t *limit, |
670 | const intel_clock_t *clock) |
670 | const intel_clock_t *clock) |
671 | { |
671 | { |
672 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
672 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
673 | INTELPllInvalid("p1 out of range\n"); |
673 | INTELPllInvalid("p1 out of range\n"); |
674 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
674 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
675 | INTELPllInvalid("p out of range\n"); |
675 | INTELPllInvalid("p out of range\n"); |
676 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
676 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
677 | INTELPllInvalid("m2 out of range\n"); |
677 | INTELPllInvalid("m2 out of range\n"); |
678 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
678 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
679 | INTELPllInvalid("m1 out of range\n"); |
679 | INTELPllInvalid("m1 out of range\n"); |
680 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
680 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
681 | INTELPllInvalid("m1 <= m2\n"); |
681 | INTELPllInvalid("m1 <= m2\n"); |
682 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
682 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
683 | INTELPllInvalid("m out of range\n"); |
683 | INTELPllInvalid("m out of range\n"); |
684 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
684 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
685 | INTELPllInvalid("n out of range\n"); |
685 | INTELPllInvalid("n out of range\n"); |
686 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
686 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
687 | INTELPllInvalid("vco out of range\n"); |
687 | INTELPllInvalid("vco out of range\n"); |
688 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
688 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
689 | * connector, etc., rather than just a single range. |
689 | * connector, etc., rather than just a single range. |
690 | */ |
690 | */ |
691 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
691 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
692 | INTELPllInvalid("dot out of range\n"); |
692 | INTELPllInvalid("dot out of range\n"); |
693 | 693 | ||
694 | return true; |
694 | return true; |
695 | } |
695 | } |
696 | 696 | ||
697 | static bool |
697 | static bool |
698 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
698 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
699 | int target, int refclk, intel_clock_t *match_clock, |
699 | int target, int refclk, intel_clock_t *match_clock, |
700 | intel_clock_t *best_clock) |
700 | intel_clock_t *best_clock) |
701 | 701 | ||
702 | { |
702 | { |
703 | struct drm_device *dev = crtc->dev; |
703 | struct drm_device *dev = crtc->dev; |
704 | struct drm_i915_private *dev_priv = dev->dev_private; |
704 | struct drm_i915_private *dev_priv = dev->dev_private; |
705 | intel_clock_t clock; |
705 | intel_clock_t clock; |
706 | int err = target; |
706 | int err = target; |
707 | 707 | ||
708 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
708 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
709 | (I915_READ(LVDS)) != 0) { |
709 | (I915_READ(LVDS)) != 0) { |
710 | /* |
710 | /* |
711 | * For LVDS, if the panel is on, just rely on its current |
711 | * For LVDS, if the panel is on, just rely on its current |
712 | * settings for dual-channel. We haven't figured out how to |
712 | * settings for dual-channel. We haven't figured out how to |
713 | * reliably set up different single/dual channel state, if we |
713 | * reliably set up different single/dual channel state, if we |
714 | * even can. |
714 | * even can. |
715 | */ |
715 | */ |
716 | if (is_dual_link_lvds(dev_priv, LVDS)) |
716 | if (is_dual_link_lvds(dev_priv, LVDS)) |
717 | clock.p2 = limit->p2.p2_fast; |
717 | clock.p2 = limit->p2.p2_fast; |
718 | else |
718 | else |
719 | clock.p2 = limit->p2.p2_slow; |
719 | clock.p2 = limit->p2.p2_slow; |
720 | } else { |
720 | } else { |
721 | if (target < limit->p2.dot_limit) |
721 | if (target < limit->p2.dot_limit) |
722 | clock.p2 = limit->p2.p2_slow; |
722 | clock.p2 = limit->p2.p2_slow; |
723 | else |
723 | else |
724 | clock.p2 = limit->p2.p2_fast; |
724 | clock.p2 = limit->p2.p2_fast; |
725 | } |
725 | } |
726 | 726 | ||
727 | memset(best_clock, 0, sizeof(*best_clock)); |
727 | memset(best_clock, 0, sizeof(*best_clock)); |
728 | 728 | ||
729 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
729 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
730 | clock.m1++) { |
730 | clock.m1++) { |
731 | for (clock.m2 = limit->m2.min; |
731 | for (clock.m2 = limit->m2.min; |
732 | clock.m2 <= limit->m2.max; clock.m2++) { |
732 | clock.m2 <= limit->m2.max; clock.m2++) { |
733 | /* m1 is always 0 in Pineview */ |
733 | /* m1 is always 0 in Pineview */ |
734 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
734 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
735 | break; |
735 | break; |
736 | for (clock.n = limit->n.min; |
736 | for (clock.n = limit->n.min; |
737 | clock.n <= limit->n.max; clock.n++) { |
737 | clock.n <= limit->n.max; clock.n++) { |
738 | for (clock.p1 = limit->p1.min; |
738 | for (clock.p1 = limit->p1.min; |
739 | clock.p1 <= limit->p1.max; clock.p1++) { |
739 | clock.p1 <= limit->p1.max; clock.p1++) { |
740 | int this_err; |
740 | int this_err; |
741 | 741 | ||
742 | intel_clock(dev, refclk, &clock); |
742 | intel_clock(dev, refclk, &clock); |
743 | if (!intel_PLL_is_valid(dev, limit, |
743 | if (!intel_PLL_is_valid(dev, limit, |
744 | &clock)) |
744 | &clock)) |
745 | continue; |
745 | continue; |
746 | if (match_clock && |
746 | if (match_clock && |
747 | clock.p != match_clock->p) |
747 | clock.p != match_clock->p) |
748 | continue; |
748 | continue; |
749 | 749 | ||
750 | this_err = abs(clock.dot - target); |
750 | this_err = abs(clock.dot - target); |
751 | if (this_err < err) { |
751 | if (this_err < err) { |
752 | *best_clock = clock; |
752 | *best_clock = clock; |
753 | err = this_err; |
753 | err = this_err; |
754 | } |
754 | } |
755 | } |
755 | } |
756 | } |
756 | } |
757 | } |
757 | } |
758 | } |
758 | } |
759 | 759 | ||
760 | return (err != target); |
760 | return (err != target); |
761 | } |
761 | } |
762 | 762 | ||
763 | static bool |
763 | static bool |
764 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
764 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
765 | int target, int refclk, intel_clock_t *match_clock, |
765 | int target, int refclk, intel_clock_t *match_clock, |
766 | intel_clock_t *best_clock) |
766 | intel_clock_t *best_clock) |
767 | { |
767 | { |
768 | struct drm_device *dev = crtc->dev; |
768 | struct drm_device *dev = crtc->dev; |
769 | struct drm_i915_private *dev_priv = dev->dev_private; |
769 | struct drm_i915_private *dev_priv = dev->dev_private; |
770 | intel_clock_t clock; |
770 | intel_clock_t clock; |
771 | int max_n; |
771 | int max_n; |
772 | bool found; |
772 | bool found; |
773 | /* approximately equals target * 0.00585 */ |
773 | /* approximately equals target * 0.00585 */ |
774 | int err_most = (target >> 8) + (target >> 9); |
774 | int err_most = (target >> 8) + (target >> 9); |
775 | found = false; |
775 | found = false; |
776 | 776 | ||
777 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
777 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
778 | int lvds_reg; |
778 | int lvds_reg; |
779 | 779 | ||
780 | if (HAS_PCH_SPLIT(dev)) |
780 | if (HAS_PCH_SPLIT(dev)) |
781 | lvds_reg = PCH_LVDS; |
781 | lvds_reg = PCH_LVDS; |
782 | else |
782 | else |
783 | lvds_reg = LVDS; |
783 | lvds_reg = LVDS; |
784 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
784 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
785 | LVDS_CLKB_POWER_UP) |
785 | LVDS_CLKB_POWER_UP) |
786 | clock.p2 = limit->p2.p2_fast; |
786 | clock.p2 = limit->p2.p2_fast; |
787 | else |
787 | else |
788 | clock.p2 = limit->p2.p2_slow; |
788 | clock.p2 = limit->p2.p2_slow; |
789 | } else { |
789 | } else { |
790 | if (target < limit->p2.dot_limit) |
790 | if (target < limit->p2.dot_limit) |
791 | clock.p2 = limit->p2.p2_slow; |
791 | clock.p2 = limit->p2.p2_slow; |
792 | else |
792 | else |
793 | clock.p2 = limit->p2.p2_fast; |
793 | clock.p2 = limit->p2.p2_fast; |
794 | } |
794 | } |
795 | 795 | ||
796 | memset(best_clock, 0, sizeof(*best_clock)); |
796 | memset(best_clock, 0, sizeof(*best_clock)); |
797 | max_n = limit->n.max; |
797 | max_n = limit->n.max; |
798 | /* based on hardware requirement, prefer smaller n to precision */ |
798 | /* based on hardware requirement, prefer smaller n to precision */ |
799 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
799 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
800 | /* based on hardware requirement, prefere larger m1,m2 */ |
800 | /* based on hardware requirement, prefere larger m1,m2 */ |
801 | for (clock.m1 = limit->m1.max; |
801 | for (clock.m1 = limit->m1.max; |
802 | clock.m1 >= limit->m1.min; clock.m1--) { |
802 | clock.m1 >= limit->m1.min; clock.m1--) { |
803 | for (clock.m2 = limit->m2.max; |
803 | for (clock.m2 = limit->m2.max; |
804 | clock.m2 >= limit->m2.min; clock.m2--) { |
804 | clock.m2 >= limit->m2.min; clock.m2--) { |
805 | for (clock.p1 = limit->p1.max; |
805 | for (clock.p1 = limit->p1.max; |
806 | clock.p1 >= limit->p1.min; clock.p1--) { |
806 | clock.p1 >= limit->p1.min; clock.p1--) { |
807 | int this_err; |
807 | int this_err; |
808 | 808 | ||
809 | intel_clock(dev, refclk, &clock); |
809 | intel_clock(dev, refclk, &clock); |
810 | if (!intel_PLL_is_valid(dev, limit, |
810 | if (!intel_PLL_is_valid(dev, limit, |
811 | &clock)) |
811 | &clock)) |
812 | continue; |
812 | continue; |
813 | if (match_clock && |
813 | if (match_clock && |
814 | clock.p != match_clock->p) |
814 | clock.p != match_clock->p) |
815 | continue; |
815 | continue; |
816 | 816 | ||
817 | this_err = abs(clock.dot - target); |
817 | this_err = abs(clock.dot - target); |
818 | if (this_err < err_most) { |
818 | if (this_err < err_most) { |
819 | *best_clock = clock; |
819 | *best_clock = clock; |
820 | err_most = this_err; |
820 | err_most = this_err; |
821 | max_n = clock.n; |
821 | max_n = clock.n; |
822 | found = true; |
822 | found = true; |
823 | } |
823 | } |
824 | } |
824 | } |
825 | } |
825 | } |
826 | } |
826 | } |
827 | } |
827 | } |
828 | return found; |
828 | return found; |
829 | } |
829 | } |
830 | 830 | ||
831 | static bool |
831 | static bool |
832 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
832 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
833 | int target, int refclk, intel_clock_t *match_clock, |
833 | int target, int refclk, intel_clock_t *match_clock, |
834 | intel_clock_t *best_clock) |
834 | intel_clock_t *best_clock) |
835 | { |
835 | { |
836 | struct drm_device *dev = crtc->dev; |
836 | struct drm_device *dev = crtc->dev; |
837 | intel_clock_t clock; |
837 | intel_clock_t clock; |
838 | 838 | ||
839 | if (target < 200000) { |
839 | if (target < 200000) { |
840 | clock.n = 1; |
840 | clock.n = 1; |
841 | clock.p1 = 2; |
841 | clock.p1 = 2; |
842 | clock.p2 = 10; |
842 | clock.p2 = 10; |
843 | clock.m1 = 12; |
843 | clock.m1 = 12; |
844 | clock.m2 = 9; |
844 | clock.m2 = 9; |
845 | } else { |
845 | } else { |
846 | clock.n = 2; |
846 | clock.n = 2; |
847 | clock.p1 = 1; |
847 | clock.p1 = 1; |
848 | clock.p2 = 10; |
848 | clock.p2 = 10; |
849 | clock.m1 = 14; |
849 | clock.m1 = 14; |
850 | clock.m2 = 8; |
850 | clock.m2 = 8; |
851 | } |
851 | } |
852 | intel_clock(dev, refclk, &clock); |
852 | intel_clock(dev, refclk, &clock); |
853 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
853 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
854 | return true; |
854 | return true; |
855 | } |
855 | } |
856 | 856 | ||
857 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
857 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
858 | static bool |
858 | static bool |
859 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
859 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
860 | int target, int refclk, intel_clock_t *match_clock, |
860 | int target, int refclk, intel_clock_t *match_clock, |
861 | intel_clock_t *best_clock) |
861 | intel_clock_t *best_clock) |
862 | { |
862 | { |
863 | intel_clock_t clock; |
863 | intel_clock_t clock; |
864 | if (target < 200000) { |
864 | if (target < 200000) { |
865 | clock.p1 = 2; |
865 | clock.p1 = 2; |
866 | clock.p2 = 10; |
866 | clock.p2 = 10; |
867 | clock.n = 2; |
867 | clock.n = 2; |
868 | clock.m1 = 23; |
868 | clock.m1 = 23; |
869 | clock.m2 = 8; |
869 | clock.m2 = 8; |
870 | } else { |
870 | } else { |
871 | clock.p1 = 1; |
871 | clock.p1 = 1; |
872 | clock.p2 = 10; |
872 | clock.p2 = 10; |
873 | clock.n = 1; |
873 | clock.n = 1; |
874 | clock.m1 = 14; |
874 | clock.m1 = 14; |
875 | clock.m2 = 2; |
875 | clock.m2 = 2; |
876 | } |
876 | } |
877 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
877 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
878 | clock.p = (clock.p1 * clock.p2); |
878 | clock.p = (clock.p1 * clock.p2); |
879 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
879 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
880 | clock.vco = 0; |
880 | clock.vco = 0; |
881 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
881 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
882 | return true; |
882 | return true; |
883 | } |
883 | } |
884 | static bool |
884 | static bool |
885 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
885 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, |
886 | int target, int refclk, intel_clock_t *match_clock, |
886 | int target, int refclk, intel_clock_t *match_clock, |
887 | intel_clock_t *best_clock) |
887 | intel_clock_t *best_clock) |
888 | { |
888 | { |
889 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
889 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
890 | u32 m, n, fastclk; |
890 | u32 m, n, fastclk; |
891 | u32 updrate, minupdate, fracbits, p; |
891 | u32 updrate, minupdate, fracbits, p; |
892 | unsigned long bestppm, ppm, absppm; |
892 | unsigned long bestppm, ppm, absppm; |
893 | int dotclk, flag; |
893 | int dotclk, flag; |
894 | 894 | ||
895 | flag = 0; |
895 | flag = 0; |
896 | dotclk = target * 1000; |
896 | dotclk = target * 1000; |
897 | bestppm = 1000000; |
897 | bestppm = 1000000; |
898 | ppm = absppm = 0; |
898 | ppm = absppm = 0; |
899 | fastclk = dotclk / (2*100); |
899 | fastclk = dotclk / (2*100); |
900 | updrate = 0; |
900 | updrate = 0; |
901 | minupdate = 19200; |
901 | minupdate = 19200; |
902 | fracbits = 1; |
902 | fracbits = 1; |
903 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
903 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
904 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
904 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
905 | 905 | ||
906 | /* based on hardware requirement, prefer smaller n to precision */ |
906 | /* based on hardware requirement, prefer smaller n to precision */ |
907 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
907 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
908 | updrate = refclk / n; |
908 | updrate = refclk / n; |
909 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
909 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
910 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
910 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
911 | if (p2 > 10) |
911 | if (p2 > 10) |
912 | p2 = p2 - 1; |
912 | p2 = p2 - 1; |
913 | p = p1 * p2; |
913 | p = p1 * p2; |
914 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
914 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
915 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
915 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
916 | m2 = (((2*(fastclk * p * n / m1 )) + |
916 | m2 = (((2*(fastclk * p * n / m1 )) + |
917 | refclk) / (2*refclk)); |
917 | refclk) / (2*refclk)); |
918 | m = m1 * m2; |
918 | m = m1 * m2; |
919 | vco = updrate * m; |
919 | vco = updrate * m; |
920 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
920 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
921 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
921 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
922 | absppm = (ppm > 0) ? ppm : (-ppm); |
922 | absppm = (ppm > 0) ? ppm : (-ppm); |
923 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
923 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
924 | bestppm = 0; |
924 | bestppm = 0; |
925 | flag = 1; |
925 | flag = 1; |
926 | } |
926 | } |
927 | if (absppm < bestppm - 10) { |
927 | if (absppm < bestppm - 10) { |
928 | bestppm = absppm; |
928 | bestppm = absppm; |
929 | flag = 1; |
929 | flag = 1; |
930 | } |
930 | } |
931 | if (flag) { |
931 | if (flag) { |
932 | bestn = n; |
932 | bestn = n; |
933 | bestm1 = m1; |
933 | bestm1 = m1; |
934 | bestm2 = m2; |
934 | bestm2 = m2; |
935 | bestp1 = p1; |
935 | bestp1 = p1; |
936 | bestp2 = p2; |
936 | bestp2 = p2; |
937 | flag = 0; |
937 | flag = 0; |
938 | } |
938 | } |
939 | } |
939 | } |
940 | } |
940 | } |
941 | } |
941 | } |
942 | } |
942 | } |
943 | } |
943 | } |
944 | best_clock->n = bestn; |
944 | best_clock->n = bestn; |
945 | best_clock->m1 = bestm1; |
945 | best_clock->m1 = bestm1; |
946 | best_clock->m2 = bestm2; |
946 | best_clock->m2 = bestm2; |
947 | best_clock->p1 = bestp1; |
947 | best_clock->p1 = bestp1; |
948 | best_clock->p2 = bestp2; |
948 | best_clock->p2 = bestp2; |
949 | 949 | ||
950 | return true; |
950 | return true; |
951 | } |
951 | } |
952 | 952 | ||
953 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
953 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
954 | { |
954 | { |
955 | struct drm_i915_private *dev_priv = dev->dev_private; |
955 | struct drm_i915_private *dev_priv = dev->dev_private; |
956 | u32 frame, frame_reg = PIPEFRAME(pipe); |
956 | u32 frame, frame_reg = PIPEFRAME(pipe); |
957 | 957 | ||
958 | frame = I915_READ(frame_reg); |
958 | frame = I915_READ(frame_reg); |
959 | 959 | ||
960 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
960 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
961 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
961 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
962 | } |
962 | } |
963 | 963 | ||
964 | /** |
964 | /** |
965 | * intel_wait_for_vblank - wait for vblank on a given pipe |
965 | * intel_wait_for_vblank - wait for vblank on a given pipe |
966 | * @dev: drm device |
966 | * @dev: drm device |
967 | * @pipe: pipe to wait for |
967 | * @pipe: pipe to wait for |
968 | * |
968 | * |
969 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
969 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
970 | * mode setting code. |
970 | * mode setting code. |
971 | */ |
971 | */ |
972 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
972 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
973 | { |
973 | { |
974 | struct drm_i915_private *dev_priv = dev->dev_private; |
974 | struct drm_i915_private *dev_priv = dev->dev_private; |
975 | int pipestat_reg = PIPESTAT(pipe); |
975 | int pipestat_reg = PIPESTAT(pipe); |
976 | 976 | ||
977 | if (INTEL_INFO(dev)->gen >= 5) { |
977 | if (INTEL_INFO(dev)->gen >= 5) { |
978 | ironlake_wait_for_vblank(dev, pipe); |
978 | ironlake_wait_for_vblank(dev, pipe); |
979 | return; |
979 | return; |
980 | } |
980 | } |
981 | 981 | ||
982 | /* Clear existing vblank status. Note this will clear any other |
982 | /* Clear existing vblank status. Note this will clear any other |
983 | * sticky status fields as well. |
983 | * sticky status fields as well. |
984 | * |
984 | * |
985 | * This races with i915_driver_irq_handler() with the result |
985 | * This races with i915_driver_irq_handler() with the result |
986 | * that either function could miss a vblank event. Here it is not |
986 | * that either function could miss a vblank event. Here it is not |
987 | * fatal, as we will either wait upon the next vblank interrupt or |
987 | * fatal, as we will either wait upon the next vblank interrupt or |
988 | * timeout. Generally speaking intel_wait_for_vblank() is only |
988 | * timeout. Generally speaking intel_wait_for_vblank() is only |
989 | * called during modeset at which time the GPU should be idle and |
989 | * called during modeset at which time the GPU should be idle and |
990 | * should *not* be performing page flips and thus not waiting on |
990 | * should *not* be performing page flips and thus not waiting on |
991 | * vblanks... |
991 | * vblanks... |
992 | * Currently, the result of us stealing a vblank from the irq |
992 | * Currently, the result of us stealing a vblank from the irq |
993 | * handler is that a single frame will be skipped during swapbuffers. |
993 | * handler is that a single frame will be skipped during swapbuffers. |
994 | */ |
994 | */ |
995 | I915_WRITE(pipestat_reg, |
995 | I915_WRITE(pipestat_reg, |
996 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
996 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
997 | 997 | ||
998 | /* Wait for vblank interrupt bit to set */ |
998 | /* Wait for vblank interrupt bit to set */ |
999 | if (wait_for(I915_READ(pipestat_reg) & |
999 | if (wait_for(I915_READ(pipestat_reg) & |
1000 | PIPE_VBLANK_INTERRUPT_STATUS, |
1000 | PIPE_VBLANK_INTERRUPT_STATUS, |
1001 | 50)) |
1001 | 50)) |
1002 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1002 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1003 | } |
1003 | } |
1004 | 1004 | ||
1005 | /* |
1005 | /* |
1006 | * intel_wait_for_pipe_off - wait for pipe to turn off |
1006 | * intel_wait_for_pipe_off - wait for pipe to turn off |
1007 | * @dev: drm device |
1007 | * @dev: drm device |
1008 | * @pipe: pipe to wait for |
1008 | * @pipe: pipe to wait for |
1009 | * |
1009 | * |
1010 | * After disabling a pipe, we can't wait for vblank in the usual way, |
1010 | * After disabling a pipe, we can't wait for vblank in the usual way, |
1011 | * spinning on the vblank interrupt status bit, since we won't actually |
1011 | * spinning on the vblank interrupt status bit, since we won't actually |
1012 | * see an interrupt when the pipe is disabled. |
1012 | * see an interrupt when the pipe is disabled. |
1013 | * |
1013 | * |
1014 | * On Gen4 and above: |
1014 | * On Gen4 and above: |
1015 | * wait for the pipe register state bit to turn off |
1015 | * wait for the pipe register state bit to turn off |
1016 | * |
1016 | * |
1017 | * Otherwise: |
1017 | * Otherwise: |
1018 | * wait for the display line value to settle (it usually |
1018 | * wait for the display line value to settle (it usually |
1019 | * ends up stopping at the start of the next frame). |
1019 | * ends up stopping at the start of the next frame). |
1020 | * |
1020 | * |
1021 | */ |
1021 | */ |
1022 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
1022 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
1023 | { |
1023 | { |
1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
1025 | 1025 | ||
1026 | if (INTEL_INFO(dev)->gen >= 4) { |
1026 | if (INTEL_INFO(dev)->gen >= 4) { |
1027 | int reg = PIPECONF(pipe); |
1027 | int reg = PIPECONF(pipe); |
1028 | 1028 | ||
1029 | /* Wait for the Pipe State to go off */ |
1029 | /* Wait for the Pipe State to go off */ |
1030 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1030 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1031 | 100)) |
1031 | 100)) |
1032 | WARN(1, "pipe_off wait timed out\n"); |
1032 | WARN(1, "pipe_off wait timed out\n"); |
1033 | } else { |
1033 | } else { |
1034 | u32 last_line, line_mask; |
1034 | u32 last_line, line_mask; |
1035 | int reg = PIPEDSL(pipe); |
1035 | int reg = PIPEDSL(pipe); |
1036 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
1036 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
1037 | 1037 | ||
1038 | if (IS_GEN2(dev)) |
1038 | if (IS_GEN2(dev)) |
1039 | line_mask = DSL_LINEMASK_GEN2; |
1039 | line_mask = DSL_LINEMASK_GEN2; |
1040 | else |
1040 | else |
1041 | line_mask = DSL_LINEMASK_GEN3; |
1041 | line_mask = DSL_LINEMASK_GEN3; |
1042 | 1042 | ||
1043 | /* Wait for the display line to settle */ |
1043 | /* Wait for the display line to settle */ |
1044 | do { |
1044 | do { |
1045 | last_line = I915_READ(reg) & line_mask; |
1045 | last_line = I915_READ(reg) & line_mask; |
1046 | mdelay(5); |
1046 | mdelay(5); |
1047 | } while (((I915_READ(reg) & line_mask) != last_line) && |
1047 | } while (((I915_READ(reg) & line_mask) != last_line) && |
1048 | time_after(timeout, GetTimerTicks())); |
1048 | time_after(timeout, GetTimerTicks())); |
1049 | if (time_after(GetTimerTicks(), timeout)) |
1049 | if (time_after(GetTimerTicks(), timeout)) |
1050 | WARN(1, "pipe_off wait timed out\n"); |
1050 | WARN(1, "pipe_off wait timed out\n"); |
1051 | } |
1051 | } |
1052 | } |
1052 | } |
1053 | 1053 | ||
1054 | static const char *state_string(bool enabled) |
1054 | static const char *state_string(bool enabled) |
1055 | { |
1055 | { |
1056 | return enabled ? "on" : "off"; |
1056 | return enabled ? "on" : "off"; |
1057 | } |
1057 | } |
1058 | 1058 | ||
1059 | /* Only for pre-ILK configs */ |
1059 | /* Only for pre-ILK configs */ |
1060 | static void assert_pll(struct drm_i915_private *dev_priv, |
1060 | static void assert_pll(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe, bool state) |
1061 | enum pipe pipe, bool state) |
1062 | { |
1062 | { |
1063 | int reg; |
1063 | int reg; |
1064 | u32 val; |
1064 | u32 val; |
1065 | bool cur_state; |
1065 | bool cur_state; |
1066 | 1066 | ||
1067 | reg = DPLL(pipe); |
1067 | reg = DPLL(pipe); |
1068 | val = I915_READ(reg); |
1068 | val = I915_READ(reg); |
1069 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1069 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1070 | WARN(cur_state != state, |
1070 | WARN(cur_state != state, |
1071 | "PLL state assertion failure (expected %s, current %s)\n", |
1071 | "PLL state assertion failure (expected %s, current %s)\n", |
1072 | state_string(state), state_string(cur_state)); |
1072 | state_string(state), state_string(cur_state)); |
1073 | } |
1073 | } |
1074 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
1074 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
1075 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
1075 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
1076 | 1076 | ||
1077 | /* For ILK+ */ |
1077 | /* For ILK+ */ |
1078 | static void assert_pch_pll(struct drm_i915_private *dev_priv, |
1078 | static void assert_pch_pll(struct drm_i915_private *dev_priv, |
1079 | struct intel_pch_pll *pll, |
1079 | struct intel_pch_pll *pll, |
1080 | struct intel_crtc *crtc, |
1080 | struct intel_crtc *crtc, |
1081 | bool state) |
1081 | bool state) |
1082 | { |
1082 | { |
1083 | u32 val; |
1083 | u32 val; |
1084 | bool cur_state; |
1084 | bool cur_state; |
1085 | 1085 | ||
1086 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1086 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1087 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
1087 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
1088 | return; |
1088 | return; |
1089 | } |
1089 | } |
1090 | 1090 | ||
1091 | if (WARN (!pll, |
1091 | if (WARN (!pll, |
1092 | "asserting PCH PLL %s with no PLL\n", state_string(state))) |
1092 | "asserting PCH PLL %s with no PLL\n", state_string(state))) |
1093 | return; |
1093 | return; |
1094 | 1094 | ||
1095 | val = I915_READ(pll->pll_reg); |
1095 | val = I915_READ(pll->pll_reg); |
1096 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1096 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1097 | WARN(cur_state != state, |
1097 | WARN(cur_state != state, |
1098 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", |
1098 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", |
1099 | pll->pll_reg, state_string(state), state_string(cur_state), val); |
1099 | pll->pll_reg, state_string(state), state_string(cur_state), val); |
1100 | 1100 | ||
1101 | /* Make sure the selected PLL is correctly attached to the transcoder */ |
1101 | /* Make sure the selected PLL is correctly attached to the transcoder */ |
1102 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { |
1102 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { |
1103 | u32 pch_dpll; |
1103 | u32 pch_dpll; |
1104 | 1104 | ||
1105 | pch_dpll = I915_READ(PCH_DPLL_SEL); |
1105 | pch_dpll = I915_READ(PCH_DPLL_SEL); |
1106 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1106 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1107 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, |
1107 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, |
1108 | "PLL[%d] not attached to this transcoder %d: %08x\n", |
1108 | "PLL[%d] not attached to this transcoder %d: %08x\n", |
1109 | cur_state, crtc->pipe, pch_dpll)) { |
1109 | cur_state, crtc->pipe, pch_dpll)) { |
1110 | cur_state = !!(val >> (4*crtc->pipe + 3)); |
1110 | cur_state = !!(val >> (4*crtc->pipe + 3)); |
1111 | WARN(cur_state != state, |
1111 | WARN(cur_state != state, |
1112 | "PLL[%d] not %s on this transcoder %d: %08x\n", |
1112 | "PLL[%d] not %s on this transcoder %d: %08x\n", |
1113 | pll->pll_reg == _PCH_DPLL_B, |
1113 | pll->pll_reg == _PCH_DPLL_B, |
1114 | state_string(state), |
1114 | state_string(state), |
1115 | crtc->pipe, |
1115 | crtc->pipe, |
1116 | val); |
1116 | val); |
1117 | } |
1117 | } |
1118 | } |
1118 | } |
1119 | } |
1119 | } |
1120 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1120 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1121 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) |
1121 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) |
1122 | 1122 | ||
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) |
1124 | enum pipe pipe, bool state) |
1125 | { |
1125 | { |
1126 | int reg; |
1126 | int reg; |
1127 | u32 val; |
1127 | u32 val; |
1128 | bool cur_state; |
1128 | bool cur_state; |
1129 | 1129 | ||
1130 | if (IS_HASWELL(dev_priv->dev)) { |
1130 | if (IS_HASWELL(dev_priv->dev)) { |
1131 | /* On Haswell, DDI is used instead of FDI_TX_CTL */ |
1131 | /* On Haswell, DDI is used instead of FDI_TX_CTL */ |
1132 | reg = DDI_FUNC_CTL(pipe); |
1132 | reg = DDI_FUNC_CTL(pipe); |
1133 | val = I915_READ(reg); |
1133 | val = I915_READ(reg); |
1134 | cur_state = !!(val & PIPE_DDI_FUNC_ENABLE); |
1134 | cur_state = !!(val & PIPE_DDI_FUNC_ENABLE); |
1135 | } else { |
1135 | } else { |
1136 | reg = FDI_TX_CTL(pipe); |
1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); |
1137 | val = I915_READ(reg); |
1138 | cur_state = !!(val & FDI_TX_ENABLE); |
1138 | cur_state = !!(val & FDI_TX_ENABLE); |
1139 | } |
1139 | } |
1140 | WARN(cur_state != state, |
1140 | WARN(cur_state != state, |
1141 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1141 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1142 | state_string(state), state_string(cur_state)); |
1142 | state_string(state), state_string(cur_state)); |
1143 | } |
1143 | } |
1144 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1144 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1145 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1145 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1146 | 1146 | ||
1147 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
1147 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
1148 | enum pipe pipe, bool state) |
1148 | enum pipe pipe, bool state) |
1149 | { |
1149 | { |
1150 | int reg; |
1150 | int reg; |
1151 | u32 val; |
1151 | u32 val; |
1152 | bool cur_state; |
1152 | bool cur_state; |
1153 | 1153 | ||
1154 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1154 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1155 | DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); |
1155 | DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); |
1156 | return; |
1156 | return; |
1157 | } else { |
1157 | } else { |
1158 | reg = FDI_RX_CTL(pipe); |
1158 | reg = FDI_RX_CTL(pipe); |
1159 | val = I915_READ(reg); |
1159 | val = I915_READ(reg); |
1160 | cur_state = !!(val & FDI_RX_ENABLE); |
1160 | cur_state = !!(val & FDI_RX_ENABLE); |
1161 | } |
1161 | } |
1162 | WARN(cur_state != state, |
1162 | WARN(cur_state != state, |
1163 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1163 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1164 | state_string(state), state_string(cur_state)); |
1164 | state_string(state), state_string(cur_state)); |
1165 | } |
1165 | } |
1166 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1166 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1167 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1167 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1168 | 1168 | ||
1169 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1169 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1170 | enum pipe pipe) |
1170 | enum pipe pipe) |
1171 | { |
1171 | { |
1172 | int reg; |
1172 | int reg; |
1173 | u32 val; |
1173 | u32 val; |
1174 | 1174 | ||
1175 | /* ILK FDI PLL is always enabled */ |
1175 | /* ILK FDI PLL is always enabled */ |
1176 | if (dev_priv->info->gen == 5) |
1176 | if (dev_priv->info->gen == 5) |
1177 | return; |
1177 | return; |
1178 | 1178 | ||
1179 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1179 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1180 | if (IS_HASWELL(dev_priv->dev)) |
1180 | if (IS_HASWELL(dev_priv->dev)) |
1181 | return; |
1181 | return; |
1182 | 1182 | ||
1183 | reg = FDI_TX_CTL(pipe); |
1183 | reg = FDI_TX_CTL(pipe); |
1184 | val = I915_READ(reg); |
1184 | val = I915_READ(reg); |
1185 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1185 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1186 | } |
1186 | } |
1187 | 1187 | ||
1188 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, |
1188 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, |
1189 | enum pipe pipe) |
1189 | enum pipe pipe) |
1190 | { |
1190 | { |
1191 | int reg; |
1191 | int reg; |
1192 | u32 val; |
1192 | u32 val; |
1193 | 1193 | ||
1194 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1194 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1195 | DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); |
1195 | DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); |
1196 | return; |
1196 | return; |
1197 | } |
1197 | } |
1198 | reg = FDI_RX_CTL(pipe); |
1198 | reg = FDI_RX_CTL(pipe); |
1199 | val = I915_READ(reg); |
1199 | val = I915_READ(reg); |
1200 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); |
1200 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); |
1201 | } |
1201 | } |
1202 | 1202 | ||
1203 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1203 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe) |
1204 | enum pipe pipe) |
1205 | { |
1205 | { |
1206 | int pp_reg, lvds_reg; |
1206 | int pp_reg, lvds_reg; |
1207 | u32 val; |
1207 | u32 val; |
1208 | enum pipe panel_pipe = PIPE_A; |
1208 | enum pipe panel_pipe = PIPE_A; |
1209 | bool locked = true; |
1209 | bool locked = true; |
1210 | 1210 | ||
1211 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1211 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1212 | pp_reg = PCH_PP_CONTROL; |
1212 | pp_reg = PCH_PP_CONTROL; |
1213 | lvds_reg = PCH_LVDS; |
1213 | lvds_reg = PCH_LVDS; |
1214 | } else { |
1214 | } else { |
1215 | pp_reg = PP_CONTROL; |
1215 | pp_reg = PP_CONTROL; |
1216 | lvds_reg = LVDS; |
1216 | lvds_reg = LVDS; |
1217 | } |
1217 | } |
1218 | 1218 | ||
1219 | val = I915_READ(pp_reg); |
1219 | val = I915_READ(pp_reg); |
1220 | if (!(val & PANEL_POWER_ON) || |
1220 | if (!(val & PANEL_POWER_ON) || |
1221 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1221 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1222 | locked = false; |
1222 | locked = false; |
1223 | 1223 | ||
1224 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1224 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1225 | panel_pipe = PIPE_B; |
1225 | panel_pipe = PIPE_B; |
1226 | 1226 | ||
1227 | WARN(panel_pipe == pipe && locked, |
1227 | WARN(panel_pipe == pipe && locked, |
1228 | "panel assertion failure, pipe %c regs locked\n", |
1228 | "panel assertion failure, pipe %c regs locked\n", |
1229 | pipe_name(pipe)); |
1229 | pipe_name(pipe)); |
1230 | } |
1230 | } |
1231 | 1231 | ||
1232 | void assert_pipe(struct drm_i915_private *dev_priv, |
1232 | void assert_pipe(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) |
1233 | enum pipe pipe, bool state) |
1234 | { |
1234 | { |
1235 | int reg; |
1235 | int reg; |
1236 | u32 val; |
1236 | u32 val; |
1237 | bool cur_state; |
1237 | bool cur_state; |
1238 | 1238 | ||
1239 | /* if we need the pipe A quirk it must be always on */ |
1239 | /* if we need the pipe A quirk it must be always on */ |
1240 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1240 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1241 | state = true; |
1241 | state = true; |
1242 | 1242 | ||
1243 | reg = PIPECONF(pipe); |
1243 | reg = PIPECONF(pipe); |
1244 | val = I915_READ(reg); |
1244 | val = I915_READ(reg); |
1245 | cur_state = !!(val & PIPECONF_ENABLE); |
1245 | cur_state = !!(val & PIPECONF_ENABLE); |
1246 | WARN(cur_state != state, |
1246 | WARN(cur_state != state, |
1247 | "pipe %c assertion failure (expected %s, current %s)\n", |
1247 | "pipe %c assertion failure (expected %s, current %s)\n", |
1248 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1248 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1249 | } |
1249 | } |
1250 | 1250 | ||
1251 | static void assert_plane(struct drm_i915_private *dev_priv, |
1251 | static void assert_plane(struct drm_i915_private *dev_priv, |
1252 | enum plane plane, bool state) |
1252 | enum plane plane, bool state) |
1253 | { |
1253 | { |
1254 | int reg; |
1254 | int reg; |
1255 | u32 val; |
1255 | u32 val; |
1256 | bool cur_state; |
1256 | bool cur_state; |
1257 | 1257 | ||
1258 | reg = DSPCNTR(plane); |
1258 | reg = DSPCNTR(plane); |
1259 | val = I915_READ(reg); |
1259 | val = I915_READ(reg); |
1260 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1260 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1261 | WARN(cur_state != state, |
1261 | WARN(cur_state != state, |
1262 | "plane %c assertion failure (expected %s, current %s)\n", |
1262 | "plane %c assertion failure (expected %s, current %s)\n", |
1263 | plane_name(plane), state_string(state), state_string(cur_state)); |
1263 | plane_name(plane), state_string(state), state_string(cur_state)); |
1264 | } |
1264 | } |
1265 | 1265 | ||
1266 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1266 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1267 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1267 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1268 | 1268 | ||
1269 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1269 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1270 | enum pipe pipe) |
1270 | enum pipe pipe) |
1271 | { |
1271 | { |
1272 | int reg, i; |
1272 | int reg, i; |
1273 | u32 val; |
1273 | u32 val; |
1274 | int cur_pipe; |
1274 | int cur_pipe; |
1275 | 1275 | ||
1276 | /* Planes are fixed to pipes on ILK+ */ |
1276 | /* Planes are fixed to pipes on ILK+ */ |
1277 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1277 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1278 | reg = DSPCNTR(pipe); |
1278 | reg = DSPCNTR(pipe); |
1279 | val = I915_READ(reg); |
1279 | val = I915_READ(reg); |
1280 | WARN((val & DISPLAY_PLANE_ENABLE), |
1280 | WARN((val & DISPLAY_PLANE_ENABLE), |
1281 | "plane %c assertion failure, should be disabled but not\n", |
1281 | "plane %c assertion failure, should be disabled but not\n", |
1282 | plane_name(pipe)); |
1282 | plane_name(pipe)); |
1283 | return; |
1283 | return; |
1284 | } |
1284 | } |
1285 | 1285 | ||
1286 | /* Need to check both planes against the pipe */ |
1286 | /* Need to check both planes against the pipe */ |
1287 | for (i = 0; i < 2; i++) { |
1287 | for (i = 0; i < 2; i++) { |
1288 | reg = DSPCNTR(i); |
1288 | reg = DSPCNTR(i); |
1289 | val = I915_READ(reg); |
1289 | val = I915_READ(reg); |
1290 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1290 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1291 | DISPPLANE_SEL_PIPE_SHIFT; |
1291 | DISPPLANE_SEL_PIPE_SHIFT; |
1292 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1292 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1293 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1293 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1294 | plane_name(i), pipe_name(pipe)); |
1294 | plane_name(i), pipe_name(pipe)); |
1295 | } |
1295 | } |
1296 | } |
1296 | } |
1297 | 1297 | ||
1298 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1298 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1299 | { |
1299 | { |
1300 | u32 val; |
1300 | u32 val; |
1301 | bool enabled; |
1301 | bool enabled; |
1302 | 1302 | ||
1303 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1303 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1304 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1304 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1305 | return; |
1305 | return; |
1306 | } |
1306 | } |
1307 | 1307 | ||
1308 | val = I915_READ(PCH_DREF_CONTROL); |
1308 | val = I915_READ(PCH_DREF_CONTROL); |
1309 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1309 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1310 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1310 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1311 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1311 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1312 | } |
1312 | } |
1313 | 1313 | ||
1314 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, |
1314 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, |
1315 | enum pipe pipe) |
1315 | enum pipe pipe) |
1316 | { |
1316 | { |
1317 | int reg; |
1317 | int reg; |
1318 | u32 val; |
1318 | u32 val; |
1319 | bool enabled; |
1319 | bool enabled; |
1320 | 1320 | ||
1321 | reg = TRANSCONF(pipe); |
1321 | reg = TRANSCONF(pipe); |
1322 | val = I915_READ(reg); |
1322 | val = I915_READ(reg); |
1323 | enabled = !!(val & TRANS_ENABLE); |
1323 | enabled = !!(val & TRANS_ENABLE); |
1324 | WARN(enabled, |
1324 | WARN(enabled, |
1325 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1325 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1326 | pipe_name(pipe)); |
1326 | pipe_name(pipe)); |
1327 | } |
1327 | } |
1328 | 1328 | ||
1329 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1329 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1330 | enum pipe pipe, u32 port_sel, u32 val) |
1330 | enum pipe pipe, u32 port_sel, u32 val) |
1331 | { |
1331 | { |
1332 | if ((val & DP_PORT_EN) == 0) |
1332 | if ((val & DP_PORT_EN) == 0) |
1333 | return false; |
1333 | return false; |
1334 | 1334 | ||
1335 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1335 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1336 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1336 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1337 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1337 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1338 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1338 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1339 | return false; |
1339 | return false; |
1340 | } else { |
1340 | } else { |
1341 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1341 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1342 | return false; |
1342 | return false; |
1343 | } |
1343 | } |
1344 | return true; |
1344 | return true; |
1345 | } |
1345 | } |
1346 | 1346 | ||
1347 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1347 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1348 | enum pipe pipe, u32 val) |
1348 | enum pipe pipe, u32 val) |
1349 | { |
1349 | { |
1350 | if ((val & PORT_ENABLE) == 0) |
1350 | if ((val & PORT_ENABLE) == 0) |
1351 | return false; |
1351 | return false; |
1352 | 1352 | ||
1353 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1353 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1354 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1355 | return false; |
1355 | return false; |
1356 | } else { |
1356 | } else { |
1357 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) |
1357 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) |
1358 | return false; |
1358 | return false; |
1359 | } |
1359 | } |
1360 | return true; |
1360 | return true; |
1361 | } |
1361 | } |
1362 | 1362 | ||
1363 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1363 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1364 | enum pipe pipe, u32 val) |
1364 | enum pipe pipe, u32 val) |
1365 | { |
1365 | { |
1366 | if ((val & LVDS_PORT_EN) == 0) |
1366 | if ((val & LVDS_PORT_EN) == 0) |
1367 | return false; |
1367 | return false; |
1368 | 1368 | ||
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1370 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1370 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1371 | return false; |
1371 | return false; |
1372 | } else { |
1372 | } else { |
1373 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1373 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1374 | return false; |
1374 | return false; |
1375 | } |
1375 | } |
1376 | return true; |
1376 | return true; |
1377 | } |
1377 | } |
1378 | 1378 | ||
1379 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1379 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1380 | enum pipe pipe, u32 val) |
1380 | enum pipe pipe, u32 val) |
1381 | { |
1381 | { |
1382 | if ((val & ADPA_DAC_ENABLE) == 0) |
1382 | if ((val & ADPA_DAC_ENABLE) == 0) |
1383 | return false; |
1383 | return false; |
1384 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1384 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1385 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1385 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1386 | return false; |
1386 | return false; |
1387 | } else { |
1387 | } else { |
1388 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1388 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1389 | return false; |
1389 | return false; |
1390 | } |
1390 | } |
1391 | return true; |
1391 | return true; |
1392 | } |
1392 | } |
1393 | 1393 | ||
1394 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1394 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1395 | enum pipe pipe, int reg, u32 port_sel) |
1395 | enum pipe pipe, int reg, u32 port_sel) |
1396 | { |
1396 | { |
1397 | u32 val = I915_READ(reg); |
1397 | u32 val = I915_READ(reg); |
1398 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1398 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1399 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1399 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1400 | reg, pipe_name(pipe)); |
1400 | reg, pipe_name(pipe)); |
1401 | 1401 | ||
1402 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1402 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1403 | && (val & DP_PIPEB_SELECT), |
1403 | && (val & DP_PIPEB_SELECT), |
1404 | "IBX PCH dp port still using transcoder B\n"); |
1404 | "IBX PCH dp port still using transcoder B\n"); |
1405 | } |
1405 | } |
1406 | 1406 | ||
1407 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1407 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1408 | enum pipe pipe, int reg) |
1408 | enum pipe pipe, int reg) |
1409 | { |
1409 | { |
1410 | u32 val = I915_READ(reg); |
1410 | u32 val = I915_READ(reg); |
1411 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1411 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1412 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1412 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1413 | reg, pipe_name(pipe)); |
1413 | reg, pipe_name(pipe)); |
1414 | 1414 | ||
1415 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
1415 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
1416 | && (val & SDVO_PIPE_B_SELECT), |
1416 | && (val & SDVO_PIPE_B_SELECT), |
1417 | "IBX PCH hdmi port still using transcoder B\n"); |
1417 | "IBX PCH hdmi port still using transcoder B\n"); |
1418 | } |
1418 | } |
1419 | 1419 | ||
1420 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1420 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1421 | enum pipe pipe) |
1421 | enum pipe pipe) |
1422 | { |
1422 | { |
1423 | int reg; |
1423 | int reg; |
1424 | u32 val; |
1424 | u32 val; |
1425 | 1425 | ||
1426 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1426 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1427 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1427 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1428 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1428 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1429 | 1429 | ||
1430 | reg = PCH_ADPA; |
1430 | reg = PCH_ADPA; |
1431 | val = I915_READ(reg); |
1431 | val = I915_READ(reg); |
1432 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1432 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1433 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1433 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1434 | pipe_name(pipe)); |
1434 | pipe_name(pipe)); |
1435 | 1435 | ||
1436 | reg = PCH_LVDS; |
1436 | reg = PCH_LVDS; |
1437 | val = I915_READ(reg); |
1437 | val = I915_READ(reg); |
1438 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1438 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1439 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1439 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1440 | pipe_name(pipe)); |
1440 | pipe_name(pipe)); |
1441 | 1441 | ||
1442 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); |
1442 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); |
1443 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); |
1443 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); |
1444 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); |
1444 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); |
1445 | } |
1445 | } |
1446 | 1446 | ||
1447 | /** |
1447 | /** |
1448 | * intel_enable_pll - enable a PLL |
1448 | * intel_enable_pll - enable a PLL |
1449 | * @dev_priv: i915 private structure |
1449 | * @dev_priv: i915 private structure |
1450 | * @pipe: pipe PLL to enable |
1450 | * @pipe: pipe PLL to enable |
1451 | * |
1451 | * |
1452 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to |
1452 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to |
1453 | * make sure the PLL reg is writable first though, since the panel write |
1453 | * make sure the PLL reg is writable first though, since the panel write |
1454 | * protect mechanism may be enabled. |
1454 | * protect mechanism may be enabled. |
1455 | * |
1455 | * |
1456 | * Note! This is for pre-ILK only. |
1456 | * Note! This is for pre-ILK only. |
1457 | * |
1457 | * |
1458 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. |
1458 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. |
1459 | */ |
1459 | */ |
1460 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1460 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1461 | { |
1461 | { |
1462 | int reg; |
1462 | int reg; |
1463 | u32 val; |
1463 | u32 val; |
1464 | 1464 | ||
1465 | /* No really, not for ILK+ */ |
1465 | /* No really, not for ILK+ */ |
1466 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
1466 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
1467 | 1467 | ||
1468 | /* PLL is protected by panel, make sure we can write it */ |
1468 | /* PLL is protected by panel, make sure we can write it */ |
1469 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1469 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1470 | assert_panel_unlocked(dev_priv, pipe); |
1470 | assert_panel_unlocked(dev_priv, pipe); |
1471 | 1471 | ||
1472 | reg = DPLL(pipe); |
1472 | reg = DPLL(pipe); |
1473 | val = I915_READ(reg); |
1473 | val = I915_READ(reg); |
1474 | val |= DPLL_VCO_ENABLE; |
1474 | val |= DPLL_VCO_ENABLE; |
1475 | 1475 | ||
1476 | /* We do this three times for luck */ |
1476 | /* We do this three times for luck */ |
1477 | I915_WRITE(reg, val); |
1477 | I915_WRITE(reg, val); |
1478 | POSTING_READ(reg); |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ |
1479 | udelay(150); /* wait for warmup */ |
1480 | I915_WRITE(reg, val); |
1480 | I915_WRITE(reg, val); |
1481 | POSTING_READ(reg); |
1481 | POSTING_READ(reg); |
1482 | udelay(150); /* wait for warmup */ |
1482 | udelay(150); /* wait for warmup */ |
1483 | I915_WRITE(reg, val); |
1483 | I915_WRITE(reg, val); |
1484 | POSTING_READ(reg); |
1484 | POSTING_READ(reg); |
1485 | udelay(150); /* wait for warmup */ |
1485 | udelay(150); /* wait for warmup */ |
1486 | } |
1486 | } |
1487 | 1487 | ||
1488 | /** |
1488 | /** |
1489 | * intel_disable_pll - disable a PLL |
1489 | * intel_disable_pll - disable a PLL |
1490 | * @dev_priv: i915 private structure |
1490 | * @dev_priv: i915 private structure |
1491 | * @pipe: pipe PLL to disable |
1491 | * @pipe: pipe PLL to disable |
1492 | * |
1492 | * |
1493 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1493 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1494 | * |
1494 | * |
1495 | * Note! This is for pre-ILK only. |
1495 | * Note! This is for pre-ILK only. |
1496 | */ |
1496 | */ |
1497 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1497 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1498 | { |
1498 | { |
1499 | int reg; |
1499 | int reg; |
1500 | u32 val; |
1500 | u32 val; |
1501 | 1501 | ||
1502 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1502 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1503 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1503 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1504 | return; |
1504 | return; |
1505 | 1505 | ||
1506 | /* Make sure the pipe isn't still relying on us */ |
1506 | /* Make sure the pipe isn't still relying on us */ |
1507 | assert_pipe_disabled(dev_priv, pipe); |
1507 | assert_pipe_disabled(dev_priv, pipe); |
1508 | 1508 | ||
1509 | reg = DPLL(pipe); |
1509 | reg = DPLL(pipe); |
1510 | val = I915_READ(reg); |
1510 | val = I915_READ(reg); |
1511 | val &= ~DPLL_VCO_ENABLE; |
1511 | val &= ~DPLL_VCO_ENABLE; |
1512 | I915_WRITE(reg, val); |
1512 | I915_WRITE(reg, val); |
1513 | POSTING_READ(reg); |
1513 | POSTING_READ(reg); |
1514 | } |
1514 | } |
1515 | 1515 | ||
1516 | /* SBI access */ |
1516 | /* SBI access */ |
1517 | static void |
1517 | static void |
1518 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) |
1518 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) |
1519 | { |
1519 | { |
1520 | unsigned long flags; |
1520 | unsigned long flags; |
1521 | 1521 | ||
1522 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
1522 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
1523 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
1523 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
1524 | 100)) { |
1524 | 100)) { |
1525 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
1525 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
1526 | goto out_unlock; |
1526 | goto out_unlock; |
1527 | } |
1527 | } |
1528 | 1528 | ||
1529 | I915_WRITE(SBI_ADDR, |
1529 | I915_WRITE(SBI_ADDR, |
1530 | (reg << 16)); |
1530 | (reg << 16)); |
1531 | I915_WRITE(SBI_DATA, |
1531 | I915_WRITE(SBI_DATA, |
1532 | value); |
1532 | value); |
1533 | I915_WRITE(SBI_CTL_STAT, |
1533 | I915_WRITE(SBI_CTL_STAT, |
1534 | SBI_BUSY | |
1534 | SBI_BUSY | |
1535 | SBI_CTL_OP_CRWR); |
1535 | SBI_CTL_OP_CRWR); |
1536 | 1536 | ||
1537 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
1537 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
1538 | 100)) { |
1538 | 100)) { |
1539 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
1539 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
1540 | goto out_unlock; |
1540 | goto out_unlock; |
1541 | } |
1541 | } |
1542 | 1542 | ||
1543 | out_unlock: |
1543 | out_unlock: |
1544 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
1544 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
1545 | } |
1545 | } |
1546 | 1546 | ||
1547 | static u32 |
1547 | static u32 |
1548 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) |
1548 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) |
1549 | { |
1549 | { |
1550 | unsigned long flags; |
1550 | unsigned long flags; |
1551 | u32 value = 0; |
1551 | u32 value = 0; |
1552 | 1552 | ||
1553 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
1553 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
1554 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
1554 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
1555 | 100)) { |
1555 | 100)) { |
1556 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
1556 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
1557 | goto out_unlock; |
1557 | goto out_unlock; |
1558 | } |
1558 | } |
1559 | 1559 | ||
1560 | I915_WRITE(SBI_ADDR, |
1560 | I915_WRITE(SBI_ADDR, |
1561 | (reg << 16)); |
1561 | (reg << 16)); |
1562 | I915_WRITE(SBI_CTL_STAT, |
1562 | I915_WRITE(SBI_CTL_STAT, |
1563 | SBI_BUSY | |
1563 | SBI_BUSY | |
1564 | SBI_CTL_OP_CRRD); |
1564 | SBI_CTL_OP_CRRD); |
1565 | 1565 | ||
1566 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
1566 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
1567 | 100)) { |
1567 | 100)) { |
1568 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
1568 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
1569 | goto out_unlock; |
1569 | goto out_unlock; |
1570 | } |
1570 | } |
1571 | 1571 | ||
1572 | value = I915_READ(SBI_DATA); |
1572 | value = I915_READ(SBI_DATA); |
1573 | 1573 | ||
1574 | out_unlock: |
1574 | out_unlock: |
1575 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
1575 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
1576 | return value; |
1576 | return value; |
1577 | } |
1577 | } |
1578 | 1578 | ||
1579 | /** |
1579 | /** |
1580 | * intel_enable_pch_pll - enable PCH PLL |
1580 | * intel_enable_pch_pll - enable PCH PLL |
1581 | * @dev_priv: i915 private structure |
1581 | * @dev_priv: i915 private structure |
1582 | * @pipe: pipe PLL to enable |
1582 | * @pipe: pipe PLL to enable |
1583 | * |
1583 | * |
1584 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1584 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1585 | * drives the transcoder clock. |
1585 | * drives the transcoder clock. |
1586 | */ |
1586 | */ |
1587 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
1587 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
1588 | { |
1588 | { |
1589 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1589 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1590 | struct intel_pch_pll *pll; |
1590 | struct intel_pch_pll *pll; |
1591 | int reg; |
1591 | int reg; |
1592 | u32 val; |
1592 | u32 val; |
1593 | 1593 | ||
1594 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1594 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1595 | BUG_ON(dev_priv->info->gen < 5); |
1595 | BUG_ON(dev_priv->info->gen < 5); |
1596 | pll = intel_crtc->pch_pll; |
1596 | pll = intel_crtc->pch_pll; |
1597 | if (pll == NULL) |
1597 | if (pll == NULL) |
1598 | return; |
1598 | return; |
1599 | 1599 | ||
1600 | if (WARN_ON(pll->refcount == 0)) |
1600 | if (WARN_ON(pll->refcount == 0)) |
1601 | return; |
1601 | return; |
1602 | 1602 | ||
1603 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", |
1603 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", |
1604 | pll->pll_reg, pll->active, pll->on, |
1604 | pll->pll_reg, pll->active, pll->on, |
1605 | intel_crtc->base.base.id); |
1605 | intel_crtc->base.base.id); |
1606 | 1606 | ||
1607 | /* PCH refclock must be enabled first */ |
1607 | /* PCH refclock must be enabled first */ |
1608 | assert_pch_refclk_enabled(dev_priv); |
1608 | assert_pch_refclk_enabled(dev_priv); |
1609 | 1609 | ||
1610 | if (pll->active++ && pll->on) { |
1610 | if (pll->active++ && pll->on) { |
1611 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
1611 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
1612 | return; |
1612 | return; |
1613 | } |
1613 | } |
1614 | 1614 | ||
1615 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); |
1615 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); |
1616 | 1616 | ||
1617 | reg = pll->pll_reg; |
1617 | reg = pll->pll_reg; |
1618 | val = I915_READ(reg); |
1618 | val = I915_READ(reg); |
1619 | val |= DPLL_VCO_ENABLE; |
1619 | val |= DPLL_VCO_ENABLE; |
1620 | I915_WRITE(reg, val); |
1620 | I915_WRITE(reg, val); |
1621 | POSTING_READ(reg); |
1621 | POSTING_READ(reg); |
1622 | udelay(200); |
1622 | udelay(200); |
1623 | 1623 | ||
1624 | pll->on = true; |
1624 | pll->on = true; |
1625 | } |
1625 | } |
1626 | 1626 | ||
1627 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
1627 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
1628 | { |
1628 | { |
1629 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1629 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1630 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
1630 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
1631 | int reg; |
1631 | int reg; |
1632 | u32 val; |
1632 | u32 val; |
1633 | 1633 | ||
1634 | /* PCH only available on ILK+ */ |
1634 | /* PCH only available on ILK+ */ |
1635 | BUG_ON(dev_priv->info->gen < 5); |
1635 | BUG_ON(dev_priv->info->gen < 5); |
1636 | if (pll == NULL) |
1636 | if (pll == NULL) |
1637 | return; |
1637 | return; |
1638 | 1638 | ||
1639 | if (WARN_ON(pll->refcount == 0)) |
1639 | if (WARN_ON(pll->refcount == 0)) |
1640 | return; |
1640 | return; |
1641 | 1641 | ||
1642 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1642 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1643 | pll->pll_reg, pll->active, pll->on, |
1643 | pll->pll_reg, pll->active, pll->on, |
1644 | intel_crtc->base.base.id); |
1644 | intel_crtc->base.base.id); |
1645 | 1645 | ||
1646 | if (WARN_ON(pll->active == 0)) { |
1646 | if (WARN_ON(pll->active == 0)) { |
1647 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
1647 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
1648 | return; |
1648 | return; |
1649 | } |
1649 | } |
1650 | 1650 | ||
1651 | if (--pll->active) { |
1651 | if (--pll->active) { |
1652 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
1652 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
1653 | return; |
1653 | return; |
1654 | } |
1654 | } |
1655 | 1655 | ||
1656 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); |
1656 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); |
1657 | 1657 | ||
1658 | /* Make sure transcoder isn't still depending on us */ |
1658 | /* Make sure transcoder isn't still depending on us */ |
1659 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); |
1659 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); |
1660 | 1660 | ||
1661 | reg = pll->pll_reg; |
1661 | reg = pll->pll_reg; |
1662 | val = I915_READ(reg); |
1662 | val = I915_READ(reg); |
1663 | val &= ~DPLL_VCO_ENABLE; |
1663 | val &= ~DPLL_VCO_ENABLE; |
1664 | I915_WRITE(reg, val); |
1664 | I915_WRITE(reg, val); |
1665 | POSTING_READ(reg); |
1665 | POSTING_READ(reg); |
1666 | udelay(200); |
1666 | udelay(200); |
1667 | 1667 | ||
1668 | pll->on = false; |
1668 | pll->on = false; |
1669 | } |
1669 | } |
1670 | 1670 | ||
1671 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1671 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1672 | enum pipe pipe) |
1672 | enum pipe pipe) |
1673 | { |
1673 | { |
1674 | int reg; |
1674 | int reg; |
1675 | u32 val, pipeconf_val; |
1675 | u32 val, pipeconf_val; |
1676 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1676 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1677 | 1677 | ||
1678 | /* PCH only available on ILK+ */ |
1678 | /* PCH only available on ILK+ */ |
1679 | BUG_ON(dev_priv->info->gen < 5); |
1679 | BUG_ON(dev_priv->info->gen < 5); |
1680 | 1680 | ||
1681 | /* Make sure PCH DPLL is enabled */ |
1681 | /* Make sure PCH DPLL is enabled */ |
1682 | assert_pch_pll_enabled(dev_priv, |
1682 | assert_pch_pll_enabled(dev_priv, |
1683 | to_intel_crtc(crtc)->pch_pll, |
1683 | to_intel_crtc(crtc)->pch_pll, |
1684 | to_intel_crtc(crtc)); |
1684 | to_intel_crtc(crtc)); |
1685 | 1685 | ||
1686 | /* FDI must be feeding us bits for PCH ports */ |
1686 | /* FDI must be feeding us bits for PCH ports */ |
1687 | assert_fdi_tx_enabled(dev_priv, pipe); |
1687 | assert_fdi_tx_enabled(dev_priv, pipe); |
1688 | assert_fdi_rx_enabled(dev_priv, pipe); |
1688 | assert_fdi_rx_enabled(dev_priv, pipe); |
1689 | 1689 | ||
1690 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1690 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1691 | DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); |
1691 | DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); |
1692 | return; |
1692 | return; |
1693 | } |
1693 | } |
1694 | reg = TRANSCONF(pipe); |
1694 | reg = TRANSCONF(pipe); |
1695 | val = I915_READ(reg); |
1695 | val = I915_READ(reg); |
1696 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1696 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1697 | 1697 | ||
1698 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1698 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1699 | /* |
1699 | /* |
1700 | * make the BPC in transcoder be consistent with |
1700 | * make the BPC in transcoder be consistent with |
1701 | * that in pipeconf reg. |
1701 | * that in pipeconf reg. |
1702 | */ |
1702 | */ |
1703 | val &= ~PIPE_BPC_MASK; |
1703 | val &= ~PIPE_BPC_MASK; |
1704 | val |= pipeconf_val & PIPE_BPC_MASK; |
1704 | val |= pipeconf_val & PIPE_BPC_MASK; |
1705 | } |
1705 | } |
1706 | 1706 | ||
1707 | val &= ~TRANS_INTERLACE_MASK; |
1707 | val &= ~TRANS_INTERLACE_MASK; |
1708 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1708 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1709 | if (HAS_PCH_IBX(dev_priv->dev) && |
1709 | if (HAS_PCH_IBX(dev_priv->dev) && |
1710 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1710 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1711 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1711 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1712 | else |
1712 | else |
1713 | val |= TRANS_INTERLACED; |
1713 | val |= TRANS_INTERLACED; |
1714 | else |
1714 | else |
1715 | val |= TRANS_PROGRESSIVE; |
1715 | val |= TRANS_PROGRESSIVE; |
1716 | 1716 | ||
1717 | I915_WRITE(reg, val | TRANS_ENABLE); |
1717 | I915_WRITE(reg, val | TRANS_ENABLE); |
1718 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1718 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1719 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
1719 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
1720 | } |
1720 | } |
1721 | 1721 | ||
1722 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, |
1722 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, |
1723 | enum pipe pipe) |
1723 | enum pipe pipe) |
1724 | { |
1724 | { |
1725 | int reg; |
1725 | int reg; |
1726 | u32 val; |
1726 | u32 val; |
1727 | 1727 | ||
1728 | /* FDI relies on the transcoder */ |
1728 | /* FDI relies on the transcoder */ |
1729 | assert_fdi_tx_disabled(dev_priv, pipe); |
1729 | assert_fdi_tx_disabled(dev_priv, pipe); |
1730 | assert_fdi_rx_disabled(dev_priv, pipe); |
1730 | assert_fdi_rx_disabled(dev_priv, pipe); |
1731 | 1731 | ||
1732 | /* Ports must be off as well */ |
1732 | /* Ports must be off as well */ |
1733 | assert_pch_ports_disabled(dev_priv, pipe); |
1733 | assert_pch_ports_disabled(dev_priv, pipe); |
1734 | 1734 | ||
1735 | reg = TRANSCONF(pipe); |
1735 | reg = TRANSCONF(pipe); |
1736 | val = I915_READ(reg); |
1736 | val = I915_READ(reg); |
1737 | val &= ~TRANS_ENABLE; |
1737 | val &= ~TRANS_ENABLE; |
1738 | I915_WRITE(reg, val); |
1738 | I915_WRITE(reg, val); |
1739 | /* wait for PCH transcoder off, transcoder state */ |
1739 | /* wait for PCH transcoder off, transcoder state */ |
1740 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1740 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1741 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
1741 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
1742 | } |
1742 | } |
1743 | 1743 | ||
1744 | /** |
1744 | /** |
1745 | * intel_enable_pipe - enable a pipe, asserting requirements |
1745 | * intel_enable_pipe - enable a pipe, asserting requirements |
1746 | * @dev_priv: i915 private structure |
1746 | * @dev_priv: i915 private structure |
1747 | * @pipe: pipe to enable |
1747 | * @pipe: pipe to enable |
1748 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1748 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1749 | * |
1749 | * |
1750 | * Enable @pipe, making sure that various hardware specific requirements |
1750 | * Enable @pipe, making sure that various hardware specific requirements |
1751 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1751 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1752 | * |
1752 | * |
1753 | * @pipe should be %PIPE_A or %PIPE_B. |
1753 | * @pipe should be %PIPE_A or %PIPE_B. |
1754 | * |
1754 | * |
1755 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1755 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1756 | * returning. |
1756 | * returning. |
1757 | */ |
1757 | */ |
1758 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1758 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1759 | bool pch_port) |
1759 | bool pch_port) |
1760 | { |
1760 | { |
1761 | int reg; |
1761 | int reg; |
1762 | u32 val; |
1762 | u32 val; |
1763 | 1763 | ||
1764 | /* |
1764 | /* |
1765 | * A pipe without a PLL won't actually be able to drive bits from |
1765 | * A pipe without a PLL won't actually be able to drive bits from |
1766 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1766 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1767 | * need the check. |
1767 | * need the check. |
1768 | */ |
1768 | */ |
1769 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1769 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1770 | assert_pll_enabled(dev_priv, pipe); |
1770 | assert_pll_enabled(dev_priv, pipe); |
1771 | else { |
1771 | else { |
1772 | if (pch_port) { |
1772 | if (pch_port) { |
1773 | /* if driving the PCH, we need FDI enabled */ |
1773 | /* if driving the PCH, we need FDI enabled */ |
1774 | assert_fdi_rx_pll_enabled(dev_priv, pipe); |
1774 | assert_fdi_rx_pll_enabled(dev_priv, pipe); |
1775 | assert_fdi_tx_pll_enabled(dev_priv, pipe); |
1775 | assert_fdi_tx_pll_enabled(dev_priv, pipe); |
1776 | } |
1776 | } |
1777 | /* FIXME: assert CPU port conditions for SNB+ */ |
1777 | /* FIXME: assert CPU port conditions for SNB+ */ |
1778 | } |
1778 | } |
1779 | 1779 | ||
1780 | reg = PIPECONF(pipe); |
1780 | reg = PIPECONF(pipe); |
1781 | val = I915_READ(reg); |
1781 | val = I915_READ(reg); |
1782 | if (val & PIPECONF_ENABLE) |
1782 | if (val & PIPECONF_ENABLE) |
1783 | return; |
1783 | return; |
1784 | 1784 | ||
1785 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1785 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1787 | } |
1787 | } |
1788 | 1788 | ||
1789 | /** |
1789 | /** |
1790 | * intel_disable_pipe - disable a pipe, asserting requirements |
1790 | * intel_disable_pipe - disable a pipe, asserting requirements |
1791 | * @dev_priv: i915 private structure |
1791 | * @dev_priv: i915 private structure |
1792 | * @pipe: pipe to disable |
1792 | * @pipe: pipe to disable |
1793 | * |
1793 | * |
1794 | * Disable @pipe, making sure that various hardware specific requirements |
1794 | * Disable @pipe, making sure that various hardware specific requirements |
1795 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1795 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1796 | * |
1796 | * |
1797 | * @pipe should be %PIPE_A or %PIPE_B. |
1797 | * @pipe should be %PIPE_A or %PIPE_B. |
1798 | * |
1798 | * |
1799 | * Will wait until the pipe has shut down before returning. |
1799 | * Will wait until the pipe has shut down before returning. |
1800 | */ |
1800 | */ |
1801 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1801 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1802 | enum pipe pipe) |
1802 | enum pipe pipe) |
1803 | { |
1803 | { |
1804 | int reg; |
1804 | int reg; |
1805 | u32 val; |
1805 | u32 val; |
1806 | 1806 | ||
1807 | /* |
1807 | /* |
1808 | * Make sure planes won't keep trying to pump pixels to us, |
1808 | * Make sure planes won't keep trying to pump pixels to us, |
1809 | * or we might hang the display. |
1809 | * or we might hang the display. |
1810 | */ |
1810 | */ |
1811 | assert_planes_disabled(dev_priv, pipe); |
1811 | assert_planes_disabled(dev_priv, pipe); |
1812 | 1812 | ||
1813 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1813 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1814 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1814 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1815 | return; |
1815 | return; |
1816 | 1816 | ||
1817 | reg = PIPECONF(pipe); |
1817 | reg = PIPECONF(pipe); |
1818 | val = I915_READ(reg); |
1818 | val = I915_READ(reg); |
1819 | if ((val & PIPECONF_ENABLE) == 0) |
1819 | if ((val & PIPECONF_ENABLE) == 0) |
1820 | return; |
1820 | return; |
1821 | 1821 | ||
1822 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1822 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1823 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1823 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1824 | - | ||
1825 | } |
1824 | } |
1826 | 1825 | ||
1827 | /* |
1826 | /* |
1828 | * Plane regs are double buffered, going from enabled->disabled needs a |
1827 | * Plane regs are double buffered, going from enabled->disabled needs a |
1829 | * trigger in order to latch. The display address reg provides this. |
1828 | * trigger in order to latch. The display address reg provides this. |
1830 | */ |
1829 | */ |
1831 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1830 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1832 | enum plane plane) |
1831 | enum plane plane) |
1833 | { |
1832 | { |
1834 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1833 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1835 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1834 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1836 | } |
1835 | } |
1837 | 1836 | ||
1838 | /** |
1837 | /** |
1839 | * intel_enable_plane - enable a display plane on a given pipe |
1838 | * intel_enable_plane - enable a display plane on a given pipe |
1840 | * @dev_priv: i915 private structure |
1839 | * @dev_priv: i915 private structure |
1841 | * @plane: plane to enable |
1840 | * @plane: plane to enable |
1842 | * @pipe: pipe being fed |
1841 | * @pipe: pipe being fed |
1843 | * |
1842 | * |
1844 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1843 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1845 | */ |
1844 | */ |
1846 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1845 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1847 | enum plane plane, enum pipe pipe) |
1846 | enum plane plane, enum pipe pipe) |
1848 | { |
1847 | { |
1849 | int reg; |
1848 | int reg; |
1850 | u32 val; |
1849 | u32 val; |
1851 | 1850 | ||
1852 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1851 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1853 | assert_pipe_enabled(dev_priv, pipe); |
1852 | assert_pipe_enabled(dev_priv, pipe); |
1854 | 1853 | ||
1855 | reg = DSPCNTR(plane); |
1854 | reg = DSPCNTR(plane); |
1856 | val = I915_READ(reg); |
1855 | val = I915_READ(reg); |
1857 | if (val & DISPLAY_PLANE_ENABLE) |
1856 | if (val & DISPLAY_PLANE_ENABLE) |
1858 | return; |
1857 | return; |
1859 | 1858 | ||
1860 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1859 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1861 | intel_flush_display_plane(dev_priv, plane); |
1860 | intel_flush_display_plane(dev_priv, plane); |
1862 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1861 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1863 | } |
1862 | } |
1864 | 1863 | ||
1865 | /** |
1864 | /** |
1866 | * intel_disable_plane - disable a display plane |
1865 | * intel_disable_plane - disable a display plane |
1867 | * @dev_priv: i915 private structure |
1866 | * @dev_priv: i915 private structure |
1868 | * @plane: plane to disable |
1867 | * @plane: plane to disable |
1869 | * @pipe: pipe consuming the data |
1868 | * @pipe: pipe consuming the data |
1870 | * |
1869 | * |
1871 | * Disable @plane; should be an independent operation. |
1870 | * Disable @plane; should be an independent operation. |
1872 | */ |
1871 | */ |
1873 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1872 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1874 | enum plane plane, enum pipe pipe) |
1873 | enum plane plane, enum pipe pipe) |
1875 | { |
1874 | { |
1876 | int reg; |
1875 | int reg; |
1877 | u32 val; |
1876 | u32 val; |
1878 | 1877 | ||
1879 | reg = DSPCNTR(plane); |
1878 | reg = DSPCNTR(plane); |
1880 | val = I915_READ(reg); |
1879 | val = I915_READ(reg); |
1881 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1880 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1882 | return; |
1881 | return; |
1883 | 1882 | ||
1884 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1883 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1885 | intel_flush_display_plane(dev_priv, plane); |
1884 | intel_flush_display_plane(dev_priv, plane); |
1886 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1885 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1887 | } |
1886 | } |
1888 | 1887 | ||
1889 | int |
1888 | int |
1890 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1889 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1891 | struct drm_i915_gem_object *obj, |
1890 | struct drm_i915_gem_object *obj, |
1892 | struct intel_ring_buffer *pipelined) |
1891 | struct intel_ring_buffer *pipelined) |
1893 | { |
1892 | { |
1894 | struct drm_i915_private *dev_priv = dev->dev_private; |
1893 | struct drm_i915_private *dev_priv = dev->dev_private; |
1895 | u32 alignment; |
1894 | u32 alignment; |
1896 | int ret; |
1895 | int ret; |
1897 | 1896 | ||
1898 | switch (obj->tiling_mode) { |
1897 | switch (obj->tiling_mode) { |
1899 | case I915_TILING_NONE: |
1898 | case I915_TILING_NONE: |
1900 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1899 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1901 | alignment = 128 * 1024; |
1900 | alignment = 128 * 1024; |
1902 | else if (INTEL_INFO(dev)->gen >= 4) |
1901 | else if (INTEL_INFO(dev)->gen >= 4) |
1903 | alignment = 4 * 1024; |
1902 | alignment = 4 * 1024; |
1904 | else |
1903 | else |
1905 | alignment = 64 * 1024; |
1904 | alignment = 64 * 1024; |
1906 | break; |
1905 | break; |
1907 | case I915_TILING_X: |
1906 | case I915_TILING_X: |
1908 | /* pin() will align the object as required by fence */ |
1907 | /* pin() will align the object as required by fence */ |
1909 | alignment = 0; |
1908 | alignment = 0; |
1910 | break; |
1909 | break; |
1911 | case I915_TILING_Y: |
1910 | case I915_TILING_Y: |
1912 | /* FIXME: Is this true? */ |
1911 | /* FIXME: Is this true? */ |
1913 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
1912 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
1914 | return -EINVAL; |
1913 | return -EINVAL; |
1915 | default: |
1914 | default: |
1916 | BUG(); |
1915 | BUG(); |
1917 | } |
1916 | } |
1918 | 1917 | ||
1919 | dev_priv->mm.interruptible = false; |
1918 | dev_priv->mm.interruptible = false; |
1920 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1919 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1921 | if (ret) |
1920 | if (ret) |
1922 | goto err_interruptible; |
1921 | goto err_interruptible; |
1923 | 1922 | ||
1924 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1923 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1925 | * fence, whereas 965+ only requires a fence if using |
1924 | * fence, whereas 965+ only requires a fence if using |
1926 | * framebuffer compression. For simplicity, we always install |
1925 | * framebuffer compression. For simplicity, we always install |
1927 | * a fence as the cost is not that onerous. |
1926 | * a fence as the cost is not that onerous. |
1928 | */ |
1927 | */ |
1929 | // if (obj->tiling_mode != I915_TILING_NONE) { |
1928 | // if (obj->tiling_mode != I915_TILING_NONE) { |
1930 | // ret = i915_gem_object_get_fence(obj, pipelined); |
1929 | // ret = i915_gem_object_get_fence(obj, pipelined); |
1931 | // if (ret) |
1930 | // if (ret) |
1932 | // goto err_unpin; |
1931 | // goto err_unpin; |
1933 | // } |
1932 | // } |
1934 | 1933 | ||
1935 | dev_priv->mm.interruptible = true; |
1934 | dev_priv->mm.interruptible = true; |
1936 | return 0; |
1935 | return 0; |
1937 | 1936 | ||
1938 | err_unpin: |
1937 | err_unpin: |
1939 | i915_gem_object_unpin(obj); |
1938 | i915_gem_object_unpin(obj); |
1940 | err_interruptible: |
1939 | err_interruptible: |
1941 | dev_priv->mm.interruptible = true; |
1940 | dev_priv->mm.interruptible = true; |
1942 | return ret; |
1941 | return ret; |
1943 | } |
1942 | } |
1944 | 1943 | ||
1945 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1944 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1946 | { |
1945 | { |
1947 | // i915_gem_object_unpin_fence(obj); |
1946 | // i915_gem_object_unpin_fence(obj); |
1948 | // i915_gem_object_unpin(obj); |
1947 | // i915_gem_object_unpin(obj); |
1949 | } |
1948 | } |
1950 | 1949 | ||
1951 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1950 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1952 | * is assumed to be a power-of-two. */ |
1951 | * is assumed to be a power-of-two. */ |
1953 | static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, |
1952 | static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, |
1954 | unsigned int bpp, |
1953 | unsigned int bpp, |
1955 | unsigned int pitch) |
1954 | unsigned int pitch) |
1956 | { |
1955 | { |
1957 | int tile_rows, tiles; |
1956 | int tile_rows, tiles; |
1958 | 1957 | ||
1959 | tile_rows = *y / 8; |
1958 | tile_rows = *y / 8; |
1960 | *y %= 8; |
1959 | *y %= 8; |
1961 | tiles = *x / (512/bpp); |
1960 | tiles = *x / (512/bpp); |
1962 | *x %= 512/bpp; |
1961 | *x %= 512/bpp; |
1963 | 1962 | ||
1964 | return tile_rows * pitch * 8 + tiles * 4096; |
1963 | return tile_rows * pitch * 8 + tiles * 4096; |
1965 | } |
1964 | } |
1966 | 1965 | ||
1967 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1966 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1968 | int x, int y) |
1967 | int x, int y) |
1969 | { |
1968 | { |
1970 | struct drm_device *dev = crtc->dev; |
1969 | struct drm_device *dev = crtc->dev; |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; |
1970 | struct drm_i915_private *dev_priv = dev->dev_private; |
1972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1973 | struct intel_framebuffer *intel_fb; |
1972 | struct intel_framebuffer *intel_fb; |
1974 | struct drm_i915_gem_object *obj; |
1973 | struct drm_i915_gem_object *obj; |
1975 | int plane = intel_crtc->plane; |
1974 | int plane = intel_crtc->plane; |
1976 | unsigned long linear_offset; |
1975 | unsigned long linear_offset; |
1977 | u32 dspcntr; |
1976 | u32 dspcntr; |
1978 | u32 reg; |
1977 | u32 reg; |
1979 | 1978 | ||
1980 | switch (plane) { |
1979 | switch (plane) { |
1981 | case 0: |
1980 | case 0: |
1982 | case 1: |
1981 | case 1: |
1983 | break; |
1982 | break; |
1984 | default: |
1983 | default: |
1985 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
1984 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
1986 | return -EINVAL; |
1985 | return -EINVAL; |
1987 | } |
1986 | } |
1988 | 1987 | ||
1989 | intel_fb = to_intel_framebuffer(fb); |
1988 | intel_fb = to_intel_framebuffer(fb); |
1990 | obj = intel_fb->obj; |
1989 | obj = intel_fb->obj; |
1991 | 1990 | ||
1992 | reg = DSPCNTR(plane); |
1991 | reg = DSPCNTR(plane); |
1993 | dspcntr = I915_READ(reg); |
1992 | dspcntr = I915_READ(reg); |
1994 | /* Mask out pixel format bits in case we change it */ |
1993 | /* Mask out pixel format bits in case we change it */ |
1995 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1994 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1996 | switch (fb->bits_per_pixel) { |
1995 | switch (fb->bits_per_pixel) { |
1997 | case 8: |
1996 | case 8: |
1998 | dspcntr |= DISPPLANE_8BPP; |
1997 | dspcntr |= DISPPLANE_8BPP; |
1999 | break; |
1998 | break; |
2000 | case 16: |
1999 | case 16: |
2001 | if (fb->depth == 15) |
2000 | if (fb->depth == 15) |
2002 | dspcntr |= DISPPLANE_15_16BPP; |
2001 | dspcntr |= DISPPLANE_15_16BPP; |
2003 | else |
2002 | else |
2004 | dspcntr |= DISPPLANE_16BPP; |
2003 | dspcntr |= DISPPLANE_16BPP; |
2005 | break; |
2004 | break; |
2006 | case 24: |
2005 | case 24: |
2007 | case 32: |
2006 | case 32: |
2008 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
2007 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
2009 | break; |
2008 | break; |
2010 | default: |
2009 | default: |
2011 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
2010 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
2012 | return -EINVAL; |
2011 | return -EINVAL; |
2013 | } |
2012 | } |
2014 | if (INTEL_INFO(dev)->gen >= 4) { |
2013 | if (INTEL_INFO(dev)->gen >= 4) { |
2015 | if (obj->tiling_mode != I915_TILING_NONE) |
2014 | if (obj->tiling_mode != I915_TILING_NONE) |
2016 | dspcntr |= DISPPLANE_TILED; |
2015 | dspcntr |= DISPPLANE_TILED; |
2017 | else |
2016 | else |
2018 | dspcntr &= ~DISPPLANE_TILED; |
2017 | dspcntr &= ~DISPPLANE_TILED; |
2019 | } |
2018 | } |
2020 | 2019 | ||
2021 | I915_WRITE(reg, dspcntr); |
2020 | I915_WRITE(reg, dspcntr); |
2022 | 2021 | ||
2023 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2022 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2024 | 2023 | ||
2025 | if (INTEL_INFO(dev)->gen >= 4) { |
2024 | if (INTEL_INFO(dev)->gen >= 4) { |
2026 | intel_crtc->dspaddr_offset = |
2025 | intel_crtc->dspaddr_offset = |
2027 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
2026 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
2028 | fb->bits_per_pixel / 8, |
2027 | fb->bits_per_pixel / 8, |
2029 | fb->pitches[0]); |
2028 | fb->pitches[0]); |
2030 | linear_offset -= intel_crtc->dspaddr_offset; |
2029 | linear_offset -= intel_crtc->dspaddr_offset; |
2031 | } else { |
2030 | } else { |
2032 | intel_crtc->dspaddr_offset = linear_offset; |
2031 | intel_crtc->dspaddr_offset = linear_offset; |
2033 | } |
2032 | } |
2034 | 2033 | ||
2035 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2034 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2036 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
2035 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
2037 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2036 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2038 | if (INTEL_INFO(dev)->gen >= 4) { |
2037 | if (INTEL_INFO(dev)->gen >= 4) { |
2039 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2038 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2040 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
2039 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
2041 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2040 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2042 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2041 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2043 | } else |
2042 | } else |
2044 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
2043 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
2045 | POSTING_READ(reg); |
2044 | POSTING_READ(reg); |
2046 | 2045 | ||
2047 | return 0; |
2046 | return 0; |
2048 | } |
2047 | } |
2049 | 2048 | ||
2050 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2049 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2051 | struct drm_framebuffer *fb, int x, int y) |
2050 | struct drm_framebuffer *fb, int x, int y) |
2052 | { |
2051 | { |
2053 | struct drm_device *dev = crtc->dev; |
2052 | struct drm_device *dev = crtc->dev; |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; |
2053 | struct drm_i915_private *dev_priv = dev->dev_private; |
2055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2056 | struct intel_framebuffer *intel_fb; |
2055 | struct intel_framebuffer *intel_fb; |
2057 | struct drm_i915_gem_object *obj; |
2056 | struct drm_i915_gem_object *obj; |
2058 | int plane = intel_crtc->plane; |
2057 | int plane = intel_crtc->plane; |
2059 | unsigned long linear_offset; |
2058 | unsigned long linear_offset; |
2060 | u32 dspcntr; |
2059 | u32 dspcntr; |
2061 | u32 reg; |
2060 | u32 reg; |
2062 | 2061 | ||
2063 | switch (plane) { |
2062 | switch (plane) { |
2064 | case 0: |
2063 | case 0: |
2065 | case 1: |
2064 | case 1: |
2066 | case 2: |
2065 | case 2: |
2067 | break; |
2066 | break; |
2068 | default: |
2067 | default: |
2069 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
2068 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
2070 | return -EINVAL; |
2069 | return -EINVAL; |
2071 | } |
2070 | } |
2072 | 2071 | ||
2073 | intel_fb = to_intel_framebuffer(fb); |
2072 | intel_fb = to_intel_framebuffer(fb); |
2074 | obj = intel_fb->obj; |
2073 | obj = intel_fb->obj; |
2075 | 2074 | ||
2076 | reg = DSPCNTR(plane); |
2075 | reg = DSPCNTR(plane); |
2077 | dspcntr = I915_READ(reg); |
2076 | dspcntr = I915_READ(reg); |
2078 | /* Mask out pixel format bits in case we change it */ |
2077 | /* Mask out pixel format bits in case we change it */ |
2079 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2078 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2080 | switch (fb->bits_per_pixel) { |
2079 | switch (fb->bits_per_pixel) { |
2081 | case 8: |
2080 | case 8: |
2082 | dspcntr |= DISPPLANE_8BPP; |
2081 | dspcntr |= DISPPLANE_8BPP; |
2083 | break; |
2082 | break; |
2084 | case 16: |
2083 | case 16: |
2085 | if (fb->depth != 16) |
2084 | if (fb->depth != 16) |
2086 | return -EINVAL; |
2085 | return -EINVAL; |
2087 | 2086 | ||
2088 | dspcntr |= DISPPLANE_16BPP; |
2087 | dspcntr |= DISPPLANE_16BPP; |
2089 | break; |
2088 | break; |
2090 | case 24: |
2089 | case 24: |
2091 | case 32: |
2090 | case 32: |
2092 | if (fb->depth == 24) |
2091 | if (fb->depth == 24) |
2093 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
2092 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
2094 | else if (fb->depth == 30) |
2093 | else if (fb->depth == 30) |
2095 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
2094 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
2096 | else |
2095 | else |
2097 | return -EINVAL; |
2096 | return -EINVAL; |
2098 | break; |
2097 | break; |
2099 | default: |
2098 | default: |
2100 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
2099 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
2101 | return -EINVAL; |
2100 | return -EINVAL; |
2102 | } |
2101 | } |
2103 | 2102 | ||
2104 | // if (obj->tiling_mode != I915_TILING_NONE) |
2103 | // if (obj->tiling_mode != I915_TILING_NONE) |
2105 | // dspcntr |= DISPPLANE_TILED; |
2104 | // dspcntr |= DISPPLANE_TILED; |
2106 | // else |
2105 | // else |
2107 | dspcntr &= ~DISPPLANE_TILED; |
2106 | dspcntr &= ~DISPPLANE_TILED; |
2108 | 2107 | ||
2109 | /* must disable */ |
2108 | /* must disable */ |
2110 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2109 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2111 | 2110 | ||
2112 | I915_WRITE(reg, dspcntr); |
2111 | I915_WRITE(reg, dspcntr); |
2113 | 2112 | ||
2114 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2113 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2115 | intel_crtc->dspaddr_offset = |
2114 | intel_crtc->dspaddr_offset = |
2116 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
2115 | gen4_compute_dspaddr_offset_xtiled(&x, &y, |
2117 | fb->bits_per_pixel / 8, |
2116 | fb->bits_per_pixel / 8, |
2118 | fb->pitches[0]); |
2117 | fb->pitches[0]); |
2119 | linear_offset -= intel_crtc->dspaddr_offset; |
2118 | linear_offset -= intel_crtc->dspaddr_offset; |
2120 | 2119 | ||
2121 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2120 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2122 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
2121 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); |
2123 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2122 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2124 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2123 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2125 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
2124 | obj->gtt_offset + intel_crtc->dspaddr_offset); |
2126 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2125 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2127 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2126 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2128 | POSTING_READ(reg); |
2127 | POSTING_READ(reg); |
2129 | 2128 | ||
2130 | return 0; |
2129 | return 0; |
2131 | } |
2130 | } |
2132 | 2131 | ||
2133 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2132 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2134 | static int |
2133 | static int |
2135 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2134 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2136 | int x, int y, enum mode_set_atomic state) |
2135 | int x, int y, enum mode_set_atomic state) |
2137 | { |
2136 | { |
2138 | struct drm_device *dev = crtc->dev; |
2137 | struct drm_device *dev = crtc->dev; |
2139 | struct drm_i915_private *dev_priv = dev->dev_private; |
2138 | struct drm_i915_private *dev_priv = dev->dev_private; |
2140 | 2139 | ||
2141 | if (dev_priv->display.disable_fbc) |
2140 | if (dev_priv->display.disable_fbc) |
2142 | dev_priv->display.disable_fbc(dev); |
2141 | dev_priv->display.disable_fbc(dev); |
2143 | intel_increase_pllclock(crtc); |
2142 | intel_increase_pllclock(crtc); |
2144 | 2143 | ||
2145 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2144 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2146 | } |
2145 | } |
2147 | 2146 | ||
2148 | #if 0 |
2147 | #if 0 |
2149 | static int |
2148 | static int |
2150 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2149 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2151 | { |
2150 | { |
2152 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2151 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2153 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2152 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2154 | bool was_interruptible = dev_priv->mm.interruptible; |
2153 | bool was_interruptible = dev_priv->mm.interruptible; |
2155 | int ret; |
2154 | int ret; |
2156 | 2155 | ||
2157 | wait_event(dev_priv->pending_flip_queue, |
2156 | wait_event(dev_priv->pending_flip_queue, |
2158 | atomic_read(&dev_priv->mm.wedged) || |
2157 | atomic_read(&dev_priv->mm.wedged) || |
2159 | atomic_read(&obj->pending_flip) == 0); |
2158 | atomic_read(&obj->pending_flip) == 0); |
2160 | 2159 | ||
2161 | /* Big Hammer, we also need to ensure that any pending |
2160 | /* Big Hammer, we also need to ensure that any pending |
2162 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2161 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2163 | * current scanout is retired before unpinning the old |
2162 | * current scanout is retired before unpinning the old |
2164 | * framebuffer. |
2163 | * framebuffer. |
2165 | * |
2164 | * |
2166 | * This should only fail upon a hung GPU, in which case we |
2165 | * This should only fail upon a hung GPU, in which case we |
2167 | * can safely continue. |
2166 | * can safely continue. |
2168 | */ |
2167 | */ |
2169 | dev_priv->mm.interruptible = false; |
2168 | dev_priv->mm.interruptible = false; |
2170 | ret = i915_gem_object_finish_gpu(obj); |
2169 | ret = i915_gem_object_finish_gpu(obj); |
2171 | dev_priv->mm.interruptible = was_interruptible; |
2170 | dev_priv->mm.interruptible = was_interruptible; |
2172 | 2171 | ||
2173 | return ret; |
2172 | return ret; |
2174 | } |
2173 | } |
2175 | #endif |
2174 | #endif |
2176 | 2175 | ||
2177 | static int |
2176 | static int |
2178 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2177 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2179 | struct drm_framebuffer *fb) |
2178 | struct drm_framebuffer *fb) |
2180 | { |
2179 | { |
2181 | struct drm_device *dev = crtc->dev; |
2180 | struct drm_device *dev = crtc->dev; |
2182 | struct drm_i915_private *dev_priv = dev->dev_private; |
2181 | struct drm_i915_private *dev_priv = dev->dev_private; |
2183 | struct drm_i915_master_private *master_priv; |
2182 | struct drm_i915_master_private *master_priv; |
2184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2185 | struct drm_framebuffer *old_fb; |
2184 | struct drm_framebuffer *old_fb; |
2186 | int ret; |
2185 | int ret; |
2187 | 2186 | ||
2188 | /* no fb bound */ |
2187 | /* no fb bound */ |
2189 | if (!fb) { |
2188 | if (!fb) { |
2190 | DRM_ERROR("No FB bound\n"); |
2189 | DRM_ERROR("No FB bound\n"); |
2191 | return 0; |
2190 | return 0; |
2192 | } |
2191 | } |
2193 | 2192 | ||
2194 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2193 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2195 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", |
2194 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", |
2196 | intel_crtc->plane, |
2195 | intel_crtc->plane, |
2197 | dev_priv->num_pipe); |
2196 | dev_priv->num_pipe); |
2198 | return -EINVAL; |
2197 | return -EINVAL; |
2199 | } |
2198 | } |
2200 | 2199 | ||
2201 | mutex_lock(&dev->struct_mutex); |
2200 | mutex_lock(&dev->struct_mutex); |
2202 | // ret = intel_pin_and_fence_fb_obj(dev, |
2201 | // ret = intel_pin_and_fence_fb_obj(dev, |
2203 | // to_intel_framebuffer(fb)->obj, |
2202 | // to_intel_framebuffer(fb)->obj, |
2204 | // NULL); |
2203 | // NULL); |
2205 | // if (ret != 0) { |
2204 | // if (ret != 0) { |
2206 | // mutex_unlock(&dev->struct_mutex); |
2205 | // mutex_unlock(&dev->struct_mutex); |
2207 | // DRM_ERROR("pin & fence failed\n"); |
2206 | // DRM_ERROR("pin & fence failed\n"); |
2208 | // return ret; |
2207 | // return ret; |
2209 | // } |
2208 | // } |
2210 | 2209 | ||
2211 | // if (crtc->fb) |
2210 | // if (crtc->fb) |
2212 | // intel_finish_fb(crtc->fb); |
2211 | // intel_finish_fb(crtc->fb); |
2213 | 2212 | ||
2214 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2213 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2215 | if (ret) { |
2214 | if (ret) { |
2216 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2215 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2217 | mutex_unlock(&dev->struct_mutex); |
2216 | mutex_unlock(&dev->struct_mutex); |
2218 | DRM_ERROR("failed to update base address\n"); |
2217 | DRM_ERROR("failed to update base address\n"); |
2219 | LEAVE(); |
- | |
2220 | return ret; |
2218 | return ret; |
2221 | } |
2219 | } |
2222 | 2220 | ||
2223 | old_fb = crtc->fb; |
2221 | old_fb = crtc->fb; |
2224 | crtc->fb = fb; |
2222 | crtc->fb = fb; |
2225 | crtc->x = x; |
2223 | crtc->x = x; |
2226 | crtc->y = y; |
2224 | crtc->y = y; |
2227 | 2225 | ||
2228 | if (old_fb) { |
2226 | if (old_fb) { |
2229 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2227 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2230 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2228 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2231 | } |
2229 | } |
2232 | 2230 | ||
2233 | intel_update_fbc(dev); |
2231 | intel_update_fbc(dev); |
2234 | mutex_unlock(&dev->struct_mutex); |
2232 | mutex_unlock(&dev->struct_mutex); |
2235 | 2233 | ||
2236 | return 0; |
2234 | return 0; |
2237 | } |
2235 | } |
2238 | 2236 | ||
2239 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
2237 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
2240 | { |
2238 | { |
2241 | struct drm_device *dev = crtc->dev; |
2239 | struct drm_device *dev = crtc->dev; |
2242 | struct drm_i915_private *dev_priv = dev->dev_private; |
2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
2243 | u32 dpa_ctl; |
2241 | u32 dpa_ctl; |
2244 | 2242 | ||
2245 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
2243 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
2246 | dpa_ctl = I915_READ(DP_A); |
2244 | dpa_ctl = I915_READ(DP_A); |
2247 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
2245 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
2248 | 2246 | ||
2249 | if (clock < 200000) { |
2247 | if (clock < 200000) { |
2250 | u32 temp; |
2248 | u32 temp; |
2251 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
2249 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
2252 | /* workaround for 160Mhz: |
2250 | /* workaround for 160Mhz: |
2253 | 1) program 0x4600c bits 15:0 = 0x8124 |
2251 | 1) program 0x4600c bits 15:0 = 0x8124 |
2254 | 2) program 0x46010 bit 0 = 1 |
2252 | 2) program 0x46010 bit 0 = 1 |
2255 | 3) program 0x46034 bit 24 = 1 |
2253 | 3) program 0x46034 bit 24 = 1 |
2256 | 4) program 0x64000 bit 14 = 1 |
2254 | 4) program 0x64000 bit 14 = 1 |
2257 | */ |
2255 | */ |
2258 | temp = I915_READ(0x4600c); |
2256 | temp = I915_READ(0x4600c); |
2259 | temp &= 0xffff0000; |
2257 | temp &= 0xffff0000; |
2260 | I915_WRITE(0x4600c, temp | 0x8124); |
2258 | I915_WRITE(0x4600c, temp | 0x8124); |
2261 | 2259 | ||
2262 | temp = I915_READ(0x46010); |
2260 | temp = I915_READ(0x46010); |
2263 | I915_WRITE(0x46010, temp | 1); |
2261 | I915_WRITE(0x46010, temp | 1); |
2264 | 2262 | ||
2265 | temp = I915_READ(0x46034); |
2263 | temp = I915_READ(0x46034); |
2266 | I915_WRITE(0x46034, temp | (1 << 24)); |
2264 | I915_WRITE(0x46034, temp | (1 << 24)); |
2267 | } else { |
2265 | } else { |
2268 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
2266 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
2269 | } |
2267 | } |
2270 | I915_WRITE(DP_A, dpa_ctl); |
2268 | I915_WRITE(DP_A, dpa_ctl); |
2271 | 2269 | ||
2272 | POSTING_READ(DP_A); |
2270 | POSTING_READ(DP_A); |
2273 | udelay(500); |
2271 | udelay(500); |
2274 | } |
2272 | } |
2275 | 2273 | ||
2276 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2274 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2277 | { |
2275 | { |
2278 | struct drm_device *dev = crtc->dev; |
2276 | struct drm_device *dev = crtc->dev; |
2279 | struct drm_i915_private *dev_priv = dev->dev_private; |
2277 | struct drm_i915_private *dev_priv = dev->dev_private; |
2280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2281 | int pipe = intel_crtc->pipe; |
2279 | int pipe = intel_crtc->pipe; |
2282 | u32 reg, temp; |
2280 | u32 reg, temp; |
2283 | 2281 | ||
2284 | /* enable normal train */ |
2282 | /* enable normal train */ |
2285 | reg = FDI_TX_CTL(pipe); |
2283 | reg = FDI_TX_CTL(pipe); |
2286 | temp = I915_READ(reg); |
2284 | temp = I915_READ(reg); |
2287 | if (IS_IVYBRIDGE(dev)) { |
2285 | if (IS_IVYBRIDGE(dev)) { |
2288 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2286 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2289 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2287 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2290 | } else { |
2288 | } else { |
2291 | temp &= ~FDI_LINK_TRAIN_NONE; |
2289 | temp &= ~FDI_LINK_TRAIN_NONE; |
2292 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2290 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2293 | } |
2291 | } |
2294 | I915_WRITE(reg, temp); |
2292 | I915_WRITE(reg, temp); |
2295 | 2293 | ||
2296 | reg = FDI_RX_CTL(pipe); |
2294 | reg = FDI_RX_CTL(pipe); |
2297 | temp = I915_READ(reg); |
2295 | temp = I915_READ(reg); |
2298 | if (HAS_PCH_CPT(dev)) { |
2296 | if (HAS_PCH_CPT(dev)) { |
2299 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2297 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2300 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2298 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2301 | } else { |
2299 | } else { |
2302 | temp &= ~FDI_LINK_TRAIN_NONE; |
2300 | temp &= ~FDI_LINK_TRAIN_NONE; |
2303 | temp |= FDI_LINK_TRAIN_NONE; |
2301 | temp |= FDI_LINK_TRAIN_NONE; |
2304 | } |
2302 | } |
2305 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2303 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2306 | 2304 | ||
2307 | /* wait one idle pattern time */ |
2305 | /* wait one idle pattern time */ |
2308 | POSTING_READ(reg); |
2306 | POSTING_READ(reg); |
2309 | udelay(1000); |
2307 | udelay(1000); |
2310 | 2308 | ||
2311 | /* IVB wants error correction enabled */ |
2309 | /* IVB wants error correction enabled */ |
2312 | if (IS_IVYBRIDGE(dev)) |
2310 | if (IS_IVYBRIDGE(dev)) |
2313 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2311 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2314 | FDI_FE_ERRC_ENABLE); |
2312 | FDI_FE_ERRC_ENABLE); |
2315 | } |
2313 | } |
2316 | 2314 | ||
2317 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2315 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2318 | { |
2316 | { |
2319 | struct drm_i915_private *dev_priv = dev->dev_private; |
2317 | struct drm_i915_private *dev_priv = dev->dev_private; |
2320 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
2318 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
2321 | 2319 | ||
2322 | flags |= FDI_PHASE_SYNC_OVR(pipe); |
2320 | flags |= FDI_PHASE_SYNC_OVR(pipe); |
2323 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ |
2321 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ |
2324 | flags |= FDI_PHASE_SYNC_EN(pipe); |
2322 | flags |= FDI_PHASE_SYNC_EN(pipe); |
2325 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ |
2323 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ |
2326 | POSTING_READ(SOUTH_CHICKEN1); |
2324 | POSTING_READ(SOUTH_CHICKEN1); |
2327 | } |
2325 | } |
2328 | 2326 | ||
2329 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2327 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2330 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2328 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2331 | { |
2329 | { |
2332 | struct drm_device *dev = crtc->dev; |
2330 | struct drm_device *dev = crtc->dev; |
2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
2331 | struct drm_i915_private *dev_priv = dev->dev_private; |
2334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2335 | int pipe = intel_crtc->pipe; |
2333 | int pipe = intel_crtc->pipe; |
2336 | int plane = intel_crtc->plane; |
2334 | int plane = intel_crtc->plane; |
2337 | u32 reg, temp, tries; |
2335 | u32 reg, temp, tries; |
2338 | 2336 | ||
2339 | /* FDI needs bits from pipe & plane first */ |
2337 | /* FDI needs bits from pipe & plane first */ |
2340 | assert_pipe_enabled(dev_priv, pipe); |
2338 | assert_pipe_enabled(dev_priv, pipe); |
2341 | assert_plane_enabled(dev_priv, plane); |
2339 | assert_plane_enabled(dev_priv, plane); |
2342 | 2340 | ||
2343 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2341 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2344 | for train result */ |
2342 | for train result */ |
2345 | reg = FDI_RX_IMR(pipe); |
2343 | reg = FDI_RX_IMR(pipe); |
2346 | temp = I915_READ(reg); |
2344 | temp = I915_READ(reg); |
2347 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2345 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2348 | temp &= ~FDI_RX_BIT_LOCK; |
2346 | temp &= ~FDI_RX_BIT_LOCK; |
2349 | I915_WRITE(reg, temp); |
2347 | I915_WRITE(reg, temp); |
2350 | I915_READ(reg); |
2348 | I915_READ(reg); |
2351 | udelay(150); |
2349 | udelay(150); |
2352 | 2350 | ||
2353 | /* enable CPU FDI TX and PCH FDI RX */ |
2351 | /* enable CPU FDI TX and PCH FDI RX */ |
2354 | reg = FDI_TX_CTL(pipe); |
2352 | reg = FDI_TX_CTL(pipe); |
2355 | temp = I915_READ(reg); |
2353 | temp = I915_READ(reg); |
2356 | temp &= ~(7 << 19); |
2354 | temp &= ~(7 << 19); |
2357 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2355 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2358 | temp &= ~FDI_LINK_TRAIN_NONE; |
2356 | temp &= ~FDI_LINK_TRAIN_NONE; |
2359 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2357 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2360 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2358 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2361 | 2359 | ||
2362 | reg = FDI_RX_CTL(pipe); |
2360 | reg = FDI_RX_CTL(pipe); |
2363 | temp = I915_READ(reg); |
2361 | temp = I915_READ(reg); |
2364 | temp &= ~FDI_LINK_TRAIN_NONE; |
2362 | temp &= ~FDI_LINK_TRAIN_NONE; |
2365 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2363 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2366 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2364 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2367 | 2365 | ||
2368 | POSTING_READ(reg); |
2366 | POSTING_READ(reg); |
2369 | udelay(150); |
2367 | udelay(150); |
2370 | 2368 | ||
2371 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2369 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2372 | if (HAS_PCH_IBX(dev)) { |
2370 | if (HAS_PCH_IBX(dev)) { |
2373 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2371 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2374 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2372 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2375 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2373 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2376 | } |
2374 | } |
2377 | 2375 | ||
2378 | reg = FDI_RX_IIR(pipe); |
2376 | reg = FDI_RX_IIR(pipe); |
2379 | for (tries = 0; tries < 5; tries++) { |
2377 | for (tries = 0; tries < 5; tries++) { |
2380 | temp = I915_READ(reg); |
2378 | temp = I915_READ(reg); |
2381 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2379 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2382 | 2380 | ||
2383 | if ((temp & FDI_RX_BIT_LOCK)) { |
2381 | if ((temp & FDI_RX_BIT_LOCK)) { |
2384 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2382 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2385 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2383 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2386 | break; |
2384 | break; |
2387 | } |
2385 | } |
2388 | } |
2386 | } |
2389 | if (tries == 5) |
2387 | if (tries == 5) |
2390 | DRM_ERROR("FDI train 1 fail!\n"); |
2388 | DRM_ERROR("FDI train 1 fail!\n"); |
2391 | 2389 | ||
2392 | /* Train 2 */ |
2390 | /* Train 2 */ |
2393 | reg = FDI_TX_CTL(pipe); |
2391 | reg = FDI_TX_CTL(pipe); |
2394 | temp = I915_READ(reg); |
2392 | temp = I915_READ(reg); |
2395 | temp &= ~FDI_LINK_TRAIN_NONE; |
2393 | temp &= ~FDI_LINK_TRAIN_NONE; |
2396 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2394 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2397 | I915_WRITE(reg, temp); |
2395 | I915_WRITE(reg, temp); |
2398 | 2396 | ||
2399 | reg = FDI_RX_CTL(pipe); |
2397 | reg = FDI_RX_CTL(pipe); |
2400 | temp = I915_READ(reg); |
2398 | temp = I915_READ(reg); |
2401 | temp &= ~FDI_LINK_TRAIN_NONE; |
2399 | temp &= ~FDI_LINK_TRAIN_NONE; |
2402 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2400 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2403 | I915_WRITE(reg, temp); |
2401 | I915_WRITE(reg, temp); |
2404 | 2402 | ||
2405 | POSTING_READ(reg); |
2403 | POSTING_READ(reg); |
2406 | udelay(150); |
2404 | udelay(150); |
2407 | 2405 | ||
2408 | reg = FDI_RX_IIR(pipe); |
2406 | reg = FDI_RX_IIR(pipe); |
2409 | for (tries = 0; tries < 5; tries++) { |
2407 | for (tries = 0; tries < 5; tries++) { |
2410 | temp = I915_READ(reg); |
2408 | temp = I915_READ(reg); |
2411 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2409 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2412 | 2410 | ||
2413 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2411 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2414 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2412 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2415 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2413 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2416 | break; |
2414 | break; |
2417 | } |
2415 | } |
2418 | } |
2416 | } |
2419 | if (tries == 5) |
2417 | if (tries == 5) |
2420 | DRM_ERROR("FDI train 2 fail!\n"); |
2418 | DRM_ERROR("FDI train 2 fail!\n"); |
2421 | 2419 | ||
2422 | DRM_DEBUG_KMS("FDI train done\n"); |
2420 | DRM_DEBUG_KMS("FDI train done\n"); |
2423 | 2421 | ||
2424 | } |
2422 | } |
2425 | 2423 | ||
2426 | static const int snb_b_fdi_train_param[] = { |
2424 | static const int snb_b_fdi_train_param[] = { |
2427 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2425 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2428 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2426 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2429 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2427 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2430 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2428 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2431 | }; |
2429 | }; |
2432 | 2430 | ||
2433 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2431 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2434 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2432 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2435 | { |
2433 | { |
2436 | struct drm_device *dev = crtc->dev; |
2434 | struct drm_device *dev = crtc->dev; |
2437 | struct drm_i915_private *dev_priv = dev->dev_private; |
2435 | struct drm_i915_private *dev_priv = dev->dev_private; |
2438 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2439 | int pipe = intel_crtc->pipe; |
2437 | int pipe = intel_crtc->pipe; |
2440 | u32 reg, temp, i, retry; |
2438 | u32 reg, temp, i, retry; |
2441 | 2439 | ||
2442 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2440 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2443 | for train result */ |
2441 | for train result */ |
2444 | reg = FDI_RX_IMR(pipe); |
2442 | reg = FDI_RX_IMR(pipe); |
2445 | temp = I915_READ(reg); |
2443 | temp = I915_READ(reg); |
2446 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2444 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2447 | temp &= ~FDI_RX_BIT_LOCK; |
2445 | temp &= ~FDI_RX_BIT_LOCK; |
2448 | I915_WRITE(reg, temp); |
2446 | I915_WRITE(reg, temp); |
2449 | 2447 | ||
2450 | POSTING_READ(reg); |
2448 | POSTING_READ(reg); |
2451 | udelay(150); |
2449 | udelay(150); |
2452 | 2450 | ||
2453 | /* enable CPU FDI TX and PCH FDI RX */ |
2451 | /* enable CPU FDI TX and PCH FDI RX */ |
2454 | reg = FDI_TX_CTL(pipe); |
2452 | reg = FDI_TX_CTL(pipe); |
2455 | temp = I915_READ(reg); |
2453 | temp = I915_READ(reg); |
2456 | temp &= ~(7 << 19); |
2454 | temp &= ~(7 << 19); |
2457 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2455 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2458 | temp &= ~FDI_LINK_TRAIN_NONE; |
2456 | temp &= ~FDI_LINK_TRAIN_NONE; |
2459 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2457 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2460 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2458 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2461 | /* SNB-B */ |
2459 | /* SNB-B */ |
2462 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2460 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2463 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2461 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2464 | 2462 | ||
2465 | reg = FDI_RX_CTL(pipe); |
2463 | reg = FDI_RX_CTL(pipe); |
2466 | temp = I915_READ(reg); |
2464 | temp = I915_READ(reg); |
2467 | if (HAS_PCH_CPT(dev)) { |
2465 | if (HAS_PCH_CPT(dev)) { |
2468 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2466 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2469 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2467 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2470 | } else { |
2468 | } else { |
2471 | temp &= ~FDI_LINK_TRAIN_NONE; |
2469 | temp &= ~FDI_LINK_TRAIN_NONE; |
2472 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2470 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2473 | } |
2471 | } |
2474 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2472 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2475 | 2473 | ||
2476 | POSTING_READ(reg); |
2474 | POSTING_READ(reg); |
2477 | udelay(150); |
2475 | udelay(150); |
2478 | 2476 | ||
2479 | if (HAS_PCH_CPT(dev)) |
2477 | if (HAS_PCH_CPT(dev)) |
2480 | cpt_phase_pointer_enable(dev, pipe); |
2478 | cpt_phase_pointer_enable(dev, pipe); |
2481 | 2479 | ||
2482 | for (i = 0; i < 4; i++) { |
2480 | for (i = 0; i < 4; i++) { |
2483 | reg = FDI_TX_CTL(pipe); |
2481 | reg = FDI_TX_CTL(pipe); |
2484 | temp = I915_READ(reg); |
2482 | temp = I915_READ(reg); |
2485 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2483 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2486 | temp |= snb_b_fdi_train_param[i]; |
2484 | temp |= snb_b_fdi_train_param[i]; |
2487 | I915_WRITE(reg, temp); |
2485 | I915_WRITE(reg, temp); |
2488 | 2486 | ||
2489 | POSTING_READ(reg); |
2487 | POSTING_READ(reg); |
2490 | udelay(500); |
2488 | udelay(500); |
2491 | 2489 | ||
2492 | for (retry = 0; retry < 5; retry++) { |
2490 | for (retry = 0; retry < 5; retry++) { |
2493 | reg = FDI_RX_IIR(pipe); |
2491 | reg = FDI_RX_IIR(pipe); |
2494 | temp = I915_READ(reg); |
2492 | temp = I915_READ(reg); |
2495 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2493 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2496 | if (temp & FDI_RX_BIT_LOCK) { |
2494 | if (temp & FDI_RX_BIT_LOCK) { |
2497 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2495 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2498 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2496 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2499 | break; |
2497 | break; |
2500 | } |
2498 | } |
2501 | udelay(50); |
2499 | udelay(50); |
2502 | } |
2500 | } |
2503 | if (retry < 5) |
2501 | if (retry < 5) |
2504 | break; |
2502 | break; |
2505 | } |
2503 | } |
2506 | if (i == 4) |
2504 | if (i == 4) |
2507 | DRM_ERROR("FDI train 1 fail!\n"); |
2505 | DRM_ERROR("FDI train 1 fail!\n"); |
2508 | 2506 | ||
2509 | /* Train 2 */ |
2507 | /* Train 2 */ |
2510 | reg = FDI_TX_CTL(pipe); |
2508 | reg = FDI_TX_CTL(pipe); |
2511 | temp = I915_READ(reg); |
2509 | temp = I915_READ(reg); |
2512 | temp &= ~FDI_LINK_TRAIN_NONE; |
2510 | temp &= ~FDI_LINK_TRAIN_NONE; |
2513 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2511 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2514 | if (IS_GEN6(dev)) { |
2512 | if (IS_GEN6(dev)) { |
2515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2513 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2516 | /* SNB-B */ |
2514 | /* SNB-B */ |
2517 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2515 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2518 | } |
2516 | } |
2519 | I915_WRITE(reg, temp); |
2517 | I915_WRITE(reg, temp); |
2520 | 2518 | ||
2521 | reg = FDI_RX_CTL(pipe); |
2519 | reg = FDI_RX_CTL(pipe); |
2522 | temp = I915_READ(reg); |
2520 | temp = I915_READ(reg); |
2523 | if (HAS_PCH_CPT(dev)) { |
2521 | if (HAS_PCH_CPT(dev)) { |
2524 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2522 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2525 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2523 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2526 | } else { |
2524 | } else { |
2527 | temp &= ~FDI_LINK_TRAIN_NONE; |
2525 | temp &= ~FDI_LINK_TRAIN_NONE; |
2528 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2526 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2529 | } |
2527 | } |
2530 | I915_WRITE(reg, temp); |
2528 | I915_WRITE(reg, temp); |
2531 | 2529 | ||
2532 | POSTING_READ(reg); |
2530 | POSTING_READ(reg); |
2533 | udelay(150); |
2531 | udelay(150); |
2534 | 2532 | ||
2535 | for (i = 0; i < 4; i++) { |
2533 | for (i = 0; i < 4; i++) { |
2536 | reg = FDI_TX_CTL(pipe); |
2534 | reg = FDI_TX_CTL(pipe); |
2537 | temp = I915_READ(reg); |
2535 | temp = I915_READ(reg); |
2538 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2536 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2539 | temp |= snb_b_fdi_train_param[i]; |
2537 | temp |= snb_b_fdi_train_param[i]; |
2540 | I915_WRITE(reg, temp); |
2538 | I915_WRITE(reg, temp); |
2541 | 2539 | ||
2542 | POSTING_READ(reg); |
2540 | POSTING_READ(reg); |
2543 | udelay(500); |
2541 | udelay(500); |
2544 | 2542 | ||
2545 | for (retry = 0; retry < 5; retry++) { |
2543 | for (retry = 0; retry < 5; retry++) { |
2546 | reg = FDI_RX_IIR(pipe); |
2544 | reg = FDI_RX_IIR(pipe); |
2547 | temp = I915_READ(reg); |
2545 | temp = I915_READ(reg); |
2548 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2546 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2549 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2547 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2550 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2548 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2551 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2549 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2552 | break; |
2550 | break; |
2553 | } |
2551 | } |
2554 | udelay(50); |
2552 | udelay(50); |
2555 | } |
2553 | } |
2556 | if (retry < 5) |
2554 | if (retry < 5) |
2557 | break; |
2555 | break; |
2558 | } |
2556 | } |
2559 | if (i == 4) |
2557 | if (i == 4) |
2560 | DRM_ERROR("FDI train 2 fail!\n"); |
2558 | DRM_ERROR("FDI train 2 fail!\n"); |
2561 | 2559 | ||
2562 | DRM_DEBUG_KMS("FDI train done.\n"); |
2560 | DRM_DEBUG_KMS("FDI train done.\n"); |
2563 | } |
2561 | } |
2564 | 2562 | ||
2565 | /* Manual link training for Ivy Bridge A0 parts */ |
2563 | /* Manual link training for Ivy Bridge A0 parts */ |
2566 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2564 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2567 | { |
2565 | { |
2568 | struct drm_device *dev = crtc->dev; |
2566 | struct drm_device *dev = crtc->dev; |
2569 | struct drm_i915_private *dev_priv = dev->dev_private; |
2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
2570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2571 | int pipe = intel_crtc->pipe; |
2569 | int pipe = intel_crtc->pipe; |
2572 | u32 reg, temp, i; |
2570 | u32 reg, temp, i; |
2573 | 2571 | ||
2574 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2572 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2575 | for train result */ |
2573 | for train result */ |
2576 | reg = FDI_RX_IMR(pipe); |
2574 | reg = FDI_RX_IMR(pipe); |
2577 | temp = I915_READ(reg); |
2575 | temp = I915_READ(reg); |
2578 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2576 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2579 | temp &= ~FDI_RX_BIT_LOCK; |
2577 | temp &= ~FDI_RX_BIT_LOCK; |
2580 | I915_WRITE(reg, temp); |
2578 | I915_WRITE(reg, temp); |
2581 | 2579 | ||
2582 | POSTING_READ(reg); |
2580 | POSTING_READ(reg); |
2583 | udelay(150); |
2581 | udelay(150); |
2584 | 2582 | ||
2585 | /* enable CPU FDI TX and PCH FDI RX */ |
2583 | /* enable CPU FDI TX and PCH FDI RX */ |
2586 | reg = FDI_TX_CTL(pipe); |
2584 | reg = FDI_TX_CTL(pipe); |
2587 | temp = I915_READ(reg); |
2585 | temp = I915_READ(reg); |
2588 | temp &= ~(7 << 19); |
2586 | temp &= ~(7 << 19); |
2589 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2587 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2590 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2588 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2591 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2589 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2592 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2590 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2593 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2591 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2594 | temp |= FDI_COMPOSITE_SYNC; |
2592 | temp |= FDI_COMPOSITE_SYNC; |
2595 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2593 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2596 | 2594 | ||
2597 | reg = FDI_RX_CTL(pipe); |
2595 | reg = FDI_RX_CTL(pipe); |
2598 | temp = I915_READ(reg); |
2596 | temp = I915_READ(reg); |
2599 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2597 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2600 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2598 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2601 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2599 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2602 | temp |= FDI_COMPOSITE_SYNC; |
2600 | temp |= FDI_COMPOSITE_SYNC; |
2603 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2601 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2604 | 2602 | ||
2605 | POSTING_READ(reg); |
2603 | POSTING_READ(reg); |
2606 | udelay(150); |
2604 | udelay(150); |
2607 | 2605 | ||
2608 | if (HAS_PCH_CPT(dev)) |
2606 | if (HAS_PCH_CPT(dev)) |
2609 | cpt_phase_pointer_enable(dev, pipe); |
2607 | cpt_phase_pointer_enable(dev, pipe); |
2610 | 2608 | ||
2611 | for (i = 0; i < 4; i++) { |
2609 | for (i = 0; i < 4; i++) { |
2612 | reg = FDI_TX_CTL(pipe); |
2610 | reg = FDI_TX_CTL(pipe); |
2613 | temp = I915_READ(reg); |
2611 | temp = I915_READ(reg); |
2614 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2612 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2615 | temp |= snb_b_fdi_train_param[i]; |
2613 | temp |= snb_b_fdi_train_param[i]; |
2616 | I915_WRITE(reg, temp); |
2614 | I915_WRITE(reg, temp); |
2617 | 2615 | ||
2618 | POSTING_READ(reg); |
2616 | POSTING_READ(reg); |
2619 | udelay(500); |
2617 | udelay(500); |
2620 | 2618 | ||
2621 | reg = FDI_RX_IIR(pipe); |
2619 | reg = FDI_RX_IIR(pipe); |
2622 | temp = I915_READ(reg); |
2620 | temp = I915_READ(reg); |
2623 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2621 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2624 | 2622 | ||
2625 | if (temp & FDI_RX_BIT_LOCK || |
2623 | if (temp & FDI_RX_BIT_LOCK || |
2626 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2624 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2627 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2625 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2628 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2626 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2629 | break; |
2627 | break; |
2630 | } |
2628 | } |
2631 | } |
2629 | } |
2632 | if (i == 4) |
2630 | if (i == 4) |
2633 | DRM_ERROR("FDI train 1 fail!\n"); |
2631 | DRM_ERROR("FDI train 1 fail!\n"); |
2634 | 2632 | ||
2635 | /* Train 2 */ |
2633 | /* Train 2 */ |
2636 | reg = FDI_TX_CTL(pipe); |
2634 | reg = FDI_TX_CTL(pipe); |
2637 | temp = I915_READ(reg); |
2635 | temp = I915_READ(reg); |
2638 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2636 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2639 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2637 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2640 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2638 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2641 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2639 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2642 | I915_WRITE(reg, temp); |
2640 | I915_WRITE(reg, temp); |
2643 | 2641 | ||
2644 | reg = FDI_RX_CTL(pipe); |
2642 | reg = FDI_RX_CTL(pipe); |
2645 | temp = I915_READ(reg); |
2643 | temp = I915_READ(reg); |
2646 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2644 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2647 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2645 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2648 | I915_WRITE(reg, temp); |
2646 | I915_WRITE(reg, temp); |
2649 | 2647 | ||
2650 | POSTING_READ(reg); |
2648 | POSTING_READ(reg); |
2651 | udelay(150); |
2649 | udelay(150); |
2652 | 2650 | ||
2653 | for (i = 0; i < 4; i++) { |
2651 | for (i = 0; i < 4; i++) { |
2654 | reg = FDI_TX_CTL(pipe); |
2652 | reg = FDI_TX_CTL(pipe); |
2655 | temp = I915_READ(reg); |
2653 | temp = I915_READ(reg); |
2656 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2654 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2657 | temp |= snb_b_fdi_train_param[i]; |
2655 | temp |= snb_b_fdi_train_param[i]; |
2658 | I915_WRITE(reg, temp); |
2656 | I915_WRITE(reg, temp); |
2659 | 2657 | ||
2660 | POSTING_READ(reg); |
2658 | POSTING_READ(reg); |
2661 | udelay(500); |
2659 | udelay(500); |
2662 | 2660 | ||
2663 | reg = FDI_RX_IIR(pipe); |
2661 | reg = FDI_RX_IIR(pipe); |
2664 | temp = I915_READ(reg); |
2662 | temp = I915_READ(reg); |
2665 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2663 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2666 | 2664 | ||
2667 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2665 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2668 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2666 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2669 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2667 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2670 | break; |
2668 | break; |
2671 | } |
2669 | } |
2672 | } |
2670 | } |
2673 | if (i == 4) |
2671 | if (i == 4) |
2674 | DRM_ERROR("FDI train 2 fail!\n"); |
2672 | DRM_ERROR("FDI train 2 fail!\n"); |
2675 | 2673 | ||
2676 | DRM_DEBUG_KMS("FDI train done.\n"); |
2674 | DRM_DEBUG_KMS("FDI train done.\n"); |
2677 | } |
2675 | } |
2678 | 2676 | ||
2679 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2677 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2680 | { |
2678 | { |
2681 | struct drm_device *dev = intel_crtc->base.dev; |
2679 | struct drm_device *dev = intel_crtc->base.dev; |
2682 | struct drm_i915_private *dev_priv = dev->dev_private; |
2680 | struct drm_i915_private *dev_priv = dev->dev_private; |
2683 | int pipe = intel_crtc->pipe; |
2681 | int pipe = intel_crtc->pipe; |
2684 | u32 reg, temp; |
2682 | u32 reg, temp; |
2685 | 2683 | ||
2686 | /* Write the TU size bits so error detection works */ |
2684 | /* Write the TU size bits so error detection works */ |
2687 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2685 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2688 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
2686 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
2689 | 2687 | ||
2690 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2688 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2691 | reg = FDI_RX_CTL(pipe); |
2689 | reg = FDI_RX_CTL(pipe); |
2692 | temp = I915_READ(reg); |
2690 | temp = I915_READ(reg); |
2693 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
2691 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
2694 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2692 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
2695 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2693 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2696 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2694 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2697 | 2695 | ||
2698 | POSTING_READ(reg); |
2696 | POSTING_READ(reg); |
2699 | udelay(200); |
2697 | udelay(200); |
2700 | 2698 | ||
2701 | /* Switch from Rawclk to PCDclk */ |
2699 | /* Switch from Rawclk to PCDclk */ |
2702 | temp = I915_READ(reg); |
2700 | temp = I915_READ(reg); |
2703 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2701 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2704 | 2702 | ||
2705 | POSTING_READ(reg); |
2703 | POSTING_READ(reg); |
2706 | udelay(200); |
2704 | udelay(200); |
2707 | 2705 | ||
2708 | /* On Haswell, the PLL configuration for ports and pipes is handled |
2706 | /* On Haswell, the PLL configuration for ports and pipes is handled |
2709 | * separately, as part of DDI setup */ |
2707 | * separately, as part of DDI setup */ |
2710 | if (!IS_HASWELL(dev)) { |
2708 | if (!IS_HASWELL(dev)) { |
2711 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2709 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2712 | reg = FDI_TX_CTL(pipe); |
2710 | reg = FDI_TX_CTL(pipe); |
2713 | temp = I915_READ(reg); |
2711 | temp = I915_READ(reg); |
2714 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2712 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2715 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2713 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2716 | 2714 | ||
2717 | POSTING_READ(reg); |
2715 | POSTING_READ(reg); |
2718 | udelay(100); |
2716 | udelay(100); |
2719 | } |
2717 | } |
2720 | } |
2718 | } |
2721 | } |
2719 | } |
2722 | 2720 | ||
2723 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2721 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2724 | { |
2722 | { |
2725 | struct drm_device *dev = intel_crtc->base.dev; |
2723 | struct drm_device *dev = intel_crtc->base.dev; |
2726 | struct drm_i915_private *dev_priv = dev->dev_private; |
2724 | struct drm_i915_private *dev_priv = dev->dev_private; |
2727 | int pipe = intel_crtc->pipe; |
2725 | int pipe = intel_crtc->pipe; |
2728 | u32 reg, temp; |
2726 | u32 reg, temp; |
2729 | 2727 | ||
2730 | /* Switch from PCDclk to Rawclk */ |
2728 | /* Switch from PCDclk to Rawclk */ |
2731 | reg = FDI_RX_CTL(pipe); |
2729 | reg = FDI_RX_CTL(pipe); |
2732 | temp = I915_READ(reg); |
2730 | temp = I915_READ(reg); |
2733 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2731 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2734 | 2732 | ||
2735 | /* Disable CPU FDI TX PLL */ |
2733 | /* Disable CPU FDI TX PLL */ |
2736 | reg = FDI_TX_CTL(pipe); |
2734 | reg = FDI_TX_CTL(pipe); |
2737 | temp = I915_READ(reg); |
2735 | temp = I915_READ(reg); |
2738 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2736 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2739 | 2737 | ||
2740 | POSTING_READ(reg); |
2738 | POSTING_READ(reg); |
2741 | udelay(100); |
2739 | udelay(100); |
2742 | 2740 | ||
2743 | reg = FDI_RX_CTL(pipe); |
2741 | reg = FDI_RX_CTL(pipe); |
2744 | temp = I915_READ(reg); |
2742 | temp = I915_READ(reg); |
2745 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2743 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2746 | 2744 | ||
2747 | /* Wait for the clocks to turn off. */ |
2745 | /* Wait for the clocks to turn off. */ |
2748 | POSTING_READ(reg); |
2746 | POSTING_READ(reg); |
2749 | udelay(100); |
2747 | udelay(100); |
2750 | } |
2748 | } |
2751 | 2749 | ||
2752 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2750 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2753 | { |
2751 | { |
2754 | struct drm_i915_private *dev_priv = dev->dev_private; |
2752 | struct drm_i915_private *dev_priv = dev->dev_private; |
2755 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
2753 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
2756 | 2754 | ||
2757 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); |
2755 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); |
2758 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ |
2756 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ |
2759 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); |
2757 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); |
2760 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ |
2758 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ |
2761 | POSTING_READ(SOUTH_CHICKEN1); |
2759 | POSTING_READ(SOUTH_CHICKEN1); |
2762 | } |
2760 | } |
2763 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2761 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2764 | { |
2762 | { |
2765 | struct drm_device *dev = crtc->dev; |
2763 | struct drm_device *dev = crtc->dev; |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; |
2764 | struct drm_i915_private *dev_priv = dev->dev_private; |
2767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2768 | int pipe = intel_crtc->pipe; |
2766 | int pipe = intel_crtc->pipe; |
2769 | u32 reg, temp; |
2767 | u32 reg, temp; |
2770 | 2768 | ||
2771 | /* disable CPU FDI tx and PCH FDI rx */ |
2769 | /* disable CPU FDI tx and PCH FDI rx */ |
2772 | reg = FDI_TX_CTL(pipe); |
2770 | reg = FDI_TX_CTL(pipe); |
2773 | temp = I915_READ(reg); |
2771 | temp = I915_READ(reg); |
2774 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2772 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2775 | POSTING_READ(reg); |
2773 | POSTING_READ(reg); |
2776 | 2774 | ||
2777 | reg = FDI_RX_CTL(pipe); |
2775 | reg = FDI_RX_CTL(pipe); |
2778 | temp = I915_READ(reg); |
2776 | temp = I915_READ(reg); |
2779 | temp &= ~(0x7 << 16); |
2777 | temp &= ~(0x7 << 16); |
2780 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2778 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2781 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2779 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2782 | 2780 | ||
2783 | POSTING_READ(reg); |
2781 | POSTING_READ(reg); |
2784 | udelay(100); |
2782 | udelay(100); |
2785 | 2783 | ||
2786 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2784 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2787 | if (HAS_PCH_IBX(dev)) { |
2785 | if (HAS_PCH_IBX(dev)) { |
2788 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2786 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2789 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2787 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2790 | I915_READ(FDI_RX_CHICKEN(pipe) & |
2788 | I915_READ(FDI_RX_CHICKEN(pipe) & |
2791 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
2789 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
2792 | } else if (HAS_PCH_CPT(dev)) { |
2790 | } else if (HAS_PCH_CPT(dev)) { |
2793 | cpt_phase_pointer_disable(dev, pipe); |
2791 | cpt_phase_pointer_disable(dev, pipe); |
2794 | } |
2792 | } |
2795 | 2793 | ||
2796 | /* still set train pattern 1 */ |
2794 | /* still set train pattern 1 */ |
2797 | reg = FDI_TX_CTL(pipe); |
2795 | reg = FDI_TX_CTL(pipe); |
2798 | temp = I915_READ(reg); |
2796 | temp = I915_READ(reg); |
2799 | temp &= ~FDI_LINK_TRAIN_NONE; |
2797 | temp &= ~FDI_LINK_TRAIN_NONE; |
2800 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2798 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2801 | I915_WRITE(reg, temp); |
2799 | I915_WRITE(reg, temp); |
2802 | 2800 | ||
2803 | reg = FDI_RX_CTL(pipe); |
2801 | reg = FDI_RX_CTL(pipe); |
2804 | temp = I915_READ(reg); |
2802 | temp = I915_READ(reg); |
2805 | if (HAS_PCH_CPT(dev)) { |
2803 | if (HAS_PCH_CPT(dev)) { |
2806 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2804 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2807 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2805 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2808 | } else { |
2806 | } else { |
2809 | temp &= ~FDI_LINK_TRAIN_NONE; |
2807 | temp &= ~FDI_LINK_TRAIN_NONE; |
2810 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2808 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2811 | } |
2809 | } |
2812 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2810 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2813 | temp &= ~(0x07 << 16); |
2811 | temp &= ~(0x07 << 16); |
2814 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2812 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2815 | I915_WRITE(reg, temp); |
2813 | I915_WRITE(reg, temp); |
2816 | 2814 | ||
2817 | POSTING_READ(reg); |
2815 | POSTING_READ(reg); |
2818 | udelay(100); |
2816 | udelay(100); |
2819 | } |
2817 | } |
2820 | 2818 | ||
2821 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2819 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2822 | { |
2820 | { |
2823 | struct drm_device *dev = crtc->dev; |
2821 | struct drm_device *dev = crtc->dev; |
2824 | struct drm_i915_private *dev_priv = dev->dev_private; |
2822 | struct drm_i915_private *dev_priv = dev->dev_private; |
2825 | unsigned long flags; |
2823 | unsigned long flags; |
2826 | bool pending; |
2824 | bool pending; |
2827 | 2825 | ||
2828 | if (atomic_read(&dev_priv->mm.wedged)) |
2826 | if (atomic_read(&dev_priv->mm.wedged)) |
2829 | return false; |
2827 | return false; |
2830 | 2828 | ||
2831 | spin_lock_irqsave(&dev->event_lock, flags); |
2829 | spin_lock_irqsave(&dev->event_lock, flags); |
2832 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2830 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2833 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2831 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2834 | 2832 | ||
2835 | return pending; |
2833 | return pending; |
2836 | } |
2834 | } |
2837 | 2835 | ||
2838 | #if 0 |
2836 | #if 0 |
2839 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2837 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2840 | { |
2838 | { |
2841 | struct drm_device *dev = crtc->dev; |
2839 | struct drm_device *dev = crtc->dev; |
2842 | struct drm_i915_private *dev_priv = dev->dev_private; |
2840 | struct drm_i915_private *dev_priv = dev->dev_private; |
2843 | 2841 | ||
2844 | if (crtc->fb == NULL) |
2842 | if (crtc->fb == NULL) |
2845 | return; |
2843 | return; |
2846 | 2844 | ||
2847 | wait_event(dev_priv->pending_flip_queue, |
2845 | wait_event(dev_priv->pending_flip_queue, |
2848 | !intel_crtc_has_pending_flip(crtc)); |
2846 | !intel_crtc_has_pending_flip(crtc)); |
2849 | 2847 | ||
2850 | mutex_lock(&dev->struct_mutex); |
2848 | mutex_lock(&dev->struct_mutex); |
2851 | intel_finish_fb(crtc->fb); |
2849 | intel_finish_fb(crtc->fb); |
2852 | mutex_unlock(&dev->struct_mutex); |
2850 | mutex_unlock(&dev->struct_mutex); |
2853 | } |
2851 | } |
2854 | #endif |
2852 | #endif |
2855 | 2853 | ||
2856 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2854 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2857 | { |
2855 | { |
2858 | struct drm_device *dev = crtc->dev; |
2856 | struct drm_device *dev = crtc->dev; |
2859 | struct intel_encoder *intel_encoder; |
2857 | struct intel_encoder *intel_encoder; |
2860 | 2858 | ||
2861 | /* |
2859 | /* |
2862 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that |
2860 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that |
2863 | * must be driven by its own crtc; no sharing is possible. |
2861 | * must be driven by its own crtc; no sharing is possible. |
2864 | */ |
2862 | */ |
2865 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2863 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2866 | 2864 | ||
2867 | /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell |
2865 | /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell |
2868 | * CPU handles all others */ |
2866 | * CPU handles all others */ |
2869 | if (IS_HASWELL(dev)) { |
2867 | if (IS_HASWELL(dev)) { |
2870 | /* It is still unclear how this will work on PPT, so throw up a warning */ |
2868 | /* It is still unclear how this will work on PPT, so throw up a warning */ |
2871 | WARN_ON(!HAS_PCH_LPT(dev)); |
2869 | WARN_ON(!HAS_PCH_LPT(dev)); |
2872 | 2870 | ||
2873 | if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { |
2871 | if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { |
2874 | DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n"); |
2872 | DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n"); |
2875 | return true; |
2873 | return true; |
2876 | } else { |
2874 | } else { |
2877 | DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n", |
2875 | DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n", |
2878 | intel_encoder->type); |
2876 | intel_encoder->type); |
2879 | return false; |
2877 | return false; |
2880 | } |
2878 | } |
2881 | } |
2879 | } |
2882 | 2880 | ||
2883 | switch (intel_encoder->type) { |
2881 | switch (intel_encoder->type) { |
2884 | case INTEL_OUTPUT_EDP: |
2882 | case INTEL_OUTPUT_EDP: |
2885 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
2883 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
2886 | return false; |
2884 | return false; |
2887 | continue; |
2885 | continue; |
2888 | } |
2886 | } |
2889 | } |
2887 | } |
2890 | 2888 | ||
2891 | return true; |
2889 | return true; |
2892 | } |
2890 | } |
2893 | 2891 | ||
2894 | /* Program iCLKIP clock to the desired frequency */ |
2892 | /* Program iCLKIP clock to the desired frequency */ |
2895 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2893 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2896 | { |
2894 | { |
2897 | struct drm_device *dev = crtc->dev; |
2895 | struct drm_device *dev = crtc->dev; |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; |
2896 | struct drm_i915_private *dev_priv = dev->dev_private; |
2899 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2897 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2900 | u32 temp; |
2898 | u32 temp; |
2901 | 2899 | ||
2902 | /* It is necessary to ungate the pixclk gate prior to programming |
2900 | /* It is necessary to ungate the pixclk gate prior to programming |
2903 | * the divisors, and gate it back when it is done. |
2901 | * the divisors, and gate it back when it is done. |
2904 | */ |
2902 | */ |
2905 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2903 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2906 | 2904 | ||
2907 | /* Disable SSCCTL */ |
2905 | /* Disable SSCCTL */ |
2908 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2906 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2909 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | |
2907 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | |
2910 | SBI_SSCCTL_DISABLE); |
2908 | SBI_SSCCTL_DISABLE); |
2911 | 2909 | ||
2912 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2910 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2913 | if (crtc->mode.clock == 20000) { |
2911 | if (crtc->mode.clock == 20000) { |
2914 | auxdiv = 1; |
2912 | auxdiv = 1; |
2915 | divsel = 0x41; |
2913 | divsel = 0x41; |
2916 | phaseinc = 0x20; |
2914 | phaseinc = 0x20; |
2917 | } else { |
2915 | } else { |
2918 | /* The iCLK virtual clock root frequency is in MHz, |
2916 | /* The iCLK virtual clock root frequency is in MHz, |
2919 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2917 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2920 | * it is necessary to divide one by another, so we |
2918 | * it is necessary to divide one by another, so we |
2921 | * convert the virtual clock precision to KHz here for higher |
2919 | * convert the virtual clock precision to KHz here for higher |
2922 | * precision. |
2920 | * precision. |
2923 | */ |
2921 | */ |
2924 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2922 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2925 | u32 iclk_pi_range = 64; |
2923 | u32 iclk_pi_range = 64; |
2926 | u32 desired_divisor, msb_divisor_value, pi_value; |
2924 | u32 desired_divisor, msb_divisor_value, pi_value; |
2927 | 2925 | ||
2928 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2926 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2929 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2927 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2930 | pi_value = desired_divisor % iclk_pi_range; |
2928 | pi_value = desired_divisor % iclk_pi_range; |
2931 | 2929 | ||
2932 | auxdiv = 0; |
2930 | auxdiv = 0; |
2933 | divsel = msb_divisor_value - 2; |
2931 | divsel = msb_divisor_value - 2; |
2934 | phaseinc = pi_value; |
2932 | phaseinc = pi_value; |
2935 | } |
2933 | } |
2936 | 2934 | ||
2937 | /* This should not happen with any sane values */ |
2935 | /* This should not happen with any sane values */ |
2938 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2936 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2939 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2937 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2940 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2938 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2941 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2939 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2942 | 2940 | ||
2943 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2941 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2944 | crtc->mode.clock, |
2942 | crtc->mode.clock, |
2945 | auxdiv, |
2943 | auxdiv, |
2946 | divsel, |
2944 | divsel, |
2947 | phasedir, |
2945 | phasedir, |
2948 | phaseinc); |
2946 | phaseinc); |
2949 | 2947 | ||
2950 | /* Program SSCDIVINTPHASE6 */ |
2948 | /* Program SSCDIVINTPHASE6 */ |
2951 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); |
2949 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); |
2952 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2950 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2953 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2951 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2954 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2952 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2955 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2953 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2956 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2954 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2957 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2955 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2958 | 2956 | ||
2959 | intel_sbi_write(dev_priv, |
2957 | intel_sbi_write(dev_priv, |
2960 | SBI_SSCDIVINTPHASE6, |
2958 | SBI_SSCDIVINTPHASE6, |
2961 | temp); |
2959 | temp); |
2962 | 2960 | ||
2963 | /* Program SSCAUXDIV */ |
2961 | /* Program SSCAUXDIV */ |
2964 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); |
2962 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); |
2965 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2963 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2966 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2964 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2967 | intel_sbi_write(dev_priv, |
2965 | intel_sbi_write(dev_priv, |
2968 | SBI_SSCAUXDIV6, |
2966 | SBI_SSCAUXDIV6, |
2969 | temp); |
2967 | temp); |
2970 | 2968 | ||
2971 | 2969 | ||
2972 | /* Enable modulator and associated divider */ |
2970 | /* Enable modulator and associated divider */ |
2973 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); |
2971 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); |
2974 | temp &= ~SBI_SSCCTL_DISABLE; |
2972 | temp &= ~SBI_SSCCTL_DISABLE; |
2975 | intel_sbi_write(dev_priv, |
2973 | intel_sbi_write(dev_priv, |
2976 | SBI_SSCCTL6, |
2974 | SBI_SSCCTL6, |
2977 | temp); |
2975 | temp); |
2978 | 2976 | ||
2979 | /* Wait for initialization time */ |
2977 | /* Wait for initialization time */ |
2980 | udelay(24); |
2978 | udelay(24); |
2981 | 2979 | ||
2982 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2980 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2983 | } |
2981 | } |
2984 | 2982 | ||
2985 | /* |
2983 | /* |
2986 | * Enable PCH resources required for PCH ports: |
2984 | * Enable PCH resources required for PCH ports: |
2987 | * - PCH PLLs |
2985 | * - PCH PLLs |
2988 | * - FDI training & RX/TX |
2986 | * - FDI training & RX/TX |
2989 | * - update transcoder timings |
2987 | * - update transcoder timings |
2990 | * - DP transcoding bits |
2988 | * - DP transcoding bits |
2991 | * - transcoder |
2989 | * - transcoder |
2992 | */ |
2990 | */ |
2993 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
2991 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
2994 | { |
2992 | { |
2995 | struct drm_device *dev = crtc->dev; |
2993 | struct drm_device *dev = crtc->dev; |
2996 | struct drm_i915_private *dev_priv = dev->dev_private; |
2994 | struct drm_i915_private *dev_priv = dev->dev_private; |
2997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2998 | int pipe = intel_crtc->pipe; |
2996 | int pipe = intel_crtc->pipe; |
2999 | u32 reg, temp; |
2997 | u32 reg, temp; |
3000 | 2998 | ||
3001 | assert_transcoder_disabled(dev_priv, pipe); |
2999 | assert_transcoder_disabled(dev_priv, pipe); |
3002 | 3000 | ||
3003 | /* For PCH output, training FDI link */ |
3001 | /* For PCH output, training FDI link */ |
3004 | dev_priv->display.fdi_link_train(crtc); |
3002 | dev_priv->display.fdi_link_train(crtc); |
3005 | 3003 | ||
3006 | intel_enable_pch_pll(intel_crtc); |
3004 | intel_enable_pch_pll(intel_crtc); |
3007 | 3005 | ||
3008 | if (HAS_PCH_LPT(dev)) { |
3006 | if (HAS_PCH_LPT(dev)) { |
3009 | DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); |
3007 | DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); |
3010 | lpt_program_iclkip(crtc); |
3008 | lpt_program_iclkip(crtc); |
3011 | } else if (HAS_PCH_CPT(dev)) { |
3009 | } else if (HAS_PCH_CPT(dev)) { |
3012 | u32 sel; |
3010 | u32 sel; |
3013 | 3011 | ||
3014 | temp = I915_READ(PCH_DPLL_SEL); |
3012 | temp = I915_READ(PCH_DPLL_SEL); |
3015 | switch (pipe) { |
3013 | switch (pipe) { |
3016 | default: |
3014 | default: |
3017 | case 0: |
3015 | case 0: |
3018 | temp |= TRANSA_DPLL_ENABLE; |
3016 | temp |= TRANSA_DPLL_ENABLE; |
3019 | sel = TRANSA_DPLLB_SEL; |
3017 | sel = TRANSA_DPLLB_SEL; |
3020 | break; |
3018 | break; |
3021 | case 1: |
3019 | case 1: |
3022 | temp |= TRANSB_DPLL_ENABLE; |
3020 | temp |= TRANSB_DPLL_ENABLE; |
3023 | sel = TRANSB_DPLLB_SEL; |
3021 | sel = TRANSB_DPLLB_SEL; |
3024 | break; |
3022 | break; |
3025 | case 2: |
3023 | case 2: |
3026 | temp |= TRANSC_DPLL_ENABLE; |
3024 | temp |= TRANSC_DPLL_ENABLE; |
3027 | sel = TRANSC_DPLLB_SEL; |
3025 | sel = TRANSC_DPLLB_SEL; |
3028 | break; |
3026 | break; |
3029 | } |
3027 | } |
3030 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3028 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3031 | temp |= sel; |
3029 | temp |= sel; |
3032 | else |
3030 | else |
3033 | temp &= ~sel; |
3031 | temp &= ~sel; |
3034 | I915_WRITE(PCH_DPLL_SEL, temp); |
3032 | I915_WRITE(PCH_DPLL_SEL, temp); |
3035 | } |
3033 | } |
3036 | 3034 | ||
3037 | /* set transcoder timing, panel must allow it */ |
3035 | /* set transcoder timing, panel must allow it */ |
3038 | assert_panel_unlocked(dev_priv, pipe); |
3036 | assert_panel_unlocked(dev_priv, pipe); |
3039 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3037 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3040 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
3038 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
3041 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
3039 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
3042 | 3040 | ||
3043 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3041 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3044 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
3042 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
3045 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
3043 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
3046 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
3044 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
3047 | 3045 | ||
3048 | if (!IS_HASWELL(dev)) |
3046 | if (!IS_HASWELL(dev)) |
3049 | intel_fdi_normal_train(crtc); |
3047 | intel_fdi_normal_train(crtc); |
3050 | 3048 | ||
3051 | /* For PCH DP, enable TRANS_DP_CTL */ |
3049 | /* For PCH DP, enable TRANS_DP_CTL */ |
3052 | if (HAS_PCH_CPT(dev) && |
3050 | if (HAS_PCH_CPT(dev) && |
3053 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3051 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3054 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3052 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3055 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
3053 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
3056 | reg = TRANS_DP_CTL(pipe); |
3054 | reg = TRANS_DP_CTL(pipe); |
3057 | temp = I915_READ(reg); |
3055 | temp = I915_READ(reg); |
3058 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3056 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3059 | TRANS_DP_SYNC_MASK | |
3057 | TRANS_DP_SYNC_MASK | |
3060 | TRANS_DP_BPC_MASK); |
3058 | TRANS_DP_BPC_MASK); |
3061 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3059 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3062 | TRANS_DP_ENH_FRAMING); |
3060 | TRANS_DP_ENH_FRAMING); |
3063 | temp |= bpc << 9; /* same format but at 11:9 */ |
3061 | temp |= bpc << 9; /* same format but at 11:9 */ |
3064 | 3062 | ||
3065 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3063 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3066 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3064 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3067 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3065 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3068 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3066 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3069 | 3067 | ||
3070 | switch (intel_trans_dp_port_sel(crtc)) { |
3068 | switch (intel_trans_dp_port_sel(crtc)) { |
3071 | case PCH_DP_B: |
3069 | case PCH_DP_B: |
3072 | temp |= TRANS_DP_PORT_SEL_B; |
3070 | temp |= TRANS_DP_PORT_SEL_B; |
3073 | break; |
3071 | break; |
3074 | case PCH_DP_C: |
3072 | case PCH_DP_C: |
3075 | temp |= TRANS_DP_PORT_SEL_C; |
3073 | temp |= TRANS_DP_PORT_SEL_C; |
3076 | break; |
3074 | break; |
3077 | case PCH_DP_D: |
3075 | case PCH_DP_D: |
3078 | temp |= TRANS_DP_PORT_SEL_D; |
3076 | temp |= TRANS_DP_PORT_SEL_D; |
3079 | break; |
3077 | break; |
3080 | default: |
3078 | default: |
3081 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
3079 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
3082 | temp |= TRANS_DP_PORT_SEL_B; |
3080 | temp |= TRANS_DP_PORT_SEL_B; |
3083 | break; |
3081 | break; |
3084 | } |
3082 | } |
3085 | 3083 | ||
3086 | I915_WRITE(reg, temp); |
3084 | I915_WRITE(reg, temp); |
3087 | } |
3085 | } |
3088 | 3086 | ||
3089 | intel_enable_transcoder(dev_priv, pipe); |
3087 | intel_enable_transcoder(dev_priv, pipe); |
3090 | } |
3088 | } |
3091 | 3089 | ||
3092 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3090 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3093 | { |
3091 | { |
3094 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
3092 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
3095 | 3093 | ||
3096 | if (pll == NULL) |
3094 | if (pll == NULL) |
3097 | return; |
3095 | return; |
3098 | 3096 | ||
3099 | if (pll->refcount == 0) { |
3097 | if (pll->refcount == 0) { |
3100 | WARN(1, "bad PCH PLL refcount\n"); |
3098 | WARN(1, "bad PCH PLL refcount\n"); |
3101 | return; |
3099 | return; |
3102 | } |
3100 | } |
3103 | 3101 | ||
3104 | --pll->refcount; |
3102 | --pll->refcount; |
3105 | intel_crtc->pch_pll = NULL; |
3103 | intel_crtc->pch_pll = NULL; |
3106 | } |
3104 | } |
3107 | 3105 | ||
3108 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) |
3106 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) |
3109 | { |
3107 | { |
3110 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
3108 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
3111 | struct intel_pch_pll *pll; |
3109 | struct intel_pch_pll *pll; |
3112 | int i; |
3110 | int i; |
3113 | 3111 | ||
3114 | pll = intel_crtc->pch_pll; |
3112 | pll = intel_crtc->pch_pll; |
3115 | if (pll) { |
3113 | if (pll) { |
3116 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", |
3114 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", |
3117 | intel_crtc->base.base.id, pll->pll_reg); |
3115 | intel_crtc->base.base.id, pll->pll_reg); |
3118 | goto prepare; |
3116 | goto prepare; |
3119 | } |
3117 | } |
3120 | 3118 | ||
3121 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3119 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3122 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3120 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3123 | i = intel_crtc->pipe; |
3121 | i = intel_crtc->pipe; |
3124 | pll = &dev_priv->pch_plls[i]; |
3122 | pll = &dev_priv->pch_plls[i]; |
3125 | 3123 | ||
3126 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", |
3124 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", |
3127 | intel_crtc->base.base.id, pll->pll_reg); |
3125 | intel_crtc->base.base.id, pll->pll_reg); |
3128 | 3126 | ||
3129 | goto found; |
3127 | goto found; |
3130 | } |
3128 | } |
3131 | 3129 | ||
3132 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3130 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3133 | pll = &dev_priv->pch_plls[i]; |
3131 | pll = &dev_priv->pch_plls[i]; |
3134 | 3132 | ||
3135 | /* Only want to check enabled timings first */ |
3133 | /* Only want to check enabled timings first */ |
3136 | if (pll->refcount == 0) |
3134 | if (pll->refcount == 0) |
3137 | continue; |
3135 | continue; |
3138 | 3136 | ||
3139 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && |
3137 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && |
3140 | fp == I915_READ(pll->fp0_reg)) { |
3138 | fp == I915_READ(pll->fp0_reg)) { |
3141 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", |
3139 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", |
3142 | intel_crtc->base.base.id, |
3140 | intel_crtc->base.base.id, |
3143 | pll->pll_reg, pll->refcount, pll->active); |
3141 | pll->pll_reg, pll->refcount, pll->active); |
3144 | 3142 | ||
3145 | goto found; |
3143 | goto found; |
3146 | } |
3144 | } |
3147 | } |
3145 | } |
3148 | 3146 | ||
3149 | /* Ok no matching timings, maybe there's a free one? */ |
3147 | /* Ok no matching timings, maybe there's a free one? */ |
3150 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3148 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3151 | pll = &dev_priv->pch_plls[i]; |
3149 | pll = &dev_priv->pch_plls[i]; |
3152 | if (pll->refcount == 0) { |
3150 | if (pll->refcount == 0) { |
3153 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", |
3151 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", |
3154 | intel_crtc->base.base.id, pll->pll_reg); |
3152 | intel_crtc->base.base.id, pll->pll_reg); |
3155 | goto found; |
3153 | goto found; |
3156 | } |
3154 | } |
3157 | } |
3155 | } |
3158 | 3156 | ||
3159 | return NULL; |
3157 | return NULL; |
3160 | 3158 | ||
3161 | found: |
3159 | found: |
3162 | intel_crtc->pch_pll = pll; |
3160 | intel_crtc->pch_pll = pll; |
3163 | pll->refcount++; |
3161 | pll->refcount++; |
3164 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); |
3162 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); |
3165 | prepare: /* separate function? */ |
3163 | prepare: /* separate function? */ |
3166 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); |
3164 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); |
3167 | 3165 | ||
3168 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3166 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3169 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
3167 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
3170 | POSTING_READ(pll->pll_reg); |
3168 | POSTING_READ(pll->pll_reg); |
3171 | udelay(150); |
3169 | udelay(150); |
3172 | 3170 | ||
3173 | I915_WRITE(pll->fp0_reg, fp); |
3171 | I915_WRITE(pll->fp0_reg, fp); |
3174 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
3172 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
3175 | pll->on = false; |
3173 | pll->on = false; |
3176 | return pll; |
3174 | return pll; |
3177 | } |
3175 | } |
3178 | 3176 | ||
3179 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3177 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3180 | { |
3178 | { |
3181 | struct drm_i915_private *dev_priv = dev->dev_private; |
3179 | struct drm_i915_private *dev_priv = dev->dev_private; |
3182 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); |
3180 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); |
3183 | u32 temp; |
3181 | u32 temp; |
3184 | 3182 | ||
3185 | temp = I915_READ(dslreg); |
3183 | temp = I915_READ(dslreg); |
3186 | udelay(500); |
3184 | udelay(500); |
3187 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3185 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3188 | /* Without this, mode sets may fail silently on FDI */ |
3186 | /* Without this, mode sets may fail silently on FDI */ |
3189 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); |
3187 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); |
3190 | udelay(250); |
3188 | udelay(250); |
3191 | I915_WRITE(tc2reg, 0); |
3189 | I915_WRITE(tc2reg, 0); |
3192 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3190 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3193 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); |
3191 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); |
3194 | } |
3192 | } |
3195 | } |
3193 | } |
3196 | 3194 | ||
3197 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3195 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3198 | { |
3196 | { |
3199 | struct drm_device *dev = crtc->dev; |
3197 | struct drm_device *dev = crtc->dev; |
3200 | struct drm_i915_private *dev_priv = dev->dev_private; |
3198 | struct drm_i915_private *dev_priv = dev->dev_private; |
3201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3202 | struct intel_encoder *encoder; |
3200 | struct intel_encoder *encoder; |
3203 | int pipe = intel_crtc->pipe; |
3201 | int pipe = intel_crtc->pipe; |
3204 | int plane = intel_crtc->plane; |
3202 | int plane = intel_crtc->plane; |
3205 | u32 temp; |
3203 | u32 temp; |
3206 | bool is_pch_port; |
3204 | bool is_pch_port; |
3207 | 3205 | ||
3208 | WARN_ON(!crtc->enabled); |
3206 | WARN_ON(!crtc->enabled); |
3209 | 3207 | ||
3210 | if (intel_crtc->active) |
3208 | if (intel_crtc->active) |
3211 | return; |
3209 | return; |
3212 | 3210 | ||
3213 | intel_crtc->active = true; |
3211 | intel_crtc->active = true; |
3214 | intel_update_watermarks(dev); |
3212 | intel_update_watermarks(dev); |
3215 | 3213 | ||
3216 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
3214 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
3217 | temp = I915_READ(PCH_LVDS); |
3215 | temp = I915_READ(PCH_LVDS); |
3218 | if ((temp & LVDS_PORT_EN) == 0) |
3216 | if ((temp & LVDS_PORT_EN) == 0) |
3219 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
3217 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
3220 | } |
3218 | } |
3221 | 3219 | ||
3222 | is_pch_port = intel_crtc_driving_pch(crtc); |
3220 | is_pch_port = intel_crtc_driving_pch(crtc); |
3223 | 3221 | ||
3224 | if (is_pch_port) { |
3222 | if (is_pch_port) { |
3225 | ironlake_fdi_pll_enable(intel_crtc); |
3223 | ironlake_fdi_pll_enable(intel_crtc); |
3226 | } else { |
3224 | } else { |
3227 | assert_fdi_tx_disabled(dev_priv, pipe); |
3225 | assert_fdi_tx_disabled(dev_priv, pipe); |
3228 | assert_fdi_rx_disabled(dev_priv, pipe); |
3226 | assert_fdi_rx_disabled(dev_priv, pipe); |
3229 | } |
3227 | } |
3230 | 3228 | ||
3231 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3229 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3232 | if (encoder->pre_enable) |
3230 | if (encoder->pre_enable) |
3233 | encoder->pre_enable(encoder); |
3231 | encoder->pre_enable(encoder); |
3234 | 3232 | ||
3235 | /* Enable panel fitting for LVDS */ |
3233 | /* Enable panel fitting for LVDS */ |
3236 | if (dev_priv->pch_pf_size && |
3234 | if (dev_priv->pch_pf_size && |
3237 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
3235 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
3238 | /* Force use of hard-coded filter coefficients |
3236 | /* Force use of hard-coded filter coefficients |
3239 | * as some pre-programmed values are broken, |
3237 | * as some pre-programmed values are broken, |
3240 | * e.g. x201. |
3238 | * e.g. x201. |
3241 | */ |
3239 | */ |
3242 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3240 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3243 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3241 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3244 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); |
3242 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); |
3245 | } |
3243 | } |
3246 | 3244 | ||
3247 | /* |
3245 | /* |
3248 | * On ILK+ LUT must be loaded before the pipe is running but with |
3246 | * On ILK+ LUT must be loaded before the pipe is running but with |
3249 | * clocks enabled |
3247 | * clocks enabled |
3250 | */ |
3248 | */ |
3251 | intel_crtc_load_lut(crtc); |
3249 | intel_crtc_load_lut(crtc); |
3252 | 3250 | ||
3253 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3251 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3254 | intel_enable_plane(dev_priv, plane, pipe); |
3252 | intel_enable_plane(dev_priv, plane, pipe); |
3255 | 3253 | ||
3256 | if (is_pch_port) |
3254 | if (is_pch_port) |
3257 | ironlake_pch_enable(crtc); |
3255 | ironlake_pch_enable(crtc); |
3258 | 3256 | ||
3259 | mutex_lock(&dev->struct_mutex); |
3257 | mutex_lock(&dev->struct_mutex); |
3260 | intel_update_fbc(dev); |
3258 | intel_update_fbc(dev); |
3261 | mutex_unlock(&dev->struct_mutex); |
3259 | mutex_unlock(&dev->struct_mutex); |
3262 | 3260 | ||
3263 | // intel_crtc_update_cursor(crtc, true); |
3261 | // intel_crtc_update_cursor(crtc, true); |
3264 | 3262 | ||
3265 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3263 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3266 | encoder->enable(encoder); |
3264 | encoder->enable(encoder); |
3267 | 3265 | ||
3268 | if (HAS_PCH_CPT(dev)) |
3266 | if (HAS_PCH_CPT(dev)) |
3269 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
3267 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
3270 | 3268 | ||
3271 | /* |
3269 | /* |
3272 | * There seems to be a race in PCH platform hw (at least on some |
3270 | * There seems to be a race in PCH platform hw (at least on some |
3273 | * outputs) where an enabled pipe still completes any pageflip right |
3271 | * outputs) where an enabled pipe still completes any pageflip right |
3274 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3272 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3275 | * as the first vblank happend, everything works as expected. Hence just |
3273 | * as the first vblank happend, everything works as expected. Hence just |
3276 | * wait for one vblank before returning to avoid strange things |
3274 | * wait for one vblank before returning to avoid strange things |
3277 | * happening. |
3275 | * happening. |
3278 | */ |
3276 | */ |
3279 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3277 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3280 | } |
3278 | } |
3281 | 3279 | ||
3282 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3280 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3283 | { |
3281 | { |
3284 | struct drm_device *dev = crtc->dev; |
3282 | struct drm_device *dev = crtc->dev; |
3285 | struct drm_i915_private *dev_priv = dev->dev_private; |
3283 | struct drm_i915_private *dev_priv = dev->dev_private; |
3286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3287 | struct intel_encoder *encoder; |
3285 | struct intel_encoder *encoder; |
3288 | int pipe = intel_crtc->pipe; |
3286 | int pipe = intel_crtc->pipe; |
3289 | int plane = intel_crtc->plane; |
3287 | int plane = intel_crtc->plane; |
3290 | u32 reg, temp; |
3288 | u32 reg, temp; |
3291 | 3289 | ||
3292 | 3290 | ||
3293 | if (!intel_crtc->active) |
3291 | if (!intel_crtc->active) |
3294 | return; |
3292 | return; |
3295 | 3293 | ||
3296 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3294 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3297 | encoder->disable(encoder); |
3295 | encoder->disable(encoder); |
3298 | 3296 | ||
3299 | // intel_crtc_wait_for_pending_flips(crtc); |
3297 | // intel_crtc_wait_for_pending_flips(crtc); |
3300 | // drm_vblank_off(dev, pipe); |
3298 | // drm_vblank_off(dev, pipe); |
3301 | // intel_crtc_update_cursor(crtc, false); |
3299 | // intel_crtc_update_cursor(crtc, false); |
3302 | 3300 | ||
3303 | intel_disable_plane(dev_priv, plane, pipe); |
3301 | intel_disable_plane(dev_priv, plane, pipe); |
3304 | 3302 | ||
3305 | if (dev_priv->cfb_plane == plane) |
3303 | if (dev_priv->cfb_plane == plane) |
3306 | intel_disable_fbc(dev); |
3304 | intel_disable_fbc(dev); |
3307 | 3305 | ||
3308 | intel_disable_pipe(dev_priv, pipe); |
3306 | intel_disable_pipe(dev_priv, pipe); |
3309 | 3307 | ||
3310 | /* Disable PF */ |
3308 | /* Disable PF */ |
3311 | I915_WRITE(PF_CTL(pipe), 0); |
3309 | I915_WRITE(PF_CTL(pipe), 0); |
3312 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3310 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3313 | 3311 | ||
3314 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3312 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3315 | if (encoder->post_disable) |
3313 | if (encoder->post_disable) |
3316 | encoder->post_disable(encoder); |
3314 | encoder->post_disable(encoder); |
3317 | 3315 | ||
3318 | ironlake_fdi_disable(crtc); |
3316 | ironlake_fdi_disable(crtc); |
3319 | 3317 | ||
3320 | intel_disable_transcoder(dev_priv, pipe); |
3318 | intel_disable_transcoder(dev_priv, pipe); |
3321 | 3319 | ||
3322 | if (HAS_PCH_CPT(dev)) { |
3320 | if (HAS_PCH_CPT(dev)) { |
3323 | /* disable TRANS_DP_CTL */ |
3321 | /* disable TRANS_DP_CTL */ |
3324 | reg = TRANS_DP_CTL(pipe); |
3322 | reg = TRANS_DP_CTL(pipe); |
3325 | temp = I915_READ(reg); |
3323 | temp = I915_READ(reg); |
3326 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
3324 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
3327 | temp |= TRANS_DP_PORT_SEL_NONE; |
3325 | temp |= TRANS_DP_PORT_SEL_NONE; |
3328 | I915_WRITE(reg, temp); |
3326 | I915_WRITE(reg, temp); |
3329 | 3327 | ||
3330 | /* disable DPLL_SEL */ |
3328 | /* disable DPLL_SEL */ |
3331 | temp = I915_READ(PCH_DPLL_SEL); |
3329 | temp = I915_READ(PCH_DPLL_SEL); |
3332 | switch (pipe) { |
3330 | switch (pipe) { |
3333 | case 0: |
3331 | case 0: |
3334 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
3332 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
3335 | break; |
3333 | break; |
3336 | case 1: |
3334 | case 1: |
3337 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
3335 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
3338 | break; |
3336 | break; |
3339 | case 2: |
3337 | case 2: |
3340 | /* C shares PLL A or B */ |
3338 | /* C shares PLL A or B */ |
3341 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
3339 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
3342 | break; |
3340 | break; |
3343 | default: |
3341 | default: |
3344 | BUG(); /* wtf */ |
3342 | BUG(); /* wtf */ |
3345 | } |
3343 | } |
3346 | I915_WRITE(PCH_DPLL_SEL, temp); |
3344 | I915_WRITE(PCH_DPLL_SEL, temp); |
3347 | } |
3345 | } |
3348 | 3346 | ||
3349 | /* disable PCH DPLL */ |
3347 | /* disable PCH DPLL */ |
3350 | intel_disable_pch_pll(intel_crtc); |
3348 | intel_disable_pch_pll(intel_crtc); |
3351 | 3349 | ||
3352 | ironlake_fdi_pll_disable(intel_crtc); |
3350 | ironlake_fdi_pll_disable(intel_crtc); |
3353 | 3351 | ||
3354 | intel_crtc->active = false; |
3352 | intel_crtc->active = false; |
3355 | intel_update_watermarks(dev); |
3353 | intel_update_watermarks(dev); |
3356 | 3354 | ||
3357 | mutex_lock(&dev->struct_mutex); |
3355 | mutex_lock(&dev->struct_mutex); |
3358 | intel_update_fbc(dev); |
3356 | intel_update_fbc(dev); |
3359 | mutex_unlock(&dev->struct_mutex); |
3357 | mutex_unlock(&dev->struct_mutex); |
3360 | - | ||
3361 | } |
3358 | } |
3362 | 3359 | ||
3363 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3360 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3364 | { |
3361 | { |
3365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3366 | intel_put_pch_pll(intel_crtc); |
3363 | intel_put_pch_pll(intel_crtc); |
3367 | } |
3364 | } |
3368 | 3365 | ||
3369 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3366 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3370 | { |
3367 | { |
3371 | if (!enable && intel_crtc->overlay) { |
3368 | if (!enable && intel_crtc->overlay) { |
3372 | struct drm_device *dev = intel_crtc->base.dev; |
3369 | struct drm_device *dev = intel_crtc->base.dev; |
3373 | struct drm_i915_private *dev_priv = dev->dev_private; |
3370 | struct drm_i915_private *dev_priv = dev->dev_private; |
3374 | 3371 | ||
3375 | mutex_lock(&dev->struct_mutex); |
3372 | mutex_lock(&dev->struct_mutex); |
3376 | dev_priv->mm.interruptible = false; |
3373 | dev_priv->mm.interruptible = false; |
3377 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3374 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3378 | dev_priv->mm.interruptible = true; |
3375 | dev_priv->mm.interruptible = true; |
3379 | mutex_unlock(&dev->struct_mutex); |
3376 | mutex_unlock(&dev->struct_mutex); |
3380 | } |
3377 | } |
3381 | 3378 | ||
3382 | /* Let userspace switch the overlay on again. In most cases userspace |
3379 | /* Let userspace switch the overlay on again. In most cases userspace |
3383 | * has to recompute where to put it anyway. |
3380 | * has to recompute where to put it anyway. |
3384 | */ |
3381 | */ |
3385 | } |
3382 | } |
3386 | 3383 | ||
3387 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3384 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3388 | { |
3385 | { |
3389 | struct drm_device *dev = crtc->dev; |
3386 | struct drm_device *dev = crtc->dev; |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
3387 | struct drm_i915_private *dev_priv = dev->dev_private; |
3391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3388 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3392 | struct intel_encoder *encoder; |
3389 | struct intel_encoder *encoder; |
3393 | int pipe = intel_crtc->pipe; |
3390 | int pipe = intel_crtc->pipe; |
3394 | int plane = intel_crtc->plane; |
3391 | int plane = intel_crtc->plane; |
3395 | 3392 | ||
3396 | WARN_ON(!crtc->enabled); |
3393 | WARN_ON(!crtc->enabled); |
3397 | 3394 | ||
3398 | if (intel_crtc->active) |
3395 | if (intel_crtc->active) |
3399 | return; |
3396 | return; |
3400 | 3397 | ||
3401 | intel_crtc->active = true; |
3398 | intel_crtc->active = true; |
3402 | intel_update_watermarks(dev); |
3399 | intel_update_watermarks(dev); |
3403 | 3400 | ||
3404 | intel_enable_pll(dev_priv, pipe); |
3401 | intel_enable_pll(dev_priv, pipe); |
3405 | intel_enable_pipe(dev_priv, pipe, false); |
3402 | intel_enable_pipe(dev_priv, pipe, false); |
3406 | intel_enable_plane(dev_priv, plane, pipe); |
3403 | intel_enable_plane(dev_priv, plane, pipe); |
3407 | 3404 | ||
3408 | intel_crtc_load_lut(crtc); |
3405 | intel_crtc_load_lut(crtc); |
3409 | intel_update_fbc(dev); |
3406 | intel_update_fbc(dev); |
3410 | 3407 | ||
3411 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3408 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3412 | intel_crtc_dpms_overlay(intel_crtc, true); |
3409 | intel_crtc_dpms_overlay(intel_crtc, true); |
3413 | // intel_crtc_update_cursor(crtc, true); |
3410 | // intel_crtc_update_cursor(crtc, true); |
3414 | 3411 | ||
3415 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3412 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3416 | encoder->enable(encoder); |
3413 | encoder->enable(encoder); |
3417 | } |
3414 | } |
3418 | 3415 | ||
3419 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3416 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3420 | { |
3417 | { |
3421 | struct drm_device *dev = crtc->dev; |
3418 | struct drm_device *dev = crtc->dev; |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; |
3419 | struct drm_i915_private *dev_priv = dev->dev_private; |
3423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3424 | struct intel_encoder *encoder; |
3421 | struct intel_encoder *encoder; |
3425 | int pipe = intel_crtc->pipe; |
3422 | int pipe = intel_crtc->pipe; |
3426 | int plane = intel_crtc->plane; |
3423 | int plane = intel_crtc->plane; |
3427 | 3424 | ||
3428 | 3425 | ||
3429 | if (!intel_crtc->active) |
3426 | if (!intel_crtc->active) |
3430 | return; |
3427 | return; |
3431 | 3428 | ||
3432 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3429 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3433 | encoder->disable(encoder); |
3430 | encoder->disable(encoder); |
3434 | 3431 | ||
3435 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3432 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3436 | // intel_crtc_wait_for_pending_flips(crtc); |
3433 | // intel_crtc_wait_for_pending_flips(crtc); |
3437 | // drm_vblank_off(dev, pipe); |
3434 | // drm_vblank_off(dev, pipe); |
3438 | intel_crtc_dpms_overlay(intel_crtc, false); |
3435 | intel_crtc_dpms_overlay(intel_crtc, false); |
3439 | // intel_crtc_update_cursor(crtc, false); |
3436 | // intel_crtc_update_cursor(crtc, false); |
3440 | 3437 | ||
3441 | if (dev_priv->cfb_plane == plane) |
3438 | if (dev_priv->cfb_plane == plane) |
3442 | intel_disable_fbc(dev); |
3439 | intel_disable_fbc(dev); |
3443 | 3440 | ||
3444 | intel_disable_plane(dev_priv, plane, pipe); |
3441 | intel_disable_plane(dev_priv, plane, pipe); |
3445 | intel_disable_pipe(dev_priv, pipe); |
3442 | intel_disable_pipe(dev_priv, pipe); |
3446 | intel_disable_pll(dev_priv, pipe); |
3443 | intel_disable_pll(dev_priv, pipe); |
3447 | 3444 | ||
3448 | intel_crtc->active = false; |
3445 | intel_crtc->active = false; |
3449 | intel_update_fbc(dev); |
3446 | intel_update_fbc(dev); |
3450 | intel_update_watermarks(dev); |
3447 | intel_update_watermarks(dev); |
3451 | } |
3448 | } |
3452 | 3449 | ||
3453 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3450 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3454 | { |
3451 | { |
3455 | } |
3452 | } |
3456 | 3453 | ||
3457 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3454 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3458 | bool enabled) |
3455 | bool enabled) |
3459 | { |
3456 | { |
3460 | struct drm_device *dev = crtc->dev; |
3457 | struct drm_device *dev = crtc->dev; |
3461 | struct drm_i915_master_private *master_priv; |
3458 | struct drm_i915_master_private *master_priv; |
3462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3463 | int pipe = intel_crtc->pipe; |
3460 | int pipe = intel_crtc->pipe; |
3464 | 3461 | ||
3465 | 3462 | ||
3466 | #if 0 |
3463 | #if 0 |
3467 | if (!dev->primary->master) |
3464 | if (!dev->primary->master) |
3468 | return; |
3465 | return; |
3469 | 3466 | ||
3470 | master_priv = dev->primary->master->driver_priv; |
3467 | master_priv = dev->primary->master->driver_priv; |
3471 | if (!master_priv->sarea_priv) |
3468 | if (!master_priv->sarea_priv) |
3472 | return; |
3469 | return; |
3473 | 3470 | ||
3474 | switch (pipe) { |
3471 | switch (pipe) { |
3475 | case 0: |
3472 | case 0: |
3476 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3473 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3477 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3474 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3478 | break; |
3475 | break; |
3479 | case 1: |
3476 | case 1: |
3480 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3477 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3481 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3478 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3482 | break; |
3479 | break; |
3483 | default: |
3480 | default: |
3484 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3481 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3485 | break; |
3482 | break; |
3486 | } |
3483 | } |
3487 | #endif |
3484 | #endif |
3488 | 3485 | ||
3489 | } |
3486 | } |
3490 | 3487 | ||
3491 | /** |
3488 | /** |
3492 | * Sets the power management mode of the pipe and plane. |
3489 | * Sets the power management mode of the pipe and plane. |
3493 | */ |
3490 | */ |
3494 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3491 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3495 | { |
3492 | { |
3496 | struct drm_device *dev = crtc->dev; |
3493 | struct drm_device *dev = crtc->dev; |
3497 | struct drm_i915_private *dev_priv = dev->dev_private; |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; |
3498 | struct intel_encoder *intel_encoder; |
3495 | struct intel_encoder *intel_encoder; |
3499 | bool enable = false; |
3496 | bool enable = false; |
3500 | 3497 | ||
3501 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3498 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3502 | enable |= intel_encoder->connectors_active; |
3499 | enable |= intel_encoder->connectors_active; |
3503 | 3500 | ||
3504 | if (enable) |
3501 | if (enable) |
3505 | dev_priv->display.crtc_enable(crtc); |
3502 | dev_priv->display.crtc_enable(crtc); |
3506 | else |
3503 | else |
3507 | dev_priv->display.crtc_disable(crtc); |
3504 | dev_priv->display.crtc_disable(crtc); |
3508 | 3505 | ||
3509 | intel_crtc_update_sarea(crtc, enable); |
3506 | intel_crtc_update_sarea(crtc, enable); |
3510 | } |
3507 | } |
3511 | 3508 | ||
3512 | static void intel_crtc_noop(struct drm_crtc *crtc) |
3509 | static void intel_crtc_noop(struct drm_crtc *crtc) |
3513 | { |
3510 | { |
3514 | } |
3511 | } |
3515 | 3512 | ||
3516 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3513 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3517 | { |
3514 | { |
3518 | struct drm_device *dev = crtc->dev; |
3515 | struct drm_device *dev = crtc->dev; |
3519 | struct drm_connector *connector; |
3516 | struct drm_connector *connector; |
3520 | struct drm_i915_private *dev_priv = dev->dev_private; |
3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
3521 | 3518 | ||
3522 | /* crtc should still be enabled when we disable it. */ |
3519 | /* crtc should still be enabled when we disable it. */ |
3523 | WARN_ON(!crtc->enabled); |
3520 | WARN_ON(!crtc->enabled); |
3524 | 3521 | ||
3525 | dev_priv->display.crtc_disable(crtc); |
3522 | dev_priv->display.crtc_disable(crtc); |
3526 | intel_crtc_update_sarea(crtc, false); |
3523 | intel_crtc_update_sarea(crtc, false); |
3527 | dev_priv->display.off(crtc); |
3524 | dev_priv->display.off(crtc); |
3528 | 3525 | ||
3529 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3526 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3530 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3527 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3531 | 3528 | ||
3532 | // if (crtc->fb) { |
3529 | // if (crtc->fb) { |
3533 | // mutex_lock(&dev->struct_mutex); |
3530 | // mutex_lock(&dev->struct_mutex); |
3534 | // intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3531 | // intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3535 | // mutex_unlock(&dev->struct_mutex); |
3532 | // mutex_unlock(&dev->struct_mutex); |
3536 | // crtc->fb = NULL; |
3533 | // crtc->fb = NULL; |
3537 | // } |
3534 | // } |
3538 | 3535 | ||
3539 | /* Update computed state. */ |
3536 | /* Update computed state. */ |
3540 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3537 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3541 | if (!connector->encoder || !connector->encoder->crtc) |
3538 | if (!connector->encoder || !connector->encoder->crtc) |
3542 | continue; |
3539 | continue; |
3543 | 3540 | ||
3544 | if (connector->encoder->crtc != crtc) |
3541 | if (connector->encoder->crtc != crtc) |
3545 | continue; |
3542 | continue; |
3546 | 3543 | ||
3547 | connector->dpms = DRM_MODE_DPMS_OFF; |
3544 | connector->dpms = DRM_MODE_DPMS_OFF; |
3548 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3545 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3549 | } |
3546 | } |
3550 | } |
3547 | } |
3551 | 3548 | ||
3552 | void intel_modeset_disable(struct drm_device *dev) |
3549 | void intel_modeset_disable(struct drm_device *dev) |
3553 | { |
3550 | { |
3554 | struct drm_crtc *crtc; |
3551 | struct drm_crtc *crtc; |
3555 | 3552 | ||
3556 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
3553 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
3557 | if (crtc->enabled) |
3554 | if (crtc->enabled) |
3558 | intel_crtc_disable(crtc); |
3555 | intel_crtc_disable(crtc); |
3559 | } |
3556 | } |
3560 | } |
3557 | } |
3561 | 3558 | ||
3562 | void intel_encoder_noop(struct drm_encoder *encoder) |
3559 | void intel_encoder_noop(struct drm_encoder *encoder) |
3563 | { |
3560 | { |
3564 | } |
3561 | } |
3565 | 3562 | ||
3566 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3563 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3567 | { |
3564 | { |
3568 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3565 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3569 | 3566 | ||
3570 | drm_encoder_cleanup(encoder); |
3567 | drm_encoder_cleanup(encoder); |
3571 | kfree(intel_encoder); |
3568 | kfree(intel_encoder); |
3572 | } |
3569 | } |
3573 | 3570 | ||
3574 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3571 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3575 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3572 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3576 | * state of the entire output pipe. */ |
3573 | * state of the entire output pipe. */ |
3577 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3574 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3578 | { |
3575 | { |
3579 | if (mode == DRM_MODE_DPMS_ON) { |
3576 | if (mode == DRM_MODE_DPMS_ON) { |
3580 | encoder->connectors_active = true; |
3577 | encoder->connectors_active = true; |
3581 | 3578 | ||
3582 | intel_crtc_update_dpms(encoder->base.crtc); |
3579 | intel_crtc_update_dpms(encoder->base.crtc); |
3583 | } else { |
3580 | } else { |
3584 | encoder->connectors_active = false; |
3581 | encoder->connectors_active = false; |
3585 | 3582 | ||
3586 | intel_crtc_update_dpms(encoder->base.crtc); |
3583 | intel_crtc_update_dpms(encoder->base.crtc); |
3587 | } |
3584 | } |
3588 | } |
3585 | } |
3589 | 3586 | ||
3590 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3587 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3591 | * internal consistency). */ |
3588 | * internal consistency). */ |
3592 | static void intel_connector_check_state(struct intel_connector *connector) |
3589 | static void intel_connector_check_state(struct intel_connector *connector) |
3593 | { |
3590 | { |
3594 | if (connector->get_hw_state(connector)) { |
3591 | if (connector->get_hw_state(connector)) { |
3595 | struct intel_encoder *encoder = connector->encoder; |
3592 | struct intel_encoder *encoder = connector->encoder; |
3596 | struct drm_crtc *crtc; |
3593 | struct drm_crtc *crtc; |
3597 | bool encoder_enabled; |
3594 | bool encoder_enabled; |
3598 | enum pipe pipe; |
3595 | enum pipe pipe; |
3599 | 3596 | ||
3600 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3597 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3601 | connector->base.base.id, |
3598 | connector->base.base.id, |
3602 | drm_get_connector_name(&connector->base)); |
3599 | drm_get_connector_name(&connector->base)); |
3603 | 3600 | ||
3604 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3601 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3605 | "wrong connector dpms state\n"); |
3602 | "wrong connector dpms state\n"); |
3606 | WARN(connector->base.encoder != &encoder->base, |
3603 | WARN(connector->base.encoder != &encoder->base, |
3607 | "active connector not linked to encoder\n"); |
3604 | "active connector not linked to encoder\n"); |
3608 | WARN(!encoder->connectors_active, |
3605 | WARN(!encoder->connectors_active, |
3609 | "encoder->connectors_active not set\n"); |
3606 | "encoder->connectors_active not set\n"); |
3610 | 3607 | ||
3611 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3608 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3612 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3609 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3613 | if (WARN_ON(!encoder->base.crtc)) |
3610 | if (WARN_ON(!encoder->base.crtc)) |
3614 | return; |
3611 | return; |
3615 | 3612 | ||
3616 | crtc = encoder->base.crtc; |
3613 | crtc = encoder->base.crtc; |
3617 | 3614 | ||
3618 | WARN(!crtc->enabled, "crtc not enabled\n"); |
3615 | WARN(!crtc->enabled, "crtc not enabled\n"); |
3619 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
3616 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
3620 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
3617 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
3621 | "encoder active on the wrong pipe\n"); |
3618 | "encoder active on the wrong pipe\n"); |
3622 | } |
3619 | } |
3623 | } |
3620 | } |
3624 | 3621 | ||
3625 | /* Even simpler default implementation, if there's really no special case to |
3622 | /* Even simpler default implementation, if there's really no special case to |
3626 | * consider. */ |
3623 | * consider. */ |
3627 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
3624 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
3628 | { |
3625 | { |
3629 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
3626 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
3630 | 3627 | ||
3631 | /* All the simple cases only support two dpms states. */ |
3628 | /* All the simple cases only support two dpms states. */ |
3632 | if (mode != DRM_MODE_DPMS_ON) |
3629 | if (mode != DRM_MODE_DPMS_ON) |
3633 | mode = DRM_MODE_DPMS_OFF; |
3630 | mode = DRM_MODE_DPMS_OFF; |
3634 | 3631 | ||
3635 | if (mode == connector->dpms) |
3632 | if (mode == connector->dpms) |
3636 | return; |
3633 | return; |
3637 | 3634 | ||
3638 | connector->dpms = mode; |
3635 | connector->dpms = mode; |
3639 | 3636 | ||
3640 | /* Only need to change hw state when actually enabled */ |
3637 | /* Only need to change hw state when actually enabled */ |
3641 | if (encoder->base.crtc) |
3638 | if (encoder->base.crtc) |
3642 | intel_encoder_dpms(encoder, mode); |
3639 | intel_encoder_dpms(encoder, mode); |
3643 | else |
3640 | else |
3644 | WARN_ON(encoder->connectors_active != false); |
3641 | WARN_ON(encoder->connectors_active != false); |
3645 | 3642 | ||
3646 | intel_modeset_check_state(connector->dev); |
3643 | intel_modeset_check_state(connector->dev); |
3647 | } |
3644 | } |
3648 | 3645 | ||
3649 | /* Simple connector->get_hw_state implementation for encoders that support only |
3646 | /* Simple connector->get_hw_state implementation for encoders that support only |
3650 | * one connector and no cloning and hence the encoder state determines the state |
3647 | * one connector and no cloning and hence the encoder state determines the state |
3651 | * of the connector. */ |
3648 | * of the connector. */ |
3652 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
3649 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
3653 | { |
3650 | { |
3654 | enum pipe pipe = 0; |
3651 | enum pipe pipe = 0; |
3655 | struct intel_encoder *encoder = connector->encoder; |
3652 | struct intel_encoder *encoder = connector->encoder; |
3656 | 3653 | ||
3657 | return encoder->get_hw_state(encoder, &pipe); |
3654 | return encoder->get_hw_state(encoder, &pipe); |
3658 | } |
3655 | } |
3659 | 3656 | ||
3660 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3657 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3661 | const struct drm_display_mode *mode, |
3658 | const struct drm_display_mode *mode, |
3662 | struct drm_display_mode *adjusted_mode) |
3659 | struct drm_display_mode *adjusted_mode) |
3663 | { |
3660 | { |
3664 | struct drm_device *dev = crtc->dev; |
3661 | struct drm_device *dev = crtc->dev; |
3665 | 3662 | ||
3666 | if (HAS_PCH_SPLIT(dev)) { |
3663 | if (HAS_PCH_SPLIT(dev)) { |
3667 | /* FDI link clock is fixed at 2.7G */ |
3664 | /* FDI link clock is fixed at 2.7G */ |
3668 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3665 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3669 | return false; |
3666 | return false; |
3670 | } |
3667 | } |
3671 | 3668 | ||
3672 | /* All interlaced capable intel hw wants timings in frames. Note though |
3669 | /* All interlaced capable intel hw wants timings in frames. Note though |
3673 | * that intel_lvds_mode_fixup does some funny tricks with the crtc |
3670 | * that intel_lvds_mode_fixup does some funny tricks with the crtc |
3674 | * timings, so we need to be careful not to clobber these.*/ |
3671 | * timings, so we need to be careful not to clobber these.*/ |
3675 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) |
3672 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) |
3676 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
3673 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
3677 | 3674 | ||
3678 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3675 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3679 | * with a hsync front porch of 0. |
3676 | * with a hsync front porch of 0. |
3680 | */ |
3677 | */ |
3681 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
3678 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
3682 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
3679 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
3683 | return false; |
3680 | return false; |
3684 | 3681 | ||
3685 | return true; |
3682 | return true; |
3686 | } |
3683 | } |
3687 | 3684 | ||
3688 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3685 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3689 | { |
3686 | { |
3690 | return 400000; /* FIXME */ |
3687 | return 400000; /* FIXME */ |
3691 | } |
3688 | } |
3692 | 3689 | ||
3693 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3690 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3694 | { |
3691 | { |
3695 | return 400000; |
3692 | return 400000; |
3696 | } |
3693 | } |
3697 | 3694 | ||
3698 | static int i915_get_display_clock_speed(struct drm_device *dev) |
3695 | static int i915_get_display_clock_speed(struct drm_device *dev) |
3699 | { |
3696 | { |
3700 | return 333000; |
3697 | return 333000; |
3701 | } |
3698 | } |
3702 | 3699 | ||
3703 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3700 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3704 | { |
3701 | { |
3705 | return 200000; |
3702 | return 200000; |
3706 | } |
3703 | } |
3707 | 3704 | ||
3708 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3705 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3709 | { |
3706 | { |
3710 | u16 gcfgc = 0; |
3707 | u16 gcfgc = 0; |
3711 | 3708 | ||
3712 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3709 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3713 | 3710 | ||
3714 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
3711 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
3715 | return 133000; |
3712 | return 133000; |
3716 | else { |
3713 | else { |
3717 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
3714 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
3718 | case GC_DISPLAY_CLOCK_333_MHZ: |
3715 | case GC_DISPLAY_CLOCK_333_MHZ: |
3719 | return 333000; |
3716 | return 333000; |
3720 | default: |
3717 | default: |
3721 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
3718 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
3722 | return 190000; |
3719 | return 190000; |
3723 | } |
3720 | } |
3724 | } |
3721 | } |
3725 | } |
3722 | } |
3726 | 3723 | ||
3727 | static int i865_get_display_clock_speed(struct drm_device *dev) |
3724 | static int i865_get_display_clock_speed(struct drm_device *dev) |
3728 | { |
3725 | { |
3729 | return 266000; |
3726 | return 266000; |
3730 | } |
3727 | } |
3731 | 3728 | ||
3732 | static int i855_get_display_clock_speed(struct drm_device *dev) |
3729 | static int i855_get_display_clock_speed(struct drm_device *dev) |
3733 | { |
3730 | { |
3734 | u16 hpllcc = 0; |
3731 | u16 hpllcc = 0; |
3735 | /* Assume that the hardware is in the high speed state. This |
3732 | /* Assume that the hardware is in the high speed state. This |
3736 | * should be the default. |
3733 | * should be the default. |
3737 | */ |
3734 | */ |
3738 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
3735 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
3739 | case GC_CLOCK_133_200: |
3736 | case GC_CLOCK_133_200: |
3740 | case GC_CLOCK_100_200: |
3737 | case GC_CLOCK_100_200: |
3741 | return 200000; |
3738 | return 200000; |
3742 | case GC_CLOCK_166_250: |
3739 | case GC_CLOCK_166_250: |
3743 | return 250000; |
3740 | return 250000; |
3744 | case GC_CLOCK_100_133: |
3741 | case GC_CLOCK_100_133: |
3745 | return 133000; |
3742 | return 133000; |
3746 | } |
3743 | } |
3747 | 3744 | ||
3748 | /* Shouldn't happen */ |
3745 | /* Shouldn't happen */ |
3749 | return 0; |
3746 | return 0; |
3750 | } |
3747 | } |
3751 | 3748 | ||
3752 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3749 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3753 | { |
3750 | { |
3754 | return 133000; |
3751 | return 133000; |
3755 | } |
3752 | } |
3756 | 3753 | ||
3757 | struct fdi_m_n { |
3754 | struct fdi_m_n { |
3758 | u32 tu; |
3755 | u32 tu; |
3759 | u32 gmch_m; |
3756 | u32 gmch_m; |
3760 | u32 gmch_n; |
3757 | u32 gmch_n; |
3761 | u32 link_m; |
3758 | u32 link_m; |
3762 | u32 link_n; |
3759 | u32 link_n; |
3763 | }; |
3760 | }; |
3764 | 3761 | ||
3765 | static void |
3762 | static void |
3766 | fdi_reduce_ratio(u32 *num, u32 *den) |
3763 | fdi_reduce_ratio(u32 *num, u32 *den) |
3767 | { |
3764 | { |
3768 | while (*num > 0xffffff || *den > 0xffffff) { |
3765 | while (*num > 0xffffff || *den > 0xffffff) { |
3769 | *num >>= 1; |
3766 | *num >>= 1; |
3770 | *den >>= 1; |
3767 | *den >>= 1; |
3771 | } |
3768 | } |
3772 | } |
3769 | } |
3773 | 3770 | ||
3774 | static void |
3771 | static void |
3775 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3772 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3776 | int link_clock, struct fdi_m_n *m_n) |
3773 | int link_clock, struct fdi_m_n *m_n) |
3777 | { |
3774 | { |
3778 | m_n->tu = 64; /* default size */ |
3775 | m_n->tu = 64; /* default size */ |
3779 | 3776 | ||
3780 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3777 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3781 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
3778 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
3782 | m_n->gmch_n = link_clock * nlanes * 8; |
3779 | m_n->gmch_n = link_clock * nlanes * 8; |
3783 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3780 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3784 | 3781 | ||
3785 | m_n->link_m = pixel_clock; |
3782 | m_n->link_m = pixel_clock; |
3786 | m_n->link_n = link_clock; |
3783 | m_n->link_n = link_clock; |
3787 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3784 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3788 | } |
3785 | } |
3789 | 3786 | ||
3790 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3787 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3791 | { |
3788 | { |
3792 | if (i915_panel_use_ssc >= 0) |
3789 | if (i915_panel_use_ssc >= 0) |
3793 | return i915_panel_use_ssc != 0; |
3790 | return i915_panel_use_ssc != 0; |
3794 | return dev_priv->lvds_use_ssc |
3791 | return dev_priv->lvds_use_ssc |
3795 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
3792 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
3796 | } |
3793 | } |
3797 | 3794 | ||
3798 | /** |
3795 | /** |
3799 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send |
3796 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send |
3800 | * @crtc: CRTC structure |
3797 | * @crtc: CRTC structure |
3801 | * @mode: requested mode |
3798 | * @mode: requested mode |
3802 | * |
3799 | * |
3803 | * A pipe may be connected to one or more outputs. Based on the depth of the |
3800 | * A pipe may be connected to one or more outputs. Based on the depth of the |
3804 | * attached framebuffer, choose a good color depth to use on the pipe. |
3801 | * attached framebuffer, choose a good color depth to use on the pipe. |
3805 | * |
3802 | * |
3806 | * If possible, match the pipe depth to the fb depth. In some cases, this |
3803 | * If possible, match the pipe depth to the fb depth. In some cases, this |
3807 | * isn't ideal, because the connected output supports a lesser or restricted |
3804 | * isn't ideal, because the connected output supports a lesser or restricted |
3808 | * set of depths. Resolve that here: |
3805 | * set of depths. Resolve that here: |
3809 | * LVDS typically supports only 6bpc, so clamp down in that case |
3806 | * LVDS typically supports only 6bpc, so clamp down in that case |
3810 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc |
3807 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc |
3811 | * Displays may support a restricted set as well, check EDID and clamp as |
3808 | * Displays may support a restricted set as well, check EDID and clamp as |
3812 | * appropriate. |
3809 | * appropriate. |
3813 | * DP may want to dither down to 6bpc to fit larger modes |
3810 | * DP may want to dither down to 6bpc to fit larger modes |
3814 | * |
3811 | * |
3815 | * RETURNS: |
3812 | * RETURNS: |
3816 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, |
3813 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, |
3817 | * true if they don't match). |
3814 | * true if they don't match). |
3818 | */ |
3815 | */ |
3819 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, |
3816 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, |
3820 | struct drm_framebuffer *fb, |
3817 | struct drm_framebuffer *fb, |
3821 | unsigned int *pipe_bpp, |
3818 | unsigned int *pipe_bpp, |
3822 | struct drm_display_mode *mode) |
3819 | struct drm_display_mode *mode) |
3823 | { |
3820 | { |
3824 | struct drm_device *dev = crtc->dev; |
3821 | struct drm_device *dev = crtc->dev; |
3825 | struct drm_i915_private *dev_priv = dev->dev_private; |
3822 | struct drm_i915_private *dev_priv = dev->dev_private; |
3826 | struct drm_connector *connector; |
3823 | struct drm_connector *connector; |
3827 | struct intel_encoder *intel_encoder; |
3824 | struct intel_encoder *intel_encoder; |
3828 | unsigned int display_bpc = UINT_MAX, bpc; |
3825 | unsigned int display_bpc = UINT_MAX, bpc; |
3829 | 3826 | ||
3830 | /* Walk the encoders & connectors on this crtc, get min bpc */ |
3827 | /* Walk the encoders & connectors on this crtc, get min bpc */ |
3831 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3828 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3832 | 3829 | ||
3833 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { |
3830 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { |
3834 | unsigned int lvds_bpc; |
3831 | unsigned int lvds_bpc; |
3835 | 3832 | ||
3836 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == |
3833 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == |
3837 | LVDS_A3_POWER_UP) |
3834 | LVDS_A3_POWER_UP) |
3838 | lvds_bpc = 8; |
3835 | lvds_bpc = 8; |
3839 | else |
3836 | else |
3840 | lvds_bpc = 6; |
3837 | lvds_bpc = 6; |
3841 | 3838 | ||
3842 | if (lvds_bpc < display_bpc) { |
3839 | if (lvds_bpc < display_bpc) { |
3843 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
3840 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
3844 | display_bpc = lvds_bpc; |
3841 | display_bpc = lvds_bpc; |
3845 | } |
3842 | } |
3846 | continue; |
3843 | continue; |
3847 | } |
3844 | } |
3848 | 3845 | ||
3849 | /* Not one of the known troublemakers, check the EDID */ |
3846 | /* Not one of the known troublemakers, check the EDID */ |
3850 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
3847 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
3851 | head) { |
3848 | head) { |
3852 | if (connector->encoder != &intel_encoder->base) |
3849 | if (connector->encoder != &intel_encoder->base) |
3853 | continue; |
3850 | continue; |
3854 | 3851 | ||
3855 | /* Don't use an invalid EDID bpc value */ |
3852 | /* Don't use an invalid EDID bpc value */ |
3856 | if (connector->display_info.bpc && |
3853 | if (connector->display_info.bpc && |
3857 | connector->display_info.bpc < display_bpc) { |
3854 | connector->display_info.bpc < display_bpc) { |
3858 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
3855 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
3859 | display_bpc = connector->display_info.bpc; |
3856 | display_bpc = connector->display_info.bpc; |
3860 | } |
3857 | } |
3861 | } |
3858 | } |
3862 | 3859 | ||
3863 | /* |
3860 | /* |
3864 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
3861 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
3865 | * through, clamp it down. (Note: >12bpc will be caught below.) |
3862 | * through, clamp it down. (Note: >12bpc will be caught below.) |
3866 | */ |
3863 | */ |
3867 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
3864 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
3868 | if (display_bpc > 8 && display_bpc < 12) { |
3865 | if (display_bpc > 8 && display_bpc < 12) { |
3869 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
3866 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
3870 | display_bpc = 12; |
3867 | display_bpc = 12; |
3871 | } else { |
3868 | } else { |
3872 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
3869 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
3873 | display_bpc = 8; |
3870 | display_bpc = 8; |
3874 | } |
3871 | } |
3875 | } |
3872 | } |
3876 | } |
3873 | } |
3877 | 3874 | ||
3878 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3875 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3879 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); |
3876 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); |
3880 | display_bpc = 6; |
3877 | display_bpc = 6; |
3881 | } |
3878 | } |
3882 | 3879 | ||
3883 | /* |
3880 | /* |
3884 | * We could just drive the pipe at the highest bpc all the time and |
3881 | * We could just drive the pipe at the highest bpc all the time and |
3885 | * enable dithering as needed, but that costs bandwidth. So choose |
3882 | * enable dithering as needed, but that costs bandwidth. So choose |
3886 | * the minimum value that expresses the full color range of the fb but |
3883 | * the minimum value that expresses the full color range of the fb but |
3887 | * also stays within the max display bpc discovered above. |
3884 | * also stays within the max display bpc discovered above. |
3888 | */ |
3885 | */ |
3889 | 3886 | ||
3890 | switch (fb->depth) { |
3887 | switch (fb->depth) { |
3891 | case 8: |
3888 | case 8: |
3892 | bpc = 8; /* since we go through a colormap */ |
3889 | bpc = 8; /* since we go through a colormap */ |
3893 | break; |
3890 | break; |
3894 | case 15: |
3891 | case 15: |
3895 | case 16: |
3892 | case 16: |
3896 | bpc = 6; /* min is 18bpp */ |
3893 | bpc = 6; /* min is 18bpp */ |
3897 | break; |
3894 | break; |
3898 | case 24: |
3895 | case 24: |
3899 | bpc = 8; |
3896 | bpc = 8; |
3900 | break; |
3897 | break; |
3901 | case 30: |
3898 | case 30: |
3902 | bpc = 10; |
3899 | bpc = 10; |
3903 | break; |
3900 | break; |
3904 | case 48: |
3901 | case 48: |
3905 | bpc = 12; |
3902 | bpc = 12; |
3906 | break; |
3903 | break; |
3907 | default: |
3904 | default: |
3908 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); |
3905 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); |
3909 | bpc = min((unsigned int)8, display_bpc); |
3906 | bpc = min((unsigned int)8, display_bpc); |
3910 | break; |
3907 | break; |
3911 | } |
3908 | } |
3912 | 3909 | ||
3913 | display_bpc = min(display_bpc, bpc); |
3910 | display_bpc = min(display_bpc, bpc); |
3914 | 3911 | ||
3915 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
3912 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
3916 | bpc, display_bpc); |
3913 | bpc, display_bpc); |
3917 | 3914 | ||
3918 | *pipe_bpp = display_bpc * 3; |
3915 | *pipe_bpp = display_bpc * 3; |
3919 | 3916 | ||
3920 | return display_bpc != bpc; |
3917 | return display_bpc != bpc; |
3921 | } |
3918 | } |
3922 | 3919 | ||
3923 | static int vlv_get_refclk(struct drm_crtc *crtc) |
3920 | static int vlv_get_refclk(struct drm_crtc *crtc) |
3924 | { |
3921 | { |
3925 | struct drm_device *dev = crtc->dev; |
3922 | struct drm_device *dev = crtc->dev; |
3926 | struct drm_i915_private *dev_priv = dev->dev_private; |
3923 | struct drm_i915_private *dev_priv = dev->dev_private; |
3927 | int refclk = 27000; /* for DP & HDMI */ |
3924 | int refclk = 27000; /* for DP & HDMI */ |
3928 | 3925 | ||
3929 | return 100000; /* only one validated so far */ |
3926 | return 100000; /* only one validated so far */ |
3930 | 3927 | ||
3931 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
3928 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
3932 | refclk = 96000; |
3929 | refclk = 96000; |
3933 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
3930 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
3934 | if (intel_panel_use_ssc(dev_priv)) |
3931 | if (intel_panel_use_ssc(dev_priv)) |
3935 | refclk = 100000; |
3932 | refclk = 100000; |
3936 | else |
3933 | else |
3937 | refclk = 96000; |
3934 | refclk = 96000; |
3938 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
3935 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
3939 | refclk = 100000; |
3936 | refclk = 100000; |
3940 | } |
3937 | } |
3941 | 3938 | ||
3942 | return refclk; |
3939 | return refclk; |
3943 | } |
3940 | } |
3944 | 3941 | ||
3945 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3942 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3946 | { |
3943 | { |
3947 | struct drm_device *dev = crtc->dev; |
3944 | struct drm_device *dev = crtc->dev; |
3948 | struct drm_i915_private *dev_priv = dev->dev_private; |
3945 | struct drm_i915_private *dev_priv = dev->dev_private; |
3949 | int refclk; |
3946 | int refclk; |
3950 | 3947 | ||
3951 | if (IS_VALLEYVIEW(dev)) { |
3948 | if (IS_VALLEYVIEW(dev)) { |
3952 | refclk = vlv_get_refclk(crtc); |
3949 | refclk = vlv_get_refclk(crtc); |
3953 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
3950 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
3954 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
3951 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
3955 | refclk = dev_priv->lvds_ssc_freq * 1000; |
3952 | refclk = dev_priv->lvds_ssc_freq * 1000; |
3956 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
3953 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
3957 | refclk / 1000); |
3954 | refclk / 1000); |
3958 | } else if (!IS_GEN2(dev)) { |
3955 | } else if (!IS_GEN2(dev)) { |
3959 | refclk = 96000; |
3956 | refclk = 96000; |
3960 | } else { |
3957 | } else { |
3961 | refclk = 48000; |
3958 | refclk = 48000; |
3962 | } |
3959 | } |
3963 | 3960 | ||
3964 | return refclk; |
3961 | return refclk; |
3965 | } |
3962 | } |
3966 | 3963 | ||
3967 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, |
3964 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, |
3968 | intel_clock_t *clock) |
3965 | intel_clock_t *clock) |
3969 | { |
3966 | { |
3970 | /* SDVO TV has fixed PLL values depend on its clock range, |
3967 | /* SDVO TV has fixed PLL values depend on its clock range, |
3971 | this mirrors vbios setting. */ |
3968 | this mirrors vbios setting. */ |
3972 | if (adjusted_mode->clock >= 100000 |
3969 | if (adjusted_mode->clock >= 100000 |
3973 | && adjusted_mode->clock < 140500) { |
3970 | && adjusted_mode->clock < 140500) { |
3974 | clock->p1 = 2; |
3971 | clock->p1 = 2; |
3975 | clock->p2 = 10; |
3972 | clock->p2 = 10; |
3976 | clock->n = 3; |
3973 | clock->n = 3; |
3977 | clock->m1 = 16; |
3974 | clock->m1 = 16; |
3978 | clock->m2 = 8; |
3975 | clock->m2 = 8; |
3979 | } else if (adjusted_mode->clock >= 140500 |
3976 | } else if (adjusted_mode->clock >= 140500 |
3980 | && adjusted_mode->clock <= 200000) { |
3977 | && adjusted_mode->clock <= 200000) { |
3981 | clock->p1 = 1; |
3978 | clock->p1 = 1; |
3982 | clock->p2 = 10; |
3979 | clock->p2 = 10; |
3983 | clock->n = 6; |
3980 | clock->n = 6; |
3984 | clock->m1 = 12; |
3981 | clock->m1 = 12; |
3985 | clock->m2 = 8; |
3982 | clock->m2 = 8; |
3986 | } |
3983 | } |
3987 | } |
3984 | } |
3988 | 3985 | ||
3989 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3986 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3990 | intel_clock_t *clock, |
3987 | intel_clock_t *clock, |
3991 | intel_clock_t *reduced_clock) |
3988 | intel_clock_t *reduced_clock) |
3992 | { |
3989 | { |
3993 | struct drm_device *dev = crtc->dev; |
3990 | struct drm_device *dev = crtc->dev; |
3994 | struct drm_i915_private *dev_priv = dev->dev_private; |
3991 | struct drm_i915_private *dev_priv = dev->dev_private; |
3995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3996 | int pipe = intel_crtc->pipe; |
3993 | int pipe = intel_crtc->pipe; |
3997 | u32 fp, fp2 = 0; |
3994 | u32 fp, fp2 = 0; |
3998 | 3995 | ||
3999 | if (IS_PINEVIEW(dev)) { |
3996 | if (IS_PINEVIEW(dev)) { |
4000 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; |
3997 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; |
4001 | if (reduced_clock) |
3998 | if (reduced_clock) |
4002 | fp2 = (1 << reduced_clock->n) << 16 | |
3999 | fp2 = (1 << reduced_clock->n) << 16 | |
4003 | reduced_clock->m1 << 8 | reduced_clock->m2; |
4000 | reduced_clock->m1 << 8 | reduced_clock->m2; |
4004 | } else { |
4001 | } else { |
4005 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; |
4002 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; |
4006 | if (reduced_clock) |
4003 | if (reduced_clock) |
4007 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | |
4004 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | |
4008 | reduced_clock->m2; |
4005 | reduced_clock->m2; |
4009 | } |
4006 | } |
4010 | 4007 | ||
4011 | I915_WRITE(FP0(pipe), fp); |
4008 | I915_WRITE(FP0(pipe), fp); |
4012 | 4009 | ||
4013 | intel_crtc->lowfreq_avail = false; |
4010 | intel_crtc->lowfreq_avail = false; |
4014 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4011 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4015 | reduced_clock && i915_powersave) { |
4012 | reduced_clock && i915_powersave) { |
4016 | I915_WRITE(FP1(pipe), fp2); |
4013 | I915_WRITE(FP1(pipe), fp2); |
4017 | intel_crtc->lowfreq_avail = true; |
4014 | intel_crtc->lowfreq_avail = true; |
4018 | } else { |
4015 | } else { |
4019 | I915_WRITE(FP1(pipe), fp); |
4016 | I915_WRITE(FP1(pipe), fp); |
4020 | } |
4017 | } |
4021 | } |
4018 | } |
4022 | 4019 | ||
4023 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
4020 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
4024 | struct drm_display_mode *adjusted_mode) |
4021 | struct drm_display_mode *adjusted_mode) |
4025 | { |
4022 | { |
4026 | struct drm_device *dev = crtc->dev; |
4023 | struct drm_device *dev = crtc->dev; |
4027 | struct drm_i915_private *dev_priv = dev->dev_private; |
4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
4028 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4029 | int pipe = intel_crtc->pipe; |
4026 | int pipe = intel_crtc->pipe; |
4030 | u32 temp; |
4027 | u32 temp; |
4031 | 4028 | ||
4032 | temp = I915_READ(LVDS); |
4029 | temp = I915_READ(LVDS); |
4033 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
4030 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
4034 | if (pipe == 1) { |
4031 | if (pipe == 1) { |
4035 | temp |= LVDS_PIPEB_SELECT; |
4032 | temp |= LVDS_PIPEB_SELECT; |
4036 | } else { |
4033 | } else { |
4037 | temp &= ~LVDS_PIPEB_SELECT; |
4034 | temp &= ~LVDS_PIPEB_SELECT; |
4038 | } |
4035 | } |
4039 | /* set the corresponsding LVDS_BORDER bit */ |
4036 | /* set the corresponsding LVDS_BORDER bit */ |
4040 | temp |= dev_priv->lvds_border_bits; |
4037 | temp |= dev_priv->lvds_border_bits; |
4041 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4038 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4042 | * set the DPLLs for dual-channel mode or not. |
4039 | * set the DPLLs for dual-channel mode or not. |
4043 | */ |
4040 | */ |
4044 | if (clock->p2 == 7) |
4041 | if (clock->p2 == 7) |
4045 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
4042 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
4046 | else |
4043 | else |
4047 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
4044 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
4048 | 4045 | ||
4049 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
4046 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
4050 | * appropriately here, but we need to look more thoroughly into how |
4047 | * appropriately here, but we need to look more thoroughly into how |
4051 | * panels behave in the two modes. |
4048 | * panels behave in the two modes. |
4052 | */ |
4049 | */ |
4053 | /* set the dithering flag on LVDS as needed */ |
4050 | /* set the dithering flag on LVDS as needed */ |
4054 | if (INTEL_INFO(dev)->gen >= 4) { |
4051 | if (INTEL_INFO(dev)->gen >= 4) { |
4055 | if (dev_priv->lvds_dither) |
4052 | if (dev_priv->lvds_dither) |
4056 | temp |= LVDS_ENABLE_DITHER; |
4053 | temp |= LVDS_ENABLE_DITHER; |
4057 | else |
4054 | else |
4058 | temp &= ~LVDS_ENABLE_DITHER; |
4055 | temp &= ~LVDS_ENABLE_DITHER; |
4059 | } |
4056 | } |
4060 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
4057 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
4061 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
4058 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
4062 | temp |= LVDS_HSYNC_POLARITY; |
4059 | temp |= LVDS_HSYNC_POLARITY; |
4063 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
4060 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
4064 | temp |= LVDS_VSYNC_POLARITY; |
4061 | temp |= LVDS_VSYNC_POLARITY; |
4065 | I915_WRITE(LVDS, temp); |
4062 | I915_WRITE(LVDS, temp); |
4066 | } |
4063 | } |
4067 | 4064 | ||
4068 | static void vlv_update_pll(struct drm_crtc *crtc, |
4065 | static void vlv_update_pll(struct drm_crtc *crtc, |
4069 | struct drm_display_mode *mode, |
4066 | struct drm_display_mode *mode, |
4070 | struct drm_display_mode *adjusted_mode, |
4067 | struct drm_display_mode *adjusted_mode, |
4071 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
4068 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
4072 | int refclk, int num_connectors) |
4069 | int refclk, int num_connectors) |
4073 | { |
4070 | { |
4074 | struct drm_device *dev = crtc->dev; |
4071 | struct drm_device *dev = crtc->dev; |
4075 | struct drm_i915_private *dev_priv = dev->dev_private; |
4072 | struct drm_i915_private *dev_priv = dev->dev_private; |
4076 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4077 | int pipe = intel_crtc->pipe; |
4074 | int pipe = intel_crtc->pipe; |
4078 | u32 dpll, mdiv, pdiv; |
4075 | u32 dpll, mdiv, pdiv; |
4079 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4076 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4080 | bool is_hdmi; |
4077 | bool is_hdmi; |
4081 | 4078 | ||
4082 | is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
4079 | is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
4083 | 4080 | ||
4084 | bestn = clock->n; |
4081 | bestn = clock->n; |
4085 | bestm1 = clock->m1; |
4082 | bestm1 = clock->m1; |
4086 | bestm2 = clock->m2; |
4083 | bestm2 = clock->m2; |
4087 | bestp1 = clock->p1; |
4084 | bestp1 = clock->p1; |
4088 | bestp2 = clock->p2; |
4085 | bestp2 = clock->p2; |
4089 | 4086 | ||
4090 | /* Enable DPIO clock input */ |
4087 | /* Enable DPIO clock input */ |
4091 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4088 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4092 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4089 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4093 | I915_WRITE(DPLL(pipe), dpll); |
4090 | I915_WRITE(DPLL(pipe), dpll); |
4094 | POSTING_READ(DPLL(pipe)); |
4091 | POSTING_READ(DPLL(pipe)); |
4095 | 4092 | ||
4096 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4093 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4097 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4094 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4098 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4095 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4099 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); |
4096 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); |
4100 | mdiv |= (1 << DPIO_K_SHIFT); |
4097 | mdiv |= (1 << DPIO_K_SHIFT); |
4101 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4098 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4102 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4099 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4103 | 4100 | ||
4104 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); |
4101 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); |
4105 | 4102 | ||
4106 | pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | |
4103 | pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | |
4107 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
4104 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
4108 | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); |
4105 | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); |
4109 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4106 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4110 | 4107 | ||
4111 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); |
4108 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); |
4112 | 4109 | ||
4113 | dpll |= DPLL_VCO_ENABLE; |
4110 | dpll |= DPLL_VCO_ENABLE; |
4114 | I915_WRITE(DPLL(pipe), dpll); |
4111 | I915_WRITE(DPLL(pipe), dpll); |
4115 | POSTING_READ(DPLL(pipe)); |
4112 | POSTING_READ(DPLL(pipe)); |
4116 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
4113 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
4117 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
4114 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
4118 | 4115 | ||
4119 | if (is_hdmi) { |
4116 | if (is_hdmi) { |
4120 | u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4117 | u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4121 | 4118 | ||
4122 | if (temp > 1) |
4119 | if (temp > 1) |
4123 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4120 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4124 | else |
4121 | else |
4125 | temp = 0; |
4122 | temp = 0; |
4126 | 4123 | ||
4127 | I915_WRITE(DPLL_MD(pipe), temp); |
4124 | I915_WRITE(DPLL_MD(pipe), temp); |
4128 | POSTING_READ(DPLL_MD(pipe)); |
4125 | POSTING_READ(DPLL_MD(pipe)); |
4129 | } |
4126 | } |
4130 | 4127 | ||
4131 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ |
4128 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ |
4132 | } |
4129 | } |
4133 | 4130 | ||
4134 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4131 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4135 | struct drm_display_mode *mode, |
4132 | struct drm_display_mode *mode, |
4136 | struct drm_display_mode *adjusted_mode, |
4133 | struct drm_display_mode *adjusted_mode, |
4137 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
4134 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
4138 | int num_connectors) |
4135 | int num_connectors) |
4139 | { |
4136 | { |
4140 | struct drm_device *dev = crtc->dev; |
4137 | struct drm_device *dev = crtc->dev; |
4141 | struct drm_i915_private *dev_priv = dev->dev_private; |
4138 | struct drm_i915_private *dev_priv = dev->dev_private; |
4142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4143 | int pipe = intel_crtc->pipe; |
4140 | int pipe = intel_crtc->pipe; |
4144 | u32 dpll; |
4141 | u32 dpll; |
4145 | bool is_sdvo; |
4142 | bool is_sdvo; |
4146 | 4143 | ||
4147 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4144 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4148 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
4145 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
4149 | 4146 | ||
4150 | dpll = DPLL_VGA_MODE_DIS; |
4147 | dpll = DPLL_VGA_MODE_DIS; |
4151 | 4148 | ||
4152 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4149 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4153 | dpll |= DPLLB_MODE_LVDS; |
4150 | dpll |= DPLLB_MODE_LVDS; |
4154 | else |
4151 | else |
4155 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4152 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4156 | if (is_sdvo) { |
4153 | if (is_sdvo) { |
4157 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4154 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4158 | if (pixel_multiplier > 1) { |
4155 | if (pixel_multiplier > 1) { |
4159 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4156 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4160 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
4157 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
4161 | } |
4158 | } |
4162 | dpll |= DPLL_DVO_HIGH_SPEED; |
4159 | dpll |= DPLL_DVO_HIGH_SPEED; |
4163 | } |
4160 | } |
4164 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4161 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4165 | dpll |= DPLL_DVO_HIGH_SPEED; |
4162 | dpll |= DPLL_DVO_HIGH_SPEED; |
4166 | 4163 | ||
4167 | /* compute bitmask from p1 value */ |
4164 | /* compute bitmask from p1 value */ |
4168 | if (IS_PINEVIEW(dev)) |
4165 | if (IS_PINEVIEW(dev)) |
4169 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4166 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4170 | else { |
4167 | else { |
4171 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4168 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4172 | if (IS_G4X(dev) && reduced_clock) |
4169 | if (IS_G4X(dev) && reduced_clock) |
4173 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4170 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4174 | } |
4171 | } |
4175 | switch (clock->p2) { |
4172 | switch (clock->p2) { |
4176 | case 5: |
4173 | case 5: |
4177 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4174 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4178 | break; |
4175 | break; |
4179 | case 7: |
4176 | case 7: |
4180 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4177 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4181 | break; |
4178 | break; |
4182 | case 10: |
4179 | case 10: |
4183 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4180 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4184 | break; |
4181 | break; |
4185 | case 14: |
4182 | case 14: |
4186 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4183 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4187 | break; |
4184 | break; |
4188 | } |
4185 | } |
4189 | if (INTEL_INFO(dev)->gen >= 4) |
4186 | if (INTEL_INFO(dev)->gen >= 4) |
4190 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4187 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4191 | 4188 | ||
4192 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4189 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4193 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4190 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4194 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4191 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4195 | /* XXX: just matching BIOS for now */ |
4192 | /* XXX: just matching BIOS for now */ |
4196 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4193 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4197 | dpll |= 3; |
4194 | dpll |= 3; |
4198 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4195 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4199 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4196 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4200 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4197 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4201 | else |
4198 | else |
4202 | dpll |= PLL_REF_INPUT_DREFCLK; |
4199 | dpll |= PLL_REF_INPUT_DREFCLK; |
4203 | 4200 | ||
4204 | dpll |= DPLL_VCO_ENABLE; |
4201 | dpll |= DPLL_VCO_ENABLE; |
4205 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
4202 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
4206 | POSTING_READ(DPLL(pipe)); |
4203 | POSTING_READ(DPLL(pipe)); |
4207 | udelay(150); |
4204 | udelay(150); |
4208 | 4205 | ||
4209 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4206 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4210 | * This is an exception to the general rule that mode_set doesn't turn |
4207 | * This is an exception to the general rule that mode_set doesn't turn |
4211 | * things on. |
4208 | * things on. |
4212 | */ |
4209 | */ |
4213 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4210 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4214 | intel_update_lvds(crtc, clock, adjusted_mode); |
4211 | intel_update_lvds(crtc, clock, adjusted_mode); |
4215 | 4212 | ||
4216 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4213 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4217 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
4214 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
4218 | 4215 | ||
4219 | I915_WRITE(DPLL(pipe), dpll); |
4216 | I915_WRITE(DPLL(pipe), dpll); |
4220 | 4217 | ||
4221 | /* Wait for the clocks to stabilize. */ |
4218 | /* Wait for the clocks to stabilize. */ |
4222 | POSTING_READ(DPLL(pipe)); |
4219 | POSTING_READ(DPLL(pipe)); |
4223 | udelay(150); |
4220 | udelay(150); |
4224 | 4221 | ||
4225 | if (INTEL_INFO(dev)->gen >= 4) { |
4222 | if (INTEL_INFO(dev)->gen >= 4) { |
4226 | u32 temp = 0; |
4223 | u32 temp = 0; |
4227 | if (is_sdvo) { |
4224 | if (is_sdvo) { |
4228 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4225 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4229 | if (temp > 1) |
4226 | if (temp > 1) |
4230 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4227 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4231 | else |
4228 | else |
4232 | temp = 0; |
4229 | temp = 0; |
4233 | } |
4230 | } |
4234 | I915_WRITE(DPLL_MD(pipe), temp); |
4231 | I915_WRITE(DPLL_MD(pipe), temp); |
4235 | } else { |
4232 | } else { |
4236 | /* The pixel multiplier can only be updated once the |
4233 | /* The pixel multiplier can only be updated once the |
4237 | * DPLL is enabled and the clocks are stable. |
4234 | * DPLL is enabled and the clocks are stable. |
4238 | * |
4235 | * |
4239 | * So write it again. |
4236 | * So write it again. |
4240 | */ |
4237 | */ |
4241 | I915_WRITE(DPLL(pipe), dpll); |
4238 | I915_WRITE(DPLL(pipe), dpll); |
4242 | } |
4239 | } |
4243 | } |
4240 | } |
4244 | 4241 | ||
4245 | static void i8xx_update_pll(struct drm_crtc *crtc, |
4242 | static void i8xx_update_pll(struct drm_crtc *crtc, |
4246 | struct drm_display_mode *adjusted_mode, |
4243 | struct drm_display_mode *adjusted_mode, |
4247 | intel_clock_t *clock, |
4244 | intel_clock_t *clock, |
4248 | int num_connectors) |
4245 | int num_connectors) |
4249 | { |
4246 | { |
4250 | struct drm_device *dev = crtc->dev; |
4247 | struct drm_device *dev = crtc->dev; |
4251 | struct drm_i915_private *dev_priv = dev->dev_private; |
4248 | struct drm_i915_private *dev_priv = dev->dev_private; |
4252 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4253 | int pipe = intel_crtc->pipe; |
4250 | int pipe = intel_crtc->pipe; |
4254 | u32 dpll; |
4251 | u32 dpll; |
4255 | 4252 | ||
4256 | dpll = DPLL_VGA_MODE_DIS; |
4253 | dpll = DPLL_VGA_MODE_DIS; |
4257 | 4254 | ||
4258 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4255 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4259 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4256 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4260 | } else { |
4257 | } else { |
4261 | if (clock->p1 == 2) |
4258 | if (clock->p1 == 2) |
4262 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4259 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4263 | else |
4260 | else |
4264 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4261 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4265 | if (clock->p2 == 4) |
4262 | if (clock->p2 == 4) |
4266 | dpll |= PLL_P2_DIVIDE_BY_4; |
4263 | dpll |= PLL_P2_DIVIDE_BY_4; |
4267 | } |
4264 | } |
4268 | 4265 | ||
4269 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4266 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
4270 | /* XXX: just matching BIOS for now */ |
4267 | /* XXX: just matching BIOS for now */ |
4271 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4268 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4272 | dpll |= 3; |
4269 | dpll |= 3; |
4273 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4270 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4274 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4271 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4275 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4272 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4276 | else |
4273 | else |
4277 | dpll |= PLL_REF_INPUT_DREFCLK; |
4274 | dpll |= PLL_REF_INPUT_DREFCLK; |
4278 | 4275 | ||
4279 | dpll |= DPLL_VCO_ENABLE; |
4276 | dpll |= DPLL_VCO_ENABLE; |
4280 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
4277 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
4281 | POSTING_READ(DPLL(pipe)); |
4278 | POSTING_READ(DPLL(pipe)); |
4282 | udelay(150); |
4279 | udelay(150); |
4283 | 4280 | ||
4284 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4281 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4285 | * This is an exception to the general rule that mode_set doesn't turn |
4282 | * This is an exception to the general rule that mode_set doesn't turn |
4286 | * things on. |
4283 | * things on. |
4287 | */ |
4284 | */ |
4288 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4285 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
4289 | intel_update_lvds(crtc, clock, adjusted_mode); |
4286 | intel_update_lvds(crtc, clock, adjusted_mode); |
4290 | 4287 | ||
4291 | I915_WRITE(DPLL(pipe), dpll); |
4288 | I915_WRITE(DPLL(pipe), dpll); |
4292 | 4289 | ||
4293 | /* Wait for the clocks to stabilize. */ |
4290 | /* Wait for the clocks to stabilize. */ |
4294 | POSTING_READ(DPLL(pipe)); |
4291 | POSTING_READ(DPLL(pipe)); |
4295 | udelay(150); |
4292 | udelay(150); |
4296 | 4293 | ||
4297 | /* The pixel multiplier can only be updated once the |
4294 | /* The pixel multiplier can only be updated once the |
4298 | * DPLL is enabled and the clocks are stable. |
4295 | * DPLL is enabled and the clocks are stable. |
4299 | * |
4296 | * |
4300 | * So write it again. |
4297 | * So write it again. |
4301 | */ |
4298 | */ |
4302 | I915_WRITE(DPLL(pipe), dpll); |
4299 | I915_WRITE(DPLL(pipe), dpll); |
4303 | } |
4300 | } |
4304 | 4301 | ||
4305 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4302 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4306 | struct drm_display_mode *mode, |
4303 | struct drm_display_mode *mode, |
4307 | struct drm_display_mode *adjusted_mode, |
4304 | struct drm_display_mode *adjusted_mode, |
4308 | int x, int y, |
4305 | int x, int y, |
4309 | struct drm_framebuffer *fb) |
4306 | struct drm_framebuffer *fb) |
4310 | { |
4307 | { |
4311 | struct drm_device *dev = crtc->dev; |
4308 | struct drm_device *dev = crtc->dev; |
4312 | struct drm_i915_private *dev_priv = dev->dev_private; |
4309 | struct drm_i915_private *dev_priv = dev->dev_private; |
4313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4314 | int pipe = intel_crtc->pipe; |
4311 | int pipe = intel_crtc->pipe; |
4315 | int plane = intel_crtc->plane; |
4312 | int plane = intel_crtc->plane; |
4316 | int refclk, num_connectors = 0; |
4313 | int refclk, num_connectors = 0; |
4317 | intel_clock_t clock, reduced_clock; |
4314 | intel_clock_t clock, reduced_clock; |
4318 | u32 dspcntr, pipeconf, vsyncshift; |
4315 | u32 dspcntr, pipeconf, vsyncshift; |
4319 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4316 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4320 | bool is_lvds = false, is_tv = false, is_dp = false; |
4317 | bool is_lvds = false, is_tv = false, is_dp = false; |
4321 | struct intel_encoder *encoder; |
4318 | struct intel_encoder *encoder; |
4322 | const intel_limit_t *limit; |
4319 | const intel_limit_t *limit; |
4323 | int ret; |
4320 | int ret; |
4324 | 4321 | ||
4325 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4322 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4326 | switch (encoder->type) { |
4323 | switch (encoder->type) { |
4327 | case INTEL_OUTPUT_LVDS: |
4324 | case INTEL_OUTPUT_LVDS: |
4328 | is_lvds = true; |
4325 | is_lvds = true; |
4329 | break; |
4326 | break; |
4330 | case INTEL_OUTPUT_SDVO: |
4327 | case INTEL_OUTPUT_SDVO: |
4331 | case INTEL_OUTPUT_HDMI: |
4328 | case INTEL_OUTPUT_HDMI: |
4332 | is_sdvo = true; |
4329 | is_sdvo = true; |
4333 | if (encoder->needs_tv_clock) |
4330 | if (encoder->needs_tv_clock) |
4334 | is_tv = true; |
4331 | is_tv = true; |
4335 | break; |
4332 | break; |
4336 | case INTEL_OUTPUT_TVOUT: |
4333 | case INTEL_OUTPUT_TVOUT: |
4337 | is_tv = true; |
4334 | is_tv = true; |
4338 | break; |
4335 | break; |
4339 | case INTEL_OUTPUT_DISPLAYPORT: |
4336 | case INTEL_OUTPUT_DISPLAYPORT: |
4340 | is_dp = true; |
4337 | is_dp = true; |
4341 | break; |
4338 | break; |
4342 | } |
4339 | } |
4343 | 4340 | ||
4344 | num_connectors++; |
4341 | num_connectors++; |
4345 | } |
4342 | } |
4346 | 4343 | ||
4347 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4344 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4348 | 4345 | ||
4349 | /* |
4346 | /* |
4350 | * Returns a set of divisors for the desired target clock with the given |
4347 | * Returns a set of divisors for the desired target clock with the given |
4351 | * refclk, or FALSE. The returned values represent the clock equation: |
4348 | * refclk, or FALSE. The returned values represent the clock equation: |
4352 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4349 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4353 | */ |
4350 | */ |
4354 | limit = intel_limit(crtc, refclk); |
4351 | limit = intel_limit(crtc, refclk); |
4355 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4352 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4356 | &clock); |
4353 | &clock); |
4357 | if (!ok) { |
4354 | if (!ok) { |
4358 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4355 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4359 | return -EINVAL; |
4356 | return -EINVAL; |
4360 | } |
4357 | } |
4361 | 4358 | ||
4362 | /* Ensure that the cursor is valid for the new mode before changing... */ |
4359 | /* Ensure that the cursor is valid for the new mode before changing... */ |
4363 | // intel_crtc_update_cursor(crtc, true); |
4360 | // intel_crtc_update_cursor(crtc, true); |
4364 | 4361 | ||
4365 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4362 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4366 | /* |
4363 | /* |
4367 | * Ensure we match the reduced clock's P to the target clock. |
4364 | * Ensure we match the reduced clock's P to the target clock. |
4368 | * If the clocks don't match, we can't switch the display clock |
4365 | * If the clocks don't match, we can't switch the display clock |
4369 | * by using the FP0/FP1. In such case we will disable the LVDS |
4366 | * by using the FP0/FP1. In such case we will disable the LVDS |
4370 | * downclock feature. |
4367 | * downclock feature. |
4371 | */ |
4368 | */ |
4372 | has_reduced_clock = limit->find_pll(limit, crtc, |
4369 | has_reduced_clock = limit->find_pll(limit, crtc, |
4373 | dev_priv->lvds_downclock, |
4370 | dev_priv->lvds_downclock, |
4374 | refclk, |
4371 | refclk, |
4375 | &clock, |
4372 | &clock, |
4376 | &reduced_clock); |
4373 | &reduced_clock); |
4377 | } |
4374 | } |
4378 | 4375 | ||
4379 | if (is_sdvo && is_tv) |
4376 | if (is_sdvo && is_tv) |
4380 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); |
4377 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); |
4381 | 4378 | ||
4382 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
4379 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
4383 | &reduced_clock : NULL); |
4380 | &reduced_clock : NULL); |
4384 | 4381 | ||
4385 | if (IS_GEN2(dev)) |
4382 | if (IS_GEN2(dev)) |
4386 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); |
4383 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); |
4387 | else if (IS_VALLEYVIEW(dev)) |
4384 | else if (IS_VALLEYVIEW(dev)) |
4388 | vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, |
4385 | vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, |
4389 | refclk, num_connectors); |
4386 | refclk, num_connectors); |
4390 | else |
4387 | else |
4391 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4388 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4392 | has_reduced_clock ? &reduced_clock : NULL, |
4389 | has_reduced_clock ? &reduced_clock : NULL, |
4393 | num_connectors); |
4390 | num_connectors); |
4394 | 4391 | ||
4395 | /* setup pipeconf */ |
4392 | /* setup pipeconf */ |
4396 | pipeconf = I915_READ(PIPECONF(pipe)); |
4393 | pipeconf = I915_READ(PIPECONF(pipe)); |
4397 | 4394 | ||
4398 | /* Set up the display plane register */ |
4395 | /* Set up the display plane register */ |
4399 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4396 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4400 | 4397 | ||
4401 | if (pipe == 0) |
4398 | if (pipe == 0) |
4402 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4399 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4403 | else |
4400 | else |
4404 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4401 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4405 | 4402 | ||
4406 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4403 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4407 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4404 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4408 | * core speed. |
4405 | * core speed. |
4409 | * |
4406 | * |
4410 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4407 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4411 | * pipe == 0 check? |
4408 | * pipe == 0 check? |
4412 | */ |
4409 | */ |
4413 | if (mode->clock > |
4410 | if (mode->clock > |
4414 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4411 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4415 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4412 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4416 | else |
4413 | else |
4417 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
4414 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
4418 | } |
4415 | } |
4419 | 4416 | ||
4420 | /* default to 8bpc */ |
4417 | /* default to 8bpc */ |
4421 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); |
4418 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); |
4422 | if (is_dp) { |
4419 | if (is_dp) { |
4423 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4420 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4424 | pipeconf |= PIPECONF_BPP_6 | |
4421 | pipeconf |= PIPECONF_BPP_6 | |
4425 | PIPECONF_DITHER_EN | |
4422 | PIPECONF_DITHER_EN | |
4426 | PIPECONF_DITHER_TYPE_SP; |
4423 | PIPECONF_DITHER_TYPE_SP; |
4427 | } |
4424 | } |
4428 | } |
4425 | } |
4429 | 4426 | ||
4430 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
4427 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
4431 | drm_mode_debug_printmodeline(mode); |
4428 | drm_mode_debug_printmodeline(mode); |
4432 | 4429 | ||
4433 | if (HAS_PIPE_CXSR(dev)) { |
4430 | if (HAS_PIPE_CXSR(dev)) { |
4434 | if (intel_crtc->lowfreq_avail) { |
4431 | if (intel_crtc->lowfreq_avail) { |
4435 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4432 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4436 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4433 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4437 | } else { |
4434 | } else { |
4438 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4435 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4439 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4436 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4440 | } |
4437 | } |
4441 | } |
4438 | } |
4442 | 4439 | ||
4443 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
4440 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
4444 | if (!IS_GEN2(dev) && |
4441 | if (!IS_GEN2(dev) && |
4445 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4442 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4446 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4443 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4447 | /* the chip adds 2 halflines automatically */ |
4444 | /* the chip adds 2 halflines automatically */ |
4448 | adjusted_mode->crtc_vtotal -= 1; |
4445 | adjusted_mode->crtc_vtotal -= 1; |
4449 | adjusted_mode->crtc_vblank_end -= 1; |
4446 | adjusted_mode->crtc_vblank_end -= 1; |
4450 | vsyncshift = adjusted_mode->crtc_hsync_start |
4447 | vsyncshift = adjusted_mode->crtc_hsync_start |
4451 | - adjusted_mode->crtc_htotal/2; |
4448 | - adjusted_mode->crtc_htotal/2; |
4452 | } else { |
4449 | } else { |
4453 | pipeconf |= PIPECONF_PROGRESSIVE; |
4450 | pipeconf |= PIPECONF_PROGRESSIVE; |
4454 | vsyncshift = 0; |
4451 | vsyncshift = 0; |
4455 | } |
4452 | } |
4456 | 4453 | ||
4457 | if (!IS_GEN3(dev)) |
4454 | if (!IS_GEN3(dev)) |
4458 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); |
4455 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); |
4459 | 4456 | ||
4460 | I915_WRITE(HTOTAL(pipe), |
4457 | I915_WRITE(HTOTAL(pipe), |
4461 | (adjusted_mode->crtc_hdisplay - 1) | |
4458 | (adjusted_mode->crtc_hdisplay - 1) | |
4462 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4459 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4463 | I915_WRITE(HBLANK(pipe), |
4460 | I915_WRITE(HBLANK(pipe), |
4464 | (adjusted_mode->crtc_hblank_start - 1) | |
4461 | (adjusted_mode->crtc_hblank_start - 1) | |
4465 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4462 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4466 | I915_WRITE(HSYNC(pipe), |
4463 | I915_WRITE(HSYNC(pipe), |
4467 | (adjusted_mode->crtc_hsync_start - 1) | |
4464 | (adjusted_mode->crtc_hsync_start - 1) | |
4468 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4465 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4469 | 4466 | ||
4470 | I915_WRITE(VTOTAL(pipe), |
4467 | I915_WRITE(VTOTAL(pipe), |
4471 | (adjusted_mode->crtc_vdisplay - 1) | |
4468 | (adjusted_mode->crtc_vdisplay - 1) | |
4472 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
4469 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
4473 | I915_WRITE(VBLANK(pipe), |
4470 | I915_WRITE(VBLANK(pipe), |
4474 | (adjusted_mode->crtc_vblank_start - 1) | |
4471 | (adjusted_mode->crtc_vblank_start - 1) | |
4475 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
4472 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
4476 | I915_WRITE(VSYNC(pipe), |
4473 | I915_WRITE(VSYNC(pipe), |
4477 | (adjusted_mode->crtc_vsync_start - 1) | |
4474 | (adjusted_mode->crtc_vsync_start - 1) | |
4478 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4475 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4479 | 4476 | ||
4480 | /* pipesrc and dspsize control the size that is scaled from, |
4477 | /* pipesrc and dspsize control the size that is scaled from, |
4481 | * which should always be the user's requested size. |
4478 | * which should always be the user's requested size. |
4482 | */ |
4479 | */ |
4483 | I915_WRITE(DSPSIZE(plane), |
4480 | I915_WRITE(DSPSIZE(plane), |
4484 | ((mode->vdisplay - 1) << 16) | |
4481 | ((mode->vdisplay - 1) << 16) | |
4485 | (mode->hdisplay - 1)); |
4482 | (mode->hdisplay - 1)); |
4486 | I915_WRITE(DSPPOS(plane), 0); |
4483 | I915_WRITE(DSPPOS(plane), 0); |
4487 | I915_WRITE(PIPESRC(pipe), |
4484 | I915_WRITE(PIPESRC(pipe), |
4488 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4485 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4489 | 4486 | ||
4490 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4487 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4491 | POSTING_READ(PIPECONF(pipe)); |
4488 | POSTING_READ(PIPECONF(pipe)); |
4492 | intel_enable_pipe(dev_priv, pipe, false); |
4489 | intel_enable_pipe(dev_priv, pipe, false); |
4493 | 4490 | ||
4494 | intel_wait_for_vblank(dev, pipe); |
4491 | intel_wait_for_vblank(dev, pipe); |
4495 | 4492 | ||
4496 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4493 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4497 | POSTING_READ(DSPCNTR(plane)); |
4494 | POSTING_READ(DSPCNTR(plane)); |
4498 | 4495 | ||
4499 | ret = intel_pipe_set_base(crtc, x, y, fb); |
4496 | ret = intel_pipe_set_base(crtc, x, y, fb); |
4500 | 4497 | ||
4501 | intel_update_watermarks(dev); |
4498 | intel_update_watermarks(dev); |
4502 | 4499 | ||
4503 | return ret; |
4500 | return ret; |
4504 | } |
4501 | } |
4505 | 4502 | ||
4506 | /* |
4503 | /* |
4507 | * Initialize reference clocks when the driver loads |
4504 | * Initialize reference clocks when the driver loads |
4508 | */ |
4505 | */ |
4509 | void ironlake_init_pch_refclk(struct drm_device *dev) |
4506 | void ironlake_init_pch_refclk(struct drm_device *dev) |
4510 | { |
4507 | { |
4511 | struct drm_i915_private *dev_priv = dev->dev_private; |
4508 | struct drm_i915_private *dev_priv = dev->dev_private; |
4512 | struct drm_mode_config *mode_config = &dev->mode_config; |
4509 | struct drm_mode_config *mode_config = &dev->mode_config; |
4513 | struct intel_encoder *encoder; |
4510 | struct intel_encoder *encoder; |
4514 | u32 temp; |
4511 | u32 temp; |
4515 | bool has_lvds = false; |
4512 | bool has_lvds = false; |
4516 | bool has_cpu_edp = false; |
4513 | bool has_cpu_edp = false; |
4517 | bool has_pch_edp = false; |
4514 | bool has_pch_edp = false; |
4518 | bool has_panel = false; |
4515 | bool has_panel = false; |
4519 | bool has_ck505 = false; |
4516 | bool has_ck505 = false; |
4520 | bool can_ssc = false; |
4517 | bool can_ssc = false; |
4521 | 4518 | ||
4522 | /* We need to take the global config into account */ |
4519 | /* We need to take the global config into account */ |
4523 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4520 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4524 | base.head) { |
4521 | base.head) { |
4525 | switch (encoder->type) { |
4522 | switch (encoder->type) { |
4526 | case INTEL_OUTPUT_LVDS: |
4523 | case INTEL_OUTPUT_LVDS: |
4527 | has_panel = true; |
4524 | has_panel = true; |
4528 | has_lvds = true; |
4525 | has_lvds = true; |
4529 | break; |
4526 | break; |
4530 | case INTEL_OUTPUT_EDP: |
4527 | case INTEL_OUTPUT_EDP: |
4531 | has_panel = true; |
4528 | has_panel = true; |
4532 | if (intel_encoder_is_pch_edp(&encoder->base)) |
4529 | if (intel_encoder_is_pch_edp(&encoder->base)) |
4533 | has_pch_edp = true; |
4530 | has_pch_edp = true; |
4534 | else |
4531 | else |
4535 | has_cpu_edp = true; |
4532 | has_cpu_edp = true; |
4536 | break; |
4533 | break; |
4537 | } |
4534 | } |
4538 | } |
4535 | } |
4539 | 4536 | ||
4540 | if (HAS_PCH_IBX(dev)) { |
4537 | if (HAS_PCH_IBX(dev)) { |
4541 | has_ck505 = dev_priv->display_clock_mode; |
4538 | has_ck505 = dev_priv->display_clock_mode; |
4542 | can_ssc = has_ck505; |
4539 | can_ssc = has_ck505; |
4543 | } else { |
4540 | } else { |
4544 | has_ck505 = false; |
4541 | has_ck505 = false; |
4545 | can_ssc = true; |
4542 | can_ssc = true; |
4546 | } |
4543 | } |
4547 | 4544 | ||
4548 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", |
4545 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", |
4549 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, |
4546 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, |
4550 | has_ck505); |
4547 | has_ck505); |
4551 | 4548 | ||
4552 | /* Ironlake: try to setup display ref clock before DPLL |
4549 | /* Ironlake: try to setup display ref clock before DPLL |
4553 | * enabling. This is only under driver's control after |
4550 | * enabling. This is only under driver's control after |
4554 | * PCH B stepping, previous chipset stepping should be |
4551 | * PCH B stepping, previous chipset stepping should be |
4555 | * ignoring this setting. |
4552 | * ignoring this setting. |
4556 | */ |
4553 | */ |
4557 | temp = I915_READ(PCH_DREF_CONTROL); |
4554 | temp = I915_READ(PCH_DREF_CONTROL); |
4558 | /* Always enable nonspread source */ |
4555 | /* Always enable nonspread source */ |
4559 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
4556 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
4560 | 4557 | ||
4561 | if (has_ck505) |
4558 | if (has_ck505) |
4562 | temp |= DREF_NONSPREAD_CK505_ENABLE; |
4559 | temp |= DREF_NONSPREAD_CK505_ENABLE; |
4563 | else |
4560 | else |
4564 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
4561 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
4565 | 4562 | ||
4566 | if (has_panel) { |
4563 | if (has_panel) { |
4567 | temp &= ~DREF_SSC_SOURCE_MASK; |
4564 | temp &= ~DREF_SSC_SOURCE_MASK; |
4568 | temp |= DREF_SSC_SOURCE_ENABLE; |
4565 | temp |= DREF_SSC_SOURCE_ENABLE; |
4569 | 4566 | ||
4570 | /* SSC must be turned on before enabling the CPU output */ |
4567 | /* SSC must be turned on before enabling the CPU output */ |
4571 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
4568 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
4572 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
4569 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
4573 | temp |= DREF_SSC1_ENABLE; |
4570 | temp |= DREF_SSC1_ENABLE; |
4574 | } else |
4571 | } else |
4575 | temp &= ~DREF_SSC1_ENABLE; |
4572 | temp &= ~DREF_SSC1_ENABLE; |
4576 | 4573 | ||
4577 | /* Get SSC going before enabling the outputs */ |
4574 | /* Get SSC going before enabling the outputs */ |
4578 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4575 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4579 | POSTING_READ(PCH_DREF_CONTROL); |
4576 | POSTING_READ(PCH_DREF_CONTROL); |
4580 | udelay(200); |
4577 | udelay(200); |
4581 | 4578 | ||
4582 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4579 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4583 | 4580 | ||
4584 | /* Enable CPU source on CPU attached eDP */ |
4581 | /* Enable CPU source on CPU attached eDP */ |
4585 | if (has_cpu_edp) { |
4582 | if (has_cpu_edp) { |
4586 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
4583 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
4587 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
4584 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
4588 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
4585 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
4589 | } |
4586 | } |
4590 | else |
4587 | else |
4591 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
4588 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
4592 | } else |
4589 | } else |
4593 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
4590 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
4594 | 4591 | ||
4595 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4592 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4596 | POSTING_READ(PCH_DREF_CONTROL); |
4593 | POSTING_READ(PCH_DREF_CONTROL); |
4597 | udelay(200); |
4594 | udelay(200); |
4598 | } else { |
4595 | } else { |
4599 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
4596 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
4600 | 4597 | ||
4601 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4598 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4602 | 4599 | ||
4603 | /* Turn off CPU output */ |
4600 | /* Turn off CPU output */ |
4604 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
4601 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
4605 | 4602 | ||
4606 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4603 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4607 | POSTING_READ(PCH_DREF_CONTROL); |
4604 | POSTING_READ(PCH_DREF_CONTROL); |
4608 | udelay(200); |
4605 | udelay(200); |
4609 | 4606 | ||
4610 | /* Turn off the SSC source */ |
4607 | /* Turn off the SSC source */ |
4611 | temp &= ~DREF_SSC_SOURCE_MASK; |
4608 | temp &= ~DREF_SSC_SOURCE_MASK; |
4612 | temp |= DREF_SSC_SOURCE_DISABLE; |
4609 | temp |= DREF_SSC_SOURCE_DISABLE; |
4613 | 4610 | ||
4614 | /* Turn off SSC1 */ |
4611 | /* Turn off SSC1 */ |
4615 | temp &= ~ DREF_SSC1_ENABLE; |
4612 | temp &= ~ DREF_SSC1_ENABLE; |
4616 | 4613 | ||
4617 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4614 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4618 | POSTING_READ(PCH_DREF_CONTROL); |
4615 | POSTING_READ(PCH_DREF_CONTROL); |
4619 | udelay(200); |
4616 | udelay(200); |
4620 | } |
4617 | } |
4621 | } |
4618 | } |
4622 | 4619 | ||
4623 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4620 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4624 | { |
4621 | { |
4625 | struct drm_device *dev = crtc->dev; |
4622 | struct drm_device *dev = crtc->dev; |
4626 | struct drm_i915_private *dev_priv = dev->dev_private; |
4623 | struct drm_i915_private *dev_priv = dev->dev_private; |
4627 | struct intel_encoder *encoder; |
4624 | struct intel_encoder *encoder; |
4628 | struct intel_encoder *edp_encoder = NULL; |
4625 | struct intel_encoder *edp_encoder = NULL; |
4629 | int num_connectors = 0; |
4626 | int num_connectors = 0; |
4630 | bool is_lvds = false; |
4627 | bool is_lvds = false; |
4631 | 4628 | ||
4632 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4629 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4633 | switch (encoder->type) { |
4630 | switch (encoder->type) { |
4634 | case INTEL_OUTPUT_LVDS: |
4631 | case INTEL_OUTPUT_LVDS: |
4635 | is_lvds = true; |
4632 | is_lvds = true; |
4636 | break; |
4633 | break; |
4637 | case INTEL_OUTPUT_EDP: |
4634 | case INTEL_OUTPUT_EDP: |
4638 | edp_encoder = encoder; |
4635 | edp_encoder = encoder; |
4639 | break; |
4636 | break; |
4640 | } |
4637 | } |
4641 | num_connectors++; |
4638 | num_connectors++; |
4642 | } |
4639 | } |
4643 | 4640 | ||
4644 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4641 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4645 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4642 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4646 | dev_priv->lvds_ssc_freq); |
4643 | dev_priv->lvds_ssc_freq); |
4647 | return dev_priv->lvds_ssc_freq * 1000; |
4644 | return dev_priv->lvds_ssc_freq * 1000; |
4648 | } |
4645 | } |
4649 | 4646 | ||
4650 | return 120000; |
4647 | return 120000; |
4651 | } |
4648 | } |
4652 | 4649 | ||
4653 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
4650 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
4654 | struct drm_display_mode *adjusted_mode, |
4651 | struct drm_display_mode *adjusted_mode, |
4655 | bool dither) |
4652 | bool dither) |
4656 | { |
4653 | { |
4657 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
4654 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
4658 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4659 | int pipe = intel_crtc->pipe; |
4656 | int pipe = intel_crtc->pipe; |
4660 | uint32_t val; |
4657 | uint32_t val; |
4661 | 4658 | ||
4662 | val = I915_READ(PIPECONF(pipe)); |
4659 | val = I915_READ(PIPECONF(pipe)); |
4663 | 4660 | ||
4664 | val &= ~PIPE_BPC_MASK; |
4661 | val &= ~PIPE_BPC_MASK; |
4665 | switch (intel_crtc->bpp) { |
4662 | switch (intel_crtc->bpp) { |
4666 | case 18: |
4663 | case 18: |
4667 | val |= PIPE_6BPC; |
4664 | val |= PIPE_6BPC; |
4668 | break; |
4665 | break; |
4669 | case 24: |
4666 | case 24: |
4670 | val |= PIPE_8BPC; |
4667 | val |= PIPE_8BPC; |
4671 | break; |
4668 | break; |
4672 | case 30: |
4669 | case 30: |
4673 | val |= PIPE_10BPC; |
4670 | val |= PIPE_10BPC; |
4674 | break; |
4671 | break; |
4675 | case 36: |
4672 | case 36: |
4676 | val |= PIPE_12BPC; |
4673 | val |= PIPE_12BPC; |
4677 | break; |
4674 | break; |
4678 | default: |
4675 | default: |
4679 | val |= PIPE_8BPC; |
4676 | val |= PIPE_8BPC; |
4680 | break; |
4677 | break; |
4681 | } |
4678 | } |
4682 | 4679 | ||
4683 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); |
4680 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); |
4684 | if (dither) |
4681 | if (dither) |
4685 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
4682 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
4686 | 4683 | ||
4687 | val &= ~PIPECONF_INTERLACE_MASK; |
4684 | val &= ~PIPECONF_INTERLACE_MASK; |
4688 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
4685 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
4689 | val |= PIPECONF_INTERLACED_ILK; |
4686 | val |= PIPECONF_INTERLACED_ILK; |
4690 | else |
4687 | else |
4691 | val |= PIPECONF_PROGRESSIVE; |
4688 | val |= PIPECONF_PROGRESSIVE; |
4692 | 4689 | ||
4693 | I915_WRITE(PIPECONF(pipe), val); |
4690 | I915_WRITE(PIPECONF(pipe), val); |
4694 | POSTING_READ(PIPECONF(pipe)); |
4691 | POSTING_READ(PIPECONF(pipe)); |
4695 | } |
4692 | } |
4696 | 4693 | ||
4697 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
4694 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
4698 | struct drm_display_mode *adjusted_mode, |
4695 | struct drm_display_mode *adjusted_mode, |
4699 | intel_clock_t *clock, |
4696 | intel_clock_t *clock, |
4700 | bool *has_reduced_clock, |
4697 | bool *has_reduced_clock, |
4701 | intel_clock_t *reduced_clock) |
4698 | intel_clock_t *reduced_clock) |
4702 | { |
4699 | { |
4703 | struct drm_device *dev = crtc->dev; |
4700 | struct drm_device *dev = crtc->dev; |
4704 | struct drm_i915_private *dev_priv = dev->dev_private; |
4701 | struct drm_i915_private *dev_priv = dev->dev_private; |
4705 | struct intel_encoder *intel_encoder; |
4702 | struct intel_encoder *intel_encoder; |
4706 | int refclk; |
4703 | int refclk; |
4707 | const intel_limit_t *limit; |
4704 | const intel_limit_t *limit; |
4708 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
4705 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
4709 | 4706 | ||
4710 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4707 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4711 | switch (intel_encoder->type) { |
4708 | switch (intel_encoder->type) { |
4712 | case INTEL_OUTPUT_LVDS: |
4709 | case INTEL_OUTPUT_LVDS: |
4713 | is_lvds = true; |
4710 | is_lvds = true; |
4714 | break; |
4711 | break; |
4715 | case INTEL_OUTPUT_SDVO: |
4712 | case INTEL_OUTPUT_SDVO: |
4716 | case INTEL_OUTPUT_HDMI: |
4713 | case INTEL_OUTPUT_HDMI: |
4717 | is_sdvo = true; |
4714 | is_sdvo = true; |
4718 | if (intel_encoder->needs_tv_clock) |
4715 | if (intel_encoder->needs_tv_clock) |
4719 | is_tv = true; |
4716 | is_tv = true; |
4720 | break; |
4717 | break; |
4721 | case INTEL_OUTPUT_TVOUT: |
4718 | case INTEL_OUTPUT_TVOUT: |
4722 | is_tv = true; |
4719 | is_tv = true; |
4723 | break; |
4720 | break; |
4724 | } |
4721 | } |
4725 | } |
4722 | } |
4726 | 4723 | ||
4727 | refclk = ironlake_get_refclk(crtc); |
4724 | refclk = ironlake_get_refclk(crtc); |
4728 | 4725 | ||
4729 | /* |
4726 | /* |
4730 | * Returns a set of divisors for the desired target clock with the given |
4727 | * Returns a set of divisors for the desired target clock with the given |
4731 | * refclk, or FALSE. The returned values represent the clock equation: |
4728 | * refclk, or FALSE. The returned values represent the clock equation: |
4732 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4729 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4733 | */ |
4730 | */ |
4734 | limit = intel_limit(crtc, refclk); |
4731 | limit = intel_limit(crtc, refclk); |
4735 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4732 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4736 | clock); |
4733 | clock); |
4737 | if (!ret) |
4734 | if (!ret) |
4738 | return false; |
4735 | return false; |
4739 | 4736 | ||
4740 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4737 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4741 | /* |
4738 | /* |
4742 | * Ensure we match the reduced clock's P to the target clock. |
4739 | * Ensure we match the reduced clock's P to the target clock. |
4743 | * If the clocks don't match, we can't switch the display clock |
4740 | * If the clocks don't match, we can't switch the display clock |
4744 | * by using the FP0/FP1. In such case we will disable the LVDS |
4741 | * by using the FP0/FP1. In such case we will disable the LVDS |
4745 | * downclock feature. |
4742 | * downclock feature. |
4746 | */ |
4743 | */ |
4747 | *has_reduced_clock = limit->find_pll(limit, crtc, |
4744 | *has_reduced_clock = limit->find_pll(limit, crtc, |
4748 | dev_priv->lvds_downclock, |
4745 | dev_priv->lvds_downclock, |
4749 | refclk, |
4746 | refclk, |
4750 | clock, |
4747 | clock, |
4751 | reduced_clock); |
4748 | reduced_clock); |
4752 | } |
4749 | } |
4753 | 4750 | ||
4754 | if (is_sdvo && is_tv) |
4751 | if (is_sdvo && is_tv) |
4755 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
4752 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
4756 | 4753 | ||
4757 | return true; |
4754 | return true; |
4758 | } |
4755 | } |
4759 | 4756 | ||
4760 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
4757 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
4761 | struct drm_display_mode *mode, |
4758 | struct drm_display_mode *mode, |
4762 | struct drm_display_mode *adjusted_mode, |
4759 | struct drm_display_mode *adjusted_mode, |
4763 | int x, int y, |
4760 | int x, int y, |
4764 | struct drm_framebuffer *fb) |
4761 | struct drm_framebuffer *fb) |
4765 | { |
4762 | { |
4766 | struct drm_device *dev = crtc->dev; |
4763 | struct drm_device *dev = crtc->dev; |
4767 | struct drm_i915_private *dev_priv = dev->dev_private; |
4764 | struct drm_i915_private *dev_priv = dev->dev_private; |
4768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4769 | int pipe = intel_crtc->pipe; |
4766 | int pipe = intel_crtc->pipe; |
4770 | int plane = intel_crtc->plane; |
4767 | int plane = intel_crtc->plane; |
4771 | int num_connectors = 0; |
4768 | int num_connectors = 0; |
4772 | intel_clock_t clock, reduced_clock; |
4769 | intel_clock_t clock, reduced_clock; |
4773 | u32 dpll, fp = 0, fp2 = 0; |
4770 | u32 dpll, fp = 0, fp2 = 0; |
4774 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4771 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4775 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
4772 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
4776 | struct intel_encoder *encoder, *edp_encoder = NULL; |
4773 | struct intel_encoder *encoder, *edp_encoder = NULL; |
4777 | int ret; |
4774 | int ret; |
4778 | struct fdi_m_n m_n = {0}; |
4775 | struct fdi_m_n m_n = {0}; |
4779 | u32 temp; |
4776 | u32 temp; |
4780 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
4777 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
4781 | unsigned int pipe_bpp; |
4778 | unsigned int pipe_bpp; |
4782 | bool dither; |
4779 | bool dither; |
4783 | bool is_cpu_edp = false, is_pch_edp = false; |
4780 | bool is_cpu_edp = false, is_pch_edp = false; |
4784 | 4781 | ||
4785 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4782 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4786 | switch (encoder->type) { |
4783 | switch (encoder->type) { |
4787 | case INTEL_OUTPUT_LVDS: |
4784 | case INTEL_OUTPUT_LVDS: |
4788 | is_lvds = true; |
4785 | is_lvds = true; |
4789 | break; |
4786 | break; |
4790 | case INTEL_OUTPUT_SDVO: |
4787 | case INTEL_OUTPUT_SDVO: |
4791 | case INTEL_OUTPUT_HDMI: |
4788 | case INTEL_OUTPUT_HDMI: |
4792 | is_sdvo = true; |
4789 | is_sdvo = true; |
4793 | if (encoder->needs_tv_clock) |
4790 | if (encoder->needs_tv_clock) |
4794 | is_tv = true; |
4791 | is_tv = true; |
4795 | break; |
4792 | break; |
4796 | case INTEL_OUTPUT_TVOUT: |
4793 | case INTEL_OUTPUT_TVOUT: |
4797 | is_tv = true; |
4794 | is_tv = true; |
4798 | break; |
4795 | break; |
4799 | case INTEL_OUTPUT_ANALOG: |
4796 | case INTEL_OUTPUT_ANALOG: |
4800 | is_crt = true; |
4797 | is_crt = true; |
4801 | break; |
4798 | break; |
4802 | case INTEL_OUTPUT_DISPLAYPORT: |
4799 | case INTEL_OUTPUT_DISPLAYPORT: |
4803 | is_dp = true; |
4800 | is_dp = true; |
4804 | break; |
4801 | break; |
4805 | case INTEL_OUTPUT_EDP: |
4802 | case INTEL_OUTPUT_EDP: |
4806 | is_dp = true; |
4803 | is_dp = true; |
4807 | if (intel_encoder_is_pch_edp(&encoder->base)) |
4804 | if (intel_encoder_is_pch_edp(&encoder->base)) |
4808 | is_pch_edp = true; |
4805 | is_pch_edp = true; |
4809 | else |
4806 | else |
4810 | is_cpu_edp = true; |
4807 | is_cpu_edp = true; |
4811 | edp_encoder = encoder; |
4808 | edp_encoder = encoder; |
4812 | break; |
4809 | break; |
4813 | } |
4810 | } |
4814 | 4811 | ||
4815 | num_connectors++; |
4812 | num_connectors++; |
4816 | } |
4813 | } |
4817 | 4814 | ||
4818 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
4815 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
4819 | &has_reduced_clock, &reduced_clock); |
4816 | &has_reduced_clock, &reduced_clock); |
4820 | if (!ok) { |
4817 | if (!ok) { |
4821 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4818 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4822 | return -EINVAL; |
4819 | return -EINVAL; |
4823 | } |
4820 | } |
4824 | 4821 | ||
4825 | /* Ensure that the cursor is valid for the new mode before changing... */ |
4822 | /* Ensure that the cursor is valid for the new mode before changing... */ |
4826 | // intel_crtc_update_cursor(crtc, true); |
4823 | // intel_crtc_update_cursor(crtc, true); |
4827 | 4824 | ||
4828 | /* FDI link */ |
4825 | /* FDI link */ |
4829 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4826 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4830 | lane = 0; |
4827 | lane = 0; |
4831 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
4828 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
4832 | according to current link config */ |
4829 | according to current link config */ |
4833 | if (is_cpu_edp) { |
4830 | if (is_cpu_edp) { |
4834 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
4831 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
4835 | } else { |
4832 | } else { |
4836 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4833 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4837 | * each output octet as 10 bits. The actual frequency |
4834 | * each output octet as 10 bits. The actual frequency |
4838 | * is stored as a divider into a 100MHz clock, and the |
4835 | * is stored as a divider into a 100MHz clock, and the |
4839 | * mode pixel clock is stored in units of 1KHz. |
4836 | * mode pixel clock is stored in units of 1KHz. |
4840 | * Hence the bw of each lane in terms of the mode signal |
4837 | * Hence the bw of each lane in terms of the mode signal |
4841 | * is: |
4838 | * is: |
4842 | */ |
4839 | */ |
4843 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4840 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4844 | } |
4841 | } |
4845 | 4842 | ||
4846 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
4843 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
4847 | if (edp_encoder) |
4844 | if (edp_encoder) |
4848 | target_clock = intel_edp_target_clock(edp_encoder, mode); |
4845 | target_clock = intel_edp_target_clock(edp_encoder, mode); |
4849 | else if (is_dp) |
4846 | else if (is_dp) |
4850 | target_clock = mode->clock; |
4847 | target_clock = mode->clock; |
4851 | else |
4848 | else |
4852 | target_clock = adjusted_mode->clock; |
4849 | target_clock = adjusted_mode->clock; |
4853 | 4850 | ||
4854 | /* determine panel color depth */ |
4851 | /* determine panel color depth */ |
4855 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, |
4852 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, |
4856 | adjusted_mode); |
4853 | adjusted_mode); |
4857 | if (is_lvds && dev_priv->lvds_dither) |
4854 | if (is_lvds && dev_priv->lvds_dither) |
4858 | dither = true; |
4855 | dither = true; |
4859 | 4856 | ||
4860 | if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 && |
4857 | if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 && |
4861 | pipe_bpp != 36) { |
4858 | pipe_bpp != 36) { |
4862 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4859 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4863 | pipe_bpp); |
4860 | pipe_bpp); |
4864 | pipe_bpp = 24; |
4861 | pipe_bpp = 24; |
4865 | } |
4862 | } |
4866 | intel_crtc->bpp = pipe_bpp; |
4863 | intel_crtc->bpp = pipe_bpp; |
4867 | 4864 | ||
4868 | if (!lane) { |
4865 | if (!lane) { |
4869 | /* |
4866 | /* |
4870 | * Account for spread spectrum to avoid |
4867 | * Account for spread spectrum to avoid |
4871 | * oversubscribing the link. Max center spread |
4868 | * oversubscribing the link. Max center spread |
4872 | * is 2.5%; use 5% for safety's sake. |
4869 | * is 2.5%; use 5% for safety's sake. |
4873 | */ |
4870 | */ |
4874 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
4871 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
4875 | lane = bps / (link_bw * 8) + 1; |
4872 | lane = bps / (link_bw * 8) + 1; |
4876 | } |
4873 | } |
4877 | 4874 | ||
4878 | intel_crtc->fdi_lanes = lane; |
4875 | intel_crtc->fdi_lanes = lane; |
4879 | 4876 | ||
4880 | if (pixel_multiplier > 1) |
4877 | if (pixel_multiplier > 1) |
4881 | link_bw *= pixel_multiplier; |
4878 | link_bw *= pixel_multiplier; |
4882 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
4879 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
4883 | &m_n); |
4880 | &m_n); |
4884 | 4881 | ||
4885 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
4882 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
4886 | if (has_reduced_clock) |
4883 | if (has_reduced_clock) |
4887 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
4884 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
4888 | reduced_clock.m2; |
4885 | reduced_clock.m2; |
4889 | 4886 | ||
4890 | /* Enable autotuning of the PLL clock (if permissible) */ |
4887 | /* Enable autotuning of the PLL clock (if permissible) */ |
4891 | factor = 21; |
4888 | factor = 21; |
4892 | if (is_lvds) { |
4889 | if (is_lvds) { |
4893 | if ((intel_panel_use_ssc(dev_priv) && |
4890 | if ((intel_panel_use_ssc(dev_priv) && |
4894 | dev_priv->lvds_ssc_freq == 100) || |
4891 | dev_priv->lvds_ssc_freq == 100) || |
4895 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) |
4892 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) |
4896 | factor = 25; |
4893 | factor = 25; |
4897 | } else if (is_sdvo && is_tv) |
4894 | } else if (is_sdvo && is_tv) |
4898 | factor = 20; |
4895 | factor = 20; |
4899 | 4896 | ||
4900 | if (clock.m < factor * clock.n) |
4897 | if (clock.m < factor * clock.n) |
4901 | fp |= FP_CB_TUNE; |
4898 | fp |= FP_CB_TUNE; |
4902 | 4899 | ||
4903 | dpll = 0; |
4900 | dpll = 0; |
4904 | 4901 | ||
4905 | if (is_lvds) |
4902 | if (is_lvds) |
4906 | dpll |= DPLLB_MODE_LVDS; |
4903 | dpll |= DPLLB_MODE_LVDS; |
4907 | else |
4904 | else |
4908 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4905 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4909 | if (is_sdvo) { |
4906 | if (is_sdvo) { |
4910 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4907 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4911 | if (pixel_multiplier > 1) { |
4908 | if (pixel_multiplier > 1) { |
4912 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
4909 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
4913 | } |
4910 | } |
4914 | dpll |= DPLL_DVO_HIGH_SPEED; |
4911 | dpll |= DPLL_DVO_HIGH_SPEED; |
4915 | } |
4912 | } |
4916 | if (is_dp && !is_cpu_edp) |
4913 | if (is_dp && !is_cpu_edp) |
4917 | dpll |= DPLL_DVO_HIGH_SPEED; |
4914 | dpll |= DPLL_DVO_HIGH_SPEED; |
4918 | 4915 | ||
4919 | /* compute bitmask from p1 value */ |
4916 | /* compute bitmask from p1 value */ |
4920 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4917 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4921 | /* also FPA1 */ |
4918 | /* also FPA1 */ |
4922 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4919 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4923 | 4920 | ||
4924 | switch (clock.p2) { |
4921 | switch (clock.p2) { |
4925 | case 5: |
4922 | case 5: |
4926 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4923 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4927 | break; |
4924 | break; |
4928 | case 7: |
4925 | case 7: |
4929 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4926 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4930 | break; |
4927 | break; |
4931 | case 10: |
4928 | case 10: |
4932 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4929 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4933 | break; |
4930 | break; |
4934 | case 14: |
4931 | case 14: |
4935 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4932 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4936 | break; |
4933 | break; |
4937 | } |
4934 | } |
4938 | 4935 | ||
4939 | if (is_sdvo && is_tv) |
4936 | if (is_sdvo && is_tv) |
4940 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4937 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4941 | else if (is_tv) |
4938 | else if (is_tv) |
4942 | /* XXX: just matching BIOS for now */ |
4939 | /* XXX: just matching BIOS for now */ |
4943 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4940 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
4944 | dpll |= 3; |
4941 | dpll |= 3; |
4945 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4942 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4946 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4943 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4947 | else |
4944 | else |
4948 | dpll |= PLL_REF_INPUT_DREFCLK; |
4945 | dpll |= PLL_REF_INPUT_DREFCLK; |
4949 | 4946 | ||
4950 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
4947 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
4951 | drm_mode_debug_printmodeline(mode); |
4948 | drm_mode_debug_printmodeline(mode); |
4952 | 4949 | ||
4953 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own on |
4950 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own on |
4954 | * pre-Haswell/LPT generation */ |
4951 | * pre-Haswell/LPT generation */ |
4955 | if (HAS_PCH_LPT(dev)) { |
4952 | if (HAS_PCH_LPT(dev)) { |
4956 | DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n", |
4953 | DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n", |
4957 | pipe); |
4954 | pipe); |
4958 | } else if (!is_cpu_edp) { |
4955 | } else if (!is_cpu_edp) { |
4959 | struct intel_pch_pll *pll; |
4956 | struct intel_pch_pll *pll; |
4960 | 4957 | ||
4961 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
4958 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
4962 | if (pll == NULL) { |
4959 | if (pll == NULL) { |
4963 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", |
4960 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", |
4964 | pipe); |
4961 | pipe); |
4965 | return -EINVAL; |
4962 | return -EINVAL; |
4966 | } |
4963 | } |
4967 | } else |
4964 | } else |
4968 | intel_put_pch_pll(intel_crtc); |
4965 | intel_put_pch_pll(intel_crtc); |
4969 | 4966 | ||
4970 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4967 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4971 | * This is an exception to the general rule that mode_set doesn't turn |
4968 | * This is an exception to the general rule that mode_set doesn't turn |
4972 | * things on. |
4969 | * things on. |
4973 | */ |
4970 | */ |
4974 | if (is_lvds) { |
4971 | if (is_lvds) { |
4975 | temp = I915_READ(PCH_LVDS); |
4972 | temp = I915_READ(PCH_LVDS); |
4976 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
4973 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
4977 | if (HAS_PCH_CPT(dev)) { |
4974 | if (HAS_PCH_CPT(dev)) { |
4978 | temp &= ~PORT_TRANS_SEL_MASK; |
4975 | temp &= ~PORT_TRANS_SEL_MASK; |
4979 | temp |= PORT_TRANS_SEL_CPT(pipe); |
4976 | temp |= PORT_TRANS_SEL_CPT(pipe); |
4980 | } else { |
4977 | } else { |
4981 | if (pipe == 1) |
4978 | if (pipe == 1) |
4982 | temp |= LVDS_PIPEB_SELECT; |
4979 | temp |= LVDS_PIPEB_SELECT; |
4983 | else |
4980 | else |
4984 | temp &= ~LVDS_PIPEB_SELECT; |
4981 | temp &= ~LVDS_PIPEB_SELECT; |
4985 | } |
4982 | } |
4986 | 4983 | ||
4987 | /* set the corresponsding LVDS_BORDER bit */ |
4984 | /* set the corresponsding LVDS_BORDER bit */ |
4988 | temp |= dev_priv->lvds_border_bits; |
4985 | temp |= dev_priv->lvds_border_bits; |
4989 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4986 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4990 | * set the DPLLs for dual-channel mode or not. |
4987 | * set the DPLLs for dual-channel mode or not. |
4991 | */ |
4988 | */ |
4992 | if (clock.p2 == 7) |
4989 | if (clock.p2 == 7) |
4993 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
4990 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
4994 | else |
4991 | else |
4995 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
4992 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
4996 | 4993 | ||
4997 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
4994 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
4998 | * appropriately here, but we need to look more thoroughly into how |
4995 | * appropriately here, but we need to look more thoroughly into how |
4999 | * panels behave in the two modes. |
4996 | * panels behave in the two modes. |
5000 | */ |
4997 | */ |
5001 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
4998 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
5002 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
4999 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5003 | temp |= LVDS_HSYNC_POLARITY; |
5000 | temp |= LVDS_HSYNC_POLARITY; |
5004 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
5001 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
5005 | temp |= LVDS_VSYNC_POLARITY; |
5002 | temp |= LVDS_VSYNC_POLARITY; |
5006 | I915_WRITE(PCH_LVDS, temp); |
5003 | I915_WRITE(PCH_LVDS, temp); |
5007 | } |
5004 | } |
5008 | 5005 | ||
5009 | if (is_dp && !is_cpu_edp) { |
5006 | if (is_dp && !is_cpu_edp) { |
5010 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5007 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5011 | } else { |
5008 | } else { |
5012 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
5009 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
5013 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5010 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5014 | I915_WRITE(TRANSDATA_N1(pipe), 0); |
5011 | I915_WRITE(TRANSDATA_N1(pipe), 0); |
5015 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); |
5012 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); |
5016 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); |
5013 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); |
5017 | } |
5014 | } |
5018 | 5015 | ||
5019 | if (intel_crtc->pch_pll) { |
5016 | if (intel_crtc->pch_pll) { |
5020 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
5017 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
5021 | 5018 | ||
5022 | /* Wait for the clocks to stabilize. */ |
5019 | /* Wait for the clocks to stabilize. */ |
5023 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
5020 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
5024 | udelay(150); |
5021 | udelay(150); |
5025 | 5022 | ||
5026 | /* The pixel multiplier can only be updated once the |
5023 | /* The pixel multiplier can only be updated once the |
5027 | * DPLL is enabled and the clocks are stable. |
5024 | * DPLL is enabled and the clocks are stable. |
5028 | * |
5025 | * |
5029 | * So write it again. |
5026 | * So write it again. |
5030 | */ |
5027 | */ |
5031 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
5028 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
5032 | } |
5029 | } |
5033 | 5030 | ||
5034 | intel_crtc->lowfreq_avail = false; |
5031 | intel_crtc->lowfreq_avail = false; |
5035 | if (intel_crtc->pch_pll) { |
5032 | if (intel_crtc->pch_pll) { |
5036 | if (is_lvds && has_reduced_clock && i915_powersave) { |
5033 | if (is_lvds && has_reduced_clock && i915_powersave) { |
5037 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
5034 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
5038 | intel_crtc->lowfreq_avail = true; |
5035 | intel_crtc->lowfreq_avail = true; |
5039 | } else { |
5036 | } else { |
5040 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
5037 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
5041 | } |
5038 | } |
5042 | } |
5039 | } |
5043 | 5040 | ||
5044 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5041 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5045 | /* the chip adds 2 halflines automatically */ |
5042 | /* the chip adds 2 halflines automatically */ |
5046 | adjusted_mode->crtc_vtotal -= 1; |
5043 | adjusted_mode->crtc_vtotal -= 1; |
5047 | adjusted_mode->crtc_vblank_end -= 1; |
5044 | adjusted_mode->crtc_vblank_end -= 1; |
5048 | I915_WRITE(VSYNCSHIFT(pipe), |
5045 | I915_WRITE(VSYNCSHIFT(pipe), |
5049 | adjusted_mode->crtc_hsync_start |
5046 | adjusted_mode->crtc_hsync_start |
5050 | - adjusted_mode->crtc_htotal/2); |
5047 | - adjusted_mode->crtc_htotal/2); |
5051 | } else { |
5048 | } else { |
5052 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
5049 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
5053 | } |
5050 | } |
5054 | 5051 | ||
5055 | I915_WRITE(HTOTAL(pipe), |
5052 | I915_WRITE(HTOTAL(pipe), |
5056 | (adjusted_mode->crtc_hdisplay - 1) | |
5053 | (adjusted_mode->crtc_hdisplay - 1) | |
5057 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5054 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5058 | I915_WRITE(HBLANK(pipe), |
5055 | I915_WRITE(HBLANK(pipe), |
5059 | (adjusted_mode->crtc_hblank_start - 1) | |
5056 | (adjusted_mode->crtc_hblank_start - 1) | |
5060 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5057 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5061 | I915_WRITE(HSYNC(pipe), |
5058 | I915_WRITE(HSYNC(pipe), |
5062 | (adjusted_mode->crtc_hsync_start - 1) | |
5059 | (adjusted_mode->crtc_hsync_start - 1) | |
5063 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5060 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5064 | 5061 | ||
5065 | I915_WRITE(VTOTAL(pipe), |
5062 | I915_WRITE(VTOTAL(pipe), |
5066 | (adjusted_mode->crtc_vdisplay - 1) | |
5063 | (adjusted_mode->crtc_vdisplay - 1) | |
5067 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5064 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5068 | I915_WRITE(VBLANK(pipe), |
5065 | I915_WRITE(VBLANK(pipe), |
5069 | (adjusted_mode->crtc_vblank_start - 1) | |
5066 | (adjusted_mode->crtc_vblank_start - 1) | |
5070 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5067 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5071 | I915_WRITE(VSYNC(pipe), |
5068 | I915_WRITE(VSYNC(pipe), |
5072 | (adjusted_mode->crtc_vsync_start - 1) | |
5069 | (adjusted_mode->crtc_vsync_start - 1) | |
5073 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5070 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5074 | 5071 | ||
5075 | /* pipesrc controls the size that is scaled from, which should |
5072 | /* pipesrc controls the size that is scaled from, which should |
5076 | * always be the user's requested size. |
5073 | * always be the user's requested size. |
5077 | */ |
5074 | */ |
5078 | I915_WRITE(PIPESRC(pipe), |
5075 | I915_WRITE(PIPESRC(pipe), |
5079 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
5076 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
5080 | 5077 | ||
5081 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5078 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5082 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
5079 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
5083 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
5080 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
5084 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
5081 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
5085 | 5082 | ||
5086 | if (is_cpu_edp) |
5083 | if (is_cpu_edp) |
5087 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
5084 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
5088 | 5085 | ||
5089 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
5086 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
5090 | 5087 | ||
5091 | intel_wait_for_vblank(dev, pipe); |
5088 | intel_wait_for_vblank(dev, pipe); |
5092 | 5089 | ||
5093 | /* Set up the display plane register */ |
5090 | /* Set up the display plane register */ |
5094 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5091 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5095 | POSTING_READ(DSPCNTR(plane)); |
5092 | POSTING_READ(DSPCNTR(plane)); |
5096 | 5093 | ||
5097 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5094 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5098 | 5095 | ||
5099 | intel_update_watermarks(dev); |
5096 | intel_update_watermarks(dev); |
5100 | 5097 | ||
5101 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5098 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5102 | 5099 | ||
5103 | return ret; |
5100 | return ret; |
5104 | } |
5101 | } |
5105 | 5102 | ||
5106 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5103 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5107 | struct drm_display_mode *mode, |
5104 | struct drm_display_mode *mode, |
5108 | struct drm_display_mode *adjusted_mode, |
5105 | struct drm_display_mode *adjusted_mode, |
5109 | int x, int y, |
5106 | int x, int y, |
5110 | struct drm_framebuffer *fb) |
5107 | struct drm_framebuffer *fb) |
5111 | { |
5108 | { |
5112 | struct drm_device *dev = crtc->dev; |
5109 | struct drm_device *dev = crtc->dev; |
5113 | struct drm_i915_private *dev_priv = dev->dev_private; |
5110 | struct drm_i915_private *dev_priv = dev->dev_private; |
5114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5115 | int pipe = intel_crtc->pipe; |
5112 | int pipe = intel_crtc->pipe; |
5116 | int ret; |
5113 | int ret; |
5117 | 5114 | ||
5118 | drm_vblank_pre_modeset(dev, pipe); |
5115 | drm_vblank_pre_modeset(dev, pipe); |
5119 | 5116 | ||
5120 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
5117 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
5121 | x, y, fb); |
5118 | x, y, fb); |
5122 | drm_vblank_post_modeset(dev, pipe); |
5119 | drm_vblank_post_modeset(dev, pipe); |
5123 | 5120 | ||
5124 | return ret; |
5121 | return ret; |
5125 | } |
5122 | } |
5126 | 5123 | ||
5127 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5124 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5128 | int reg_eldv, uint32_t bits_eldv, |
5125 | int reg_eldv, uint32_t bits_eldv, |
5129 | int reg_elda, uint32_t bits_elda, |
5126 | int reg_elda, uint32_t bits_elda, |
5130 | int reg_edid) |
5127 | int reg_edid) |
5131 | { |
5128 | { |
5132 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5129 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5133 | uint8_t *eld = connector->eld; |
5130 | uint8_t *eld = connector->eld; |
5134 | uint32_t i; |
5131 | uint32_t i; |
5135 | 5132 | ||
5136 | i = I915_READ(reg_eldv); |
5133 | i = I915_READ(reg_eldv); |
5137 | i &= bits_eldv; |
5134 | i &= bits_eldv; |
5138 | 5135 | ||
5139 | if (!eld[0]) |
5136 | if (!eld[0]) |
5140 | return !i; |
5137 | return !i; |
5141 | 5138 | ||
5142 | if (!i) |
5139 | if (!i) |
5143 | return false; |
5140 | return false; |
5144 | 5141 | ||
5145 | i = I915_READ(reg_elda); |
5142 | i = I915_READ(reg_elda); |
5146 | i &= ~bits_elda; |
5143 | i &= ~bits_elda; |
5147 | I915_WRITE(reg_elda, i); |
5144 | I915_WRITE(reg_elda, i); |
5148 | 5145 | ||
5149 | for (i = 0; i < eld[2]; i++) |
5146 | for (i = 0; i < eld[2]; i++) |
5150 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
5147 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
5151 | return false; |
5148 | return false; |
5152 | 5149 | ||
5153 | return true; |
5150 | return true; |
5154 | } |
5151 | } |
5155 | 5152 | ||
5156 | static void g4x_write_eld(struct drm_connector *connector, |
5153 | static void g4x_write_eld(struct drm_connector *connector, |
5157 | struct drm_crtc *crtc) |
5154 | struct drm_crtc *crtc) |
5158 | { |
5155 | { |
5159 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5156 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5160 | uint8_t *eld = connector->eld; |
5157 | uint8_t *eld = connector->eld; |
5161 | uint32_t eldv; |
5158 | uint32_t eldv; |
5162 | uint32_t len; |
5159 | uint32_t len; |
5163 | uint32_t i; |
5160 | uint32_t i; |
5164 | 5161 | ||
5165 | i = I915_READ(G4X_AUD_VID_DID); |
5162 | i = I915_READ(G4X_AUD_VID_DID); |
5166 | 5163 | ||
5167 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
5164 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
5168 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
5165 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
5169 | else |
5166 | else |
5170 | eldv = G4X_ELDV_DEVCTG; |
5167 | eldv = G4X_ELDV_DEVCTG; |
5171 | 5168 | ||
5172 | if (intel_eld_uptodate(connector, |
5169 | if (intel_eld_uptodate(connector, |
5173 | G4X_AUD_CNTL_ST, eldv, |
5170 | G4X_AUD_CNTL_ST, eldv, |
5174 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
5171 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
5175 | G4X_HDMIW_HDMIEDID)) |
5172 | G4X_HDMIW_HDMIEDID)) |
5176 | return; |
5173 | return; |
5177 | 5174 | ||
5178 | i = I915_READ(G4X_AUD_CNTL_ST); |
5175 | i = I915_READ(G4X_AUD_CNTL_ST); |
5179 | i &= ~(eldv | G4X_ELD_ADDR); |
5176 | i &= ~(eldv | G4X_ELD_ADDR); |
5180 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
5177 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
5181 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
5178 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
5182 | 5179 | ||
5183 | if (!eld[0]) |
5180 | if (!eld[0]) |
5184 | return; |
5181 | return; |
5185 | 5182 | ||
5186 | len = min_t(uint8_t, eld[2], len); |
5183 | len = min_t(uint8_t, eld[2], len); |
5187 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5184 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5188 | for (i = 0; i < len; i++) |
5185 | for (i = 0; i < len; i++) |
5189 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
5186 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
5190 | 5187 | ||
5191 | i = I915_READ(G4X_AUD_CNTL_ST); |
5188 | i = I915_READ(G4X_AUD_CNTL_ST); |
5192 | i |= eldv; |
5189 | i |= eldv; |
5193 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
5190 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
5194 | } |
5191 | } |
5195 | 5192 | ||
5196 | static void haswell_write_eld(struct drm_connector *connector, |
5193 | static void haswell_write_eld(struct drm_connector *connector, |
5197 | struct drm_crtc *crtc) |
5194 | struct drm_crtc *crtc) |
5198 | { |
5195 | { |
5199 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5196 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5200 | uint8_t *eld = connector->eld; |
5197 | uint8_t *eld = connector->eld; |
5201 | struct drm_device *dev = crtc->dev; |
5198 | struct drm_device *dev = crtc->dev; |
5202 | uint32_t eldv; |
5199 | uint32_t eldv; |
5203 | uint32_t i; |
5200 | uint32_t i; |
5204 | int len; |
5201 | int len; |
5205 | int pipe = to_intel_crtc(crtc)->pipe; |
5202 | int pipe = to_intel_crtc(crtc)->pipe; |
5206 | int tmp; |
5203 | int tmp; |
5207 | 5204 | ||
5208 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
5205 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
5209 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
5206 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
5210 | int aud_config = HSW_AUD_CFG(pipe); |
5207 | int aud_config = HSW_AUD_CFG(pipe); |
5211 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
5208 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
5212 | 5209 | ||
5213 | 5210 | ||
5214 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
5211 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
5215 | 5212 | ||
5216 | /* Audio output enable */ |
5213 | /* Audio output enable */ |
5217 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
5214 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
5218 | tmp = I915_READ(aud_cntrl_st2); |
5215 | tmp = I915_READ(aud_cntrl_st2); |
5219 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
5216 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
5220 | I915_WRITE(aud_cntrl_st2, tmp); |
5217 | I915_WRITE(aud_cntrl_st2, tmp); |
5221 | 5218 | ||
5222 | /* Wait for 1 vertical blank */ |
5219 | /* Wait for 1 vertical blank */ |
5223 | intel_wait_for_vblank(dev, pipe); |
5220 | intel_wait_for_vblank(dev, pipe); |
5224 | 5221 | ||
5225 | /* Set ELD valid state */ |
5222 | /* Set ELD valid state */ |
5226 | tmp = I915_READ(aud_cntrl_st2); |
5223 | tmp = I915_READ(aud_cntrl_st2); |
5227 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); |
5224 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); |
5228 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
5225 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
5229 | I915_WRITE(aud_cntrl_st2, tmp); |
5226 | I915_WRITE(aud_cntrl_st2, tmp); |
5230 | tmp = I915_READ(aud_cntrl_st2); |
5227 | tmp = I915_READ(aud_cntrl_st2); |
5231 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); |
5228 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); |
5232 | 5229 | ||
5233 | /* Enable HDMI mode */ |
5230 | /* Enable HDMI mode */ |
5234 | tmp = I915_READ(aud_config); |
5231 | tmp = I915_READ(aud_config); |
5235 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); |
5232 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); |
5236 | /* clear N_programing_enable and N_value_index */ |
5233 | /* clear N_programing_enable and N_value_index */ |
5237 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
5234 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
5238 | I915_WRITE(aud_config, tmp); |
5235 | I915_WRITE(aud_config, tmp); |
5239 | 5236 | ||
5240 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
5237 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
5241 | 5238 | ||
5242 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
5239 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
5243 | 5240 | ||
5244 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5241 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5245 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
5242 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
5246 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
5243 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
5247 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5244 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5248 | } else |
5245 | } else |
5249 | I915_WRITE(aud_config, 0); |
5246 | I915_WRITE(aud_config, 0); |
5250 | 5247 | ||
5251 | if (intel_eld_uptodate(connector, |
5248 | if (intel_eld_uptodate(connector, |
5252 | aud_cntrl_st2, eldv, |
5249 | aud_cntrl_st2, eldv, |
5253 | aud_cntl_st, IBX_ELD_ADDRESS, |
5250 | aud_cntl_st, IBX_ELD_ADDRESS, |
5254 | hdmiw_hdmiedid)) |
5251 | hdmiw_hdmiedid)) |
5255 | return; |
5252 | return; |
5256 | 5253 | ||
5257 | i = I915_READ(aud_cntrl_st2); |
5254 | i = I915_READ(aud_cntrl_st2); |
5258 | i &= ~eldv; |
5255 | i &= ~eldv; |
5259 | I915_WRITE(aud_cntrl_st2, i); |
5256 | I915_WRITE(aud_cntrl_st2, i); |
5260 | 5257 | ||
5261 | if (!eld[0]) |
5258 | if (!eld[0]) |
5262 | return; |
5259 | return; |
5263 | 5260 | ||
5264 | i = I915_READ(aud_cntl_st); |
5261 | i = I915_READ(aud_cntl_st); |
5265 | i &= ~IBX_ELD_ADDRESS; |
5262 | i &= ~IBX_ELD_ADDRESS; |
5266 | I915_WRITE(aud_cntl_st, i); |
5263 | I915_WRITE(aud_cntl_st, i); |
5267 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
5264 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
5268 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
5265 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
5269 | 5266 | ||
5270 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
5267 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
5271 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5268 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5272 | for (i = 0; i < len; i++) |
5269 | for (i = 0; i < len; i++) |
5273 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
5270 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
5274 | 5271 | ||
5275 | i = I915_READ(aud_cntrl_st2); |
5272 | i = I915_READ(aud_cntrl_st2); |
5276 | i |= eldv; |
5273 | i |= eldv; |
5277 | I915_WRITE(aud_cntrl_st2, i); |
5274 | I915_WRITE(aud_cntrl_st2, i); |
5278 | 5275 | ||
5279 | } |
5276 | } |
5280 | 5277 | ||
5281 | static void ironlake_write_eld(struct drm_connector *connector, |
5278 | static void ironlake_write_eld(struct drm_connector *connector, |
5282 | struct drm_crtc *crtc) |
5279 | struct drm_crtc *crtc) |
5283 | { |
5280 | { |
5284 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5281 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
5285 | uint8_t *eld = connector->eld; |
5282 | uint8_t *eld = connector->eld; |
5286 | uint32_t eldv; |
5283 | uint32_t eldv; |
5287 | uint32_t i; |
5284 | uint32_t i; |
5288 | int len; |
5285 | int len; |
5289 | int hdmiw_hdmiedid; |
5286 | int hdmiw_hdmiedid; |
5290 | int aud_config; |
5287 | int aud_config; |
5291 | int aud_cntl_st; |
5288 | int aud_cntl_st; |
5292 | int aud_cntrl_st2; |
5289 | int aud_cntrl_st2; |
5293 | int pipe = to_intel_crtc(crtc)->pipe; |
5290 | int pipe = to_intel_crtc(crtc)->pipe; |
5294 | 5291 | ||
5295 | if (HAS_PCH_IBX(connector->dev)) { |
5292 | if (HAS_PCH_IBX(connector->dev)) { |
5296 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5293 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5297 | aud_config = IBX_AUD_CFG(pipe); |
5294 | aud_config = IBX_AUD_CFG(pipe); |
5298 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
5295 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
5299 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
5296 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
5300 | } else { |
5297 | } else { |
5301 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5298 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5302 | aud_config = CPT_AUD_CFG(pipe); |
5299 | aud_config = CPT_AUD_CFG(pipe); |
5303 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
5300 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
5304 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
5301 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
5305 | } |
5302 | } |
5306 | 5303 | ||
5307 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
5304 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
5308 | 5305 | ||
5309 | i = I915_READ(aud_cntl_st); |
5306 | i = I915_READ(aud_cntl_st); |
5310 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
5307 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
5311 | if (!i) { |
5308 | if (!i) { |
5312 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
5309 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
5313 | /* operate blindly on all ports */ |
5310 | /* operate blindly on all ports */ |
5314 | eldv = IBX_ELD_VALIDB; |
5311 | eldv = IBX_ELD_VALIDB; |
5315 | eldv |= IBX_ELD_VALIDB << 4; |
5312 | eldv |= IBX_ELD_VALIDB << 4; |
5316 | eldv |= IBX_ELD_VALIDB << 8; |
5313 | eldv |= IBX_ELD_VALIDB << 8; |
5317 | } else { |
5314 | } else { |
5318 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); |
5315 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); |
5319 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
5316 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
5320 | } |
5317 | } |
5321 | 5318 | ||
5322 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5319 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5323 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
5320 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
5324 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
5321 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
5325 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5322 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5326 | } else |
5323 | } else |
5327 | I915_WRITE(aud_config, 0); |
5324 | I915_WRITE(aud_config, 0); |
5328 | 5325 | ||
5329 | if (intel_eld_uptodate(connector, |
5326 | if (intel_eld_uptodate(connector, |
5330 | aud_cntrl_st2, eldv, |
5327 | aud_cntrl_st2, eldv, |
5331 | aud_cntl_st, IBX_ELD_ADDRESS, |
5328 | aud_cntl_st, IBX_ELD_ADDRESS, |
5332 | hdmiw_hdmiedid)) |
5329 | hdmiw_hdmiedid)) |
5333 | return; |
5330 | return; |
5334 | 5331 | ||
5335 | i = I915_READ(aud_cntrl_st2); |
5332 | i = I915_READ(aud_cntrl_st2); |
5336 | i &= ~eldv; |
5333 | i &= ~eldv; |
5337 | I915_WRITE(aud_cntrl_st2, i); |
5334 | I915_WRITE(aud_cntrl_st2, i); |
5338 | 5335 | ||
5339 | if (!eld[0]) |
5336 | if (!eld[0]) |
5340 | return; |
5337 | return; |
5341 | 5338 | ||
5342 | i = I915_READ(aud_cntl_st); |
5339 | i = I915_READ(aud_cntl_st); |
5343 | i &= ~IBX_ELD_ADDRESS; |
5340 | i &= ~IBX_ELD_ADDRESS; |
5344 | I915_WRITE(aud_cntl_st, i); |
5341 | I915_WRITE(aud_cntl_st, i); |
5345 | 5342 | ||
5346 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
5343 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
5347 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5344 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
5348 | for (i = 0; i < len; i++) |
5345 | for (i = 0; i < len; i++) |
5349 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
5346 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
5350 | 5347 | ||
5351 | i = I915_READ(aud_cntrl_st2); |
5348 | i = I915_READ(aud_cntrl_st2); |
5352 | i |= eldv; |
5349 | i |= eldv; |
5353 | I915_WRITE(aud_cntrl_st2, i); |
5350 | I915_WRITE(aud_cntrl_st2, i); |
5354 | } |
5351 | } |
5355 | 5352 | ||
5356 | void intel_write_eld(struct drm_encoder *encoder, |
5353 | void intel_write_eld(struct drm_encoder *encoder, |
5357 | struct drm_display_mode *mode) |
5354 | struct drm_display_mode *mode) |
5358 | { |
5355 | { |
5359 | struct drm_crtc *crtc = encoder->crtc; |
5356 | struct drm_crtc *crtc = encoder->crtc; |
5360 | struct drm_connector *connector; |
5357 | struct drm_connector *connector; |
5361 | struct drm_device *dev = encoder->dev; |
5358 | struct drm_device *dev = encoder->dev; |
5362 | struct drm_i915_private *dev_priv = dev->dev_private; |
5359 | struct drm_i915_private *dev_priv = dev->dev_private; |
5363 | 5360 | ||
5364 | connector = drm_select_eld(encoder, mode); |
5361 | connector = drm_select_eld(encoder, mode); |
5365 | if (!connector) |
5362 | if (!connector) |
5366 | return; |
5363 | return; |
5367 | 5364 | ||
5368 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5365 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5369 | connector->base.id, |
5366 | connector->base.id, |
5370 | drm_get_connector_name(connector), |
5367 | drm_get_connector_name(connector), |
5371 | connector->encoder->base.id, |
5368 | connector->encoder->base.id, |
5372 | drm_get_encoder_name(connector->encoder)); |
5369 | drm_get_encoder_name(connector->encoder)); |
5373 | 5370 | ||
5374 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
5371 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
5375 | 5372 | ||
5376 | if (dev_priv->display.write_eld) |
5373 | if (dev_priv->display.write_eld) |
5377 | dev_priv->display.write_eld(connector, crtc); |
5374 | dev_priv->display.write_eld(connector, crtc); |
5378 | } |
5375 | } |
5379 | 5376 | ||
5380 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5377 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5381 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
5378 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
5382 | { |
5379 | { |
5383 | struct drm_device *dev = crtc->dev; |
5380 | struct drm_device *dev = crtc->dev; |
5384 | struct drm_i915_private *dev_priv = dev->dev_private; |
5381 | struct drm_i915_private *dev_priv = dev->dev_private; |
5385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5386 | int palreg = PALETTE(intel_crtc->pipe); |
5383 | int palreg = PALETTE(intel_crtc->pipe); |
5387 | int i; |
5384 | int i; |
5388 | 5385 | ||
5389 | /* The clocks have to be on to load the palette. */ |
5386 | /* The clocks have to be on to load the palette. */ |
5390 | if (!crtc->enabled || !intel_crtc->active) |
5387 | if (!crtc->enabled || !intel_crtc->active) |
5391 | return; |
5388 | return; |
5392 | 5389 | ||
5393 | /* use legacy palette for Ironlake */ |
5390 | /* use legacy palette for Ironlake */ |
5394 | if (HAS_PCH_SPLIT(dev)) |
5391 | if (HAS_PCH_SPLIT(dev)) |
5395 | palreg = LGC_PALETTE(intel_crtc->pipe); |
5392 | palreg = LGC_PALETTE(intel_crtc->pipe); |
5396 | 5393 | ||
5397 | for (i = 0; i < 256; i++) { |
5394 | for (i = 0; i < 256; i++) { |
5398 | I915_WRITE(palreg + 4 * i, |
5395 | I915_WRITE(palreg + 4 * i, |
5399 | (intel_crtc->lut_r[i] << 16) | |
5396 | (intel_crtc->lut_r[i] << 16) | |
5400 | (intel_crtc->lut_g[i] << 8) | |
5397 | (intel_crtc->lut_g[i] << 8) | |
5401 | intel_crtc->lut_b[i]); |
5398 | intel_crtc->lut_b[i]); |
5402 | } |
5399 | } |
5403 | } |
5400 | } |
5404 | 5401 | ||
5405 | #if 0 |
5402 | #if 0 |
5406 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5403 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5407 | { |
5404 | { |
5408 | struct drm_device *dev = crtc->dev; |
5405 | struct drm_device *dev = crtc->dev; |
5409 | struct drm_i915_private *dev_priv = dev->dev_private; |
5406 | struct drm_i915_private *dev_priv = dev->dev_private; |
5410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5411 | bool visible = base != 0; |
5408 | bool visible = base != 0; |
5412 | u32 cntl; |
5409 | u32 cntl; |
5413 | 5410 | ||
5414 | if (intel_crtc->cursor_visible == visible) |
5411 | if (intel_crtc->cursor_visible == visible) |
5415 | return; |
5412 | return; |
5416 | 5413 | ||
5417 | cntl = I915_READ(_CURACNTR); |
5414 | cntl = I915_READ(_CURACNTR); |
5418 | if (visible) { |
5415 | if (visible) { |
5419 | /* On these chipsets we can only modify the base whilst |
5416 | /* On these chipsets we can only modify the base whilst |
5420 | * the cursor is disabled. |
5417 | * the cursor is disabled. |
5421 | */ |
5418 | */ |
5422 | I915_WRITE(_CURABASE, base); |
5419 | I915_WRITE(_CURABASE, base); |
5423 | 5420 | ||
5424 | cntl &= ~(CURSOR_FORMAT_MASK); |
5421 | cntl &= ~(CURSOR_FORMAT_MASK); |
5425 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
5422 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
5426 | cntl |= CURSOR_ENABLE | |
5423 | cntl |= CURSOR_ENABLE | |
5427 | CURSOR_GAMMA_ENABLE | |
5424 | CURSOR_GAMMA_ENABLE | |
5428 | CURSOR_FORMAT_ARGB; |
5425 | CURSOR_FORMAT_ARGB; |
5429 | } else |
5426 | } else |
5430 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
5427 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
5431 | I915_WRITE(_CURACNTR, cntl); |
5428 | I915_WRITE(_CURACNTR, cntl); |
5432 | 5429 | ||
5433 | intel_crtc->cursor_visible = visible; |
5430 | intel_crtc->cursor_visible = visible; |
5434 | } |
5431 | } |
5435 | 5432 | ||
5436 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
5433 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
5437 | { |
5434 | { |
5438 | struct drm_device *dev = crtc->dev; |
5435 | struct drm_device *dev = crtc->dev; |
5439 | struct drm_i915_private *dev_priv = dev->dev_private; |
5436 | struct drm_i915_private *dev_priv = dev->dev_private; |
5440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5441 | int pipe = intel_crtc->pipe; |
5438 | int pipe = intel_crtc->pipe; |
5442 | bool visible = base != 0; |
5439 | bool visible = base != 0; |
5443 | 5440 | ||
5444 | if (intel_crtc->cursor_visible != visible) { |
5441 | if (intel_crtc->cursor_visible != visible) { |
5445 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
5442 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
5446 | if (base) { |
5443 | if (base) { |
5447 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
5444 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
5448 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
5445 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
5449 | cntl |= pipe << 28; /* Connect to correct pipe */ |
5446 | cntl |= pipe << 28; /* Connect to correct pipe */ |
5450 | } else { |
5447 | } else { |
5451 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
5448 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
5452 | cntl |= CURSOR_MODE_DISABLE; |
5449 | cntl |= CURSOR_MODE_DISABLE; |
5453 | } |
5450 | } |
5454 | I915_WRITE(CURCNTR(pipe), cntl); |
5451 | I915_WRITE(CURCNTR(pipe), cntl); |
5455 | 5452 | ||
5456 | intel_crtc->cursor_visible = visible; |
5453 | intel_crtc->cursor_visible = visible; |
5457 | } |
5454 | } |
5458 | /* and commit changes on next vblank */ |
5455 | /* and commit changes on next vblank */ |
5459 | I915_WRITE(CURBASE(pipe), base); |
5456 | I915_WRITE(CURBASE(pipe), base); |
5460 | } |
5457 | } |
5461 | 5458 | ||
5462 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5459 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5463 | { |
5460 | { |
5464 | struct drm_device *dev = crtc->dev; |
5461 | struct drm_device *dev = crtc->dev; |
5465 | struct drm_i915_private *dev_priv = dev->dev_private; |
5462 | struct drm_i915_private *dev_priv = dev->dev_private; |
5466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5463 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5467 | int pipe = intel_crtc->pipe; |
5464 | int pipe = intel_crtc->pipe; |
5468 | bool visible = base != 0; |
5465 | bool visible = base != 0; |
5469 | 5466 | ||
5470 | if (intel_crtc->cursor_visible != visible) { |
5467 | if (intel_crtc->cursor_visible != visible) { |
5471 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
5468 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
5472 | if (base) { |
5469 | if (base) { |
5473 | cntl &= ~CURSOR_MODE; |
5470 | cntl &= ~CURSOR_MODE; |
5474 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
5471 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
5475 | } else { |
5472 | } else { |
5476 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
5473 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
5477 | cntl |= CURSOR_MODE_DISABLE; |
5474 | cntl |= CURSOR_MODE_DISABLE; |
5478 | } |
5475 | } |
5479 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
5476 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
5480 | 5477 | ||
5481 | intel_crtc->cursor_visible = visible; |
5478 | intel_crtc->cursor_visible = visible; |
5482 | } |
5479 | } |
5483 | /* and commit changes on next vblank */ |
5480 | /* and commit changes on next vblank */ |
5484 | I915_WRITE(CURBASE_IVB(pipe), base); |
5481 | I915_WRITE(CURBASE_IVB(pipe), base); |
5485 | } |
5482 | } |
5486 | 5483 | ||
5487 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
5484 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
5488 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5485 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5489 | bool on) |
5486 | bool on) |
5490 | { |
5487 | { |
5491 | struct drm_device *dev = crtc->dev; |
5488 | struct drm_device *dev = crtc->dev; |
5492 | struct drm_i915_private *dev_priv = dev->dev_private; |
5489 | struct drm_i915_private *dev_priv = dev->dev_private; |
5493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5494 | int pipe = intel_crtc->pipe; |
5491 | int pipe = intel_crtc->pipe; |
5495 | int x = intel_crtc->cursor_x; |
5492 | int x = intel_crtc->cursor_x; |
5496 | int y = intel_crtc->cursor_y; |
5493 | int y = intel_crtc->cursor_y; |
5497 | u32 base, pos; |
5494 | u32 base, pos; |
5498 | bool visible; |
5495 | bool visible; |
5499 | 5496 | ||
5500 | pos = 0; |
5497 | pos = 0; |
5501 | 5498 | ||
5502 | if (on && crtc->enabled && crtc->fb) { |
5499 | if (on && crtc->enabled && crtc->fb) { |
5503 | base = intel_crtc->cursor_addr; |
5500 | base = intel_crtc->cursor_addr; |
5504 | if (x > (int) crtc->fb->width) |
5501 | if (x > (int) crtc->fb->width) |
5505 | base = 0; |
5502 | base = 0; |
5506 | 5503 | ||
5507 | if (y > (int) crtc->fb->height) |
5504 | if (y > (int) crtc->fb->height) |
5508 | base = 0; |
5505 | base = 0; |
5509 | } else |
5506 | } else |
5510 | base = 0; |
5507 | base = 0; |
5511 | 5508 | ||
5512 | if (x < 0) { |
5509 | if (x < 0) { |
5513 | if (x + intel_crtc->cursor_width < 0) |
5510 | if (x + intel_crtc->cursor_width < 0) |
5514 | base = 0; |
5511 | base = 0; |
5515 | 5512 | ||
5516 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
5513 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
5517 | x = -x; |
5514 | x = -x; |
5518 | } |
5515 | } |
5519 | pos |= x << CURSOR_X_SHIFT; |
5516 | pos |= x << CURSOR_X_SHIFT; |
5520 | 5517 | ||
5521 | if (y < 0) { |
5518 | if (y < 0) { |
5522 | if (y + intel_crtc->cursor_height < 0) |
5519 | if (y + intel_crtc->cursor_height < 0) |
5523 | base = 0; |
5520 | base = 0; |
5524 | 5521 | ||
5525 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
5522 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
5526 | y = -y; |
5523 | y = -y; |
5527 | } |
5524 | } |
5528 | pos |= y << CURSOR_Y_SHIFT; |
5525 | pos |= y << CURSOR_Y_SHIFT; |
5529 | 5526 | ||
5530 | visible = base != 0; |
5527 | visible = base != 0; |
5531 | if (!visible && !intel_crtc->cursor_visible) |
5528 | if (!visible && !intel_crtc->cursor_visible) |
5532 | return; |
5529 | return; |
5533 | 5530 | ||
5534 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
5531 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
5535 | I915_WRITE(CURPOS_IVB(pipe), pos); |
5532 | I915_WRITE(CURPOS_IVB(pipe), pos); |
5536 | ivb_update_cursor(crtc, base); |
5533 | ivb_update_cursor(crtc, base); |
5537 | } else { |
5534 | } else { |
5538 | I915_WRITE(CURPOS(pipe), pos); |
5535 | I915_WRITE(CURPOS(pipe), pos); |
5539 | if (IS_845G(dev) || IS_I865G(dev)) |
5536 | if (IS_845G(dev) || IS_I865G(dev)) |
5540 | i845_update_cursor(crtc, base); |
5537 | i845_update_cursor(crtc, base); |
5541 | else |
5538 | else |
5542 | i9xx_update_cursor(crtc, base); |
5539 | i9xx_update_cursor(crtc, base); |
5543 | } |
5540 | } |
5544 | } |
5541 | } |
5545 | 5542 | ||
5546 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
5543 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
5547 | struct drm_file *file, |
5544 | struct drm_file *file, |
5548 | uint32_t handle, |
5545 | uint32_t handle, |
5549 | uint32_t width, uint32_t height) |
5546 | uint32_t width, uint32_t height) |
5550 | { |
5547 | { |
5551 | struct drm_device *dev = crtc->dev; |
5548 | struct drm_device *dev = crtc->dev; |
5552 | struct drm_i915_private *dev_priv = dev->dev_private; |
5549 | struct drm_i915_private *dev_priv = dev->dev_private; |
5553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5554 | struct drm_i915_gem_object *obj; |
5551 | struct drm_i915_gem_object *obj; |
5555 | uint32_t addr; |
5552 | uint32_t addr; |
5556 | int ret; |
5553 | int ret; |
5557 | 5554 | ||
5558 | /* if we want to turn off the cursor ignore width and height */ |
5555 | /* if we want to turn off the cursor ignore width and height */ |
5559 | if (!handle) { |
5556 | if (!handle) { |
5560 | DRM_DEBUG_KMS("cursor off\n"); |
5557 | DRM_DEBUG_KMS("cursor off\n"); |
5561 | addr = 0; |
5558 | addr = 0; |
5562 | obj = NULL; |
5559 | obj = NULL; |
5563 | mutex_lock(&dev->struct_mutex); |
5560 | mutex_lock(&dev->struct_mutex); |
5564 | goto finish; |
5561 | goto finish; |
5565 | } |
5562 | } |
5566 | 5563 | ||
5567 | /* Currently we only support 64x64 cursors */ |
5564 | /* Currently we only support 64x64 cursors */ |
5568 | if (width != 64 || height != 64) { |
5565 | if (width != 64 || height != 64) { |
5569 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
5566 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
5570 | return -EINVAL; |
5567 | return -EINVAL; |
5571 | } |
5568 | } |
5572 | 5569 | ||
5573 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
5570 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
5574 | if (&obj->base == NULL) |
5571 | if (&obj->base == NULL) |
5575 | return -ENOENT; |
5572 | return -ENOENT; |
5576 | 5573 | ||
5577 | if (obj->base.size < width * height * 4) { |
5574 | if (obj->base.size < width * height * 4) { |
5578 | DRM_ERROR("buffer is to small\n"); |
5575 | DRM_ERROR("buffer is to small\n"); |
5579 | ret = -ENOMEM; |
5576 | ret = -ENOMEM; |
5580 | goto fail; |
5577 | goto fail; |
5581 | } |
5578 | } |
5582 | 5579 | ||
5583 | /* we only need to pin inside GTT if cursor is non-phy */ |
5580 | /* we only need to pin inside GTT if cursor is non-phy */ |
5584 | mutex_lock(&dev->struct_mutex); |
5581 | mutex_lock(&dev->struct_mutex); |
5585 | if (!dev_priv->info->cursor_needs_physical) { |
5582 | if (!dev_priv->info->cursor_needs_physical) { |
5586 | if (obj->tiling_mode) { |
5583 | if (obj->tiling_mode) { |
5587 | DRM_ERROR("cursor cannot be tiled\n"); |
5584 | DRM_ERROR("cursor cannot be tiled\n"); |
5588 | ret = -EINVAL; |
5585 | ret = -EINVAL; |
5589 | goto fail_locked; |
5586 | goto fail_locked; |
5590 | } |
5587 | } |
5591 | 5588 | ||
5592 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
5589 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
5593 | if (ret) { |
5590 | if (ret) { |
5594 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
5591 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
5595 | goto fail_locked; |
5592 | goto fail_locked; |
5596 | } |
5593 | } |
5597 | 5594 | ||
5598 | ret = i915_gem_object_put_fence(obj); |
5595 | ret = i915_gem_object_put_fence(obj); |
5599 | if (ret) { |
5596 | if (ret) { |
5600 | DRM_ERROR("failed to release fence for cursor"); |
5597 | DRM_ERROR("failed to release fence for cursor"); |
5601 | goto fail_unpin; |
5598 | goto fail_unpin; |
5602 | } |
5599 | } |
5603 | 5600 | ||
5604 | addr = obj->gtt_offset; |
5601 | addr = obj->gtt_offset; |
5605 | } else { |
5602 | } else { |
5606 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
5603 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
5607 | ret = i915_gem_attach_phys_object(dev, obj, |
5604 | ret = i915_gem_attach_phys_object(dev, obj, |
5608 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
5605 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
5609 | align); |
5606 | align); |
5610 | if (ret) { |
5607 | if (ret) { |
5611 | DRM_ERROR("failed to attach phys object\n"); |
5608 | DRM_ERROR("failed to attach phys object\n"); |
5612 | goto fail_locked; |
5609 | goto fail_locked; |
5613 | } |
5610 | } |
5614 | addr = obj->phys_obj->handle->busaddr; |
5611 | addr = obj->phys_obj->handle->busaddr; |
5615 | } |
5612 | } |
5616 | 5613 | ||
5617 | if (IS_GEN2(dev)) |
5614 | if (IS_GEN2(dev)) |
5618 | I915_WRITE(CURSIZE, (height << 12) | width); |
5615 | I915_WRITE(CURSIZE, (height << 12) | width); |
5619 | 5616 | ||
5620 | finish: |
5617 | finish: |
5621 | if (intel_crtc->cursor_bo) { |
5618 | if (intel_crtc->cursor_bo) { |
5622 | if (dev_priv->info->cursor_needs_physical) { |
5619 | if (dev_priv->info->cursor_needs_physical) { |
5623 | if (intel_crtc->cursor_bo != obj) |
5620 | if (intel_crtc->cursor_bo != obj) |
5624 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
5621 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
5625 | } else |
5622 | } else |
5626 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
5623 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
5627 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
5624 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
5628 | } |
5625 | } |
5629 | 5626 | ||
5630 | mutex_unlock(&dev->struct_mutex); |
5627 | mutex_unlock(&dev->struct_mutex); |
5631 | 5628 | ||
5632 | intel_crtc->cursor_addr = addr; |
5629 | intel_crtc->cursor_addr = addr; |
5633 | intel_crtc->cursor_bo = obj; |
5630 | intel_crtc->cursor_bo = obj; |
5634 | intel_crtc->cursor_width = width; |
5631 | intel_crtc->cursor_width = width; |
5635 | intel_crtc->cursor_height = height; |
5632 | intel_crtc->cursor_height = height; |
5636 | 5633 | ||
5637 | // intel_crtc_update_cursor(crtc, true); |
5634 | // intel_crtc_update_cursor(crtc, true); |
5638 | 5635 | ||
5639 | return 0; |
5636 | return 0; |
5640 | fail_unpin: |
5637 | fail_unpin: |
5641 | i915_gem_object_unpin(obj); |
5638 | i915_gem_object_unpin(obj); |
5642 | fail_locked: |
5639 | fail_locked: |
5643 | mutex_unlock(&dev->struct_mutex); |
5640 | mutex_unlock(&dev->struct_mutex); |
5644 | fail: |
5641 | fail: |
5645 | drm_gem_object_unreference_unlocked(&obj->base); |
5642 | drm_gem_object_unreference_unlocked(&obj->base); |
5646 | return ret; |
5643 | return ret; |
5647 | } |
5644 | } |
5648 | 5645 | ||
5649 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
5646 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
5650 | { |
5647 | { |
5651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5652 | 5649 | ||
5653 | intel_crtc->cursor_x = x; |
5650 | intel_crtc->cursor_x = x; |
5654 | intel_crtc->cursor_y = y; |
5651 | intel_crtc->cursor_y = y; |
5655 | 5652 | ||
5656 | // intel_crtc_update_cursor(crtc, true); |
5653 | // intel_crtc_update_cursor(crtc, true); |
5657 | 5654 | ||
5658 | return 0; |
5655 | return 0; |
5659 | } |
5656 | } |
5660 | #endif |
5657 | #endif |
5661 | 5658 | ||
5662 | /** Sets the color ramps on behalf of RandR */ |
5659 | /** Sets the color ramps on behalf of RandR */ |
5663 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
5660 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
5664 | u16 blue, int regno) |
5661 | u16 blue, int regno) |
5665 | { |
5662 | { |
5666 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5667 | 5664 | ||
5668 | intel_crtc->lut_r[regno] = red >> 8; |
5665 | intel_crtc->lut_r[regno] = red >> 8; |
5669 | intel_crtc->lut_g[regno] = green >> 8; |
5666 | intel_crtc->lut_g[regno] = green >> 8; |
5670 | intel_crtc->lut_b[regno] = blue >> 8; |
5667 | intel_crtc->lut_b[regno] = blue >> 8; |
5671 | } |
5668 | } |
5672 | 5669 | ||
5673 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
5670 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
5674 | u16 *blue, int regno) |
5671 | u16 *blue, int regno) |
5675 | { |
5672 | { |
5676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5677 | 5674 | ||
5678 | *red = intel_crtc->lut_r[regno] << 8; |
5675 | *red = intel_crtc->lut_r[regno] << 8; |
5679 | *green = intel_crtc->lut_g[regno] << 8; |
5676 | *green = intel_crtc->lut_g[regno] << 8; |
5680 | *blue = intel_crtc->lut_b[regno] << 8; |
5677 | *blue = intel_crtc->lut_b[regno] << 8; |
5681 | } |
5678 | } |
5682 | 5679 | ||
5683 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
5680 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
5684 | u16 *blue, uint32_t start, uint32_t size) |
5681 | u16 *blue, uint32_t start, uint32_t size) |
5685 | { |
5682 | { |
5686 | int end = (start + size > 256) ? 256 : start + size, i; |
5683 | int end = (start + size > 256) ? 256 : start + size, i; |
5687 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5688 | 5685 | ||
5689 | for (i = start; i < end; i++) { |
5686 | for (i = start; i < end; i++) { |
5690 | intel_crtc->lut_r[i] = red[i] >> 8; |
5687 | intel_crtc->lut_r[i] = red[i] >> 8; |
5691 | intel_crtc->lut_g[i] = green[i] >> 8; |
5688 | intel_crtc->lut_g[i] = green[i] >> 8; |
5692 | intel_crtc->lut_b[i] = blue[i] >> 8; |
5689 | intel_crtc->lut_b[i] = blue[i] >> 8; |
5693 | } |
5690 | } |
5694 | 5691 | ||
5695 | intel_crtc_load_lut(crtc); |
5692 | intel_crtc_load_lut(crtc); |
5696 | } |
5693 | } |
5697 | 5694 | ||
5698 | /** |
5695 | /** |
5699 | * Get a pipe with a simple mode set on it for doing load-based monitor |
5696 | * Get a pipe with a simple mode set on it for doing load-based monitor |
5700 | * detection. |
5697 | * detection. |
5701 | * |
5698 | * |
5702 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
5699 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
5703 | * its requirements. The pipe will be connected to no other encoders. |
5700 | * its requirements. The pipe will be connected to no other encoders. |
5704 | * |
5701 | * |
5705 | * Currently this code will only succeed if there is a pipe with no encoders |
5702 | * Currently this code will only succeed if there is a pipe with no encoders |
5706 | * configured for it. In the future, it could choose to temporarily disable |
5703 | * configured for it. In the future, it could choose to temporarily disable |
5707 | * some outputs to free up a pipe for its use. |
5704 | * some outputs to free up a pipe for its use. |
5708 | * |
5705 | * |
5709 | * \return crtc, or NULL if no pipes are available. |
5706 | * \return crtc, or NULL if no pipes are available. |
5710 | */ |
5707 | */ |
5711 | 5708 | ||
5712 | /* VESA 640x480x72Hz mode to set on the pipe */ |
5709 | /* VESA 640x480x72Hz mode to set on the pipe */ |
5713 | static struct drm_display_mode load_detect_mode = { |
5710 | static struct drm_display_mode load_detect_mode = { |
5714 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
5711 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
5715 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
5712 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
5716 | }; |
5713 | }; |
5717 | 5714 | ||
5718 | static struct drm_framebuffer * |
5715 | static struct drm_framebuffer * |
5719 | intel_framebuffer_create(struct drm_device *dev, |
5716 | intel_framebuffer_create(struct drm_device *dev, |
5720 | struct drm_mode_fb_cmd2 *mode_cmd, |
5717 | struct drm_mode_fb_cmd2 *mode_cmd, |
5721 | struct drm_i915_gem_object *obj) |
5718 | struct drm_i915_gem_object *obj) |
5722 | { |
5719 | { |
5723 | struct intel_framebuffer *intel_fb; |
5720 | struct intel_framebuffer *intel_fb; |
5724 | int ret; |
5721 | int ret; |
5725 | 5722 | ||
5726 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5723 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5727 | if (!intel_fb) { |
5724 | if (!intel_fb) { |
5728 | drm_gem_object_unreference_unlocked(&obj->base); |
5725 | drm_gem_object_unreference_unlocked(&obj->base); |
5729 | return ERR_PTR(-ENOMEM); |
5726 | return ERR_PTR(-ENOMEM); |
5730 | } |
5727 | } |
5731 | 5728 | ||
5732 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
5729 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
5733 | if (ret) { |
5730 | if (ret) { |
5734 | drm_gem_object_unreference_unlocked(&obj->base); |
5731 | drm_gem_object_unreference_unlocked(&obj->base); |
5735 | kfree(intel_fb); |
5732 | kfree(intel_fb); |
5736 | return ERR_PTR(ret); |
5733 | return ERR_PTR(ret); |
5737 | } |
5734 | } |
5738 | 5735 | ||
5739 | return &intel_fb->base; |
5736 | return &intel_fb->base; |
5740 | } |
5737 | } |
5741 | 5738 | ||
5742 | static u32 |
5739 | static u32 |
5743 | intel_framebuffer_pitch_for_width(int width, int bpp) |
5740 | intel_framebuffer_pitch_for_width(int width, int bpp) |
5744 | { |
5741 | { |
5745 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
5742 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
5746 | return ALIGN(pitch, 64); |
5743 | return ALIGN(pitch, 64); |
5747 | } |
5744 | } |
5748 | 5745 | ||
5749 | static u32 |
5746 | static u32 |
5750 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
5747 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
5751 | { |
5748 | { |
5752 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
5749 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
5753 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
5750 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
5754 | } |
5751 | } |
5755 | 5752 | ||
5756 | static struct drm_framebuffer * |
5753 | static struct drm_framebuffer * |
5757 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
5754 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
5758 | struct drm_display_mode *mode, |
5755 | struct drm_display_mode *mode, |
5759 | int depth, int bpp) |
5756 | int depth, int bpp) |
5760 | { |
5757 | { |
5761 | struct drm_i915_gem_object *obj; |
5758 | struct drm_i915_gem_object *obj; |
5762 | struct drm_mode_fb_cmd2 mode_cmd; |
5759 | struct drm_mode_fb_cmd2 mode_cmd; |
5763 | 5760 | ||
5764 | // obj = i915_gem_alloc_object(dev, |
5761 | // obj = i915_gem_alloc_object(dev, |
5765 | // intel_framebuffer_size_for_mode(mode, bpp)); |
5762 | // intel_framebuffer_size_for_mode(mode, bpp)); |
5766 | // if (obj == NULL) |
5763 | // if (obj == NULL) |
5767 | return ERR_PTR(-ENOMEM); |
5764 | return ERR_PTR(-ENOMEM); |
5768 | 5765 | ||
5769 | // mode_cmd.width = mode->hdisplay; |
5766 | // mode_cmd.width = mode->hdisplay; |
5770 | // mode_cmd.height = mode->vdisplay; |
5767 | // mode_cmd.height = mode->vdisplay; |
5771 | // mode_cmd.depth = depth; |
5768 | // mode_cmd.depth = depth; |
5772 | // mode_cmd.bpp = bpp; |
5769 | // mode_cmd.bpp = bpp; |
5773 | // mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); |
5770 | // mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); |
5774 | 5771 | ||
5775 | // return intel_framebuffer_create(dev, &mode_cmd, obj); |
5772 | // return intel_framebuffer_create(dev, &mode_cmd, obj); |
5776 | } |
5773 | } |
5777 | 5774 | ||
5778 | static struct drm_framebuffer * |
5775 | static struct drm_framebuffer * |
5779 | mode_fits_in_fbdev(struct drm_device *dev, |
5776 | mode_fits_in_fbdev(struct drm_device *dev, |
5780 | struct drm_display_mode *mode) |
5777 | struct drm_display_mode *mode) |
5781 | { |
5778 | { |
5782 | struct drm_i915_private *dev_priv = dev->dev_private; |
5779 | struct drm_i915_private *dev_priv = dev->dev_private; |
5783 | struct drm_i915_gem_object *obj; |
5780 | struct drm_i915_gem_object *obj; |
5784 | struct drm_framebuffer *fb; |
5781 | struct drm_framebuffer *fb; |
5785 | 5782 | ||
5786 | // if (dev_priv->fbdev == NULL) |
5783 | // if (dev_priv->fbdev == NULL) |
5787 | // return NULL; |
5784 | // return NULL; |
5788 | 5785 | ||
5789 | // obj = dev_priv->fbdev->ifb.obj; |
5786 | // obj = dev_priv->fbdev->ifb.obj; |
5790 | // if (obj == NULL) |
5787 | // if (obj == NULL) |
5791 | return NULL; |
5788 | return NULL; |
5792 | 5789 | ||
5793 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
5790 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
5794 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5791 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5795 | fb->bits_per_pixel)) |
5792 | fb->bits_per_pixel)) |
5796 | // return NULL; |
5793 | // return NULL; |
5797 | 5794 | ||
5798 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
5795 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
5799 | return NULL; |
5796 | return NULL; |
5800 | 5797 | ||
5801 | // return fb; |
5798 | // return fb; |
5802 | } |
5799 | } |
5803 | 5800 | ||
5804 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
5801 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
5805 | struct drm_display_mode *mode, |
5802 | struct drm_display_mode *mode, |
5806 | struct intel_load_detect_pipe *old) |
5803 | struct intel_load_detect_pipe *old) |
5807 | { |
5804 | { |
5808 | struct intel_crtc *intel_crtc; |
5805 | struct intel_crtc *intel_crtc; |
5809 | struct intel_encoder *intel_encoder = |
5806 | struct intel_encoder *intel_encoder = |
5810 | intel_attached_encoder(connector); |
5807 | intel_attached_encoder(connector); |
5811 | struct drm_crtc *possible_crtc; |
5808 | struct drm_crtc *possible_crtc; |
5812 | struct drm_encoder *encoder = &intel_encoder->base; |
5809 | struct drm_encoder *encoder = &intel_encoder->base; |
5813 | struct drm_crtc *crtc = NULL; |
5810 | struct drm_crtc *crtc = NULL; |
5814 | struct drm_device *dev = encoder->dev; |
5811 | struct drm_device *dev = encoder->dev; |
5815 | struct drm_framebuffer *fb; |
5812 | struct drm_framebuffer *fb; |
5816 | int i = -1; |
5813 | int i = -1; |
5817 | 5814 | ||
5818 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5815 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5819 | connector->base.id, drm_get_connector_name(connector), |
5816 | connector->base.id, drm_get_connector_name(connector), |
5820 | encoder->base.id, drm_get_encoder_name(encoder)); |
5817 | encoder->base.id, drm_get_encoder_name(encoder)); |
5821 | 5818 | ||
5822 | /* |
5819 | /* |
5823 | * Algorithm gets a little messy: |
5820 | * Algorithm gets a little messy: |
5824 | * |
5821 | * |
5825 | * - if the connector already has an assigned crtc, use it (but make |
5822 | * - if the connector already has an assigned crtc, use it (but make |
5826 | * sure it's on first) |
5823 | * sure it's on first) |
5827 | * |
5824 | * |
5828 | * - try to find the first unused crtc that can drive this connector, |
5825 | * - try to find the first unused crtc that can drive this connector, |
5829 | * and use that if we find one |
5826 | * and use that if we find one |
5830 | */ |
5827 | */ |
5831 | 5828 | ||
5832 | /* See if we already have a CRTC for this connector */ |
5829 | /* See if we already have a CRTC for this connector */ |
5833 | if (encoder->crtc) { |
5830 | if (encoder->crtc) { |
5834 | crtc = encoder->crtc; |
5831 | crtc = encoder->crtc; |
5835 | 5832 | ||
5836 | old->dpms_mode = connector->dpms; |
5833 | old->dpms_mode = connector->dpms; |
5837 | old->load_detect_temp = false; |
5834 | old->load_detect_temp = false; |
5838 | 5835 | ||
5839 | /* Make sure the crtc and connector are running */ |
5836 | /* Make sure the crtc and connector are running */ |
5840 | if (connector->dpms != DRM_MODE_DPMS_ON) |
5837 | if (connector->dpms != DRM_MODE_DPMS_ON) |
5841 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
5838 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
5842 | 5839 | ||
5843 | return true; |
5840 | return true; |
5844 | } |
5841 | } |
5845 | 5842 | ||
5846 | /* Find an unused one (if possible) */ |
5843 | /* Find an unused one (if possible) */ |
5847 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
5844 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
5848 | i++; |
5845 | i++; |
5849 | if (!(encoder->possible_crtcs & (1 << i))) |
5846 | if (!(encoder->possible_crtcs & (1 << i))) |
5850 | continue; |
5847 | continue; |
5851 | if (!possible_crtc->enabled) { |
5848 | if (!possible_crtc->enabled) { |
5852 | crtc = possible_crtc; |
5849 | crtc = possible_crtc; |
5853 | break; |
5850 | break; |
5854 | } |
5851 | } |
5855 | } |
5852 | } |
5856 | 5853 | ||
5857 | /* |
5854 | /* |
5858 | * If we didn't find an unused CRTC, don't use any. |
5855 | * If we didn't find an unused CRTC, don't use any. |
5859 | */ |
5856 | */ |
5860 | if (!crtc) { |
5857 | if (!crtc) { |
5861 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
5858 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
5862 | return false; |
5859 | return false; |
5863 | } |
5860 | } |
5864 | 5861 | ||
5865 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
5862 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
5866 | to_intel_connector(connector)->new_encoder = intel_encoder; |
5863 | to_intel_connector(connector)->new_encoder = intel_encoder; |
5867 | 5864 | ||
5868 | intel_crtc = to_intel_crtc(crtc); |
5865 | intel_crtc = to_intel_crtc(crtc); |
5869 | old->dpms_mode = connector->dpms; |
5866 | old->dpms_mode = connector->dpms; |
5870 | old->load_detect_temp = true; |
5867 | old->load_detect_temp = true; |
5871 | old->release_fb = NULL; |
5868 | old->release_fb = NULL; |
5872 | 5869 | ||
5873 | if (!mode) |
5870 | if (!mode) |
5874 | mode = &load_detect_mode; |
5871 | mode = &load_detect_mode; |
5875 | 5872 | ||
5876 | /* We need a framebuffer large enough to accommodate all accesses |
5873 | /* We need a framebuffer large enough to accommodate all accesses |
5877 | * that the plane may generate whilst we perform load detection. |
5874 | * that the plane may generate whilst we perform load detection. |
5878 | * We can not rely on the fbcon either being present (we get called |
5875 | * We can not rely on the fbcon either being present (we get called |
5879 | * during its initialisation to detect all boot displays, or it may |
5876 | * during its initialisation to detect all boot displays, or it may |
5880 | * not even exist) or that it is large enough to satisfy the |
5877 | * not even exist) or that it is large enough to satisfy the |
5881 | * requested mode. |
5878 | * requested mode. |
5882 | */ |
5879 | */ |
5883 | fb = mode_fits_in_fbdev(dev, mode); |
5880 | fb = mode_fits_in_fbdev(dev, mode); |
5884 | if (fb == NULL) { |
5881 | if (fb == NULL) { |
5885 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
5882 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
5886 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
5883 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
5887 | old->release_fb = fb; |
5884 | old->release_fb = fb; |
5888 | } else |
5885 | } else |
5889 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
5886 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
5890 | if (IS_ERR(fb)) { |
5887 | if (IS_ERR(fb)) { |
5891 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
5888 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
5892 | goto fail; |
5889 | goto fail; |
5893 | } |
5890 | } |
5894 | 5891 | ||
5895 | if (!intel_set_mode(crtc, mode, 0, 0, fb)) { |
5892 | if (!intel_set_mode(crtc, mode, 0, 0, fb)) { |
5896 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
5893 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
5897 | if (old->release_fb) |
5894 | if (old->release_fb) |
5898 | old->release_fb->funcs->destroy(old->release_fb); |
5895 | old->release_fb->funcs->destroy(old->release_fb); |
5899 | goto fail; |
5896 | goto fail; |
5900 | } |
5897 | } |
5901 | 5898 | ||
5902 | /* let the connector get through one full cycle before testing */ |
5899 | /* let the connector get through one full cycle before testing */ |
5903 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5900 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5904 | 5901 | ||
5905 | return true; |
5902 | return true; |
5906 | fail: |
5903 | fail: |
5907 | connector->encoder = NULL; |
5904 | connector->encoder = NULL; |
5908 | encoder->crtc = NULL; |
5905 | encoder->crtc = NULL; |
5909 | return false; |
5906 | return false; |
5910 | } |
5907 | } |
5911 | 5908 | ||
5912 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
5909 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
5913 | struct intel_load_detect_pipe *old) |
5910 | struct intel_load_detect_pipe *old) |
5914 | { |
5911 | { |
5915 | struct intel_encoder *intel_encoder = |
5912 | struct intel_encoder *intel_encoder = |
5916 | intel_attached_encoder(connector); |
5913 | intel_attached_encoder(connector); |
5917 | struct drm_encoder *encoder = &intel_encoder->base; |
5914 | struct drm_encoder *encoder = &intel_encoder->base; |
5918 | 5915 | ||
5919 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5916 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5920 | connector->base.id, drm_get_connector_name(connector), |
5917 | connector->base.id, drm_get_connector_name(connector), |
5921 | encoder->base.id, drm_get_encoder_name(encoder)); |
5918 | encoder->base.id, drm_get_encoder_name(encoder)); |
5922 | 5919 | ||
5923 | if (old->load_detect_temp) { |
5920 | if (old->load_detect_temp) { |
5924 | struct drm_crtc *crtc = encoder->crtc; |
5921 | struct drm_crtc *crtc = encoder->crtc; |
5925 | 5922 | ||
5926 | to_intel_connector(connector)->new_encoder = NULL; |
5923 | to_intel_connector(connector)->new_encoder = NULL; |
5927 | intel_encoder->new_crtc = NULL; |
5924 | intel_encoder->new_crtc = NULL; |
5928 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
5925 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
5929 | 5926 | ||
5930 | if (old->release_fb) |
5927 | if (old->release_fb) |
5931 | old->release_fb->funcs->destroy(old->release_fb); |
5928 | old->release_fb->funcs->destroy(old->release_fb); |
5932 | 5929 | ||
5933 | return; |
5930 | return; |
5934 | } |
5931 | } |
5935 | 5932 | ||
5936 | /* Switch crtc and encoder back off if necessary */ |
5933 | /* Switch crtc and encoder back off if necessary */ |
5937 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
5934 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
5938 | connector->funcs->dpms(connector, old->dpms_mode); |
5935 | connector->funcs->dpms(connector, old->dpms_mode); |
5939 | } |
5936 | } |
5940 | 5937 | ||
5941 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
5938 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
5942 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
5939 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
5943 | { |
5940 | { |
5944 | struct drm_i915_private *dev_priv = dev->dev_private; |
5941 | struct drm_i915_private *dev_priv = dev->dev_private; |
5945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5946 | int pipe = intel_crtc->pipe; |
5943 | int pipe = intel_crtc->pipe; |
5947 | u32 dpll = I915_READ(DPLL(pipe)); |
5944 | u32 dpll = I915_READ(DPLL(pipe)); |
5948 | u32 fp; |
5945 | u32 fp; |
5949 | intel_clock_t clock; |
5946 | intel_clock_t clock; |
5950 | 5947 | ||
5951 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
5948 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
5952 | fp = I915_READ(FP0(pipe)); |
5949 | fp = I915_READ(FP0(pipe)); |
5953 | else |
5950 | else |
5954 | fp = I915_READ(FP1(pipe)); |
5951 | fp = I915_READ(FP1(pipe)); |
5955 | 5952 | ||
5956 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
5953 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
5957 | if (IS_PINEVIEW(dev)) { |
5954 | if (IS_PINEVIEW(dev)) { |
5958 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
5955 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
5959 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
5956 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
5960 | } else { |
5957 | } else { |
5961 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
5958 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
5962 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
5959 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
5963 | } |
5960 | } |
5964 | 5961 | ||
5965 | if (!IS_GEN2(dev)) { |
5962 | if (!IS_GEN2(dev)) { |
5966 | if (IS_PINEVIEW(dev)) |
5963 | if (IS_PINEVIEW(dev)) |
5967 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
5964 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
5968 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
5965 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
5969 | else |
5966 | else |
5970 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
5967 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
5971 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5968 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5972 | 5969 | ||
5973 | switch (dpll & DPLL_MODE_MASK) { |
5970 | switch (dpll & DPLL_MODE_MASK) { |
5974 | case DPLLB_MODE_DAC_SERIAL: |
5971 | case DPLLB_MODE_DAC_SERIAL: |
5975 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
5972 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
5976 | 5 : 10; |
5973 | 5 : 10; |
5977 | break; |
5974 | break; |
5978 | case DPLLB_MODE_LVDS: |
5975 | case DPLLB_MODE_LVDS: |
5979 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
5976 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
5980 | 7 : 14; |
5977 | 7 : 14; |
5981 | break; |
5978 | break; |
5982 | default: |
5979 | default: |
5983 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
5980 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
5984 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5981 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5985 | return 0; |
5982 | return 0; |
5986 | } |
5983 | } |
5987 | 5984 | ||
5988 | /* XXX: Handle the 100Mhz refclk */ |
5985 | /* XXX: Handle the 100Mhz refclk */ |
5989 | intel_clock(dev, 96000, &clock); |
5986 | intel_clock(dev, 96000, &clock); |
5990 | } else { |
5987 | } else { |
5991 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
5988 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
5992 | 5989 | ||
5993 | if (is_lvds) { |
5990 | if (is_lvds) { |
5994 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
5991 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
5995 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5992 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5996 | clock.p2 = 14; |
5993 | clock.p2 = 14; |
5997 | 5994 | ||
5998 | if ((dpll & PLL_REF_INPUT_MASK) == |
5995 | if ((dpll & PLL_REF_INPUT_MASK) == |
5999 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
5996 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
6000 | /* XXX: might not be 66MHz */ |
5997 | /* XXX: might not be 66MHz */ |
6001 | intel_clock(dev, 66000, &clock); |
5998 | intel_clock(dev, 66000, &clock); |
6002 | } else |
5999 | } else |
6003 | intel_clock(dev, 48000, &clock); |
6000 | intel_clock(dev, 48000, &clock); |
6004 | } else { |
6001 | } else { |
6005 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
6002 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
6006 | clock.p1 = 2; |
6003 | clock.p1 = 2; |
6007 | else { |
6004 | else { |
6008 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
6005 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
6009 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
6006 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
6010 | } |
6007 | } |
6011 | if (dpll & PLL_P2_DIVIDE_BY_4) |
6008 | if (dpll & PLL_P2_DIVIDE_BY_4) |
6012 | clock.p2 = 4; |
6009 | clock.p2 = 4; |
6013 | else |
6010 | else |
6014 | clock.p2 = 2; |
6011 | clock.p2 = 2; |
6015 | 6012 | ||
6016 | intel_clock(dev, 48000, &clock); |
6013 | intel_clock(dev, 48000, &clock); |
6017 | } |
6014 | } |
6018 | } |
6015 | } |
6019 | 6016 | ||
6020 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
6017 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
6021 | * i830PllIsValid() because it relies on the xf86_config connector |
6018 | * i830PllIsValid() because it relies on the xf86_config connector |
6022 | * configuration being accurate, which it isn't necessarily. |
6019 | * configuration being accurate, which it isn't necessarily. |
6023 | */ |
6020 | */ |
6024 | 6021 | ||
6025 | return clock.dot; |
6022 | return clock.dot; |
6026 | } |
6023 | } |
6027 | 6024 | ||
6028 | /** Returns the currently programmed mode of the given pipe. */ |
6025 | /** Returns the currently programmed mode of the given pipe. */ |
6029 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
6026 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
6030 | struct drm_crtc *crtc) |
6027 | struct drm_crtc *crtc) |
6031 | { |
6028 | { |
6032 | struct drm_i915_private *dev_priv = dev->dev_private; |
6029 | struct drm_i915_private *dev_priv = dev->dev_private; |
6033 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6034 | int pipe = intel_crtc->pipe; |
6031 | int pipe = intel_crtc->pipe; |
6035 | struct drm_display_mode *mode; |
6032 | struct drm_display_mode *mode; |
6036 | int htot = I915_READ(HTOTAL(pipe)); |
6033 | int htot = I915_READ(HTOTAL(pipe)); |
6037 | int hsync = I915_READ(HSYNC(pipe)); |
6034 | int hsync = I915_READ(HSYNC(pipe)); |
6038 | int vtot = I915_READ(VTOTAL(pipe)); |
6035 | int vtot = I915_READ(VTOTAL(pipe)); |
6039 | int vsync = I915_READ(VSYNC(pipe)); |
6036 | int vsync = I915_READ(VSYNC(pipe)); |
6040 | 6037 | ||
6041 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
6038 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
6042 | if (!mode) |
6039 | if (!mode) |
6043 | return NULL; |
6040 | return NULL; |
6044 | 6041 | ||
6045 | mode->clock = intel_crtc_clock_get(dev, crtc); |
6042 | mode->clock = intel_crtc_clock_get(dev, crtc); |
6046 | mode->hdisplay = (htot & 0xffff) + 1; |
6043 | mode->hdisplay = (htot & 0xffff) + 1; |
6047 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
6044 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
6048 | mode->hsync_start = (hsync & 0xffff) + 1; |
6045 | mode->hsync_start = (hsync & 0xffff) + 1; |
6049 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
6046 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
6050 | mode->vdisplay = (vtot & 0xffff) + 1; |
6047 | mode->vdisplay = (vtot & 0xffff) + 1; |
6051 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
6048 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
6052 | mode->vsync_start = (vsync & 0xffff) + 1; |
6049 | mode->vsync_start = (vsync & 0xffff) + 1; |
6053 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
6050 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
6054 | 6051 | ||
6055 | drm_mode_set_name(mode); |
6052 | drm_mode_set_name(mode); |
6056 | 6053 | ||
6057 | return mode; |
6054 | return mode; |
6058 | } |
6055 | } |
6059 | 6056 | ||
6060 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
6057 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
6061 | { |
6058 | { |
6062 | struct drm_device *dev = crtc->dev; |
6059 | struct drm_device *dev = crtc->dev; |
6063 | drm_i915_private_t *dev_priv = dev->dev_private; |
6060 | drm_i915_private_t *dev_priv = dev->dev_private; |
6064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6065 | int pipe = intel_crtc->pipe; |
6062 | int pipe = intel_crtc->pipe; |
6066 | int dpll_reg = DPLL(pipe); |
6063 | int dpll_reg = DPLL(pipe); |
6067 | int dpll; |
6064 | int dpll; |
6068 | 6065 | ||
6069 | if (HAS_PCH_SPLIT(dev)) |
6066 | if (HAS_PCH_SPLIT(dev)) |
6070 | return; |
6067 | return; |
6071 | 6068 | ||
6072 | if (!dev_priv->lvds_downclock_avail) |
6069 | if (!dev_priv->lvds_downclock_avail) |
6073 | return; |
6070 | return; |
6074 | 6071 | ||
6075 | dpll = I915_READ(dpll_reg); |
6072 | dpll = I915_READ(dpll_reg); |
6076 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
6073 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
6077 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
6074 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
6078 | 6075 | ||
6079 | assert_panel_unlocked(dev_priv, pipe); |
6076 | assert_panel_unlocked(dev_priv, pipe); |
6080 | 6077 | ||
6081 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
6078 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
6082 | I915_WRITE(dpll_reg, dpll); |
6079 | I915_WRITE(dpll_reg, dpll); |
6083 | intel_wait_for_vblank(dev, pipe); |
6080 | intel_wait_for_vblank(dev, pipe); |
6084 | 6081 | ||
6085 | dpll = I915_READ(dpll_reg); |
6082 | dpll = I915_READ(dpll_reg); |
6086 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
6083 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
6087 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
6084 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
6088 | } |
6085 | } |
6089 | } |
6086 | } |
6090 | 6087 | ||
6091 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
6088 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
6092 | { |
6089 | { |
6093 | struct drm_device *dev = crtc->dev; |
6090 | struct drm_device *dev = crtc->dev; |
6094 | drm_i915_private_t *dev_priv = dev->dev_private; |
6091 | drm_i915_private_t *dev_priv = dev->dev_private; |
6095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6096 | 6093 | ||
6097 | if (HAS_PCH_SPLIT(dev)) |
6094 | if (HAS_PCH_SPLIT(dev)) |
6098 | return; |
6095 | return; |
6099 | 6096 | ||
6100 | if (!dev_priv->lvds_downclock_avail) |
6097 | if (!dev_priv->lvds_downclock_avail) |
6101 | return; |
6098 | return; |
6102 | 6099 | ||
6103 | /* |
6100 | /* |
6104 | * Since this is called by a timer, we should never get here in |
6101 | * Since this is called by a timer, we should never get here in |
6105 | * the manual case. |
6102 | * the manual case. |
6106 | */ |
6103 | */ |
6107 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
6104 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
6108 | int pipe = intel_crtc->pipe; |
6105 | int pipe = intel_crtc->pipe; |
6109 | int dpll_reg = DPLL(pipe); |
6106 | int dpll_reg = DPLL(pipe); |
6110 | int dpll; |
6107 | int dpll; |
6111 | 6108 | ||
6112 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
6109 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
6113 | 6110 | ||
6114 | assert_panel_unlocked(dev_priv, pipe); |
6111 | assert_panel_unlocked(dev_priv, pipe); |
6115 | 6112 | ||
6116 | dpll = I915_READ(dpll_reg); |
6113 | dpll = I915_READ(dpll_reg); |
6117 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6114 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6118 | I915_WRITE(dpll_reg, dpll); |
6115 | I915_WRITE(dpll_reg, dpll); |
6119 | intel_wait_for_vblank(dev, pipe); |
6116 | intel_wait_for_vblank(dev, pipe); |
6120 | dpll = I915_READ(dpll_reg); |
6117 | dpll = I915_READ(dpll_reg); |
6121 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
6118 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
6122 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
6119 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
6123 | } |
6120 | } |
6124 | 6121 | ||
6125 | } |
6122 | } |
6126 | 6123 | ||
6127 | void intel_mark_busy(struct drm_device *dev) |
6124 | void intel_mark_busy(struct drm_device *dev) |
6128 | { |
6125 | { |
6129 | i915_update_gfx_val(dev->dev_private); |
6126 | i915_update_gfx_val(dev->dev_private); |
6130 | } |
6127 | } |
6131 | 6128 | ||
6132 | void intel_mark_idle(struct drm_device *dev) |
6129 | void intel_mark_idle(struct drm_device *dev) |
6133 | { |
6130 | { |
6134 | } |
6131 | } |
6135 | 6132 | ||
6136 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
6133 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
6137 | { |
6134 | { |
6138 | struct drm_device *dev = obj->base.dev; |
6135 | struct drm_device *dev = obj->base.dev; |
6139 | struct drm_crtc *crtc; |
6136 | struct drm_crtc *crtc; |
6140 | 6137 | ||
6141 | if (!i915_powersave) |
6138 | if (!i915_powersave) |
6142 | return; |
6139 | return; |
6143 | 6140 | ||
6144 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6141 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6145 | if (!crtc->fb) |
6142 | if (!crtc->fb) |
6146 | continue; |
6143 | continue; |
6147 | 6144 | ||
6148 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6145 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6149 | intel_increase_pllclock(crtc); |
6146 | intel_increase_pllclock(crtc); |
6150 | } |
6147 | } |
6151 | } |
6148 | } |
6152 | 6149 | ||
6153 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
6150 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
6154 | { |
6151 | { |
6155 | struct drm_device *dev = obj->base.dev; |
6152 | struct drm_device *dev = obj->base.dev; |
6156 | struct drm_crtc *crtc; |
6153 | struct drm_crtc *crtc; |
6157 | 6154 | ||
6158 | if (!i915_powersave) |
6155 | if (!i915_powersave) |
6159 | return; |
6156 | return; |
6160 | 6157 | ||
6161 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6158 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6162 | if (!crtc->fb) |
6159 | if (!crtc->fb) |
6163 | continue; |
6160 | continue; |
6164 | 6161 | ||
6165 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6162 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6166 | intel_decrease_pllclock(crtc); |
6163 | intel_decrease_pllclock(crtc); |
6167 | } |
6164 | } |
6168 | } |
6165 | } |
6169 | 6166 | ||
6170 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6167 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6171 | { |
6168 | { |
6172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6173 | struct drm_device *dev = crtc->dev; |
6170 | struct drm_device *dev = crtc->dev; |
6174 | struct intel_unpin_work *work; |
6171 | struct intel_unpin_work *work; |
6175 | unsigned long flags; |
6172 | unsigned long flags; |
6176 | 6173 | ||
6177 | spin_lock_irqsave(&dev->event_lock, flags); |
6174 | spin_lock_irqsave(&dev->event_lock, flags); |
6178 | work = intel_crtc->unpin_work; |
6175 | work = intel_crtc->unpin_work; |
6179 | intel_crtc->unpin_work = NULL; |
6176 | intel_crtc->unpin_work = NULL; |
6180 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6177 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6181 | 6178 | ||
6182 | if (work) { |
6179 | if (work) { |
6183 | // cancel_work_sync(&work->work); |
6180 | // cancel_work_sync(&work->work); |
6184 | kfree(work); |
6181 | kfree(work); |
6185 | } |
6182 | } |
6186 | 6183 | ||
6187 | drm_crtc_cleanup(crtc); |
6184 | drm_crtc_cleanup(crtc); |
6188 | 6185 | ||
6189 | kfree(intel_crtc); |
6186 | kfree(intel_crtc); |
6190 | } |
6187 | } |
6191 | 6188 | ||
6192 | #if 0 |
6189 | #if 0 |
6193 | static void intel_unpin_work_fn(struct work_struct *__work) |
6190 | static void intel_unpin_work_fn(struct work_struct *__work) |
6194 | { |
6191 | { |
6195 | struct intel_unpin_work *work = |
6192 | struct intel_unpin_work *work = |
6196 | container_of(__work, struct intel_unpin_work, work); |
6193 | container_of(__work, struct intel_unpin_work, work); |
6197 | 6194 | ||
6198 | mutex_lock(&work->dev->struct_mutex); |
6195 | mutex_lock(&work->dev->struct_mutex); |
6199 | intel_unpin_fb_obj(work->old_fb_obj); |
6196 | intel_unpin_fb_obj(work->old_fb_obj); |
6200 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6197 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6201 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6198 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6202 | 6199 | ||
6203 | intel_update_fbc(work->dev); |
6200 | intel_update_fbc(work->dev); |
6204 | mutex_unlock(&work->dev->struct_mutex); |
6201 | mutex_unlock(&work->dev->struct_mutex); |
6205 | kfree(work); |
6202 | kfree(work); |
6206 | } |
6203 | } |
6207 | 6204 | ||
6208 | static void do_intel_finish_page_flip(struct drm_device *dev, |
6205 | static void do_intel_finish_page_flip(struct drm_device *dev, |
6209 | struct drm_crtc *crtc) |
6206 | struct drm_crtc *crtc) |
6210 | { |
6207 | { |
6211 | drm_i915_private_t *dev_priv = dev->dev_private; |
6208 | drm_i915_private_t *dev_priv = dev->dev_private; |
6212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6213 | struct intel_unpin_work *work; |
6210 | struct intel_unpin_work *work; |
6214 | struct drm_i915_gem_object *obj; |
6211 | struct drm_i915_gem_object *obj; |
6215 | struct drm_pending_vblank_event *e; |
6212 | struct drm_pending_vblank_event *e; |
6216 | struct timeval tvbl; |
6213 | struct timeval tvbl; |
6217 | unsigned long flags; |
6214 | unsigned long flags; |
6218 | 6215 | ||
6219 | /* Ignore early vblank irqs */ |
6216 | /* Ignore early vblank irqs */ |
6220 | if (intel_crtc == NULL) |
6217 | if (intel_crtc == NULL) |
6221 | return; |
6218 | return; |
6222 | 6219 | ||
6223 | spin_lock_irqsave(&dev->event_lock, flags); |
6220 | spin_lock_irqsave(&dev->event_lock, flags); |
6224 | work = intel_crtc->unpin_work; |
6221 | work = intel_crtc->unpin_work; |
6225 | if (work == NULL || !work->pending) { |
6222 | if (work == NULL || !work->pending) { |
6226 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6223 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6227 | return; |
6224 | return; |
6228 | } |
6225 | } |
6229 | 6226 | ||
6230 | intel_crtc->unpin_work = NULL; |
6227 | intel_crtc->unpin_work = NULL; |
6231 | 6228 | ||
6232 | if (work->event) { |
6229 | if (work->event) { |
6233 | e = work->event; |
6230 | e = work->event; |
6234 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
6231 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
6235 | 6232 | ||
6236 | e->event.tv_sec = tvbl.tv_sec; |
6233 | e->event.tv_sec = tvbl.tv_sec; |
6237 | e->event.tv_usec = tvbl.tv_usec; |
6234 | e->event.tv_usec = tvbl.tv_usec; |
6238 | 6235 | ||
6239 | list_add_tail(&e->base.link, |
6236 | list_add_tail(&e->base.link, |
6240 | &e->base.file_priv->event_list); |
6237 | &e->base.file_priv->event_list); |
6241 | wake_up_interruptible(&e->base.file_priv->event_wait); |
6238 | wake_up_interruptible(&e->base.file_priv->event_wait); |
6242 | } |
6239 | } |
6243 | 6240 | ||
6244 | drm_vblank_put(dev, intel_crtc->pipe); |
6241 | drm_vblank_put(dev, intel_crtc->pipe); |
6245 | 6242 | ||
6246 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6243 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6247 | 6244 | ||
6248 | obj = work->old_fb_obj; |
6245 | obj = work->old_fb_obj; |
6249 | 6246 | ||
6250 | atomic_clear_mask(1 << intel_crtc->plane, |
6247 | atomic_clear_mask(1 << intel_crtc->plane, |
6251 | &obj->pending_flip.counter); |
6248 | &obj->pending_flip.counter); |
6252 | 6249 | ||
6253 | wake_up(&dev_priv->pending_flip_queue); |
6250 | wake_up(&dev_priv->pending_flip_queue); |
6254 | schedule_work(&work->work); |
6251 | schedule_work(&work->work); |
6255 | 6252 | ||
6256 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
6253 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
6257 | } |
6254 | } |
6258 | 6255 | ||
6259 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6256 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6260 | { |
6257 | { |
6261 | drm_i915_private_t *dev_priv = dev->dev_private; |
6258 | drm_i915_private_t *dev_priv = dev->dev_private; |
6262 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
6259 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
6263 | 6260 | ||
6264 | do_intel_finish_page_flip(dev, crtc); |
6261 | do_intel_finish_page_flip(dev, crtc); |
6265 | } |
6262 | } |
6266 | 6263 | ||
6267 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
6264 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
6268 | { |
6265 | { |
6269 | drm_i915_private_t *dev_priv = dev->dev_private; |
6266 | drm_i915_private_t *dev_priv = dev->dev_private; |
6270 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
6267 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
6271 | 6268 | ||
6272 | do_intel_finish_page_flip(dev, crtc); |
6269 | do_intel_finish_page_flip(dev, crtc); |
6273 | } |
6270 | } |
6274 | 6271 | ||
6275 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6272 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6276 | { |
6273 | { |
6277 | drm_i915_private_t *dev_priv = dev->dev_private; |
6274 | drm_i915_private_t *dev_priv = dev->dev_private; |
6278 | struct intel_crtc *intel_crtc = |
6275 | struct intel_crtc *intel_crtc = |
6279 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
6276 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
6280 | unsigned long flags; |
6277 | unsigned long flags; |
6281 | 6278 | ||
6282 | spin_lock_irqsave(&dev->event_lock, flags); |
6279 | spin_lock_irqsave(&dev->event_lock, flags); |
6283 | if (intel_crtc->unpin_work) { |
6280 | if (intel_crtc->unpin_work) { |
6284 | if ((++intel_crtc->unpin_work->pending) > 1) |
6281 | if ((++intel_crtc->unpin_work->pending) > 1) |
6285 | DRM_ERROR("Prepared flip multiple times\n"); |
6282 | DRM_ERROR("Prepared flip multiple times\n"); |
6286 | } else { |
6283 | } else { |
6287 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
6284 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
6288 | } |
6285 | } |
6289 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6286 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6290 | } |
6287 | } |
6291 | 6288 | ||
6292 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6289 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6293 | struct drm_crtc *crtc, |
6290 | struct drm_crtc *crtc, |
6294 | struct drm_framebuffer *fb, |
6291 | struct drm_framebuffer *fb, |
6295 | struct drm_i915_gem_object *obj) |
6292 | struct drm_i915_gem_object *obj) |
6296 | { |
6293 | { |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; |
6294 | struct drm_i915_private *dev_priv = dev->dev_private; |
6298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6299 | u32 flip_mask; |
6296 | u32 flip_mask; |
6300 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6297 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6301 | int ret; |
6298 | int ret; |
6302 | 6299 | ||
6303 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6300 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6304 | if (ret) |
6301 | if (ret) |
6305 | goto err; |
6302 | goto err; |
6306 | 6303 | ||
6307 | ret = intel_ring_begin(ring, 6); |
6304 | ret = intel_ring_begin(ring, 6); |
6308 | if (ret) |
6305 | if (ret) |
6309 | goto err_unpin; |
6306 | goto err_unpin; |
6310 | 6307 | ||
6311 | /* Can't queue multiple flips, so wait for the previous |
6308 | /* Can't queue multiple flips, so wait for the previous |
6312 | * one to finish before executing the next. |
6309 | * one to finish before executing the next. |
6313 | */ |
6310 | */ |
6314 | if (intel_crtc->plane) |
6311 | if (intel_crtc->plane) |
6315 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
6312 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
6316 | else |
6313 | else |
6317 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
6314 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
6318 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6315 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6319 | intel_ring_emit(ring, MI_NOOP); |
6316 | intel_ring_emit(ring, MI_NOOP); |
6320 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6317 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6321 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6318 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6322 | intel_ring_emit(ring, fb->pitches[0]); |
6319 | intel_ring_emit(ring, fb->pitches[0]); |
6323 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6320 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6324 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
6321 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
6325 | intel_ring_advance(ring); |
6322 | intel_ring_advance(ring); |
6326 | return 0; |
6323 | return 0; |
6327 | 6324 | ||
6328 | err_unpin: |
6325 | err_unpin: |
6329 | intel_unpin_fb_obj(obj); |
6326 | intel_unpin_fb_obj(obj); |
6330 | err: |
6327 | err: |
6331 | return ret; |
6328 | return ret; |
6332 | } |
6329 | } |
6333 | 6330 | ||
6334 | static int intel_gen3_queue_flip(struct drm_device *dev, |
6331 | static int intel_gen3_queue_flip(struct drm_device *dev, |
6335 | struct drm_crtc *crtc, |
6332 | struct drm_crtc *crtc, |
6336 | struct drm_framebuffer *fb, |
6333 | struct drm_framebuffer *fb, |
6337 | struct drm_i915_gem_object *obj) |
6334 | struct drm_i915_gem_object *obj) |
6338 | { |
6335 | { |
6339 | struct drm_i915_private *dev_priv = dev->dev_private; |
6336 | struct drm_i915_private *dev_priv = dev->dev_private; |
6340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6341 | u32 flip_mask; |
6338 | u32 flip_mask; |
6342 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6339 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6343 | int ret; |
6340 | int ret; |
6344 | 6341 | ||
6345 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6342 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6346 | if (ret) |
6343 | if (ret) |
6347 | goto err; |
6344 | goto err; |
6348 | 6345 | ||
6349 | ret = intel_ring_begin(ring, 6); |
6346 | ret = intel_ring_begin(ring, 6); |
6350 | if (ret) |
6347 | if (ret) |
6351 | goto err_unpin; |
6348 | goto err_unpin; |
6352 | 6349 | ||
6353 | if (intel_crtc->plane) |
6350 | if (intel_crtc->plane) |
6354 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
6351 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
6355 | else |
6352 | else |
6356 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
6353 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
6357 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6354 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6358 | intel_ring_emit(ring, MI_NOOP); |
6355 | intel_ring_emit(ring, MI_NOOP); |
6359 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
6356 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
6360 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6357 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6361 | intel_ring_emit(ring, fb->pitches[0]); |
6358 | intel_ring_emit(ring, fb->pitches[0]); |
6362 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6359 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6363 | intel_ring_emit(ring, MI_NOOP); |
6360 | intel_ring_emit(ring, MI_NOOP); |
6364 | 6361 | ||
6365 | intel_ring_advance(ring); |
6362 | intel_ring_advance(ring); |
6366 | return 0; |
6363 | return 0; |
6367 | 6364 | ||
6368 | err_unpin: |
6365 | err_unpin: |
6369 | intel_unpin_fb_obj(obj); |
6366 | intel_unpin_fb_obj(obj); |
6370 | err: |
6367 | err: |
6371 | return ret; |
6368 | return ret; |
6372 | } |
6369 | } |
6373 | 6370 | ||
6374 | static int intel_gen4_queue_flip(struct drm_device *dev, |
6371 | static int intel_gen4_queue_flip(struct drm_device *dev, |
6375 | struct drm_crtc *crtc, |
6372 | struct drm_crtc *crtc, |
6376 | struct drm_framebuffer *fb, |
6373 | struct drm_framebuffer *fb, |
6377 | struct drm_i915_gem_object *obj) |
6374 | struct drm_i915_gem_object *obj) |
6378 | { |
6375 | { |
6379 | struct drm_i915_private *dev_priv = dev->dev_private; |
6376 | struct drm_i915_private *dev_priv = dev->dev_private; |
6380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6377 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6381 | uint32_t pf, pipesrc; |
6378 | uint32_t pf, pipesrc; |
6382 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6379 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6383 | int ret; |
6380 | int ret; |
6384 | 6381 | ||
6385 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6382 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6386 | if (ret) |
6383 | if (ret) |
6387 | goto err; |
6384 | goto err; |
6388 | 6385 | ||
6389 | ret = intel_ring_begin(ring, 4); |
6386 | ret = intel_ring_begin(ring, 4); |
6390 | if (ret) |
6387 | if (ret) |
6391 | goto err_unpin; |
6388 | goto err_unpin; |
6392 | 6389 | ||
6393 | /* i965+ uses the linear or tiled offsets from the |
6390 | /* i965+ uses the linear or tiled offsets from the |
6394 | * Display Registers (which do not change across a page-flip) |
6391 | * Display Registers (which do not change across a page-flip) |
6395 | * so we need only reprogram the base address. |
6392 | * so we need only reprogram the base address. |
6396 | */ |
6393 | */ |
6397 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6394 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6398 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6395 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6399 | intel_ring_emit(ring, fb->pitches[0]); |
6396 | intel_ring_emit(ring, fb->pitches[0]); |
6400 | intel_ring_emit(ring, |
6397 | intel_ring_emit(ring, |
6401 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | |
6398 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | |
6402 | obj->tiling_mode); |
6399 | obj->tiling_mode); |
6403 | 6400 | ||
6404 | /* XXX Enabling the panel-fitter across page-flip is so far |
6401 | /* XXX Enabling the panel-fitter across page-flip is so far |
6405 | * untested on non-native modes, so ignore it for now. |
6402 | * untested on non-native modes, so ignore it for now. |
6406 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
6403 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
6407 | */ |
6404 | */ |
6408 | pf = 0; |
6405 | pf = 0; |
6409 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6406 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6410 | intel_ring_emit(ring, pf | pipesrc); |
6407 | intel_ring_emit(ring, pf | pipesrc); |
6411 | intel_ring_advance(ring); |
6408 | intel_ring_advance(ring); |
6412 | return 0; |
6409 | return 0; |
6413 | 6410 | ||
6414 | err_unpin: |
6411 | err_unpin: |
6415 | intel_unpin_fb_obj(obj); |
6412 | intel_unpin_fb_obj(obj); |
6416 | err: |
6413 | err: |
6417 | return ret; |
6414 | return ret; |
6418 | } |
6415 | } |
6419 | 6416 | ||
6420 | static int intel_gen6_queue_flip(struct drm_device *dev, |
6417 | static int intel_gen6_queue_flip(struct drm_device *dev, |
6421 | struct drm_crtc *crtc, |
6418 | struct drm_crtc *crtc, |
6422 | struct drm_framebuffer *fb, |
6419 | struct drm_framebuffer *fb, |
6423 | struct drm_i915_gem_object *obj) |
6420 | struct drm_i915_gem_object *obj) |
6424 | { |
6421 | { |
6425 | struct drm_i915_private *dev_priv = dev->dev_private; |
6422 | struct drm_i915_private *dev_priv = dev->dev_private; |
6426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6427 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6424 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6428 | uint32_t pf, pipesrc; |
6425 | uint32_t pf, pipesrc; |
6429 | int ret; |
6426 | int ret; |
6430 | 6427 | ||
6431 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6428 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6432 | if (ret) |
6429 | if (ret) |
6433 | goto err; |
6430 | goto err; |
6434 | 6431 | ||
6435 | ret = intel_ring_begin(ring, 4); |
6432 | ret = intel_ring_begin(ring, 4); |
6436 | if (ret) |
6433 | if (ret) |
6437 | goto err_unpin; |
6434 | goto err_unpin; |
6438 | 6435 | ||
6439 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6436 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6440 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6437 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
6441 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
6438 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
6442 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6439 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6443 | 6440 | ||
6444 | /* Contrary to the suggestions in the documentation, |
6441 | /* Contrary to the suggestions in the documentation, |
6445 | * "Enable Panel Fitter" does not seem to be required when page |
6442 | * "Enable Panel Fitter" does not seem to be required when page |
6446 | * flipping with a non-native mode, and worse causes a normal |
6443 | * flipping with a non-native mode, and worse causes a normal |
6447 | * modeset to fail. |
6444 | * modeset to fail. |
6448 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
6445 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
6449 | */ |
6446 | */ |
6450 | pf = 0; |
6447 | pf = 0; |
6451 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6448 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6452 | intel_ring_emit(ring, pf | pipesrc); |
6449 | intel_ring_emit(ring, pf | pipesrc); |
6453 | intel_ring_advance(ring); |
6450 | intel_ring_advance(ring); |
6454 | return 0; |
6451 | return 0; |
6455 | 6452 | ||
6456 | err_unpin: |
6453 | err_unpin: |
6457 | intel_unpin_fb_obj(obj); |
6454 | intel_unpin_fb_obj(obj); |
6458 | err: |
6455 | err: |
6459 | return ret; |
6456 | return ret; |
6460 | } |
6457 | } |
6461 | 6458 | ||
6462 | /* |
6459 | /* |
6463 | * On gen7 we currently use the blit ring because (in early silicon at least) |
6460 | * On gen7 we currently use the blit ring because (in early silicon at least) |
6464 | * the render ring doesn't give us interrpts for page flip completion, which |
6461 | * the render ring doesn't give us interrpts for page flip completion, which |
6465 | * means clients will hang after the first flip is queued. Fortunately the |
6462 | * means clients will hang after the first flip is queued. Fortunately the |
6466 | * blit ring generates interrupts properly, so use it instead. |
6463 | * blit ring generates interrupts properly, so use it instead. |
6467 | */ |
6464 | */ |
6468 | static int intel_gen7_queue_flip(struct drm_device *dev, |
6465 | static int intel_gen7_queue_flip(struct drm_device *dev, |
6469 | struct drm_crtc *crtc, |
6466 | struct drm_crtc *crtc, |
6470 | struct drm_framebuffer *fb, |
6467 | struct drm_framebuffer *fb, |
6471 | struct drm_i915_gem_object *obj) |
6468 | struct drm_i915_gem_object *obj) |
6472 | { |
6469 | { |
6473 | struct drm_i915_private *dev_priv = dev->dev_private; |
6470 | struct drm_i915_private *dev_priv = dev->dev_private; |
6474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6475 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
6472 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
6476 | uint32_t plane_bit = 0; |
6473 | uint32_t plane_bit = 0; |
6477 | int ret; |
6474 | int ret; |
6478 | 6475 | ||
6479 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6476 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
6480 | if (ret) |
6477 | if (ret) |
6481 | goto err; |
6478 | goto err; |
6482 | 6479 | ||
6483 | switch(intel_crtc->plane) { |
6480 | switch(intel_crtc->plane) { |
6484 | case PLANE_A: |
6481 | case PLANE_A: |
6485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
6482 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
6486 | break; |
6483 | break; |
6487 | case PLANE_B: |
6484 | case PLANE_B: |
6488 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
6485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
6489 | break; |
6486 | break; |
6490 | case PLANE_C: |
6487 | case PLANE_C: |
6491 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
6488 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
6492 | break; |
6489 | break; |
6493 | default: |
6490 | default: |
6494 | WARN_ONCE(1, "unknown plane in flip command\n"); |
6491 | WARN_ONCE(1, "unknown plane in flip command\n"); |
6495 | ret = -ENODEV; |
6492 | ret = -ENODEV; |
6496 | goto err_unpin; |
6493 | goto err_unpin; |
6497 | } |
6494 | } |
6498 | 6495 | ||
6499 | ret = intel_ring_begin(ring, 4); |
6496 | ret = intel_ring_begin(ring, 4); |
6500 | if (ret) |
6497 | if (ret) |
6501 | goto err_unpin; |
6498 | goto err_unpin; |
6502 | 6499 | ||
6503 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
6500 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
6504 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
6501 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
6505 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6502 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6506 | intel_ring_emit(ring, (MI_NOOP)); |
6503 | intel_ring_emit(ring, (MI_NOOP)); |
6507 | intel_ring_advance(ring); |
6504 | intel_ring_advance(ring); |
6508 | return 0; |
6505 | return 0; |
6509 | 6506 | ||
6510 | err_unpin: |
6507 | err_unpin: |
6511 | intel_unpin_fb_obj(obj); |
6508 | intel_unpin_fb_obj(obj); |
6512 | err: |
6509 | err: |
6513 | return ret; |
6510 | return ret; |
6514 | } |
6511 | } |
6515 | 6512 | ||
6516 | static int intel_default_queue_flip(struct drm_device *dev, |
6513 | static int intel_default_queue_flip(struct drm_device *dev, |
6517 | struct drm_crtc *crtc, |
6514 | struct drm_crtc *crtc, |
6518 | struct drm_framebuffer *fb, |
6515 | struct drm_framebuffer *fb, |
6519 | struct drm_i915_gem_object *obj) |
6516 | struct drm_i915_gem_object *obj) |
6520 | { |
6517 | { |
6521 | return -ENODEV; |
6518 | return -ENODEV; |
6522 | } |
6519 | } |
6523 | 6520 | ||
6524 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6521 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6525 | struct drm_framebuffer *fb, |
6522 | struct drm_framebuffer *fb, |
6526 | struct drm_pending_vblank_event *event) |
6523 | struct drm_pending_vblank_event *event) |
6527 | { |
6524 | { |
6528 | struct drm_device *dev = crtc->dev; |
6525 | struct drm_device *dev = crtc->dev; |
6529 | struct drm_i915_private *dev_priv = dev->dev_private; |
6526 | struct drm_i915_private *dev_priv = dev->dev_private; |
6530 | struct intel_framebuffer *intel_fb; |
6527 | struct intel_framebuffer *intel_fb; |
6531 | struct drm_i915_gem_object *obj; |
6528 | struct drm_i915_gem_object *obj; |
6532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6529 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6533 | struct intel_unpin_work *work; |
6530 | struct intel_unpin_work *work; |
6534 | unsigned long flags; |
6531 | unsigned long flags; |
6535 | int ret; |
6532 | int ret; |
6536 | 6533 | ||
6537 | /* Can't change pixel format via MI display flips. */ |
6534 | /* Can't change pixel format via MI display flips. */ |
6538 | if (fb->pixel_format != crtc->fb->pixel_format) |
6535 | if (fb->pixel_format != crtc->fb->pixel_format) |
6539 | return -EINVAL; |
6536 | return -EINVAL; |
6540 | 6537 | ||
6541 | /* |
6538 | /* |
6542 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
6539 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
6543 | * Note that pitch changes could also affect these register. |
6540 | * Note that pitch changes could also affect these register. |
6544 | */ |
6541 | */ |
6545 | if (INTEL_INFO(dev)->gen > 3 && |
6542 | if (INTEL_INFO(dev)->gen > 3 && |
6546 | (fb->offsets[0] != crtc->fb->offsets[0] || |
6543 | (fb->offsets[0] != crtc->fb->offsets[0] || |
6547 | fb->pitches[0] != crtc->fb->pitches[0])) |
6544 | fb->pitches[0] != crtc->fb->pitches[0])) |
6548 | return -EINVAL; |
6545 | return -EINVAL; |
6549 | 6546 | ||
6550 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6547 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6551 | if (work == NULL) |
6548 | if (work == NULL) |
6552 | return -ENOMEM; |
6549 | return -ENOMEM; |
6553 | 6550 | ||
6554 | work->event = event; |
6551 | work->event = event; |
6555 | work->dev = crtc->dev; |
6552 | work->dev = crtc->dev; |
6556 | intel_fb = to_intel_framebuffer(crtc->fb); |
6553 | intel_fb = to_intel_framebuffer(crtc->fb); |
6557 | work->old_fb_obj = intel_fb->obj; |
6554 | work->old_fb_obj = intel_fb->obj; |
6558 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6555 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6559 | 6556 | ||
6560 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6557 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6561 | if (ret) |
6558 | if (ret) |
6562 | goto free_work; |
6559 | goto free_work; |
6563 | 6560 | ||
6564 | /* We borrow the event spin lock for protecting unpin_work */ |
6561 | /* We borrow the event spin lock for protecting unpin_work */ |
6565 | spin_lock_irqsave(&dev->event_lock, flags); |
6562 | spin_lock_irqsave(&dev->event_lock, flags); |
6566 | if (intel_crtc->unpin_work) { |
6563 | if (intel_crtc->unpin_work) { |
6567 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6564 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6568 | kfree(work); |
6565 | kfree(work); |
6569 | drm_vblank_put(dev, intel_crtc->pipe); |
6566 | drm_vblank_put(dev, intel_crtc->pipe); |
6570 | 6567 | ||
6571 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
6568 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
6572 | return -EBUSY; |
6569 | return -EBUSY; |
6573 | } |
6570 | } |
6574 | intel_crtc->unpin_work = work; |
6571 | intel_crtc->unpin_work = work; |
6575 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6572 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6576 | 6573 | ||
6577 | intel_fb = to_intel_framebuffer(fb); |
6574 | intel_fb = to_intel_framebuffer(fb); |
6578 | obj = intel_fb->obj; |
6575 | obj = intel_fb->obj; |
6579 | 6576 | ||
6580 | ret = i915_mutex_lock_interruptible(dev); |
6577 | ret = i915_mutex_lock_interruptible(dev); |
6581 | if (ret) |
6578 | if (ret) |
6582 | goto cleanup; |
6579 | goto cleanup; |
6583 | 6580 | ||
6584 | /* Reference the objects for the scheduled work. */ |
6581 | /* Reference the objects for the scheduled work. */ |
6585 | drm_gem_object_reference(&work->old_fb_obj->base); |
6582 | drm_gem_object_reference(&work->old_fb_obj->base); |
6586 | drm_gem_object_reference(&obj->base); |
6583 | drm_gem_object_reference(&obj->base); |
6587 | 6584 | ||
6588 | crtc->fb = fb; |
6585 | crtc->fb = fb; |
6589 | 6586 | ||
6590 | work->pending_flip_obj = obj; |
6587 | work->pending_flip_obj = obj; |
6591 | 6588 | ||
6592 | work->enable_stall_check = true; |
6589 | work->enable_stall_check = true; |
6593 | 6590 | ||
6594 | /* Block clients from rendering to the new back buffer until |
6591 | /* Block clients from rendering to the new back buffer until |
6595 | * the flip occurs and the object is no longer visible. |
6592 | * the flip occurs and the object is no longer visible. |
6596 | */ |
6593 | */ |
6597 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
6594 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
6598 | 6595 | ||
6599 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
6596 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
6600 | if (ret) |
6597 | if (ret) |
6601 | goto cleanup_pending; |
6598 | goto cleanup_pending; |
6602 | 6599 | ||
6603 | intel_disable_fbc(dev); |
6600 | intel_disable_fbc(dev); |
6604 | intel_mark_fb_busy(obj); |
6601 | intel_mark_fb_busy(obj); |
6605 | mutex_unlock(&dev->struct_mutex); |
6602 | mutex_unlock(&dev->struct_mutex); |
6606 | 6603 | ||
6607 | trace_i915_flip_request(intel_crtc->plane, obj); |
6604 | trace_i915_flip_request(intel_crtc->plane, obj); |
6608 | 6605 | ||
6609 | return 0; |
6606 | return 0; |
6610 | 6607 | ||
6611 | cleanup_pending: |
6608 | cleanup_pending: |
6612 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
6609 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
6613 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6610 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6614 | drm_gem_object_unreference(&obj->base); |
6611 | drm_gem_object_unreference(&obj->base); |
6615 | mutex_unlock(&dev->struct_mutex); |
6612 | mutex_unlock(&dev->struct_mutex); |
6616 | 6613 | ||
6617 | cleanup: |
6614 | cleanup: |
6618 | spin_lock_irqsave(&dev->event_lock, flags); |
6615 | spin_lock_irqsave(&dev->event_lock, flags); |
6619 | intel_crtc->unpin_work = NULL; |
6616 | intel_crtc->unpin_work = NULL; |
6620 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6617 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6621 | 6618 | ||
6622 | drm_vblank_put(dev, intel_crtc->pipe); |
6619 | drm_vblank_put(dev, intel_crtc->pipe); |
6623 | free_work: |
6620 | free_work: |
6624 | kfree(work); |
6621 | kfree(work); |
6625 | 6622 | ||
6626 | return ret; |
6623 | return ret; |
6627 | } |
6624 | } |
6628 | 6625 | ||
6629 | #endif |
6626 | #endif |
6630 | 6627 | ||
6631 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
6628 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
6632 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
6629 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
6633 | .load_lut = intel_crtc_load_lut, |
6630 | .load_lut = intel_crtc_load_lut, |
6634 | .disable = intel_crtc_noop, |
6631 | .disable = intel_crtc_noop, |
6635 | }; |
6632 | }; |
6636 | 6633 | ||
6637 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
6634 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
6638 | { |
6635 | { |
6639 | struct intel_encoder *other_encoder; |
6636 | struct intel_encoder *other_encoder; |
6640 | struct drm_crtc *crtc = &encoder->new_crtc->base; |
6637 | struct drm_crtc *crtc = &encoder->new_crtc->base; |
6641 | 6638 | ||
6642 | if (WARN_ON(!crtc)) |
6639 | if (WARN_ON(!crtc)) |
6643 | return false; |
6640 | return false; |
6644 | 6641 | ||
6645 | list_for_each_entry(other_encoder, |
6642 | list_for_each_entry(other_encoder, |
6646 | &crtc->dev->mode_config.encoder_list, |
6643 | &crtc->dev->mode_config.encoder_list, |
6647 | base.head) { |
6644 | base.head) { |
6648 | 6645 | ||
6649 | if (&other_encoder->new_crtc->base != crtc || |
6646 | if (&other_encoder->new_crtc->base != crtc || |
6650 | encoder == other_encoder) |
6647 | encoder == other_encoder) |
6651 | continue; |
6648 | continue; |
6652 | else |
6649 | else |
6653 | return true; |
6650 | return true; |
6654 | } |
6651 | } |
6655 | 6652 | ||
6656 | return false; |
6653 | return false; |
6657 | } |
6654 | } |
6658 | 6655 | ||
6659 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
6656 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
6660 | struct drm_crtc *crtc) |
6657 | struct drm_crtc *crtc) |
6661 | { |
6658 | { |
6662 | struct drm_device *dev; |
6659 | struct drm_device *dev; |
6663 | struct drm_crtc *tmp; |
6660 | struct drm_crtc *tmp; |
6664 | int crtc_mask = 1; |
6661 | int crtc_mask = 1; |
6665 | 6662 | ||
6666 | WARN(!crtc, "checking null crtc?\n"); |
6663 | WARN(!crtc, "checking null crtc?\n"); |
6667 | 6664 | ||
6668 | dev = crtc->dev; |
6665 | dev = crtc->dev; |
6669 | 6666 | ||
6670 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
6667 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
6671 | if (tmp == crtc) |
6668 | if (tmp == crtc) |
6672 | break; |
6669 | break; |
6673 | crtc_mask <<= 1; |
6670 | crtc_mask <<= 1; |
6674 | } |
6671 | } |
6675 | 6672 | ||
6676 | if (encoder->possible_crtcs & crtc_mask) |
6673 | if (encoder->possible_crtcs & crtc_mask) |
6677 | return true; |
6674 | return true; |
6678 | return false; |
6675 | return false; |
6679 | } |
6676 | } |
6680 | 6677 | ||
6681 | /** |
6678 | /** |
6682 | * intel_modeset_update_staged_output_state |
6679 | * intel_modeset_update_staged_output_state |
6683 | * |
6680 | * |
6684 | * Updates the staged output configuration state, e.g. after we've read out the |
6681 | * Updates the staged output configuration state, e.g. after we've read out the |
6685 | * current hw state. |
6682 | * current hw state. |
6686 | */ |
6683 | */ |
6687 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
6684 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
6688 | { |
6685 | { |
6689 | struct intel_encoder *encoder; |
6686 | struct intel_encoder *encoder; |
6690 | struct intel_connector *connector; |
6687 | struct intel_connector *connector; |
6691 | 6688 | ||
6692 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6689 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6693 | base.head) { |
6690 | base.head) { |
6694 | connector->new_encoder = |
6691 | connector->new_encoder = |
6695 | to_intel_encoder(connector->base.encoder); |
6692 | to_intel_encoder(connector->base.encoder); |
6696 | } |
6693 | } |
6697 | 6694 | ||
6698 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6695 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6699 | base.head) { |
6696 | base.head) { |
6700 | encoder->new_crtc = |
6697 | encoder->new_crtc = |
6701 | to_intel_crtc(encoder->base.crtc); |
6698 | to_intel_crtc(encoder->base.crtc); |
6702 | } |
6699 | } |
6703 | } |
6700 | } |
6704 | 6701 | ||
6705 | /** |
6702 | /** |
6706 | * intel_modeset_commit_output_state |
6703 | * intel_modeset_commit_output_state |
6707 | * |
6704 | * |
6708 | * This function copies the stage display pipe configuration to the real one. |
6705 | * This function copies the stage display pipe configuration to the real one. |
6709 | */ |
6706 | */ |
6710 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
6707 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
6711 | { |
6708 | { |
6712 | struct intel_encoder *encoder; |
6709 | struct intel_encoder *encoder; |
6713 | struct intel_connector *connector; |
6710 | struct intel_connector *connector; |
6714 | 6711 | ||
6715 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6712 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6716 | base.head) { |
6713 | base.head) { |
6717 | connector->base.encoder = &connector->new_encoder->base; |
6714 | connector->base.encoder = &connector->new_encoder->base; |
6718 | } |
6715 | } |
6719 | 6716 | ||
6720 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6717 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6721 | base.head) { |
6718 | base.head) { |
6722 | encoder->base.crtc = &encoder->new_crtc->base; |
6719 | encoder->base.crtc = &encoder->new_crtc->base; |
6723 | } |
6720 | } |
6724 | } |
6721 | } |
6725 | 6722 | ||
6726 | static struct drm_display_mode * |
6723 | static struct drm_display_mode * |
6727 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, |
6724 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, |
6728 | struct drm_display_mode *mode) |
6725 | struct drm_display_mode *mode) |
6729 | { |
6726 | { |
6730 | struct drm_device *dev = crtc->dev; |
6727 | struct drm_device *dev = crtc->dev; |
6731 | struct drm_display_mode *adjusted_mode; |
6728 | struct drm_display_mode *adjusted_mode; |
6732 | struct drm_encoder_helper_funcs *encoder_funcs; |
6729 | struct drm_encoder_helper_funcs *encoder_funcs; |
6733 | struct intel_encoder *encoder; |
6730 | struct intel_encoder *encoder; |
6734 | 6731 | ||
6735 | adjusted_mode = drm_mode_duplicate(dev, mode); |
6732 | adjusted_mode = drm_mode_duplicate(dev, mode); |
6736 | if (!adjusted_mode) |
6733 | if (!adjusted_mode) |
6737 | return ERR_PTR(-ENOMEM); |
6734 | return ERR_PTR(-ENOMEM); |
6738 | 6735 | ||
6739 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
6736 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
6740 | * adjust it according to limitations or connector properties, and also |
6737 | * adjust it according to limitations or connector properties, and also |
6741 | * a chance to reject the mode entirely. |
6738 | * a chance to reject the mode entirely. |
6742 | */ |
6739 | */ |
6743 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6740 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6744 | base.head) { |
6741 | base.head) { |
6745 | 6742 | ||
6746 | if (&encoder->new_crtc->base != crtc) |
6743 | if (&encoder->new_crtc->base != crtc) |
6747 | continue; |
6744 | continue; |
6748 | encoder_funcs = encoder->base.helper_private; |
6745 | encoder_funcs = encoder->base.helper_private; |
6749 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, |
6746 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, |
6750 | adjusted_mode))) { |
6747 | adjusted_mode))) { |
6751 | DRM_DEBUG_KMS("Encoder fixup failed\n"); |
6748 | DRM_DEBUG_KMS("Encoder fixup failed\n"); |
6752 | goto fail; |
6749 | goto fail; |
6753 | } |
6750 | } |
6754 | } |
6751 | } |
6755 | 6752 | ||
6756 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
6753 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
6757 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
6754 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
6758 | goto fail; |
6755 | goto fail; |
6759 | } |
6756 | } |
6760 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
6757 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
6761 | 6758 | ||
6762 | return adjusted_mode; |
6759 | return adjusted_mode; |
6763 | fail: |
6760 | fail: |
6764 | drm_mode_destroy(dev, adjusted_mode); |
6761 | drm_mode_destroy(dev, adjusted_mode); |
6765 | return ERR_PTR(-EINVAL); |
6762 | return ERR_PTR(-EINVAL); |
6766 | } |
6763 | } |
6767 | 6764 | ||
6768 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
6765 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
6769 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
6766 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
6770 | static void |
6767 | static void |
6771 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
6768 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
6772 | unsigned *prepare_pipes, unsigned *disable_pipes) |
6769 | unsigned *prepare_pipes, unsigned *disable_pipes) |
6773 | { |
6770 | { |
6774 | struct intel_crtc *intel_crtc; |
6771 | struct intel_crtc *intel_crtc; |
6775 | struct drm_device *dev = crtc->dev; |
6772 | struct drm_device *dev = crtc->dev; |
6776 | struct intel_encoder *encoder; |
6773 | struct intel_encoder *encoder; |
6777 | struct intel_connector *connector; |
6774 | struct intel_connector *connector; |
6778 | struct drm_crtc *tmp_crtc; |
6775 | struct drm_crtc *tmp_crtc; |
6779 | 6776 | ||
6780 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
6777 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
6781 | 6778 | ||
6782 | /* Check which crtcs have changed outputs connected to them, these need |
6779 | /* Check which crtcs have changed outputs connected to them, these need |
6783 | * to be part of the prepare_pipes mask. We don't (yet) support global |
6780 | * to be part of the prepare_pipes mask. We don't (yet) support global |
6784 | * modeset across multiple crtcs, so modeset_pipes will only have one |
6781 | * modeset across multiple crtcs, so modeset_pipes will only have one |
6785 | * bit set at most. */ |
6782 | * bit set at most. */ |
6786 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6783 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6787 | base.head) { |
6784 | base.head) { |
6788 | if (connector->base.encoder == &connector->new_encoder->base) |
6785 | if (connector->base.encoder == &connector->new_encoder->base) |
6789 | continue; |
6786 | continue; |
6790 | 6787 | ||
6791 | if (connector->base.encoder) { |
6788 | if (connector->base.encoder) { |
6792 | tmp_crtc = connector->base.encoder->crtc; |
6789 | tmp_crtc = connector->base.encoder->crtc; |
6793 | 6790 | ||
6794 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
6791 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
6795 | } |
6792 | } |
6796 | 6793 | ||
6797 | if (connector->new_encoder) |
6794 | if (connector->new_encoder) |
6798 | *prepare_pipes |= |
6795 | *prepare_pipes |= |
6799 | 1 << connector->new_encoder->new_crtc->pipe; |
6796 | 1 << connector->new_encoder->new_crtc->pipe; |
6800 | } |
6797 | } |
6801 | 6798 | ||
6802 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6799 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6803 | base.head) { |
6800 | base.head) { |
6804 | if (encoder->base.crtc == &encoder->new_crtc->base) |
6801 | if (encoder->base.crtc == &encoder->new_crtc->base) |
6805 | continue; |
6802 | continue; |
6806 | 6803 | ||
6807 | if (encoder->base.crtc) { |
6804 | if (encoder->base.crtc) { |
6808 | tmp_crtc = encoder->base.crtc; |
6805 | tmp_crtc = encoder->base.crtc; |
6809 | 6806 | ||
6810 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
6807 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
6811 | } |
6808 | } |
6812 | 6809 | ||
6813 | if (encoder->new_crtc) |
6810 | if (encoder->new_crtc) |
6814 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
6811 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
6815 | } |
6812 | } |
6816 | 6813 | ||
6817 | /* Check for any pipes that will be fully disabled ... */ |
6814 | /* Check for any pipes that will be fully disabled ... */ |
6818 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
6815 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
6819 | base.head) { |
6816 | base.head) { |
6820 | bool used = false; |
6817 | bool used = false; |
6821 | 6818 | ||
6822 | /* Don't try to disable disabled crtcs. */ |
6819 | /* Don't try to disable disabled crtcs. */ |
6823 | if (!intel_crtc->base.enabled) |
6820 | if (!intel_crtc->base.enabled) |
6824 | continue; |
6821 | continue; |
6825 | 6822 | ||
6826 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6823 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6827 | base.head) { |
6824 | base.head) { |
6828 | if (encoder->new_crtc == intel_crtc) |
6825 | if (encoder->new_crtc == intel_crtc) |
6829 | used = true; |
6826 | used = true; |
6830 | } |
6827 | } |
6831 | 6828 | ||
6832 | if (!used) |
6829 | if (!used) |
6833 | *disable_pipes |= 1 << intel_crtc->pipe; |
6830 | *disable_pipes |= 1 << intel_crtc->pipe; |
6834 | } |
6831 | } |
6835 | 6832 | ||
6836 | 6833 | ||
6837 | /* set_mode is also used to update properties on life display pipes. */ |
6834 | /* set_mode is also used to update properties on life display pipes. */ |
6838 | intel_crtc = to_intel_crtc(crtc); |
6835 | intel_crtc = to_intel_crtc(crtc); |
6839 | if (crtc->enabled) |
6836 | if (crtc->enabled) |
6840 | *prepare_pipes |= 1 << intel_crtc->pipe; |
6837 | *prepare_pipes |= 1 << intel_crtc->pipe; |
6841 | 6838 | ||
6842 | /* We only support modeset on one single crtc, hence we need to do that |
6839 | /* We only support modeset on one single crtc, hence we need to do that |
6843 | * only for the passed in crtc iff we change anything else than just |
6840 | * only for the passed in crtc iff we change anything else than just |
6844 | * disable crtcs. |
6841 | * disable crtcs. |
6845 | * |
6842 | * |
6846 | * This is actually not true, to be fully compatible with the old crtc |
6843 | * This is actually not true, to be fully compatible with the old crtc |
6847 | * helper we automatically disable _any_ output (i.e. doesn't need to be |
6844 | * helper we automatically disable _any_ output (i.e. doesn't need to be |
6848 | * connected to the crtc we're modesetting on) if it's disconnected. |
6845 | * connected to the crtc we're modesetting on) if it's disconnected. |
6849 | * Which is a rather nutty api (since changed the output configuration |
6846 | * Which is a rather nutty api (since changed the output configuration |
6850 | * without userspace's explicit request can lead to confusion), but |
6847 | * without userspace's explicit request can lead to confusion), but |
6851 | * alas. Hence we currently need to modeset on all pipes we prepare. */ |
6848 | * alas. Hence we currently need to modeset on all pipes we prepare. */ |
6852 | if (*prepare_pipes) |
6849 | if (*prepare_pipes) |
6853 | *modeset_pipes = *prepare_pipes; |
6850 | *modeset_pipes = *prepare_pipes; |
6854 | 6851 | ||
6855 | /* ... and mask these out. */ |
6852 | /* ... and mask these out. */ |
6856 | *modeset_pipes &= ~(*disable_pipes); |
6853 | *modeset_pipes &= ~(*disable_pipes); |
6857 | *prepare_pipes &= ~(*disable_pipes); |
6854 | *prepare_pipes &= ~(*disable_pipes); |
6858 | } |
6855 | } |
6859 | 6856 | ||
6860 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
6857 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
6861 | { |
6858 | { |
6862 | struct drm_encoder *encoder; |
6859 | struct drm_encoder *encoder; |
6863 | struct drm_device *dev = crtc->dev; |
6860 | struct drm_device *dev = crtc->dev; |
6864 | 6861 | ||
6865 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
6862 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
6866 | if (encoder->crtc == crtc) |
6863 | if (encoder->crtc == crtc) |
6867 | return true; |
6864 | return true; |
6868 | 6865 | ||
6869 | return false; |
6866 | return false; |
6870 | } |
6867 | } |
6871 | 6868 | ||
6872 | static void |
6869 | static void |
6873 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
6870 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
6874 | { |
6871 | { |
6875 | struct intel_encoder *intel_encoder; |
6872 | struct intel_encoder *intel_encoder; |
6876 | struct intel_crtc *intel_crtc; |
6873 | struct intel_crtc *intel_crtc; |
6877 | struct drm_connector *connector; |
6874 | struct drm_connector *connector; |
6878 | 6875 | ||
6879 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
6876 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
6880 | base.head) { |
6877 | base.head) { |
6881 | if (!intel_encoder->base.crtc) |
6878 | if (!intel_encoder->base.crtc) |
6882 | continue; |
6879 | continue; |
6883 | 6880 | ||
6884 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
6881 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
6885 | 6882 | ||
6886 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
6883 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
6887 | intel_encoder->connectors_active = false; |
6884 | intel_encoder->connectors_active = false; |
6888 | } |
6885 | } |
6889 | 6886 | ||
6890 | intel_modeset_commit_output_state(dev); |
6887 | intel_modeset_commit_output_state(dev); |
6891 | 6888 | ||
6892 | /* Update computed state. */ |
6889 | /* Update computed state. */ |
6893 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
6890 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
6894 | base.head) { |
6891 | base.head) { |
6895 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
6892 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
6896 | } |
6893 | } |
6897 | 6894 | ||
6898 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
6895 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
6899 | if (!connector->encoder || !connector->encoder->crtc) |
6896 | if (!connector->encoder || !connector->encoder->crtc) |
6900 | continue; |
6897 | continue; |
6901 | 6898 | ||
6902 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
6899 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
6903 | 6900 | ||
6904 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
6901 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
6905 | struct drm_property *dpms_property = |
6902 | struct drm_property *dpms_property = |
6906 | dev->mode_config.dpms_property; |
6903 | dev->mode_config.dpms_property; |
6907 | 6904 | ||
6908 | connector->dpms = DRM_MODE_DPMS_ON; |
6905 | connector->dpms = DRM_MODE_DPMS_ON; |
6909 | drm_connector_property_set_value(connector, |
6906 | drm_connector_property_set_value(connector, |
6910 | dpms_property, |
6907 | dpms_property, |
6911 | DRM_MODE_DPMS_ON); |
6908 | DRM_MODE_DPMS_ON); |
6912 | 6909 | ||
6913 | intel_encoder = to_intel_encoder(connector->encoder); |
6910 | intel_encoder = to_intel_encoder(connector->encoder); |
6914 | intel_encoder->connectors_active = true; |
6911 | intel_encoder->connectors_active = true; |
6915 | } |
6912 | } |
6916 | } |
6913 | } |
6917 | 6914 | ||
6918 | } |
6915 | } |
6919 | 6916 | ||
6920 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
6917 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
6921 | list_for_each_entry((intel_crtc), \ |
6918 | list_for_each_entry((intel_crtc), \ |
6922 | &(dev)->mode_config.crtc_list, \ |
6919 | &(dev)->mode_config.crtc_list, \ |
6923 | base.head) \ |
6920 | base.head) \ |
6924 | if (mask & (1 <<(intel_crtc)->pipe)) \ |
6921 | if (mask & (1 <<(intel_crtc)->pipe)) \ |
6925 | 6922 | ||
6926 | void |
6923 | void |
6927 | intel_modeset_check_state(struct drm_device *dev) |
6924 | intel_modeset_check_state(struct drm_device *dev) |
6928 | { |
6925 | { |
6929 | struct intel_crtc *crtc; |
6926 | struct intel_crtc *crtc; |
6930 | struct intel_encoder *encoder; |
6927 | struct intel_encoder *encoder; |
6931 | struct intel_connector *connector; |
6928 | struct intel_connector *connector; |
6932 | 6929 | ||
6933 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6930 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6934 | base.head) { |
6931 | base.head) { |
6935 | /* This also checks the encoder/connector hw state with the |
6932 | /* This also checks the encoder/connector hw state with the |
6936 | * ->get_hw_state callbacks. */ |
6933 | * ->get_hw_state callbacks. */ |
6937 | intel_connector_check_state(connector); |
6934 | intel_connector_check_state(connector); |
6938 | 6935 | ||
6939 | WARN(&connector->new_encoder->base != connector->base.encoder, |
6936 | WARN(&connector->new_encoder->base != connector->base.encoder, |
6940 | "connector's staged encoder doesn't match current encoder\n"); |
6937 | "connector's staged encoder doesn't match current encoder\n"); |
6941 | } |
6938 | } |
6942 | 6939 | ||
6943 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6940 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
6944 | base.head) { |
6941 | base.head) { |
6945 | bool enabled = false; |
6942 | bool enabled = false; |
6946 | bool active = false; |
6943 | bool active = false; |
6947 | enum pipe pipe, tracked_pipe; |
6944 | enum pipe pipe, tracked_pipe; |
6948 | 6945 | ||
6949 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
6946 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
6950 | encoder->base.base.id, |
6947 | encoder->base.base.id, |
6951 | drm_get_encoder_name(&encoder->base)); |
6948 | drm_get_encoder_name(&encoder->base)); |
6952 | 6949 | ||
6953 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
6950 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
6954 | "encoder's stage crtc doesn't match current crtc\n"); |
6951 | "encoder's stage crtc doesn't match current crtc\n"); |
6955 | WARN(encoder->connectors_active && !encoder->base.crtc, |
6952 | WARN(encoder->connectors_active && !encoder->base.crtc, |
6956 | "encoder's active_connectors set, but no crtc\n"); |
6953 | "encoder's active_connectors set, but no crtc\n"); |
6957 | 6954 | ||
6958 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6955 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
6959 | base.head) { |
6956 | base.head) { |
6960 | if (connector->base.encoder != &encoder->base) |
6957 | if (connector->base.encoder != &encoder->base) |
6961 | continue; |
6958 | continue; |
6962 | enabled = true; |
6959 | enabled = true; |
6963 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
6960 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
6964 | active = true; |
6961 | active = true; |
6965 | } |
6962 | } |
6966 | WARN(!!encoder->base.crtc != enabled, |
6963 | WARN(!!encoder->base.crtc != enabled, |
6967 | "encoder's enabled state mismatch " |
6964 | "encoder's enabled state mismatch " |
6968 | "(expected %i, found %i)\n", |
6965 | "(expected %i, found %i)\n", |
6969 | !!encoder->base.crtc, enabled); |
6966 | !!encoder->base.crtc, enabled); |
6970 | WARN(active && !encoder->base.crtc, |
6967 | WARN(active && !encoder->base.crtc, |
6971 | "active encoder with no crtc\n"); |
6968 | "active encoder with no crtc\n"); |
6972 | 6969 | ||
6973 | WARN(encoder->connectors_active != active, |
6970 | WARN(encoder->connectors_active != active, |
6974 | "encoder's computed active state doesn't match tracked active state " |
6971 | "encoder's computed active state doesn't match tracked active state " |
6975 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
6972 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
6976 | 6973 | ||
6977 | active = encoder->get_hw_state(encoder, &pipe); |
6974 | active = encoder->get_hw_state(encoder, &pipe); |
6978 | WARN(active != encoder->connectors_active, |
6975 | WARN(active != encoder->connectors_active, |
6979 | "encoder's hw state doesn't match sw tracking " |
6976 | "encoder's hw state doesn't match sw tracking " |
6980 | "(expected %i, found %i)\n", |
6977 | "(expected %i, found %i)\n", |
6981 | encoder->connectors_active, active); |
6978 | encoder->connectors_active, active); |
6982 | 6979 | ||
6983 | if (!encoder->base.crtc) |
6980 | if (!encoder->base.crtc) |
6984 | continue; |
6981 | continue; |
6985 | 6982 | ||
6986 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
6983 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
6987 | WARN(active && pipe != tracked_pipe, |
6984 | WARN(active && pipe != tracked_pipe, |
6988 | "active encoder's pipe doesn't match" |
6985 | "active encoder's pipe doesn't match" |
6989 | "(expected %i, found %i)\n", |
6986 | "(expected %i, found %i)\n", |
6990 | tracked_pipe, pipe); |
6987 | tracked_pipe, pipe); |
6991 | 6988 | ||
6992 | } |
6989 | } |
6993 | 6990 | ||
6994 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
6991 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
6995 | base.head) { |
6992 | base.head) { |
6996 | bool enabled = false; |
6993 | bool enabled = false; |
6997 | bool active = false; |
6994 | bool active = false; |
6998 | 6995 | ||
6999 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
6996 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
7000 | crtc->base.base.id); |
6997 | crtc->base.base.id); |
7001 | 6998 | ||
7002 | WARN(crtc->active && !crtc->base.enabled, |
6999 | WARN(crtc->active && !crtc->base.enabled, |
7003 | "active crtc, but not enabled in sw tracking\n"); |
7000 | "active crtc, but not enabled in sw tracking\n"); |
7004 | 7001 | ||
7005 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7002 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7006 | base.head) { |
7003 | base.head) { |
7007 | if (encoder->base.crtc != &crtc->base) |
7004 | if (encoder->base.crtc != &crtc->base) |
7008 | continue; |
7005 | continue; |
7009 | enabled = true; |
7006 | enabled = true; |
7010 | if (encoder->connectors_active) |
7007 | if (encoder->connectors_active) |
7011 | active = true; |
7008 | active = true; |
7012 | } |
7009 | } |
7013 | WARN(active != crtc->active, |
7010 | WARN(active != crtc->active, |
7014 | "crtc's computed active state doesn't match tracked active state " |
7011 | "crtc's computed active state doesn't match tracked active state " |
7015 | "(expected %i, found %i)\n", active, crtc->active); |
7012 | "(expected %i, found %i)\n", active, crtc->active); |
7016 | WARN(enabled != crtc->base.enabled, |
7013 | WARN(enabled != crtc->base.enabled, |
7017 | "crtc's computed enabled state doesn't match tracked enabled state " |
7014 | "crtc's computed enabled state doesn't match tracked enabled state " |
7018 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
7015 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
7019 | 7016 | ||
7020 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); |
7017 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); |
7021 | } |
7018 | } |
7022 | } |
7019 | } |
7023 | 7020 | ||
7024 | bool intel_set_mode(struct drm_crtc *crtc, |
7021 | bool intel_set_mode(struct drm_crtc *crtc, |
7025 | struct drm_display_mode *mode, |
7022 | struct drm_display_mode *mode, |
7026 | int x, int y, struct drm_framebuffer *fb) |
7023 | int x, int y, struct drm_framebuffer *fb) |
7027 | { |
7024 | { |
7028 | struct drm_device *dev = crtc->dev; |
7025 | struct drm_device *dev = crtc->dev; |
7029 | drm_i915_private_t *dev_priv = dev->dev_private; |
7026 | drm_i915_private_t *dev_priv = dev->dev_private; |
7030 | struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode; |
7027 | struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode; |
7031 | struct drm_encoder_helper_funcs *encoder_funcs; |
7028 | struct drm_encoder_helper_funcs *encoder_funcs; |
7032 | struct drm_encoder *encoder; |
7029 | struct drm_encoder *encoder; |
7033 | struct intel_crtc *intel_crtc; |
7030 | struct intel_crtc *intel_crtc; |
7034 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
7031 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
7035 | bool ret = true; |
7032 | bool ret = true; |
7036 | 7033 | ||
7037 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
7034 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
7038 | &prepare_pipes, &disable_pipes); |
7035 | &prepare_pipes, &disable_pipes); |
7039 | 7036 | ||
7040 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
7037 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
7041 | modeset_pipes, prepare_pipes, disable_pipes); |
7038 | modeset_pipes, prepare_pipes, disable_pipes); |
7042 | 7039 | ||
7043 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
7040 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
7044 | intel_crtc_disable(&intel_crtc->base); |
7041 | intel_crtc_disable(&intel_crtc->base); |
7045 | 7042 | ||
7046 | saved_hwmode = crtc->hwmode; |
7043 | saved_hwmode = crtc->hwmode; |
7047 | saved_mode = crtc->mode; |
7044 | saved_mode = crtc->mode; |
7048 | 7045 | ||
7049 | /* Hack: Because we don't (yet) support global modeset on multiple |
7046 | /* Hack: Because we don't (yet) support global modeset on multiple |
7050 | * crtcs, we don't keep track of the new mode for more than one crtc. |
7047 | * crtcs, we don't keep track of the new mode for more than one crtc. |
7051 | * Hence simply check whether any bit is set in modeset_pipes in all the |
7048 | * Hence simply check whether any bit is set in modeset_pipes in all the |
7052 | * pieces of code that are not yet converted to deal with mutliple crtcs |
7049 | * pieces of code that are not yet converted to deal with mutliple crtcs |
7053 | * changing their mode at the same time. */ |
7050 | * changing their mode at the same time. */ |
7054 | adjusted_mode = NULL; |
7051 | adjusted_mode = NULL; |
7055 | if (modeset_pipes) { |
7052 | if (modeset_pipes) { |
7056 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); |
7053 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); |
7057 | if (IS_ERR(adjusted_mode)) { |
7054 | if (IS_ERR(adjusted_mode)) { |
7058 | return false; |
7055 | return false; |
7059 | } |
7056 | } |
7060 | } |
7057 | } |
7061 | 7058 | ||
7062 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7059 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7063 | if (intel_crtc->base.enabled) |
7060 | if (intel_crtc->base.enabled) |
7064 | dev_priv->display.crtc_disable(&intel_crtc->base); |
7061 | dev_priv->display.crtc_disable(&intel_crtc->base); |
7065 | } |
7062 | } |
7066 | 7063 | ||
7067 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7064 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7068 | * to set it here already despite that we pass it down the callchain. |
7065 | * to set it here already despite that we pass it down the callchain. |
7069 | */ |
7066 | */ |
7070 | if (modeset_pipes) |
7067 | if (modeset_pipes) |
7071 | crtc->mode = *mode; |
7068 | crtc->mode = *mode; |
7072 | 7069 | ||
7073 | /* Only after disabling all output pipelines that will be changed can we |
7070 | /* Only after disabling all output pipelines that will be changed can we |
7074 | * update the the output configuration. */ |
7071 | * update the the output configuration. */ |
7075 | intel_modeset_update_state(dev, prepare_pipes); |
7072 | intel_modeset_update_state(dev, prepare_pipes); |
7076 | 7073 | ||
7077 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7074 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7078 | * on the DPLL. |
7075 | * on the DPLL. |
7079 | */ |
7076 | */ |
7080 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
7077 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
7081 | ret = !intel_crtc_mode_set(&intel_crtc->base, |
7078 | ret = !intel_crtc_mode_set(&intel_crtc->base, |
7082 | mode, adjusted_mode, |
7079 | mode, adjusted_mode, |
7083 | x, y, fb); |
7080 | x, y, fb); |
7084 | if (!ret) |
7081 | if (!ret) |
7085 | goto done; |
7082 | goto done; |
7086 | 7083 | ||
7087 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
7084 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
7088 | 7085 | ||
7089 | if (encoder->crtc != &intel_crtc->base) |
7086 | if (encoder->crtc != &intel_crtc->base) |
7090 | continue; |
7087 | continue; |
7091 | 7088 | ||
7092 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
7089 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
7093 | encoder->base.id, drm_get_encoder_name(encoder), |
7090 | encoder->base.id, drm_get_encoder_name(encoder), |
7094 | mode->base.id, mode->name); |
7091 | mode->base.id, mode->name); |
7095 | encoder_funcs = encoder->helper_private; |
7092 | encoder_funcs = encoder->helper_private; |
7096 | encoder_funcs->mode_set(encoder, mode, adjusted_mode); |
7093 | encoder_funcs->mode_set(encoder, mode, adjusted_mode); |
7097 | } |
7094 | } |
7098 | } |
7095 | } |
7099 | 7096 | ||
7100 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
7097 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
7101 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7098 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7102 | dev_priv->display.crtc_enable(&intel_crtc->base); |
7099 | dev_priv->display.crtc_enable(&intel_crtc->base); |
7103 | 7100 | ||
7104 | if (modeset_pipes) { |
7101 | if (modeset_pipes) { |
7105 | /* Store real post-adjustment hardware mode. */ |
7102 | /* Store real post-adjustment hardware mode. */ |
7106 | crtc->hwmode = *adjusted_mode; |
7103 | crtc->hwmode = *adjusted_mode; |
7107 | 7104 | ||
7108 | /* Calculate and store various constants which |
7105 | /* Calculate and store various constants which |
7109 | * are later needed by vblank and swap-completion |
7106 | * are later needed by vblank and swap-completion |
7110 | * timestamping. They are derived from true hwmode. |
7107 | * timestamping. They are derived from true hwmode. |
7111 | */ |
7108 | */ |
7112 | drm_calc_timestamping_constants(crtc); |
7109 | drm_calc_timestamping_constants(crtc); |
7113 | } |
7110 | } |
7114 | 7111 | ||
7115 | /* FIXME: add subpixel order */ |
7112 | /* FIXME: add subpixel order */ |
7116 | done: |
7113 | done: |
7117 | drm_mode_destroy(dev, adjusted_mode); |
7114 | drm_mode_destroy(dev, adjusted_mode); |
7118 | if (!ret && crtc->enabled) { |
7115 | if (!ret && crtc->enabled) { |
7119 | crtc->hwmode = saved_hwmode; |
7116 | crtc->hwmode = saved_hwmode; |
7120 | crtc->mode = saved_mode; |
7117 | crtc->mode = saved_mode; |
7121 | } else { |
7118 | } else { |
7122 | intel_modeset_check_state(dev); |
7119 | intel_modeset_check_state(dev); |
7123 | } |
7120 | } |
7124 | 7121 | ||
7125 | return ret; |
7122 | return ret; |
7126 | } |
7123 | } |
7127 | 7124 | ||
7128 | #undef for_each_intel_crtc_masked |
7125 | #undef for_each_intel_crtc_masked |
7129 | 7126 | ||
7130 | static void intel_set_config_free(struct intel_set_config *config) |
7127 | static void intel_set_config_free(struct intel_set_config *config) |
7131 | { |
7128 | { |
7132 | if (!config) |
7129 | if (!config) |
7133 | return; |
7130 | return; |
7134 | 7131 | ||
7135 | kfree(config->save_connector_encoders); |
7132 | kfree(config->save_connector_encoders); |
7136 | kfree(config->save_encoder_crtcs); |
7133 | kfree(config->save_encoder_crtcs); |
7137 | kfree(config); |
7134 | kfree(config); |
7138 | } |
7135 | } |
7139 | 7136 | ||
7140 | static int intel_set_config_save_state(struct drm_device *dev, |
7137 | static int intel_set_config_save_state(struct drm_device *dev, |
7141 | struct intel_set_config *config) |
7138 | struct intel_set_config *config) |
7142 | { |
7139 | { |
7143 | struct drm_encoder *encoder; |
7140 | struct drm_encoder *encoder; |
7144 | struct drm_connector *connector; |
7141 | struct drm_connector *connector; |
7145 | int count; |
7142 | int count; |
7146 | 7143 | ||
7147 | config->save_encoder_crtcs = |
7144 | config->save_encoder_crtcs = |
7148 | kcalloc(dev->mode_config.num_encoder, |
7145 | kcalloc(dev->mode_config.num_encoder, |
7149 | sizeof(struct drm_crtc *), GFP_KERNEL); |
7146 | sizeof(struct drm_crtc *), GFP_KERNEL); |
7150 | if (!config->save_encoder_crtcs) |
7147 | if (!config->save_encoder_crtcs) |
7151 | return -ENOMEM; |
7148 | return -ENOMEM; |
7152 | 7149 | ||
7153 | config->save_connector_encoders = |
7150 | config->save_connector_encoders = |
7154 | kcalloc(dev->mode_config.num_connector, |
7151 | kcalloc(dev->mode_config.num_connector, |
7155 | sizeof(struct drm_encoder *), GFP_KERNEL); |
7152 | sizeof(struct drm_encoder *), GFP_KERNEL); |
7156 | if (!config->save_connector_encoders) |
7153 | if (!config->save_connector_encoders) |
7157 | return -ENOMEM; |
7154 | return -ENOMEM; |
7158 | 7155 | ||
7159 | /* Copy data. Note that driver private data is not affected. |
7156 | /* Copy data. Note that driver private data is not affected. |
7160 | * Should anything bad happen only the expected state is |
7157 | * Should anything bad happen only the expected state is |
7161 | * restored, not the drivers personal bookkeeping. |
7158 | * restored, not the drivers personal bookkeeping. |
7162 | */ |
7159 | */ |
7163 | count = 0; |
7160 | count = 0; |
7164 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
7161 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
7165 | config->save_encoder_crtcs[count++] = encoder->crtc; |
7162 | config->save_encoder_crtcs[count++] = encoder->crtc; |
7166 | } |
7163 | } |
7167 | 7164 | ||
7168 | count = 0; |
7165 | count = 0; |
7169 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
7166 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
7170 | config->save_connector_encoders[count++] = connector->encoder; |
7167 | config->save_connector_encoders[count++] = connector->encoder; |
7171 | } |
7168 | } |
7172 | 7169 | ||
7173 | return 0; |
7170 | return 0; |
7174 | } |
7171 | } |
7175 | 7172 | ||
7176 | static void intel_set_config_restore_state(struct drm_device *dev, |
7173 | static void intel_set_config_restore_state(struct drm_device *dev, |
7177 | struct intel_set_config *config) |
7174 | struct intel_set_config *config) |
7178 | { |
7175 | { |
7179 | struct intel_encoder *encoder; |
7176 | struct intel_encoder *encoder; |
7180 | struct intel_connector *connector; |
7177 | struct intel_connector *connector; |
7181 | int count; |
7178 | int count; |
7182 | 7179 | ||
7183 | count = 0; |
7180 | count = 0; |
7184 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7181 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7185 | encoder->new_crtc = |
7182 | encoder->new_crtc = |
7186 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
7183 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
7187 | } |
7184 | } |
7188 | 7185 | ||
7189 | count = 0; |
7186 | count = 0; |
7190 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7187 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7191 | connector->new_encoder = |
7188 | connector->new_encoder = |
7192 | to_intel_encoder(config->save_connector_encoders[count++]); |
7189 | to_intel_encoder(config->save_connector_encoders[count++]); |
7193 | } |
7190 | } |
7194 | } |
7191 | } |
7195 | 7192 | ||
7196 | static void |
7193 | static void |
7197 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
7194 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
7198 | struct intel_set_config *config) |
7195 | struct intel_set_config *config) |
7199 | { |
7196 | { |
7200 | 7197 | ||
7201 | /* We should be able to check here if the fb has the same properties |
7198 | /* We should be able to check here if the fb has the same properties |
7202 | * and then just flip_or_move it */ |
7199 | * and then just flip_or_move it */ |
7203 | if (set->crtc->fb != set->fb) { |
7200 | if (set->crtc->fb != set->fb) { |
7204 | /* If we have no fb then treat it as a full mode set */ |
7201 | /* If we have no fb then treat it as a full mode set */ |
7205 | if (set->crtc->fb == NULL) { |
7202 | if (set->crtc->fb == NULL) { |
7206 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); |
7203 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); |
7207 | config->mode_changed = true; |
7204 | config->mode_changed = true; |
7208 | } else if (set->fb == NULL) { |
7205 | } else if (set->fb == NULL) { |
7209 | config->mode_changed = true; |
7206 | config->mode_changed = true; |
7210 | } else if (set->fb->depth != set->crtc->fb->depth) { |
7207 | } else if (set->fb->depth != set->crtc->fb->depth) { |
7211 | config->mode_changed = true; |
7208 | config->mode_changed = true; |
7212 | } else if (set->fb->bits_per_pixel != |
7209 | } else if (set->fb->bits_per_pixel != |
7213 | set->crtc->fb->bits_per_pixel) { |
7210 | set->crtc->fb->bits_per_pixel) { |
7214 | config->mode_changed = true; |
7211 | config->mode_changed = true; |
7215 | } else |
7212 | } else |
7216 | config->fb_changed = true; |
7213 | config->fb_changed = true; |
7217 | } |
7214 | } |
7218 | 7215 | ||
7219 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
7216 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
7220 | config->fb_changed = true; |
7217 | config->fb_changed = true; |
7221 | 7218 | ||
7222 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
7219 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
7223 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
7220 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
7224 | drm_mode_debug_printmodeline(&set->crtc->mode); |
7221 | drm_mode_debug_printmodeline(&set->crtc->mode); |
7225 | drm_mode_debug_printmodeline(set->mode); |
7222 | drm_mode_debug_printmodeline(set->mode); |
7226 | config->mode_changed = true; |
7223 | config->mode_changed = true; |
7227 | } |
7224 | } |
7228 | } |
7225 | } |
7229 | 7226 | ||
7230 | static int |
7227 | static int |
7231 | intel_modeset_stage_output_state(struct drm_device *dev, |
7228 | intel_modeset_stage_output_state(struct drm_device *dev, |
7232 | struct drm_mode_set *set, |
7229 | struct drm_mode_set *set, |
7233 | struct intel_set_config *config) |
7230 | struct intel_set_config *config) |
7234 | { |
7231 | { |
7235 | struct drm_crtc *new_crtc; |
7232 | struct drm_crtc *new_crtc; |
7236 | struct intel_connector *connector; |
7233 | struct intel_connector *connector; |
7237 | struct intel_encoder *encoder; |
7234 | struct intel_encoder *encoder; |
7238 | int count, ro; |
7235 | int count, ro; |
7239 | 7236 | ||
7240 | /* The upper layers ensure that we either disabl a crtc or have a list |
7237 | /* The upper layers ensure that we either disabl a crtc or have a list |
7241 | * of connectors. For paranoia, double-check this. */ |
7238 | * of connectors. For paranoia, double-check this. */ |
7242 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
7239 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
7243 | WARN_ON(set->fb && (set->num_connectors == 0)); |
7240 | WARN_ON(set->fb && (set->num_connectors == 0)); |
7244 | 7241 | ||
7245 | count = 0; |
7242 | count = 0; |
7246 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7243 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7247 | base.head) { |
7244 | base.head) { |
7248 | /* Otherwise traverse passed in connector list and get encoders |
7245 | /* Otherwise traverse passed in connector list and get encoders |
7249 | * for them. */ |
7246 | * for them. */ |
7250 | for (ro = 0; ro < set->num_connectors; ro++) { |
7247 | for (ro = 0; ro < set->num_connectors; ro++) { |
7251 | if (set->connectors[ro] == &connector->base) { |
7248 | if (set->connectors[ro] == &connector->base) { |
7252 | connector->new_encoder = connector->encoder; |
7249 | connector->new_encoder = connector->encoder; |
7253 | break; |
7250 | break; |
7254 | } |
7251 | } |
7255 | } |
7252 | } |
7256 | 7253 | ||
7257 | /* If we disable the crtc, disable all its connectors. Also, if |
7254 | /* If we disable the crtc, disable all its connectors. Also, if |
7258 | * the connector is on the changing crtc but not on the new |
7255 | * the connector is on the changing crtc but not on the new |
7259 | * connector list, disable it. */ |
7256 | * connector list, disable it. */ |
7260 | if ((!set->fb || ro == set->num_connectors) && |
7257 | if ((!set->fb || ro == set->num_connectors) && |
7261 | connector->base.encoder && |
7258 | connector->base.encoder && |
7262 | connector->base.encoder->crtc == set->crtc) { |
7259 | connector->base.encoder->crtc == set->crtc) { |
7263 | connector->new_encoder = NULL; |
7260 | connector->new_encoder = NULL; |
7264 | 7261 | ||
7265 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
7262 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
7266 | connector->base.base.id, |
7263 | connector->base.base.id, |
7267 | drm_get_connector_name(&connector->base)); |
7264 | drm_get_connector_name(&connector->base)); |
7268 | } |
7265 | } |
7269 | 7266 | ||
7270 | 7267 | ||
7271 | if (&connector->new_encoder->base != connector->base.encoder) { |
7268 | if (&connector->new_encoder->base != connector->base.encoder) { |
7272 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
7269 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
7273 | config->mode_changed = true; |
7270 | config->mode_changed = true; |
7274 | } |
7271 | } |
7275 | 7272 | ||
7276 | /* Disable all disconnected encoders. */ |
7273 | /* Disable all disconnected encoders. */ |
7277 | if (connector->base.status == connector_status_disconnected) |
7274 | if (connector->base.status == connector_status_disconnected) |
7278 | connector->new_encoder = NULL; |
7275 | connector->new_encoder = NULL; |
7279 | } |
7276 | } |
7280 | /* connector->new_encoder is now updated for all connectors. */ |
7277 | /* connector->new_encoder is now updated for all connectors. */ |
7281 | 7278 | ||
7282 | /* Update crtc of enabled connectors. */ |
7279 | /* Update crtc of enabled connectors. */ |
7283 | count = 0; |
7280 | count = 0; |
7284 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7281 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7285 | base.head) { |
7282 | base.head) { |
7286 | if (!connector->new_encoder) |
7283 | if (!connector->new_encoder) |
7287 | continue; |
7284 | continue; |
7288 | 7285 | ||
7289 | new_crtc = connector->new_encoder->base.crtc; |
7286 | new_crtc = connector->new_encoder->base.crtc; |
7290 | 7287 | ||
7291 | for (ro = 0; ro < set->num_connectors; ro++) { |
7288 | for (ro = 0; ro < set->num_connectors; ro++) { |
7292 | if (set->connectors[ro] == &connector->base) |
7289 | if (set->connectors[ro] == &connector->base) |
7293 | new_crtc = set->crtc; |
7290 | new_crtc = set->crtc; |
7294 | } |
7291 | } |
7295 | 7292 | ||
7296 | /* Make sure the new CRTC will work with the encoder */ |
7293 | /* Make sure the new CRTC will work with the encoder */ |
7297 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7294 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7298 | new_crtc)) { |
7295 | new_crtc)) { |
7299 | return -EINVAL; |
7296 | return -EINVAL; |
7300 | } |
7297 | } |
7301 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7298 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7302 | 7299 | ||
7303 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
7300 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
7304 | connector->base.base.id, |
7301 | connector->base.base.id, |
7305 | drm_get_connector_name(&connector->base), |
7302 | drm_get_connector_name(&connector->base), |
7306 | new_crtc->base.id); |
7303 | new_crtc->base.id); |
7307 | } |
7304 | } |
7308 | 7305 | ||
7309 | /* Check for any encoders that needs to be disabled. */ |
7306 | /* Check for any encoders that needs to be disabled. */ |
7310 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7307 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7311 | base.head) { |
7308 | base.head) { |
7312 | list_for_each_entry(connector, |
7309 | list_for_each_entry(connector, |
7313 | &dev->mode_config.connector_list, |
7310 | &dev->mode_config.connector_list, |
7314 | base.head) { |
7311 | base.head) { |
7315 | if (connector->new_encoder == encoder) { |
7312 | if (connector->new_encoder == encoder) { |
7316 | WARN_ON(!connector->new_encoder->new_crtc); |
7313 | WARN_ON(!connector->new_encoder->new_crtc); |
7317 | 7314 | ||
7318 | goto next_encoder; |
7315 | goto next_encoder; |
7319 | } |
7316 | } |
7320 | } |
7317 | } |
7321 | encoder->new_crtc = NULL; |
7318 | encoder->new_crtc = NULL; |
7322 | next_encoder: |
7319 | next_encoder: |
7323 | /* Only now check for crtc changes so we don't miss encoders |
7320 | /* Only now check for crtc changes so we don't miss encoders |
7324 | * that will be disabled. */ |
7321 | * that will be disabled. */ |
7325 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
7322 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
7326 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
7323 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
7327 | config->mode_changed = true; |
7324 | config->mode_changed = true; |
7328 | } |
7325 | } |
7329 | } |
7326 | } |
7330 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
7327 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
7331 | 7328 | ||
7332 | return 0; |
7329 | return 0; |
7333 | } |
7330 | } |
7334 | 7331 | ||
7335 | static int intel_crtc_set_config(struct drm_mode_set *set) |
7332 | static int intel_crtc_set_config(struct drm_mode_set *set) |
7336 | { |
7333 | { |
7337 | struct drm_device *dev; |
7334 | struct drm_device *dev; |
7338 | struct drm_mode_set save_set; |
7335 | struct drm_mode_set save_set; |
7339 | struct intel_set_config *config; |
7336 | struct intel_set_config *config; |
7340 | int ret; |
7337 | int ret; |
7341 | 7338 | ||
7342 | BUG_ON(!set); |
7339 | BUG_ON(!set); |
7343 | BUG_ON(!set->crtc); |
7340 | BUG_ON(!set->crtc); |
7344 | BUG_ON(!set->crtc->helper_private); |
7341 | BUG_ON(!set->crtc->helper_private); |
7345 | 7342 | ||
7346 | if (!set->mode) |
7343 | if (!set->mode) |
7347 | set->fb = NULL; |
7344 | set->fb = NULL; |
7348 | 7345 | ||
7349 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7346 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7350 | * Unfortunately the crtc helper doesn't do much at all for this case, |
7347 | * Unfortunately the crtc helper doesn't do much at all for this case, |
7351 | * so we have to cope with this madness until the fb helper is fixed up. */ |
7348 | * so we have to cope with this madness until the fb helper is fixed up. */ |
7352 | if (set->fb && set->num_connectors == 0) |
7349 | if (set->fb && set->num_connectors == 0) |
7353 | return 0; |
7350 | return 0; |
7354 | 7351 | ||
7355 | if (set->fb) { |
7352 | if (set->fb) { |
7356 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
7353 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
7357 | set->crtc->base.id, set->fb->base.id, |
7354 | set->crtc->base.id, set->fb->base.id, |
7358 | (int)set->num_connectors, set->x, set->y); |
7355 | (int)set->num_connectors, set->x, set->y); |
7359 | } else { |
7356 | } else { |
7360 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
7357 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
7361 | } |
7358 | } |
7362 | 7359 | ||
7363 | dev = set->crtc->dev; |
7360 | dev = set->crtc->dev; |
7364 | 7361 | ||
7365 | ret = -ENOMEM; |
7362 | ret = -ENOMEM; |
7366 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
7363 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
7367 | if (!config) |
7364 | if (!config) |
7368 | goto out_config; |
7365 | goto out_config; |
7369 | 7366 | ||
7370 | ret = intel_set_config_save_state(dev, config); |
7367 | ret = intel_set_config_save_state(dev, config); |
7371 | if (ret) |
7368 | if (ret) |
7372 | goto out_config; |
7369 | goto out_config; |
7373 | 7370 | ||
7374 | save_set.crtc = set->crtc; |
7371 | save_set.crtc = set->crtc; |
7375 | save_set.mode = &set->crtc->mode; |
7372 | save_set.mode = &set->crtc->mode; |
7376 | save_set.x = set->crtc->x; |
7373 | save_set.x = set->crtc->x; |
7377 | save_set.y = set->crtc->y; |
7374 | save_set.y = set->crtc->y; |
7378 | save_set.fb = set->crtc->fb; |
7375 | save_set.fb = set->crtc->fb; |
7379 | 7376 | ||
7380 | /* Compute whether we need a full modeset, only an fb base update or no |
7377 | /* Compute whether we need a full modeset, only an fb base update or no |
7381 | * change at all. In the future we might also check whether only the |
7378 | * change at all. In the future we might also check whether only the |
7382 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
7379 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
7383 | * such cases. */ |
7380 | * such cases. */ |
7384 | intel_set_config_compute_mode_changes(set, config); |
7381 | intel_set_config_compute_mode_changes(set, config); |
7385 | 7382 | ||
7386 | ret = intel_modeset_stage_output_state(dev, set, config); |
7383 | ret = intel_modeset_stage_output_state(dev, set, config); |
7387 | if (ret) |
7384 | if (ret) |
7388 | goto fail; |
7385 | goto fail; |
7389 | 7386 | ||
7390 | if (config->mode_changed) { |
7387 | if (config->mode_changed) { |
7391 | if (set->mode) { |
7388 | if (set->mode) { |
7392 | DRM_DEBUG_KMS("attempting to set mode from" |
7389 | DRM_DEBUG_KMS("attempting to set mode from" |
7393 | " userspace\n"); |
7390 | " userspace\n"); |
7394 | drm_mode_debug_printmodeline(set->mode); |
7391 | drm_mode_debug_printmodeline(set->mode); |
7395 | } |
7392 | } |
7396 | 7393 | ||
7397 | if (!intel_set_mode(set->crtc, set->mode, |
7394 | if (!intel_set_mode(set->crtc, set->mode, |
7398 | set->x, set->y, set->fb)) { |
7395 | set->x, set->y, set->fb)) { |
7399 | DRM_ERROR("failed to set mode on [CRTC:%d]\n", |
7396 | DRM_ERROR("failed to set mode on [CRTC:%d]\n", |
7400 | set->crtc->base.id); |
7397 | set->crtc->base.id); |
7401 | ret = -EINVAL; |
7398 | ret = -EINVAL; |
7402 | goto fail; |
7399 | goto fail; |
7403 | } |
7400 | } |
7404 | } else if (config->fb_changed) { |
7401 | } else if (config->fb_changed) { |
7405 | ret = intel_pipe_set_base(set->crtc, |
7402 | ret = intel_pipe_set_base(set->crtc, |
7406 | set->x, set->y, set->fb); |
7403 | set->x, set->y, set->fb); |
7407 | } |
7404 | } |
7408 | 7405 | ||
7409 | intel_set_config_free(config); |
7406 | intel_set_config_free(config); |
7410 | 7407 | ||
7411 | return 0; |
7408 | return 0; |
7412 | 7409 | ||
7413 | fail: |
7410 | fail: |
7414 | intel_set_config_restore_state(dev, config); |
7411 | intel_set_config_restore_state(dev, config); |
7415 | 7412 | ||
7416 | /* Try to restore the config */ |
7413 | /* Try to restore the config */ |
7417 | if (config->mode_changed && |
7414 | if (config->mode_changed && |
7418 | !intel_set_mode(save_set.crtc, save_set.mode, |
7415 | !intel_set_mode(save_set.crtc, save_set.mode, |
7419 | save_set.x, save_set.y, save_set.fb)) |
7416 | save_set.x, save_set.y, save_set.fb)) |
7420 | DRM_ERROR("failed to restore config after modeset failure\n"); |
7417 | DRM_ERROR("failed to restore config after modeset failure\n"); |
7421 | 7418 | ||
7422 | out_config: |
7419 | out_config: |
7423 | intel_set_config_free(config); |
7420 | intel_set_config_free(config); |
7424 | return ret; |
7421 | return ret; |
7425 | } |
7422 | } |
7426 | 7423 | ||
7427 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
7424 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
7428 | // .cursor_set = intel_crtc_cursor_set, |
7425 | // .cursor_set = intel_crtc_cursor_set, |
7429 | // .cursor_move = intel_crtc_cursor_move, |
7426 | // .cursor_move = intel_crtc_cursor_move, |
7430 | .gamma_set = intel_crtc_gamma_set, |
7427 | .gamma_set = intel_crtc_gamma_set, |
7431 | .set_config = intel_crtc_set_config, |
7428 | .set_config = intel_crtc_set_config, |
7432 | .destroy = intel_crtc_destroy, |
7429 | .destroy = intel_crtc_destroy, |
7433 | // .page_flip = intel_crtc_page_flip, |
7430 | // .page_flip = intel_crtc_page_flip, |
7434 | }; |
7431 | }; |
7435 | 7432 | ||
7436 | static void intel_pch_pll_init(struct drm_device *dev) |
7433 | static void intel_pch_pll_init(struct drm_device *dev) |
7437 | { |
7434 | { |
7438 | drm_i915_private_t *dev_priv = dev->dev_private; |
7435 | drm_i915_private_t *dev_priv = dev->dev_private; |
7439 | int i; |
7436 | int i; |
7440 | 7437 | ||
7441 | if (dev_priv->num_pch_pll == 0) { |
7438 | if (dev_priv->num_pch_pll == 0) { |
7442 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); |
7439 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); |
7443 | return; |
7440 | return; |
7444 | } |
7441 | } |
7445 | 7442 | ||
7446 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
7443 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
7447 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); |
7444 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); |
7448 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); |
7445 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); |
7449 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); |
7446 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); |
7450 | } |
7447 | } |
7451 | } |
7448 | } |
7452 | 7449 | ||
7453 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
7450 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
7454 | { |
7451 | { |
7455 | drm_i915_private_t *dev_priv = dev->dev_private; |
7452 | drm_i915_private_t *dev_priv = dev->dev_private; |
7456 | struct intel_crtc *intel_crtc; |
7453 | struct intel_crtc *intel_crtc; |
7457 | int i; |
7454 | int i; |
7458 | 7455 | ||
7459 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
7456 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
7460 | if (intel_crtc == NULL) |
7457 | if (intel_crtc == NULL) |
7461 | return; |
7458 | return; |
7462 | 7459 | ||
7463 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
7460 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
7464 | 7461 | ||
7465 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
7462 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
7466 | for (i = 0; i < 256; i++) { |
7463 | for (i = 0; i < 256; i++) { |
7467 | intel_crtc->lut_r[i] = i; |
7464 | intel_crtc->lut_r[i] = i; |
7468 | intel_crtc->lut_g[i] = i; |
7465 | intel_crtc->lut_g[i] = i; |
7469 | intel_crtc->lut_b[i] = i; |
7466 | intel_crtc->lut_b[i] = i; |
7470 | } |
7467 | } |
7471 | 7468 | ||
7472 | /* Swap pipes & planes for FBC on pre-965 */ |
7469 | /* Swap pipes & planes for FBC on pre-965 */ |
7473 | intel_crtc->pipe = pipe; |
7470 | intel_crtc->pipe = pipe; |
7474 | intel_crtc->plane = pipe; |
7471 | intel_crtc->plane = pipe; |
7475 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
7472 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
7476 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
7473 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
7477 | intel_crtc->plane = !pipe; |
7474 | intel_crtc->plane = !pipe; |
7478 | } |
7475 | } |
7479 | 7476 | ||
7480 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7477 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7481 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
7478 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
7482 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
7479 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
7483 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
7480 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
7484 | 7481 | ||
7485 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7482 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7486 | 7483 | ||
7487 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7484 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7488 | 7485 | ||
7489 | dbgprintf("CRTC %d mode %x FB %x enable %d\n", |
7486 | DRM_DEBUG_KMS("CRTC %d mode %x FB %x enable %d\n", |
7490 | intel_crtc->base.base.id, intel_crtc->base.mode, |
7487 | intel_crtc->base.base.id, intel_crtc->base.mode, |
7491 | intel_crtc->base.fb, intel_crtc->base.enabled); |
7488 | intel_crtc->base.fb, intel_crtc->base.enabled); |
7492 | 7489 | ||
7493 | } |
7490 | } |
7494 | 7491 | ||
7495 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
7492 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
7496 | struct drm_file *file) |
7493 | struct drm_file *file) |
7497 | { |
7494 | { |
7498 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7495 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7499 | struct drm_mode_object *drmmode_obj; |
7496 | struct drm_mode_object *drmmode_obj; |
7500 | struct intel_crtc *crtc; |
7497 | struct intel_crtc *crtc; |
7501 | 7498 | ||
7502 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7499 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7503 | DRM_MODE_OBJECT_CRTC); |
7500 | DRM_MODE_OBJECT_CRTC); |
7504 | 7501 | ||
7505 | if (!drmmode_obj) { |
7502 | if (!drmmode_obj) { |
7506 | DRM_ERROR("no such CRTC id\n"); |
7503 | DRM_ERROR("no such CRTC id\n"); |
7507 | return -EINVAL; |
7504 | return -EINVAL; |
7508 | } |
7505 | } |
7509 | 7506 | ||
7510 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7507 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7511 | pipe_from_crtc_id->pipe = crtc->pipe; |
7508 | pipe_from_crtc_id->pipe = crtc->pipe; |
7512 | 7509 | ||
7513 | return 0; |
7510 | return 0; |
7514 | } |
7511 | } |
7515 | 7512 | ||
7516 | static int intel_encoder_clones(struct intel_encoder *encoder) |
7513 | static int intel_encoder_clones(struct intel_encoder *encoder) |
7517 | { |
7514 | { |
7518 | struct drm_device *dev = encoder->base.dev; |
7515 | struct drm_device *dev = encoder->base.dev; |
7519 | struct intel_encoder *source_encoder; |
7516 | struct intel_encoder *source_encoder; |
7520 | int index_mask = 0; |
7517 | int index_mask = 0; |
7521 | int entry = 0; |
7518 | int entry = 0; |
7522 | 7519 | ||
7523 | list_for_each_entry(source_encoder, |
7520 | list_for_each_entry(source_encoder, |
7524 | &dev->mode_config.encoder_list, base.head) { |
7521 | &dev->mode_config.encoder_list, base.head) { |
7525 | 7522 | ||
7526 | if (encoder == source_encoder) |
7523 | if (encoder == source_encoder) |
7527 | index_mask |= (1 << entry); |
7524 | index_mask |= (1 << entry); |
7528 | 7525 | ||
7529 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
7526 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
7530 | if (encoder->cloneable && source_encoder->cloneable) |
7527 | if (encoder->cloneable && source_encoder->cloneable) |
7531 | index_mask |= (1 << entry); |
7528 | index_mask |= (1 << entry); |
7532 | 7529 | ||
7533 | entry++; |
7530 | entry++; |
7534 | } |
7531 | } |
7535 | 7532 | ||
7536 | return index_mask; |
7533 | return index_mask; |
7537 | } |
7534 | } |
7538 | 7535 | ||
7539 | static bool has_edp_a(struct drm_device *dev) |
7536 | static bool has_edp_a(struct drm_device *dev) |
7540 | { |
7537 | { |
7541 | struct drm_i915_private *dev_priv = dev->dev_private; |
7538 | struct drm_i915_private *dev_priv = dev->dev_private; |
7542 | 7539 | ||
7543 | if (!IS_MOBILE(dev)) |
7540 | if (!IS_MOBILE(dev)) |
7544 | return false; |
7541 | return false; |
7545 | 7542 | ||
7546 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
7543 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
7547 | return false; |
7544 | return false; |
7548 | 7545 | ||
7549 | if (IS_GEN5(dev) && |
7546 | if (IS_GEN5(dev) && |
7550 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
7547 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
7551 | return false; |
7548 | return false; |
7552 | 7549 | ||
7553 | return true; |
7550 | return true; |
7554 | } |
7551 | } |
7555 | 7552 | ||
7556 | static void intel_setup_outputs(struct drm_device *dev) |
7553 | static void intel_setup_outputs(struct drm_device *dev) |
7557 | { |
7554 | { |
7558 | struct drm_i915_private *dev_priv = dev->dev_private; |
7555 | struct drm_i915_private *dev_priv = dev->dev_private; |
7559 | struct intel_encoder *encoder; |
7556 | struct intel_encoder *encoder; |
7560 | bool dpd_is_edp = false; |
7557 | bool dpd_is_edp = false; |
7561 | bool has_lvds; |
7558 | bool has_lvds; |
7562 | 7559 | ||
7563 | has_lvds = intel_lvds_init(dev); |
7560 | has_lvds = intel_lvds_init(dev); |
7564 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7561 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7565 | /* disable the panel fitter on everything but LVDS */ |
7562 | /* disable the panel fitter on everything but LVDS */ |
7566 | I915_WRITE(PFIT_CONTROL, 0); |
7563 | I915_WRITE(PFIT_CONTROL, 0); |
7567 | } |
7564 | } |
7568 | 7565 | ||
7569 | if (HAS_PCH_SPLIT(dev)) { |
7566 | if (HAS_PCH_SPLIT(dev)) { |
7570 | dpd_is_edp = intel_dpd_is_edp(dev); |
7567 | dpd_is_edp = intel_dpd_is_edp(dev); |
7571 | 7568 | ||
7572 | if (has_edp_a(dev)) |
7569 | if (has_edp_a(dev)) |
7573 | intel_dp_init(dev, DP_A, PORT_A); |
7570 | intel_dp_init(dev, DP_A, PORT_A); |
7574 | 7571 | ||
7575 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7572 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7576 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
7573 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
7577 | } |
7574 | } |
7578 | 7575 | ||
7579 | intel_crt_init(dev); |
7576 | intel_crt_init(dev); |
7580 | 7577 | ||
7581 | if (IS_HASWELL(dev)) { |
7578 | if (IS_HASWELL(dev)) { |
7582 | int found; |
7579 | int found; |
7583 | 7580 | ||
7584 | /* Haswell uses DDI functions to detect digital outputs */ |
7581 | /* Haswell uses DDI functions to detect digital outputs */ |
7585 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
7582 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
7586 | /* DDI A only supports eDP */ |
7583 | /* DDI A only supports eDP */ |
7587 | if (found) |
7584 | if (found) |
7588 | intel_ddi_init(dev, PORT_A); |
7585 | intel_ddi_init(dev, PORT_A); |
7589 | 7586 | ||
7590 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
7587 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
7591 | * register */ |
7588 | * register */ |
7592 | found = I915_READ(SFUSE_STRAP); |
7589 | found = I915_READ(SFUSE_STRAP); |
7593 | 7590 | ||
7594 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
7591 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
7595 | intel_ddi_init(dev, PORT_B); |
7592 | intel_ddi_init(dev, PORT_B); |
7596 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
7593 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
7597 | intel_ddi_init(dev, PORT_C); |
7594 | intel_ddi_init(dev, PORT_C); |
7598 | if (found & SFUSE_STRAP_DDID_DETECTED) |
7595 | if (found & SFUSE_STRAP_DDID_DETECTED) |
7599 | intel_ddi_init(dev, PORT_D); |
7596 | intel_ddi_init(dev, PORT_D); |
7600 | } else if (HAS_PCH_SPLIT(dev)) { |
7597 | } else if (HAS_PCH_SPLIT(dev)) { |
7601 | int found; |
7598 | int found; |
7602 | 7599 | ||
7603 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
7600 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
7604 | /* PCH SDVOB multiplex with HDMIB */ |
7601 | /* PCH SDVOB multiplex with HDMIB */ |
7605 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
7602 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
7606 | if (!found) |
7603 | if (!found) |
7607 | intel_hdmi_init(dev, HDMIB, PORT_B); |
7604 | intel_hdmi_init(dev, HDMIB, PORT_B); |
7608 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7605 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7609 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
7606 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
7610 | } |
7607 | } |
7611 | 7608 | ||
7612 | if (I915_READ(HDMIC) & PORT_DETECTED) |
7609 | if (I915_READ(HDMIC) & PORT_DETECTED) |
7613 | intel_hdmi_init(dev, HDMIC, PORT_C); |
7610 | intel_hdmi_init(dev, HDMIC, PORT_C); |
7614 | 7611 | ||
7615 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
7612 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
7616 | intel_hdmi_init(dev, HDMID, PORT_D); |
7613 | intel_hdmi_init(dev, HDMID, PORT_D); |
7617 | 7614 | ||
7618 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7615 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7619 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
7616 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
7620 | 7617 | ||
7621 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7618 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7622 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
7619 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
7623 | } else if (IS_VALLEYVIEW(dev)) { |
7620 | } else if (IS_VALLEYVIEW(dev)) { |
7624 | int found; |
7621 | int found; |
7625 | 7622 | ||
7626 | if (I915_READ(SDVOB) & PORT_DETECTED) { |
7623 | if (I915_READ(SDVOB) & PORT_DETECTED) { |
7627 | /* SDVOB multiplex with HDMIB */ |
7624 | /* SDVOB multiplex with HDMIB */ |
7628 | found = intel_sdvo_init(dev, SDVOB, true); |
7625 | found = intel_sdvo_init(dev, SDVOB, true); |
7629 | if (!found) |
7626 | if (!found) |
7630 | intel_hdmi_init(dev, SDVOB, PORT_B); |
7627 | intel_hdmi_init(dev, SDVOB, PORT_B); |
7631 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
7628 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
7632 | intel_dp_init(dev, DP_B, PORT_B); |
7629 | intel_dp_init(dev, DP_B, PORT_B); |
7633 | } |
7630 | } |
7634 | 7631 | ||
7635 | if (I915_READ(SDVOC) & PORT_DETECTED) |
7632 | if (I915_READ(SDVOC) & PORT_DETECTED) |
7636 | intel_hdmi_init(dev, SDVOC, PORT_C); |
7633 | intel_hdmi_init(dev, SDVOC, PORT_C); |
7637 | 7634 | ||
7638 | /* Shares lanes with HDMI on SDVOC */ |
7635 | /* Shares lanes with HDMI on SDVOC */ |
7639 | if (I915_READ(DP_C) & DP_DETECTED) |
7636 | if (I915_READ(DP_C) & DP_DETECTED) |
7640 | intel_dp_init(dev, DP_C, PORT_C); |
7637 | intel_dp_init(dev, DP_C, PORT_C); |
7641 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
7638 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
7642 | bool found = false; |
7639 | bool found = false; |
7643 | 7640 | ||
7644 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7641 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7645 | DRM_DEBUG_KMS("probing SDVOB\n"); |
7642 | DRM_DEBUG_KMS("probing SDVOB\n"); |
7646 | found = intel_sdvo_init(dev, SDVOB, true); |
7643 | found = intel_sdvo_init(dev, SDVOB, true); |
7647 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7644 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7648 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
7645 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
7649 | intel_hdmi_init(dev, SDVOB, PORT_B); |
7646 | intel_hdmi_init(dev, SDVOB, PORT_B); |
7650 | } |
7647 | } |
7651 | 7648 | ||
7652 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7649 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7653 | DRM_DEBUG_KMS("probing DP_B\n"); |
7650 | DRM_DEBUG_KMS("probing DP_B\n"); |
7654 | intel_dp_init(dev, DP_B, PORT_B); |
7651 | intel_dp_init(dev, DP_B, PORT_B); |
7655 | } |
7652 | } |
7656 | } |
7653 | } |
7657 | 7654 | ||
7658 | /* Before G4X SDVOC doesn't have its own detect register */ |
7655 | /* Before G4X SDVOC doesn't have its own detect register */ |
7659 | 7656 | ||
7660 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7657 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7661 | DRM_DEBUG_KMS("probing SDVOC\n"); |
7658 | DRM_DEBUG_KMS("probing SDVOC\n"); |
7662 | found = intel_sdvo_init(dev, SDVOC, false); |
7659 | found = intel_sdvo_init(dev, SDVOC, false); |
7663 | } |
7660 | } |
7664 | 7661 | ||
7665 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
7662 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
7666 | 7663 | ||
7667 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7664 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7668 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
7665 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
7669 | intel_hdmi_init(dev, SDVOC, PORT_C); |
7666 | intel_hdmi_init(dev, SDVOC, PORT_C); |
7670 | } |
7667 | } |
7671 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
7668 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
7672 | DRM_DEBUG_KMS("probing DP_C\n"); |
7669 | DRM_DEBUG_KMS("probing DP_C\n"); |
7673 | intel_dp_init(dev, DP_C, PORT_C); |
7670 | intel_dp_init(dev, DP_C, PORT_C); |
7674 | } |
7671 | } |
7675 | } |
7672 | } |
7676 | 7673 | ||
7677 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7674 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7678 | (I915_READ(DP_D) & DP_DETECTED)) { |
7675 | (I915_READ(DP_D) & DP_DETECTED)) { |
7679 | DRM_DEBUG_KMS("probing DP_D\n"); |
7676 | DRM_DEBUG_KMS("probing DP_D\n"); |
7680 | intel_dp_init(dev, DP_D, PORT_D); |
7677 | intel_dp_init(dev, DP_D, PORT_D); |
7681 | } |
7678 | } |
7682 | } else if (IS_GEN2(dev)) |
7679 | } else if (IS_GEN2(dev)) |
7683 | intel_dvo_init(dev); |
7680 | intel_dvo_init(dev); |
7684 | 7681 | ||
7685 | // if (SUPPORTS_TV(dev)) |
7682 | // if (SUPPORTS_TV(dev)) |
7686 | // intel_tv_init(dev); |
7683 | // intel_tv_init(dev); |
7687 | 7684 | ||
7688 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7685 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7689 | encoder->base.possible_crtcs = encoder->crtc_mask; |
7686 | encoder->base.possible_crtcs = encoder->crtc_mask; |
7690 | encoder->base.possible_clones = |
7687 | encoder->base.possible_clones = |
7691 | intel_encoder_clones(encoder); |
7688 | intel_encoder_clones(encoder); |
7692 | } |
7689 | } |
7693 | 7690 | ||
7694 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
7691 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
7695 | ironlake_init_pch_refclk(dev); |
7692 | ironlake_init_pch_refclk(dev); |
7696 | } |
7693 | } |
7697 | 7694 | ||
7698 | 7695 | ||
7699 | 7696 | ||
7700 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
7697 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
7701 | // .destroy = intel_user_framebuffer_destroy, |
7698 | // .destroy = intel_user_framebuffer_destroy, |
7702 | // .create_handle = intel_user_framebuffer_create_handle, |
7699 | // .create_handle = intel_user_framebuffer_create_handle, |
7703 | }; |
7700 | }; |
7704 | 7701 | ||
7705 | int intel_framebuffer_init(struct drm_device *dev, |
7702 | int intel_framebuffer_init(struct drm_device *dev, |
7706 | struct intel_framebuffer *intel_fb, |
7703 | struct intel_framebuffer *intel_fb, |
7707 | struct drm_mode_fb_cmd2 *mode_cmd, |
7704 | struct drm_mode_fb_cmd2 *mode_cmd, |
7708 | struct drm_i915_gem_object *obj) |
7705 | struct drm_i915_gem_object *obj) |
7709 | { |
7706 | { |
7710 | int ret; |
7707 | int ret; |
7711 | 7708 | ||
7712 | if (obj->tiling_mode == I915_TILING_Y) |
7709 | if (obj->tiling_mode == I915_TILING_Y) |
7713 | return -EINVAL; |
7710 | return -EINVAL; |
7714 | 7711 | ||
7715 | if (mode_cmd->pitches[0] & 63) |
7712 | if (mode_cmd->pitches[0] & 63) |
7716 | return -EINVAL; |
7713 | return -EINVAL; |
7717 | 7714 | ||
7718 | switch (mode_cmd->pixel_format) { |
7715 | switch (mode_cmd->pixel_format) { |
7719 | case DRM_FORMAT_RGB332: |
7716 | case DRM_FORMAT_RGB332: |
7720 | case DRM_FORMAT_RGB565: |
7717 | case DRM_FORMAT_RGB565: |
7721 | case DRM_FORMAT_XRGB8888: |
7718 | case DRM_FORMAT_XRGB8888: |
7722 | case DRM_FORMAT_XBGR8888: |
7719 | case DRM_FORMAT_XBGR8888: |
7723 | case DRM_FORMAT_ARGB8888: |
7720 | case DRM_FORMAT_ARGB8888: |
7724 | case DRM_FORMAT_XRGB2101010: |
7721 | case DRM_FORMAT_XRGB2101010: |
7725 | case DRM_FORMAT_ARGB2101010: |
7722 | case DRM_FORMAT_ARGB2101010: |
7726 | /* RGB formats are common across chipsets */ |
7723 | /* RGB formats are common across chipsets */ |
7727 | break; |
7724 | break; |
7728 | case DRM_FORMAT_YUYV: |
7725 | case DRM_FORMAT_YUYV: |
7729 | case DRM_FORMAT_UYVY: |
7726 | case DRM_FORMAT_UYVY: |
7730 | case DRM_FORMAT_YVYU: |
7727 | case DRM_FORMAT_YVYU: |
7731 | case DRM_FORMAT_VYUY: |
7728 | case DRM_FORMAT_VYUY: |
7732 | break; |
7729 | break; |
7733 | default: |
7730 | default: |
7734 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7731 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7735 | mode_cmd->pixel_format); |
7732 | mode_cmd->pixel_format); |
7736 | return -EINVAL; |
7733 | return -EINVAL; |
7737 | } |
7734 | } |
7738 | 7735 | ||
7739 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7736 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7740 | if (ret) { |
7737 | if (ret) { |
7741 | DRM_ERROR("framebuffer init failed %d\n", ret); |
7738 | DRM_ERROR("framebuffer init failed %d\n", ret); |
7742 | return ret; |
7739 | return ret; |
7743 | } |
7740 | } |
7744 | 7741 | ||
7745 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
7742 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
7746 | intel_fb->obj = obj; |
7743 | intel_fb->obj = obj; |
7747 | return 0; |
7744 | return 0; |
7748 | } |
7745 | } |
7749 | 7746 | ||
7750 | 7747 | ||
7751 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
7748 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
7752 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
7749 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
7753 | .output_poll_changed = NULL /*intel_fb_output_poll_changed*/, |
7750 | .output_poll_changed = NULL /*intel_fb_output_poll_changed*/, |
7754 | }; |
7751 | }; |
7755 | 7752 | ||
7756 | /* Set up chip specific display functions */ |
7753 | /* Set up chip specific display functions */ |
7757 | static void intel_init_display(struct drm_device *dev) |
7754 | static void intel_init_display(struct drm_device *dev) |
7758 | { |
7755 | { |
7759 | struct drm_i915_private *dev_priv = dev->dev_private; |
7756 | struct drm_i915_private *dev_priv = dev->dev_private; |
7760 | 7757 | ||
7761 | /* We always want a DPMS function */ |
7758 | /* We always want a DPMS function */ |
7762 | if (HAS_PCH_SPLIT(dev)) { |
7759 | if (HAS_PCH_SPLIT(dev)) { |
7763 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
7760 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
7764 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
7761 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
7765 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
7762 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
7766 | dev_priv->display.off = ironlake_crtc_off; |
7763 | dev_priv->display.off = ironlake_crtc_off; |
7767 | dev_priv->display.update_plane = ironlake_update_plane; |
7764 | dev_priv->display.update_plane = ironlake_update_plane; |
7768 | } else { |
7765 | } else { |
7769 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
7766 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
7770 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
7767 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
7771 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
7768 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
7772 | dev_priv->display.off = i9xx_crtc_off; |
7769 | dev_priv->display.off = i9xx_crtc_off; |
7773 | dev_priv->display.update_plane = i9xx_update_plane; |
7770 | dev_priv->display.update_plane = i9xx_update_plane; |
7774 | } |
7771 | } |
7775 | 7772 | ||
7776 | /* Returns the core display clock speed */ |
7773 | /* Returns the core display clock speed */ |
7777 | if (IS_VALLEYVIEW(dev)) |
7774 | if (IS_VALLEYVIEW(dev)) |
7778 | dev_priv->display.get_display_clock_speed = |
7775 | dev_priv->display.get_display_clock_speed = |
7779 | valleyview_get_display_clock_speed; |
7776 | valleyview_get_display_clock_speed; |
7780 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
7777 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
7781 | dev_priv->display.get_display_clock_speed = |
7778 | dev_priv->display.get_display_clock_speed = |
7782 | i945_get_display_clock_speed; |
7779 | i945_get_display_clock_speed; |
7783 | else if (IS_I915G(dev)) |
7780 | else if (IS_I915G(dev)) |
7784 | dev_priv->display.get_display_clock_speed = |
7781 | dev_priv->display.get_display_clock_speed = |
7785 | i915_get_display_clock_speed; |
7782 | i915_get_display_clock_speed; |
7786 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
7783 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
7787 | dev_priv->display.get_display_clock_speed = |
7784 | dev_priv->display.get_display_clock_speed = |
7788 | i9xx_misc_get_display_clock_speed; |
7785 | i9xx_misc_get_display_clock_speed; |
7789 | else if (IS_I915GM(dev)) |
7786 | else if (IS_I915GM(dev)) |
7790 | dev_priv->display.get_display_clock_speed = |
7787 | dev_priv->display.get_display_clock_speed = |
7791 | i915gm_get_display_clock_speed; |
7788 | i915gm_get_display_clock_speed; |
7792 | else if (IS_I865G(dev)) |
7789 | else if (IS_I865G(dev)) |
7793 | dev_priv->display.get_display_clock_speed = |
7790 | dev_priv->display.get_display_clock_speed = |
7794 | i865_get_display_clock_speed; |
7791 | i865_get_display_clock_speed; |
7795 | else if (IS_I85X(dev)) |
7792 | else if (IS_I85X(dev)) |
7796 | dev_priv->display.get_display_clock_speed = |
7793 | dev_priv->display.get_display_clock_speed = |
7797 | i855_get_display_clock_speed; |
7794 | i855_get_display_clock_speed; |
7798 | else /* 852, 830 */ |
7795 | else /* 852, 830 */ |
7799 | dev_priv->display.get_display_clock_speed = |
7796 | dev_priv->display.get_display_clock_speed = |
7800 | i830_get_display_clock_speed; |
7797 | i830_get_display_clock_speed; |
7801 | 7798 | ||
7802 | if (HAS_PCH_SPLIT(dev)) { |
7799 | if (HAS_PCH_SPLIT(dev)) { |
7803 | if (IS_GEN5(dev)) { |
7800 | if (IS_GEN5(dev)) { |
7804 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
7801 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
7805 | dev_priv->display.write_eld = ironlake_write_eld; |
7802 | dev_priv->display.write_eld = ironlake_write_eld; |
7806 | } else if (IS_GEN6(dev)) { |
7803 | } else if (IS_GEN6(dev)) { |
7807 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
7804 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
7808 | dev_priv->display.write_eld = ironlake_write_eld; |
7805 | dev_priv->display.write_eld = ironlake_write_eld; |
7809 | } else if (IS_IVYBRIDGE(dev)) { |
7806 | } else if (IS_IVYBRIDGE(dev)) { |
7810 | /* FIXME: detect B0+ stepping and use auto training */ |
7807 | /* FIXME: detect B0+ stepping and use auto training */ |
7811 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
7808 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
7812 | dev_priv->display.write_eld = ironlake_write_eld; |
7809 | dev_priv->display.write_eld = ironlake_write_eld; |
7813 | } else if (IS_HASWELL(dev)) { |
7810 | } else if (IS_HASWELL(dev)) { |
7814 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
7811 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
7815 | dev_priv->display.write_eld = haswell_write_eld; |
7812 | dev_priv->display.write_eld = haswell_write_eld; |
7816 | } else |
7813 | } else |
7817 | dev_priv->display.update_wm = NULL; |
7814 | dev_priv->display.update_wm = NULL; |
7818 | } else if (IS_G4X(dev)) { |
7815 | } else if (IS_G4X(dev)) { |
7819 | dev_priv->display.write_eld = g4x_write_eld; |
7816 | dev_priv->display.write_eld = g4x_write_eld; |
7820 | } |
7817 | } |
7821 | 7818 | ||
7822 | /* Default just returns -ENODEV to indicate unsupported */ |
7819 | /* Default just returns -ENODEV to indicate unsupported */ |
7823 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
7820 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
7824 | 7821 | ||
7825 | 7822 | ||
7826 | 7823 | ||
7827 | 7824 | ||
7828 | } |
7825 | } |
7829 | 7826 | ||
7830 | /* |
7827 | /* |
7831 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
7828 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
7832 | * resume, or other times. This quirk makes sure that's the case for |
7829 | * resume, or other times. This quirk makes sure that's the case for |
7833 | * affected systems. |
7830 | * affected systems. |
7834 | */ |
7831 | */ |
7835 | static void quirk_pipea_force(struct drm_device *dev) |
7832 | static void quirk_pipea_force(struct drm_device *dev) |
7836 | { |
7833 | { |
7837 | struct drm_i915_private *dev_priv = dev->dev_private; |
7834 | struct drm_i915_private *dev_priv = dev->dev_private; |
7838 | 7835 | ||
7839 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
7836 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
7840 | DRM_INFO("applying pipe a force quirk\n"); |
7837 | DRM_INFO("applying pipe a force quirk\n"); |
7841 | } |
7838 | } |
7842 | 7839 | ||
7843 | /* |
7840 | /* |
7844 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
7841 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
7845 | */ |
7842 | */ |
7846 | static void quirk_ssc_force_disable(struct drm_device *dev) |
7843 | static void quirk_ssc_force_disable(struct drm_device *dev) |
7847 | { |
7844 | { |
7848 | struct drm_i915_private *dev_priv = dev->dev_private; |
7845 | struct drm_i915_private *dev_priv = dev->dev_private; |
7849 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
7846 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
7850 | DRM_INFO("applying lvds SSC disable quirk\n"); |
7847 | DRM_INFO("applying lvds SSC disable quirk\n"); |
7851 | } |
7848 | } |
7852 | 7849 | ||
7853 | /* |
7850 | /* |
7854 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
7851 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
7855 | * brightness value |
7852 | * brightness value |
7856 | */ |
7853 | */ |
7857 | static void quirk_invert_brightness(struct drm_device *dev) |
7854 | static void quirk_invert_brightness(struct drm_device *dev) |
7858 | { |
7855 | { |
7859 | struct drm_i915_private *dev_priv = dev->dev_private; |
7856 | struct drm_i915_private *dev_priv = dev->dev_private; |
7860 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
7857 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
7861 | DRM_INFO("applying inverted panel brightness quirk\n"); |
7858 | DRM_INFO("applying inverted panel brightness quirk\n"); |
7862 | } |
7859 | } |
7863 | 7860 | ||
7864 | struct intel_quirk { |
7861 | struct intel_quirk { |
7865 | int device; |
7862 | int device; |
7866 | int subsystem_vendor; |
7863 | int subsystem_vendor; |
7867 | int subsystem_device; |
7864 | int subsystem_device; |
7868 | void (*hook)(struct drm_device *dev); |
7865 | void (*hook)(struct drm_device *dev); |
7869 | }; |
7866 | }; |
7870 | 7867 | ||
7871 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
7868 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
7872 | struct intel_dmi_quirk { |
7869 | struct intel_dmi_quirk { |
7873 | void (*hook)(struct drm_device *dev); |
7870 | void (*hook)(struct drm_device *dev); |
7874 | const struct dmi_system_id (*dmi_id_list)[]; |
7871 | const struct dmi_system_id (*dmi_id_list)[]; |
7875 | }; |
7872 | }; |
7876 | 7873 | ||
7877 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
7874 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
7878 | { |
7875 | { |
7879 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
7876 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
7880 | return 1; |
7877 | return 1; |
7881 | } |
7878 | } |
7882 | 7879 | ||
7883 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
7880 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
7884 | { |
7881 | { |
7885 | .dmi_id_list = &(const struct dmi_system_id[]) { |
7882 | .dmi_id_list = &(const struct dmi_system_id[]) { |
7886 | { |
7883 | { |
7887 | .callback = intel_dmi_reverse_brightness, |
7884 | .callback = intel_dmi_reverse_brightness, |
7888 | .ident = "NCR Corporation", |
7885 | .ident = "NCR Corporation", |
7889 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
7886 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
7890 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
7887 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
7891 | }, |
7888 | }, |
7892 | }, |
7889 | }, |
7893 | { } /* terminating entry */ |
7890 | { } /* terminating entry */ |
7894 | }, |
7891 | }, |
7895 | .hook = quirk_invert_brightness, |
7892 | .hook = quirk_invert_brightness, |
7896 | }, |
7893 | }, |
7897 | }; |
7894 | }; |
7898 | 7895 | ||
7899 | static struct intel_quirk intel_quirks[] = { |
7896 | static struct intel_quirk intel_quirks[] = { |
7900 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
7897 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
7901 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
7898 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
7902 | 7899 | ||
7903 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
7900 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
7904 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
7901 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
7905 | 7902 | ||
7906 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
7903 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
7907 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
7904 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
7908 | 7905 | ||
7909 | /* 830/845 need to leave pipe A & dpll A up */ |
7906 | /* 830/845 need to leave pipe A & dpll A up */ |
7910 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
7907 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
7911 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
7908 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
7912 | 7909 | ||
7913 | /* Lenovo U160 cannot use SSC on LVDS */ |
7910 | /* Lenovo U160 cannot use SSC on LVDS */ |
7914 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
7911 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
7915 | 7912 | ||
7916 | /* Sony Vaio Y cannot use SSC on LVDS */ |
7913 | /* Sony Vaio Y cannot use SSC on LVDS */ |
7917 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
7914 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
7918 | 7915 | ||
7919 | /* Acer Aspire 5734Z must invert backlight brightness */ |
7916 | /* Acer Aspire 5734Z must invert backlight brightness */ |
7920 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
7917 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
7921 | }; |
7918 | }; |
7922 | 7919 | ||
7923 | static void intel_init_quirks(struct drm_device *dev) |
7920 | static void intel_init_quirks(struct drm_device *dev) |
7924 | { |
7921 | { |
7925 | struct pci_dev *d = dev->pdev; |
7922 | struct pci_dev *d = dev->pdev; |
7926 | int i; |
7923 | int i; |
7927 | 7924 | ||
7928 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
7925 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
7929 | struct intel_quirk *q = &intel_quirks[i]; |
7926 | struct intel_quirk *q = &intel_quirks[i]; |
7930 | 7927 | ||
7931 | if (d->device == q->device && |
7928 | if (d->device == q->device && |
7932 | (d->subsystem_vendor == q->subsystem_vendor || |
7929 | (d->subsystem_vendor == q->subsystem_vendor || |
7933 | q->subsystem_vendor == PCI_ANY_ID) && |
7930 | q->subsystem_vendor == PCI_ANY_ID) && |
7934 | (d->subsystem_device == q->subsystem_device || |
7931 | (d->subsystem_device == q->subsystem_device || |
7935 | q->subsystem_device == PCI_ANY_ID)) |
7932 | q->subsystem_device == PCI_ANY_ID)) |
7936 | q->hook(dev); |
7933 | q->hook(dev); |
7937 | } |
7934 | } |
7938 | // for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
7935 | // for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
7939 | // if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
7936 | // if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
7940 | // intel_dmi_quirks[i].hook(dev); |
7937 | // intel_dmi_quirks[i].hook(dev); |
7941 | // } |
7938 | // } |
7942 | } |
7939 | } |
7943 | 7940 | ||
7944 | /* Disable the VGA plane that we never use */ |
7941 | /* Disable the VGA plane that we never use */ |
7945 | static void i915_disable_vga(struct drm_device *dev) |
7942 | static void i915_disable_vga(struct drm_device *dev) |
7946 | { |
7943 | { |
7947 | struct drm_i915_private *dev_priv = dev->dev_private; |
7944 | struct drm_i915_private *dev_priv = dev->dev_private; |
7948 | u8 sr1; |
7945 | u8 sr1; |
7949 | u32 vga_reg; |
7946 | u32 vga_reg; |
7950 | 7947 | ||
7951 | if (HAS_PCH_SPLIT(dev)) |
7948 | if (HAS_PCH_SPLIT(dev)) |
7952 | vga_reg = CPU_VGACNTRL; |
7949 | vga_reg = CPU_VGACNTRL; |
7953 | else |
7950 | else |
7954 | vga_reg = VGACNTRL; |
7951 | vga_reg = VGACNTRL; |
7955 | 7952 | ||
7956 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
7953 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
7957 | out8(SR01, VGA_SR_INDEX); |
7954 | out8(SR01, VGA_SR_INDEX); |
7958 | sr1 = in8(VGA_SR_DATA); |
7955 | sr1 = in8(VGA_SR_DATA); |
7959 | out8(sr1 | 1<<5, VGA_SR_DATA); |
7956 | out8(sr1 | 1<<5, VGA_SR_DATA); |
7960 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
7957 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
7961 | udelay(300); |
7958 | udelay(300); |
7962 | 7959 | ||
7963 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
7960 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
7964 | POSTING_READ(vga_reg); |
7961 | POSTING_READ(vga_reg); |
7965 | } |
7962 | } |
7966 | 7963 | ||
7967 | void intel_modeset_init_hw(struct drm_device *dev) |
7964 | void intel_modeset_init_hw(struct drm_device *dev) |
7968 | { |
7965 | { |
7969 | /* We attempt to init the necessary power wells early in the initialization |
7966 | /* We attempt to init the necessary power wells early in the initialization |
7970 | * time, so the subsystems that expect power to be enabled can work. |
7967 | * time, so the subsystems that expect power to be enabled can work. |
7971 | */ |
7968 | */ |
7972 | intel_init_power_wells(dev); |
7969 | intel_init_power_wells(dev); |
7973 | 7970 | ||
7974 | intel_prepare_ddi(dev); |
7971 | intel_prepare_ddi(dev); |
7975 | 7972 | ||
7976 | intel_init_clock_gating(dev); |
7973 | intel_init_clock_gating(dev); |
7977 | 7974 | ||
7978 | // mutex_lock(&dev->struct_mutex); |
7975 | // mutex_lock(&dev->struct_mutex); |
7979 | // intel_enable_gt_powersave(dev); |
7976 | // intel_enable_gt_powersave(dev); |
7980 | // mutex_unlock(&dev->struct_mutex); |
7977 | // mutex_unlock(&dev->struct_mutex); |
7981 | } |
7978 | } |
7982 | 7979 | ||
7983 | void intel_modeset_init(struct drm_device *dev) |
7980 | void intel_modeset_init(struct drm_device *dev) |
7984 | { |
7981 | { |
7985 | struct drm_i915_private *dev_priv = dev->dev_private; |
7982 | struct drm_i915_private *dev_priv = dev->dev_private; |
7986 | int i, ret; |
7983 | int i, ret; |
7987 | 7984 | ||
7988 | drm_mode_config_init(dev); |
7985 | drm_mode_config_init(dev); |
7989 | 7986 | ||
7990 | dev->mode_config.min_width = 0; |
7987 | dev->mode_config.min_width = 0; |
7991 | dev->mode_config.min_height = 0; |
7988 | dev->mode_config.min_height = 0; |
7992 | 7989 | ||
7993 | dev->mode_config.preferred_depth = 24; |
7990 | dev->mode_config.preferred_depth = 24; |
7994 | dev->mode_config.prefer_shadow = 1; |
7991 | dev->mode_config.prefer_shadow = 1; |
7995 | 7992 | ||
7996 | dev->mode_config.funcs = &intel_mode_funcs; |
7993 | dev->mode_config.funcs = &intel_mode_funcs; |
7997 | 7994 | ||
7998 | intel_init_quirks(dev); |
7995 | intel_init_quirks(dev); |
7999 | 7996 | ||
8000 | intel_init_pm(dev); |
7997 | intel_init_pm(dev); |
8001 | 7998 | ||
8002 | intel_init_display(dev); |
7999 | intel_init_display(dev); |
8003 | 8000 | ||
8004 | if (IS_GEN2(dev)) { |
8001 | if (IS_GEN2(dev)) { |
8005 | dev->mode_config.max_width = 2048; |
8002 | dev->mode_config.max_width = 2048; |
8006 | dev->mode_config.max_height = 2048; |
8003 | dev->mode_config.max_height = 2048; |
8007 | } else if (IS_GEN3(dev)) { |
8004 | } else if (IS_GEN3(dev)) { |
8008 | dev->mode_config.max_width = 4096; |
8005 | dev->mode_config.max_width = 4096; |
8009 | dev->mode_config.max_height = 4096; |
8006 | dev->mode_config.max_height = 4096; |
8010 | } else { |
8007 | } else { |
8011 | dev->mode_config.max_width = 8192; |
8008 | dev->mode_config.max_width = 8192; |
8012 | dev->mode_config.max_height = 8192; |
8009 | dev->mode_config.max_height = 8192; |
8013 | } |
8010 | } |
8014 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
8011 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
8015 | 8012 | ||
8016 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
8013 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
8017 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
8014 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
8018 | 8015 | ||
8019 | for (i = 0; i < dev_priv->num_pipe; i++) { |
8016 | for (i = 0; i < dev_priv->num_pipe; i++) { |
8020 | intel_crtc_init(dev, i); |
8017 | intel_crtc_init(dev, i); |
8021 | ret = intel_plane_init(dev, i); |
8018 | ret = intel_plane_init(dev, i); |
8022 | if (ret) |
8019 | if (ret) |
8023 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); |
8020 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); |
8024 | } |
8021 | } |
8025 | 8022 | ||
8026 | intel_pch_pll_init(dev); |
8023 | intel_pch_pll_init(dev); |
8027 | 8024 | ||
8028 | /* Just disable it once at startup */ |
8025 | /* Just disable it once at startup */ |
8029 | i915_disable_vga(dev); |
8026 | i915_disable_vga(dev); |
8030 | intel_setup_outputs(dev); |
8027 | intel_setup_outputs(dev); |
8031 | } |
8028 | } |
8032 | 8029 | ||
8033 | static void |
8030 | static void |
8034 | intel_connector_break_all_links(struct intel_connector *connector) |
8031 | intel_connector_break_all_links(struct intel_connector *connector) |
8035 | { |
8032 | { |
8036 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
8033 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
8037 | connector->base.encoder = NULL; |
8034 | connector->base.encoder = NULL; |
8038 | connector->encoder->connectors_active = false; |
8035 | connector->encoder->connectors_active = false; |
8039 | connector->encoder->base.crtc = NULL; |
8036 | connector->encoder->base.crtc = NULL; |
8040 | } |
8037 | } |
8041 | 8038 | ||
8042 | static void intel_enable_pipe_a(struct drm_device *dev) |
8039 | static void intel_enable_pipe_a(struct drm_device *dev) |
8043 | { |
8040 | { |
8044 | struct intel_connector *connector; |
8041 | struct intel_connector *connector; |
8045 | struct drm_connector *crt = NULL; |
8042 | struct drm_connector *crt = NULL; |
8046 | struct intel_load_detect_pipe load_detect_temp; |
8043 | struct intel_load_detect_pipe load_detect_temp; |
8047 | 8044 | ||
8048 | /* We can't just switch on the pipe A, we need to set things up with a |
8045 | /* We can't just switch on the pipe A, we need to set things up with a |
8049 | * proper mode and output configuration. As a gross hack, enable pipe A |
8046 | * proper mode and output configuration. As a gross hack, enable pipe A |
8050 | * by enabling the load detect pipe once. */ |
8047 | * by enabling the load detect pipe once. */ |
8051 | list_for_each_entry(connector, |
8048 | list_for_each_entry(connector, |
8052 | &dev->mode_config.connector_list, |
8049 | &dev->mode_config.connector_list, |
8053 | base.head) { |
8050 | base.head) { |
8054 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
8051 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
8055 | crt = &connector->base; |
8052 | crt = &connector->base; |
8056 | break; |
8053 | break; |
8057 | } |
8054 | } |
8058 | } |
8055 | } |
8059 | 8056 | ||
8060 | if (!crt) |
8057 | if (!crt) |
8061 | return; |
8058 | return; |
8062 | 8059 | ||
8063 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
8060 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
8064 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
8061 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
8065 | 8062 | ||
8066 | 8063 | ||
8067 | } |
8064 | } |
8068 | 8065 | ||
8069 | static bool |
8066 | static bool |
8070 | intel_check_plane_mapping(struct intel_crtc *crtc) |
8067 | intel_check_plane_mapping(struct intel_crtc *crtc) |
8071 | { |
8068 | { |
8072 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8069 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8073 | u32 reg, val; |
8070 | u32 reg, val; |
8074 | 8071 | ||
8075 | if (dev_priv->num_pipe == 1) |
8072 | if (dev_priv->num_pipe == 1) |
8076 | return true; |
8073 | return true; |
8077 | 8074 | ||
8078 | reg = DSPCNTR(!crtc->plane); |
8075 | reg = DSPCNTR(!crtc->plane); |
8079 | val = I915_READ(reg); |
8076 | val = I915_READ(reg); |
8080 | 8077 | ||
8081 | if ((val & DISPLAY_PLANE_ENABLE) && |
8078 | if ((val & DISPLAY_PLANE_ENABLE) && |
8082 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
8079 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
8083 | return false; |
8080 | return false; |
8084 | 8081 | ||
8085 | return true; |
8082 | return true; |
8086 | } |
8083 | } |
8087 | 8084 | ||
8088 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8085 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8089 | { |
8086 | { |
8090 | struct drm_device *dev = crtc->base.dev; |
8087 | struct drm_device *dev = crtc->base.dev; |
8091 | struct drm_i915_private *dev_priv = dev->dev_private; |
8088 | struct drm_i915_private *dev_priv = dev->dev_private; |
8092 | u32 reg; |
8089 | u32 reg; |
8093 | 8090 | ||
8094 | /* Clear any frame start delays used for debugging left by the BIOS */ |
8091 | /* Clear any frame start delays used for debugging left by the BIOS */ |
8095 | reg = PIPECONF(crtc->pipe); |
8092 | reg = PIPECONF(crtc->pipe); |
8096 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8093 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8097 | 8094 | ||
8098 | /* We need to sanitize the plane -> pipe mapping first because this will |
8095 | /* We need to sanitize the plane -> pipe mapping first because this will |
8099 | * disable the crtc (and hence change the state) if it is wrong. Note |
8096 | * disable the crtc (and hence change the state) if it is wrong. Note |
8100 | * that gen4+ has a fixed plane -> pipe mapping. */ |
8097 | * that gen4+ has a fixed plane -> pipe mapping. */ |
8101 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
8098 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
8102 | struct intel_connector *connector; |
8099 | struct intel_connector *connector; |
8103 | bool plane; |
8100 | bool plane; |
8104 | 8101 | ||
8105 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8102 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8106 | crtc->base.base.id); |
8103 | crtc->base.base.id); |
8107 | 8104 | ||
8108 | /* Pipe has the wrong plane attached and the plane is active. |
8105 | /* Pipe has the wrong plane attached and the plane is active. |
8109 | * Temporarily change the plane mapping and disable everything |
8106 | * Temporarily change the plane mapping and disable everything |
8110 | * ... */ |
8107 | * ... */ |
8111 | plane = crtc->plane; |
8108 | plane = crtc->plane; |
8112 | crtc->plane = !plane; |
8109 | crtc->plane = !plane; |
8113 | dev_priv->display.crtc_disable(&crtc->base); |
8110 | dev_priv->display.crtc_disable(&crtc->base); |
8114 | crtc->plane = plane; |
8111 | crtc->plane = plane; |
8115 | 8112 | ||
8116 | /* ... and break all links. */ |
8113 | /* ... and break all links. */ |
8117 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8114 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8118 | base.head) { |
8115 | base.head) { |
8119 | if (connector->encoder->base.crtc != &crtc->base) |
8116 | if (connector->encoder->base.crtc != &crtc->base) |
8120 | continue; |
8117 | continue; |
8121 | 8118 | ||
8122 | intel_connector_break_all_links(connector); |
8119 | intel_connector_break_all_links(connector); |
8123 | } |
8120 | } |
8124 | 8121 | ||
8125 | WARN_ON(crtc->active); |
8122 | WARN_ON(crtc->active); |
8126 | crtc->base.enabled = false; |
8123 | crtc->base.enabled = false; |
8127 | } |
8124 | } |
8128 | 8125 | ||
8129 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8126 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8130 | crtc->pipe == PIPE_A && !crtc->active) { |
8127 | crtc->pipe == PIPE_A && !crtc->active) { |
8131 | /* BIOS forgot to enable pipe A, this mostly happens after |
8128 | /* BIOS forgot to enable pipe A, this mostly happens after |
8132 | * resume. Force-enable the pipe to fix this, the update_dpms |
8129 | * resume. Force-enable the pipe to fix this, the update_dpms |
8133 | * call below we restore the pipe to the right state, but leave |
8130 | * call below we restore the pipe to the right state, but leave |
8134 | * the required bits on. */ |
8131 | * the required bits on. */ |
8135 | intel_enable_pipe_a(dev); |
8132 | intel_enable_pipe_a(dev); |
8136 | } |
8133 | } |
8137 | 8134 | ||
8138 | /* Adjust the state of the output pipe according to whether we |
8135 | /* Adjust the state of the output pipe according to whether we |
8139 | * have active connectors/encoders. */ |
8136 | * have active connectors/encoders. */ |
8140 | intel_crtc_update_dpms(&crtc->base); |
8137 | intel_crtc_update_dpms(&crtc->base); |
8141 | 8138 | ||
8142 | if (crtc->active != crtc->base.enabled) { |
8139 | if (crtc->active != crtc->base.enabled) { |
8143 | struct intel_encoder *encoder; |
8140 | struct intel_encoder *encoder; |
8144 | 8141 | ||
8145 | /* This can happen either due to bugs in the get_hw_state |
8142 | /* This can happen either due to bugs in the get_hw_state |
8146 | * functions or because the pipe is force-enabled due to the |
8143 | * functions or because the pipe is force-enabled due to the |
8147 | * pipe A quirk. */ |
8144 | * pipe A quirk. */ |
8148 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
8145 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
8149 | crtc->base.base.id, |
8146 | crtc->base.base.id, |
8150 | crtc->base.enabled ? "enabled" : "disabled", |
8147 | crtc->base.enabled ? "enabled" : "disabled", |
8151 | crtc->active ? "enabled" : "disabled"); |
8148 | crtc->active ? "enabled" : "disabled"); |
8152 | 8149 | ||
8153 | crtc->base.enabled = crtc->active; |
8150 | crtc->base.enabled = crtc->active; |
8154 | 8151 | ||
8155 | /* Because we only establish the connector -> encoder -> |
8152 | /* Because we only establish the connector -> encoder -> |
8156 | * crtc links if something is active, this means the |
8153 | * crtc links if something is active, this means the |
8157 | * crtc is now deactivated. Break the links. connector |
8154 | * crtc is now deactivated. Break the links. connector |
8158 | * -> encoder links are only establish when things are |
8155 | * -> encoder links are only establish when things are |
8159 | * actually up, hence no need to break them. */ |
8156 | * actually up, hence no need to break them. */ |
8160 | WARN_ON(crtc->active); |
8157 | WARN_ON(crtc->active); |
8161 | 8158 | ||
8162 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
8159 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
8163 | WARN_ON(encoder->connectors_active); |
8160 | WARN_ON(encoder->connectors_active); |
8164 | encoder->base.crtc = NULL; |
8161 | encoder->base.crtc = NULL; |
8165 | } |
8162 | } |
8166 | } |
8163 | } |
8167 | } |
8164 | } |
8168 | 8165 | ||
8169 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
8166 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
8170 | { |
8167 | { |
8171 | struct intel_connector *connector; |
8168 | struct intel_connector *connector; |
8172 | struct drm_device *dev = encoder->base.dev; |
8169 | struct drm_device *dev = encoder->base.dev; |
8173 | 8170 | ||
8174 | /* We need to check both for a crtc link (meaning that the |
8171 | /* We need to check both for a crtc link (meaning that the |
8175 | * encoder is active and trying to read from a pipe) and the |
8172 | * encoder is active and trying to read from a pipe) and the |
8176 | * pipe itself being active. */ |
8173 | * pipe itself being active. */ |
8177 | bool has_active_crtc = encoder->base.crtc && |
8174 | bool has_active_crtc = encoder->base.crtc && |
8178 | to_intel_crtc(encoder->base.crtc)->active; |
8175 | to_intel_crtc(encoder->base.crtc)->active; |
8179 | 8176 | ||
8180 | if (encoder->connectors_active && !has_active_crtc) { |
8177 | if (encoder->connectors_active && !has_active_crtc) { |
8181 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
8178 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
8182 | encoder->base.base.id, |
8179 | encoder->base.base.id, |
8183 | drm_get_encoder_name(&encoder->base)); |
8180 | drm_get_encoder_name(&encoder->base)); |
8184 | 8181 | ||
8185 | /* Connector is active, but has no active pipe. This is |
8182 | /* Connector is active, but has no active pipe. This is |
8186 | * fallout from our resume register restoring. Disable |
8183 | * fallout from our resume register restoring. Disable |
8187 | * the encoder manually again. */ |
8184 | * the encoder manually again. */ |
8188 | if (encoder->base.crtc) { |
8185 | if (encoder->base.crtc) { |
8189 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
8186 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
8190 | encoder->base.base.id, |
8187 | encoder->base.base.id, |
8191 | drm_get_encoder_name(&encoder->base)); |
8188 | drm_get_encoder_name(&encoder->base)); |
8192 | encoder->disable(encoder); |
8189 | encoder->disable(encoder); |
8193 | } |
8190 | } |
8194 | 8191 | ||
8195 | /* Inconsistent output/port/pipe state happens presumably due to |
8192 | /* Inconsistent output/port/pipe state happens presumably due to |
8196 | * a bug in one of the get_hw_state functions. Or someplace else |
8193 | * a bug in one of the get_hw_state functions. Or someplace else |
8197 | * in our code, like the register restore mess on resume. Clamp |
8194 | * in our code, like the register restore mess on resume. Clamp |
8198 | * things to off as a safer default. */ |
8195 | * things to off as a safer default. */ |
8199 | list_for_each_entry(connector, |
8196 | list_for_each_entry(connector, |
8200 | &dev->mode_config.connector_list, |
8197 | &dev->mode_config.connector_list, |
8201 | base.head) { |
8198 | base.head) { |
8202 | if (connector->encoder != encoder) |
8199 | if (connector->encoder != encoder) |
8203 | continue; |
8200 | continue; |
8204 | 8201 | ||
8205 | intel_connector_break_all_links(connector); |
8202 | intel_connector_break_all_links(connector); |
8206 | } |
8203 | } |
8207 | } |
8204 | } |
8208 | /* Enabled encoders without active connectors will be fixed in |
8205 | /* Enabled encoders without active connectors will be fixed in |
8209 | * the crtc fixup. */ |
8206 | * the crtc fixup. */ |
8210 | } |
8207 | } |
8211 | 8208 | ||
8212 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
8209 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
8213 | * and i915 state tracking structures. */ |
8210 | * and i915 state tracking structures. */ |
8214 | void intel_modeset_setup_hw_state(struct drm_device *dev) |
8211 | void intel_modeset_setup_hw_state(struct drm_device *dev) |
8215 | { |
8212 | { |
8216 | struct drm_i915_private *dev_priv = dev->dev_private; |
8213 | struct drm_i915_private *dev_priv = dev->dev_private; |
8217 | enum pipe pipe; |
8214 | enum pipe pipe; |
8218 | u32 tmp; |
8215 | u32 tmp; |
8219 | struct intel_crtc *crtc; |
8216 | struct intel_crtc *crtc; |
8220 | struct intel_encoder *encoder; |
8217 | struct intel_encoder *encoder; |
8221 | struct intel_connector *connector; |
8218 | struct intel_connector *connector; |
8222 | 8219 | ||
8223 | for_each_pipe(pipe) { |
8220 | for_each_pipe(pipe) { |
8224 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
8221 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
8225 | 8222 | ||
8226 | tmp = I915_READ(PIPECONF(pipe)); |
8223 | tmp = I915_READ(PIPECONF(pipe)); |
8227 | if (tmp & PIPECONF_ENABLE) |
8224 | if (tmp & PIPECONF_ENABLE) |
8228 | crtc->active = true; |
8225 | crtc->active = true; |
8229 | else |
8226 | else |
8230 | crtc->active = false; |
8227 | crtc->active = false; |
8231 | 8228 | ||
8232 | crtc->base.enabled = crtc->active; |
8229 | crtc->base.enabled = crtc->active; |
8233 | 8230 | ||
8234 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
8231 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
8235 | crtc->base.base.id, |
8232 | crtc->base.base.id, |
8236 | crtc->active ? "enabled" : "disabled"); |
8233 | crtc->active ? "enabled" : "disabled"); |
8237 | } |
8234 | } |
8238 | 8235 | ||
8239 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8236 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8240 | base.head) { |
8237 | base.head) { |
8241 | pipe = 0; |
8238 | pipe = 0; |
8242 | 8239 | ||
8243 | if (encoder->get_hw_state(encoder, &pipe)) { |
8240 | if (encoder->get_hw_state(encoder, &pipe)) { |
8244 | encoder->base.crtc = |
8241 | encoder->base.crtc = |
8245 | dev_priv->pipe_to_crtc_mapping[pipe]; |
8242 | dev_priv->pipe_to_crtc_mapping[pipe]; |
8246 | } else { |
8243 | } else { |
8247 | encoder->base.crtc = NULL; |
8244 | encoder->base.crtc = NULL; |
8248 | } |
8245 | } |
8249 | 8246 | ||
8250 | encoder->connectors_active = false; |
8247 | encoder->connectors_active = false; |
8251 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
8248 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
8252 | encoder->base.base.id, |
8249 | encoder->base.base.id, |
8253 | drm_get_encoder_name(&encoder->base), |
8250 | drm_get_encoder_name(&encoder->base), |
8254 | encoder->base.crtc ? "enabled" : "disabled", |
8251 | encoder->base.crtc ? "enabled" : "disabled", |
8255 | pipe); |
8252 | pipe); |
8256 | } |
8253 | } |
8257 | 8254 | ||
8258 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8255 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8259 | base.head) { |
8256 | base.head) { |
8260 | if (connector->get_hw_state(connector)) { |
8257 | if (connector->get_hw_state(connector)) { |
8261 | connector->base.dpms = DRM_MODE_DPMS_ON; |
8258 | connector->base.dpms = DRM_MODE_DPMS_ON; |
8262 | connector->encoder->connectors_active = true; |
8259 | connector->encoder->connectors_active = true; |
8263 | connector->base.encoder = &connector->encoder->base; |
8260 | connector->base.encoder = &connector->encoder->base; |
8264 | } else { |
8261 | } else { |
8265 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
8262 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
8266 | connector->base.encoder = NULL; |
8263 | connector->base.encoder = NULL; |
8267 | } |
8264 | } |
8268 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
8265 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
8269 | connector->base.base.id, |
8266 | connector->base.base.id, |
8270 | drm_get_connector_name(&connector->base), |
8267 | drm_get_connector_name(&connector->base), |
8271 | connector->base.encoder ? "enabled" : "disabled"); |
8268 | connector->base.encoder ? "enabled" : "disabled"); |
8272 | } |
8269 | } |
8273 | 8270 | ||
8274 | /* HW state is read out, now we need to sanitize this mess. */ |
8271 | /* HW state is read out, now we need to sanitize this mess. */ |
8275 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8272 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8276 | base.head) { |
8273 | base.head) { |
8277 | intel_sanitize_encoder(encoder); |
8274 | intel_sanitize_encoder(encoder); |
8278 | } |
8275 | } |
8279 | 8276 | ||
8280 | for_each_pipe(pipe) { |
8277 | for_each_pipe(pipe) { |
8281 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
8278 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
8282 | intel_sanitize_crtc(crtc); |
8279 | intel_sanitize_crtc(crtc); |
8283 | } |
8280 | } |
8284 | 8281 | ||
8285 | intel_modeset_update_staged_output_state(dev); |
8282 | intel_modeset_update_staged_output_state(dev); |
8286 | 8283 | ||
8287 | intel_modeset_check_state(dev); |
8284 | intel_modeset_check_state(dev); |
8288 | } |
8285 | } |
8289 | 8286 | ||
8290 | void intel_modeset_gem_init(struct drm_device *dev) |
8287 | void intel_modeset_gem_init(struct drm_device *dev) |
8291 | { |
8288 | { |
8292 | intel_modeset_init_hw(dev); |
8289 | intel_modeset_init_hw(dev); |
8293 | 8290 | ||
8294 | // intel_setup_overlay(dev); |
8291 | // intel_setup_overlay(dev); |
8295 | 8292 | ||
8296 | intel_modeset_setup_hw_state(dev); |
8293 | intel_modeset_setup_hw_state(dev); |
8297 | } |
8294 | } |
8298 | 8295 | ||
8299 | void intel_modeset_cleanup(struct drm_device *dev) |
8296 | void intel_modeset_cleanup(struct drm_device *dev) |
8300 | { |
8297 | { |
8301 | #if 0 |
8298 | #if 0 |
8302 | struct drm_i915_private *dev_priv = dev->dev_private; |
8299 | struct drm_i915_private *dev_priv = dev->dev_private; |
8303 | struct drm_crtc *crtc; |
8300 | struct drm_crtc *crtc; |
8304 | struct intel_crtc *intel_crtc; |
8301 | struct intel_crtc *intel_crtc; |
8305 | 8302 | ||
8306 | // drm_kms_helper_poll_fini(dev); |
8303 | // drm_kms_helper_poll_fini(dev); |
8307 | mutex_lock(&dev->struct_mutex); |
8304 | mutex_lock(&dev->struct_mutex); |
8308 | 8305 | ||
8309 | // intel_unregister_dsm_handler(); |
8306 | // intel_unregister_dsm_handler(); |
8310 | 8307 | ||
8311 | 8308 | ||
8312 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8309 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8313 | /* Skip inactive CRTCs */ |
8310 | /* Skip inactive CRTCs */ |
8314 | if (!crtc->fb) |
8311 | if (!crtc->fb) |
8315 | continue; |
8312 | continue; |
8316 | 8313 | ||
8317 | intel_crtc = to_intel_crtc(crtc); |
8314 | intel_crtc = to_intel_crtc(crtc); |
8318 | intel_increase_pllclock(crtc); |
8315 | intel_increase_pllclock(crtc); |
8319 | } |
8316 | } |
8320 | 8317 | ||
8321 | intel_disable_fbc(dev); |
8318 | intel_disable_fbc(dev); |
8322 | 8319 | ||
8323 | intel_disable_gt_powersave(dev); |
8320 | intel_disable_gt_powersave(dev); |
8324 | 8321 | ||
8325 | ironlake_teardown_rc6(dev); |
8322 | ironlake_teardown_rc6(dev); |
8326 | 8323 | ||
8327 | if (IS_VALLEYVIEW(dev)) |
8324 | if (IS_VALLEYVIEW(dev)) |
8328 | vlv_init_dpio(dev); |
8325 | vlv_init_dpio(dev); |
8329 | 8326 | ||
8330 | mutex_unlock(&dev->struct_mutex); |
8327 | mutex_unlock(&dev->struct_mutex); |
8331 | 8328 | ||
8332 | /* Disable the irq before mode object teardown, for the irq might |
8329 | /* Disable the irq before mode object teardown, for the irq might |
8333 | * enqueue unpin/hotplug work. */ |
8330 | * enqueue unpin/hotplug work. */ |
8334 | // drm_irq_uninstall(dev); |
8331 | // drm_irq_uninstall(dev); |
8335 | // cancel_work_sync(&dev_priv->hotplug_work); |
8332 | // cancel_work_sync(&dev_priv->hotplug_work); |
8336 | // cancel_work_sync(&dev_priv->rps.work); |
8333 | // cancel_work_sync(&dev_priv->rps.work); |
8337 | 8334 | ||
8338 | /* flush any delayed tasks or pending work */ |
8335 | /* flush any delayed tasks or pending work */ |
8339 | // flush_scheduled_work(); |
8336 | // flush_scheduled_work(); |
8340 | 8337 | ||
8341 | drm_mode_config_cleanup(dev); |
8338 | drm_mode_config_cleanup(dev); |
8342 | #endif |
8339 | #endif |
8343 | } |
8340 | } |
8344 | 8341 | ||
8345 | /* |
8342 | /* |
8346 | * Return which encoder is currently attached for connector. |
8343 | * Return which encoder is currently attached for connector. |
8347 | */ |
8344 | */ |
8348 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
8345 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
8349 | { |
8346 | { |
8350 | return &intel_attached_encoder(connector)->base; |
8347 | return &intel_attached_encoder(connector)->base; |
8351 | } |
8348 | } |
8352 | 8349 | ||
8353 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8350 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8354 | struct intel_encoder *encoder) |
8351 | struct intel_encoder *encoder) |
8355 | { |
8352 | { |
8356 | connector->encoder = encoder; |
8353 | connector->encoder = encoder; |
8357 | drm_mode_connector_attach_encoder(&connector->base, |
8354 | drm_mode_connector_attach_encoder(&connector->base, |
8358 | &encoder->base); |
8355 | &encoder->base); |
8359 | } |
8356 | } |
8360 | 8357 | ||
8361 | /* |
8358 | /* |
8362 | * set vga decode state - true == enable VGA decode |
8359 | * set vga decode state - true == enable VGA decode |
8363 | */ |
8360 | */ |
8364 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
8361 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
8365 | { |
8362 | { |
8366 | struct drm_i915_private *dev_priv = dev->dev_private; |
8363 | struct drm_i915_private *dev_priv = dev->dev_private; |
8367 | u16 gmch_ctrl; |
8364 | u16 gmch_ctrl; |
8368 | 8365 | ||
8369 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
8366 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
8370 | if (state) |
8367 | if (state) |
8371 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
8368 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
8372 | else |
8369 | else |
8373 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
8370 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
8374 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
8371 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
8375 | return 0; |
8372 | return 0; |
8376 | } |
8373 | } |
8377 | 8374 | ||
8378 | #ifdef CONFIG_DEBUG_FS |
8375 | #ifdef CONFIG_DEBUG_FS |
8379 | #include |
8376 | #include |
8380 | 8377 | ||
8381 | struct intel_display_error_state { |
8378 | struct intel_display_error_state { |
8382 | struct intel_cursor_error_state { |
8379 | struct intel_cursor_error_state { |
8383 | u32 control; |
8380 | u32 control; |
8384 | u32 position; |
8381 | u32 position; |
8385 | u32 base; |
8382 | u32 base; |
8386 | u32 size; |
8383 | u32 size; |
8387 | } cursor[I915_MAX_PIPES]; |
8384 | } cursor[I915_MAX_PIPES]; |
8388 | 8385 | ||
8389 | struct intel_pipe_error_state { |
8386 | struct intel_pipe_error_state { |
8390 | u32 conf; |
8387 | u32 conf; |
8391 | u32 source; |
8388 | u32 source; |
8392 | 8389 | ||
8393 | u32 htotal; |
8390 | u32 htotal; |
8394 | u32 hblank; |
8391 | u32 hblank; |
8395 | u32 hsync; |
8392 | u32 hsync; |
8396 | u32 vtotal; |
8393 | u32 vtotal; |
8397 | u32 vblank; |
8394 | u32 vblank; |
8398 | u32 vsync; |
8395 | u32 vsync; |
8399 | } pipe[I915_MAX_PIPES]; |
8396 | } pipe[I915_MAX_PIPES]; |
8400 | 8397 | ||
8401 | struct intel_plane_error_state { |
8398 | struct intel_plane_error_state { |
8402 | u32 control; |
8399 | u32 control; |
8403 | u32 stride; |
8400 | u32 stride; |
8404 | u32 size; |
8401 | u32 size; |
8405 | u32 pos; |
8402 | u32 pos; |
8406 | u32 addr; |
8403 | u32 addr; |
8407 | u32 surface; |
8404 | u32 surface; |
8408 | u32 tile_offset; |
8405 | u32 tile_offset; |
8409 | } plane[I915_MAX_PIPES]; |
8406 | } plane[I915_MAX_PIPES]; |
8410 | }; |
8407 | }; |
8411 | 8408 | ||
8412 | struct intel_display_error_state * |
8409 | struct intel_display_error_state * |
8413 | intel_display_capture_error_state(struct drm_device *dev) |
8410 | intel_display_capture_error_state(struct drm_device *dev) |
8414 | { |
8411 | { |
8415 | drm_i915_private_t *dev_priv = dev->dev_private; |
8412 | drm_i915_private_t *dev_priv = dev->dev_private; |
8416 | struct intel_display_error_state *error; |
8413 | struct intel_display_error_state *error; |
8417 | int i; |
8414 | int i; |
8418 | 8415 | ||
8419 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
8416 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
8420 | if (error == NULL) |
8417 | if (error == NULL) |
8421 | return NULL; |
8418 | return NULL; |
8422 | 8419 | ||
8423 | for_each_pipe(i) { |
8420 | for_each_pipe(i) { |
8424 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
8421 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
8425 | error->cursor[i].position = I915_READ(CURPOS(i)); |
8422 | error->cursor[i].position = I915_READ(CURPOS(i)); |
8426 | error->cursor[i].base = I915_READ(CURBASE(i)); |
8423 | error->cursor[i].base = I915_READ(CURBASE(i)); |
8427 | 8424 | ||
8428 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
8425 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
8429 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
8426 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
8430 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
8427 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
8431 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
8428 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
8432 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8429 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8433 | if (INTEL_INFO(dev)->gen >= 4) { |
8430 | if (INTEL_INFO(dev)->gen >= 4) { |
8434 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
8431 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
8435 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
8432 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
8436 | } |
8433 | } |
8437 | 8434 | ||
8438 | error->pipe[i].conf = I915_READ(PIPECONF(i)); |
8435 | error->pipe[i].conf = I915_READ(PIPECONF(i)); |
8439 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
8436 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
8440 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); |
8437 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); |
8441 | error->pipe[i].hblank = I915_READ(HBLANK(i)); |
8438 | error->pipe[i].hblank = I915_READ(HBLANK(i)); |
8442 | error->pipe[i].hsync = I915_READ(HSYNC(i)); |
8439 | error->pipe[i].hsync = I915_READ(HSYNC(i)); |
8443 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); |
8440 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); |
8444 | error->pipe[i].vblank = I915_READ(VBLANK(i)); |
8441 | error->pipe[i].vblank = I915_READ(VBLANK(i)); |
8445 | error->pipe[i].vsync = I915_READ(VSYNC(i)); |
8442 | error->pipe[i].vsync = I915_READ(VSYNC(i)); |
8446 | } |
8443 | } |
8447 | 8444 | ||
8448 | return error; |
8445 | return error; |
8449 | } |
8446 | } |
8450 | 8447 | ||
8451 | void |
8448 | void |
8452 | intel_display_print_error_state(struct seq_file *m, |
8449 | intel_display_print_error_state(struct seq_file *m, |
8453 | struct drm_device *dev, |
8450 | struct drm_device *dev, |
8454 | struct intel_display_error_state *error) |
8451 | struct intel_display_error_state *error) |
8455 | { |
8452 | { |
8456 | drm_i915_private_t *dev_priv = dev->dev_private; |
8453 | drm_i915_private_t *dev_priv = dev->dev_private; |
8457 | int i; |
8454 | int i; |
8458 | 8455 | ||
8459 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
8456 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
8460 | for_each_pipe(i) { |
8457 | for_each_pipe(i) { |
8461 | seq_printf(m, "Pipe [%d]:\n", i); |
8458 | seq_printf(m, "Pipe [%d]:\n", i); |
8462 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
8459 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
8463 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); |
8460 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); |
8464 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); |
8461 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); |
8465 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); |
8462 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); |
8466 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); |
8463 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); |
8467 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); |
8464 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); |
8468 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); |
8465 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); |
8469 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); |
8466 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); |
8470 | 8467 | ||
8471 | seq_printf(m, "Plane [%d]:\n", i); |
8468 | seq_printf(m, "Plane [%d]:\n", i); |
8472 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); |
8469 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); |
8473 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
8470 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
8474 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
8471 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
8475 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
8472 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
8476 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
8473 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
8477 | if (INTEL_INFO(dev)->gen >= 4) { |
8474 | if (INTEL_INFO(dev)->gen >= 4) { |
8478 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); |
8475 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); |
8479 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
8476 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
8480 | } |
8477 | } |
8481 | 8478 | ||
8482 | seq_printf(m, "Cursor [%d]:\n", i); |
8479 | seq_printf(m, "Cursor [%d]:\n", i); |
8483 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
8480 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
8484 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); |
8481 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); |
8485 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); |
8482 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); |
8486 | } |
8483 | } |
8487 | } |
8484 | } |
8488 | #endif>>5,><5,>>>><>><>>>>>(intel_crtc)-><(intel_crtc)->><>><>><>><>><>><>><>><>=><=>><>><>><>><>>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>><>><>><>><>><>><>><>>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>20)><20)>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>>>>>>>>><>><>><>><>><>><>><>><>><>>>><>><>>>>>>>><>><>>>><>><>><>>><>><>>>>><>><>><>>>>>=>=>>>>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |
8485 | #endif>>5,><5,>>>><>><>>>>>(intel_crtc)-><(intel_crtc)->><>><>><>><>><>><>><>><>=><=>><>><>><>><>>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>><>><>><>><>><>><>><>>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>20)><20)>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>>>>>>>>><>><>><>><>><>><>><>><>><>>>><>><>>>>>>>><>><>>>><>><>><>>><>><>>>>><>><>><>>>>>=>=>>>>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |