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Line 27... | Line 27... | ||
27 | //#include |
27 | //#include |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | //#include |
32 | #include |
33 | //#include |
33 | //#include |
34 | #include "drmP.h" |
34 | #include "drmP.h" |
35 | #include "intel_drv.h" |
35 | #include "intel_drv.h" |
- | 36 | #include "i915_drm.h" |
|
36 | #include "i915_drv.h" |
37 | #include "i915_drv.h" |
37 | //#include "i915_trace.h" |
38 | //#include "i915_trace.h" |
38 | #include "drm_dp_helper.h" |
39 | #include "drm_dp_helper.h" |
Line 39... | Line 40... | ||
39 | 40 | ||
Line 40... | Line -... | ||
40 | #include "drm_crtc_helper.h" |
- | |
41 | - | ||
42 | #include |
41 | #include "drm_crtc_helper.h" |
Line 43... | Line 42... | ||
43 | 42 | ||
44 | phys_addr_t get_bus_addr(void); |
43 | phys_addr_t get_bus_addr(void); |
45 | 44 | ||
46 | static inline __attribute__((const)) |
45 | static inline __attribute__((const)) |
47 | bool is_power_of_2(unsigned long n) |
46 | bool is_power_of_2(unsigned long n) |
Line -... | Line 47... | ||
- | 47 | { |
|
- | 48 | return (n != 0 && ((n & (n - 1)) == 0)); |
|
- | 49 | } |
|
- | 50 | ||
- | 51 | #define MAX_ERRNO 4095 |
|
- | 52 | ||
- | 53 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
|
- | 54 | ||
- | 55 | static inline long IS_ERR(const void *ptr) |
|
- | 56 | { |
|
- | 57 | return IS_ERR_VALUE((unsigned long)ptr); |
|
- | 58 | } |
|
- | 59 | ||
- | 60 | static inline void *ERR_PTR(long error) |
|
- | 61 | { |
|
48 | { |
62 | return (void *) error; |
49 | return (n != 0 && ((n & (n - 1)) == 0)); |
63 | } |
50 | } |
64 | |
51 | 65 | ||
52 | static inline int pci_read_config_word(struct pci_dev *dev, int where, |
66 | static inline int pci_read_config_word(struct pci_dev *dev, int where, |
Line 1912... | Line -... | ||
1912 | - | ||
1913 | - | ||
1914 | - | ||
1915 | - | ||
1916 | - | ||
1917 | - | ||
1918 | - | ||
1919 | - | ||
1920 | - | ||
1921 | - | ||
1922 | - | ||
1923 | - | ||
1924 | - | ||
1925 | - | ||
1926 | - | ||
1927 | 1926 | ||
1928 | 1927 | ||
1929 | 1928 | ||
1930 | 1929 | ||
1931 | 1930 | ||
Line 2068... | Line 2067... | ||
2068 | // Start = obj->gtt_offset; |
2067 | // Start = obj->gtt_offset; |
2069 | // Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
2068 | // Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
Line 2070... | Line 2069... | ||
2070 | 2069 | ||
2071 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2070 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2072 | Start, Offset, x, y, fb->pitch); |
2071 | Start, Offset, x, y, fb->pitch); |
2073 | // I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
2072 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
2074 | // I915_WRITE(DSPSURF(plane), Start); |
2073 | I915_WRITE(DSPSURF(plane), Start); |
2075 | // I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2074 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2076 | // I915_WRITE(DSPADDR(plane), Offset); |
2075 | I915_WRITE(DSPADDR(plane), Offset); |
Line 2077... | Line 2076... | ||
2077 | // POSTING_READ(reg); |
2076 | POSTING_READ(reg); |
2078 | 2077 | ||
Line 2079... | Line 2078... | ||
2079 | return 0; |
2078 | return 0; |
Line 2165... | Line 2164... | ||
2165 | // intel_wait_for_vblank(dev, intel_crtc->pipe); |
2164 | // intel_wait_for_vblank(dev, intel_crtc->pipe); |
2166 | // i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
2165 | // i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
2167 | } |
2166 | } |
Line 2168... | Line 2167... | ||
2168 | 2167 | ||
- | 2168 | mutex_unlock(&dev->struct_mutex); |
|
- | 2169 | #if 0 |
|
- | 2170 | if (!dev->primary->master) |
|
Line 2169... | Line -... | ||
2169 | mutex_unlock(&dev->struct_mutex); |
- | |
2170 | - | ||
2171 | // if (!dev->primary->master) |
- | |
2172 | // return 0; |
2171 | return 0; |
2173 | 2172 | ||
2174 | // master_priv = dev->primary->master->driver_priv; |
2173 | master_priv = dev->primary->master->driver_priv; |
2175 | // if (!master_priv->sarea_priv) |
- | |
2176 | // return 0; |
- | |
2177 | - | ||
2178 | // if (intel_crtc->pipe) { |
- | |
2179 | // master_priv->sarea_priv->pipeB_x = x; |
- | |
2180 | // master_priv->sarea_priv->pipeB_y = y; |
- | |
2181 | // } else { |
- | |
2182 | // master_priv->sarea_priv->pipeA_x = x; |
- | |
Line -... | Line 2174... | ||
- | 2174 | if (!master_priv->sarea_priv) |
|
- | 2175 | return 0; |
|
- | 2176 | ||
- | 2177 | if (intel_crtc->pipe) { |
|
- | 2178 | master_priv->sarea_priv->pipeB_x = x; |
|
- | 2179 | master_priv->sarea_priv->pipeB_y = y; |
|
- | 2180 | } else { |
|
- | 2181 | master_priv->sarea_priv->pipeA_x = x; |
|
2183 | // master_priv->sarea_priv->pipeA_y = y; |
2182 | master_priv->sarea_priv->pipeA_y = y; |
2184 | // } |
2183 | } |
Line 2185... | Line 2184... | ||
2185 | 2184 | #endif |
|
2186 | return 0; |
2185 | return 0; |
Line 3139... | Line 3138... | ||
3139 | i9xx_crtc_disable(crtc); |
3138 | i9xx_crtc_disable(crtc); |
3140 | break; |
3139 | break; |
3141 | } |
3140 | } |
3142 | } |
3141 | } |
Line -... | Line 3142... | ||
- | 3142 | ||
- | 3143 | /** |
|
- | 3144 | * Sets the power management mode of the pipe and plane. |
|
- | 3145 | */ |
|
- | 3146 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
|
- | 3147 | { |
|
- | 3148 | struct drm_device *dev = crtc->dev; |
|
- | 3149 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3150 | struct drm_i915_master_private *master_priv; |
|
- | 3151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 3152 | int pipe = intel_crtc->pipe; |
|
- | 3153 | bool enabled; |
|
- | 3154 | ||
- | 3155 | if (intel_crtc->dpms_mode == mode) |
|
- | 3156 | return; |
|
- | 3157 | ||
- | 3158 | intel_crtc->dpms_mode = mode; |
|
- | 3159 | ||
- | 3160 | dev_priv->display.dpms(crtc, mode); |
|
- | 3161 | ||
- | 3162 | if (!dev->primary->master) |
|
- | 3163 | return; |
|
- | 3164 | ||
- | 3165 | master_priv = dev->primary->master->driver_priv; |
|
- | 3166 | if (!master_priv->sarea_priv) |
|
- | 3167 | return; |
|
- | 3168 | ||
Line -... | Line 3169... | ||
- | 3169 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
|
- | 3170 | ||
- | 3171 | switch (pipe) { |
|
- | 3172 | case 0: |
|
- | 3173 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
|
- | 3174 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
|
- | 3175 | break; |
|
- | 3176 | case 1: |
|
- | 3177 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
|
- | 3178 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
|
- | 3179 | break; |
|
- | 3180 | default: |
|
- | 3181 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
|
- | 3182 | break; |
|
Line -... | Line 3183... | ||
- | 3183 | } |
|
- | 3184 | } |
|
- | 3185 | ||
- | 3186 | static void intel_crtc_disable(struct drm_crtc *crtc) |
|
Line -... | Line 3187... | ||
- | 3187 | { |
|
Line -... | Line 3188... | ||
- | 3188 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
|
- | 3189 | struct drm_device *dev = crtc->dev; |
|
- | 3190 | ||
- | 3191 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
|
- | 3192 | ||
- | 3193 | if (crtc->fb) { |
|
Line -... | Line 3194... | ||
- | 3194 | mutex_lock(&dev->struct_mutex); |
|
- | 3195 | // i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
|
- | 3196 | mutex_unlock(&dev->struct_mutex); |
|
- | 3197 | } |
|
- | 3198 | } |
|
- | 3199 | ||
- | 3200 | /* Prepare for a mode set. |
|
- | 3201 | * |
|
- | 3202 | * Note we could be a lot smarter here. We need to figure out which outputs |
|
- | 3203 | * will be enabled, which disabled (in short, how the config will changes) |
|
- | 3204 | * and perform the minimum necessary steps to accomplish that, e.g. updating |
|
- | 3205 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, |
|
Line -... | Line 3206... | ||
- | 3206 | * panel fitting is in the proper state, etc. |
|
- | 3207 | */ |
|
- | 3208 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) |
|
- | 3209 | { |
|
Line -... | Line 3210... | ||
- | 3210 | i9xx_crtc_disable(crtc); |
|
- | 3211 | } |
|
- | 3212 | ||
- | 3213 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
|
Line -... | Line 3214... | ||
- | 3214 | { |
|
- | 3215 | i9xx_crtc_enable(crtc); |
|
- | 3216 | } |
|
- | 3217 | ||
Line -... | Line 3218... | ||
- | 3218 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) |
|
- | 3219 | { |
|
- | 3220 | ironlake_crtc_disable(crtc); |
|
- | 3221 | } |
|
- | 3222 | ||
- | 3223 | static void ironlake_crtc_commit(struct drm_crtc *crtc) |
|
Line -... | Line 3224... | ||
- | 3224 | { |
|
- | 3225 | ironlake_crtc_enable(crtc); |
|
- | 3226 | } |
|
- | 3227 | ||
- | 3228 | void intel_encoder_prepare (struct drm_encoder *encoder) |
|
- | 3229 | { |
|
Line -... | Line 3230... | ||
- | 3230 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
|
- | 3231 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
|
- | 3232 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
|
Line -... | Line 3233... | ||
- | 3233 | } |
|
- | 3234 | ||
- | 3235 | void intel_encoder_commit (struct drm_encoder *encoder) |
|
Line -... | Line 3236... | ||
- | 3236 | { |
|
- | 3237 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
|
- | 3238 | /* lvds has its own version of commit see intel_lvds_commit */ |
|
- | 3239 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
|
- | 3240 | } |
|
Line -... | Line 3241... | ||
- | 3241 | ||
- | 3242 | void intel_encoder_destroy(struct drm_encoder *encoder) |
|
- | 3243 | { |
|
- | 3244 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
|
- | 3245 | ||
Line -... | Line 3246... | ||
- | 3246 | drm_encoder_cleanup(encoder); |
|
- | 3247 | kfree(intel_encoder); |
|
- | 3248 | } |
|
- | 3249 | ||
- | 3250 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
|
Line -... | Line 3251... | ||
- | 3251 | struct drm_display_mode *mode, |
|
- | 3252 | struct drm_display_mode *adjusted_mode) |
|
Line 3143... | Line 3253... | ||
3143 | 3253 | { |
|
3144 | 3254 | struct drm_device *dev = crtc->dev; |
|
3145 | 3255 | ||
3146 | 3256 | if (HAS_PCH_SPLIT(dev)) { |
|
Line 5471... | Line 5581... | ||
5471 | intel_update_watermarks(dev); |
5581 | intel_update_watermarks(dev); |
Line 5472... | Line 5582... | ||
5472 | 5582 | ||
5473 | return ret; |
5583 | return ret; |
Line -... | Line 5584... | ||
- | 5584 | } |
|
- | 5585 | ||
- | 5586 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
|
- | 5587 | struct drm_display_mode *mode, |
|
- | 5588 | struct drm_display_mode *adjusted_mode, |
|
- | 5589 | int x, int y, |
|
- | 5590 | struct drm_framebuffer *old_fb) |
|
- | 5591 | { |
|
- | 5592 | struct drm_device *dev = crtc->dev; |
|
- | 5593 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
Line -... | Line 5595... | ||
- | 5595 | int pipe = intel_crtc->pipe; |
|
Line -... | Line 5596... | ||
- | 5596 | int ret; |
|
- | 5597 | ||
Line -... | Line 5598... | ||
- | 5598 | // drm_vblank_pre_modeset(dev, pipe); |
|
Line -... | Line 5599... | ||
- | 5599 | ||
Line -... | Line 5600... | ||
- | 5600 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
|
5474 | } |
5601 | x, y, old_fb); |
Line 5475... | Line 5602... | ||
5475 | 5602 | ||
5476 | 5603 | // drm_vblank_post_modeset(dev, pipe); |
|
5477 | 5604 | ||
5478 | 5605 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; |
|
Line -... | Line 5670... | ||
- | 5670 | ||
- | 5671 | ||
- | 5672 | ||
- | 5673 | ||
- | 5674 | ||
- | 5675 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
|
- | 5676 | u16 *blue, uint32_t start, uint32_t size) |
|
- | 5677 | { |
|
- | 5678 | int end = (start + size > 256) ? 256 : start + size, i; |
|
- | 5679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 5680 | ||
- | 5681 | for (i = start; i < end; i++) { |
|
- | 5682 | intel_crtc->lut_r[i] = red[i] >> 8; |
|
- | 5683 | intel_crtc->lut_g[i] = green[i] >> 8; |
|
- | 5684 | intel_crtc->lut_b[i] = blue[i] >> 8; |
|
- | 5685 | } |
|
- | 5686 | ||
- | 5687 | intel_crtc_load_lut(crtc); |
|
- | 5688 | } |
|
- | 5689 | ||
- | 5690 | /** |
|
- | 5691 | * Get a pipe with a simple mode set on it for doing load-based monitor |
|
- | 5692 | * detection. |
|
- | 5693 | * |
|
- | 5694 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
|
- | 5695 | * its requirements. The pipe will be connected to no other encoders. |
|
- | 5696 | * |
|
- | 5697 | * Currently this code will only succeed if there is a pipe with no encoders |
|
- | 5698 | * configured for it. In the future, it could choose to temporarily disable |
|
- | 5699 | * some outputs to free up a pipe for its use. |
|
- | 5700 | * |
|
- | 5701 | * \return crtc, or NULL if no pipes are available. |
|
- | 5702 | */ |
|
- | 5703 | ||
Line -... | Line 5704... | ||
- | 5704 | /* VESA 640x480x72Hz mode to set on the pipe */ |
|
- | 5705 | static struct drm_display_mode load_detect_mode = { |
|
- | 5706 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
|
- | 5707 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
|
- | 5708 | }; |
|
- | 5709 | ||
Line -... | Line 5710... | ||
- | 5710 | ||
- | 5711 | ||
- | 5712 | ||
- | 5713 | ||
- | 5714 | static u32 |
|
- | 5715 | intel_framebuffer_pitch_for_width(int width, int bpp) |
|
Line -... | Line 5716... | ||
- | 5716 | { |
|
- | 5717 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
|
- | 5718 | return ALIGN(pitch, 64); |
|
- | 5719 | } |
|
- | 5720 | ||
- | 5721 | static u32 |
|
- | 5722 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
|
Line -... | Line 5723... | ||
- | 5723 | { |
|
- | 5724 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
|
- | 5725 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
|
- | 5726 | } |
|
Line -... | Line 5727... | ||
- | 5727 | ||
- | 5728 | static struct drm_framebuffer * |
|
- | 5729 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
|
- | 5730 | struct drm_display_mode *mode, |
|
- | 5731 | int depth, int bpp) |
|
Line -... | Line 5732... | ||
- | 5732 | { |
|
- | 5733 | struct drm_i915_gem_object *obj; |
|
Line -... | Line 5734... | ||
- | 5734 | struct drm_mode_fb_cmd mode_cmd; |
|
- | 5735 | ||
- | 5736 | // obj = i915_gem_alloc_object(dev, |
|
- | 5737 | // intel_framebuffer_size_for_mode(mode, bpp)); |
|
- | 5738 | // if (obj == NULL) |
|
- | 5739 | return ERR_PTR(-ENOMEM); |
|
- | 5740 | ||
Line -... | Line 5741... | ||
- | 5741 | // mode_cmd.width = mode->hdisplay; |
|
- | 5742 | // mode_cmd.height = mode->vdisplay; |
|
Line -... | Line 5743... | ||
- | 5743 | // mode_cmd.depth = depth; |
|
- | 5744 | // mode_cmd.bpp = bpp; |
|
- | 5745 | // mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); |
|
- | 5746 | ||
- | 5747 | // return intel_framebuffer_create(dev, &mode_cmd, obj); |
|
- | 5748 | } |
|
- | 5749 | ||
- | 5750 | static struct drm_framebuffer * |
|
Line -... | Line 5751... | ||
- | 5751 | mode_fits_in_fbdev(struct drm_device *dev, |
|
- | 5752 | struct drm_display_mode *mode) |
|
Line -... | Line 5753... | ||
- | 5753 | { |
|
- | 5754 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line -... | Line 5755... | ||
- | 5755 | struct drm_i915_gem_object *obj; |
|
- | 5756 | struct drm_framebuffer *fb; |
|
- | 5757 | ||
- | 5758 | // if (dev_priv->fbdev == NULL) |
|
- | 5759 | // return NULL; |
|
- | 5760 | ||
- | 5761 | // obj = dev_priv->fbdev->ifb.obj; |
|
- | 5762 | // if (obj == NULL) |
|
- | 5763 | // return NULL; |
|
- | 5764 | ||
- | 5765 | // fb = &dev_priv->fbdev->ifb.base; |
|
- | 5766 | // if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay, |
|
- | 5767 | // fb->bits_per_pixel)) |
|
- | 5768 | return NULL; |
|
- | 5769 | ||
- | 5770 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
|
Line -... | Line 5771... | ||
- | 5771 | // return NULL; |
|
- | 5772 | ||
- | 5773 | // return fb; |
|
- | 5774 | } |
|
- | 5775 | ||
- | 5776 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
|
- | 5777 | struct drm_connector *connector, |
|
- | 5778 | struct drm_display_mode *mode, |
|
- | 5779 | struct intel_load_detect_pipe *old) |
|
Line -... | Line 5780... | ||
- | 5780 | { |
|
- | 5781 | struct intel_crtc *intel_crtc; |
|
- | 5782 | struct drm_crtc *possible_crtc; |
|
Line -... | Line 5783... | ||
- | 5783 | struct drm_encoder *encoder = &intel_encoder->base; |
|
- | 5784 | struct drm_crtc *crtc = NULL; |
|
- | 5785 | struct drm_device *dev = encoder->dev; |
|
Line -... | Line 5786... | ||
- | 5786 | struct drm_framebuffer *old_fb; |
|
- | 5787 | int i = -1; |
|
- | 5788 | ||
- | 5789 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
|
Line -... | Line 5790... | ||
- | 5790 | connector->base.id, drm_get_connector_name(connector), |
|
- | 5791 | encoder->base.id, drm_get_encoder_name(encoder)); |
|
Line -... | Line 5792... | ||
- | 5792 | ||
- | 5793 | /* |
|
- | 5794 | * Algorithm gets a little messy: |
|
Line -... | Line 5795... | ||
- | 5795 | * |
|
- | 5796 | * - if the connector already has an assigned crtc, use it (but make |
|
Line -... | Line 5797... | ||
- | 5797 | * sure it's on first) |
|
- | 5798 | * |
|
- | 5799 | * - try to find the first unused crtc that can drive this connector, |
|
- | 5800 | * and use that if we find one |
|
- | 5801 | */ |
|
- | 5802 | ||
- | 5803 | /* See if we already have a CRTC for this connector */ |
|
- | 5804 | if (encoder->crtc) { |
|
- | 5805 | crtc = encoder->crtc; |
|
- | 5806 | ||
Line -... | Line 5807... | ||
- | 5807 | intel_crtc = to_intel_crtc(crtc); |
|
- | 5808 | old->dpms_mode = intel_crtc->dpms_mode; |
|
- | 5809 | old->load_detect_temp = false; |
|
- | 5810 | ||
- | 5811 | /* Make sure the crtc and connector are running */ |
|
- | 5812 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
|
- | 5813 | struct drm_encoder_helper_funcs *encoder_funcs; |
|
Line -... | Line 5814... | ||
- | 5814 | struct drm_crtc_helper_funcs *crtc_funcs; |
|
- | 5815 | ||
Line -... | Line 5816... | ||
- | 5816 | crtc_funcs = crtc->helper_private; |
|
- | 5817 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
|
- | 5818 | ||
- | 5819 | encoder_funcs = encoder->helper_private; |
|
- | 5820 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
|
- | 5821 | } |
|
- | 5822 | ||
- | 5823 | return true; |
|
- | 5824 | } |
|
- | 5825 | ||
- | 5826 | /* Find an unused one (if possible) */ |
|
- | 5827 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
|
- | 5828 | i++; |
|
- | 5829 | if (!(encoder->possible_crtcs & (1 << i))) |
|
- | 5830 | continue; |
|
- | 5831 | if (!possible_crtc->enabled) { |
|
- | 5832 | crtc = possible_crtc; |
|
- | 5833 | break; |
|
- | 5834 | } |
|
- | 5835 | } |
|
- | 5836 | ||
- | 5837 | /* |
|
- | 5838 | * If we didn't find an unused CRTC, don't use any. |
|
- | 5839 | */ |
|
- | 5840 | if (!crtc) { |
|
- | 5841 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
|
- | 5842 | return false; |
|
- | 5843 | } |
|
- | 5844 | ||
Line -... | Line 5845... | ||
- | 5845 | encoder->crtc = crtc; |
|
- | 5846 | connector->encoder = encoder; |
|
- | 5847 | ||
- | 5848 | intel_crtc = to_intel_crtc(crtc); |
|
- | 5849 | old->dpms_mode = intel_crtc->dpms_mode; |
|
- | 5850 | old->load_detect_temp = true; |
|
- | 5851 | old->release_fb = NULL; |
|
Line -... | Line 5852... | ||
- | 5852 | ||
- | 5853 | if (!mode) |
|
Line -... | Line 5854... | ||
- | 5854 | mode = &load_detect_mode; |
|
- | 5855 | ||
Line -... | Line 5856... | ||
- | 5856 | old_fb = crtc->fb; |
|
- | 5857 | ||
- | 5858 | /* We need a framebuffer large enough to accommodate all accesses |
|
- | 5859 | * that the plane may generate whilst we perform load detection. |
|
- | 5860 | * We can not rely on the fbcon either being present (we get called |
|
- | 5861 | * during its initialisation to detect all boot displays, or it may |
|
- | 5862 | * not even exist) or that it is large enough to satisfy the |
|
- | 5863 | * requested mode. |
|
- | 5864 | */ |
|
- | 5865 | crtc->fb = mode_fits_in_fbdev(dev, mode); |
|
- | 5866 | if (crtc->fb == NULL) { |
|
- | 5867 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
|
- | 5868 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
|
- | 5869 | old->release_fb = crtc->fb; |
|
- | 5870 | } else |
|
- | 5871 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
|
- | 5872 | if (IS_ERR(crtc->fb)) { |
|
Line -... | Line 5873... | ||
- | 5873 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
|
- | 5874 | crtc->fb = old_fb; |
|
Line -... | Line 5875... | ||
- | 5875 | return false; |
|
- | 5876 | } |
|
Line -... | Line 5877... | ||
- | 5877 | ||
- | 5878 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
|
- | 5879 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
|
- | 5880 | if (old->release_fb) |
|
- | 5881 | old->release_fb->funcs->destroy(old->release_fb); |
|
- | 5882 | crtc->fb = old_fb; |
|
Line -... | Line 5883... | ||
- | 5883 | return false; |
|
- | 5884 | } |
|
- | 5885 | ||
- | 5886 | /* let the connector get through one full cycle before testing */ |
|
- | 5887 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 5888 | ||
- | 5889 | return true; |
|
- | 5890 | } |
|
- | 5891 | ||
Line -... | Line 5892... | ||
- | 5892 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
|
- | 5893 | struct drm_connector *connector, |
|
- | 5894 | struct intel_load_detect_pipe *old) |
|
- | 5895 | { |
|
Line -... | Line 5896... | ||
- | 5896 | struct drm_encoder *encoder = &intel_encoder->base; |
|
- | 5897 | struct drm_device *dev = encoder->dev; |
|
- | 5898 | struct drm_crtc *crtc = encoder->crtc; |
|
- | 5899 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
|
- | 5900 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
|
- | 5901 | ||
- | 5902 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
|
- | 5903 | connector->base.id, drm_get_connector_name(connector), |
|
Line -... | Line 5904... | ||
- | 5904 | encoder->base.id, drm_get_encoder_name(encoder)); |
|
- | 5905 | ||
- | 5906 | if (old->load_detect_temp) { |
|
- | 5907 | connector->encoder = NULL; |
|
- | 5908 | drm_helper_disable_unused_functions(dev); |
|
- | 5909 | ||
- | 5910 | if (old->release_fb) |
|
Line -... | Line 5911... | ||
- | 5911 | old->release_fb->funcs->destroy(old->release_fb); |
|
- | 5912 | ||
- | 5913 | return; |
|
- | 5914 | } |
|
- | 5915 | ||
- | 5916 | /* Switch crtc and encoder back off if necessary */ |
|
- | 5917 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
|
- | 5918 | encoder_funcs->dpms(encoder, old->dpms_mode); |
|
- | 5919 | crtc_funcs->dpms(crtc, old->dpms_mode); |
|
- | 5920 | } |
|
- | 5921 | } |
|
- | 5922 | ||
- | 5923 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
|
- | 5924 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
|
Line -... | Line 5925... | ||
- | 5925 | { |
|
- | 5926 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 5927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 5928 | int pipe = intel_crtc->pipe; |
|
Line -... | Line 5929... | ||
- | 5929 | u32 dpll = I915_READ(DPLL(pipe)); |
|
- | 5930 | u32 fp; |
|
- | 5931 | intel_clock_t clock; |
|
- | 5932 | ||
- | 5933 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
|
- | 5934 | fp = I915_READ(FP0(pipe)); |
|
- | 5935 | else |
|
- | 5936 | fp = I915_READ(FP1(pipe)); |
|
- | 5937 | ||
- | 5938 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
|
- | 5939 | if (IS_PINEVIEW(dev)) { |
|
- | 5940 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
|
- | 5941 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
|
- | 5942 | } else { |
|
- | 5943 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
|
- | 5944 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
|
- | 5945 | } |
|
- | 5946 | ||
- | 5947 | if (!IS_GEN2(dev)) { |
|
- | 5948 | if (IS_PINEVIEW(dev)) |
|
- | 5949 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
|
- | 5950 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
|
Line -... | Line 5951... | ||
- | 5951 | else |
|
- | 5952 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
|
- | 5953 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
|
Line -... | Line 5954... | ||
- | 5954 | ||
- | 5955 | switch (dpll & DPLL_MODE_MASK) { |
|
- | 5956 | case DPLLB_MODE_DAC_SERIAL: |
|
- | 5957 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
|
Line -... | Line 5958... | ||
- | 5958 | 5 : 10; |
|
- | 5959 | break; |
|
Line -... | Line 5960... | ||
- | 5960 | case DPLLB_MODE_LVDS: |
|
- | 5961 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
|
- | 5962 | 7 : 14; |
|
- | 5963 | break; |
|
- | 5964 | default: |
|
- | 5965 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
|
- | 5966 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
|
- | 5967 | return 0; |
|
- | 5968 | } |
|
- | 5969 | ||
- | 5970 | /* XXX: Handle the 100Mhz refclk */ |
|
- | 5971 | intel_clock(dev, 96000, &clock); |
|
Line -... | Line 5972... | ||
- | 5972 | } else { |
|
- | 5973 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
|
- | 5974 | ||
Line -... | Line 5975... | ||
- | 5975 | if (is_lvds) { |
|
- | 5976 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
|
- | 5977 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
|
- | 5978 | clock.p2 = 14; |
|
- | 5979 | ||
- | 5980 | if ((dpll & PLL_REF_INPUT_MASK) == |
|
- | 5981 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
|
- | 5982 | /* XXX: might not be 66MHz */ |
|
- | 5983 | intel_clock(dev, 66000, &clock); |
|
Line -... | Line 5984... | ||
- | 5984 | } else |
|
- | 5985 | intel_clock(dev, 48000, &clock); |
|
Line -... | Line 5986... | ||
- | 5986 | } else { |
|
- | 5987 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
|
Line -... | Line 5988... | ||
- | 5988 | clock.p1 = 2; |
|
Line -... | Line 5989... | ||
- | 5989 | else { |
|
Line 5543... | Line 5990... | ||
5543 | 5990 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
|
Line -... | Line 6109... | ||
- | 6109 | ||
- | 6110 | ||
- | 6111 | ||
- | 6112 | ||
- | 6113 | ||
- | 6114 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
|
Line -... | Line 6115... | ||
- | 6115 | { |
|
- | 6116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 6117 | struct drm_device *dev = crtc->dev; |
|
- | 6118 | struct intel_unpin_work *work; |
|
Line -... | Line 6119... | ||
- | 6119 | unsigned long flags; |
|
- | 6120 | ||
- | 6121 | spin_lock_irqsave(&dev->event_lock, flags); |
|
- | 6122 | work = intel_crtc->unpin_work; |
|
Line -... | Line 6123... | ||
- | 6123 | intel_crtc->unpin_work = NULL; |
|
Line -... | Line 6124... | ||
- | 6124 | spin_unlock_irqrestore(&dev->event_lock, flags); |
|
- | 6125 | ||
Line -... | Line 6196... | ||
- | 6196 | ||
- | 6197 | ||
- | 6198 | ||
- | 6199 | ||
- | 6200 | ||
- | 6201 | static void intel_sanitize_modesetting(struct drm_device *dev, |
|
- | 6202 | int pipe, int plane) |
|
- | 6203 | { |
|
Line -... | Line 6204... | ||
- | 6204 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6205 | u32 reg, val; |
|
- | 6206 | ||
- | 6207 | if (HAS_PCH_SPLIT(dev)) |
|
- | 6208 | return; |
|
- | 6209 | ||
- | 6210 | /* Who knows what state these registers were left in by the BIOS or |
|
- | 6211 | * grub? |
|
- | 6212 | * |
|
- | 6213 | * If we leave the registers in a conflicting state (e.g. with the |
|
Line -... | Line 6214... | ||
- | 6214 | * display plane reading from the other pipe than the one we intend |
|
- | 6215 | * to use) then when we attempt to teardown the active mode, we will |
|
Line -... | Line 6216... | ||
- | 6216 | * not disable the pipes and planes in the correct order -- leaving |
|
- | 6217 | * a plane reading from a disabled pipe and possibly leading to |
|
- | 6218 | * undefined behaviour. |
|
- | 6219 | */ |
|
Line -... | Line 6220... | ||
- | 6220 | ||
- | 6221 | reg = DSPCNTR(plane); |
|
Line -... | Line 6222... | ||
- | 6222 | val = I915_READ(reg); |
|
- | 6223 | ||
- | 6224 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
|
- | 6225 | return; |
|
Line -... | Line 6226... | ||
- | 6226 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) |
|
- | 6227 | return; |
|
- | 6228 | ||
- | 6229 | /* This display plane is active and attached to the other CPU pipe. */ |
|
Line -... | Line 6230... | ||
- | 6230 | pipe = !pipe; |
|
- | 6231 | ||
- | 6232 | /* Disable the plane and wait for it to stop reading from the pipe. */ |
|
- | 6233 | intel_disable_plane(dev_priv, plane, pipe); |
|
Line -... | Line 6234... | ||
- | 6234 | intel_disable_pipe(dev_priv, pipe); |
|
- | 6235 | } |
|
- | 6236 | ||
- | 6237 | static void intel_crtc_reset(struct drm_crtc *crtc) |
|
- | 6238 | { |
|
Line -... | Line 6239... | ||
- | 6239 | struct drm_device *dev = crtc->dev; |
|
- | 6240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 6241 | ||
- | 6242 | /* Reset flags back to the 'unknown' status so that they |
|
- | 6243 | * will be correctly set on the initial modeset. |
|
- | 6244 | */ |
|
- | 6245 | intel_crtc->dpms_mode = -1; |
|
- | 6246 | ||
- | 6247 | /* We need to fix up any BIOS configuration that conflicts with |
|
Line -... | Line 6248... | ||
- | 6248 | * our expectations. |
|
- | 6249 | */ |
|
- | 6250 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); |
|
- | 6251 | } |
|
- | 6252 | ||
- | 6253 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
|
- | 6254 | .dpms = intel_crtc_dpms, |
|
- | 6255 | .mode_fixup = intel_crtc_mode_fixup, |
|
- | 6256 | .mode_set = intel_crtc_mode_set, |
|
Line -... | Line 6257... | ||
- | 6257 | .mode_set_base = intel_pipe_set_base, |
|
- | 6258 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
|
- | 6259 | .load_lut = intel_crtc_load_lut, |
|
- | 6260 | .disable = intel_crtc_disable, |
|
- | 6261 | }; |
|
Line -... | Line 6262... | ||
- | 6262 | ||
Line -... | Line 6263... | ||
- | 6263 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
|
- | 6264 | .reset = intel_crtc_reset, |
|
- | 6265 | // .cursor_set = intel_crtc_cursor_set, |
|
Line -... | Line 6266... | ||
- | 6266 | // .cursor_move = intel_crtc_cursor_move, |
|
Line -... | Line 6267... | ||
- | 6267 | .gamma_set = intel_crtc_gamma_set, |
|
- | 6268 | .set_config = drm_crtc_helper_set_config, |
|
- | 6269 | .destroy = intel_crtc_destroy, |
|
- | 6270 | // .page_flip = intel_crtc_page_flip, |
|
- | 6271 | }; |
|
- | 6272 | ||
- | 6273 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
|
- | 6274 | { |
|
- | 6275 | drm_i915_private_t *dev_priv = dev->dev_private; |
|
- | 6276 | struct intel_crtc *intel_crtc; |
|
- | 6277 | int i; |
|
- | 6278 | ||
- | 6279 | ENTER(); |
|
- | 6280 | ||
- | 6281 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
|
- | 6282 | if (intel_crtc == NULL) |
|
- | 6283 | return; |
|
- | 6284 | ||
- | 6285 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
|
- | 6286 | ||
- | 6287 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
|
- | 6288 | for (i = 0; i < 256; i++) { |
|
- | 6289 | intel_crtc->lut_r[i] = i; |
|
Line -... | Line 6290... | ||
- | 6290 | intel_crtc->lut_g[i] = i; |
|
- | 6291 | intel_crtc->lut_b[i] = i; |
|
- | 6292 | } |
|
- | 6293 | ||
- | 6294 | /* Swap pipes & planes for FBC on pre-965 */ |
|
- | 6295 | intel_crtc->pipe = pipe; |
|
- | 6296 | intel_crtc->plane = pipe; |
|
Line -... | Line 6297... | ||
- | 6297 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
|
Line -... | Line 6298... | ||
- | 6298 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
|
Line -... | Line 6299... | ||
- | 6299 | intel_crtc->plane = !pipe; |
|
Line -... | Line 6300... | ||
- | 6300 | } |
|
- | 6301 | ||
- | 6302 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
|
Line -... | Line 6303... | ||
- | 6303 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
|
- | 6304 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
|
- | 6305 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
|
- | 6306 | ||
- | 6307 | intel_crtc_reset(&intel_crtc->base); |
|
Line -... | Line 6308... | ||
- | 6308 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
|
- | 6309 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
|
- | 6310 | ||
- | 6311 | if (HAS_PCH_SPLIT(dev)) { |
|
- | 6312 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
|
Line -... | Line 6313... | ||
- | 6313 | intel_helper_funcs.commit = ironlake_crtc_commit; |
|
- | 6314 | } else { |
|
Line -... | Line 6315... | ||
- | 6315 | intel_helper_funcs.prepare = i9xx_crtc_prepare; |
|
- | 6316 | intel_helper_funcs.commit = i9xx_crtc_commit; |
|
- | 6317 | } |
|
Line -... | Line 6318... | ||
- | 6318 | ||
- | 6319 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
|
Line -... | Line 6320... | ||
- | 6320 | ||
- | 6321 | intel_crtc->busy = false; |
|
Line -... | Line 6322... | ||
- | 6322 | ||
- | 6323 | LEAVE(); |
|
- | 6324 | ||
Line -... | Line 6325... | ||
- | 6325 | // setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
|
- | 6326 | // (unsigned long)intel_crtc); |
|
Line -... | Line 6327... | ||
- | 6327 | } |
|
- | 6328 | ||
- | 6329 | ||
- | 6330 | ||
- | 6331 | ||
- | 6332 | ||
Line -... | Line 6333... | ||
- | 6333 | ||
- | 6334 | ||
- | 6335 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
|
- | 6336 | { |
|
- | 6337 | struct intel_encoder *encoder; |
|
- | 6338 | int index_mask = 0; |
|
Line -... | Line 6339... | ||
- | 6339 | int entry = 0; |
|
- | 6340 | ||
Line -... | Line 6341... | ||
- | 6341 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
|
- | 6342 | if (type_mask & encoder->clone_mask) |
|
Line -... | Line 6343... | ||
- | 6343 | index_mask |= (1 << entry); |
|
- | 6344 | entry++; |
|
- | 6345 | } |
|
Line -... | Line 6346... | ||
- | 6346 | ||
Line -... | Line 6347... | ||
- | 6347 | return index_mask; |
|
- | 6348 | } |
|
Line -... | Line 6349... | ||
- | 6349 | ||
- | 6350 | static bool has_edp_a(struct drm_device *dev) |
|
- | 6351 | { |
|
- | 6352 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6353 | ||
- | 6354 | if (!IS_MOBILE(dev)) |
|
- | 6355 | return false; |
|
- | 6356 | ||
Line -... | Line 6357... | ||
- | 6357 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
|
- | 6358 | return false; |
|
Line -... | Line 6359... | ||
- | 6359 | ||
- | 6360 | if (IS_GEN5(dev) && |
|
Line -... | Line 6361... | ||
- | 6361 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
|
- | 6362 | return false; |
|
Line -... | Line 6363... | ||
- | 6363 | ||
- | 6364 | return true; |
|
Line -... | Line 6365... | ||
- | 6365 | } |
|
- | 6366 | ||
Line -... | Line 6367... | ||
- | 6367 | static void intel_setup_outputs(struct drm_device *dev) |
|
- | 6368 | { |
|
- | 6369 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6370 | struct intel_encoder *encoder; |
|
- | 6371 | bool dpd_is_edp = false; |
|
- | 6372 | bool has_lvds = false; |
|
- | 6373 | ||
Line -... | Line 6374... | ||
- | 6374 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
|
- | 6375 | has_lvds = intel_lvds_init(dev); |
|
- | 6376 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
|
- | 6377 | /* disable the panel fitter on everything but LVDS */ |
|
- | 6378 | I915_WRITE(PFIT_CONTROL, 0); |
|
Line -... | Line 6379... | ||
- | 6379 | } |
|
Line -... | Line 6380... | ||
- | 6380 | ||
- | 6381 | if (HAS_PCH_SPLIT(dev)) { |
|
- | 6382 | dpd_is_edp = intel_dpd_is_edp(dev); |
|
- | 6383 | ||
Line -... | Line 6384... | ||
- | 6384 | if (has_edp_a(dev)) |
|
Line -... | Line 6385... | ||
- | 6385 | intel_dp_init(dev, DP_A); |
|
- | 6386 | ||
- | 6387 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
|
- | 6388 | intel_dp_init(dev, PCH_DP_D); |
|
- | 6389 | } |
|
- | 6390 | ||
- | 6391 | intel_crt_init(dev); |
|
- | 6392 | ||
- | 6393 | if (HAS_PCH_SPLIT(dev)) { |
|
Line -... | Line 6394... | ||
- | 6394 | int found; |
|
- | 6395 | ||
- | 6396 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
|
- | 6397 | /* PCH SDVOB multiplex with HDMIB */ |
|
- | 6398 | found = intel_sdvo_init(dev, PCH_SDVOB); |
|
- | 6399 | if (!found) |
|
- | 6400 | intel_hdmi_init(dev, HDMIB); |
|
Line -... | Line 6401... | ||
- | 6401 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
|
- | 6402 | intel_dp_init(dev, PCH_DP_B); |
|
Line -... | Line 6403... | ||
- | 6403 | } |
|
- | 6404 | ||
- | 6405 | if (I915_READ(HDMIC) & PORT_DETECTED) |
|
- | 6406 | intel_hdmi_init(dev, HDMIC); |
|
- | 6407 | ||
Line -... | Line 6408... | ||
- | 6408 | if (I915_READ(HDMID) & PORT_DETECTED) |
|
- | 6409 | intel_hdmi_init(dev, HDMID); |
|
- | 6410 | ||
Line 5732... | Line 6411... | ||
5732 | 6411 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
|
Line -... | Line 6508... | ||
- | 6508 | ||
- | 6509 | ||
- | 6510 | ||
- | 6511 | ||
- | 6512 | ||
- | 6513 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
|
- | 6514 | { |
|
- | 6515 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6516 | u16 rgvswctl; |
|
- | 6517 | ||
- | 6518 | rgvswctl = I915_READ16(MEMSWCTL); |
|
- | 6519 | if (rgvswctl & MEMCTL_CMD_STS) { |
|
- | 6520 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
|
- | 6521 | return false; /* still busy with another command */ |
|
- | 6522 | } |
|
- | 6523 | ||
- | 6524 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
|
- | 6525 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
|
- | 6526 | I915_WRITE16(MEMSWCTL, rgvswctl); |
|
- | 6527 | POSTING_READ16(MEMSWCTL); |
|
- | 6528 | ||
- | 6529 | rgvswctl |= MEMCTL_CMD_STS; |
|
- | 6530 | I915_WRITE16(MEMSWCTL, rgvswctl); |
|
- | 6531 | ||
- | 6532 | return true; |
|
- | 6533 | } |
|
- | 6534 | ||
- | 6535 | void ironlake_enable_drps(struct drm_device *dev) |
|
- | 6536 | { |
|
- | 6537 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6538 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
|
- | 6539 | u8 fmax, fmin, fstart, vstart; |
|
- | 6540 | ||
- | 6541 | /* Enable temp reporting */ |
|
- | 6542 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
|
- | 6543 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
|
- | 6544 | ||
- | 6545 | /* 100ms RC evaluation intervals */ |
|
- | 6546 | I915_WRITE(RCUPEI, 100000); |
|
- | 6547 | I915_WRITE(RCDNEI, 100000); |
|
- | 6548 | ||
- | 6549 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
|
- | 6550 | I915_WRITE(RCBMAXAVG, 90000); |
|
- | 6551 | I915_WRITE(RCBMINAVG, 80000); |
|
- | 6552 | ||
- | 6553 | I915_WRITE(MEMIHYST, 1); |
|
- | 6554 | ||
Line -... | Line 6555... | ||
- | 6555 | /* Set up min, max, and cur for interrupt handling */ |
|
- | 6556 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
|
Line -... | Line 6557... | ||
- | 6557 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
|
- | 6558 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
|
Line -... | Line 6559... | ||
- | 6559 | MEMMODE_FSTART_SHIFT; |
|
- | 6560 | ||
- | 6561 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
|
Line -... | Line 6562... | ||
- | 6562 | PXVFREQ_PX_SHIFT; |
|
- | 6563 | ||
Line -... | Line 6564... | ||
- | 6564 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
|
- | 6565 | dev_priv->fstart = fstart; |
|
- | 6566 | ||
- | 6567 | dev_priv->max_delay = fstart; |
|
- | 6568 | dev_priv->min_delay = fmin; |
|
Line -... | Line 6569... | ||
- | 6569 | dev_priv->cur_delay = fstart; |
|
- | 6570 | ||
Line -... | Line 6571... | ||
- | 6571 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
|
- | 6572 | fmax, fmin, fstart); |
|
Line -... | Line 6573... | ||
- | 6573 | ||
- | 6574 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
|
- | 6575 | ||
Line -... | Line 6576... | ||
- | 6576 | /* |
|
Line -... | Line 6577... | ||
- | 6577 | * Interrupts will be enabled in ironlake_irq_postinstall |
|
- | 6578 | */ |
|
- | 6579 | ||
- | 6580 | I915_WRITE(VIDSTART, vstart); |
|
- | 6581 | POSTING_READ(VIDSTART); |
|
- | 6582 | ||
Line -... | Line 6608... | ||
- | 6608 | ||
- | 6609 | ||
- | 6610 | ||
- | 6611 | ||
- | 6612 | ||
- | 6613 | static unsigned long intel_pxfreq(u32 vidfreq) |
|
Line -... | Line 6614... | ||
- | 6614 | { |
|
- | 6615 | unsigned long freq; |
|
Line -... | Line 6616... | ||
- | 6616 | int div = (vidfreq & 0x3f0000) >> 16; |
|
Line -... | Line 6617... | ||
- | 6617 | int post = (vidfreq & 0x3000) >> 12; |
|
- | 6618 | int pre = (vidfreq & 0x7); |
|
Line -... | Line 6619... | ||
- | 6619 | ||
- | 6620 | if (!pre) |
|
- | 6621 | return 0; |
|
- | 6622 | ||
- | 6623 | freq = ((div * 133333) / ((1< |
|
- | 6624 | ||
Line -... | Line 6625... | ||
- | 6625 | return freq; |
|
- | 6626 | } |
|
- | 6627 | ||
- | 6628 | void intel_init_emon(struct drm_device *dev) |
|
- | 6629 | { |
|
- | 6630 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6631 | u32 lcfuse; |
|
- | 6632 | u8 pxw[16]; |
|
- | 6633 | int i; |
|
- | 6634 | ||
- | 6635 | /* Disable to program */ |
|
- | 6636 | I915_WRITE(ECR, 0); |
|
- | 6637 | POSTING_READ(ECR); |
|
- | 6638 | ||
- | 6639 | /* Program energy weights for various events */ |
|
- | 6640 | I915_WRITE(SDEW, 0x15040d00); |
|
- | 6641 | I915_WRITE(CSIEW0, 0x007f0000); |
|
- | 6642 | I915_WRITE(CSIEW1, 0x1e220004); |
|
- | 6643 | I915_WRITE(CSIEW2, 0x04000004); |
|
- | 6644 | ||
- | 6645 | for (i = 0; i < 5; i++) |
|
- | 6646 | I915_WRITE(PEW + (i * 4), 0); |
|
- | 6647 | for (i = 0; i < 3; i++) |
|
- | 6648 | I915_WRITE(DEW + (i * 4), 0); |
|
- | 6649 | ||
- | 6650 | /* Program P-state weights to account for frequency power adjustment */ |
|
- | 6651 | for (i = 0; i < 16; i++) { |
|
- | 6652 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
|
- | 6653 | unsigned long freq = intel_pxfreq(pxvidfreq); |
|
- | 6654 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
|
- | 6655 | PXVFREQ_PX_SHIFT; |
|
- | 6656 | unsigned long val; |
|
- | 6657 | ||
- | 6658 | val = vid * vid; |
|
Line -... | Line 6659... | ||
- | 6659 | val *= (freq / 1000); |
|
- | 6660 | val *= 255; |
|
- | 6661 | val /= (127*127*900); |
|
- | 6662 | if (val > 0xff) |
|
- | 6663 | DRM_ERROR("bad pxval: %ld\n", val); |
|
Line -... | Line 6664... | ||
- | 6664 | pxw[i] = val; |
|
- | 6665 | } |
|
- | 6666 | /* Render standby states get 0 weight */ |
|
- | 6667 | pxw[14] = 0; |
|
- | 6668 | pxw[15] = 0; |
|
- | 6669 | ||
- | 6670 | for (i = 0; i < 4; i++) { |
|
- | 6671 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
|
- | 6672 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
|
- | 6673 | I915_WRITE(PXW + (i * 4), val); |
|
- | 6674 | } |
|
Line -... | Line 6675... | ||
- | 6675 | ||
- | 6676 | /* Adjust magic regs to magic values (more experimental results) */ |
|
Line -... | Line 6677... | ||
- | 6677 | I915_WRITE(OGW0, 0); |
|
- | 6678 | I915_WRITE(OGW1, 0); |
|
Line -... | Line 6679... | ||
- | 6679 | I915_WRITE(EG0, 0x00007f00); |
|
Line -... | Line 6680... | ||
- | 6680 | I915_WRITE(EG1, 0x0000000e); |
|
- | 6681 | I915_WRITE(EG2, 0x000e0000); |
|
Line -... | Line 6682... | ||
- | 6682 | I915_WRITE(EG3, 0x68000300); |
|
- | 6683 | I915_WRITE(EG4, 0x42000000); |
|
- | 6684 | I915_WRITE(EG5, 0x00140031); |
|
- | 6685 | I915_WRITE(EG6, 0); |
|
- | 6686 | I915_WRITE(EG7, 0); |
|
- | 6687 | ||
- | 6688 | for (i = 0; i < 8; i++) |
|
Line -... | Line 6689... | ||
- | 6689 | I915_WRITE(PXWL + (i * 4), 0); |
|
- | 6690 | ||
- | 6691 | /* Enable PMON + select events */ |
|
- | 6692 | I915_WRITE(ECR, 0x80000019); |
|
- | 6693 | ||
- | 6694 | lcfuse = I915_READ(LCFUSE02); |
|
- | 6695 | ||
- | 6696 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
|
- | 6697 | } |
|
Line -... | Line 6698... | ||
- | 6698 | ||
- | 6699 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
|
Line -... | Line 6700... | ||
- | 6700 | { |
|
- | 6701 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
|
- | 6702 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
|
- | 6703 | u32 pcu_mbox, rc6_mask = 0; |
|
- | 6704 | int cur_freq, min_freq, max_freq; |
|
- | 6705 | int i; |
|
- | 6706 | ||
- | 6707 | /* Here begins a magic sequence of register writes to enable |
|
- | 6708 | * auto-downclocking. |
|
- | 6709 | * |
|
- | 6710 | * Perhaps there might be some value in exposing these to |
|
- | 6711 | * userspace... |
|
- | 6712 | */ |
|
- | 6713 | I915_WRITE(GEN6_RC_STATE, 0); |
|
- | 6714 | mutex_lock(&dev_priv->dev->struct_mutex); |
|
- | 6715 | gen6_gt_force_wake_get(dev_priv); |
|
- | 6716 | ||
- | 6717 | /* disable the counters and set deterministic thresholds */ |
|
- | 6718 | I915_WRITE(GEN6_RC_CONTROL, 0); |
|
- | 6719 | ||
- | 6720 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
|
- | 6721 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
|
- | 6722 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
|
- | 6723 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
|
- | 6724 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
|
- | 6725 | ||
- | 6726 | for (i = 0; i < I915_NUM_RINGS; i++) |
|
- | 6727 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); |
|
- | 6728 | ||
- | 6729 | I915_WRITE(GEN6_RC_SLEEP, 0); |
|
- | 6730 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
|
- | 6731 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
|
- | 6732 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
|
- | 6733 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
|
- | 6734 | ||
- | 6735 | if (i915_enable_rc6) |
|
- | 6736 | rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | |
|
- | 6737 | GEN6_RC_CTL_RC6_ENABLE; |
|
- | 6738 | ||
- | 6739 | I915_WRITE(GEN6_RC_CONTROL, |
|
- | 6740 | rc6_mask | |
|
- | 6741 | GEN6_RC_CTL_EI_MODE(1) | |
|
- | 6742 | GEN6_RC_CTL_HW_ENABLE); |
|
- | 6743 | ||
- | 6744 | I915_WRITE(GEN6_RPNSWREQ, |
|
- | 6745 | GEN6_FREQUENCY(10) | |
|
- | 6746 | GEN6_OFFSET(0) | |
|
- | 6747 | GEN6_AGGRESSIVE_TURBO); |
|
- | 6748 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
|
- | 6749 | GEN6_FREQUENCY(12)); |
|
- | 6750 | ||
- | 6751 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
|
- | 6752 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
|
- | 6753 | 18 << 24 | |
|
- | 6754 | 6 << 16); |
|
- | 6755 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
|
- | 6756 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); |
|
- | 6757 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
|
- | 6758 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
|
- | 6759 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
|
- | 6760 | I915_WRITE(GEN6_RP_CONTROL, |
|
- | 6761 | GEN6_RP_MEDIA_TURBO | |
|
- | 6762 | GEN6_RP_USE_NORMAL_FREQ | |
|
- | 6763 | GEN6_RP_MEDIA_IS_GFX | |
|
- | 6764 | GEN6_RP_ENABLE | |
|
- | 6765 | GEN6_RP_UP_BUSY_AVG | |
|
- | 6766 | GEN6_RP_DOWN_IDLE_CONT); |
|
- | 6767 | ||
- | 6768 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 6769 | 500)) |
|
- | 6770 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
|
- | 6771 | ||
- | 6772 | I915_WRITE(GEN6_PCODE_DATA, 0); |
|
- | 6773 | I915_WRITE(GEN6_PCODE_MAILBOX, |
|
- | 6774 | GEN6_PCODE_READY | |
|
- | 6775 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
|
- | 6776 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 6777 | 500)) |
|
- | 6778 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
|
- | 6779 | ||
- | 6780 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
|
- | 6781 | max_freq = rp_state_cap & 0xff; |
|
- | 6782 | cur_freq = (gt_perf_status & 0xff00) >> 8; |
|
- | 6783 | ||
- | 6784 | /* Check for overclock support */ |
|
- | 6785 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 6786 | 500)) |
|
- | 6787 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
|
- | 6788 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); |
|
- | 6789 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); |
|
- | 6790 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
|
- | 6791 | 500)) |
|
- | 6792 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
|
- | 6793 | if (pcu_mbox & (1<<31)) { /* OC supported */ |
|
- | 6794 | max_freq = pcu_mbox & 0xff; |
|
- | 6795 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
|
- | 6796 | } |
|
- | 6797 | ||
Line -... | Line 6798... | ||
- | 6798 | /* In units of 100MHz */ |
|
- | 6799 | dev_priv->max_delay = max_freq; |
|
- | 6800 | dev_priv->min_delay = min_freq; |
|
Line -... | Line 6801... | ||
- | 6801 | dev_priv->cur_delay = cur_freq; |
|
- | 6802 | ||
- | 6803 | /* requires MSI enabled */ |
|
- | 6804 | I915_WRITE(GEN6_PMIER, |
|
- | 6805 | GEN6_PM_MBOX_EVENT | |
|
Line -... | Line 6806... | ||
- | 6806 | GEN6_PM_THERMAL_EVENT | |
|
- | 6807 | GEN6_PM_RP_DOWN_TIMEOUT | |
|
- | 6808 | GEN6_PM_RP_UP_THRESHOLD | |
|
- | 6809 | GEN6_PM_RP_DOWN_THRESHOLD | |
|
- | 6810 | GEN6_PM_RP_UP_EI_EXPIRED | |
|
- | 6811 | GEN6_PM_RP_DOWN_EI_EXPIRED); |
|
- | 6812 | // spin_lock_irq(&dev_priv->rps_lock); |
|
Line -... | Line 6813... | ||
- | 6813 | // WARN_ON(dev_priv->pm_iir != 0); |
|
- | 6814 | I915_WRITE(GEN6_PMIMR, 0); |
|
Line -... | Line 6815... | ||
- | 6815 | // spin_unlock_irq(&dev_priv->rps_lock); |
|
Line -... | Line 6816... | ||
- | 6816 | /* enable all PM interrupts */ |
|
- | 6817 | I915_WRITE(GEN6_PMINTRMSK, 0); |
|
- | 6818 | ||
- | 6819 | gen6_gt_force_wake_put(dev_priv); |
|
- | 6820 | mutex_unlock(&dev_priv->dev->struct_mutex); |
|
- | 6821 | } |
|
- | 6822 | ||
- | 6823 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
|
Line -... | Line 6824... | ||
- | 6824 | { |
|
- | 6825 | int min_freq = 15; |
|
- | 6826 | int gpu_freq, ia_freq, max_ia_freq; |
|
- | 6827 | int scaling_factor = 180; |
|
- | 6828 | ||
- | 6829 | // max_ia_freq = cpufreq_quick_get_max(0); |
|
- | 6830 | /* |
|
- | 6831 | * Default to measured freq if none found, PCU will ensure we don't go |
|
- | 6832 | * over |
|
Line -... | Line 6833... | ||
- | 6833 | */ |
|
- | 6834 | // if (!max_ia_freq) |
|
- | 6835 | max_ia_freq = 3000000; //tsc_khz; |
|
- | 6836 | ||
- | 6837 | /* Convert from kHz to MHz */ |
|
- | 6838 | max_ia_freq /= 1000; |
|
- | 6839 | ||
- | 6840 | mutex_lock(&dev_priv->dev->struct_mutex); |
|
- | 6841 | ||
- | 6842 | /* |
|
- | 6843 | * For each potential GPU frequency, load a ring frequency we'd like |
|
Line -... | Line 6844... | ||
- | 6844 | * to use for memory access. We do this by specifying the IA frequency |
|
- | 6845 | * the PCU should use as a reference to determine the ring frequency. |
|
Line 5854... | Line 6846... | ||
5854 | 6846 | */ |
|
5855 | 6847 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; |
|
5856 | 6848 | gpu_freq--) { |
|
5857 | 6849 | int diff = dev_priv->max_delay - gpu_freq; |
|
Line 6112... | Line 7104... | ||
6112 | } |
7104 | } |
Line -... | Line 7105... | ||
- | 7105 | ||
- | 7106 | ||
- | 7107 | ||
- | 7108 | ||
- | 7109 | ||
- | 7110 | void intel_init_clock_gating(struct drm_device *dev) |
|
- | 7111 | { |
|
- | 7112 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7113 | ||
- | 7114 | dev_priv->display.init_clock_gating(dev); |
|
- | 7115 | ||
6113 | 7116 | if (dev_priv->display.init_pch_clock_gating) |
|
6114 | 7117 | dev_priv->display.init_pch_clock_gating(dev); |
|
6115 | 7118 | } |
|
6116 | 7119 | ||
Line 6358... | Line 7361... | ||
6358 | q->subsystem_device == PCI_ANY_ID)) |
7361 | q->subsystem_device == PCI_ANY_ID)) |
6359 | q->hook(dev); |
7362 | q->hook(dev); |
6360 | } |
7363 | } |
6361 | } |
7364 | } |
Line -... | Line 7365... | ||
- | 7365 | ||
- | 7366 | /* Disable the VGA plane that we never use */ |
|
- | 7367 | static void i915_disable_vga(struct drm_device *dev) |
|
- | 7368 | { |
|
- | 7369 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 7370 | u8 sr1; |
|
- | 7371 | u32 vga_reg; |
|
- | 7372 | ||
- | 7373 | if (HAS_PCH_SPLIT(dev)) |
|
- | 7374 | vga_reg = CPU_VGACNTRL; |
|
- | 7375 | else |
|
- | 7376 | vga_reg = VGACNTRL; |
|
- | 7377 | ||
- | 7378 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
|
- | 7379 | out8(VGA_SR_INDEX, 1); |
|
- | 7380 | sr1 = in8(VGA_SR_DATA); |
|
- | 7381 | out8(VGA_SR_DATA,sr1 | 1<<5); |
|
- | 7382 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
|
- | 7383 | udelay(300); |
|
- | 7384 | ||
- | 7385 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
|
- | 7386 | POSTING_READ(vga_reg); |
|
Line 6362... | Line 7387... | ||
6362 | 7387 | } |
|
6363 | 7388 | ||
6364 | void intel_modeset_init(struct drm_device *dev) |
7389 | void intel_modeset_init(struct drm_device *dev) |
6365 | { |
7390 | { |
Line 6391... | Line 7416... | ||
6391 | dev->mode_config.fb_base = get_bus_addr(); |
7416 | dev->mode_config.fb_base = get_bus_addr(); |
Line 6392... | Line 7417... | ||
6392 | 7417 | ||
6393 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7418 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Line 6394... | Line -... | ||
6394 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
- | |
6395 | - | ||
6396 | #if 0 |
7419 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
6397 | 7420 | ||
6398 | for (i = 0; i < dev_priv->num_pipe; i++) { |
7421 | for (i = 0; i < dev_priv->num_pipe; i++) { |
Line 6399... | Line 7422... | ||
6399 | intel_crtc_init(dev, i); |
7422 | intel_crtc_init(dev, i); |
Line 6413... | Line 7436... | ||
6413 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
7436 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
6414 | gen6_enable_rps(dev_priv); |
7437 | gen6_enable_rps(dev_priv); |
6415 | gen6_update_ring_freq(dev_priv); |
7438 | gen6_update_ring_freq(dev_priv); |
6416 | } |
7439 | } |
Line 6417... | Line -... | ||
6417 | - | ||
6418 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
- | |
6419 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
- | |
6420 | (unsigned long)dev); |
7440 | |
- | 7441 | } |
|
Line -... | Line 7442... | ||
- | 7442 | ||
- | 7443 | ||
- | 7444 | /* |
|
- | 7445 | * Return which encoder is currently attached for connector. |
|
- | 7446 | */ |
|
- | 7447 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
|
- | 7448 | { |
|
- | 7449 | return &intel_attached_encoder(connector)->base; |
|
- | 7450 | } |
|
- | 7451 | ||
- | 7452 | void intel_connector_attach_encoder(struct intel_connector *connector, |
|
- | 7453 | struct intel_encoder *encoder) |
|
- | 7454 | { |
|
- | 7455 | connector->encoder = encoder; |
|
6421 | #endif |
7456 | drm_mode_connector_attach_encoder(&connector->base, |