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1 | /* |
1 | /* |
2 | * Copyright © 2012 Intel Corporation |
2 | * Copyright © 2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eugeni Dodonov |
24 | * Eugeni Dodonov |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include "i915_drv.h" |
28 | #include "i915_drv.h" |
29 | #include "intel_drv.h" |
29 | #include "intel_drv.h" |
30 | 30 | ||
31 | struct ddi_buf_trans { |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ |
32 | u32 trans1; /* balance leg enable, de-emph level */ |
33 | u32 trans2; /* vref sel, vswing */ |
33 | u32 trans2; /* vref sel, vswing */ |
34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
35 | }; |
35 | }; |
36 | 36 | ||
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
38 | * them for both DP and FDI transports, allowing those ports to |
38 | * them for both DP and FDI transports, allowing those ports to |
39 | * automatically adapt to HDMI connections as well |
39 | * automatically adapt to HDMI connections as well |
40 | */ |
40 | */ |
41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
42 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
42 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
43 | { 0x00D75FFF, 0x0005000A, 0x0 }, |
43 | { 0x00D75FFF, 0x0005000A, 0x0 }, |
44 | { 0x00C30FFF, 0x00040006, 0x0 }, |
44 | { 0x00C30FFF, 0x00040006, 0x0 }, |
45 | { 0x80AAAFFF, 0x000B0000, 0x0 }, |
45 | { 0x80AAAFFF, 0x000B0000, 0x0 }, |
46 | { 0x00FFFFFF, 0x0005000A, 0x0 }, |
46 | { 0x00FFFFFF, 0x0005000A, 0x0 }, |
47 | { 0x00D75FFF, 0x000C0004, 0x0 }, |
47 | { 0x00D75FFF, 0x000C0004, 0x0 }, |
48 | { 0x80C30FFF, 0x000B0000, 0x0 }, |
48 | { 0x80C30FFF, 0x000B0000, 0x0 }, |
49 | { 0x00FFFFFF, 0x00040006, 0x0 }, |
49 | { 0x00FFFFFF, 0x00040006, 0x0 }, |
50 | { 0x80D75FFF, 0x000B0000, 0x0 }, |
50 | { 0x80D75FFF, 0x000B0000, 0x0 }, |
51 | }; |
51 | }; |
52 | 52 | ||
53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
54 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
54 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
55 | { 0x00D75FFF, 0x000F000A, 0x0 }, |
55 | { 0x00D75FFF, 0x000F000A, 0x0 }, |
56 | { 0x00C30FFF, 0x00060006, 0x0 }, |
56 | { 0x00C30FFF, 0x00060006, 0x0 }, |
57 | { 0x00AAAFFF, 0x001E0000, 0x0 }, |
57 | { 0x00AAAFFF, 0x001E0000, 0x0 }, |
58 | { 0x00FFFFFF, 0x000F000A, 0x0 }, |
58 | { 0x00FFFFFF, 0x000F000A, 0x0 }, |
59 | { 0x00D75FFF, 0x00160004, 0x0 }, |
59 | { 0x00D75FFF, 0x00160004, 0x0 }, |
60 | { 0x00C30FFF, 0x001E0000, 0x0 }, |
60 | { 0x00C30FFF, 0x001E0000, 0x0 }, |
61 | { 0x00FFFFFF, 0x00060006, 0x0 }, |
61 | { 0x00FFFFFF, 0x00060006, 0x0 }, |
62 | { 0x00D75FFF, 0x001E0000, 0x0 }, |
62 | { 0x00D75FFF, 0x001E0000, 0x0 }, |
63 | }; |
63 | }; |
64 | 64 | ||
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
66 | /* Idx NT mV d T mV d db */ |
66 | /* Idx NT mV d T mV d db */ |
67 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
67 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
68 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ |
68 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ |
69 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ |
69 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ |
70 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ |
70 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ |
71 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ |
71 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ |
72 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ |
72 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ |
73 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ |
73 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ |
74 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ |
74 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ |
75 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ |
75 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ |
76 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ |
76 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ |
77 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ |
77 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ |
78 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ |
78 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ |
79 | }; |
79 | }; |
80 | 80 | ||
81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
82 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
82 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
83 | { 0x00EBAFFF, 0x00020011, 0x0 }, |
83 | { 0x00EBAFFF, 0x00020011, 0x0 }, |
84 | { 0x00C71FFF, 0x0006000F, 0x0 }, |
84 | { 0x00C71FFF, 0x0006000F, 0x0 }, |
85 | { 0x00AAAFFF, 0x000E000A, 0x0 }, |
85 | { 0x00AAAFFF, 0x000E000A, 0x0 }, |
86 | { 0x00FFFFFF, 0x00020011, 0x0 }, |
86 | { 0x00FFFFFF, 0x00020011, 0x0 }, |
87 | { 0x00DB6FFF, 0x0005000F, 0x0 }, |
87 | { 0x00DB6FFF, 0x0005000F, 0x0 }, |
88 | { 0x00BEEFFF, 0x000A000C, 0x0 }, |
88 | { 0x00BEEFFF, 0x000A000C, 0x0 }, |
89 | { 0x00FFFFFF, 0x0005000F, 0x0 }, |
89 | { 0x00FFFFFF, 0x0005000F, 0x0 }, |
90 | { 0x00DB6FFF, 0x000A000C, 0x0 }, |
90 | { 0x00DB6FFF, 0x000A000C, 0x0 }, |
91 | }; |
91 | }; |
92 | 92 | ||
93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
94 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
94 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
95 | { 0x00D75FFF, 0x000E000A, 0x0 }, |
95 | { 0x00D75FFF, 0x000E000A, 0x0 }, |
96 | { 0x00BEFFFF, 0x00140006, 0x0 }, |
96 | { 0x00BEFFFF, 0x00140006, 0x0 }, |
97 | { 0x80B2CFFF, 0x001B0002, 0x0 }, |
97 | { 0x80B2CFFF, 0x001B0002, 0x0 }, |
98 | { 0x00FFFFFF, 0x000E000A, 0x0 }, |
98 | { 0x00FFFFFF, 0x000E000A, 0x0 }, |
99 | { 0x00DB6FFF, 0x00160005, 0x0 }, |
99 | { 0x00DB6FFF, 0x00160005, 0x0 }, |
100 | { 0x80C71FFF, 0x001A0002, 0x0 }, |
100 | { 0x80C71FFF, 0x001A0002, 0x0 }, |
101 | { 0x00F7DFFF, 0x00180004, 0x0 }, |
101 | { 0x00F7DFFF, 0x00180004, 0x0 }, |
102 | { 0x80D75FFF, 0x001B0002, 0x0 }, |
102 | { 0x80D75FFF, 0x001B0002, 0x0 }, |
103 | }; |
103 | }; |
104 | 104 | ||
105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
106 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
106 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
107 | { 0x00D75FFF, 0x0004000A, 0x0 }, |
107 | { 0x00D75FFF, 0x0004000A, 0x0 }, |
108 | { 0x00C30FFF, 0x00070006, 0x0 }, |
108 | { 0x00C30FFF, 0x00070006, 0x0 }, |
109 | { 0x00AAAFFF, 0x000C0000, 0x0 }, |
109 | { 0x00AAAFFF, 0x000C0000, 0x0 }, |
110 | { 0x00FFFFFF, 0x0004000A, 0x0 }, |
110 | { 0x00FFFFFF, 0x0004000A, 0x0 }, |
111 | { 0x00D75FFF, 0x00090004, 0x0 }, |
111 | { 0x00D75FFF, 0x00090004, 0x0 }, |
112 | { 0x00C30FFF, 0x000C0000, 0x0 }, |
112 | { 0x00C30FFF, 0x000C0000, 0x0 }, |
113 | { 0x00FFFFFF, 0x00070006, 0x0 }, |
113 | { 0x00FFFFFF, 0x00070006, 0x0 }, |
114 | { 0x00D75FFF, 0x000C0000, 0x0 }, |
114 | { 0x00D75FFF, 0x000C0000, 0x0 }, |
115 | }; |
115 | }; |
116 | 116 | ||
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
118 | /* Idx NT mV d T mV df db */ |
118 | /* Idx NT mV d T mV df db */ |
119 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
119 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
120 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ |
120 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ |
121 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ |
121 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ |
122 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ |
122 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ |
123 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ |
123 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ |
124 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ |
124 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ |
125 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ |
125 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ |
126 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ |
126 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ |
127 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ |
127 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ |
128 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ |
128 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ |
129 | }; |
129 | }; |
130 | 130 | ||
131 | /* Skylake H and S */ |
131 | /* Skylake H and S */ |
132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, |
135 | { 0x00007011, 0x00000088, 0x0 }, |
135 | { 0x00007011, 0x00000088, 0x0 }, |
136 | { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
136 | { 0x80009010, 0x000000C0, 0x1 }, |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, |
139 | { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
139 | { 0x80007011, 0x000000C0, 0x1 }, |
140 | { 0x00002016, 0x000000DF, 0x0 }, |
140 | { 0x00002016, 0x000000DF, 0x0 }, |
141 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
141 | { 0x80005012, 0x000000C0, 0x1 }, |
142 | }; |
142 | }; |
143 | 143 | ||
144 | /* Skylake U */ |
144 | /* Skylake U */ |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { |
146 | { 0x0000201B, 0x000000A2, 0x0 }, |
146 | { 0x0000201B, 0x000000A2, 0x0 }, |
147 | { 0x00005012, 0x00000088, 0x0 }, |
147 | { 0x00005012, 0x00000088, 0x0 }, |
148 | { 0x00007011, 0x00000087, 0x0 }, |
148 | { 0x80007011, 0x000000CD, 0x0 }, |
149 | { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
149 | { 0x80009010, 0x000000C0, 0x1 }, |
150 | { 0x0000201B, 0x0000009D, 0x0 }, |
150 | { 0x0000201B, 0x0000009D, 0x0 }, |
151 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
151 | { 0x80005012, 0x000000C0, 0x1 }, |
152 | { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
152 | { 0x80007011, 0x000000C0, 0x1 }, |
153 | { 0x00002016, 0x00000088, 0x0 }, |
153 | { 0x00002016, 0x00000088, 0x0 }, |
154 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
154 | { 0x80005012, 0x000000C0, 0x1 }, |
155 | }; |
155 | }; |
156 | 156 | ||
157 | /* Skylake Y */ |
157 | /* Skylake Y */ |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, |
161 | { 0x00007011, 0x00000087, 0x0 }, |
161 | { 0x80007011, 0x000000CD, 0x0 }, |
162 | { 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
162 | { 0x80009010, 0x000000C0, 0x3 }, |
163 | { 0x00000018, 0x0000009D, 0x0 }, |
163 | { 0x00000018, 0x0000009D, 0x0 }, |
164 | { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
164 | { 0x80005012, 0x000000C0, 0x3 }, |
165 | { 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
165 | { 0x80007011, 0x000000C0, 0x3 }, |
166 | { 0x00000018, 0x00000088, 0x0 }, |
166 | { 0x00000018, 0x00000088, 0x0 }, |
167 | { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
167 | { 0x80005012, 0x000000C0, 0x3 }, |
168 | }; |
168 | }; |
169 | 169 | ||
170 | /* |
170 | /* |
171 | * Skylake H and S |
171 | * Skylake H and S |
172 | * eDP 1.4 low vswing translation parameters |
172 | * eDP 1.4 low vswing translation parameters |
173 | */ |
173 | */ |
174 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
174 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
175 | { 0x00000018, 0x000000A8, 0x0 }, |
175 | { 0x00000018, 0x000000A8, 0x0 }, |
176 | { 0x00004013, 0x000000A9, 0x0 }, |
176 | { 0x00004013, 0x000000A9, 0x0 }, |
177 | { 0x00007011, 0x000000A2, 0x0 }, |
177 | { 0x00007011, 0x000000A2, 0x0 }, |
178 | { 0x00009010, 0x0000009C, 0x0 }, |
178 | { 0x00009010, 0x0000009C, 0x0 }, |
179 | { 0x00000018, 0x000000A9, 0x0 }, |
179 | { 0x00000018, 0x000000A9, 0x0 }, |
180 | { 0x00006013, 0x000000A2, 0x0 }, |
180 | { 0x00006013, 0x000000A2, 0x0 }, |
181 | { 0x00007011, 0x000000A6, 0x0 }, |
181 | { 0x00007011, 0x000000A6, 0x0 }, |
182 | { 0x00000018, 0x000000AB, 0x0 }, |
182 | { 0x00000018, 0x000000AB, 0x0 }, |
183 | { 0x00007013, 0x0000009F, 0x0 }, |
183 | { 0x00007013, 0x0000009F, 0x0 }, |
184 | { 0x00000018, 0x000000DF, 0x0 }, |
184 | { 0x00000018, 0x000000DF, 0x0 }, |
185 | }; |
185 | }; |
186 | 186 | ||
187 | /* |
187 | /* |
188 | * Skylake U |
188 | * Skylake U |
189 | * eDP 1.4 low vswing translation parameters |
189 | * eDP 1.4 low vswing translation parameters |
190 | */ |
190 | */ |
191 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { |
191 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { |
192 | { 0x00000018, 0x000000A8, 0x0 }, |
192 | { 0x00000018, 0x000000A8, 0x0 }, |
193 | { 0x00004013, 0x000000A9, 0x0 }, |
193 | { 0x00004013, 0x000000A9, 0x0 }, |
194 | { 0x00007011, 0x000000A2, 0x0 }, |
194 | { 0x00007011, 0x000000A2, 0x0 }, |
195 | { 0x00009010, 0x0000009C, 0x0 }, |
195 | { 0x00009010, 0x0000009C, 0x0 }, |
196 | { 0x00000018, 0x000000A9, 0x0 }, |
196 | { 0x00000018, 0x000000A9, 0x0 }, |
197 | { 0x00006013, 0x000000A2, 0x0 }, |
197 | { 0x00006013, 0x000000A2, 0x0 }, |
198 | { 0x00007011, 0x000000A6, 0x0 }, |
198 | { 0x00007011, 0x000000A6, 0x0 }, |
199 | { 0x00002016, 0x000000AB, 0x0 }, |
199 | { 0x00002016, 0x000000AB, 0x0 }, |
200 | { 0x00005013, 0x0000009F, 0x0 }, |
200 | { 0x00005013, 0x0000009F, 0x0 }, |
201 | { 0x00000018, 0x000000DF, 0x0 }, |
201 | { 0x00000018, 0x000000DF, 0x0 }, |
202 | }; |
202 | }; |
203 | 203 | ||
204 | /* |
204 | /* |
205 | * Skylake Y |
205 | * Skylake Y |
206 | * eDP 1.4 low vswing translation parameters |
206 | * eDP 1.4 low vswing translation parameters |
207 | */ |
207 | */ |
208 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
208 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
209 | { 0x00000018, 0x000000A8, 0x0 }, |
209 | { 0x00000018, 0x000000A8, 0x0 }, |
210 | { 0x00004013, 0x000000AB, 0x0 }, |
210 | { 0x00004013, 0x000000AB, 0x0 }, |
211 | { 0x00007011, 0x000000A4, 0x0 }, |
211 | { 0x00007011, 0x000000A4, 0x0 }, |
212 | { 0x00009010, 0x000000DF, 0x0 }, |
212 | { 0x00009010, 0x000000DF, 0x0 }, |
213 | { 0x00000018, 0x000000AA, 0x0 }, |
213 | { 0x00000018, 0x000000AA, 0x0 }, |
214 | { 0x00006013, 0x000000A4, 0x0 }, |
214 | { 0x00006013, 0x000000A4, 0x0 }, |
215 | { 0x00007011, 0x0000009D, 0x0 }, |
215 | { 0x00007011, 0x0000009D, 0x0 }, |
216 | { 0x00000018, 0x000000A0, 0x0 }, |
216 | { 0x00000018, 0x000000A0, 0x0 }, |
217 | { 0x00006012, 0x000000DF, 0x0 }, |
217 | { 0x00006012, 0x000000DF, 0x0 }, |
218 | { 0x00000018, 0x0000008A, 0x0 }, |
218 | { 0x00000018, 0x0000008A, 0x0 }, |
219 | }; |
219 | }; |
220 | 220 | ||
221 | /* Skylake U, H and S */ |
221 | /* Skylake U, H and S */ |
222 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
222 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
223 | { 0x00000018, 0x000000AC, 0x0 }, |
223 | { 0x00000018, 0x000000AC, 0x0 }, |
224 | { 0x00005012, 0x0000009D, 0x0 }, |
224 | { 0x00005012, 0x0000009D, 0x0 }, |
225 | { 0x00007011, 0x00000088, 0x0 }, |
225 | { 0x00007011, 0x00000088, 0x0 }, |
226 | { 0x00000018, 0x000000A1, 0x0 }, |
226 | { 0x00000018, 0x000000A1, 0x0 }, |
227 | { 0x00000018, 0x00000098, 0x0 }, |
227 | { 0x00000018, 0x00000098, 0x0 }, |
228 | { 0x00004013, 0x00000088, 0x0 }, |
228 | { 0x00004013, 0x00000088, 0x0 }, |
229 | { 0x00006012, 0x00000087, 0x0 }, |
229 | { 0x80006012, 0x000000CD, 0x1 }, |
230 | { 0x00000018, 0x000000DF, 0x0 }, |
230 | { 0x00000018, 0x000000DF, 0x0 }, |
231 | { 0x00003015, 0x00000087, 0x0 }, /* Default */ |
231 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
232 | { 0x00003015, 0x000000C7, 0x0 }, |
232 | { 0x80003015, 0x000000C0, 0x1 }, |
233 | { 0x00000018, 0x000000C7, 0x0 }, |
233 | { 0x80000018, 0x000000C0, 0x1 }, |
234 | }; |
234 | }; |
235 | 235 | ||
236 | /* Skylake Y */ |
236 | /* Skylake Y */ |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, |
240 | { 0x00007011, 0x00000084, 0x0 }, |
240 | { 0x80007011, 0x000000CB, 0x3 }, |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, |
243 | { 0x00004013, 0x00000080, 0x0 }, |
243 | { 0x00004013, 0x00000080, 0x0 }, |
244 | { 0x00006013, 0x000000C7, 0x0 }, |
244 | { 0x80006013, 0x000000C0, 0x3 }, |
245 | { 0x00000018, 0x0000008A, 0x0 }, |
245 | { 0x00000018, 0x0000008A, 0x0 }, |
246 | { 0x00003015, 0x000000C7, 0x0 }, /* Default */ |
246 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
247 | { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ |
247 | { 0x80003015, 0x000000C0, 0x3 }, |
248 | { 0x00000018, 0x000000C7, 0x0 }, |
248 | { 0x80000018, 0x000000C0, 0x3 }, |
249 | }; |
249 | }; |
250 | 250 | ||
251 | struct bxt_ddi_buf_trans { |
251 | struct bxt_ddi_buf_trans { |
252 | u32 margin; /* swing value */ |
252 | u32 margin; /* swing value */ |
253 | u32 scale; /* scale value */ |
253 | u32 scale; /* scale value */ |
254 | u32 enable; /* scale enable */ |
254 | u32 enable; /* scale enable */ |
255 | u32 deemphasis; |
255 | u32 deemphasis; |
256 | bool default_index; /* true if the entry represents default value */ |
256 | bool default_index; /* true if the entry represents default value */ |
257 | }; |
257 | }; |
258 | 258 | ||
259 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
259 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
260 | /* Idx NT mV diff db */ |
260 | /* Idx NT mV diff db */ |
261 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
261 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
262 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
262 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
263 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
263 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
264 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
264 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
265 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
265 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
266 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
266 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
267 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
267 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
268 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
268 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
269 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
269 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
270 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
270 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
271 | }; |
271 | }; |
272 | 272 | ||
273 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
273 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
274 | /* Idx NT mV diff db */ |
274 | /* Idx NT mV diff db */ |
275 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ |
275 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ |
276 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ |
276 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ |
277 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ |
277 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ |
278 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ |
278 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ |
279 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ |
279 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ |
280 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ |
280 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ |
281 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ |
281 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ |
282 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ |
282 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ |
283 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ |
283 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ |
284 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ |
284 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ |
285 | }; |
285 | }; |
286 | 286 | ||
287 | /* BSpec has 2 recommended values - entries 0 and 8. |
287 | /* BSpec has 2 recommended values - entries 0 and 8. |
288 | * Using the entry with higher vswing. |
288 | * Using the entry with higher vswing. |
289 | */ |
289 | */ |
290 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { |
290 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { |
291 | /* Idx NT mV diff db */ |
291 | /* Idx NT mV diff db */ |
292 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
292 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
293 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
293 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
294 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
294 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
295 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
295 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
296 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
296 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
297 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
297 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
298 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
298 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
302 | }; |
302 | }; |
303 | 303 | ||
304 | static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, |
304 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
305 | enum port port, int type); |
305 | u32 level, enum port port, int type); |
306 | 306 | ||
307 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
307 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
308 | struct intel_digital_port **dig_port, |
308 | struct intel_digital_port **dig_port, |
309 | enum port *port) |
309 | enum port *port) |
310 | { |
310 | { |
311 | struct drm_encoder *encoder = &intel_encoder->base; |
311 | struct drm_encoder *encoder = &intel_encoder->base; |
312 | 312 | ||
313 | switch (intel_encoder->type) { |
313 | switch (intel_encoder->type) { |
314 | case INTEL_OUTPUT_DP_MST: |
314 | case INTEL_OUTPUT_DP_MST: |
315 | *dig_port = enc_to_mst(encoder)->primary; |
315 | *dig_port = enc_to_mst(encoder)->primary; |
316 | *port = (*dig_port)->port; |
316 | *port = (*dig_port)->port; |
317 | break; |
317 | break; |
318 | case INTEL_OUTPUT_DISPLAYPORT: |
318 | case INTEL_OUTPUT_DISPLAYPORT: |
319 | case INTEL_OUTPUT_EDP: |
319 | case INTEL_OUTPUT_EDP: |
320 | case INTEL_OUTPUT_HDMI: |
320 | case INTEL_OUTPUT_HDMI: |
321 | case INTEL_OUTPUT_UNKNOWN: |
321 | case INTEL_OUTPUT_UNKNOWN: |
322 | *dig_port = enc_to_dig_port(encoder); |
322 | *dig_port = enc_to_dig_port(encoder); |
323 | *port = (*dig_port)->port; |
323 | *port = (*dig_port)->port; |
324 | break; |
324 | break; |
325 | case INTEL_OUTPUT_ANALOG: |
325 | case INTEL_OUTPUT_ANALOG: |
326 | *dig_port = NULL; |
326 | *dig_port = NULL; |
327 | *port = PORT_E; |
327 | *port = PORT_E; |
328 | break; |
328 | break; |
329 | default: |
329 | default: |
330 | WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); |
330 | WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); |
331 | break; |
331 | break; |
332 | } |
332 | } |
333 | } |
333 | } |
334 | 334 | ||
335 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
335 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
336 | { |
336 | { |
337 | struct intel_digital_port *dig_port; |
337 | struct intel_digital_port *dig_port; |
338 | enum port port; |
338 | enum port port; |
339 | 339 | ||
340 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); |
340 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); |
341 | 341 | ||
342 | return port; |
342 | return port; |
343 | } |
343 | } |
344 | - | ||
345 | static bool |
344 | |
346 | intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) |
- | |
347 | { |
- | |
348 | return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg); |
- | |
349 | } |
- | |
350 | 345 | static const struct ddi_buf_trans * |
|
351 | static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, |
- | |
352 | int *n_entries) |
346 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
353 | { |
- | |
354 | const struct ddi_buf_trans *ddi_translations; |
- | |
355 | 347 | { |
|
356 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
- | |
357 | ddi_translations = skl_y_ddi_translations_dp; |
348 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
- | 349 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
|
358 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
350 | return skl_y_ddi_translations_dp; |
359 | } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
- | |
360 | ddi_translations = skl_u_ddi_translations_dp; |
351 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
- | 352 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
|
361 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
353 | return skl_u_ddi_translations_dp; |
362 | } else { |
- | |
363 | ddi_translations = skl_ddi_translations_dp; |
354 | } else { |
- | 355 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
|
364 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
356 | return skl_ddi_translations_dp; |
365 | } |
- | |
366 | - | ||
367 | return ddi_translations; |
357 | } |
368 | } |
358 | } |
369 | 359 | ||
370 | static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, |
360 | static const struct ddi_buf_trans * |
371 | int *n_entries) |
- | |
372 | { |
- | |
373 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
374 | const struct ddi_buf_trans *ddi_translations; |
- | |
375 | 361 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
|
376 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
362 | { |
377 | if (dev_priv->edp_low_vswing) { |
363 | if (dev_priv->edp_low_vswing) { |
378 | ddi_translations = skl_y_ddi_translations_edp; |
- | |
379 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
364 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
380 | } else { |
- | |
381 | ddi_translations = skl_y_ddi_translations_dp; |
- | |
382 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
365 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
383 | } |
- | |
384 | } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
- | |
385 | if (dev_priv->edp_low_vswing) { |
366 | return skl_y_ddi_translations_edp; |
- | 367 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
|
386 | ddi_translations = skl_u_ddi_translations_edp; |
368 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
387 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
- | |
388 | } else { |
- | |
389 | ddi_translations = skl_u_ddi_translations_dp; |
- | |
390 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
- | |
391 | } |
- | |
392 | } else { |
- | |
393 | if (dev_priv->edp_low_vswing) { |
369 | return skl_u_ddi_translations_edp; |
394 | ddi_translations = skl_ddi_translations_edp; |
- | |
395 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
370 | } else { |
396 | } else { |
- | |
397 | ddi_translations = skl_ddi_translations_dp; |
371 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
398 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
372 | return skl_ddi_translations_edp; |
399 | } |
373 | } |
400 | } |
374 | } |
401 | 375 | ||
402 | return ddi_translations; |
376 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
403 | } |
377 | } |
404 | 378 | ||
405 | static const struct ddi_buf_trans * |
379 | static const struct ddi_buf_trans * |
406 | skl_get_buf_trans_hdmi(struct drm_device *dev, |
380 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
407 | int *n_entries) |
- | |
408 | { |
381 | { |
409 | const struct ddi_buf_trans *ddi_translations; |
- | |
410 | - | ||
411 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
382 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
412 | ddi_translations = skl_y_ddi_translations_hdmi; |
- | |
413 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
383 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
- | 384 | return skl_y_ddi_translations_hdmi; |
|
414 | } else { |
385 | } else { |
415 | ddi_translations = skl_ddi_translations_hdmi; |
- | |
416 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
386 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
- | 387 | return skl_ddi_translations_hdmi; |
|
417 | } |
388 | } |
418 | - | ||
419 | return ddi_translations; |
- | |
420 | } |
389 | } |
421 | 390 | ||
422 | /* |
391 | /* |
423 | * Starting with Haswell, DDI port buffers must be programmed with correct |
392 | * Starting with Haswell, DDI port buffers must be programmed with correct |
424 | * values in advance. The buffer values are different for FDI and DP modes, |
393 | * values in advance. The buffer values are different for FDI and DP modes, |
425 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
394 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
426 | * in either FDI or DP modes only, as HDMI connections will work with both |
395 | * in either FDI or DP modes only, as HDMI connections will work with both |
427 | * of those |
396 | * of those |
428 | */ |
397 | */ |
429 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, |
398 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder) |
430 | bool supports_hdmi) |
- | |
431 | { |
399 | { |
432 | struct drm_i915_private *dev_priv = dev->dev_private; |
400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
433 | u32 iboost_bit = 0; |
401 | u32 iboost_bit = 0; |
434 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
402 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
435 | size; |
403 | size; |
436 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
404 | int hdmi_level; |
- | 405 | enum port port; |
|
437 | const struct ddi_buf_trans *ddi_translations_fdi; |
406 | const struct ddi_buf_trans *ddi_translations_fdi; |
438 | const struct ddi_buf_trans *ddi_translations_dp; |
407 | const struct ddi_buf_trans *ddi_translations_dp; |
439 | const struct ddi_buf_trans *ddi_translations_edp; |
408 | const struct ddi_buf_trans *ddi_translations_edp; |
440 | const struct ddi_buf_trans *ddi_translations_hdmi; |
409 | const struct ddi_buf_trans *ddi_translations_hdmi; |
441 | const struct ddi_buf_trans *ddi_translations; |
410 | const struct ddi_buf_trans *ddi_translations; |
- | 411 | ||
- | 412 | port = intel_ddi_get_encoder_port(encoder); |
|
- | 413 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
|
442 | 414 | ||
443 | if (IS_BROXTON(dev)) { |
415 | if (IS_BROXTON(dev_priv)) { |
444 | if (!supports_hdmi) |
416 | if (encoder->type != INTEL_OUTPUT_HDMI) |
445 | return; |
417 | return; |
446 | 418 | ||
447 | /* Vswing programming for HDMI */ |
419 | /* Vswing programming for HDMI */ |
448 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, |
420 | bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port, |
449 | INTEL_OUTPUT_HDMI); |
421 | INTEL_OUTPUT_HDMI); |
450 | return; |
422 | return; |
- | 423 | } |
|
- | 424 | ||
451 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
425 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
452 | ddi_translations_fdi = NULL; |
426 | ddi_translations_fdi = NULL; |
453 | ddi_translations_dp = |
427 | ddi_translations_dp = |
454 | skl_get_buf_trans_dp(dev, &n_dp_entries); |
428 | skl_get_buf_trans_dp(dev_priv, &n_dp_entries); |
455 | ddi_translations_edp = |
429 | ddi_translations_edp = |
456 | skl_get_buf_trans_edp(dev, &n_edp_entries); |
430 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); |
457 | ddi_translations_hdmi = |
431 | ddi_translations_hdmi = |
458 | skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); |
432 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
459 | hdmi_default_entry = 8; |
433 | hdmi_default_entry = 8; |
460 | /* If we're boosting the current, set bit 31 of trans1 */ |
434 | /* If we're boosting the current, set bit 31 of trans1 */ |
461 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || |
435 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || |
462 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) |
436 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) |
463 | iboost_bit = 1<<31; |
437 | iboost_bit = 1<<31; |
- | 438 | ||
- | 439 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && |
|
- | 440 | port != PORT_A && port != PORT_E && |
|
- | 441 | n_edp_entries > 9)) |
|
- | 442 | n_edp_entries = 9; |
|
464 | } else if (IS_BROADWELL(dev)) { |
443 | } else if (IS_BROADWELL(dev_priv)) { |
465 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
444 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
466 | ddi_translations_dp = bdw_ddi_translations_dp; |
445 | ddi_translations_dp = bdw_ddi_translations_dp; |
467 | 446 | ||
468 | if (dev_priv->edp_low_vswing) { |
447 | if (dev_priv->edp_low_vswing) { |
469 | ddi_translations_edp = bdw_ddi_translations_edp; |
448 | ddi_translations_edp = bdw_ddi_translations_edp; |
470 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
449 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
471 | } else { |
450 | } else { |
472 | ddi_translations_edp = bdw_ddi_translations_dp; |
451 | ddi_translations_edp = bdw_ddi_translations_dp; |
473 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
452 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
474 | } |
453 | } |
475 | 454 | ||
476 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
455 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
477 | 456 | ||
478 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
457 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
479 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
458 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
480 | hdmi_default_entry = 7; |
459 | hdmi_default_entry = 7; |
481 | } else if (IS_HASWELL(dev)) { |
460 | } else if (IS_HASWELL(dev_priv)) { |
482 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
461 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
483 | ddi_translations_dp = hsw_ddi_translations_dp; |
462 | ddi_translations_dp = hsw_ddi_translations_dp; |
484 | ddi_translations_edp = hsw_ddi_translations_dp; |
463 | ddi_translations_edp = hsw_ddi_translations_dp; |
485 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
464 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
486 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
465 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
487 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
466 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
488 | hdmi_default_entry = 6; |
467 | hdmi_default_entry = 6; |
489 | } else { |
468 | } else { |
490 | WARN(1, "ddi translation table missing\n"); |
469 | WARN(1, "ddi translation table missing\n"); |
491 | ddi_translations_edp = bdw_ddi_translations_dp; |
470 | ddi_translations_edp = bdw_ddi_translations_dp; |
492 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
471 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
493 | ddi_translations_dp = bdw_ddi_translations_dp; |
472 | ddi_translations_dp = bdw_ddi_translations_dp; |
494 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
473 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
495 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
474 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
496 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
475 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
497 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
476 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
498 | hdmi_default_entry = 7; |
477 | hdmi_default_entry = 7; |
499 | } |
478 | } |
500 | 479 | ||
501 | switch (port) { |
480 | switch (encoder->type) { |
502 | case PORT_A: |
481 | case INTEL_OUTPUT_EDP: |
503 | ddi_translations = ddi_translations_edp; |
482 | ddi_translations = ddi_translations_edp; |
504 | size = n_edp_entries; |
483 | size = n_edp_entries; |
505 | break; |
484 | break; |
506 | case PORT_B: |
- | |
507 | case PORT_C: |
485 | case INTEL_OUTPUT_DISPLAYPORT: |
508 | ddi_translations = ddi_translations_dp; |
- | |
509 | size = n_dp_entries; |
- | |
510 | break; |
- | |
511 | case PORT_D: |
486 | case INTEL_OUTPUT_HDMI: |
512 | if (intel_dp_is_edp(dev, PORT_D)) { |
- | |
513 | ddi_translations = ddi_translations_edp; |
- | |
514 | size = n_edp_entries; |
- | |
515 | } else { |
- | |
516 | ddi_translations = ddi_translations_dp; |
487 | ddi_translations = ddi_translations_dp; |
517 | size = n_dp_entries; |
488 | size = n_dp_entries; |
518 | } |
- | |
519 | break; |
489 | break; |
520 | case PORT_E: |
490 | case INTEL_OUTPUT_ANALOG: |
521 | if (ddi_translations_fdi) |
- | |
522 | ddi_translations = ddi_translations_fdi; |
491 | ddi_translations = ddi_translations_fdi; |
523 | else |
- | |
524 | ddi_translations = ddi_translations_dp; |
- | |
525 | size = n_dp_entries; |
492 | size = n_dp_entries; |
526 | break; |
493 | break; |
527 | default: |
494 | default: |
528 | BUG(); |
495 | BUG(); |
529 | } |
496 | } |
530 | 497 | ||
531 | for (i = 0; i < size; i++) { |
498 | for (i = 0; i < size; i++) { |
532 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
499 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
533 | ddi_translations[i].trans1 | iboost_bit); |
500 | ddi_translations[i].trans1 | iboost_bit); |
534 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
501 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
535 | ddi_translations[i].trans2); |
502 | ddi_translations[i].trans2); |
536 | } |
503 | } |
537 | 504 | ||
538 | if (!supports_hdmi) |
505 | if (encoder->type != INTEL_OUTPUT_HDMI) |
539 | return; |
506 | return; |
540 | 507 | ||
541 | /* Choose a good default if VBT is badly populated */ |
508 | /* Choose a good default if VBT is badly populated */ |
542 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || |
509 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || |
543 | hdmi_level >= n_hdmi_entries) |
510 | hdmi_level >= n_hdmi_entries) |
544 | hdmi_level = hdmi_default_entry; |
511 | hdmi_level = hdmi_default_entry; |
545 | 512 | ||
546 | /* Entry 9 is for HDMI: */ |
513 | /* Entry 9 is for HDMI: */ |
547 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
514 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
548 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
515 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
549 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
516 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
550 | ddi_translations_hdmi[hdmi_level].trans2); |
517 | ddi_translations_hdmi[hdmi_level].trans2); |
551 | } |
518 | } |
552 | - | ||
553 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP |
- | |
554 | * mode and port E for FDI. |
- | |
555 | */ |
- | |
556 | void intel_prepare_ddi(struct drm_device *dev) |
- | |
557 | { |
- | |
558 | struct intel_encoder *intel_encoder; |
- | |
559 | bool visited[I915_MAX_PORTS] = { 0, }; |
- | |
560 | - | ||
561 | if (!HAS_DDI(dev)) |
- | |
562 | return; |
- | |
563 | - | ||
564 | for_each_intel_encoder(dev, intel_encoder) { |
- | |
565 | struct intel_digital_port *intel_dig_port; |
- | |
566 | enum port port; |
- | |
567 | bool supports_hdmi; |
- | |
568 | - | ||
569 | if (intel_encoder->type == INTEL_OUTPUT_DSI) |
- | |
570 | continue; |
- | |
571 | - | ||
572 | ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); |
- | |
573 | if (visited[port]) |
- | |
574 | continue; |
- | |
575 | - | ||
576 | supports_hdmi = intel_dig_port && |
- | |
577 | intel_dig_port_supports_hdmi(intel_dig_port); |
- | |
578 | - | ||
579 | intel_prepare_ddi_buffers(dev, port, supports_hdmi); |
- | |
580 | visited[port] = true; |
- | |
581 | } |
- | |
582 | } |
- | |
583 | 519 | ||
584 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
520 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
585 | enum port port) |
521 | enum port port) |
586 | { |
522 | { |
587 | i915_reg_t reg = DDI_BUF_CTL(port); |
523 | i915_reg_t reg = DDI_BUF_CTL(port); |
588 | int i; |
524 | int i; |
589 | 525 | ||
590 | for (i = 0; i < 16; i++) { |
526 | for (i = 0; i < 16; i++) { |
591 | udelay(1); |
527 | udelay(1); |
592 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) |
528 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) |
593 | return; |
529 | return; |
594 | } |
530 | } |
595 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); |
531 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); |
596 | } |
532 | } |
597 | 533 | ||
598 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
534 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
599 | * connection to the PCH-located connectors. For this, it is necessary to train |
535 | * connection to the PCH-located connectors. For this, it is necessary to train |
600 | * both the DDI port and PCH receiver for the desired DDI buffer settings. |
536 | * both the DDI port and PCH receiver for the desired DDI buffer settings. |
601 | * |
537 | * |
602 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, |
538 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, |
603 | * please note that when FDI mode is active on DDI E, it shares 2 lines with |
539 | * please note that when FDI mode is active on DDI E, it shares 2 lines with |
604 | * DDI A (which is used for eDP) |
540 | * DDI A (which is used for eDP) |
605 | */ |
541 | */ |
606 | 542 | ||
607 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
543 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
608 | { |
544 | { |
609 | struct drm_device *dev = crtc->dev; |
545 | struct drm_device *dev = crtc->dev; |
610 | struct drm_i915_private *dev_priv = dev->dev_private; |
546 | struct drm_i915_private *dev_priv = dev->dev_private; |
611 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 548 | struct intel_encoder *encoder; |
|
612 | u32 temp, i, rx_ctl_val; |
549 | u32 temp, i, rx_ctl_val; |
- | 550 | ||
- | 551 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
- | 552 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); |
|
- | 553 | intel_prepare_ddi_buffer(encoder); |
|
- | 554 | } |
|
613 | 555 | ||
614 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
556 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
615 | * mode set "sequence for CRT port" document: |
557 | * mode set "sequence for CRT port" document: |
616 | * - TP1 to TP2 time with the default value |
558 | * - TP1 to TP2 time with the default value |
617 | * - FDI delay to 90h |
559 | * - FDI delay to 90h |
618 | * |
560 | * |
619 | * WaFDIAutoLinkSetTimingOverrride:hsw |
561 | * WaFDIAutoLinkSetTimingOverrride:hsw |
620 | */ |
562 | */ |
621 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
563 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
622 | FDI_RX_PWRDN_LANE0_VAL(2) | |
564 | FDI_RX_PWRDN_LANE0_VAL(2) | |
623 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
565 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
624 | 566 | ||
625 | /* Enable the PCH Receiver FDI PLL */ |
567 | /* Enable the PCH Receiver FDI PLL */ |
626 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
568 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
627 | FDI_RX_PLL_ENABLE | |
569 | FDI_RX_PLL_ENABLE | |
628 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
570 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
629 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
571 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
630 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
572 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
631 | udelay(220); |
573 | udelay(220); |
632 | 574 | ||
633 | /* Switch from Rawclk to PCDclk */ |
575 | /* Switch from Rawclk to PCDclk */ |
634 | rx_ctl_val |= FDI_PCDCLK; |
576 | rx_ctl_val |= FDI_PCDCLK; |
635 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
577 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
636 | 578 | ||
637 | /* Configure Port Clock Select */ |
579 | /* Configure Port Clock Select */ |
638 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
580 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
639 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); |
581 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); |
640 | 582 | ||
641 | /* Start the training iterating through available voltages and emphasis, |
583 | /* Start the training iterating through available voltages and emphasis, |
642 | * testing each value twice. */ |
584 | * testing each value twice. */ |
643 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
585 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
644 | /* Configure DP_TP_CTL with auto-training */ |
586 | /* Configure DP_TP_CTL with auto-training */ |
645 | I915_WRITE(DP_TP_CTL(PORT_E), |
587 | I915_WRITE(DP_TP_CTL(PORT_E), |
646 | DP_TP_CTL_FDI_AUTOTRAIN | |
588 | DP_TP_CTL_FDI_AUTOTRAIN | |
647 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
589 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
648 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
590 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
649 | DP_TP_CTL_ENABLE); |
591 | DP_TP_CTL_ENABLE); |
650 | 592 | ||
651 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
593 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
652 | * DDI E does not support port reversal, the functionality is |
594 | * DDI E does not support port reversal, the functionality is |
653 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the |
595 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the |
654 | * port reversal bit */ |
596 | * port reversal bit */ |
655 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
597 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
656 | DDI_BUF_CTL_ENABLE | |
598 | DDI_BUF_CTL_ENABLE | |
657 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
599 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
658 | DDI_BUF_TRANS_SELECT(i / 2)); |
600 | DDI_BUF_TRANS_SELECT(i / 2)); |
659 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
601 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
660 | 602 | ||
661 | udelay(600); |
603 | udelay(600); |
662 | 604 | ||
663 | /* Program PCH FDI Receiver TU */ |
605 | /* Program PCH FDI Receiver TU */ |
664 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
606 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
665 | 607 | ||
666 | /* Enable PCH FDI Receiver with auto-training */ |
608 | /* Enable PCH FDI Receiver with auto-training */ |
667 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; |
609 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; |
668 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
610 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
669 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
611 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
670 | 612 | ||
671 | /* Wait for FDI receiver lane calibration */ |
613 | /* Wait for FDI receiver lane calibration */ |
672 | udelay(30); |
614 | udelay(30); |
673 | 615 | ||
674 | /* Unset FDI_RX_MISC pwrdn lanes */ |
616 | /* Unset FDI_RX_MISC pwrdn lanes */ |
675 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
617 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
676 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
618 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
677 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
619 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
678 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
620 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
679 | 621 | ||
680 | /* Wait for FDI auto training time */ |
622 | /* Wait for FDI auto training time */ |
681 | udelay(5); |
623 | udelay(5); |
682 | 624 | ||
683 | temp = I915_READ(DP_TP_STATUS(PORT_E)); |
625 | temp = I915_READ(DP_TP_STATUS(PORT_E)); |
684 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
626 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
685 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
627 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
686 | break; |
628 | break; |
687 | } |
629 | } |
688 | 630 | ||
689 | /* |
631 | /* |
690 | * Leave things enabled even if we failed to train FDI. |
632 | * Leave things enabled even if we failed to train FDI. |
691 | * Results in less fireworks from the state checker. |
633 | * Results in less fireworks from the state checker. |
692 | */ |
634 | */ |
693 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { |
635 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { |
694 | DRM_ERROR("FDI link training failed!\n"); |
636 | DRM_ERROR("FDI link training failed!\n"); |
695 | break; |
637 | break; |
696 | } |
638 | } |
697 | 639 | ||
698 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
640 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
699 | temp &= ~DDI_BUF_CTL_ENABLE; |
641 | temp &= ~DDI_BUF_CTL_ENABLE; |
700 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); |
642 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); |
701 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
643 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
702 | 644 | ||
703 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
645 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
704 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
646 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
705 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
647 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
706 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
648 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
707 | I915_WRITE(DP_TP_CTL(PORT_E), temp); |
649 | I915_WRITE(DP_TP_CTL(PORT_E), temp); |
708 | POSTING_READ(DP_TP_CTL(PORT_E)); |
650 | POSTING_READ(DP_TP_CTL(PORT_E)); |
709 | 651 | ||
710 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); |
652 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); |
711 | 653 | ||
712 | rx_ctl_val &= ~FDI_RX_ENABLE; |
654 | rx_ctl_val &= ~FDI_RX_ENABLE; |
713 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
655 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
714 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
656 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
715 | 657 | ||
716 | /* Reset FDI_RX_MISC pwrdn lanes */ |
658 | /* Reset FDI_RX_MISC pwrdn lanes */ |
717 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
659 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
718 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
660 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
719 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
661 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
720 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
662 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
721 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
663 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
722 | } |
664 | } |
723 | 665 | ||
724 | /* Enable normal pixel sending for FDI */ |
666 | /* Enable normal pixel sending for FDI */ |
725 | I915_WRITE(DP_TP_CTL(PORT_E), |
667 | I915_WRITE(DP_TP_CTL(PORT_E), |
726 | DP_TP_CTL_FDI_AUTOTRAIN | |
668 | DP_TP_CTL_FDI_AUTOTRAIN | |
727 | DP_TP_CTL_LINK_TRAIN_NORMAL | |
669 | DP_TP_CTL_LINK_TRAIN_NORMAL | |
728 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
670 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
729 | DP_TP_CTL_ENABLE); |
671 | DP_TP_CTL_ENABLE); |
730 | } |
672 | } |
731 | 673 | ||
732 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
674 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
733 | { |
675 | { |
734 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
676 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
735 | struct intel_digital_port *intel_dig_port = |
677 | struct intel_digital_port *intel_dig_port = |
736 | enc_to_dig_port(&encoder->base); |
678 | enc_to_dig_port(&encoder->base); |
737 | 679 | ||
738 | intel_dp->DP = intel_dig_port->saved_port_bits | |
680 | intel_dp->DP = intel_dig_port->saved_port_bits | |
739 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
681 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
740 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
682 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
741 | } |
683 | } |
742 | 684 | ||
743 | static struct intel_encoder * |
685 | static struct intel_encoder * |
744 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) |
686 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) |
745 | { |
687 | { |
746 | struct drm_device *dev = crtc->dev; |
688 | struct drm_device *dev = crtc->dev; |
747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
748 | struct intel_encoder *intel_encoder, *ret = NULL; |
690 | struct intel_encoder *intel_encoder, *ret = NULL; |
749 | int num_encoders = 0; |
691 | int num_encoders = 0; |
750 | 692 | ||
751 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
693 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
752 | ret = intel_encoder; |
694 | ret = intel_encoder; |
753 | num_encoders++; |
695 | num_encoders++; |
754 | } |
696 | } |
755 | 697 | ||
756 | if (num_encoders != 1) |
698 | if (num_encoders != 1) |
757 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
699 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
758 | pipe_name(intel_crtc->pipe)); |
700 | pipe_name(intel_crtc->pipe)); |
759 | 701 | ||
760 | BUG_ON(ret == NULL); |
702 | BUG_ON(ret == NULL); |
761 | return ret; |
703 | return ret; |
762 | } |
704 | } |
763 | 705 | ||
764 | struct intel_encoder * |
706 | struct intel_encoder * |
765 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
707 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
766 | { |
708 | { |
767 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
709 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
768 | struct intel_encoder *ret = NULL; |
710 | struct intel_encoder *ret = NULL; |
769 | struct drm_atomic_state *state; |
711 | struct drm_atomic_state *state; |
770 | struct drm_connector *connector; |
712 | struct drm_connector *connector; |
771 | struct drm_connector_state *connector_state; |
713 | struct drm_connector_state *connector_state; |
772 | int num_encoders = 0; |
714 | int num_encoders = 0; |
773 | int i; |
715 | int i; |
774 | 716 | ||
775 | state = crtc_state->base.state; |
717 | state = crtc_state->base.state; |
776 | 718 | ||
777 | for_each_connector_in_state(state, connector, connector_state, i) { |
719 | for_each_connector_in_state(state, connector, connector_state, i) { |
778 | if (connector_state->crtc != crtc_state->base.crtc) |
720 | if (connector_state->crtc != crtc_state->base.crtc) |
779 | continue; |
721 | continue; |
780 | 722 | ||
781 | ret = to_intel_encoder(connector_state->best_encoder); |
723 | ret = to_intel_encoder(connector_state->best_encoder); |
782 | num_encoders++; |
724 | num_encoders++; |
783 | } |
725 | } |
784 | 726 | ||
785 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, |
727 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, |
786 | pipe_name(crtc->pipe)); |
728 | pipe_name(crtc->pipe)); |
787 | 729 | ||
788 | BUG_ON(ret == NULL); |
730 | BUG_ON(ret == NULL); |
789 | return ret; |
731 | return ret; |
790 | } |
732 | } |
791 | 733 | ||
792 | #define LC_FREQ 2700 |
734 | #define LC_FREQ 2700 |
793 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
735 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
794 | 736 | ||
795 | #define P_MIN 2 |
737 | #define P_MIN 2 |
796 | #define P_MAX 64 |
738 | #define P_MAX 64 |
797 | #define P_INC 2 |
739 | #define P_INC 2 |
798 | 740 | ||
799 | /* Constraints for PLL good behavior */ |
741 | /* Constraints for PLL good behavior */ |
800 | #define REF_MIN 48 |
742 | #define REF_MIN 48 |
801 | #define REF_MAX 400 |
743 | #define REF_MAX 400 |
802 | #define VCO_MIN 2400 |
744 | #define VCO_MIN 2400 |
803 | #define VCO_MAX 4800 |
745 | #define VCO_MAX 4800 |
804 | 746 | ||
805 | #define abs_diff(a, b) ({ \ |
747 | #define abs_diff(a, b) ({ \ |
806 | typeof(a) __a = (a); \ |
748 | typeof(a) __a = (a); \ |
807 | typeof(b) __b = (b); \ |
749 | typeof(b) __b = (b); \ |
808 | (void) (&__a == &__b); \ |
750 | (void) (&__a == &__b); \ |
809 | __a > __b ? (__a - __b) : (__b - __a); }) |
751 | __a > __b ? (__a - __b) : (__b - __a); }) |
810 | 752 | ||
811 | struct hsw_wrpll_rnp { |
753 | struct hsw_wrpll_rnp { |
812 | unsigned p, n2, r2; |
754 | unsigned p, n2, r2; |
813 | }; |
755 | }; |
814 | 756 | ||
815 | static unsigned hsw_wrpll_get_budget_for_freq(int clock) |
757 | static unsigned hsw_wrpll_get_budget_for_freq(int clock) |
816 | { |
758 | { |
817 | unsigned budget; |
759 | unsigned budget; |
818 | 760 | ||
819 | switch (clock) { |
761 | switch (clock) { |
820 | case 25175000: |
762 | case 25175000: |
821 | case 25200000: |
763 | case 25200000: |
822 | case 27000000: |
764 | case 27000000: |
823 | case 27027000: |
765 | case 27027000: |
824 | case 37762500: |
766 | case 37762500: |
825 | case 37800000: |
767 | case 37800000: |
826 | case 40500000: |
768 | case 40500000: |
827 | case 40541000: |
769 | case 40541000: |
828 | case 54000000: |
770 | case 54000000: |
829 | case 54054000: |
771 | case 54054000: |
830 | case 59341000: |
772 | case 59341000: |
831 | case 59400000: |
773 | case 59400000: |
832 | case 72000000: |
774 | case 72000000: |
833 | case 74176000: |
775 | case 74176000: |
834 | case 74250000: |
776 | case 74250000: |
835 | case 81000000: |
777 | case 81000000: |
836 | case 81081000: |
778 | case 81081000: |
837 | case 89012000: |
779 | case 89012000: |
838 | case 89100000: |
780 | case 89100000: |
839 | case 108000000: |
781 | case 108000000: |
840 | case 108108000: |
782 | case 108108000: |
841 | case 111264000: |
783 | case 111264000: |
842 | case 111375000: |
784 | case 111375000: |
843 | case 148352000: |
785 | case 148352000: |
844 | case 148500000: |
786 | case 148500000: |
845 | case 162000000: |
787 | case 162000000: |
846 | case 162162000: |
788 | case 162162000: |
847 | case 222525000: |
789 | case 222525000: |
848 | case 222750000: |
790 | case 222750000: |
849 | case 296703000: |
791 | case 296703000: |
850 | case 297000000: |
792 | case 297000000: |
851 | budget = 0; |
793 | budget = 0; |
852 | break; |
794 | break; |
853 | case 233500000: |
795 | case 233500000: |
854 | case 245250000: |
796 | case 245250000: |
855 | case 247750000: |
797 | case 247750000: |
856 | case 253250000: |
798 | case 253250000: |
857 | case 298000000: |
799 | case 298000000: |
858 | budget = 1500; |
800 | budget = 1500; |
859 | break; |
801 | break; |
860 | case 169128000: |
802 | case 169128000: |
861 | case 169500000: |
803 | case 169500000: |
862 | case 179500000: |
804 | case 179500000: |
863 | case 202000000: |
805 | case 202000000: |
864 | budget = 2000; |
806 | budget = 2000; |
865 | break; |
807 | break; |
866 | case 256250000: |
808 | case 256250000: |
867 | case 262500000: |
809 | case 262500000: |
868 | case 270000000: |
810 | case 270000000: |
869 | case 272500000: |
811 | case 272500000: |
870 | case 273750000: |
812 | case 273750000: |
871 | case 280750000: |
813 | case 280750000: |
872 | case 281250000: |
814 | case 281250000: |
873 | case 286000000: |
815 | case 286000000: |
874 | case 291750000: |
816 | case 291750000: |
875 | budget = 4000; |
817 | budget = 4000; |
876 | break; |
818 | break; |
877 | case 267250000: |
819 | case 267250000: |
878 | case 268500000: |
820 | case 268500000: |
879 | budget = 5000; |
821 | budget = 5000; |
880 | break; |
822 | break; |
881 | default: |
823 | default: |
882 | budget = 1000; |
824 | budget = 1000; |
883 | break; |
825 | break; |
884 | } |
826 | } |
885 | 827 | ||
886 | return budget; |
828 | return budget; |
887 | } |
829 | } |
888 | 830 | ||
889 | static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, |
831 | static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, |
890 | unsigned r2, unsigned n2, unsigned p, |
832 | unsigned r2, unsigned n2, unsigned p, |
891 | struct hsw_wrpll_rnp *best) |
833 | struct hsw_wrpll_rnp *best) |
892 | { |
834 | { |
893 | uint64_t a, b, c, d, diff, diff_best; |
835 | uint64_t a, b, c, d, diff, diff_best; |
894 | 836 | ||
895 | /* No best (r,n,p) yet */ |
837 | /* No best (r,n,p) yet */ |
896 | if (best->p == 0) { |
838 | if (best->p == 0) { |
897 | best->p = p; |
839 | best->p = p; |
898 | best->n2 = n2; |
840 | best->n2 = n2; |
899 | best->r2 = r2; |
841 | best->r2 = r2; |
900 | return; |
842 | return; |
901 | } |
843 | } |
902 | 844 | ||
903 | /* |
845 | /* |
904 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to |
846 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to |
905 | * freq2k. |
847 | * freq2k. |
906 | * |
848 | * |
907 | * delta = 1e6 * |
849 | * delta = 1e6 * |
908 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / |
850 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / |
909 | * freq2k; |
851 | * freq2k; |
910 | * |
852 | * |
911 | * and we would like delta <= budget. |
853 | * and we would like delta <= budget. |
912 | * |
854 | * |
913 | * If the discrepancy is above the PPM-based budget, always prefer to |
855 | * If the discrepancy is above the PPM-based budget, always prefer to |
914 | * improve upon the previous solution. However, if you're within the |
856 | * improve upon the previous solution. However, if you're within the |
915 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). |
857 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). |
916 | */ |
858 | */ |
917 | a = freq2k * budget * p * r2; |
859 | a = freq2k * budget * p * r2; |
918 | b = freq2k * budget * best->p * best->r2; |
860 | b = freq2k * budget * best->p * best->r2; |
919 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
861 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
920 | diff_best = abs_diff(freq2k * best->p * best->r2, |
862 | diff_best = abs_diff(freq2k * best->p * best->r2, |
921 | LC_FREQ_2K * best->n2); |
863 | LC_FREQ_2K * best->n2); |
922 | c = 1000000 * diff; |
864 | c = 1000000 * diff; |
923 | d = 1000000 * diff_best; |
865 | d = 1000000 * diff_best; |
924 | 866 | ||
925 | if (a < c && b < d) { |
867 | if (a < c && b < d) { |
926 | /* If both are above the budget, pick the closer */ |
868 | /* If both are above the budget, pick the closer */ |
927 | if (best->p * best->r2 * diff < p * r2 * diff_best) { |
869 | if (best->p * best->r2 * diff < p * r2 * diff_best) { |
928 | best->p = p; |
870 | best->p = p; |
929 | best->n2 = n2; |
871 | best->n2 = n2; |
930 | best->r2 = r2; |
872 | best->r2 = r2; |
931 | } |
873 | } |
932 | } else if (a >= c && b < d) { |
874 | } else if (a >= c && b < d) { |
933 | /* If A is below the threshold but B is above it? Update. */ |
875 | /* If A is below the threshold but B is above it? Update. */ |
934 | best->p = p; |
876 | best->p = p; |
935 | best->n2 = n2; |
877 | best->n2 = n2; |
936 | best->r2 = r2; |
878 | best->r2 = r2; |
937 | } else if (a >= c && b >= d) { |
879 | } else if (a >= c && b >= d) { |
938 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ |
880 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ |
939 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { |
881 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { |
940 | best->p = p; |
882 | best->p = p; |
941 | best->n2 = n2; |
883 | best->n2 = n2; |
942 | best->r2 = r2; |
884 | best->r2 = r2; |
943 | } |
885 | } |
944 | } |
886 | } |
945 | /* Otherwise a < c && b >= d, do nothing */ |
887 | /* Otherwise a < c && b >= d, do nothing */ |
946 | } |
888 | } |
947 | 889 | ||
948 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
890 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
949 | i915_reg_t reg) |
891 | i915_reg_t reg) |
950 | { |
892 | { |
951 | int refclk = LC_FREQ; |
893 | int refclk = LC_FREQ; |
952 | int n, p, r; |
894 | int n, p, r; |
953 | u32 wrpll; |
895 | u32 wrpll; |
954 | 896 | ||
955 | wrpll = I915_READ(reg); |
897 | wrpll = I915_READ(reg); |
956 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
898 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
957 | case WRPLL_PLL_SSC: |
899 | case WRPLL_PLL_SSC: |
958 | case WRPLL_PLL_NON_SSC: |
900 | case WRPLL_PLL_NON_SSC: |
959 | /* |
901 | /* |
960 | * We could calculate spread here, but our checking |
902 | * We could calculate spread here, but our checking |
961 | * code only cares about 5% accuracy, and spread is a max of |
903 | * code only cares about 5% accuracy, and spread is a max of |
962 | * 0.5% downspread. |
904 | * 0.5% downspread. |
963 | */ |
905 | */ |
964 | refclk = 135; |
906 | refclk = 135; |
965 | break; |
907 | break; |
966 | case WRPLL_PLL_LCPLL: |
908 | case WRPLL_PLL_LCPLL: |
967 | refclk = LC_FREQ; |
909 | refclk = LC_FREQ; |
968 | break; |
910 | break; |
969 | default: |
911 | default: |
970 | WARN(1, "bad wrpll refclk\n"); |
912 | WARN(1, "bad wrpll refclk\n"); |
971 | return 0; |
913 | return 0; |
972 | } |
914 | } |
973 | 915 | ||
974 | r = wrpll & WRPLL_DIVIDER_REF_MASK; |
916 | r = wrpll & WRPLL_DIVIDER_REF_MASK; |
975 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; |
917 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; |
976 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; |
918 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; |
977 | 919 | ||
978 | /* Convert to KHz, p & r have a fixed point portion */ |
920 | /* Convert to KHz, p & r have a fixed point portion */ |
979 | return (refclk * n * 100) / (p * r); |
921 | return (refclk * n * 100) / (p * r); |
980 | } |
922 | } |
981 | 923 | ||
982 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
924 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
983 | uint32_t dpll) |
925 | uint32_t dpll) |
984 | { |
926 | { |
985 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
927 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
986 | uint32_t cfgcr1_val, cfgcr2_val; |
928 | uint32_t cfgcr1_val, cfgcr2_val; |
987 | uint32_t p0, p1, p2, dco_freq; |
929 | uint32_t p0, p1, p2, dco_freq; |
988 | 930 | ||
989 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
931 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
990 | cfgcr2_reg = DPLL_CFGCR2(dpll); |
932 | cfgcr2_reg = DPLL_CFGCR2(dpll); |
991 | 933 | ||
992 | cfgcr1_val = I915_READ(cfgcr1_reg); |
934 | cfgcr1_val = I915_READ(cfgcr1_reg); |
993 | cfgcr2_val = I915_READ(cfgcr2_reg); |
935 | cfgcr2_val = I915_READ(cfgcr2_reg); |
994 | 936 | ||
995 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; |
937 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; |
996 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; |
938 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; |
997 | 939 | ||
998 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) |
940 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) |
999 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; |
941 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; |
1000 | else |
942 | else |
1001 | p1 = 1; |
943 | p1 = 1; |
1002 | 944 | ||
1003 | 945 | ||
1004 | switch (p0) { |
946 | switch (p0) { |
1005 | case DPLL_CFGCR2_PDIV_1: |
947 | case DPLL_CFGCR2_PDIV_1: |
1006 | p0 = 1; |
948 | p0 = 1; |
1007 | break; |
949 | break; |
1008 | case DPLL_CFGCR2_PDIV_2: |
950 | case DPLL_CFGCR2_PDIV_2: |
1009 | p0 = 2; |
951 | p0 = 2; |
1010 | break; |
952 | break; |
1011 | case DPLL_CFGCR2_PDIV_3: |
953 | case DPLL_CFGCR2_PDIV_3: |
1012 | p0 = 3; |
954 | p0 = 3; |
1013 | break; |
955 | break; |
1014 | case DPLL_CFGCR2_PDIV_7: |
956 | case DPLL_CFGCR2_PDIV_7: |
1015 | p0 = 7; |
957 | p0 = 7; |
1016 | break; |
958 | break; |
1017 | } |
959 | } |
1018 | 960 | ||
1019 | switch (p2) { |
961 | switch (p2) { |
1020 | case DPLL_CFGCR2_KDIV_5: |
962 | case DPLL_CFGCR2_KDIV_5: |
1021 | p2 = 5; |
963 | p2 = 5; |
1022 | break; |
964 | break; |
1023 | case DPLL_CFGCR2_KDIV_2: |
965 | case DPLL_CFGCR2_KDIV_2: |
1024 | p2 = 2; |
966 | p2 = 2; |
1025 | break; |
967 | break; |
1026 | case DPLL_CFGCR2_KDIV_3: |
968 | case DPLL_CFGCR2_KDIV_3: |
1027 | p2 = 3; |
969 | p2 = 3; |
1028 | break; |
970 | break; |
1029 | case DPLL_CFGCR2_KDIV_1: |
971 | case DPLL_CFGCR2_KDIV_1: |
1030 | p2 = 1; |
972 | p2 = 1; |
1031 | break; |
973 | break; |
1032 | } |
974 | } |
1033 | 975 | ||
1034 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; |
976 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; |
1035 | 977 | ||
1036 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * |
978 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * |
1037 | 1000) / 0x8000; |
979 | 1000) / 0x8000; |
1038 | 980 | ||
1039 | return dco_freq / (p0 * p1 * p2 * 5); |
981 | return dco_freq / (p0 * p1 * p2 * 5); |
1040 | } |
982 | } |
1041 | 983 | ||
1042 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
984 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
1043 | { |
985 | { |
1044 | int dotclock; |
986 | int dotclock; |
1045 | 987 | ||
1046 | if (pipe_config->has_pch_encoder) |
988 | if (pipe_config->has_pch_encoder) |
1047 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
989 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1048 | &pipe_config->fdi_m_n); |
990 | &pipe_config->fdi_m_n); |
1049 | else if (pipe_config->has_dp_encoder) |
991 | else if (pipe_config->has_dp_encoder) |
1050 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
992 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1051 | &pipe_config->dp_m_n); |
993 | &pipe_config->dp_m_n); |
1052 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) |
994 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) |
1053 | dotclock = pipe_config->port_clock * 2 / 3; |
995 | dotclock = pipe_config->port_clock * 2 / 3; |
1054 | else |
996 | else |
1055 | dotclock = pipe_config->port_clock; |
997 | dotclock = pipe_config->port_clock; |
1056 | 998 | ||
1057 | if (pipe_config->pixel_multiplier) |
999 | if (pipe_config->pixel_multiplier) |
1058 | dotclock /= pipe_config->pixel_multiplier; |
1000 | dotclock /= pipe_config->pixel_multiplier; |
1059 | 1001 | ||
1060 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
1002 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
1061 | } |
1003 | } |
1062 | 1004 | ||
1063 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
1005 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
1064 | struct intel_crtc_state *pipe_config) |
1006 | struct intel_crtc_state *pipe_config) |
1065 | { |
1007 | { |
1066 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1008 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1067 | int link_clock = 0; |
1009 | int link_clock = 0; |
1068 | uint32_t dpll_ctl1, dpll; |
1010 | uint32_t dpll_ctl1, dpll; |
1069 | 1011 | ||
1070 | dpll = pipe_config->ddi_pll_sel; |
1012 | dpll = pipe_config->ddi_pll_sel; |
1071 | 1013 | ||
1072 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
1014 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
1073 | 1015 | ||
1074 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { |
1016 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { |
1075 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); |
1017 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); |
1076 | } else { |
1018 | } else { |
1077 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
1019 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
1078 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); |
1020 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); |
1079 | 1021 | ||
1080 | switch (link_clock) { |
1022 | switch (link_clock) { |
1081 | case DPLL_CTRL1_LINK_RATE_810: |
1023 | case DPLL_CTRL1_LINK_RATE_810: |
1082 | link_clock = 81000; |
1024 | link_clock = 81000; |
1083 | break; |
1025 | break; |
1084 | case DPLL_CTRL1_LINK_RATE_1080: |
1026 | case DPLL_CTRL1_LINK_RATE_1080: |
1085 | link_clock = 108000; |
1027 | link_clock = 108000; |
1086 | break; |
1028 | break; |
1087 | case DPLL_CTRL1_LINK_RATE_1350: |
1029 | case DPLL_CTRL1_LINK_RATE_1350: |
1088 | link_clock = 135000; |
1030 | link_clock = 135000; |
1089 | break; |
1031 | break; |
1090 | case DPLL_CTRL1_LINK_RATE_1620: |
1032 | case DPLL_CTRL1_LINK_RATE_1620: |
1091 | link_clock = 162000; |
1033 | link_clock = 162000; |
1092 | break; |
1034 | break; |
1093 | case DPLL_CTRL1_LINK_RATE_2160: |
1035 | case DPLL_CTRL1_LINK_RATE_2160: |
1094 | link_clock = 216000; |
1036 | link_clock = 216000; |
1095 | break; |
1037 | break; |
1096 | case DPLL_CTRL1_LINK_RATE_2700: |
1038 | case DPLL_CTRL1_LINK_RATE_2700: |
1097 | link_clock = 270000; |
1039 | link_clock = 270000; |
1098 | break; |
1040 | break; |
1099 | default: |
1041 | default: |
1100 | WARN(1, "Unsupported link rate\n"); |
1042 | WARN(1, "Unsupported link rate\n"); |
1101 | break; |
1043 | break; |
1102 | } |
1044 | } |
1103 | link_clock *= 2; |
1045 | link_clock *= 2; |
1104 | } |
1046 | } |
1105 | 1047 | ||
1106 | pipe_config->port_clock = link_clock; |
1048 | pipe_config->port_clock = link_clock; |
1107 | 1049 | ||
1108 | ddi_dotclock_get(pipe_config); |
1050 | ddi_dotclock_get(pipe_config); |
1109 | } |
1051 | } |
1110 | 1052 | ||
1111 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
1053 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
1112 | struct intel_crtc_state *pipe_config) |
1054 | struct intel_crtc_state *pipe_config) |
1113 | { |
1055 | { |
1114 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1056 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1115 | int link_clock = 0; |
1057 | int link_clock = 0; |
1116 | u32 val, pll; |
1058 | u32 val, pll; |
1117 | 1059 | ||
1118 | val = pipe_config->ddi_pll_sel; |
1060 | val = pipe_config->ddi_pll_sel; |
1119 | switch (val & PORT_CLK_SEL_MASK) { |
1061 | switch (val & PORT_CLK_SEL_MASK) { |
1120 | case PORT_CLK_SEL_LCPLL_810: |
1062 | case PORT_CLK_SEL_LCPLL_810: |
1121 | link_clock = 81000; |
1063 | link_clock = 81000; |
1122 | break; |
1064 | break; |
1123 | case PORT_CLK_SEL_LCPLL_1350: |
1065 | case PORT_CLK_SEL_LCPLL_1350: |
1124 | link_clock = 135000; |
1066 | link_clock = 135000; |
1125 | break; |
1067 | break; |
1126 | case PORT_CLK_SEL_LCPLL_2700: |
1068 | case PORT_CLK_SEL_LCPLL_2700: |
1127 | link_clock = 270000; |
1069 | link_clock = 270000; |
1128 | break; |
1070 | break; |
1129 | case PORT_CLK_SEL_WRPLL1: |
1071 | case PORT_CLK_SEL_WRPLL1: |
1130 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
1072 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
1131 | break; |
1073 | break; |
1132 | case PORT_CLK_SEL_WRPLL2: |
1074 | case PORT_CLK_SEL_WRPLL2: |
1133 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
1075 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
1134 | break; |
1076 | break; |
1135 | case PORT_CLK_SEL_SPLL: |
1077 | case PORT_CLK_SEL_SPLL: |
1136 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; |
1078 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; |
1137 | if (pll == SPLL_PLL_FREQ_810MHz) |
1079 | if (pll == SPLL_PLL_FREQ_810MHz) |
1138 | link_clock = 81000; |
1080 | link_clock = 81000; |
1139 | else if (pll == SPLL_PLL_FREQ_1350MHz) |
1081 | else if (pll == SPLL_PLL_FREQ_1350MHz) |
1140 | link_clock = 135000; |
1082 | link_clock = 135000; |
1141 | else if (pll == SPLL_PLL_FREQ_2700MHz) |
1083 | else if (pll == SPLL_PLL_FREQ_2700MHz) |
1142 | link_clock = 270000; |
1084 | link_clock = 270000; |
1143 | else { |
1085 | else { |
1144 | WARN(1, "bad spll freq\n"); |
1086 | WARN(1, "bad spll freq\n"); |
1145 | return; |
1087 | return; |
1146 | } |
1088 | } |
1147 | break; |
1089 | break; |
1148 | default: |
1090 | default: |
1149 | WARN(1, "bad port clock sel\n"); |
1091 | WARN(1, "bad port clock sel\n"); |
1150 | return; |
1092 | return; |
1151 | } |
1093 | } |
1152 | 1094 | ||
1153 | pipe_config->port_clock = link_clock * 2; |
1095 | pipe_config->port_clock = link_clock * 2; |
1154 | 1096 | ||
1155 | ddi_dotclock_get(pipe_config); |
1097 | ddi_dotclock_get(pipe_config); |
1156 | } |
1098 | } |
1157 | 1099 | ||
1158 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
1100 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
1159 | enum intel_dpll_id dpll) |
1101 | enum intel_dpll_id dpll) |
1160 | { |
1102 | { |
1161 | struct intel_shared_dpll *pll; |
1103 | struct intel_shared_dpll *pll; |
1162 | struct intel_dpll_hw_state *state; |
1104 | struct intel_dpll_hw_state *state; |
1163 | intel_clock_t clock; |
1105 | intel_clock_t clock; |
1164 | 1106 | ||
1165 | /* For DDI ports we always use a shared PLL. */ |
1107 | /* For DDI ports we always use a shared PLL. */ |
1166 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) |
1108 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) |
1167 | return 0; |
1109 | return 0; |
1168 | 1110 | ||
1169 | pll = &dev_priv->shared_dplls[dpll]; |
1111 | pll = &dev_priv->shared_dplls[dpll]; |
1170 | state = &pll->config.hw_state; |
1112 | state = &pll->config.hw_state; |
1171 | 1113 | ||
1172 | clock.m1 = 2; |
1114 | clock.m1 = 2; |
1173 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; |
1115 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; |
1174 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) |
1116 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) |
1175 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; |
1117 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; |
1176 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; |
1118 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; |
1177 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; |
1119 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; |
1178 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; |
1120 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; |
1179 | 1121 | ||
1180 | return chv_calc_dpll_params(100000, &clock); |
1122 | return chv_calc_dpll_params(100000, &clock); |
1181 | } |
1123 | } |
1182 | 1124 | ||
1183 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, |
1125 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, |
1184 | struct intel_crtc_state *pipe_config) |
1126 | struct intel_crtc_state *pipe_config) |
1185 | { |
1127 | { |
1186 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1128 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1187 | enum port port = intel_ddi_get_encoder_port(encoder); |
1129 | enum port port = intel_ddi_get_encoder_port(encoder); |
1188 | uint32_t dpll = port; |
1130 | uint32_t dpll = port; |
1189 | 1131 | ||
1190 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
1132 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
1191 | 1133 | ||
1192 | ddi_dotclock_get(pipe_config); |
1134 | ddi_dotclock_get(pipe_config); |
1193 | } |
1135 | } |
1194 | 1136 | ||
1195 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
1137 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
1196 | struct intel_crtc_state *pipe_config) |
1138 | struct intel_crtc_state *pipe_config) |
1197 | { |
1139 | { |
1198 | struct drm_device *dev = encoder->base.dev; |
1140 | struct drm_device *dev = encoder->base.dev; |
1199 | 1141 | ||
1200 | if (INTEL_INFO(dev)->gen <= 8) |
1142 | if (INTEL_INFO(dev)->gen <= 8) |
1201 | hsw_ddi_clock_get(encoder, pipe_config); |
1143 | hsw_ddi_clock_get(encoder, pipe_config); |
1202 | else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1144 | else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1203 | skl_ddi_clock_get(encoder, pipe_config); |
1145 | skl_ddi_clock_get(encoder, pipe_config); |
1204 | else if (IS_BROXTON(dev)) |
1146 | else if (IS_BROXTON(dev)) |
1205 | bxt_ddi_clock_get(encoder, pipe_config); |
1147 | bxt_ddi_clock_get(encoder, pipe_config); |
1206 | } |
1148 | } |
1207 | 1149 | ||
1208 | static void |
1150 | static void |
1209 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
1151 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
1210 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) |
1152 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) |
1211 | { |
1153 | { |
1212 | uint64_t freq2k; |
1154 | uint64_t freq2k; |
1213 | unsigned p, n2, r2; |
1155 | unsigned p, n2, r2; |
1214 | struct hsw_wrpll_rnp best = { 0, 0, 0 }; |
1156 | struct hsw_wrpll_rnp best = { 0, 0, 0 }; |
1215 | unsigned budget; |
1157 | unsigned budget; |
1216 | 1158 | ||
1217 | freq2k = clock / 100; |
1159 | freq2k = clock / 100; |
1218 | 1160 | ||
1219 | budget = hsw_wrpll_get_budget_for_freq(clock); |
1161 | budget = hsw_wrpll_get_budget_for_freq(clock); |
1220 | 1162 | ||
1221 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely |
1163 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely |
1222 | * and directly pass the LC PLL to it. */ |
1164 | * and directly pass the LC PLL to it. */ |
1223 | if (freq2k == 5400000) { |
1165 | if (freq2k == 5400000) { |
1224 | *n2_out = 2; |
1166 | *n2_out = 2; |
1225 | *p_out = 1; |
1167 | *p_out = 1; |
1226 | *r2_out = 2; |
1168 | *r2_out = 2; |
1227 | return; |
1169 | return; |
1228 | } |
1170 | } |
1229 | 1171 | ||
1230 | /* |
1172 | /* |
1231 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by |
1173 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by |
1232 | * the WR PLL. |
1174 | * the WR PLL. |
1233 | * |
1175 | * |
1234 | * We want R so that REF_MIN <= Ref <= REF_MAX. |
1176 | * We want R so that REF_MIN <= Ref <= REF_MAX. |
1235 | * Injecting R2 = 2 * R gives: |
1177 | * Injecting R2 = 2 * R gives: |
1236 | * REF_MAX * r2 > LC_FREQ * 2 and |
1178 | * REF_MAX * r2 > LC_FREQ * 2 and |
1237 | * REF_MIN * r2 < LC_FREQ * 2 |
1179 | * REF_MIN * r2 < LC_FREQ * 2 |
1238 | * |
1180 | * |
1239 | * Which means the desired boundaries for r2 are: |
1181 | * Which means the desired boundaries for r2 are: |
1240 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN |
1182 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN |
1241 | * |
1183 | * |
1242 | */ |
1184 | */ |
1243 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; |
1185 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; |
1244 | r2 <= LC_FREQ * 2 / REF_MIN; |
1186 | r2 <= LC_FREQ * 2 / REF_MIN; |
1245 | r2++) { |
1187 | r2++) { |
1246 | 1188 | ||
1247 | /* |
1189 | /* |
1248 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R |
1190 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R |
1249 | * |
1191 | * |
1250 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. |
1192 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. |
1251 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: |
1193 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: |
1252 | * VCO_MAX * r2 > n2 * LC_FREQ and |
1194 | * VCO_MAX * r2 > n2 * LC_FREQ and |
1253 | * VCO_MIN * r2 < n2 * LC_FREQ) |
1195 | * VCO_MIN * r2 < n2 * LC_FREQ) |
1254 | * |
1196 | * |
1255 | * Which means the desired boundaries for n2 are: |
1197 | * Which means the desired boundaries for n2 are: |
1256 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ |
1198 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ |
1257 | */ |
1199 | */ |
1258 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; |
1200 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; |
1259 | n2 <= VCO_MAX * r2 / LC_FREQ; |
1201 | n2 <= VCO_MAX * r2 / LC_FREQ; |
1260 | n2++) { |
1202 | n2++) { |
1261 | 1203 | ||
1262 | for (p = P_MIN; p <= P_MAX; p += P_INC) |
1204 | for (p = P_MIN; p <= P_MAX; p += P_INC) |
1263 | hsw_wrpll_update_rnp(freq2k, budget, |
1205 | hsw_wrpll_update_rnp(freq2k, budget, |
1264 | r2, n2, p, &best); |
1206 | r2, n2, p, &best); |
1265 | } |
1207 | } |
1266 | } |
1208 | } |
1267 | 1209 | ||
1268 | *n2_out = best.n2; |
1210 | *n2_out = best.n2; |
1269 | *p_out = best.p; |
1211 | *p_out = best.p; |
1270 | *r2_out = best.r2; |
1212 | *r2_out = best.r2; |
1271 | } |
1213 | } |
1272 | 1214 | ||
1273 | static bool |
1215 | static bool |
1274 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
1216 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
1275 | struct intel_crtc_state *crtc_state, |
1217 | struct intel_crtc_state *crtc_state, |
1276 | struct intel_encoder *intel_encoder) |
1218 | struct intel_encoder *intel_encoder) |
1277 | { |
1219 | { |
1278 | int clock = crtc_state->port_clock; |
1220 | int clock = crtc_state->port_clock; |
1279 | 1221 | ||
1280 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1222 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1281 | struct intel_shared_dpll *pll; |
1223 | struct intel_shared_dpll *pll; |
1282 | uint32_t val; |
1224 | uint32_t val; |
1283 | unsigned p, n2, r2; |
1225 | unsigned p, n2, r2; |
1284 | 1226 | ||
1285 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
1227 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
1286 | 1228 | ||
1287 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
1229 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
1288 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
1230 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
1289 | WRPLL_DIVIDER_POST(p); |
1231 | WRPLL_DIVIDER_POST(p); |
1290 | 1232 | ||
1291 | memset(&crtc_state->dpll_hw_state, 0, |
1233 | memset(&crtc_state->dpll_hw_state, 0, |
1292 | sizeof(crtc_state->dpll_hw_state)); |
1234 | sizeof(crtc_state->dpll_hw_state)); |
1293 | 1235 | ||
1294 | crtc_state->dpll_hw_state.wrpll = val; |
1236 | crtc_state->dpll_hw_state.wrpll = val; |
1295 | 1237 | ||
1296 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1238 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1297 | if (pll == NULL) { |
1239 | if (pll == NULL) { |
1298 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1240 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1299 | pipe_name(intel_crtc->pipe)); |
1241 | pipe_name(intel_crtc->pipe)); |
1300 | return false; |
1242 | return false; |
1301 | } |
1243 | } |
1302 | 1244 | ||
1303 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
1245 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
1304 | } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { |
1246 | } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { |
1305 | struct drm_atomic_state *state = crtc_state->base.state; |
1247 | struct drm_atomic_state *state = crtc_state->base.state; |
1306 | struct intel_shared_dpll_config *spll = |
1248 | struct intel_shared_dpll_config *spll = |
1307 | &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; |
1249 | &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; |
1308 | 1250 | ||
1309 | if (spll->crtc_mask && |
1251 | if (spll->crtc_mask && |
1310 | WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) |
1252 | WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) |
1311 | return false; |
1253 | return false; |
1312 | 1254 | ||
1313 | crtc_state->shared_dpll = DPLL_ID_SPLL; |
1255 | crtc_state->shared_dpll = DPLL_ID_SPLL; |
1314 | spll->hw_state.spll = crtc_state->dpll_hw_state.spll; |
1256 | spll->hw_state.spll = crtc_state->dpll_hw_state.spll; |
1315 | spll->crtc_mask |= 1 << intel_crtc->pipe; |
1257 | spll->crtc_mask |= 1 << intel_crtc->pipe; |
1316 | } |
1258 | } |
1317 | 1259 | ||
1318 | return true; |
1260 | return true; |
1319 | } |
1261 | } |
1320 | 1262 | ||
1321 | struct skl_wrpll_context { |
1263 | struct skl_wrpll_context { |
1322 | uint64_t min_deviation; /* current minimal deviation */ |
1264 | uint64_t min_deviation; /* current minimal deviation */ |
1323 | uint64_t central_freq; /* chosen central freq */ |
1265 | uint64_t central_freq; /* chosen central freq */ |
1324 | uint64_t dco_freq; /* chosen dco freq */ |
1266 | uint64_t dco_freq; /* chosen dco freq */ |
1325 | unsigned int p; /* chosen divider */ |
1267 | unsigned int p; /* chosen divider */ |
1326 | }; |
1268 | }; |
1327 | 1269 | ||
1328 | static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) |
1270 | static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) |
1329 | { |
1271 | { |
1330 | memset(ctx, 0, sizeof(*ctx)); |
1272 | memset(ctx, 0, sizeof(*ctx)); |
1331 | 1273 | ||
1332 | ctx->min_deviation = U64_MAX; |
1274 | ctx->min_deviation = U64_MAX; |
1333 | } |
1275 | } |
1334 | 1276 | ||
1335 | /* DCO freq must be within +1%/-6% of the DCO central freq */ |
1277 | /* DCO freq must be within +1%/-6% of the DCO central freq */ |
1336 | #define SKL_DCO_MAX_PDEVIATION 100 |
1278 | #define SKL_DCO_MAX_PDEVIATION 100 |
1337 | #define SKL_DCO_MAX_NDEVIATION 600 |
1279 | #define SKL_DCO_MAX_NDEVIATION 600 |
1338 | 1280 | ||
1339 | static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, |
1281 | static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, |
1340 | uint64_t central_freq, |
1282 | uint64_t central_freq, |
1341 | uint64_t dco_freq, |
1283 | uint64_t dco_freq, |
1342 | unsigned int divider) |
1284 | unsigned int divider) |
1343 | { |
1285 | { |
1344 | uint64_t deviation; |
1286 | uint64_t deviation; |
1345 | 1287 | ||
1346 | deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), |
1288 | deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), |
1347 | central_freq); |
1289 | central_freq); |
1348 | 1290 | ||
1349 | /* positive deviation */ |
1291 | /* positive deviation */ |
1350 | if (dco_freq >= central_freq) { |
1292 | if (dco_freq >= central_freq) { |
1351 | if (deviation < SKL_DCO_MAX_PDEVIATION && |
1293 | if (deviation < SKL_DCO_MAX_PDEVIATION && |
1352 | deviation < ctx->min_deviation) { |
1294 | deviation < ctx->min_deviation) { |
1353 | ctx->min_deviation = deviation; |
1295 | ctx->min_deviation = deviation; |
1354 | ctx->central_freq = central_freq; |
1296 | ctx->central_freq = central_freq; |
1355 | ctx->dco_freq = dco_freq; |
1297 | ctx->dco_freq = dco_freq; |
1356 | ctx->p = divider; |
1298 | ctx->p = divider; |
1357 | } |
1299 | } |
1358 | /* negative deviation */ |
1300 | /* negative deviation */ |
1359 | } else if (deviation < SKL_DCO_MAX_NDEVIATION && |
1301 | } else if (deviation < SKL_DCO_MAX_NDEVIATION && |
1360 | deviation < ctx->min_deviation) { |
1302 | deviation < ctx->min_deviation) { |
1361 | ctx->min_deviation = deviation; |
1303 | ctx->min_deviation = deviation; |
1362 | ctx->central_freq = central_freq; |
1304 | ctx->central_freq = central_freq; |
1363 | ctx->dco_freq = dco_freq; |
1305 | ctx->dco_freq = dco_freq; |
1364 | ctx->p = divider; |
1306 | ctx->p = divider; |
1365 | } |
1307 | } |
1366 | } |
1308 | } |
1367 | 1309 | ||
1368 | static void skl_wrpll_get_multipliers(unsigned int p, |
1310 | static void skl_wrpll_get_multipliers(unsigned int p, |
1369 | unsigned int *p0 /* out */, |
1311 | unsigned int *p0 /* out */, |
1370 | unsigned int *p1 /* out */, |
1312 | unsigned int *p1 /* out */, |
1371 | unsigned int *p2 /* out */) |
1313 | unsigned int *p2 /* out */) |
1372 | { |
1314 | { |
1373 | /* even dividers */ |
1315 | /* even dividers */ |
1374 | if (p % 2 == 0) { |
1316 | if (p % 2 == 0) { |
1375 | unsigned int half = p / 2; |
1317 | unsigned int half = p / 2; |
1376 | 1318 | ||
1377 | if (half == 1 || half == 2 || half == 3 || half == 5) { |
1319 | if (half == 1 || half == 2 || half == 3 || half == 5) { |
1378 | *p0 = 2; |
1320 | *p0 = 2; |
1379 | *p1 = 1; |
1321 | *p1 = 1; |
1380 | *p2 = half; |
1322 | *p2 = half; |
1381 | } else if (half % 2 == 0) { |
1323 | } else if (half % 2 == 0) { |
1382 | *p0 = 2; |
1324 | *p0 = 2; |
1383 | *p1 = half / 2; |
1325 | *p1 = half / 2; |
1384 | *p2 = 2; |
1326 | *p2 = 2; |
1385 | } else if (half % 3 == 0) { |
1327 | } else if (half % 3 == 0) { |
1386 | *p0 = 3; |
1328 | *p0 = 3; |
1387 | *p1 = half / 3; |
1329 | *p1 = half / 3; |
1388 | *p2 = 2; |
1330 | *p2 = 2; |
1389 | } else if (half % 7 == 0) { |
1331 | } else if (half % 7 == 0) { |
1390 | *p0 = 7; |
1332 | *p0 = 7; |
1391 | *p1 = half / 7; |
1333 | *p1 = half / 7; |
1392 | *p2 = 2; |
1334 | *p2 = 2; |
1393 | } |
1335 | } |
1394 | } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ |
1336 | } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ |
1395 | *p0 = 3; |
1337 | *p0 = 3; |
1396 | *p1 = 1; |
1338 | *p1 = 1; |
1397 | *p2 = p / 3; |
1339 | *p2 = p / 3; |
1398 | } else if (p == 5 || p == 7) { |
1340 | } else if (p == 5 || p == 7) { |
1399 | *p0 = p; |
1341 | *p0 = p; |
1400 | *p1 = 1; |
1342 | *p1 = 1; |
1401 | *p2 = 1; |
1343 | *p2 = 1; |
1402 | } else if (p == 15) { |
1344 | } else if (p == 15) { |
1403 | *p0 = 3; |
1345 | *p0 = 3; |
1404 | *p1 = 1; |
1346 | *p1 = 1; |
1405 | *p2 = 5; |
1347 | *p2 = 5; |
1406 | } else if (p == 21) { |
1348 | } else if (p == 21) { |
1407 | *p0 = 7; |
1349 | *p0 = 7; |
1408 | *p1 = 1; |
1350 | *p1 = 1; |
1409 | *p2 = 3; |
1351 | *p2 = 3; |
1410 | } else if (p == 35) { |
1352 | } else if (p == 35) { |
1411 | *p0 = 7; |
1353 | *p0 = 7; |
1412 | *p1 = 1; |
1354 | *p1 = 1; |
1413 | *p2 = 5; |
1355 | *p2 = 5; |
1414 | } |
1356 | } |
1415 | } |
1357 | } |
1416 | 1358 | ||
1417 | struct skl_wrpll_params { |
1359 | struct skl_wrpll_params { |
1418 | uint32_t dco_fraction; |
1360 | uint32_t dco_fraction; |
1419 | uint32_t dco_integer; |
1361 | uint32_t dco_integer; |
1420 | uint32_t qdiv_ratio; |
1362 | uint32_t qdiv_ratio; |
1421 | uint32_t qdiv_mode; |
1363 | uint32_t qdiv_mode; |
1422 | uint32_t kdiv; |
1364 | uint32_t kdiv; |
1423 | uint32_t pdiv; |
1365 | uint32_t pdiv; |
1424 | uint32_t central_freq; |
1366 | uint32_t central_freq; |
1425 | }; |
1367 | }; |
1426 | 1368 | ||
1427 | static void skl_wrpll_params_populate(struct skl_wrpll_params *params, |
1369 | static void skl_wrpll_params_populate(struct skl_wrpll_params *params, |
1428 | uint64_t afe_clock, |
1370 | uint64_t afe_clock, |
1429 | uint64_t central_freq, |
1371 | uint64_t central_freq, |
1430 | uint32_t p0, uint32_t p1, uint32_t p2) |
1372 | uint32_t p0, uint32_t p1, uint32_t p2) |
1431 | { |
1373 | { |
1432 | uint64_t dco_freq; |
1374 | uint64_t dco_freq; |
1433 | 1375 | ||
1434 | switch (central_freq) { |
1376 | switch (central_freq) { |
1435 | case 9600000000ULL: |
1377 | case 9600000000ULL: |
1436 | params->central_freq = 0; |
1378 | params->central_freq = 0; |
1437 | break; |
1379 | break; |
1438 | case 9000000000ULL: |
1380 | case 9000000000ULL: |
1439 | params->central_freq = 1; |
1381 | params->central_freq = 1; |
1440 | break; |
1382 | break; |
1441 | case 8400000000ULL: |
1383 | case 8400000000ULL: |
1442 | params->central_freq = 3; |
1384 | params->central_freq = 3; |
1443 | } |
1385 | } |
1444 | 1386 | ||
1445 | switch (p0) { |
1387 | switch (p0) { |
1446 | case 1: |
1388 | case 1: |
1447 | params->pdiv = 0; |
1389 | params->pdiv = 0; |
1448 | break; |
1390 | break; |
1449 | case 2: |
1391 | case 2: |
1450 | params->pdiv = 1; |
1392 | params->pdiv = 1; |
1451 | break; |
1393 | break; |
1452 | case 3: |
1394 | case 3: |
1453 | params->pdiv = 2; |
1395 | params->pdiv = 2; |
1454 | break; |
1396 | break; |
1455 | case 7: |
1397 | case 7: |
1456 | params->pdiv = 4; |
1398 | params->pdiv = 4; |
1457 | break; |
1399 | break; |
1458 | default: |
1400 | default: |
1459 | WARN(1, "Incorrect PDiv\n"); |
1401 | WARN(1, "Incorrect PDiv\n"); |
1460 | } |
1402 | } |
1461 | 1403 | ||
1462 | switch (p2) { |
1404 | switch (p2) { |
1463 | case 5: |
1405 | case 5: |
1464 | params->kdiv = 0; |
1406 | params->kdiv = 0; |
1465 | break; |
1407 | break; |
1466 | case 2: |
1408 | case 2: |
1467 | params->kdiv = 1; |
1409 | params->kdiv = 1; |
1468 | break; |
1410 | break; |
1469 | case 3: |
1411 | case 3: |
1470 | params->kdiv = 2; |
1412 | params->kdiv = 2; |
1471 | break; |
1413 | break; |
1472 | case 1: |
1414 | case 1: |
1473 | params->kdiv = 3; |
1415 | params->kdiv = 3; |
1474 | break; |
1416 | break; |
1475 | default: |
1417 | default: |
1476 | WARN(1, "Incorrect KDiv\n"); |
1418 | WARN(1, "Incorrect KDiv\n"); |
1477 | } |
1419 | } |
1478 | 1420 | ||
1479 | params->qdiv_ratio = p1; |
1421 | params->qdiv_ratio = p1; |
1480 | params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; |
1422 | params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; |
1481 | 1423 | ||
1482 | dco_freq = p0 * p1 * p2 * afe_clock; |
1424 | dco_freq = p0 * p1 * p2 * afe_clock; |
1483 | 1425 | ||
1484 | /* |
1426 | /* |
1485 | * Intermediate values are in Hz. |
1427 | * Intermediate values are in Hz. |
1486 | * Divide by MHz to match bsepc |
1428 | * Divide by MHz to match bsepc |
1487 | */ |
1429 | */ |
1488 | params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); |
1430 | params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); |
1489 | params->dco_fraction = |
1431 | params->dco_fraction = |
1490 | div_u64((div_u64(dco_freq, 24) - |
1432 | div_u64((div_u64(dco_freq, 24) - |
1491 | params->dco_integer * MHz(1)) * 0x8000, MHz(1)); |
1433 | params->dco_integer * MHz(1)) * 0x8000, MHz(1)); |
1492 | } |
1434 | } |
1493 | 1435 | ||
1494 | static bool |
1436 | static bool |
1495 | skl_ddi_calculate_wrpll(int clock /* in Hz */, |
1437 | skl_ddi_calculate_wrpll(int clock /* in Hz */, |
1496 | struct skl_wrpll_params *wrpll_params) |
1438 | struct skl_wrpll_params *wrpll_params) |
1497 | { |
1439 | { |
1498 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ |
1440 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ |
1499 | uint64_t dco_central_freq[3] = {8400000000ULL, |
1441 | uint64_t dco_central_freq[3] = {8400000000ULL, |
1500 | 9000000000ULL, |
1442 | 9000000000ULL, |
1501 | 9600000000ULL}; |
1443 | 9600000000ULL}; |
1502 | static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, |
1444 | static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, |
1503 | 24, 28, 30, 32, 36, 40, 42, 44, |
1445 | 24, 28, 30, 32, 36, 40, 42, 44, |
1504 | 48, 52, 54, 56, 60, 64, 66, 68, |
1446 | 48, 52, 54, 56, 60, 64, 66, 68, |
1505 | 70, 72, 76, 78, 80, 84, 88, 90, |
1447 | 70, 72, 76, 78, 80, 84, 88, 90, |
1506 | 92, 96, 98 }; |
1448 | 92, 96, 98 }; |
1507 | static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; |
1449 | static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; |
1508 | static const struct { |
1450 | static const struct { |
1509 | const int *list; |
1451 | const int *list; |
1510 | int n_dividers; |
1452 | int n_dividers; |
1511 | } dividers[] = { |
1453 | } dividers[] = { |
1512 | { even_dividers, ARRAY_SIZE(even_dividers) }, |
1454 | { even_dividers, ARRAY_SIZE(even_dividers) }, |
1513 | { odd_dividers, ARRAY_SIZE(odd_dividers) }, |
1455 | { odd_dividers, ARRAY_SIZE(odd_dividers) }, |
1514 | }; |
1456 | }; |
1515 | struct skl_wrpll_context ctx; |
1457 | struct skl_wrpll_context ctx; |
1516 | unsigned int dco, d, i; |
1458 | unsigned int dco, d, i; |
1517 | unsigned int p0, p1, p2; |
1459 | unsigned int p0, p1, p2; |
1518 | 1460 | ||
1519 | skl_wrpll_context_init(&ctx); |
1461 | skl_wrpll_context_init(&ctx); |
1520 | 1462 | ||
1521 | for (d = 0; d < ARRAY_SIZE(dividers); d++) { |
1463 | for (d = 0; d < ARRAY_SIZE(dividers); d++) { |
1522 | for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { |
1464 | for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { |
1523 | for (i = 0; i < dividers[d].n_dividers; i++) { |
1465 | for (i = 0; i < dividers[d].n_dividers; i++) { |
1524 | unsigned int p = dividers[d].list[i]; |
1466 | unsigned int p = dividers[d].list[i]; |
1525 | uint64_t dco_freq = p * afe_clock; |
1467 | uint64_t dco_freq = p * afe_clock; |
1526 | 1468 | ||
1527 | skl_wrpll_try_divider(&ctx, |
1469 | skl_wrpll_try_divider(&ctx, |
1528 | dco_central_freq[dco], |
1470 | dco_central_freq[dco], |
1529 | dco_freq, |
1471 | dco_freq, |
1530 | p); |
1472 | p); |
1531 | /* |
1473 | /* |
1532 | * Skip the remaining dividers if we're sure to |
1474 | * Skip the remaining dividers if we're sure to |
1533 | * have found the definitive divider, we can't |
1475 | * have found the definitive divider, we can't |
1534 | * improve a 0 deviation. |
1476 | * improve a 0 deviation. |
1535 | */ |
1477 | */ |
1536 | if (ctx.min_deviation == 0) |
1478 | if (ctx.min_deviation == 0) |
1537 | goto skip_remaining_dividers; |
1479 | goto skip_remaining_dividers; |
1538 | } |
1480 | } |
1539 | } |
1481 | } |
1540 | 1482 | ||
1541 | skip_remaining_dividers: |
1483 | skip_remaining_dividers: |
1542 | /* |
1484 | /* |
1543 | * If a solution is found with an even divider, prefer |
1485 | * If a solution is found with an even divider, prefer |
1544 | * this one. |
1486 | * this one. |
1545 | */ |
1487 | */ |
1546 | if (d == 0 && ctx.p) |
1488 | if (d == 0 && ctx.p) |
1547 | break; |
1489 | break; |
1548 | } |
1490 | } |
1549 | 1491 | ||
1550 | if (!ctx.p) { |
1492 | if (!ctx.p) { |
1551 | DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); |
1493 | DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); |
1552 | return false; |
1494 | return false; |
1553 | } |
1495 | } |
1554 | 1496 | ||
1555 | /* |
1497 | /* |
1556 | * gcc incorrectly analyses that these can be used without being |
1498 | * gcc incorrectly analyses that these can be used without being |
1557 | * initialized. To be fair, it's hard to guess. |
1499 | * initialized. To be fair, it's hard to guess. |
1558 | */ |
1500 | */ |
1559 | p0 = p1 = p2 = 0; |
1501 | p0 = p1 = p2 = 0; |
1560 | skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); |
1502 | skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); |
1561 | skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, |
1503 | skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, |
1562 | p0, p1, p2); |
1504 | p0, p1, p2); |
1563 | 1505 | ||
1564 | return true; |
1506 | return true; |
1565 | } |
1507 | } |
1566 | 1508 | ||
1567 | static bool |
1509 | static bool |
1568 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, |
1510 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, |
1569 | struct intel_crtc_state *crtc_state, |
1511 | struct intel_crtc_state *crtc_state, |
1570 | struct intel_encoder *intel_encoder) |
1512 | struct intel_encoder *intel_encoder) |
1571 | { |
1513 | { |
1572 | struct intel_shared_dpll *pll; |
1514 | struct intel_shared_dpll *pll; |
1573 | uint32_t ctrl1, cfgcr1, cfgcr2; |
1515 | uint32_t ctrl1, cfgcr1, cfgcr2; |
1574 | int clock = crtc_state->port_clock; |
1516 | int clock = crtc_state->port_clock; |
1575 | 1517 | ||
1576 | /* |
1518 | /* |
1577 | * See comment in intel_dpll_hw_state to understand why we always use 0 |
1519 | * See comment in intel_dpll_hw_state to understand why we always use 0 |
1578 | * as the DPLL id in this function. |
1520 | * as the DPLL id in this function. |
1579 | */ |
1521 | */ |
1580 | 1522 | ||
1581 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); |
1523 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); |
1582 | 1524 | ||
1583 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1525 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1584 | struct skl_wrpll_params wrpll_params = { 0, }; |
1526 | struct skl_wrpll_params wrpll_params = { 0, }; |
1585 | 1527 | ||
1586 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); |
1528 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); |
1587 | 1529 | ||
1588 | if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) |
1530 | if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) |
1589 | return false; |
1531 | return false; |
1590 | 1532 | ||
1591 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | |
1533 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | |
1592 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | |
1534 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | |
1593 | wrpll_params.dco_integer; |
1535 | wrpll_params.dco_integer; |
1594 | 1536 | ||
1595 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | |
1537 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | |
1596 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | |
1538 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | |
1597 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | |
1539 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | |
1598 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | |
1540 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | |
1599 | wrpll_params.central_freq; |
1541 | wrpll_params.central_freq; |
1600 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1542 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1601 | intel_encoder->type == INTEL_OUTPUT_DP_MST) { |
1543 | intel_encoder->type == INTEL_OUTPUT_DP_MST) { |
1602 | switch (crtc_state->port_clock / 2) { |
1544 | switch (crtc_state->port_clock / 2) { |
1603 | case 81000: |
1545 | case 81000: |
1604 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); |
1546 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); |
1605 | break; |
1547 | break; |
1606 | case 135000: |
1548 | case 135000: |
1607 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); |
1549 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); |
1608 | break; |
1550 | break; |
1609 | case 270000: |
1551 | case 270000: |
1610 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
1552 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
1611 | break; |
1553 | break; |
1612 | } |
1554 | } |
1613 | 1555 | ||
1614 | cfgcr1 = cfgcr2 = 0; |
1556 | cfgcr1 = cfgcr2 = 0; |
1615 | } else /* eDP */ |
1557 | } else if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
1616 | return true; |
1558 | return true; |
- | 1559 | } else |
|
- | 1560 | return false; |
|
1617 | 1561 | ||
1618 | memset(&crtc_state->dpll_hw_state, 0, |
1562 | memset(&crtc_state->dpll_hw_state, 0, |
1619 | sizeof(crtc_state->dpll_hw_state)); |
1563 | sizeof(crtc_state->dpll_hw_state)); |
1620 | 1564 | ||
1621 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
1565 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
1622 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; |
1566 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; |
1623 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; |
1567 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; |
1624 | 1568 | ||
1625 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1569 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1626 | if (pll == NULL) { |
1570 | if (pll == NULL) { |
1627 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1571 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1628 | pipe_name(intel_crtc->pipe)); |
1572 | pipe_name(intel_crtc->pipe)); |
1629 | return false; |
1573 | return false; |
1630 | } |
1574 | } |
1631 | 1575 | ||
1632 | /* shared DPLL id 0 is DPLL 1 */ |
1576 | /* shared DPLL id 0 is DPLL 1 */ |
1633 | crtc_state->ddi_pll_sel = pll->id + 1; |
1577 | crtc_state->ddi_pll_sel = pll->id + 1; |
1634 | 1578 | ||
1635 | return true; |
1579 | return true; |
1636 | } |
1580 | } |
1637 | 1581 | ||
1638 | /* bxt clock parameters */ |
1582 | /* bxt clock parameters */ |
1639 | struct bxt_clk_div { |
1583 | struct bxt_clk_div { |
1640 | int clock; |
1584 | int clock; |
1641 | uint32_t p1; |
1585 | uint32_t p1; |
1642 | uint32_t p2; |
1586 | uint32_t p2; |
1643 | uint32_t m2_int; |
1587 | uint32_t m2_int; |
1644 | uint32_t m2_frac; |
1588 | uint32_t m2_frac; |
1645 | bool m2_frac_en; |
1589 | bool m2_frac_en; |
1646 | uint32_t n; |
1590 | uint32_t n; |
1647 | }; |
1591 | }; |
1648 | 1592 | ||
1649 | /* pre-calculated values for DP linkrates */ |
1593 | /* pre-calculated values for DP linkrates */ |
1650 | static const struct bxt_clk_div bxt_dp_clk_val[] = { |
1594 | static const struct bxt_clk_div bxt_dp_clk_val[] = { |
1651 | {162000, 4, 2, 32, 1677722, 1, 1}, |
1595 | {162000, 4, 2, 32, 1677722, 1, 1}, |
1652 | {270000, 4, 1, 27, 0, 0, 1}, |
1596 | {270000, 4, 1, 27, 0, 0, 1}, |
1653 | {540000, 2, 1, 27, 0, 0, 1}, |
1597 | {540000, 2, 1, 27, 0, 0, 1}, |
1654 | {216000, 3, 2, 32, 1677722, 1, 1}, |
1598 | {216000, 3, 2, 32, 1677722, 1, 1}, |
1655 | {243000, 4, 1, 24, 1258291, 1, 1}, |
1599 | {243000, 4, 1, 24, 1258291, 1, 1}, |
1656 | {324000, 4, 1, 32, 1677722, 1, 1}, |
1600 | {324000, 4, 1, 32, 1677722, 1, 1}, |
1657 | {432000, 3, 1, 32, 1677722, 1, 1} |
1601 | {432000, 3, 1, 32, 1677722, 1, 1} |
1658 | }; |
1602 | }; |
1659 | 1603 | ||
1660 | static bool |
1604 | static bool |
1661 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, |
1605 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, |
1662 | struct intel_crtc_state *crtc_state, |
1606 | struct intel_crtc_state *crtc_state, |
1663 | struct intel_encoder *intel_encoder) |
1607 | struct intel_encoder *intel_encoder) |
1664 | { |
1608 | { |
1665 | struct intel_shared_dpll *pll; |
1609 | struct intel_shared_dpll *pll; |
1666 | struct bxt_clk_div clk_div = {0}; |
1610 | struct bxt_clk_div clk_div = {0}; |
1667 | int vco = 0; |
1611 | int vco = 0; |
1668 | uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; |
1612 | uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; |
1669 | uint32_t lanestagger; |
1613 | uint32_t lanestagger; |
1670 | int clock = crtc_state->port_clock; |
1614 | int clock = crtc_state->port_clock; |
1671 | 1615 | ||
1672 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1616 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
1673 | intel_clock_t best_clock; |
1617 | intel_clock_t best_clock; |
1674 | 1618 | ||
1675 | /* Calculate HDMI div */ |
1619 | /* Calculate HDMI div */ |
1676 | /* |
1620 | /* |
1677 | * FIXME: tie the following calculation into |
1621 | * FIXME: tie the following calculation into |
1678 | * i9xx_crtc_compute_clock |
1622 | * i9xx_crtc_compute_clock |
1679 | */ |
1623 | */ |
1680 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { |
1624 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { |
1681 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", |
1625 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", |
1682 | clock, pipe_name(intel_crtc->pipe)); |
1626 | clock, pipe_name(intel_crtc->pipe)); |
1683 | return false; |
1627 | return false; |
1684 | } |
1628 | } |
1685 | 1629 | ||
1686 | clk_div.p1 = best_clock.p1; |
1630 | clk_div.p1 = best_clock.p1; |
1687 | clk_div.p2 = best_clock.p2; |
1631 | clk_div.p2 = best_clock.p2; |
1688 | WARN_ON(best_clock.m1 != 2); |
1632 | WARN_ON(best_clock.m1 != 2); |
1689 | clk_div.n = best_clock.n; |
1633 | clk_div.n = best_clock.n; |
1690 | clk_div.m2_int = best_clock.m2 >> 22; |
1634 | clk_div.m2_int = best_clock.m2 >> 22; |
1691 | clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); |
1635 | clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); |
1692 | clk_div.m2_frac_en = clk_div.m2_frac != 0; |
1636 | clk_div.m2_frac_en = clk_div.m2_frac != 0; |
1693 | 1637 | ||
1694 | vco = best_clock.vco; |
1638 | vco = best_clock.vco; |
1695 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1639 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1696 | intel_encoder->type == INTEL_OUTPUT_EDP) { |
1640 | intel_encoder->type == INTEL_OUTPUT_EDP) { |
1697 | int i; |
1641 | int i; |
1698 | 1642 | ||
1699 | clk_div = bxt_dp_clk_val[0]; |
1643 | clk_div = bxt_dp_clk_val[0]; |
1700 | for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { |
1644 | for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { |
1701 | if (bxt_dp_clk_val[i].clock == clock) { |
1645 | if (bxt_dp_clk_val[i].clock == clock) { |
1702 | clk_div = bxt_dp_clk_val[i]; |
1646 | clk_div = bxt_dp_clk_val[i]; |
1703 | break; |
1647 | break; |
1704 | } |
1648 | } |
1705 | } |
1649 | } |
1706 | vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; |
1650 | vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; |
1707 | } |
1651 | } |
1708 | 1652 | ||
1709 | if (vco >= 6200000 && vco <= 6700000) { |
1653 | if (vco >= 6200000 && vco <= 6700000) { |
1710 | prop_coef = 4; |
1654 | prop_coef = 4; |
1711 | int_coef = 9; |
1655 | int_coef = 9; |
1712 | gain_ctl = 3; |
1656 | gain_ctl = 3; |
1713 | targ_cnt = 8; |
1657 | targ_cnt = 8; |
1714 | } else if ((vco > 5400000 && vco < 6200000) || |
1658 | } else if ((vco > 5400000 && vco < 6200000) || |
1715 | (vco >= 4800000 && vco < 5400000)) { |
1659 | (vco >= 4800000 && vco < 5400000)) { |
1716 | prop_coef = 5; |
1660 | prop_coef = 5; |
1717 | int_coef = 11; |
1661 | int_coef = 11; |
1718 | gain_ctl = 3; |
1662 | gain_ctl = 3; |
1719 | targ_cnt = 9; |
1663 | targ_cnt = 9; |
1720 | } else if (vco == 5400000) { |
1664 | } else if (vco == 5400000) { |
1721 | prop_coef = 3; |
1665 | prop_coef = 3; |
1722 | int_coef = 8; |
1666 | int_coef = 8; |
1723 | gain_ctl = 1; |
1667 | gain_ctl = 1; |
1724 | targ_cnt = 9; |
1668 | targ_cnt = 9; |
1725 | } else { |
1669 | } else { |
1726 | DRM_ERROR("Invalid VCO\n"); |
1670 | DRM_ERROR("Invalid VCO\n"); |
1727 | return false; |
1671 | return false; |
1728 | } |
1672 | } |
1729 | 1673 | ||
1730 | memset(&crtc_state->dpll_hw_state, 0, |
1674 | memset(&crtc_state->dpll_hw_state, 0, |
1731 | sizeof(crtc_state->dpll_hw_state)); |
1675 | sizeof(crtc_state->dpll_hw_state)); |
1732 | 1676 | ||
1733 | if (clock > 270000) |
1677 | if (clock > 270000) |
1734 | lanestagger = 0x18; |
1678 | lanestagger = 0x18; |
1735 | else if (clock > 135000) |
1679 | else if (clock > 135000) |
1736 | lanestagger = 0x0d; |
1680 | lanestagger = 0x0d; |
1737 | else if (clock > 67000) |
1681 | else if (clock > 67000) |
1738 | lanestagger = 0x07; |
1682 | lanestagger = 0x07; |
1739 | else if (clock > 33000) |
1683 | else if (clock > 33000) |
1740 | lanestagger = 0x04; |
1684 | lanestagger = 0x04; |
1741 | else |
1685 | else |
1742 | lanestagger = 0x02; |
1686 | lanestagger = 0x02; |
1743 | 1687 | ||
1744 | crtc_state->dpll_hw_state.ebb0 = |
1688 | crtc_state->dpll_hw_state.ebb0 = |
1745 | PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); |
1689 | PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); |
1746 | crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; |
1690 | crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; |
1747 | crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); |
1691 | crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); |
1748 | crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; |
1692 | crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; |
1749 | 1693 | ||
1750 | if (clk_div.m2_frac_en) |
1694 | if (clk_div.m2_frac_en) |
1751 | crtc_state->dpll_hw_state.pll3 = |
1695 | crtc_state->dpll_hw_state.pll3 = |
1752 | PORT_PLL_M2_FRAC_ENABLE; |
1696 | PORT_PLL_M2_FRAC_ENABLE; |
1753 | 1697 | ||
1754 | crtc_state->dpll_hw_state.pll6 = |
1698 | crtc_state->dpll_hw_state.pll6 = |
1755 | prop_coef | PORT_PLL_INT_COEFF(int_coef); |
1699 | prop_coef | PORT_PLL_INT_COEFF(int_coef); |
1756 | crtc_state->dpll_hw_state.pll6 |= |
1700 | crtc_state->dpll_hw_state.pll6 |= |
1757 | PORT_PLL_GAIN_CTL(gain_ctl); |
1701 | PORT_PLL_GAIN_CTL(gain_ctl); |
1758 | 1702 | ||
1759 | crtc_state->dpll_hw_state.pll8 = targ_cnt; |
1703 | crtc_state->dpll_hw_state.pll8 = targ_cnt; |
1760 | 1704 | ||
1761 | crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; |
1705 | crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; |
1762 | 1706 | ||
1763 | crtc_state->dpll_hw_state.pll10 = |
1707 | crtc_state->dpll_hw_state.pll10 = |
1764 | PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) |
1708 | PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) |
1765 | | PORT_PLL_DCO_AMP_OVR_EN_H; |
1709 | | PORT_PLL_DCO_AMP_OVR_EN_H; |
1766 | 1710 | ||
1767 | crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; |
1711 | crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; |
1768 | 1712 | ||
1769 | crtc_state->dpll_hw_state.pcsdw12 = |
1713 | crtc_state->dpll_hw_state.pcsdw12 = |
1770 | LANESTAGGER_STRAP_OVRD | lanestagger; |
1714 | LANESTAGGER_STRAP_OVRD | lanestagger; |
1771 | 1715 | ||
1772 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1716 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
1773 | if (pll == NULL) { |
1717 | if (pll == NULL) { |
1774 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1718 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
1775 | pipe_name(intel_crtc->pipe)); |
1719 | pipe_name(intel_crtc->pipe)); |
1776 | return false; |
1720 | return false; |
1777 | } |
1721 | } |
1778 | 1722 | ||
1779 | /* shared DPLL id 0 is DPLL A */ |
1723 | /* shared DPLL id 0 is DPLL A */ |
1780 | crtc_state->ddi_pll_sel = pll->id; |
1724 | crtc_state->ddi_pll_sel = pll->id; |
1781 | 1725 | ||
1782 | return true; |
1726 | return true; |
1783 | } |
1727 | } |
1784 | 1728 | ||
1785 | /* |
1729 | /* |
1786 | * Tries to find a *shared* PLL for the CRTC and store it in |
1730 | * Tries to find a *shared* PLL for the CRTC and store it in |
1787 | * intel_crtc->ddi_pll_sel. |
1731 | * intel_crtc->ddi_pll_sel. |
1788 | * |
1732 | * |
1789 | * For private DPLLs, compute_config() should do the selection for us. This |
1733 | * For private DPLLs, compute_config() should do the selection for us. This |
1790 | * function should be folded into compute_config() eventually. |
1734 | * function should be folded into compute_config() eventually. |
1791 | */ |
1735 | */ |
1792 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1736 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1793 | struct intel_crtc_state *crtc_state) |
1737 | struct intel_crtc_state *crtc_state) |
1794 | { |
1738 | { |
1795 | struct drm_device *dev = intel_crtc->base.dev; |
1739 | struct drm_device *dev = intel_crtc->base.dev; |
1796 | struct intel_encoder *intel_encoder = |
1740 | struct intel_encoder *intel_encoder = |
1797 | intel_ddi_get_crtc_new_encoder(crtc_state); |
1741 | intel_ddi_get_crtc_new_encoder(crtc_state); |
1798 | 1742 | ||
1799 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1743 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1800 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
1744 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
1801 | intel_encoder); |
1745 | intel_encoder); |
1802 | else if (IS_BROXTON(dev)) |
1746 | else if (IS_BROXTON(dev)) |
1803 | return bxt_ddi_pll_select(intel_crtc, crtc_state, |
1747 | return bxt_ddi_pll_select(intel_crtc, crtc_state, |
1804 | intel_encoder); |
1748 | intel_encoder); |
1805 | else |
1749 | else |
1806 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
1750 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
1807 | intel_encoder); |
1751 | intel_encoder); |
1808 | } |
1752 | } |
1809 | 1753 | ||
1810 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1754 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1811 | { |
1755 | { |
1812 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
1756 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
1813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1814 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1758 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1815 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1759 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1816 | int type = intel_encoder->type; |
1760 | int type = intel_encoder->type; |
1817 | uint32_t temp; |
1761 | uint32_t temp; |
1818 | 1762 | ||
1819 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
1763 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
1820 | temp = TRANS_MSA_SYNC_CLK; |
1764 | temp = TRANS_MSA_SYNC_CLK; |
1821 | switch (intel_crtc->config->pipe_bpp) { |
1765 | switch (intel_crtc->config->pipe_bpp) { |
1822 | case 18: |
1766 | case 18: |
1823 | temp |= TRANS_MSA_6_BPC; |
1767 | temp |= TRANS_MSA_6_BPC; |
1824 | break; |
1768 | break; |
1825 | case 24: |
1769 | case 24: |
1826 | temp |= TRANS_MSA_8_BPC; |
1770 | temp |= TRANS_MSA_8_BPC; |
1827 | break; |
1771 | break; |
1828 | case 30: |
1772 | case 30: |
1829 | temp |= TRANS_MSA_10_BPC; |
1773 | temp |= TRANS_MSA_10_BPC; |
1830 | break; |
1774 | break; |
1831 | case 36: |
1775 | case 36: |
1832 | temp |= TRANS_MSA_12_BPC; |
1776 | temp |= TRANS_MSA_12_BPC; |
1833 | break; |
1777 | break; |
1834 | default: |
1778 | default: |
1835 | BUG(); |
1779 | BUG(); |
1836 | } |
1780 | } |
1837 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
1781 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
1838 | } |
1782 | } |
1839 | } |
1783 | } |
1840 | 1784 | ||
1841 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1785 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1842 | { |
1786 | { |
1843 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1844 | struct drm_device *dev = crtc->dev; |
1788 | struct drm_device *dev = crtc->dev; |
1845 | struct drm_i915_private *dev_priv = dev->dev_private; |
1789 | struct drm_i915_private *dev_priv = dev->dev_private; |
1846 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1790 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1847 | uint32_t temp; |
1791 | uint32_t temp; |
1848 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1792 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1849 | if (state == true) |
1793 | if (state == true) |
1850 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
1794 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
1851 | else |
1795 | else |
1852 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
1796 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
1853 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
1797 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
1854 | } |
1798 | } |
1855 | 1799 | ||
1856 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
1800 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
1857 | { |
1801 | { |
1858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1859 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1803 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1860 | struct drm_encoder *encoder = &intel_encoder->base; |
1804 | struct drm_encoder *encoder = &intel_encoder->base; |
1861 | struct drm_device *dev = crtc->dev; |
1805 | struct drm_device *dev = crtc->dev; |
1862 | struct drm_i915_private *dev_priv = dev->dev_private; |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; |
1863 | enum pipe pipe = intel_crtc->pipe; |
1807 | enum pipe pipe = intel_crtc->pipe; |
1864 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1808 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1865 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1809 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1866 | int type = intel_encoder->type; |
1810 | int type = intel_encoder->type; |
1867 | uint32_t temp; |
1811 | uint32_t temp; |
1868 | 1812 | ||
1869 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1813 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1870 | temp = TRANS_DDI_FUNC_ENABLE; |
1814 | temp = TRANS_DDI_FUNC_ENABLE; |
1871 | temp |= TRANS_DDI_SELECT_PORT(port); |
1815 | temp |= TRANS_DDI_SELECT_PORT(port); |
1872 | 1816 | ||
1873 | switch (intel_crtc->config->pipe_bpp) { |
1817 | switch (intel_crtc->config->pipe_bpp) { |
1874 | case 18: |
1818 | case 18: |
1875 | temp |= TRANS_DDI_BPC_6; |
1819 | temp |= TRANS_DDI_BPC_6; |
1876 | break; |
1820 | break; |
1877 | case 24: |
1821 | case 24: |
1878 | temp |= TRANS_DDI_BPC_8; |
1822 | temp |= TRANS_DDI_BPC_8; |
1879 | break; |
1823 | break; |
1880 | case 30: |
1824 | case 30: |
1881 | temp |= TRANS_DDI_BPC_10; |
1825 | temp |= TRANS_DDI_BPC_10; |
1882 | break; |
1826 | break; |
1883 | case 36: |
1827 | case 36: |
1884 | temp |= TRANS_DDI_BPC_12; |
1828 | temp |= TRANS_DDI_BPC_12; |
1885 | break; |
1829 | break; |
1886 | default: |
1830 | default: |
1887 | BUG(); |
1831 | BUG(); |
1888 | } |
1832 | } |
1889 | 1833 | ||
1890 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
1834 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
1891 | temp |= TRANS_DDI_PVSYNC; |
1835 | temp |= TRANS_DDI_PVSYNC; |
1892 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
1836 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
1893 | temp |= TRANS_DDI_PHSYNC; |
1837 | temp |= TRANS_DDI_PHSYNC; |
1894 | 1838 | ||
1895 | if (cpu_transcoder == TRANSCODER_EDP) { |
1839 | if (cpu_transcoder == TRANSCODER_EDP) { |
1896 | switch (pipe) { |
1840 | switch (pipe) { |
1897 | case PIPE_A: |
1841 | case PIPE_A: |
1898 | /* On Haswell, can only use the always-on power well for |
1842 | /* On Haswell, can only use the always-on power well for |
1899 | * eDP when not using the panel fitter, and when not |
1843 | * eDP when not using the panel fitter, and when not |
1900 | * using motion blur mitigation (which we don't |
1844 | * using motion blur mitigation (which we don't |
1901 | * support). */ |
1845 | * support). */ |
1902 | if (IS_HASWELL(dev) && |
1846 | if (IS_HASWELL(dev) && |
1903 | (intel_crtc->config->pch_pfit.enabled || |
1847 | (intel_crtc->config->pch_pfit.enabled || |
1904 | intel_crtc->config->pch_pfit.force_thru)) |
1848 | intel_crtc->config->pch_pfit.force_thru)) |
1905 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1849 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1906 | else |
1850 | else |
1907 | temp |= TRANS_DDI_EDP_INPUT_A_ON; |
1851 | temp |= TRANS_DDI_EDP_INPUT_A_ON; |
1908 | break; |
1852 | break; |
1909 | case PIPE_B: |
1853 | case PIPE_B: |
1910 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; |
1854 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; |
1911 | break; |
1855 | break; |
1912 | case PIPE_C: |
1856 | case PIPE_C: |
1913 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; |
1857 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; |
1914 | break; |
1858 | break; |
1915 | default: |
1859 | default: |
1916 | BUG(); |
1860 | BUG(); |
1917 | break; |
1861 | break; |
1918 | } |
1862 | } |
1919 | } |
1863 | } |
1920 | 1864 | ||
1921 | if (type == INTEL_OUTPUT_HDMI) { |
1865 | if (type == INTEL_OUTPUT_HDMI) { |
1922 | if (intel_crtc->config->has_hdmi_sink) |
1866 | if (intel_crtc->config->has_hdmi_sink) |
1923 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
1867 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
1924 | else |
1868 | else |
1925 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
1869 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
1926 | 1870 | ||
1927 | } else if (type == INTEL_OUTPUT_ANALOG) { |
1871 | } else if (type == INTEL_OUTPUT_ANALOG) { |
1928 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
1872 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
1929 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
1873 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
1930 | 1874 | ||
1931 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || |
1875 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || |
1932 | type == INTEL_OUTPUT_EDP) { |
1876 | type == INTEL_OUTPUT_EDP) { |
1933 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1877 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1934 | 1878 | ||
1935 | if (intel_dp->is_mst) { |
1879 | if (intel_dp->is_mst) { |
1936 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
1880 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
1937 | } else |
1881 | } else |
1938 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
1882 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
1939 | 1883 | ||
1940 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
1884 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
1941 | } else if (type == INTEL_OUTPUT_DP_MST) { |
1885 | } else if (type == INTEL_OUTPUT_DP_MST) { |
1942 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; |
1886 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; |
1943 | 1887 | ||
1944 | if (intel_dp->is_mst) { |
1888 | if (intel_dp->is_mst) { |
1945 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
1889 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
1946 | } else |
1890 | } else |
1947 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
1891 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
1948 | 1892 | ||
1949 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
1893 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
1950 | } else { |
1894 | } else { |
1951 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1895 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1952 | intel_encoder->type, pipe_name(pipe)); |
1896 | intel_encoder->type, pipe_name(pipe)); |
1953 | } |
1897 | } |
1954 | 1898 | ||
1955 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
1899 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
1956 | } |
1900 | } |
1957 | 1901 | ||
1958 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1902 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1959 | enum transcoder cpu_transcoder) |
1903 | enum transcoder cpu_transcoder) |
1960 | { |
1904 | { |
1961 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1905 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1962 | uint32_t val = I915_READ(reg); |
1906 | uint32_t val = I915_READ(reg); |
1963 | 1907 | ||
1964 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
1908 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
1965 | val |= TRANS_DDI_PORT_NONE; |
1909 | val |= TRANS_DDI_PORT_NONE; |
1966 | I915_WRITE(reg, val); |
1910 | I915_WRITE(reg, val); |
1967 | } |
1911 | } |
1968 | 1912 | ||
1969 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1913 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1970 | { |
1914 | { |
1971 | struct drm_device *dev = intel_connector->base.dev; |
1915 | struct drm_device *dev = intel_connector->base.dev; |
1972 | struct drm_i915_private *dev_priv = dev->dev_private; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; |
1973 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
1917 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
1974 | int type = intel_connector->base.connector_type; |
1918 | int type = intel_connector->base.connector_type; |
1975 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1919 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1976 | enum pipe pipe = 0; |
1920 | enum pipe pipe = 0; |
1977 | enum transcoder cpu_transcoder; |
1921 | enum transcoder cpu_transcoder; |
1978 | enum intel_display_power_domain power_domain; |
1922 | enum intel_display_power_domain power_domain; |
1979 | uint32_t tmp; |
1923 | uint32_t tmp; |
1980 | bool ret; |
1924 | bool ret; |
1981 | 1925 | ||
1982 | power_domain = intel_display_port_power_domain(intel_encoder); |
1926 | power_domain = intel_display_port_power_domain(intel_encoder); |
1983 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
1927 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
1984 | return false; |
1928 | return false; |
1985 | 1929 | ||
1986 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1930 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1987 | ret = false; |
1931 | ret = false; |
1988 | goto out; |
1932 | goto out; |
1989 | } |
1933 | } |
1990 | 1934 | ||
1991 | if (port == PORT_A) |
1935 | if (port == PORT_A) |
1992 | cpu_transcoder = TRANSCODER_EDP; |
1936 | cpu_transcoder = TRANSCODER_EDP; |
1993 | else |
1937 | else |
1994 | cpu_transcoder = (enum transcoder) pipe; |
1938 | cpu_transcoder = (enum transcoder) pipe; |
1995 | 1939 | ||
1996 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1940 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1997 | 1941 | ||
1998 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { |
1942 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { |
1999 | case TRANS_DDI_MODE_SELECT_HDMI: |
1943 | case TRANS_DDI_MODE_SELECT_HDMI: |
2000 | case TRANS_DDI_MODE_SELECT_DVI: |
1944 | case TRANS_DDI_MODE_SELECT_DVI: |
2001 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1945 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
2002 | break; |
1946 | break; |
2003 | 1947 | ||
2004 | case TRANS_DDI_MODE_SELECT_DP_SST: |
1948 | case TRANS_DDI_MODE_SELECT_DP_SST: |
2005 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1949 | ret = type == DRM_MODE_CONNECTOR_eDP || |
2006 | type == DRM_MODE_CONNECTOR_DisplayPort; |
1950 | type == DRM_MODE_CONNECTOR_DisplayPort; |
2007 | break; |
1951 | break; |
2008 | 1952 | ||
2009 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1953 | case TRANS_DDI_MODE_SELECT_DP_MST: |
2010 | /* if the transcoder is in MST state then |
1954 | /* if the transcoder is in MST state then |
2011 | * connector isn't connected */ |
1955 | * connector isn't connected */ |
2012 | ret = false; |
1956 | ret = false; |
2013 | break; |
1957 | break; |
2014 | 1958 | ||
2015 | case TRANS_DDI_MODE_SELECT_FDI: |
1959 | case TRANS_DDI_MODE_SELECT_FDI: |
2016 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1960 | ret = type == DRM_MODE_CONNECTOR_VGA; |
2017 | break; |
1961 | break; |
2018 | 1962 | ||
2019 | default: |
1963 | default: |
2020 | ret = false; |
1964 | ret = false; |
2021 | break; |
1965 | break; |
2022 | } |
1966 | } |
2023 | 1967 | ||
2024 | out: |
1968 | out: |
2025 | intel_display_power_put(dev_priv, power_domain); |
1969 | intel_display_power_put(dev_priv, power_domain); |
2026 | 1970 | ||
2027 | return ret; |
1971 | return ret; |
2028 | } |
1972 | } |
2029 | 1973 | ||
2030 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1974 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
2031 | enum pipe *pipe) |
1975 | enum pipe *pipe) |
2032 | { |
1976 | { |
2033 | struct drm_device *dev = encoder->base.dev; |
1977 | struct drm_device *dev = encoder->base.dev; |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; |
1978 | struct drm_i915_private *dev_priv = dev->dev_private; |
2035 | enum port port = intel_ddi_get_encoder_port(encoder); |
1979 | enum port port = intel_ddi_get_encoder_port(encoder); |
2036 | enum intel_display_power_domain power_domain; |
1980 | enum intel_display_power_domain power_domain; |
2037 | u32 tmp; |
1981 | u32 tmp; |
2038 | int i; |
1982 | int i; |
2039 | bool ret; |
1983 | bool ret; |
2040 | 1984 | ||
2041 | power_domain = intel_display_port_power_domain(encoder); |
1985 | power_domain = intel_display_port_power_domain(encoder); |
2042 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
1986 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
2043 | return false; |
1987 | return false; |
2044 | 1988 | ||
2045 | ret = false; |
1989 | ret = false; |
2046 | 1990 | ||
2047 | tmp = I915_READ(DDI_BUF_CTL(port)); |
1991 | tmp = I915_READ(DDI_BUF_CTL(port)); |
2048 | 1992 | ||
2049 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
1993 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
2050 | goto out; |
1994 | goto out; |
2051 | 1995 | ||
2052 | if (port == PORT_A) { |
1996 | if (port == PORT_A) { |
2053 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
1997 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
2054 | 1998 | ||
2055 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1999 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
2056 | case TRANS_DDI_EDP_INPUT_A_ON: |
2000 | case TRANS_DDI_EDP_INPUT_A_ON: |
2057 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
2001 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
2058 | *pipe = PIPE_A; |
2002 | *pipe = PIPE_A; |
2059 | break; |
2003 | break; |
2060 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
2004 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
2061 | *pipe = PIPE_B; |
2005 | *pipe = PIPE_B; |
2062 | break; |
2006 | break; |
2063 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
2007 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
2064 | *pipe = PIPE_C; |
2008 | *pipe = PIPE_C; |
2065 | break; |
2009 | break; |
2066 | } |
2010 | } |
2067 | 2011 | ||
2068 | ret = true; |
2012 | ret = true; |
2069 | 2013 | ||
2070 | goto out; |
2014 | goto out; |
2071 | } |
2015 | } |
2072 | 2016 | ||
2073 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
2017 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
2074 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
2018 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
2075 | 2019 | ||
2076 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { |
2020 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { |
2077 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == |
2021 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == |
2078 | TRANS_DDI_MODE_SELECT_DP_MST) |
2022 | TRANS_DDI_MODE_SELECT_DP_MST) |
2079 | goto out; |
2023 | goto out; |
2080 | 2024 | ||
2081 | *pipe = i; |
2025 | *pipe = i; |
2082 | ret = true; |
2026 | ret = true; |
2083 | 2027 | ||
2084 | goto out; |
2028 | goto out; |
2085 | } |
2029 | } |
2086 | } |
2030 | } |
2087 | 2031 | ||
2088 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
2032 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
2089 | 2033 | ||
2090 | out: |
2034 | out: |
2091 | intel_display_power_put(dev_priv, power_domain); |
2035 | intel_display_power_put(dev_priv, power_domain); |
2092 | 2036 | ||
2093 | return ret; |
2037 | return ret; |
2094 | } |
2038 | } |
2095 | 2039 | ||
2096 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
2040 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
2097 | { |
2041 | { |
2098 | struct drm_crtc *crtc = &intel_crtc->base; |
2042 | struct drm_crtc *crtc = &intel_crtc->base; |
2099 | struct drm_device *dev = crtc->dev; |
2043 | struct drm_device *dev = crtc->dev; |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
2044 | struct drm_i915_private *dev_priv = dev->dev_private; |
2101 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
2045 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
2102 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2046 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2103 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
2047 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
2104 | 2048 | ||
2105 | if (cpu_transcoder != TRANSCODER_EDP) |
2049 | if (cpu_transcoder != TRANSCODER_EDP) |
2106 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2050 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2107 | TRANS_CLK_SEL_PORT(port)); |
2051 | TRANS_CLK_SEL_PORT(port)); |
2108 | } |
2052 | } |
2109 | 2053 | ||
2110 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
2054 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
2111 | { |
2055 | { |
2112 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
2056 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
2113 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
2057 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
2114 | 2058 | ||
2115 | if (cpu_transcoder != TRANSCODER_EDP) |
2059 | if (cpu_transcoder != TRANSCODER_EDP) |
2116 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2060 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2117 | TRANS_CLK_SEL_DISABLED); |
2061 | TRANS_CLK_SEL_DISABLED); |
2118 | } |
2062 | } |
2119 | 2063 | ||
2120 | static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, |
2064 | static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
2121 | enum port port, int type) |
2065 | u32 level, enum port port, int type) |
2122 | { |
- | |
2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
2066 | { |
2124 | const struct ddi_buf_trans *ddi_translations; |
2067 | const struct ddi_buf_trans *ddi_translations; |
2125 | uint8_t iboost; |
2068 | uint8_t iboost; |
2126 | uint8_t dp_iboost, hdmi_iboost; |
2069 | uint8_t dp_iboost, hdmi_iboost; |
2127 | int n_entries; |
2070 | int n_entries; |
2128 | u32 reg; |
2071 | u32 reg; |
2129 | 2072 | ||
2130 | /* VBT may override standard boost values */ |
2073 | /* VBT may override standard boost values */ |
2131 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; |
2074 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; |
2132 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; |
2075 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; |
2133 | 2076 | ||
2134 | if (type == INTEL_OUTPUT_DISPLAYPORT) { |
2077 | if (type == INTEL_OUTPUT_DISPLAYPORT) { |
2135 | if (dp_iboost) { |
2078 | if (dp_iboost) { |
2136 | iboost = dp_iboost; |
2079 | iboost = dp_iboost; |
2137 | } else { |
2080 | } else { |
2138 | ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); |
2081 | ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); |
2139 | iboost = ddi_translations[level].i_boost; |
2082 | iboost = ddi_translations[level].i_boost; |
2140 | } |
2083 | } |
2141 | } else if (type == INTEL_OUTPUT_EDP) { |
2084 | } else if (type == INTEL_OUTPUT_EDP) { |
2142 | if (dp_iboost) { |
2085 | if (dp_iboost) { |
2143 | iboost = dp_iboost; |
2086 | iboost = dp_iboost; |
2144 | } else { |
2087 | } else { |
2145 | ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); |
2088 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
- | 2089 | ||
- | 2090 | if (WARN_ON(port != PORT_A && |
|
- | 2091 | port != PORT_E && n_entries > 9)) |
|
- | 2092 | n_entries = 9; |
|
- | 2093 | ||
2146 | iboost = ddi_translations[level].i_boost; |
2094 | iboost = ddi_translations[level].i_boost; |
2147 | } |
2095 | } |
2148 | } else if (type == INTEL_OUTPUT_HDMI) { |
2096 | } else if (type == INTEL_OUTPUT_HDMI) { |
2149 | if (hdmi_iboost) { |
2097 | if (hdmi_iboost) { |
2150 | iboost = hdmi_iboost; |
2098 | iboost = hdmi_iboost; |
2151 | } else { |
2099 | } else { |
2152 | ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); |
2100 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
2153 | iboost = ddi_translations[level].i_boost; |
2101 | iboost = ddi_translations[level].i_boost; |
2154 | } |
2102 | } |
2155 | } else { |
2103 | } else { |
2156 | return; |
2104 | return; |
2157 | } |
2105 | } |
2158 | 2106 | ||
2159 | /* Make sure that the requested I_boost is valid */ |
2107 | /* Make sure that the requested I_boost is valid */ |
2160 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { |
2108 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { |
2161 | DRM_ERROR("Invalid I_boost value %u\n", iboost); |
2109 | DRM_ERROR("Invalid I_boost value %u\n", iboost); |
2162 | return; |
2110 | return; |
2163 | } |
2111 | } |
2164 | 2112 | ||
2165 | reg = I915_READ(DISPIO_CR_TX_BMU_CR0); |
2113 | reg = I915_READ(DISPIO_CR_TX_BMU_CR0); |
2166 | reg &= ~BALANCE_LEG_MASK(port); |
2114 | reg &= ~BALANCE_LEG_MASK(port); |
2167 | reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); |
2115 | reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); |
2168 | 2116 | ||
2169 | if (iboost) |
2117 | if (iboost) |
2170 | reg |= iboost << BALANCE_LEG_SHIFT(port); |
2118 | reg |= iboost << BALANCE_LEG_SHIFT(port); |
2171 | else |
2119 | else |
2172 | reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); |
2120 | reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); |
2173 | 2121 | ||
2174 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); |
2122 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); |
2175 | } |
2123 | } |
2176 | 2124 | ||
2177 | static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, |
2125 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
2178 | enum port port, int type) |
2126 | u32 level, enum port port, int type) |
2179 | { |
- | |
2180 | struct drm_i915_private *dev_priv = dev->dev_private; |
2127 | { |
2181 | const struct bxt_ddi_buf_trans *ddi_translations; |
2128 | const struct bxt_ddi_buf_trans *ddi_translations; |
2182 | u32 n_entries, i; |
2129 | u32 n_entries, i; |
2183 | uint32_t val; |
2130 | uint32_t val; |
2184 | 2131 | ||
2185 | if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { |
2132 | if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { |
2186 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
2133 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
2187 | ddi_translations = bxt_ddi_translations_edp; |
2134 | ddi_translations = bxt_ddi_translations_edp; |
2188 | } else if (type == INTEL_OUTPUT_DISPLAYPORT |
2135 | } else if (type == INTEL_OUTPUT_DISPLAYPORT |
2189 | || type == INTEL_OUTPUT_EDP) { |
2136 | || type == INTEL_OUTPUT_EDP) { |
2190 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
2137 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
2191 | ddi_translations = bxt_ddi_translations_dp; |
2138 | ddi_translations = bxt_ddi_translations_dp; |
2192 | } else if (type == INTEL_OUTPUT_HDMI) { |
2139 | } else if (type == INTEL_OUTPUT_HDMI) { |
2193 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); |
2140 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); |
2194 | ddi_translations = bxt_ddi_translations_hdmi; |
2141 | ddi_translations = bxt_ddi_translations_hdmi; |
2195 | } else { |
2142 | } else { |
2196 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", |
2143 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", |
2197 | type); |
2144 | type); |
2198 | return; |
2145 | return; |
2199 | } |
2146 | } |
2200 | 2147 | ||
2201 | /* Check if default value has to be used */ |
2148 | /* Check if default value has to be used */ |
2202 | if (level >= n_entries || |
2149 | if (level >= n_entries || |
2203 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { |
2150 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { |
2204 | for (i = 0; i < n_entries; i++) { |
2151 | for (i = 0; i < n_entries; i++) { |
2205 | if (ddi_translations[i].default_index) { |
2152 | if (ddi_translations[i].default_index) { |
2206 | level = i; |
2153 | level = i; |
2207 | break; |
2154 | break; |
2208 | } |
2155 | } |
2209 | } |
2156 | } |
2210 | } |
2157 | } |
2211 | 2158 | ||
2212 | /* |
2159 | /* |
2213 | * While we write to the group register to program all lanes at once we |
2160 | * While we write to the group register to program all lanes at once we |
2214 | * can read only lane registers and we pick lanes 0/1 for that. |
2161 | * can read only lane registers and we pick lanes 0/1 for that. |
2215 | */ |
2162 | */ |
2216 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); |
2163 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); |
2217 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); |
2164 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); |
2218 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); |
2165 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); |
2219 | 2166 | ||
2220 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); |
2167 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); |
2221 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); |
2168 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); |
2222 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | |
2169 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | |
2223 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; |
2170 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; |
2224 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); |
2171 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); |
2225 | 2172 | ||
2226 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); |
2173 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); |
2227 | val &= ~SCALE_DCOMP_METHOD; |
2174 | val &= ~SCALE_DCOMP_METHOD; |
2228 | if (ddi_translations[level].enable) |
2175 | if (ddi_translations[level].enable) |
2229 | val |= SCALE_DCOMP_METHOD; |
2176 | val |= SCALE_DCOMP_METHOD; |
2230 | 2177 | ||
2231 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) |
2178 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) |
2232 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); |
2179 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); |
2233 | 2180 | ||
2234 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); |
2181 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); |
2235 | 2182 | ||
2236 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); |
2183 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); |
2237 | val &= ~DE_EMPHASIS; |
2184 | val &= ~DE_EMPHASIS; |
2238 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; |
2185 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; |
2239 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); |
2186 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); |
2240 | 2187 | ||
2241 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); |
2188 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); |
2242 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; |
2189 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; |
2243 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); |
2190 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); |
2244 | } |
2191 | } |
2245 | 2192 | ||
2246 | static uint32_t translate_signal_level(int signal_levels) |
2193 | static uint32_t translate_signal_level(int signal_levels) |
2247 | { |
2194 | { |
2248 | uint32_t level; |
2195 | uint32_t level; |
2249 | 2196 | ||
2250 | switch (signal_levels) { |
2197 | switch (signal_levels) { |
2251 | default: |
2198 | default: |
2252 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
2199 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
2253 | signal_levels); |
2200 | signal_levels); |
2254 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2201 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2255 | level = 0; |
2202 | level = 0; |
2256 | break; |
2203 | break; |
2257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2258 | level = 1; |
2205 | level = 1; |
2259 | break; |
2206 | break; |
2260 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2207 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2261 | level = 2; |
2208 | level = 2; |
2262 | break; |
2209 | break; |
2263 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: |
2210 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: |
2264 | level = 3; |
2211 | level = 3; |
2265 | break; |
2212 | break; |
2266 | 2213 | ||
2267 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2268 | level = 4; |
2215 | level = 4; |
2269 | break; |
2216 | break; |
2270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2217 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2271 | level = 5; |
2218 | level = 5; |
2272 | break; |
2219 | break; |
2273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2274 | level = 6; |
2221 | level = 6; |
2275 | break; |
2222 | break; |
2276 | 2223 | ||
2277 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2224 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2278 | level = 7; |
2225 | level = 7; |
2279 | break; |
2226 | break; |
2280 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2227 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2281 | level = 8; |
2228 | level = 8; |
2282 | break; |
2229 | break; |
2283 | 2230 | ||
2284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2285 | level = 9; |
2232 | level = 9; |
2286 | break; |
2233 | break; |
2287 | } |
2234 | } |
2288 | 2235 | ||
2289 | return level; |
2236 | return level; |
2290 | } |
2237 | } |
2291 | 2238 | ||
2292 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) |
2239 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) |
2293 | { |
2240 | { |
2294 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2241 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2295 | struct drm_device *dev = dport->base.base.dev; |
2242 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
2296 | struct intel_encoder *encoder = &dport->base; |
2243 | struct intel_encoder *encoder = &dport->base; |
2297 | uint8_t train_set = intel_dp->train_set[0]; |
2244 | uint8_t train_set = intel_dp->train_set[0]; |
2298 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2245 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2299 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2246 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2300 | enum port port = dport->port; |
2247 | enum port port = dport->port; |
2301 | uint32_t level; |
2248 | uint32_t level; |
2302 | 2249 | ||
2303 | level = translate_signal_level(signal_levels); |
2250 | level = translate_signal_level(signal_levels); |
2304 | 2251 | ||
2305 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2252 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
2306 | skl_ddi_set_iboost(dev, level, port, encoder->type); |
2253 | skl_ddi_set_iboost(dev_priv, level, port, encoder->type); |
2307 | else if (IS_BROXTON(dev)) |
2254 | else if (IS_BROXTON(dev_priv)) |
2308 | bxt_ddi_vswing_sequence(dev, level, port, encoder->type); |
2255 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); |
2309 | 2256 | ||
2310 | return DDI_BUF_TRANS_SELECT(level); |
2257 | return DDI_BUF_TRANS_SELECT(level); |
2311 | } |
2258 | } |
2312 | 2259 | ||
2313 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
2260 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
2314 | const struct intel_crtc_state *pipe_config) |
2261 | const struct intel_crtc_state *pipe_config) |
2315 | { |
2262 | { |
2316 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2263 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2317 | enum port port = intel_ddi_get_encoder_port(encoder); |
2264 | enum port port = intel_ddi_get_encoder_port(encoder); |
2318 | 2265 | ||
2319 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
2266 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
2320 | uint32_t dpll = pipe_config->ddi_pll_sel; |
2267 | uint32_t dpll = pipe_config->ddi_pll_sel; |
2321 | uint32_t val; |
2268 | uint32_t val; |
2322 | 2269 | ||
2323 | /* |
2270 | /* |
2324 | * DPLL0 is used for eDP and is the only "private" DPLL (as |
2271 | * DPLL0 is used for eDP and is the only "private" DPLL (as |
2325 | * opposed to shared) on SKL |
2272 | * opposed to shared) on SKL |
2326 | */ |
2273 | */ |
2327 | if (encoder->type == INTEL_OUTPUT_EDP) { |
2274 | if (encoder->type == INTEL_OUTPUT_EDP) { |
2328 | WARN_ON(dpll != SKL_DPLL0); |
2275 | WARN_ON(dpll != SKL_DPLL0); |
2329 | 2276 | ||
2330 | val = I915_READ(DPLL_CTRL1); |
2277 | val = I915_READ(DPLL_CTRL1); |
2331 | 2278 | ||
2332 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | |
2279 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | |
2333 | DPLL_CTRL1_SSC(dpll) | |
2280 | DPLL_CTRL1_SSC(dpll) | |
2334 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
2281 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
2335 | val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); |
2282 | val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); |
2336 | 2283 | ||
2337 | I915_WRITE(DPLL_CTRL1, val); |
2284 | I915_WRITE(DPLL_CTRL1, val); |
2338 | POSTING_READ(DPLL_CTRL1); |
2285 | POSTING_READ(DPLL_CTRL1); |
2339 | } |
2286 | } |
2340 | 2287 | ||
2341 | /* DDI -> PLL mapping */ |
2288 | /* DDI -> PLL mapping */ |
2342 | val = I915_READ(DPLL_CTRL2); |
2289 | val = I915_READ(DPLL_CTRL2); |
2343 | 2290 | ||
2344 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | |
2291 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | |
2345 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); |
2292 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); |
2346 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | |
2293 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | |
2347 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
2294 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
2348 | 2295 | ||
2349 | I915_WRITE(DPLL_CTRL2, val); |
2296 | I915_WRITE(DPLL_CTRL2, val); |
2350 | 2297 | ||
2351 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
2298 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
2352 | WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
2299 | WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
2353 | I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); |
2300 | I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); |
2354 | } |
2301 | } |
2355 | } |
2302 | } |
2356 | 2303 | ||
2357 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
2304 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
2358 | { |
2305 | { |
2359 | struct drm_encoder *encoder = &intel_encoder->base; |
2306 | struct drm_encoder *encoder = &intel_encoder->base; |
2360 | struct drm_device *dev = encoder->dev; |
- | |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
2307 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
2362 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
2308 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
2363 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2309 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2364 | int type = intel_encoder->type; |
2310 | int type = intel_encoder->type; |
- | 2311 | ||
- | 2312 | if (type == INTEL_OUTPUT_HDMI) { |
|
- | 2313 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
|
- | 2314 | ||
- | 2315 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
|
- | 2316 | } |
|
- | 2317 | ||
2365 | int hdmi_level; |
2318 | intel_prepare_ddi_buffer(intel_encoder); |
2366 | 2319 | ||
2367 | if (type == INTEL_OUTPUT_EDP) { |
2320 | if (type == INTEL_OUTPUT_EDP) { |
2368 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2321 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2369 | intel_edp_panel_on(intel_dp); |
2322 | intel_edp_panel_on(intel_dp); |
2370 | } |
2323 | } |
2371 | 2324 | ||
2372 | intel_ddi_clk_select(intel_encoder, crtc->config); |
2325 | intel_ddi_clk_select(intel_encoder, crtc->config); |
2373 | 2326 | ||
2374 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
2327 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
2375 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2328 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2376 | 2329 | ||
2377 | intel_dp_set_link_params(intel_dp, crtc->config); |
2330 | intel_dp_set_link_params(intel_dp, crtc->config); |
2378 | 2331 | ||
2379 | intel_ddi_init_dp_buf_reg(intel_encoder); |
2332 | intel_ddi_init_dp_buf_reg(intel_encoder); |
2380 | 2333 | ||
2381 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2334 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2382 | intel_dp_start_link_train(intel_dp); |
2335 | intel_dp_start_link_train(intel_dp); |
2383 | if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) |
2336 | if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) |
2384 | intel_dp_stop_link_train(intel_dp); |
2337 | intel_dp_stop_link_train(intel_dp); |
2385 | } else if (type == INTEL_OUTPUT_HDMI) { |
2338 | } else if (type == INTEL_OUTPUT_HDMI) { |
2386 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
2339 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
2387 | - | ||
2388 | if (IS_BROXTON(dev)) { |
- | |
2389 | hdmi_level = dev_priv->vbt. |
- | |
2390 | ddi_port_info[port].hdmi_level_shift; |
- | |
2391 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, |
- | |
2392 | INTEL_OUTPUT_HDMI); |
- | |
2393 | } |
2340 | |
2394 | intel_hdmi->set_infoframes(encoder, |
2341 | intel_hdmi->set_infoframes(encoder, |
2395 | crtc->config->has_hdmi_sink, |
2342 | crtc->config->has_hdmi_sink, |
2396 | &crtc->config->base.adjusted_mode); |
2343 | &crtc->config->base.adjusted_mode); |
2397 | } |
2344 | } |
2398 | } |
2345 | } |
2399 | 2346 | ||
2400 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
2347 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
2401 | { |
2348 | { |
2402 | struct drm_encoder *encoder = &intel_encoder->base; |
2349 | struct drm_encoder *encoder = &intel_encoder->base; |
2403 | struct drm_device *dev = encoder->dev; |
2350 | struct drm_device *dev = encoder->dev; |
2404 | struct drm_i915_private *dev_priv = dev->dev_private; |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; |
2405 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2352 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2406 | int type = intel_encoder->type; |
2353 | int type = intel_encoder->type; |
2407 | uint32_t val; |
2354 | uint32_t val; |
2408 | bool wait = false; |
2355 | bool wait = false; |
2409 | 2356 | ||
2410 | val = I915_READ(DDI_BUF_CTL(port)); |
2357 | val = I915_READ(DDI_BUF_CTL(port)); |
2411 | if (val & DDI_BUF_CTL_ENABLE) { |
2358 | if (val & DDI_BUF_CTL_ENABLE) { |
2412 | val &= ~DDI_BUF_CTL_ENABLE; |
2359 | val &= ~DDI_BUF_CTL_ENABLE; |
2413 | I915_WRITE(DDI_BUF_CTL(port), val); |
2360 | I915_WRITE(DDI_BUF_CTL(port), val); |
2414 | wait = true; |
2361 | wait = true; |
2415 | } |
2362 | } |
2416 | 2363 | ||
2417 | val = I915_READ(DP_TP_CTL(port)); |
2364 | val = I915_READ(DP_TP_CTL(port)); |
2418 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
2365 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
2419 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2366 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2420 | I915_WRITE(DP_TP_CTL(port), val); |
2367 | I915_WRITE(DP_TP_CTL(port), val); |
2421 | 2368 | ||
2422 | if (wait) |
2369 | if (wait) |
2423 | intel_wait_ddi_buf_idle(dev_priv, port); |
2370 | intel_wait_ddi_buf_idle(dev_priv, port); |
2424 | 2371 | ||
2425 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
2372 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
2426 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2373 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2427 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2374 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2428 | intel_edp_panel_vdd_on(intel_dp); |
2375 | intel_edp_panel_vdd_on(intel_dp); |
2429 | intel_edp_panel_off(intel_dp); |
2376 | intel_edp_panel_off(intel_dp); |
2430 | } |
2377 | } |
2431 | 2378 | ||
2432 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2379 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2433 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
2380 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
2434 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
2381 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
2435 | else if (INTEL_INFO(dev)->gen < 9) |
2382 | else if (INTEL_INFO(dev)->gen < 9) |
2436 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
2383 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
- | 2384 | ||
- | 2385 | if (type == INTEL_OUTPUT_HDMI) { |
|
- | 2386 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
|
- | 2387 | ||
- | 2388 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); |
|
- | 2389 | } |
|
2437 | } |
2390 | } |
2438 | 2391 | ||
2439 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
2392 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
2440 | { |
2393 | { |
2441 | struct drm_encoder *encoder = &intel_encoder->base; |
2394 | struct drm_encoder *encoder = &intel_encoder->base; |
2442 | struct drm_crtc *crtc = encoder->crtc; |
2395 | struct drm_crtc *crtc = encoder->crtc; |
2443 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2444 | struct drm_device *dev = encoder->dev; |
2397 | struct drm_device *dev = encoder->dev; |
2445 | struct drm_i915_private *dev_priv = dev->dev_private; |
2398 | struct drm_i915_private *dev_priv = dev->dev_private; |
2446 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2399 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2447 | int type = intel_encoder->type; |
2400 | int type = intel_encoder->type; |
2448 | 2401 | ||
2449 | if (type == INTEL_OUTPUT_HDMI) { |
2402 | if (type == INTEL_OUTPUT_HDMI) { |
2450 | struct intel_digital_port *intel_dig_port = |
2403 | struct intel_digital_port *intel_dig_port = |
2451 | enc_to_dig_port(encoder); |
2404 | enc_to_dig_port(encoder); |
2452 | 2405 | ||
2453 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
2406 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
2454 | * are ignored so nothing special needs to be done besides |
2407 | * are ignored so nothing special needs to be done besides |
2455 | * enabling the port. |
2408 | * enabling the port. |
2456 | */ |
2409 | */ |
2457 | I915_WRITE(DDI_BUF_CTL(port), |
2410 | I915_WRITE(DDI_BUF_CTL(port), |
2458 | intel_dig_port->saved_port_bits | |
2411 | intel_dig_port->saved_port_bits | |
2459 | DDI_BUF_CTL_ENABLE); |
2412 | DDI_BUF_CTL_ENABLE); |
2460 | } else if (type == INTEL_OUTPUT_EDP) { |
2413 | } else if (type == INTEL_OUTPUT_EDP) { |
2461 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2414 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2462 | 2415 | ||
2463 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
2416 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
2464 | intel_dp_stop_link_train(intel_dp); |
2417 | intel_dp_stop_link_train(intel_dp); |
2465 | 2418 | ||
2466 | intel_edp_backlight_on(intel_dp); |
2419 | intel_edp_backlight_on(intel_dp); |
2467 | intel_psr_enable(intel_dp); |
2420 | intel_psr_enable(intel_dp); |
2468 | intel_edp_drrs_enable(intel_dp); |
2421 | intel_edp_drrs_enable(intel_dp); |
2469 | } |
2422 | } |
2470 | 2423 | ||
2471 | if (intel_crtc->config->has_audio) { |
2424 | if (intel_crtc->config->has_audio) { |
2472 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
2425 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
2473 | intel_audio_codec_enable(intel_encoder); |
2426 | intel_audio_codec_enable(intel_encoder); |
2474 | } |
2427 | } |
2475 | } |
2428 | } |
2476 | 2429 | ||
2477 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
2430 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
2478 | { |
2431 | { |
2479 | struct drm_encoder *encoder = &intel_encoder->base; |
2432 | struct drm_encoder *encoder = &intel_encoder->base; |
2480 | struct drm_crtc *crtc = encoder->crtc; |
2433 | struct drm_crtc *crtc = encoder->crtc; |
2481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2482 | int type = intel_encoder->type; |
2435 | int type = intel_encoder->type; |
2483 | struct drm_device *dev = encoder->dev; |
2436 | struct drm_device *dev = encoder->dev; |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; |
2437 | struct drm_i915_private *dev_priv = dev->dev_private; |
2485 | 2438 | ||
2486 | if (intel_crtc->config->has_audio) { |
2439 | if (intel_crtc->config->has_audio) { |
2487 | intel_audio_codec_disable(intel_encoder); |
2440 | intel_audio_codec_disable(intel_encoder); |
2488 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
2441 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
2489 | } |
2442 | } |
2490 | 2443 | ||
2491 | if (type == INTEL_OUTPUT_EDP) { |
2444 | if (type == INTEL_OUTPUT_EDP) { |
2492 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2445 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2493 | 2446 | ||
2494 | intel_edp_drrs_disable(intel_dp); |
2447 | intel_edp_drrs_disable(intel_dp); |
2495 | intel_psr_disable(intel_dp); |
2448 | intel_psr_disable(intel_dp); |
2496 | intel_edp_backlight_off(intel_dp); |
2449 | intel_edp_backlight_off(intel_dp); |
2497 | } |
2450 | } |
2498 | } |
2451 | } |
2499 | 2452 | ||
2500 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
2453 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
2501 | struct intel_shared_dpll *pll) |
2454 | struct intel_shared_dpll *pll) |
2502 | { |
2455 | { |
2503 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
2456 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
2504 | POSTING_READ(WRPLL_CTL(pll->id)); |
2457 | POSTING_READ(WRPLL_CTL(pll->id)); |
2505 | udelay(20); |
2458 | udelay(20); |
2506 | } |
2459 | } |
2507 | 2460 | ||
2508 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, |
2461 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, |
2509 | struct intel_shared_dpll *pll) |
2462 | struct intel_shared_dpll *pll) |
2510 | { |
2463 | { |
2511 | I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); |
2464 | I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); |
2512 | POSTING_READ(SPLL_CTL); |
2465 | POSTING_READ(SPLL_CTL); |
2513 | udelay(20); |
2466 | udelay(20); |
2514 | } |
2467 | } |
2515 | 2468 | ||
2516 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, |
2469 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, |
2517 | struct intel_shared_dpll *pll) |
2470 | struct intel_shared_dpll *pll) |
2518 | { |
2471 | { |
2519 | uint32_t val; |
2472 | uint32_t val; |
2520 | 2473 | ||
2521 | val = I915_READ(WRPLL_CTL(pll->id)); |
2474 | val = I915_READ(WRPLL_CTL(pll->id)); |
2522 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
2475 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
2523 | POSTING_READ(WRPLL_CTL(pll->id)); |
2476 | POSTING_READ(WRPLL_CTL(pll->id)); |
2524 | } |
2477 | } |
2525 | 2478 | ||
2526 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, |
2479 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, |
2527 | struct intel_shared_dpll *pll) |
2480 | struct intel_shared_dpll *pll) |
2528 | { |
2481 | { |
2529 | uint32_t val; |
2482 | uint32_t val; |
2530 | 2483 | ||
2531 | val = I915_READ(SPLL_CTL); |
2484 | val = I915_READ(SPLL_CTL); |
2532 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
2485 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
2533 | POSTING_READ(SPLL_CTL); |
2486 | POSTING_READ(SPLL_CTL); |
2534 | } |
2487 | } |
2535 | 2488 | ||
2536 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, |
2489 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, |
2537 | struct intel_shared_dpll *pll, |
2490 | struct intel_shared_dpll *pll, |
2538 | struct intel_dpll_hw_state *hw_state) |
2491 | struct intel_dpll_hw_state *hw_state) |
2539 | { |
2492 | { |
2540 | uint32_t val; |
2493 | uint32_t val; |
2541 | 2494 | ||
2542 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2495 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2543 | return false; |
2496 | return false; |
2544 | 2497 | ||
2545 | val = I915_READ(WRPLL_CTL(pll->id)); |
2498 | val = I915_READ(WRPLL_CTL(pll->id)); |
2546 | hw_state->wrpll = val; |
2499 | hw_state->wrpll = val; |
2547 | 2500 | ||
2548 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2501 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2549 | 2502 | ||
2550 | return val & WRPLL_PLL_ENABLE; |
2503 | return val & WRPLL_PLL_ENABLE; |
2551 | } |
2504 | } |
2552 | 2505 | ||
2553 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, |
2506 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, |
2554 | struct intel_shared_dpll *pll, |
2507 | struct intel_shared_dpll *pll, |
2555 | struct intel_dpll_hw_state *hw_state) |
2508 | struct intel_dpll_hw_state *hw_state) |
2556 | { |
2509 | { |
2557 | uint32_t val; |
2510 | uint32_t val; |
2558 | 2511 | ||
2559 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2512 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2560 | return false; |
2513 | return false; |
2561 | 2514 | ||
2562 | val = I915_READ(SPLL_CTL); |
2515 | val = I915_READ(SPLL_CTL); |
2563 | hw_state->spll = val; |
2516 | hw_state->spll = val; |
2564 | 2517 | ||
2565 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2518 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2566 | 2519 | ||
2567 | return val & SPLL_PLL_ENABLE; |
2520 | return val & SPLL_PLL_ENABLE; |
2568 | } |
2521 | } |
2569 | 2522 | ||
2570 | 2523 | ||
2571 | static const char * const hsw_ddi_pll_names[] = { |
2524 | static const char * const hsw_ddi_pll_names[] = { |
2572 | "WRPLL 1", |
2525 | "WRPLL 1", |
2573 | "WRPLL 2", |
2526 | "WRPLL 2", |
2574 | "SPLL" |
2527 | "SPLL" |
2575 | }; |
2528 | }; |
2576 | 2529 | ||
2577 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
2530 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
2578 | { |
2531 | { |
2579 | int i; |
2532 | int i; |
2580 | 2533 | ||
2581 | dev_priv->num_shared_dpll = 3; |
2534 | dev_priv->num_shared_dpll = 3; |
2582 | 2535 | ||
2583 | for (i = 0; i < 2; i++) { |
2536 | for (i = 0; i < 2; i++) { |
2584 | dev_priv->shared_dplls[i].id = i; |
2537 | dev_priv->shared_dplls[i].id = i; |
2585 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
2538 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
2586 | dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; |
2539 | dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; |
2587 | dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; |
2540 | dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; |
2588 | dev_priv->shared_dplls[i].get_hw_state = |
2541 | dev_priv->shared_dplls[i].get_hw_state = |
2589 | hsw_ddi_wrpll_get_hw_state; |
2542 | hsw_ddi_wrpll_get_hw_state; |
2590 | } |
2543 | } |
2591 | 2544 | ||
2592 | /* SPLL is special, but needs to be initialized anyway.. */ |
2545 | /* SPLL is special, but needs to be initialized anyway.. */ |
2593 | dev_priv->shared_dplls[i].id = i; |
2546 | dev_priv->shared_dplls[i].id = i; |
2594 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
2547 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
2595 | dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; |
2548 | dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; |
2596 | dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; |
2549 | dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; |
2597 | dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; |
2550 | dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; |
2598 | 2551 | ||
2599 | } |
2552 | } |
2600 | 2553 | ||
2601 | static const char * const skl_ddi_pll_names[] = { |
2554 | static const char * const skl_ddi_pll_names[] = { |
2602 | "DPLL 1", |
2555 | "DPLL 1", |
2603 | "DPLL 2", |
2556 | "DPLL 2", |
2604 | "DPLL 3", |
2557 | "DPLL 3", |
2605 | }; |
2558 | }; |
2606 | 2559 | ||
2607 | struct skl_dpll_regs { |
2560 | struct skl_dpll_regs { |
2608 | i915_reg_t ctl, cfgcr1, cfgcr2; |
2561 | i915_reg_t ctl, cfgcr1, cfgcr2; |
2609 | }; |
2562 | }; |
2610 | 2563 | ||
2611 | /* this array is indexed by the *shared* pll id */ |
2564 | /* this array is indexed by the *shared* pll id */ |
2612 | static const struct skl_dpll_regs skl_dpll_regs[3] = { |
2565 | static const struct skl_dpll_regs skl_dpll_regs[3] = { |
2613 | { |
2566 | { |
2614 | /* DPLL 1 */ |
2567 | /* DPLL 1 */ |
2615 | .ctl = LCPLL2_CTL, |
2568 | .ctl = LCPLL2_CTL, |
2616 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), |
2569 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), |
2617 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), |
2570 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), |
2618 | }, |
2571 | }, |
2619 | { |
2572 | { |
2620 | /* DPLL 2 */ |
2573 | /* DPLL 2 */ |
2621 | .ctl = WRPLL_CTL(0), |
2574 | .ctl = WRPLL_CTL(0), |
2622 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
2575 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
2623 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), |
2576 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), |
2624 | }, |
2577 | }, |
2625 | { |
2578 | { |
2626 | /* DPLL 3 */ |
2579 | /* DPLL 3 */ |
2627 | .ctl = WRPLL_CTL(1), |
2580 | .ctl = WRPLL_CTL(1), |
2628 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
2581 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
2629 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), |
2582 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), |
2630 | }, |
2583 | }, |
2631 | }; |
2584 | }; |
2632 | 2585 | ||
2633 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, |
2586 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, |
2634 | struct intel_shared_dpll *pll) |
2587 | struct intel_shared_dpll *pll) |
2635 | { |
2588 | { |
2636 | uint32_t val; |
2589 | uint32_t val; |
2637 | unsigned int dpll; |
2590 | unsigned int dpll; |
2638 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2591 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2639 | 2592 | ||
2640 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
2593 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
2641 | dpll = pll->id + 1; |
2594 | dpll = pll->id + 1; |
2642 | 2595 | ||
2643 | val = I915_READ(DPLL_CTRL1); |
2596 | val = I915_READ(DPLL_CTRL1); |
2644 | 2597 | ||
2645 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | |
2598 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | |
2646 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
2599 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
2647 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
2600 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
2648 | 2601 | ||
2649 | I915_WRITE(DPLL_CTRL1, val); |
2602 | I915_WRITE(DPLL_CTRL1, val); |
2650 | POSTING_READ(DPLL_CTRL1); |
2603 | POSTING_READ(DPLL_CTRL1); |
2651 | 2604 | ||
2652 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); |
2605 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); |
2653 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); |
2606 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); |
2654 | POSTING_READ(regs[pll->id].cfgcr1); |
2607 | POSTING_READ(regs[pll->id].cfgcr1); |
2655 | POSTING_READ(regs[pll->id].cfgcr2); |
2608 | POSTING_READ(regs[pll->id].cfgcr2); |
2656 | 2609 | ||
2657 | /* the enable bit is always bit 31 */ |
2610 | /* the enable bit is always bit 31 */ |
2658 | I915_WRITE(regs[pll->id].ctl, |
2611 | I915_WRITE(regs[pll->id].ctl, |
2659 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); |
2612 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); |
2660 | 2613 | ||
2661 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) |
2614 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) |
2662 | DRM_ERROR("DPLL %d not locked\n", dpll); |
2615 | DRM_ERROR("DPLL %d not locked\n", dpll); |
2663 | } |
2616 | } |
2664 | 2617 | ||
2665 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, |
2618 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, |
2666 | struct intel_shared_dpll *pll) |
2619 | struct intel_shared_dpll *pll) |
2667 | { |
2620 | { |
2668 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2621 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2669 | 2622 | ||
2670 | /* the enable bit is always bit 31 */ |
2623 | /* the enable bit is always bit 31 */ |
2671 | I915_WRITE(regs[pll->id].ctl, |
2624 | I915_WRITE(regs[pll->id].ctl, |
2672 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); |
2625 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); |
2673 | POSTING_READ(regs[pll->id].ctl); |
2626 | POSTING_READ(regs[pll->id].ctl); |
2674 | } |
2627 | } |
2675 | 2628 | ||
2676 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
2629 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
2677 | struct intel_shared_dpll *pll, |
2630 | struct intel_shared_dpll *pll, |
2678 | struct intel_dpll_hw_state *hw_state) |
2631 | struct intel_dpll_hw_state *hw_state) |
2679 | { |
2632 | { |
2680 | uint32_t val; |
2633 | uint32_t val; |
2681 | unsigned int dpll; |
2634 | unsigned int dpll; |
2682 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2635 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
2683 | bool ret; |
2636 | bool ret; |
2684 | 2637 | ||
2685 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2638 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2686 | return false; |
2639 | return false; |
2687 | 2640 | ||
2688 | ret = false; |
2641 | ret = false; |
2689 | 2642 | ||
2690 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
2643 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
2691 | dpll = pll->id + 1; |
2644 | dpll = pll->id + 1; |
2692 | 2645 | ||
2693 | val = I915_READ(regs[pll->id].ctl); |
2646 | val = I915_READ(regs[pll->id].ctl); |
2694 | if (!(val & LCPLL_PLL_ENABLE)) |
2647 | if (!(val & LCPLL_PLL_ENABLE)) |
2695 | goto out; |
2648 | goto out; |
2696 | 2649 | ||
2697 | val = I915_READ(DPLL_CTRL1); |
2650 | val = I915_READ(DPLL_CTRL1); |
2698 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; |
2651 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; |
2699 | 2652 | ||
2700 | /* avoid reading back stale values if HDMI mode is not enabled */ |
2653 | /* avoid reading back stale values if HDMI mode is not enabled */ |
2701 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { |
2654 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { |
2702 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
2655 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
2703 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
2656 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
2704 | } |
2657 | } |
2705 | ret = true; |
2658 | ret = true; |
2706 | 2659 | ||
2707 | out: |
2660 | out: |
2708 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2661 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2709 | 2662 | ||
2710 | return ret; |
2663 | return ret; |
2711 | } |
2664 | } |
2712 | 2665 | ||
2713 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) |
2666 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) |
2714 | { |
2667 | { |
2715 | int i; |
2668 | int i; |
2716 | 2669 | ||
2717 | dev_priv->num_shared_dpll = 3; |
2670 | dev_priv->num_shared_dpll = 3; |
2718 | 2671 | ||
2719 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
2672 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
2720 | dev_priv->shared_dplls[i].id = i; |
2673 | dev_priv->shared_dplls[i].id = i; |
2721 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; |
2674 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; |
2722 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; |
2675 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; |
2723 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; |
2676 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; |
2724 | dev_priv->shared_dplls[i].get_hw_state = |
2677 | dev_priv->shared_dplls[i].get_hw_state = |
2725 | skl_ddi_pll_get_hw_state; |
2678 | skl_ddi_pll_get_hw_state; |
2726 | } |
2679 | } |
2727 | } |
2680 | } |
2728 | 2681 | ||
2729 | static void broxton_phy_init(struct drm_i915_private *dev_priv, |
2682 | static void broxton_phy_init(struct drm_i915_private *dev_priv, |
2730 | enum dpio_phy phy) |
2683 | enum dpio_phy phy) |
2731 | { |
2684 | { |
2732 | enum port port; |
2685 | enum port port; |
2733 | uint32_t val; |
2686 | uint32_t val; |
2734 | 2687 | ||
2735 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); |
2688 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); |
2736 | val |= GT_DISPLAY_POWER_ON(phy); |
2689 | val |= GT_DISPLAY_POWER_ON(phy); |
2737 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); |
2690 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); |
2738 | 2691 | ||
2739 | /* Considering 10ms timeout until BSpec is updated */ |
2692 | /* Considering 10ms timeout until BSpec is updated */ |
2740 | if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) |
2693 | if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) |
2741 | DRM_ERROR("timeout during PHY%d power on\n", phy); |
2694 | DRM_ERROR("timeout during PHY%d power on\n", phy); |
2742 | 2695 | ||
2743 | for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); |
2696 | for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); |
2744 | port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { |
2697 | port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { |
2745 | int lane; |
2698 | int lane; |
2746 | 2699 | ||
2747 | for (lane = 0; lane < 4; lane++) { |
2700 | for (lane = 0; lane < 4; lane++) { |
2748 | val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); |
2701 | val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); |
2749 | /* |
2702 | /* |
2750 | * Note that on CHV this flag is called UPAR, but has |
2703 | * Note that on CHV this flag is called UPAR, but has |
2751 | * the same function. |
2704 | * the same function. |
2752 | */ |
2705 | */ |
2753 | val &= ~LATENCY_OPTIM; |
2706 | val &= ~LATENCY_OPTIM; |
2754 | if (lane != 1) |
2707 | if (lane != 1) |
2755 | val |= LATENCY_OPTIM; |
2708 | val |= LATENCY_OPTIM; |
2756 | 2709 | ||
2757 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); |
2710 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); |
2758 | } |
2711 | } |
2759 | } |
2712 | } |
2760 | 2713 | ||
2761 | /* Program PLL Rcomp code offset */ |
2714 | /* Program PLL Rcomp code offset */ |
2762 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); |
2715 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); |
2763 | val &= ~IREF0RC_OFFSET_MASK; |
2716 | val &= ~IREF0RC_OFFSET_MASK; |
2764 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; |
2717 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; |
2765 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); |
2718 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); |
2766 | 2719 | ||
2767 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); |
2720 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); |
2768 | val &= ~IREF1RC_OFFSET_MASK; |
2721 | val &= ~IREF1RC_OFFSET_MASK; |
2769 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; |
2722 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; |
2770 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); |
2723 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); |
2771 | 2724 | ||
2772 | /* Program power gating */ |
2725 | /* Program power gating */ |
2773 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); |
2726 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); |
2774 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | |
2727 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | |
2775 | SUS_CLK_CONFIG; |
2728 | SUS_CLK_CONFIG; |
2776 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); |
2729 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); |
2777 | 2730 | ||
2778 | if (phy == DPIO_PHY0) { |
2731 | if (phy == DPIO_PHY0) { |
2779 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); |
2732 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); |
2780 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; |
2733 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; |
2781 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); |
2734 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); |
2782 | } |
2735 | } |
2783 | 2736 | ||
2784 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); |
2737 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); |
2785 | val &= ~OCL2_LDOFUSE_PWR_DIS; |
2738 | val &= ~OCL2_LDOFUSE_PWR_DIS; |
2786 | /* |
2739 | /* |
2787 | * On PHY1 disable power on the second channel, since no port is |
2740 | * On PHY1 disable power on the second channel, since no port is |
2788 | * connected there. On PHY0 both channels have a port, so leave it |
2741 | * connected there. On PHY0 both channels have a port, so leave it |
2789 | * enabled. |
2742 | * enabled. |
2790 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should |
2743 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should |
2791 | * power down the second channel on PHY0 as well. |
2744 | * power down the second channel on PHY0 as well. |
2792 | */ |
2745 | */ |
2793 | if (phy == DPIO_PHY1) |
2746 | if (phy == DPIO_PHY1) |
2794 | val |= OCL2_LDOFUSE_PWR_DIS; |
2747 | val |= OCL2_LDOFUSE_PWR_DIS; |
2795 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); |
2748 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); |
2796 | 2749 | ||
2797 | if (phy == DPIO_PHY0) { |
2750 | if (phy == DPIO_PHY0) { |
2798 | uint32_t grc_code; |
2751 | uint32_t grc_code; |
2799 | /* |
2752 | /* |
2800 | * PHY0 isn't connected to an RCOMP resistor so copy over |
2753 | * PHY0 isn't connected to an RCOMP resistor so copy over |
2801 | * the corresponding calibrated value from PHY1, and disable |
2754 | * the corresponding calibrated value from PHY1, and disable |
2802 | * the automatic calibration on PHY0. |
2755 | * the automatic calibration on PHY0. |
2803 | */ |
2756 | */ |
2804 | if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, |
2757 | if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, |
2805 | 10)) |
2758 | 10)) |
2806 | DRM_ERROR("timeout waiting for PHY1 GRC\n"); |
2759 | DRM_ERROR("timeout waiting for PHY1 GRC\n"); |
2807 | 2760 | ||
2808 | val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); |
2761 | val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); |
2809 | val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; |
2762 | val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; |
2810 | grc_code = val << GRC_CODE_FAST_SHIFT | |
2763 | grc_code = val << GRC_CODE_FAST_SHIFT | |
2811 | val << GRC_CODE_SLOW_SHIFT | |
2764 | val << GRC_CODE_SLOW_SHIFT | |
2812 | val; |
2765 | val; |
2813 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); |
2766 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); |
2814 | 2767 | ||
2815 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); |
2768 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); |
2816 | val |= GRC_DIS | GRC_RDY_OVRD; |
2769 | val |= GRC_DIS | GRC_RDY_OVRD; |
2817 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); |
2770 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); |
2818 | } |
2771 | } |
2819 | 2772 | ||
2820 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
2773 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
2821 | val |= COMMON_RESET_DIS; |
2774 | val |= COMMON_RESET_DIS; |
2822 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); |
2775 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); |
2823 | } |
2776 | } |
2824 | 2777 | ||
2825 | void broxton_ddi_phy_init(struct drm_device *dev) |
2778 | void broxton_ddi_phy_init(struct drm_device *dev) |
2826 | { |
2779 | { |
2827 | /* Enable PHY1 first since it provides Rcomp for PHY0 */ |
2780 | /* Enable PHY1 first since it provides Rcomp for PHY0 */ |
2828 | broxton_phy_init(dev->dev_private, DPIO_PHY1); |
2781 | broxton_phy_init(dev->dev_private, DPIO_PHY1); |
2829 | broxton_phy_init(dev->dev_private, DPIO_PHY0); |
2782 | broxton_phy_init(dev->dev_private, DPIO_PHY0); |
2830 | } |
2783 | } |
2831 | 2784 | ||
2832 | static void broxton_phy_uninit(struct drm_i915_private *dev_priv, |
2785 | static void broxton_phy_uninit(struct drm_i915_private *dev_priv, |
2833 | enum dpio_phy phy) |
2786 | enum dpio_phy phy) |
2834 | { |
2787 | { |
2835 | uint32_t val; |
2788 | uint32_t val; |
2836 | 2789 | ||
2837 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
2790 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
2838 | val &= ~COMMON_RESET_DIS; |
2791 | val &= ~COMMON_RESET_DIS; |
2839 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); |
2792 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); |
2840 | } |
2793 | } |
2841 | 2794 | ||
2842 | void broxton_ddi_phy_uninit(struct drm_device *dev) |
2795 | void broxton_ddi_phy_uninit(struct drm_device *dev) |
2843 | { |
2796 | { |
2844 | struct drm_i915_private *dev_priv = dev->dev_private; |
2797 | struct drm_i915_private *dev_priv = dev->dev_private; |
2845 | 2798 | ||
2846 | broxton_phy_uninit(dev_priv, DPIO_PHY1); |
2799 | broxton_phy_uninit(dev_priv, DPIO_PHY1); |
2847 | broxton_phy_uninit(dev_priv, DPIO_PHY0); |
2800 | broxton_phy_uninit(dev_priv, DPIO_PHY0); |
2848 | 2801 | ||
2849 | /* FIXME: do this in broxton_phy_uninit per phy */ |
2802 | /* FIXME: do this in broxton_phy_uninit per phy */ |
2850 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); |
2803 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); |
2851 | } |
2804 | } |
2852 | 2805 | ||
2853 | static const char * const bxt_ddi_pll_names[] = { |
2806 | static const char * const bxt_ddi_pll_names[] = { |
2854 | "PORT PLL A", |
2807 | "PORT PLL A", |
2855 | "PORT PLL B", |
2808 | "PORT PLL B", |
2856 | "PORT PLL C", |
2809 | "PORT PLL C", |
2857 | }; |
2810 | }; |
2858 | 2811 | ||
2859 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, |
2812 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, |
2860 | struct intel_shared_dpll *pll) |
2813 | struct intel_shared_dpll *pll) |
2861 | { |
2814 | { |
2862 | uint32_t temp; |
2815 | uint32_t temp; |
2863 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2816 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2864 | 2817 | ||
2865 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2818 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2866 | temp &= ~PORT_PLL_REF_SEL; |
2819 | temp &= ~PORT_PLL_REF_SEL; |
2867 | /* Non-SSC reference */ |
2820 | /* Non-SSC reference */ |
2868 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2821 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2869 | 2822 | ||
2870 | /* Disable 10 bit clock */ |
2823 | /* Disable 10 bit clock */ |
2871 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2824 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2872 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
2825 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
2873 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2826 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2874 | 2827 | ||
2875 | /* Write P1 & P2 */ |
2828 | /* Write P1 & P2 */ |
2876 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
2829 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
2877 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); |
2830 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); |
2878 | temp |= pll->config.hw_state.ebb0; |
2831 | temp |= pll->config.hw_state.ebb0; |
2879 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); |
2832 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); |
2880 | 2833 | ||
2881 | /* Write M2 integer */ |
2834 | /* Write M2 integer */ |
2882 | temp = I915_READ(BXT_PORT_PLL(port, 0)); |
2835 | temp = I915_READ(BXT_PORT_PLL(port, 0)); |
2883 | temp &= ~PORT_PLL_M2_MASK; |
2836 | temp &= ~PORT_PLL_M2_MASK; |
2884 | temp |= pll->config.hw_state.pll0; |
2837 | temp |= pll->config.hw_state.pll0; |
2885 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); |
2838 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); |
2886 | 2839 | ||
2887 | /* Write N */ |
2840 | /* Write N */ |
2888 | temp = I915_READ(BXT_PORT_PLL(port, 1)); |
2841 | temp = I915_READ(BXT_PORT_PLL(port, 1)); |
2889 | temp &= ~PORT_PLL_N_MASK; |
2842 | temp &= ~PORT_PLL_N_MASK; |
2890 | temp |= pll->config.hw_state.pll1; |
2843 | temp |= pll->config.hw_state.pll1; |
2891 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); |
2844 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); |
2892 | 2845 | ||
2893 | /* Write M2 fraction */ |
2846 | /* Write M2 fraction */ |
2894 | temp = I915_READ(BXT_PORT_PLL(port, 2)); |
2847 | temp = I915_READ(BXT_PORT_PLL(port, 2)); |
2895 | temp &= ~PORT_PLL_M2_FRAC_MASK; |
2848 | temp &= ~PORT_PLL_M2_FRAC_MASK; |
2896 | temp |= pll->config.hw_state.pll2; |
2849 | temp |= pll->config.hw_state.pll2; |
2897 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); |
2850 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); |
2898 | 2851 | ||
2899 | /* Write M2 fraction enable */ |
2852 | /* Write M2 fraction enable */ |
2900 | temp = I915_READ(BXT_PORT_PLL(port, 3)); |
2853 | temp = I915_READ(BXT_PORT_PLL(port, 3)); |
2901 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; |
2854 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; |
2902 | temp |= pll->config.hw_state.pll3; |
2855 | temp |= pll->config.hw_state.pll3; |
2903 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); |
2856 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); |
2904 | 2857 | ||
2905 | /* Write coeff */ |
2858 | /* Write coeff */ |
2906 | temp = I915_READ(BXT_PORT_PLL(port, 6)); |
2859 | temp = I915_READ(BXT_PORT_PLL(port, 6)); |
2907 | temp &= ~PORT_PLL_PROP_COEFF_MASK; |
2860 | temp &= ~PORT_PLL_PROP_COEFF_MASK; |
2908 | temp &= ~PORT_PLL_INT_COEFF_MASK; |
2861 | temp &= ~PORT_PLL_INT_COEFF_MASK; |
2909 | temp &= ~PORT_PLL_GAIN_CTL_MASK; |
2862 | temp &= ~PORT_PLL_GAIN_CTL_MASK; |
2910 | temp |= pll->config.hw_state.pll6; |
2863 | temp |= pll->config.hw_state.pll6; |
2911 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); |
2864 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); |
2912 | 2865 | ||
2913 | /* Write calibration val */ |
2866 | /* Write calibration val */ |
2914 | temp = I915_READ(BXT_PORT_PLL(port, 8)); |
2867 | temp = I915_READ(BXT_PORT_PLL(port, 8)); |
2915 | temp &= ~PORT_PLL_TARGET_CNT_MASK; |
2868 | temp &= ~PORT_PLL_TARGET_CNT_MASK; |
2916 | temp |= pll->config.hw_state.pll8; |
2869 | temp |= pll->config.hw_state.pll8; |
2917 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); |
2870 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); |
2918 | 2871 | ||
2919 | temp = I915_READ(BXT_PORT_PLL(port, 9)); |
2872 | temp = I915_READ(BXT_PORT_PLL(port, 9)); |
2920 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; |
2873 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; |
2921 | temp |= pll->config.hw_state.pll9; |
2874 | temp |= pll->config.hw_state.pll9; |
2922 | I915_WRITE(BXT_PORT_PLL(port, 9), temp); |
2875 | I915_WRITE(BXT_PORT_PLL(port, 9), temp); |
2923 | 2876 | ||
2924 | temp = I915_READ(BXT_PORT_PLL(port, 10)); |
2877 | temp = I915_READ(BXT_PORT_PLL(port, 10)); |
2925 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; |
2878 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; |
2926 | temp &= ~PORT_PLL_DCO_AMP_MASK; |
2879 | temp &= ~PORT_PLL_DCO_AMP_MASK; |
2927 | temp |= pll->config.hw_state.pll10; |
2880 | temp |= pll->config.hw_state.pll10; |
2928 | I915_WRITE(BXT_PORT_PLL(port, 10), temp); |
2881 | I915_WRITE(BXT_PORT_PLL(port, 10), temp); |
2929 | 2882 | ||
2930 | /* Recalibrate with new settings */ |
2883 | /* Recalibrate with new settings */ |
2931 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2884 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2932 | temp |= PORT_PLL_RECALIBRATE; |
2885 | temp |= PORT_PLL_RECALIBRATE; |
2933 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2886 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2934 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
2887 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
2935 | temp |= pll->config.hw_state.ebb4; |
2888 | temp |= pll->config.hw_state.ebb4; |
2936 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2889 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2937 | 2890 | ||
2938 | /* Enable PLL */ |
2891 | /* Enable PLL */ |
2939 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2892 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2940 | temp |= PORT_PLL_ENABLE; |
2893 | temp |= PORT_PLL_ENABLE; |
2941 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2894 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2942 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
2895 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
2943 | 2896 | ||
2944 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & |
2897 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & |
2945 | PORT_PLL_LOCK), 200)) |
2898 | PORT_PLL_LOCK), 200)) |
2946 | DRM_ERROR("PLL %d not locked\n", port); |
2899 | DRM_ERROR("PLL %d not locked\n", port); |
2947 | 2900 | ||
2948 | /* |
2901 | /* |
2949 | * While we write to the group register to program all lanes at once we |
2902 | * While we write to the group register to program all lanes at once we |
2950 | * can read only lane registers and we pick lanes 0/1 for that. |
2903 | * can read only lane registers and we pick lanes 0/1 for that. |
2951 | */ |
2904 | */ |
2952 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
2905 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
2953 | temp &= ~LANE_STAGGER_MASK; |
2906 | temp &= ~LANE_STAGGER_MASK; |
2954 | temp &= ~LANESTAGGER_STRAP_OVRD; |
2907 | temp &= ~LANESTAGGER_STRAP_OVRD; |
2955 | temp |= pll->config.hw_state.pcsdw12; |
2908 | temp |= pll->config.hw_state.pcsdw12; |
2956 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); |
2909 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); |
2957 | } |
2910 | } |
2958 | 2911 | ||
2959 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, |
2912 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, |
2960 | struct intel_shared_dpll *pll) |
2913 | struct intel_shared_dpll *pll) |
2961 | { |
2914 | { |
2962 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2915 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2963 | uint32_t temp; |
2916 | uint32_t temp; |
2964 | 2917 | ||
2965 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2918 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2966 | temp &= ~PORT_PLL_ENABLE; |
2919 | temp &= ~PORT_PLL_ENABLE; |
2967 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2920 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
2968 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
2921 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
2969 | } |
2922 | } |
2970 | 2923 | ||
2971 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
2924 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
2972 | struct intel_shared_dpll *pll, |
2925 | struct intel_shared_dpll *pll, |
2973 | struct intel_dpll_hw_state *hw_state) |
2926 | struct intel_dpll_hw_state *hw_state) |
2974 | { |
2927 | { |
2975 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2928 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
2976 | uint32_t val; |
2929 | uint32_t val; |
2977 | bool ret; |
2930 | bool ret; |
2978 | 2931 | ||
2979 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2932 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
2980 | return false; |
2933 | return false; |
2981 | 2934 | ||
2982 | ret = false; |
2935 | ret = false; |
2983 | 2936 | ||
2984 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2937 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2985 | if (!(val & PORT_PLL_ENABLE)) |
2938 | if (!(val & PORT_PLL_ENABLE)) |
2986 | goto out; |
2939 | goto out; |
2987 | 2940 | ||
2988 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
2941 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
2989 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
2942 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
2990 | 2943 | ||
2991 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2944 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2992 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; |
2945 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; |
2993 | 2946 | ||
2994 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); |
2947 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); |
2995 | hw_state->pll0 &= PORT_PLL_M2_MASK; |
2948 | hw_state->pll0 &= PORT_PLL_M2_MASK; |
2996 | 2949 | ||
2997 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); |
2950 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); |
2998 | hw_state->pll1 &= PORT_PLL_N_MASK; |
2951 | hw_state->pll1 &= PORT_PLL_N_MASK; |
2999 | 2952 | ||
3000 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); |
2953 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); |
3001 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; |
2954 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; |
3002 | 2955 | ||
3003 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); |
2956 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); |
3004 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; |
2957 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; |
3005 | 2958 | ||
3006 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); |
2959 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); |
3007 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | |
2960 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | |
3008 | PORT_PLL_INT_COEFF_MASK | |
2961 | PORT_PLL_INT_COEFF_MASK | |
3009 | PORT_PLL_GAIN_CTL_MASK; |
2962 | PORT_PLL_GAIN_CTL_MASK; |
3010 | 2963 | ||
3011 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); |
2964 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); |
3012 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; |
2965 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; |
3013 | 2966 | ||
3014 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); |
2967 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); |
3015 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; |
2968 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; |
3016 | 2969 | ||
3017 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); |
2970 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); |
3018 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | |
2971 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | |
3019 | PORT_PLL_DCO_AMP_MASK; |
2972 | PORT_PLL_DCO_AMP_MASK; |
3020 | 2973 | ||
3021 | /* |
2974 | /* |
3022 | * While we write to the group register to program all lanes at once we |
2975 | * While we write to the group register to program all lanes at once we |
3023 | * can read only lane registers. We configure all lanes the same way, so |
2976 | * can read only lane registers. We configure all lanes the same way, so |
3024 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. |
2977 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. |
3025 | */ |
2978 | */ |
3026 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
2979 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
3027 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) |
2980 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) |
3028 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", |
2981 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", |
3029 | hw_state->pcsdw12, |
2982 | hw_state->pcsdw12, |
3030 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); |
2983 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); |
3031 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
2984 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
3032 | 2985 | ||
3033 | ret = true; |
2986 | ret = true; |
3034 | 2987 | ||
3035 | out: |
2988 | out: |
3036 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2989 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
3037 | 2990 | ||
3038 | return ret; |
2991 | return ret; |
3039 | } |
2992 | } |
3040 | 2993 | ||
3041 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) |
2994 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) |
3042 | { |
2995 | { |
3043 | int i; |
2996 | int i; |
3044 | 2997 | ||
3045 | dev_priv->num_shared_dpll = 3; |
2998 | dev_priv->num_shared_dpll = 3; |
3046 | 2999 | ||
3047 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3000 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3048 | dev_priv->shared_dplls[i].id = i; |
3001 | dev_priv->shared_dplls[i].id = i; |
3049 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; |
3002 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; |
3050 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; |
3003 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; |
3051 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; |
3004 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; |
3052 | dev_priv->shared_dplls[i].get_hw_state = |
3005 | dev_priv->shared_dplls[i].get_hw_state = |
3053 | bxt_ddi_pll_get_hw_state; |
3006 | bxt_ddi_pll_get_hw_state; |
3054 | } |
3007 | } |
3055 | } |
3008 | } |
3056 | 3009 | ||
3057 | void intel_ddi_pll_init(struct drm_device *dev) |
3010 | void intel_ddi_pll_init(struct drm_device *dev) |
3058 | { |
3011 | { |
3059 | struct drm_i915_private *dev_priv = dev->dev_private; |
3012 | struct drm_i915_private *dev_priv = dev->dev_private; |
3060 | uint32_t val = I915_READ(LCPLL_CTL); |
3013 | uint32_t val = I915_READ(LCPLL_CTL); |
3061 | 3014 | ||
3062 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
3015 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
3063 | skl_shared_dplls_init(dev_priv); |
3016 | skl_shared_dplls_init(dev_priv); |
3064 | else if (IS_BROXTON(dev)) |
3017 | else if (IS_BROXTON(dev)) |
3065 | bxt_shared_dplls_init(dev_priv); |
3018 | bxt_shared_dplls_init(dev_priv); |
3066 | else |
3019 | else |
3067 | hsw_shared_dplls_init(dev_priv); |
3020 | hsw_shared_dplls_init(dev_priv); |
3068 | 3021 | ||
3069 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
3022 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
3070 | int cdclk_freq; |
3023 | int cdclk_freq; |
3071 | 3024 | ||
3072 | cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
3025 | cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
3073 | dev_priv->skl_boot_cdclk = cdclk_freq; |
3026 | dev_priv->skl_boot_cdclk = cdclk_freq; |
3074 | if (skl_sanitize_cdclk(dev_priv)) |
3027 | if (skl_sanitize_cdclk(dev_priv)) |
3075 | DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); |
3028 | DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); |
3076 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
3029 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
3077 | DRM_ERROR("LCPLL1 is disabled\n"); |
3030 | DRM_ERROR("LCPLL1 is disabled\n"); |
3078 | } else if (IS_BROXTON(dev)) { |
3031 | } else if (IS_BROXTON(dev)) { |
3079 | broxton_init_cdclk(dev); |
3032 | broxton_init_cdclk(dev); |
3080 | broxton_ddi_phy_init(dev); |
3033 | broxton_ddi_phy_init(dev); |
3081 | } else { |
3034 | } else { |
3082 | /* |
3035 | /* |
3083 | * The LCPLL register should be turned on by the BIOS. For now |
3036 | * The LCPLL register should be turned on by the BIOS. For now |
3084 | * let's just check its state and print errors in case |
3037 | * let's just check its state and print errors in case |
3085 | * something is wrong. Don't even try to turn it on. |
3038 | * something is wrong. Don't even try to turn it on. |
3086 | */ |
3039 | */ |
3087 | 3040 | ||
3088 | if (val & LCPLL_CD_SOURCE_FCLK) |
3041 | if (val & LCPLL_CD_SOURCE_FCLK) |
3089 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
3042 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
3090 | 3043 | ||
3091 | if (val & LCPLL_PLL_DISABLE) |
3044 | if (val & LCPLL_PLL_DISABLE) |
3092 | DRM_ERROR("LCPLL is disabled\n"); |
3045 | DRM_ERROR("LCPLL is disabled\n"); |
3093 | } |
3046 | } |
3094 | } |
3047 | } |
3095 | 3048 | ||
3096 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
3049 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
3097 | { |
3050 | { |
3098 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3051 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3099 | struct drm_i915_private *dev_priv = |
3052 | struct drm_i915_private *dev_priv = |
3100 | to_i915(intel_dig_port->base.base.dev); |
3053 | to_i915(intel_dig_port->base.base.dev); |
3101 | enum port port = intel_dig_port->port; |
3054 | enum port port = intel_dig_port->port; |
3102 | uint32_t val; |
3055 | uint32_t val; |
3103 | bool wait = false; |
3056 | bool wait = false; |
3104 | 3057 | ||
3105 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { |
3058 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { |
3106 | val = I915_READ(DDI_BUF_CTL(port)); |
3059 | val = I915_READ(DDI_BUF_CTL(port)); |
3107 | if (val & DDI_BUF_CTL_ENABLE) { |
3060 | if (val & DDI_BUF_CTL_ENABLE) { |
3108 | val &= ~DDI_BUF_CTL_ENABLE; |
3061 | val &= ~DDI_BUF_CTL_ENABLE; |
3109 | I915_WRITE(DDI_BUF_CTL(port), val); |
3062 | I915_WRITE(DDI_BUF_CTL(port), val); |
3110 | wait = true; |
3063 | wait = true; |
3111 | } |
3064 | } |
3112 | 3065 | ||
3113 | val = I915_READ(DP_TP_CTL(port)); |
3066 | val = I915_READ(DP_TP_CTL(port)); |
3114 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
3067 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
3115 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
3068 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
3116 | I915_WRITE(DP_TP_CTL(port), val); |
3069 | I915_WRITE(DP_TP_CTL(port), val); |
3117 | POSTING_READ(DP_TP_CTL(port)); |
3070 | POSTING_READ(DP_TP_CTL(port)); |
3118 | 3071 | ||
3119 | if (wait) |
3072 | if (wait) |
3120 | intel_wait_ddi_buf_idle(dev_priv, port); |
3073 | intel_wait_ddi_buf_idle(dev_priv, port); |
3121 | } |
3074 | } |
3122 | 3075 | ||
3123 | val = DP_TP_CTL_ENABLE | |
3076 | val = DP_TP_CTL_ENABLE | |
3124 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
3077 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
3125 | if (intel_dp->is_mst) |
3078 | if (intel_dp->is_mst) |
3126 | val |= DP_TP_CTL_MODE_MST; |
3079 | val |= DP_TP_CTL_MODE_MST; |
3127 | else { |
3080 | else { |
3128 | val |= DP_TP_CTL_MODE_SST; |
3081 | val |= DP_TP_CTL_MODE_SST; |
3129 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3082 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3130 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
3083 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
3131 | } |
3084 | } |
3132 | I915_WRITE(DP_TP_CTL(port), val); |
3085 | I915_WRITE(DP_TP_CTL(port), val); |
3133 | POSTING_READ(DP_TP_CTL(port)); |
3086 | POSTING_READ(DP_TP_CTL(port)); |
3134 | 3087 | ||
3135 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; |
3088 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; |
3136 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); |
3089 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); |
3137 | POSTING_READ(DDI_BUF_CTL(port)); |
3090 | POSTING_READ(DDI_BUF_CTL(port)); |
3138 | 3091 | ||
3139 | udelay(600); |
3092 | udelay(600); |
3140 | } |
3093 | } |
3141 | 3094 | ||
3142 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
3095 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
3143 | { |
3096 | { |
3144 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
3097 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
3145 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
3098 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
3146 | uint32_t val; |
3099 | uint32_t val; |
3147 | 3100 | ||
3148 | intel_ddi_post_disable(intel_encoder); |
3101 | intel_ddi_post_disable(intel_encoder); |
3149 | 3102 | ||
3150 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3103 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3151 | val &= ~FDI_RX_ENABLE; |
3104 | val &= ~FDI_RX_ENABLE; |
3152 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3105 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3153 | 3106 | ||
3154 | val = I915_READ(FDI_RX_MISC(PIPE_A)); |
3107 | val = I915_READ(FDI_RX_MISC(PIPE_A)); |
3155 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
3108 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
3156 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
3109 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
3157 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); |
3110 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); |
3158 | 3111 | ||
3159 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3112 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3160 | val &= ~FDI_PCDCLK; |
3113 | val &= ~FDI_PCDCLK; |
3161 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3114 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3162 | 3115 | ||
3163 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3116 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
3164 | val &= ~FDI_RX_PLL_ENABLE; |
3117 | val &= ~FDI_RX_PLL_ENABLE; |
3165 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3118 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
3166 | } |
3119 | } |
3167 | 3120 | ||
3168 | void intel_ddi_get_config(struct intel_encoder *encoder, |
3121 | void intel_ddi_get_config(struct intel_encoder *encoder, |
3169 | struct intel_crtc_state *pipe_config) |
3122 | struct intel_crtc_state *pipe_config) |
3170 | { |
3123 | { |
3171 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
3124 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
3172 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
3125 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
3173 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
3126 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
3174 | struct intel_hdmi *intel_hdmi; |
3127 | struct intel_hdmi *intel_hdmi; |
3175 | u32 temp, flags = 0; |
3128 | u32 temp, flags = 0; |
3176 | 3129 | ||
3177 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
3130 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
3178 | if (temp & TRANS_DDI_PHSYNC) |
3131 | if (temp & TRANS_DDI_PHSYNC) |
3179 | flags |= DRM_MODE_FLAG_PHSYNC; |
3132 | flags |= DRM_MODE_FLAG_PHSYNC; |
3180 | else |
3133 | else |
3181 | flags |= DRM_MODE_FLAG_NHSYNC; |
3134 | flags |= DRM_MODE_FLAG_NHSYNC; |
3182 | if (temp & TRANS_DDI_PVSYNC) |
3135 | if (temp & TRANS_DDI_PVSYNC) |
3183 | flags |= DRM_MODE_FLAG_PVSYNC; |
3136 | flags |= DRM_MODE_FLAG_PVSYNC; |
3184 | else |
3137 | else |
3185 | flags |= DRM_MODE_FLAG_NVSYNC; |
3138 | flags |= DRM_MODE_FLAG_NVSYNC; |
3186 | 3139 | ||
3187 | pipe_config->base.adjusted_mode.flags |= flags; |
3140 | pipe_config->base.adjusted_mode.flags |= flags; |
3188 | 3141 | ||
3189 | switch (temp & TRANS_DDI_BPC_MASK) { |
3142 | switch (temp & TRANS_DDI_BPC_MASK) { |
3190 | case TRANS_DDI_BPC_6: |
3143 | case TRANS_DDI_BPC_6: |
3191 | pipe_config->pipe_bpp = 18; |
3144 | pipe_config->pipe_bpp = 18; |
3192 | break; |
3145 | break; |
3193 | case TRANS_DDI_BPC_8: |
3146 | case TRANS_DDI_BPC_8: |
3194 | pipe_config->pipe_bpp = 24; |
3147 | pipe_config->pipe_bpp = 24; |
3195 | break; |
3148 | break; |
3196 | case TRANS_DDI_BPC_10: |
3149 | case TRANS_DDI_BPC_10: |
3197 | pipe_config->pipe_bpp = 30; |
3150 | pipe_config->pipe_bpp = 30; |
3198 | break; |
3151 | break; |
3199 | case TRANS_DDI_BPC_12: |
3152 | case TRANS_DDI_BPC_12: |
3200 | pipe_config->pipe_bpp = 36; |
3153 | pipe_config->pipe_bpp = 36; |
3201 | break; |
3154 | break; |
3202 | default: |
3155 | default: |
3203 | break; |
3156 | break; |
3204 | } |
3157 | } |
3205 | 3158 | ||
3206 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { |
3159 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { |
3207 | case TRANS_DDI_MODE_SELECT_HDMI: |
3160 | case TRANS_DDI_MODE_SELECT_HDMI: |
3208 | pipe_config->has_hdmi_sink = true; |
3161 | pipe_config->has_hdmi_sink = true; |
3209 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
3162 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
3210 | 3163 | ||
3211 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
3164 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
3212 | pipe_config->has_infoframe = true; |
3165 | pipe_config->has_infoframe = true; |
3213 | break; |
3166 | break; |
3214 | case TRANS_DDI_MODE_SELECT_DVI: |
3167 | case TRANS_DDI_MODE_SELECT_DVI: |
3215 | case TRANS_DDI_MODE_SELECT_FDI: |
3168 | case TRANS_DDI_MODE_SELECT_FDI: |
3216 | break; |
3169 | break; |
3217 | case TRANS_DDI_MODE_SELECT_DP_SST: |
3170 | case TRANS_DDI_MODE_SELECT_DP_SST: |
3218 | case TRANS_DDI_MODE_SELECT_DP_MST: |
3171 | case TRANS_DDI_MODE_SELECT_DP_MST: |
3219 | pipe_config->has_dp_encoder = true; |
3172 | pipe_config->has_dp_encoder = true; |
3220 | pipe_config->lane_count = |
3173 | pipe_config->lane_count = |
3221 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; |
3174 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; |
3222 | intel_dp_get_m_n(intel_crtc, pipe_config); |
3175 | intel_dp_get_m_n(intel_crtc, pipe_config); |
3223 | break; |
3176 | break; |
3224 | default: |
3177 | default: |
3225 | break; |
3178 | break; |
3226 | } |
3179 | } |
3227 | 3180 | ||
3228 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
3181 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
3229 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
3182 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
3230 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
3183 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
3231 | pipe_config->has_audio = true; |
3184 | pipe_config->has_audio = true; |
3232 | } |
3185 | } |
3233 | 3186 | ||
3234 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
3187 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
3235 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
3188 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
3236 | /* |
3189 | /* |
3237 | * This is a big fat ugly hack. |
3190 | * This is a big fat ugly hack. |
3238 | * |
3191 | * |
3239 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
3192 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
3240 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
3193 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
3241 | * unknown we fail to light up. Yet the same BIOS boots up with |
3194 | * unknown we fail to light up. Yet the same BIOS boots up with |
3242 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
3195 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
3243 | * max, not what it tells us to use. |
3196 | * max, not what it tells us to use. |
3244 | * |
3197 | * |
3245 | * Note: This will still be broken if the eDP panel is not lit |
3198 | * Note: This will still be broken if the eDP panel is not lit |
3246 | * up by the BIOS, and thus we can't get the mode at module |
3199 | * up by the BIOS, and thus we can't get the mode at module |
3247 | * load. |
3200 | * load. |
3248 | */ |
3201 | */ |
3249 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
3202 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
3250 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
3203 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
3251 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
3204 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
3252 | } |
3205 | } |
3253 | 3206 | ||
3254 | intel_ddi_clock_get(encoder, pipe_config); |
3207 | intel_ddi_clock_get(encoder, pipe_config); |
3255 | } |
3208 | } |
3256 | 3209 | ||
3257 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
3210 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
3258 | struct intel_crtc_state *pipe_config) |
3211 | struct intel_crtc_state *pipe_config) |
3259 | { |
3212 | { |
3260 | int type = encoder->type; |
3213 | int type = encoder->type; |
3261 | int port = intel_ddi_get_encoder_port(encoder); |
3214 | int port = intel_ddi_get_encoder_port(encoder); |
3262 | 3215 | ||
3263 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
3216 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
3264 | 3217 | ||
3265 | if (port == PORT_A) |
3218 | if (port == PORT_A) |
3266 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
3219 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
3267 | 3220 | ||
3268 | if (type == INTEL_OUTPUT_HDMI) |
3221 | if (type == INTEL_OUTPUT_HDMI) |
3269 | return intel_hdmi_compute_config(encoder, pipe_config); |
3222 | return intel_hdmi_compute_config(encoder, pipe_config); |
3270 | else |
3223 | else |
3271 | return intel_dp_compute_config(encoder, pipe_config); |
3224 | return intel_dp_compute_config(encoder, pipe_config); |
3272 | } |
3225 | } |
3273 | 3226 | ||
3274 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
3227 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
3275 | .reset = intel_dp_encoder_reset, |
3228 | .reset = intel_dp_encoder_reset, |
3276 | .destroy = intel_dp_encoder_destroy, |
3229 | .destroy = intel_dp_encoder_destroy, |
3277 | }; |
3230 | }; |
3278 | 3231 | ||
3279 | static struct intel_connector * |
3232 | static struct intel_connector * |
3280 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) |
3233 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) |
3281 | { |
3234 | { |
3282 | struct intel_connector *connector; |
3235 | struct intel_connector *connector; |
3283 | enum port port = intel_dig_port->port; |
3236 | enum port port = intel_dig_port->port; |
3284 | 3237 | ||
3285 | connector = intel_connector_alloc(); |
3238 | connector = intel_connector_alloc(); |
3286 | if (!connector) |
3239 | if (!connector) |
3287 | return NULL; |
3240 | return NULL; |
3288 | 3241 | ||
3289 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
3242 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
3290 | if (!intel_dp_init_connector(intel_dig_port, connector)) { |
3243 | if (!intel_dp_init_connector(intel_dig_port, connector)) { |
3291 | kfree(connector); |
3244 | kfree(connector); |
3292 | return NULL; |
3245 | return NULL; |
3293 | } |
3246 | } |
3294 | 3247 | ||
3295 | return connector; |
3248 | return connector; |
3296 | } |
3249 | } |
3297 | 3250 | ||
3298 | static struct intel_connector * |
3251 | static struct intel_connector * |
3299 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) |
3252 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) |
3300 | { |
3253 | { |
3301 | struct intel_connector *connector; |
3254 | struct intel_connector *connector; |
3302 | enum port port = intel_dig_port->port; |
3255 | enum port port = intel_dig_port->port; |
3303 | 3256 | ||
3304 | connector = intel_connector_alloc(); |
3257 | connector = intel_connector_alloc(); |
3305 | if (!connector) |
3258 | if (!connector) |
3306 | return NULL; |
3259 | return NULL; |
3307 | 3260 | ||
3308 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
3261 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
3309 | intel_hdmi_init_connector(intel_dig_port, connector); |
3262 | intel_hdmi_init_connector(intel_dig_port, connector); |
3310 | 3263 | ||
3311 | return connector; |
3264 | return connector; |
3312 | } |
3265 | } |
3313 | 3266 | ||
3314 | void intel_ddi_init(struct drm_device *dev, enum port port) |
3267 | void intel_ddi_init(struct drm_device *dev, enum port port) |
3315 | { |
3268 | { |
3316 | struct drm_i915_private *dev_priv = dev->dev_private; |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; |
3317 | struct intel_digital_port *intel_dig_port; |
3270 | struct intel_digital_port *intel_dig_port; |
3318 | struct intel_encoder *intel_encoder; |
3271 | struct intel_encoder *intel_encoder; |
3319 | struct drm_encoder *encoder; |
3272 | struct drm_encoder *encoder; |
3320 | bool init_hdmi, init_dp; |
3273 | bool init_hdmi, init_dp; |
- | 3274 | int max_lanes; |
|
- | 3275 | ||
- | 3276 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { |
|
- | 3277 | switch (port) { |
|
- | 3278 | case PORT_A: |
|
- | 3279 | max_lanes = 4; |
|
- | 3280 | break; |
|
- | 3281 | case PORT_E: |
|
- | 3282 | max_lanes = 0; |
|
- | 3283 | break; |
|
- | 3284 | default: |
|
- | 3285 | max_lanes = 4; |
|
- | 3286 | break; |
|
- | 3287 | } |
|
- | 3288 | } else { |
|
- | 3289 | switch (port) { |
|
- | 3290 | case PORT_A: |
|
- | 3291 | max_lanes = 2; |
|
- | 3292 | break; |
|
- | 3293 | case PORT_E: |
|
- | 3294 | max_lanes = 2; |
|
- | 3295 | break; |
|
- | 3296 | default: |
|
- | 3297 | max_lanes = 4; |
|
- | 3298 | break; |
|
- | 3299 | } |
|
- | 3300 | } |
|
3321 | 3301 | ||
3322 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
3302 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
3323 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
3303 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
3324 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
3304 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
3325 | if (!init_dp && !init_hdmi) { |
3305 | if (!init_dp && !init_hdmi) { |
3326 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
3306 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
3327 | port_name(port)); |
3307 | port_name(port)); |
3328 | return; |
3308 | return; |
3329 | } |
3309 | } |
3330 | 3310 | ||
3331 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3311 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3332 | if (!intel_dig_port) |
3312 | if (!intel_dig_port) |
3333 | return; |
3313 | return; |
3334 | 3314 | ||
3335 | intel_encoder = &intel_dig_port->base; |
3315 | intel_encoder = &intel_dig_port->base; |
3336 | encoder = &intel_encoder->base; |
3316 | encoder = &intel_encoder->base; |
3337 | 3317 | ||
3338 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
3318 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
3339 | DRM_MODE_ENCODER_TMDS, NULL); |
3319 | DRM_MODE_ENCODER_TMDS, NULL); |
3340 | 3320 | ||
3341 | intel_encoder->compute_config = intel_ddi_compute_config; |
3321 | intel_encoder->compute_config = intel_ddi_compute_config; |
3342 | intel_encoder->enable = intel_enable_ddi; |
3322 | intel_encoder->enable = intel_enable_ddi; |
3343 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
3323 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
3344 | intel_encoder->disable = intel_disable_ddi; |
3324 | intel_encoder->disable = intel_disable_ddi; |
3345 | intel_encoder->post_disable = intel_ddi_post_disable; |
3325 | intel_encoder->post_disable = intel_ddi_post_disable; |
3346 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
3326 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
3347 | intel_encoder->get_config = intel_ddi_get_config; |
3327 | intel_encoder->get_config = intel_ddi_get_config; |
3348 | intel_encoder->suspend = intel_dp_encoder_suspend; |
3328 | intel_encoder->suspend = intel_dp_encoder_suspend; |
3349 | 3329 | ||
3350 | intel_dig_port->port = port; |
3330 | intel_dig_port->port = port; |
3351 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
3331 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
3352 | (DDI_BUF_PORT_REVERSAL | |
3332 | (DDI_BUF_PORT_REVERSAL | |
3353 | DDI_A_4_LANES); |
3333 | DDI_A_4_LANES); |
3354 | 3334 | ||
3355 | /* |
3335 | /* |
3356 | * Bspec says that DDI_A_4_LANES is the only supported configuration |
3336 | * Bspec says that DDI_A_4_LANES is the only supported configuration |
3357 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP |
3337 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP |
3358 | * wasn't lit up at boot. Force this bit on in our internal |
3338 | * wasn't lit up at boot. Force this bit on in our internal |
3359 | * configuration so that we use the proper lane count for our |
3339 | * configuration so that we use the proper lane count for our |
3360 | * calculations. |
3340 | * calculations. |
3361 | */ |
3341 | */ |
3362 | if (IS_BROXTON(dev) && port == PORT_A) { |
3342 | if (IS_BROXTON(dev) && port == PORT_A) { |
3363 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
3343 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
3364 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
3344 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
3365 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
3345 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
- | 3346 | max_lanes = 4; |
|
3366 | } |
3347 | } |
3367 | } |
3348 | } |
- | 3349 | ||
- | 3350 | intel_dig_port->max_lanes = max_lanes; |
|
3368 | 3351 | ||
3369 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
3352 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
3370 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3353 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3371 | intel_encoder->cloneable = 0; |
3354 | intel_encoder->cloneable = 0; |
3372 | 3355 | ||
3373 | if (init_dp) { |
3356 | if (init_dp) { |
3374 | if (!intel_ddi_init_dp_connector(intel_dig_port)) |
3357 | if (!intel_ddi_init_dp_connector(intel_dig_port)) |
3375 | goto err; |
3358 | goto err; |
3376 | 3359 | ||
3377 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
3360 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
3378 | /* |
3361 | /* |
3379 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
3362 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
3380 | * interrupts to check the external panel connection. |
3363 | * interrupts to check the external panel connection. |
3381 | */ |
3364 | */ |
3382 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) |
3365 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) |
3383 | dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
3366 | dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
3384 | else |
3367 | else |
3385 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
3368 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
3386 | } |
3369 | } |
3387 | 3370 | ||
3388 | /* In theory we don't need the encoder->type check, but leave it just in |
3371 | /* In theory we don't need the encoder->type check, but leave it just in |
3389 | * case we have some really bad VBTs... */ |
3372 | * case we have some really bad VBTs... */ |
3390 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
3373 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
3391 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) |
3374 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) |
3392 | goto err; |
3375 | goto err; |
3393 | } |
3376 | } |
3394 | 3377 | ||
3395 | return; |
3378 | return; |
3396 | 3379 | ||
3397 | err: |
3380 | err: |
3398 | drm_encoder_cleanup(encoder); |
3381 | drm_encoder_cleanup(encoder); |
3399 | kfree(intel_dig_port); |
3382 | kfree(intel_dig_port); |
3400 | }><>><>><>>><>><>><>><>>=>>><>>>>>><>><>><>><>>><>><>><>=>><>><>>>=>>><>>>>>>>>><>=>=>>>>=>=>=>>>>=>=>=>><>>>>>>=>><>>>>31; |
3383 | }><>><>><>>><>><>><>><>>=>>><>>>>>><>><>><>><>>><>><>><>=>><>><>>>=>>><>>>>>>>>><>=>=>>>>=>=>=>>>>=>=>=>><>>>>>>=>><>>>>31; |
3401 | ><31; |
3384 | |
3402 | > |
3385 | ><31; |
- | 3386 | ||
- | 3387 | > |