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Rev 3480 | Rev 3746 | ||
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Line 896... | Line 896... | ||
896 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", |
896 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", |
897 | pipe_name(pipe)); |
897 | pipe_name(pipe)); |
898 | plls->spll_refcount++; |
898 | plls->spll_refcount++; |
899 | reg = SPLL_CTL; |
899 | reg = SPLL_CTL; |
900 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
900 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
- | 901 | } else { |
|
- | 902 | DRM_ERROR("SPLL already in use\n"); |
|
- | 903 | return false; |
|
901 | } |
904 | } |
Line 902... | Line 905... | ||
902 | 905 | ||
903 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, |
906 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, |
Line 919... | Line 922... | ||
919 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
922 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
920 | { |
923 | { |
921 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
924 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
925 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
923 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
926 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
924 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
927 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
925 | int type = intel_encoder->type; |
928 | int type = intel_encoder->type; |
926 | uint32_t temp; |
929 | uint32_t temp; |
Line 927... | Line 930... | ||
927 | 930 | ||
Line 928... | Line 931... | ||
928 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
931 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
929 | 932 | ||
930 | temp = TRANS_MSA_SYNC_CLK; |
933 | temp = TRANS_MSA_SYNC_CLK; |
931 | switch (intel_crtc->bpp) { |
934 | switch (intel_crtc->config.pipe_bpp) { |
932 | case 18: |
935 | case 18: |
933 | temp |= TRANS_MSA_6_BPC; |
936 | temp |= TRANS_MSA_6_BPC; |
934 | break; |
937 | break; |
Line 940... | Line 943... | ||
940 | break; |
943 | break; |
941 | case 36: |
944 | case 36: |
942 | temp |= TRANS_MSA_12_BPC; |
945 | temp |= TRANS_MSA_12_BPC; |
943 | break; |
946 | break; |
944 | default: |
947 | default: |
945 | temp |= TRANS_MSA_8_BPC; |
- | |
946 | WARN(1, "%d bpp unsupported by DDI function\n", |
- | |
947 | intel_crtc->bpp); |
948 | BUG(); |
948 | } |
949 | } |
949 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
950 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
950 | } |
951 | } |
951 | } |
952 | } |
Line 952... | Line 953... | ||
952 | 953 | ||
953 | void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) |
954 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
954 | { |
955 | { |
955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
956 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
957 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
957 | struct drm_encoder *encoder = &intel_encoder->base; |
958 | struct drm_encoder *encoder = &intel_encoder->base; |
958 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
959 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
959 | enum pipe pipe = intel_crtc->pipe; |
960 | enum pipe pipe = intel_crtc->pipe; |
960 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
961 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
961 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
962 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
962 | int type = intel_encoder->type; |
963 | int type = intel_encoder->type; |
Line 963... | Line 964... | ||
963 | uint32_t temp; |
964 | uint32_t temp; |
964 | 965 | ||
965 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
966 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
Line 966... | Line 967... | ||
966 | temp = TRANS_DDI_FUNC_ENABLE; |
967 | temp = TRANS_DDI_FUNC_ENABLE; |
967 | temp |= TRANS_DDI_SELECT_PORT(port); |
968 | temp |= TRANS_DDI_SELECT_PORT(port); |
968 | 969 | ||
969 | switch (intel_crtc->bpp) { |
970 | switch (intel_crtc->config.pipe_bpp) { |
970 | case 18: |
971 | case 18: |
971 | temp |= TRANS_DDI_BPC_6; |
972 | temp |= TRANS_DDI_BPC_6; |
Line 978... | Line 979... | ||
978 | break; |
979 | break; |
979 | case 36: |
980 | case 36: |
980 | temp |= TRANS_DDI_BPC_12; |
981 | temp |= TRANS_DDI_BPC_12; |
981 | break; |
982 | break; |
982 | default: |
983 | default: |
983 | WARN(1, "%d bpp unsupported by transcoder DDI function\n", |
- | |
984 | intel_crtc->bpp); |
984 | BUG(); |
985 | } |
985 | } |
Line 986... | Line 986... | ||
986 | 986 | ||
987 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
987 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
988 | temp |= TRANS_DDI_PVSYNC; |
988 | temp |= TRANS_DDI_PVSYNC; |
Line 1148... | Line 1148... | ||
1148 | } |
1148 | } |
1149 | } |
1149 | } |
Line 1150... | Line 1150... | ||
1150 | 1150 | ||
Line 1151... | Line 1151... | ||
1151 | DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); |
1151 | DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); |
1152 | 1152 | ||
Line 1153... | Line 1153... | ||
1153 | return true; |
1153 | return false; |
1154 | } |
1154 | } |
1155 | 1155 | ||
1156 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1156 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe) |
1157 | enum pipe pipe) |
1158 | { |
1158 | { |
1159 | uint32_t temp, ret; |
1159 | uint32_t temp, ret; |
1160 | enum port port; |
1160 | enum port port = I915_MAX_PORTS; |
Line 1161... | Line 1161... | ||
1161 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1161 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
Line 1171... | Line 1171... | ||
1171 | for (i = PORT_B; i <= PORT_E; i++) |
1171 | for (i = PORT_B; i <= PORT_E; i++) |
1172 | if (temp == TRANS_DDI_SELECT_PORT(i)) |
1172 | if (temp == TRANS_DDI_SELECT_PORT(i)) |
1173 | port = i; |
1173 | port = i; |
1174 | } |
1174 | } |
Line -... | Line 1175... | ||
- | 1175 | ||
- | 1176 | if (port == I915_MAX_PORTS) { |
|
- | 1177 | WARN(1, "Pipe %c enabled on an unknown port\n", |
|
- | 1178 | pipe_name(pipe)); |
|
- | 1179 | ret = PORT_CLK_SEL_NONE; |
|
1175 | 1180 | } else { |
|
1176 | ret = I915_READ(PORT_CLK_SEL(port)); |
- | |
1177 | 1181 | ret = I915_READ(PORT_CLK_SEL(port)); |
|
1178 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", |
1182 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " |
- | 1183 | "0x%08x\n", pipe_name(pipe), port_name(port), |
|
- | 1184 | ret); |
|
Line 1179... | Line 1185... | ||
1179 | pipe_name(pipe), port_name(port), ret); |
1185 | } |
1180 | 1186 | ||
Line 1181... | Line 1187... | ||
1181 | return ret; |
1187 | return ret; |
Line 1215... | Line 1221... | ||
1215 | { |
1221 | { |
1216 | struct drm_crtc *crtc = &intel_crtc->base; |
1222 | struct drm_crtc *crtc = &intel_crtc->base; |
1217 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
1223 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
1218 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1224 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1219 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1225 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1220 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1226 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Line 1221... | Line 1227... | ||
1221 | 1227 | ||
1222 | if (cpu_transcoder != TRANSCODER_EDP) |
1228 | if (cpu_transcoder != TRANSCODER_EDP) |
1223 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
1229 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
1224 | TRANS_CLK_SEL_PORT(port)); |
1230 | TRANS_CLK_SEL_PORT(port)); |
Line 1225... | Line 1231... | ||
1225 | } |
1231 | } |
1226 | 1232 | ||
1227 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
1233 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
1228 | { |
1234 | { |
Line 1229... | Line 1235... | ||
1229 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1235 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1230 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1236 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1231 | 1237 | ||
1232 | if (cpu_transcoder != TRANSCODER_EDP) |
1238 | if (cpu_transcoder != TRANSCODER_EDP) |
Line 1257... | Line 1263... | ||
1257 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1263 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Line 1258... | Line 1264... | ||
1258 | 1264 | ||
1259 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1265 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1260 | intel_dp_start_link_train(intel_dp); |
1266 | intel_dp_start_link_train(intel_dp); |
- | 1267 | intel_dp_complete_link_train(intel_dp); |
|
- | 1268 | if (port != PORT_A) |
|
1261 | intel_dp_complete_link_train(intel_dp); |
1269 | intel_dp_stop_link_train(intel_dp); |
1262 | } |
1270 | } |
Line 1263... | Line 1271... | ||
1263 | } |
1271 | } |
1264 | 1272 | ||
Line 1318... | Line 1326... | ||
1318 | I915_WRITE(DDI_BUF_CTL(port), |
1326 | I915_WRITE(DDI_BUF_CTL(port), |
1319 | intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE); |
1327 | intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE); |
1320 | } else if (type == INTEL_OUTPUT_EDP) { |
1328 | } else if (type == INTEL_OUTPUT_EDP) { |
1321 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1329 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Line -... | Line 1330... | ||
- | 1330 | ||
- | 1331 | if (port == PORT_A) |
|
- | 1332 | intel_dp_stop_link_train(intel_dp); |
|
1322 | 1333 | ||
1323 | ironlake_edp_backlight_on(intel_dp); |
1334 | ironlake_edp_backlight_on(intel_dp); |
Line 1324... | Line 1335... | ||
1324 | } |
1335 | } |
1325 | 1336 | ||
Line 1339... | Line 1350... | ||
1339 | int type = intel_encoder->type; |
1350 | int type = intel_encoder->type; |
1340 | struct drm_device *dev = encoder->dev; |
1351 | struct drm_device *dev = encoder->dev; |
1341 | struct drm_i915_private *dev_priv = dev->dev_private; |
1352 | struct drm_i915_private *dev_priv = dev->dev_private; |
1342 | uint32_t tmp; |
1353 | uint32_t tmp; |
Line -... | Line 1354... | ||
- | 1354 | ||
- | 1355 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
|
- | 1356 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); |
|
- | 1357 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
|
1343 | 1358 | ||
1344 | if (type == INTEL_OUTPUT_EDP) { |
1359 | if (type == INTEL_OUTPUT_EDP) { |
Line 1345... | Line 1360... | ||
1345 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1360 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1346 | 1361 | ||
1347 | ironlake_edp_backlight_off(intel_dp); |
- | |
1348 | } |
- | |
1349 | - | ||
1350 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
- | |
1351 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); |
1362 | ironlake_edp_backlight_off(intel_dp); |
Line 1352... | Line 1363... | ||
1352 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
1363 | } |
1353 | } |
1364 | } |
1354 | 1365 | ||
Line 1465... | Line 1476... | ||
1465 | { |
1476 | { |
1466 | /* HDMI has nothing special to destroy, so we can go with this. */ |
1477 | /* HDMI has nothing special to destroy, so we can go with this. */ |
1467 | intel_dp_encoder_destroy(encoder); |
1478 | intel_dp_encoder_destroy(encoder); |
1468 | } |
1479 | } |
Line 1469... | Line 1480... | ||
1469 | 1480 | ||
1470 | static bool intel_ddi_mode_fixup(struct drm_encoder *encoder, |
- | |
1471 | const struct drm_display_mode *mode, |
1481 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1472 | struct drm_display_mode *adjusted_mode) |
1482 | struct intel_crtc_config *pipe_config) |
1473 | { |
- | |
1474 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
1483 | { |
Line 1475... | Line 1484... | ||
1475 | int type = intel_encoder->type; |
1484 | int type = encoder->type; |
Line 1476... | Line 1485... | ||
1476 | 1485 | ||
1477 | WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n"); |
1486 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
1478 | 1487 | ||
1479 | if (type == INTEL_OUTPUT_HDMI) |
1488 | if (type == INTEL_OUTPUT_HDMI) |
1480 | return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode); |
1489 | return intel_hdmi_compute_config(encoder, pipe_config); |
Line 1481... | Line 1490... | ||
1481 | else |
1490 | else |
1482 | return intel_dp_mode_fixup(encoder, mode, adjusted_mode); |
1491 | return intel_dp_compute_config(encoder, pipe_config); |
1483 | } |
1492 | } |
Line 1484... | Line 1493... | ||
1484 | 1493 | ||
1485 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
- | |
1486 | .destroy = intel_ddi_destroy, |
1494 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
1487 | }; |
1495 | .destroy = intel_ddi_destroy, |
Line 1488... | Line 1496... | ||
1488 | 1496 | }; |
|
1489 | static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { |
1497 | |
Line 1525... | Line 1533... | ||
1525 | 1533 | ||
1526 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
1534 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
1527 | DRM_MODE_ENCODER_TMDS); |
1535 | DRM_MODE_ENCODER_TMDS); |
Line -... | Line 1536... | ||
- | 1536 | drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); |
|
1528 | drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); |
1537 | |
1529 | 1538 | intel_encoder->compute_config = intel_ddi_compute_config; |
|
1530 | intel_encoder->enable = intel_enable_ddi; |
1539 | intel_encoder->enable = intel_enable_ddi; |
1531 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
1540 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
1532 | intel_encoder->disable = intel_disable_ddi; |
1541 | intel_encoder->disable = intel_disable_ddi; |
Line 1533... | Line 1542... | ||
1533 | intel_encoder->post_disable = intel_ddi_post_disable; |
1542 | intel_encoder->post_disable = intel_ddi_post_disable; |
1534 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
1543 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
1535 | 1544 | ||
1536 | intel_dig_port->port = port; |
1545 | intel_dig_port->port = port; |
1537 | intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & |
1546 | intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & |
1538 | DDI_BUF_PORT_REVERSAL; |
- | |
1539 | if (hdmi_connector) |
- | |
1540 | intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); |
1547 | DDI_BUF_PORT_REVERSAL; |
Line 1541... | Line 1548... | ||
1541 | else |
1548 | if (hdmi_connector) |
1542 | intel_dig_port->hdmi.sdvox_reg = 0; |
1549 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
1543 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
1550 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |